From d186d7dcc7d29e6ef12ca2c65cf68e733231a631 Mon Sep 17 00:00:00 2001 From: Lizhenrong <315894961@qq.com> Date: Mon, 6 Apr 2026 19:02:09 +0800 Subject: [PATCH] Initial commit --- .gitignore | 59 + FW/.mxproject | 72 + FW/Core/Inc/dma.h | 52 + FW/Core/Inc/dma2d.h | 50 + FW/Core/Inc/fdcan.h | 52 + FW/Core/Inc/fmc.h | 59 + FW/Core/Inc/gpio.h | 49 + FW/Core/Inc/iwdg.h | 50 + FW/Core/Inc/jpeg.h | 52 + FW/Core/Inc/jpeg_utils_conf.h | 56 + FW/Core/Inc/ltdc.h | 52 + FW/Core/Inc/main.h | 108 + FW/Core/Inc/quadspi.h | 54 + FW/Core/Inc/rtc.h | 50 + FW/Core/Inc/spi.h | 50 + FW/Core/Inc/stm32_assert.h | 53 + FW/Core/Inc/stm32h7xx_hal_conf.h | 515 + FW/Core/Inc/stm32h7xx_it.h | 79 + FW/Core/Inc/task.h | 18 + FW/Core/Inc/tim.h | 54 + FW/Core/Inc/usart.h | 57 + FW/Core/Src/dma.c | 57 + FW/Core/Src/dma2d.c | 59 + FW/Core/Src/fdcan.c | 149 + FW/Core/Src/fmc.c | 365 + FW/Core/Src/gpio.c | 172 + FW/Core/Src/iwdg.c | 55 + FW/Core/Src/jpeg.c | 85 + FW/Core/Src/ltdc.c | 360 + FW/Core/Src/main.c | 338 + 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mode 100644 MyCode/src/ProtoCrt.cpp create mode 100644 MyCode/src/ProtoCrt.h create mode 100644 MyCode/src/ProtoFecBus.cpp create mode 100644 MyCode/src/ProtoFecBus.h create mode 100644 MyCode/src/ProtoFecBusCRT.cpp create mode 100644 MyCode/src/ProtoFecBusCRT.h create mode 100644 MyCode/src/ProtoInnerCan.cpp create mode 100644 MyCode/src/ProtoInnerCan.h create mode 100644 MyCode/src/ProtoM2M.cpp create mode 100644 MyCode/src/ProtoM2M.h create mode 100644 MyCode/src/RemoteData.cpp create mode 100644 MyCode/src/RemoteData.h create mode 100644 MyCode/src/RtUserCode.cpp create mode 100644 MyCode/src/RtUserCode.h create mode 100644 MyCode/src/Runtime.cpp create mode 100644 MyCode/src/Runtime.h create mode 100644 MyCode/src/RuntimeData.cpp create mode 100644 MyCode/src/RuntimeData.h create mode 100644 MyCode/src/Storage.cpp create mode 100644 MyCode/src/Storage.h create mode 100644 MyCode/src/TDataTime.cpp create mode 100644 MyCode/src/TDateTime.h create mode 100644 MyCode/src/TimerTask.cpp create mode 100644 MyCode/src/TimerTask.h create mode 100644 MyCode/src/UartPrinter.cpp create mode 100644 MyCode/src/UartPrinter.h create mode 100644 MyCode/src/exRecord.cpp create mode 100644 MyCode/src/exRecord.h create mode 100644 MyCode/src/gType.h create mode 100644 MyCode/src/record.cpp create mode 100644 MyCode/src/record.h create mode 100644 MyCode/src/server.cpp create mode 100644 MyCode/src/server.h diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..047e0c8 --- /dev/null +++ b/.gitignore @@ -0,0 +1,59 @@ +# Keil uVision project files +*.uvproj +*.uvprojx +*.uvopt +*.uvoptx +*.mdklaunch + +# Build output +*.axf +*.crf +*.o +*.d +*.hex +*.bin +*.lst +*.map +*.htm +*.h51 +*.lnp +*.sct + +# Debug files +*.dbg* +*.ini + +# User files +*.plg +*.bak +*.log + +# IDE files +.vscode/ +.idea/ + +# System files +Thumbs.db +.DS_Store + +# Large files +sdram_map.xlsx + +# Middleware libraries +Middlewares/ +Utilities/ + +# USB files +USB_DEVICE/ +USB_HOST/ + +# MDK-ARM directory +MDK-ARM/ + +# STM32CubeMX files +*.ioc + +# Build directories +build/ +debug/ +release/ \ No newline at end of file diff --git a/FW/.mxproject b/FW/.mxproject new file mode 100644 index 0000000..1e42afe --- /dev/null +++ b/FW/.mxproject @@ -0,0 +1,72 @@ +[PreviousLibFiles] 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HAL_Driver\Src\stm32h7xx_ll_lpuart.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_bdma.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_usart.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_ltdc_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_rtc.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_spi.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_tim_ex.c;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_tim.c;Middlewares\Third_Party\FatFs\src\diskio.c;Middlewares\Third_Party\FatFs\src\ff.c;Middlewares\Third_Party\FatFs\src\ff_gen_drv.c;Middlewares\Third_Party\FatFs\src\option\syscall.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_core.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ctlreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_ioreq.c;Middlewares\ST\STM32_USB_Host_Library\Core\Src\usbh_pipes.c;Middlewares\ST\STM32_USB_Host_Library\Class\MSC\Src\usbh_msc.c;Middlewares\ST\STM32_USB_Host_Library\Class\MSC\Src\usbh_msc_bot.c;Middlewares\ST\STM32_USB_Host_Library\Class\MSC\Src\usbh_msc_scsi.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_system.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_exti.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hcd.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usb.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_rcc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bus.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rcc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_crs.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_utils.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_flash_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_gpio_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_hsem.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_dma_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dmamux.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_mdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_pwr_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_pwr.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_cortex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_def.h;Drivers\STM32H7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_i2c_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_exti.h;Drivers\STM32H7xx_HAL_Driver\Src\stm32h7xx_ll_exti.c;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_dma2d.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_fdcan.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_fmc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_sdram.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_iwdg.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_jpeg.h;Utilities\JPEG\jpeg_utils.h;Utilities\JPEG\jpeg_utils_conf_template.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_lpuart.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_bdma.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_usart.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_ltdc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_ltdc_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_qspi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_rtc.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_spi.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_hal_tim_ex.h;Drivers\STM32H7xx_HAL_Driver\Inc\stm32h7xx_ll_tim.h;Middlewares\Third_Party\FatFs\src\diskio.h;Middlewares\Third_Party\FatFs\src\ff.h;Middlewares\Third_Party\FatFs\src\ff_gen_drv.h;Middlewares\Third_Party\FatFs\src\integer.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_core.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_ctlreq.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_def.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_ioreq.h;Middlewares\ST\STM32_USB_Host_Library\Core\Inc\usbh_pipes.h;Middlewares\ST\STM32_USB_Host_Library\Class\MSC\Inc\usbh_msc.h;Middlewares\ST\STM32_USB_Host_Library\Class\MSC\Inc\usbh_msc_bot.h;Middlewares\ST\STM32_USB_Host_Library\Class\MSC\Inc\usbh_msc_scsi.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h;Drivers\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Dri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+ +[PreviousUsedKeilFiles] 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+HeaderPath=..\Drivers\STM32H7xx_HAL_Driver\Inc;..\Drivers\STM32H7xx_HAL_Driver\Inc\Legacy;..\Utilities\JPEG;..\Middlewares\Third_Party\FatFs\src;..\Middlewares\ST\STM32_USB_Host_Library\Core\Inc;..\Middlewares\ST\STM32_USB_Host_Library\Class\MSC\Inc;..\Drivers\CMSIS\Device\ST\STM32H7xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc;..\FATFS\Target;..\FATFS\App;..\USB_HOST\App;..\USB_HOST\Target; +CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32H743xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=24 +HeaderFiles#0=..\Core\Inc\gpio.h +HeaderFiles#1=..\Core\Inc\dma.h +HeaderFiles#2=..\Core\Inc\dma2d.h +HeaderFiles#3=..\FATFS\Target\ffconf.h +HeaderFiles#4=..\FATFS\Target\usbh_diskio.h +HeaderFiles#5=..\FATFS\App\fatfs.h +HeaderFiles#6=..\Core\Inc\fdcan.h +HeaderFiles#7=..\Core\Inc\fmc.h +HeaderFiles#8=..\Core\Inc\iwdg.h +HeaderFiles#9=..\Core\Inc\jpeg.h +HeaderFiles#10=..\Core\Inc\jpeg_utils_conf.h +HeaderFiles#11=..\Core\Inc\usart.h +HeaderFiles#12=..\Core\Inc\ltdc.h +HeaderFiles#13=..\Core\Inc\quadspi.h +HeaderFiles#14=..\Core\Inc\rtc.h +HeaderFiles#15=..\Core\Inc\spi.h +HeaderFiles#16=..\Core\Inc\tim.h +HeaderFiles#17=..\USB_HOST\App\usb_host.h +HeaderFiles#18=..\USB_HOST\Target\usbh_conf.h +HeaderFiles#19=..\USB_HOST\Target\usbh_platform.h +HeaderFiles#20=..\Core\Inc\stm32h7xx_it.h +HeaderFiles#21=..\Core\Inc\stm32_assert.h +HeaderFiles#22=..\Core\Inc\stm32h7xx_hal_conf.h +HeaderFiles#23=..\Core\Inc\main.h +HeaderFolderListSize=5 +HeaderPath#0=..\Core\Inc +HeaderPath#1=..\FATFS\Target +HeaderPath#2=..\FATFS\App +HeaderPath#3=..\USB_HOST\App +HeaderPath#4=..\USB_HOST\Target +HeaderFiles=; +SourceFileListSize=21 +SourceFiles#0=..\Core\Src\gpio.c +SourceFiles#1=..\Core\Src\dma.c +SourceFiles#2=..\Core\Src\dma2d.c +SourceFiles#3=..\FATFS\Target\usbh_diskio.c +SourceFiles#4=..\FATFS\App\fatfs.c +SourceFiles#5=..\Core\Src\fdcan.c +SourceFiles#6=..\Core\Src\fmc.c +SourceFiles#7=..\Core\Src\iwdg.c +SourceFiles#8=..\Core\Src\jpeg.c +SourceFiles#9=..\Core\Src\usart.c +SourceFiles#10=..\Core\Src\ltdc.c +SourceFiles#11=..\Core\Src\quadspi.c +SourceFiles#12=..\Core\Src\rtc.c +SourceFiles#13=..\Core\Src\spi.c +SourceFiles#14=..\Core\Src\tim.c +SourceFiles#15=..\USB_HOST\App\usb_host.c +SourceFiles#16=..\USB_HOST\Target\usbh_conf.c +SourceFiles#17=..\USB_HOST\Target\usbh_platform.c +SourceFiles#18=..\Core\Src\stm32h7xx_it.c +SourceFiles#19=..\Core\Src\stm32h7xx_hal_msp.c +SourceFiles#20=..\Core\Src\main.c +SourceFolderListSize=5 +SourcePath#0=..\Core\Src +SourcePath#1=..\FATFS\Target +SourcePath#2=..\FATFS\App +SourcePath#3=..\USB_HOST\App +SourcePath#4=..\USB_HOST\Target +SourceFiles=; + diff --git a/FW/Core/Inc/dma.h b/FW/Core/Inc/dma.h new file mode 100644 index 0000000..f3b1a09 --- /dev/null +++ b/FW/Core/Inc/dma.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/FW/Core/Inc/dma2d.h b/FW/Core/Inc/dma2d.h new file mode 100644 index 0000000..67d89fd --- /dev/null +++ b/FW/Core/Inc/dma2d.h @@ -0,0 +1,50 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma2d.h + * @brief This file contains all the function prototypes for + * the dma2d.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA2D_H__ +#define __DMA2D_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA2D_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA2D_H__ */ + diff --git a/FW/Core/Inc/fdcan.h b/FW/Core/Inc/fdcan.h new file mode 100644 index 0000000..9772001 --- /dev/null +++ b/FW/Core/Inc/fdcan.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file fdcan.h + * @brief This file contains all the function prototypes for + * the fdcan.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FDCAN_H__ +#define __FDCAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern FDCAN_HandleTypeDef hfdcan2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_FDCAN2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FDCAN_H__ */ + diff --git a/FW/Core/Inc/fmc.h b/FW/Core/Inc/fmc.h new file mode 100644 index 0000000..1c5e4a0 --- /dev/null +++ b/FW/Core/Inc/fmc.h @@ -0,0 +1,59 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : FMC.h + * Description : This file provides code for the configuration + * of the FMC peripheral. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FMC_H +#define __FMC_H +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern SDRAM_HandleTypeDef hsdram1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_FMC_Init(void); +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram); +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__FMC_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Core/Inc/gpio.h b/FW/Core/Inc/gpio.h new file mode 100644 index 0000000..6c03ac7 --- /dev/null +++ b/FW/Core/Inc/gpio.h @@ -0,0 +1,49 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + diff --git a/FW/Core/Inc/iwdg.h b/FW/Core/Inc/iwdg.h new file mode 100644 index 0000000..3def90d --- /dev/null +++ b/FW/Core/Inc/iwdg.h @@ -0,0 +1,50 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file iwdg.h + * @brief This file contains all the function prototypes for + * the iwdg.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __IWDG_H__ +#define __IWDG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_IWDG1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IWDG_H__ */ + diff --git a/FW/Core/Inc/jpeg.h b/FW/Core/Inc/jpeg.h new file mode 100644 index 0000000..154e23b --- /dev/null +++ b/FW/Core/Inc/jpeg.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file jpeg.h + * @brief This file contains all the function prototypes for + * the jpeg.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __JPEG_H__ +#define __JPEG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern JPEG_HandleTypeDef hjpeg; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_JPEG_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __JPEG_H__ */ + diff --git a/FW/Core/Inc/jpeg_utils_conf.h b/FW/Core/Inc/jpeg_utils_conf.h new file mode 100644 index 0000000..b1c148f --- /dev/null +++ b/FW/Core/Inc/jpeg_utils_conf.h @@ -0,0 +1,56 @@ +/* + * jpeg_utils_conf.h + * + * Copyright (C) 1991-1997, Thomas G. Lane. + * Modified 1997-2011 by Guido Vollbeding. + * This file is part of the Independent JPEG Group's software. + * For conditions of distribution and use, see the accompanying README file. + * + * This file contains additional configuration options that customize the + * JPEG HW configuration. Most users will not need to touch this file. + */ + + /* Define to prevent recursive inclusion -------------------------------------*/ + +#ifndef __JPEG_UTILS_CONF_H__ +#define __JPEG_UTILS_CONF_H__ + +/* Includes ------------------------------------------------------------------*/ + +#include "stm32h7xx_hal.h" +#include "stm32h7xx_hal_jpeg.h" + +/* Private define ------------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Defines + * @{ + */ +/* RGB Color format definition for JPEG encoding/Decoding : Should not be modified*/ +#define JPEG_ARGB8888 0 /* ARGB8888 Color Format */ +#define JPEG_RGB888 1 /* RGB888 Color Format */ +#define JPEG_RGB565 2 /* RGB565 Color Format */ + +/* + * Define USE_JPEG_DECODER + */ + +#define USE_JPEG_DECODER 1 /* 1 or 0 ********* Value different from default value : 1 ********** */ +/* + * Define USE_JPEG_ENCODER + */ + +#define USE_JPEG_ENCODER 1 /* 1 or 0 ********* Value different from default value : 1 ********** */ + +/* + * Define JPEG_RGB_FORMAT + */ +#define JPEG_RGB_FORMAT JPEG_ARGB8888 /* JPEG_ARGB8888, JPEG_RGB888, JPEG_RGB565 ********* Value different from default value : 0 ********** */ + +/* + * Define JPEG_SWAP_RG + */ +#define JPEG_SWAP_RG 0 /* 0 or 1 ********* Value different from default value : 0 ********** */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __JPEG_UTILS_CONF_H__ */ diff --git a/FW/Core/Inc/ltdc.h b/FW/Core/Inc/ltdc.h new file mode 100644 index 0000000..7ab190d --- /dev/null +++ b/FW/Core/Inc/ltdc.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ltdc.h + * @brief This file contains all the function prototypes for + * the ltdc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __LTDC_H__ +#define __LTDC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern LTDC_HandleTypeDef hltdc; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_LTDC_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LTDC_H__ */ + diff --git a/FW/Core/Inc/main.h b/FW/Core/Inc/main.h new file mode 100644 index 0000000..ba51fa1 --- /dev/null +++ b/FW/Core/Inc/main.h @@ -0,0 +1,108 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +#include "stm32h7xx_ll_crc.h" +#include "stm32h7xx_ll_dma.h" +#include "stm32h7xx_ll_dma2d.h" +#include "stm32h7xx_ll_iwdg.h" +#include "stm32h7xx_ll_lpuart.h" +#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_rtc.h" +#include "stm32h7xx_ll_spi.h" +#include "stm32h7xx_ll_tim.h" +#include "stm32h7xx_ll_usart.h" +#include "stm32h7xx_ll_system.h" +#include "stm32h7xx_ll_gpio.h" +#include "stm32h7xx_ll_exti.h" +#include "stm32h7xx_ll_bus.h" +#include "stm32h7xx_ll_cortex.h" +#include "stm32h7xx_ll_utils.h" +#include "stm32h7xx_ll_pwr.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ +#define FLASH_BASE_ADDR (uint32_t)(FLASH_BASE) +#define FLASH_END_ADDR (uint32_t)(0x081FFFFF) + +/* Base address of the Flash sectors Bank 1 */ +#define ADDR_FLASH_SECTOR_0_BANK1 ((uint32_t)0x08000000) /* Base @ of Sector 0, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_1_BANK1 ((uint32_t)0x08020000) /* Base @ of Sector 1, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_2_BANK1 ((uint32_t)0x08040000) /* Base @ of Sector 2, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_3_BANK1 ((uint32_t)0x08060000) /* Base @ of Sector 3, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_4_BANK1 ((uint32_t)0x08080000) /* Base @ of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5_BANK1 ((uint32_t)0x080A0000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6_BANK1 ((uint32_t)0x080C0000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7_BANK1 ((uint32_t)0x080E0000) /* Base @ of Sector 7, 128 Kbytes */ + +/* Base address of the Flash sectors Bank 2 */ +#define ADDR_FLASH_SECTOR_0_BANK2 ((uint32_t)0x08100000) /* Base @ of Sector 0, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_1_BANK2 ((uint32_t)0x08120000) /* Base @ of Sector 1, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_2_BANK2 ((uint32_t)0x08140000) /* Base @ of Sector 2, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_3_BANK2 ((uint32_t)0x08160000) /* Base @ of Sector 3, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_4_BANK2 ((uint32_t)0x08180000) /* Base @ of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5_BANK2 ((uint32_t)0x081A0000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6_BANK2 ((uint32_t)0x081C0000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7_BANK2 ((uint32_t)0x081E0000) /* Base @ of Sector 7, 128 Kbytes */ +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/FW/Core/Inc/quadspi.h b/FW/Core/Inc/quadspi.h new file mode 100644 index 0000000..e8a7ba7 --- /dev/null +++ b/FW/Core/Inc/quadspi.h @@ -0,0 +1,54 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file quadspi.h + * @brief This file contains all the function prototypes for + * the quadspi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __QUADSPI_H__ +#define __QUADSPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern QSPI_HandleTypeDef hqspi; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_QUADSPI_Init(void); + +/* USER CODE BEGIN Prototypes */ +void QSPI_Send_CMD(unsigned int instruction,unsigned int address,unsigned int dummyCycles,unsigned int instructionMode,unsigned int addressMode,unsigned int addressSize,unsigned int dataMode); +unsigned char QSPI_Receive(unsigned char* buf,unsigned int datalen); +unsigned char QSPI_Transmit(unsigned char* buf,unsigned int datalen); +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QUADSPI_H__ */ + diff --git a/FW/Core/Inc/rtc.h b/FW/Core/Inc/rtc.h new file mode 100644 index 0000000..74c90a2 --- /dev/null +++ b/FW/Core/Inc/rtc.h @@ -0,0 +1,50 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file rtc.h + * @brief This file contains all the function prototypes for + * the rtc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_RTC_Init(void); + +/* USER CODE BEGIN Prototypes */ +void RTC_DataTimeSet(unsigned char aY, unsigned char aM, unsigned char aD, unsigned char aH, unsigned char aMin, unsigned char aSec, unsigned char aWk); +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + diff --git a/FW/Core/Inc/spi.h b/FW/Core/Inc/spi.h new file mode 100644 index 0000000..913f44b --- /dev/null +++ b/FW/Core/Inc/spi.h @@ -0,0 +1,50 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.h + * @brief This file contains all the function prototypes for + * the spi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SPI1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ + diff --git a/FW/Core/Inc/stm32_assert.h b/FW/Core/Inc/stm32_assert.h new file mode 100644 index 0000000..f61b663 --- /dev/null +++ b/FW/Core/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32_assert.h + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + diff --git a/FW/Core/Inc/stm32h7xx_hal_conf.h b/FW/Core/Inc/stm32h7xx_hal_conf.h new file mode 100644 index 0000000..02e1dc9 --- /dev/null +++ b/FW/Core/Inc/stm32h7xx_hal_conf.h @@ -0,0 +1,515 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CONF_H +#define STM32H7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_ADC_MODULE_ENABLED */ +#define HAL_FDCAN_MODULE_ENABLED +/* #define HAL_FMAC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_COMP_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_OTFDEC_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +#define HAL_SDRAM_MODULE_ENABLED +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HRTIM_MODULE_ENABLED */ +/* #define HAL_HSEM_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +#define HAL_JPEG_MODULE_ENABLED +/* #define HAL_OPAMP_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_OSPI_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +#define HAL_LTDC_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SWPMI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_UART_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +#define HAL_JPEG_MODULE_ENABLED +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_MDMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal oscillator (CSI) default value. + * This value is the default CSI value after Reset. + */ +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature.*/ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */ +#define USE_RTOS 0 +#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ +#define USE_SPI_CRC 0U /*!< use CRC in SPI */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################### Ethernet Configuration ######################### */ +#define ETH_TX_DESC_CNT 4U /* number of Ethernet Tx DMA descriptors */ +#define ETH_RX_DESC_CNT 4U /* number of Ethernet Rx DMA descriptors */ + +#define ETH_MAC_ADDR0 (0x02UL) +#define ETH_MAC_ADDR1 (0x00UL) +#define ETH_MAC_ADDR2 (0x00UL) +#define ETH_MAC_ADDR3 (0x00UL) +#define ETH_MAC_ADDR4 (0x00UL) +#define ETH_MAC_ADDR5 (0x00UL) + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_MDMA_MODULE_ENABLED + #include "stm32h7xx_hal_mdma.h" +#endif /* HAL_MDMA_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32h7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32h7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32h7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32h7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32h7xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32h7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED + #include "stm32h7xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_HRTIM_MODULE_ENABLED + #include "stm32h7xx_hal_hrtim.h" +#endif /* HAL_HRTIM_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED + #include "stm32h7xx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32h7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32h7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32h7xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OSPI_MODULE_ENABLED + #include "stm32h7xx_hal_ospi.h" +#endif /* HAL_OSPI_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h7xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32h7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7xx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SWPMI_MODULE_ENABLED + #include "stm32h7xx_hal_swpmi.h" +#endif /* HAL_SWPMI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CONF_H */ diff --git a/FW/Core/Inc/stm32h7xx_it.h b/FW/Core/Inc/stm32h7xx_it.h new file mode 100644 index 0000000..84caf5c --- /dev/null +++ b/FW/Core/Inc/stm32h7xx_it.h @@ -0,0 +1,79 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_IT_H +#define __STM32H7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void DMA1_Stream3_IRQHandler(void); +void FDCAN2_IT0_IRQHandler(void); +void USART1_IRQHandler(void); +void USART2_IRQHandler(void); +void USART3_IRQHandler(void); +void UART4_IRQHandler(void); +void UART5_IRQHandler(void); +void TIM7_IRQHandler(void); +void USART6_IRQHandler(void); +void UART7_IRQHandler(void); +void LTDC_IRQHandler(void); +void OTG_FS_IRQHandler(void); +void LPUART1_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_IT_H */ diff --git a/FW/Core/Inc/task.h b/FW/Core/Inc/task.h new file mode 100644 index 0000000..2089ead --- /dev/null +++ b/FW/Core/Inc/task.h @@ -0,0 +1,18 @@ +#ifndef TASK_H_ +#define TASK_H_ + +extern unsigned int sys_tick_1s_rdy; + +extern unsigned int UserRequestReset ; +extern unsigned int SysLoopTick ; + +extern void DoUpdataRtc(); +extern void my_sys_tick(void); +extern void operation_finction(void); + + + + +#endif + + diff --git a/FW/Core/Inc/tim.h b/FW/Core/Inc/tim.h new file mode 100644 index 0000000..b2e8968 --- /dev/null +++ b/FW/Core/Inc/tim.h @@ -0,0 +1,54 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM2_Init(void); +void MX_TIM3_Init(void); +void MX_TIM6_Init(void); +void MX_TIM7_Init(void); +void MX_TIM12_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/FW/Core/Inc/usart.h b/FW/Core/Inc/usart.h new file mode 100644 index 0000000..94cc752 --- /dev/null +++ b/FW/Core/Inc/usart.h @@ -0,0 +1,57 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_LPUART1_UART_Init(void); +void MX_UART4_Init(void); +void MX_UART5_Init(void); +void MX_UART7_Init(void); +void MX_USART1_UART_Init(void); +void MX_USART2_UART_Init(void); +void MX_USART3_UART_Init(void); +void MX_USART6_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + diff --git a/FW/Core/Src/dma.c b/FW/Core/Src/dma.c new file mode 100644 index 0000000..1ecf409 --- /dev/null +++ b/FW/Core/Src/dma.c @@ -0,0 +1,57 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* Init with LL driver */ + /* DMA controller clock enable */ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2); + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); + + /* DMA interrupt init */ + /* DMA1_Stream3_IRQn interrupt configuration */ + NVIC_SetPriority(DMA1_Stream3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(DMA1_Stream3_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/FW/Core/Src/dma2d.c b/FW/Core/Src/dma2d.c new file mode 100644 index 0000000..c7df104 --- /dev/null +++ b/FW/Core/Src/dma2d.c @@ -0,0 +1,59 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma2d.c + * @brief This file provides code for the configuration + * of the DMA2D instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "dma2d.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* DMA2D init function */ +void MX_DMA2D_Init(void) +{ + + /* USER CODE BEGIN DMA2D_Init 0 */ + + /* USER CODE END DMA2D_Init 0 */ + + /* Peripheral clock enable */ + LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_DMA2D); + + /* USER CODE BEGIN DMA2D_Init 1 */ + + /* USER CODE END DMA2D_Init 1 */ + LL_DMA2D_SetMode(DMA2D, LL_DMA2D_MODE_M2M); + LL_DMA2D_SetOutputColorMode(DMA2D, LL_DMA2D_OUTPUT_MODE_ARGB8888); + LL_DMA2D_SetLineOffset(DMA2D, 0); + LL_DMA2D_FGND_SetColorMode(DMA2D, LL_DMA2D_INPUT_MODE_ARGB8888); + LL_DMA2D_FGND_SetAlphaMode(DMA2D, LL_DMA2D_ALPHA_MODE_REPLACE); + LL_DMA2D_FGND_SetAlpha(DMA2D, 0); + LL_DMA2D_FGND_SetLineOffset(DMA2D, 0); + LL_DMA2D_FGND_SetRBSwapMode(DMA2D, LL_DMA2D_RB_MODE_REGULAR); + LL_DMA2D_FGND_SetAlphaInvMode(DMA2D, LL_DMA2D_ALPHA_REGULAR); + LL_DMA2D_FGND_SetChrSubSampling(DMA2D, LL_DMA2D_CSS_444); + /* USER CODE BEGIN DMA2D_Init 2 */ + + /* USER CODE END DMA2D_Init 2 */ + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/fdcan.c b/FW/Core/Src/fdcan.c new file mode 100644 index 0000000..84210e8 --- /dev/null +++ b/FW/Core/Src/fdcan.c @@ -0,0 +1,149 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file fdcan.c + * @brief This file provides code for the configuration + * of the FDCAN instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "fdcan.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +FDCAN_HandleTypeDef hfdcan2; + +/* FDCAN2 init function */ +void MX_FDCAN2_Init(void) +{ + + /* USER CODE BEGIN FDCAN2_Init 0 */ + + /* USER CODE END FDCAN2_Init 0 */ + + /* USER CODE BEGIN FDCAN2_Init 1 */ + + /* USER CODE END FDCAN2_Init 1 */ + hfdcan2.Instance = FDCAN2; + hfdcan2.Init.FrameFormat = FDCAN_FRAME_CLASSIC; + hfdcan2.Init.Mode = FDCAN_MODE_NORMAL; + hfdcan2.Init.AutoRetransmission = ENABLE; + hfdcan2.Init.TransmitPause = DISABLE; + hfdcan2.Init.ProtocolException = DISABLE; + hfdcan2.Init.NominalPrescaler = 53; + hfdcan2.Init.NominalSyncJumpWidth = 3; + hfdcan2.Init.NominalTimeSeg1 = 12; + hfdcan2.Init.NominalTimeSeg2 = 5; + hfdcan2.Init.DataPrescaler = 1; + hfdcan2.Init.DataSyncJumpWidth = 1; + hfdcan2.Init.DataTimeSeg1 = 1; + hfdcan2.Init.DataTimeSeg2 = 1; + hfdcan2.Init.MessageRAMOffset = 0; + hfdcan2.Init.StdFiltersNbr = 0; + hfdcan2.Init.ExtFiltersNbr = 0; + hfdcan2.Init.RxFifo0ElmtsNbr = 1; + hfdcan2.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; + hfdcan2.Init.RxFifo1ElmtsNbr = 0; + hfdcan2.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; + hfdcan2.Init.RxBuffersNbr = 0; + hfdcan2.Init.RxBufferSize = FDCAN_DATA_BYTES_8; + hfdcan2.Init.TxEventsNbr = 0; + hfdcan2.Init.TxBuffersNbr = 0; + hfdcan2.Init.TxFifoQueueElmtsNbr = 1; + hfdcan2.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; + hfdcan2.Init.TxElmtSize = FDCAN_DATA_BYTES_8; + if (HAL_FDCAN_Init(&hfdcan2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN FDCAN2_Init 2 */ + + /* USER CODE END FDCAN2_Init 2 */ + +} + +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* fdcanHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspInit 0 */ + + /* USER CODE END FDCAN2_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN; + PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* FDCAN2 clock enable */ + __HAL_RCC_FDCAN_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* FDCAN2 interrupt Init */ + HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspInit 1 */ + + /* USER CODE END FDCAN2_MspInit 1 */ + } +} + +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* fdcanHandle) +{ + + if(fdcanHandle->Instance==FDCAN2) + { + /* USER CODE BEGIN FDCAN2_MspDeInit 0 */ + + /* USER CODE END FDCAN2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_FDCAN_CLK_DISABLE(); + + /**FDCAN2 GPIO Configuration + PB12 ------> FDCAN2_RX + PB13 ------> FDCAN2_TX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13); + + /* FDCAN2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(FDCAN2_IT0_IRQn); + /* USER CODE BEGIN FDCAN2_MspDeInit 1 */ + + /* USER CODE END FDCAN2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/fmc.c b/FW/Core/Src/fmc.c new file mode 100644 index 0000000..b94dddd --- /dev/null +++ b/FW/Core/Src/fmc.c @@ -0,0 +1,365 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * File Name : FMC.c + * Description : This file provides code for the configuration + * of the FMC peripheral. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "fmc.h" + +/* USER CODE BEGIN 0 */ +FMC_SDRAM_CommandTypeDef command; +/* USER CODE END 0 */ + +SDRAM_HandleTypeDef hsdram1; + +/* FMC initialization function */ +void MX_FMC_Init(void) +{ + /* USER CODE BEGIN FMC_Init 0 */ + + /* USER CODE END FMC_Init 0 */ + + FMC_SDRAM_TimingTypeDef SdramTiming = {0}; + + /* USER CODE BEGIN FMC_Init 1 */ + + /* USER CODE END FMC_Init 1 */ + + /** Perform the SDRAM1 memory initialization sequence + */ + hsdram1.Instance = FMC_SDRAM_DEVICE; + /* hsdram1.Init */ + hsdram1.Init.SDBank = FMC_SDRAM_BANK1; + hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9; + hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13; + hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32; + hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; + hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; + hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; + hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; + /* SdramTiming */ + SdramTiming.LoadToActiveDelay = 2; + SdramTiming.ExitSelfRefreshDelay = 8; + SdramTiming.SelfRefreshTime = 6; + SdramTiming.RowCycleDelay = 6; + SdramTiming.WriteRecoveryTime = 4; + SdramTiming.RPDelay = 2; + SdramTiming.RCDDelay = 2; + + if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) + { + Error_Handler( ); + } + + /* USER CODE BEGIN FMC_Init 2 */ + SDRAM_Initialization_Sequence(&hsdram1, &command); + /* USER CODE END FMC_Init 2 */ +} + +static uint32_t FMC_Initialized = 0; + +static void HAL_FMC_MspInit(void){ + /* USER CODE BEGIN FMC_MspInit 0 */ + + /* USER CODE END FMC_MspInit 0 */ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if (FMC_Initialized) { + return; + } + FMC_Initialized = 1; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC; + PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /** FMC GPIO Configuration + PI9 ------> FMC_D30 + PI10 ------> FMC_D31 + PF0 ------> FMC_A0 + PF1 ------> FMC_A1 + PF2 ------> FMC_A2 + PF3 ------> FMC_A3 + PF4 ------> FMC_A4 + PF5 ------> FMC_A5 + PC2_C ------> FMC_SDNE0 + PC3_C ------> FMC_SDCKE0 + PH5 ------> FMC_SDNWE + PF11 ------> FMC_SDNRAS + PF12 ------> FMC_A6 + PF13 ------> FMC_A7 + PF14 ------> FMC_A8 + PF15 ------> FMC_A9 + PG0 ------> FMC_A10 + PG1 ------> FMC_A11 + PE7 ------> FMC_D4 + PE8 ------> FMC_D5 + PE9 ------> FMC_D6 + PE10 ------> FMC_D7 + PE11 ------> FMC_D8 + PE12 ------> FMC_D9 + PE13 ------> FMC_D10 + PE14 ------> FMC_D11 + PE15 ------> FMC_D12 + PH8 ------> FMC_D16 + PH9 ------> FMC_D17 + PH10 ------> FMC_D18 + PH11 ------> FMC_D19 + PH12 ------> FMC_D20 + PD8 ------> FMC_D13 + PD9 ------> FMC_D14 + PD10 ------> FMC_D15 + PD14 ------> FMC_D0 + PD15 ------> FMC_D1 + PG2 ------> FMC_A12 + PG4 ------> FMC_BA0 + PG5 ------> FMC_BA1 + PG8 ------> FMC_SDCLK + PH13 ------> FMC_D21 + PH14 ------> FMC_D22 + PH15 ------> FMC_D23 + PI0 ------> FMC_D24 + PI1 ------> FMC_D25 + PI2 ------> FMC_D26 + PI3 ------> FMC_D27 + PD0 ------> FMC_D2 + PD1 ------> FMC_D3 + PG15 ------> FMC_SDNCAS + PE0 ------> FMC_NBL0 + PE1 ------> FMC_NBL1 + PI4 ------> FMC_NBL2 + PI5 ------> FMC_NBL3 + PI6 ------> FMC_D28 + PI7 ------> FMC_D29 + */ + /* GPIO_InitStruct */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 + |GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /* GPIO_InitStruct */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* GPIO_InitStruct */ + GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* GPIO_InitStruct */ + GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /* GPIO_InitStruct */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* GPIO_InitStruct */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* GPIO_InitStruct */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_FMC; + + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN FMC_MspInit 1 */ + + /* USER CODE END FMC_MspInit 1 */ +} + +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* sdramHandle){ + /* USER CODE BEGIN SDRAM_MspInit 0 */ + + /* USER CODE END SDRAM_MspInit 0 */ + HAL_FMC_MspInit(); + /* USER CODE BEGIN SDRAM_MspInit 1 */ + + /* USER CODE END SDRAM_MspInit 1 */ +} + +static uint32_t FMC_DeInitialized = 0; + +static void HAL_FMC_MspDeInit(void){ + /* USER CODE BEGIN FMC_MspDeInit 0 */ + + /* USER CODE END FMC_MspDeInit 0 */ + if (FMC_DeInitialized) { + return; + } + FMC_DeInitialized = 1; + /* Peripheral clock enable */ + __HAL_RCC_FMC_CLK_DISABLE(); + + /** FMC GPIO Configuration + PI9 ------> FMC_D30 + PI10 ------> FMC_D31 + PF0 ------> FMC_A0 + PF1 ------> FMC_A1 + PF2 ------> FMC_A2 + PF3 ------> FMC_A3 + PF4 ------> FMC_A4 + PF5 ------> FMC_A5 + PC2_C ------> FMC_SDNE0 + PC3_C ------> FMC_SDCKE0 + PH5 ------> FMC_SDNWE + PF11 ------> FMC_SDNRAS + PF12 ------> FMC_A6 + PF13 ------> FMC_A7 + PF14 ------> FMC_A8 + PF15 ------> FMC_A9 + PG0 ------> FMC_A10 + PG1 ------> FMC_A11 + PE7 ------> FMC_D4 + PE8 ------> FMC_D5 + PE9 ------> FMC_D6 + PE10 ------> FMC_D7 + PE11 ------> FMC_D8 + PE12 ------> FMC_D9 + PE13 ------> FMC_D10 + PE14 ------> FMC_D11 + PE15 ------> FMC_D12 + PH8 ------> FMC_D16 + PH9 ------> FMC_D17 + PH10 ------> FMC_D18 + PH11 ------> FMC_D19 + PH12 ------> FMC_D20 + PD8 ------> FMC_D13 + PD9 ------> FMC_D14 + PD10 ------> FMC_D15 + PD14 ------> FMC_D0 + PD15 ------> FMC_D1 + PG2 ------> FMC_A12 + PG4 ------> FMC_BA0 + PG5 ------> FMC_BA1 + PG8 ------> FMC_SDCLK + PH13 ------> FMC_D21 + PH14 ------> FMC_D22 + PH15 ------> FMC_D23 + PI0 ------> FMC_D24 + PI1 ------> FMC_D25 + PI2 ------> FMC_D26 + PI3 ------> FMC_D27 + PD0 ------> FMC_D2 + PD1 ------> FMC_D3 + PG15 ------> FMC_SDNCAS + PE0 ------> FMC_NBL0 + PE1 ------> FMC_NBL1 + PI4 ------> FMC_NBL2 + PI5 ------> FMC_NBL3 + PI6 ------> FMC_D28 + PI7 ------> FMC_D29 + */ + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1 + |GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5 + |GPIO_PIN_6|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 + |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12 + |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3); + + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15); + + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 + |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14 + |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1); + + /* USER CODE BEGIN FMC_MspDeInit 1 */ + + /* USER CODE END FMC_MspDeInit 1 */ +} + +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* sdramHandle){ + /* USER CODE BEGIN SDRAM_MspDeInit 0 */ + + /* USER CODE END SDRAM_MspDeInit 0 */ + HAL_FMC_MspDeInit(); + /* USER CODE BEGIN SDRAM_MspDeInit 1 */ + + /* USER CODE END SDRAM_MspDeInit 1 */ +} +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Core/Src/gpio.c b/FW/Core/Src/gpio.c new file mode 100644 index 0000000..01dff6a --- /dev/null +++ b/FW/Core/Src/gpio.c @@ -0,0 +1,172 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI +*/ +void MX_GPIO_Init(void) +{ + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOE); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOI); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOF); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD); + + /**/ + LL_GPIO_ResetOutputPin(GPIOE, LL_GPIO_PIN_3); + + /**/ + LL_GPIO_ResetOutputPin(GPIOI, LL_GPIO_PIN_8); + + /**/ + LL_GPIO_ResetOutputPin(GPIOC, LL_GPIO_PIN_1|LL_GPIO_PIN_4|LL_GPIO_PIN_5|LL_GPIO_PIN_8); + + /**/ + LL_GPIO_ResetOutputPin(GPIOH, LL_GPIO_PIN_7); + + /**/ + LL_GPIO_ResetOutputPin(GPIOG, LL_GPIO_PIN_3|LL_GPIO_PIN_13); + + /**/ + LL_GPIO_SetOutputPin(GPIOD, LL_GPIO_PIN_11|LL_GPIO_PIN_12|LL_GPIO_PIN_13); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_13; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_1|LL_GPIO_PIN_4|LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12|LL_GPIO_PIN_13; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_MEDIUM; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_8; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LL_GPIO_PIN_13; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ diff --git a/FW/Core/Src/iwdg.c b/FW/Core/Src/iwdg.c new file mode 100644 index 0000000..2775427 --- /dev/null +++ b/FW/Core/Src/iwdg.c @@ -0,0 +1,55 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file iwdg.c + * @brief This file provides code for the configuration + * of the IWDG instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "iwdg.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* IWDG1 init function */ +void MX_IWDG1_Init(void) +{ + + /* USER CODE BEGIN IWDG1_Init 0 */ + + /* USER CODE END IWDG1_Init 0 */ + + /* USER CODE BEGIN IWDG1_Init 1 */ + + /* USER CODE END IWDG1_Init 1 */ + LL_IWDG_Enable(IWDG1); + LL_IWDG_EnableWriteAccess(IWDG1); + LL_IWDG_SetPrescaler(IWDG1, LL_IWDG_PRESCALER_16); + LL_IWDG_SetReloadCounter(IWDG1, 4095); + while (LL_IWDG_IsReady(IWDG1) != 1) + { + } + + LL_IWDG_ReloadCounter(IWDG1); + /* USER CODE BEGIN IWDG1_Init 2 */ + + /* USER CODE END IWDG1_Init 2 */ + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/jpeg.c b/FW/Core/Src/jpeg.c new file mode 100644 index 0000000..37c7cbb --- /dev/null +++ b/FW/Core/Src/jpeg.c @@ -0,0 +1,85 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file jpeg.c + * @brief This file provides code for the configuration + * of the JPEG instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "jpeg.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +JPEG_HandleTypeDef hjpeg; + +/* JPEG init function */ +void MX_JPEG_Init(void) +{ + + /* USER CODE BEGIN JPEG_Init 0 */ + + /* USER CODE END JPEG_Init 0 */ + + /* USER CODE BEGIN JPEG_Init 1 */ + + /* USER CODE END JPEG_Init 1 */ + hjpeg.Instance = JPEG; + if (HAL_JPEG_Init(&hjpeg) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN JPEG_Init 2 */ + + /* USER CODE END JPEG_Init 2 */ + +} + +void HAL_JPEG_MspInit(JPEG_HandleTypeDef* jpegHandle) +{ + + if(jpegHandle->Instance==JPEG) + { + /* USER CODE BEGIN JPEG_MspInit 0 */ + + /* USER CODE END JPEG_MspInit 0 */ + /* JPEG clock enable */ + __HAL_RCC_JPEG_CLK_ENABLE(); + /* USER CODE BEGIN JPEG_MspInit 1 */ + + /* USER CODE END JPEG_MspInit 1 */ + } +} + +void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef* jpegHandle) +{ + + if(jpegHandle->Instance==JPEG) + { + /* USER CODE BEGIN JPEG_MspDeInit 0 */ + + /* USER CODE END JPEG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_JPEG_CLK_DISABLE(); + /* USER CODE BEGIN JPEG_MspDeInit 1 */ + + /* USER CODE END JPEG_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/ltdc.c b/FW/Core/Src/ltdc.c new file mode 100644 index 0000000..691a896 --- /dev/null +++ b/FW/Core/Src/ltdc.c @@ -0,0 +1,360 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ltdc.c + * @brief This file provides code for the configuration + * of the LTDC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "ltdc.h" + +/* USER CODE BEGIN 0 */ +#include "stm32h7xx_hal_ltdc.h" +/* USER CODE END 0 */ + +LTDC_HandleTypeDef hltdc; + +/* LTDC init function */ +void MX_LTDC_Init(void) +{ + + /* USER CODE BEGIN LTDC_Init 0 */ + + /* USER CODE END LTDC_Init 0 */ + + LTDC_LayerCfgTypeDef pLayerCfg = {0}; + LTDC_LayerCfgTypeDef pLayerCfg1 = {0}; + + /* USER CODE BEGIN LTDC_Init 1 */ + + /* USER CODE END LTDC_Init 1 */ + hltdc.Instance = LTDC; + hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL; + hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL; + hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL; + hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; + hltdc.Init.HorizontalSync = 0; + hltdc.Init.VerticalSync = 0; + hltdc.Init.AccumulatedHBP = 46; + hltdc.Init.AccumulatedVBP = 23; + hltdc.Init.AccumulatedActiveW = 846; + hltdc.Init.AccumulatedActiveH = 503; + hltdc.Init.TotalWidth = 1056; + hltdc.Init.TotalHeigh = 525; + hltdc.Init.Backcolor.Blue = 0; + hltdc.Init.Backcolor.Green = 0; + hltdc.Init.Backcolor.Red = 0; + if (HAL_LTDC_Init(&hltdc) != HAL_OK) + { + Error_Handler(); + } + pLayerCfg.WindowX0 = 0; + pLayerCfg.WindowX1 = 800; + pLayerCfg.WindowY0 = 0; + pLayerCfg.WindowY1 = 480; + pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + pLayerCfg.Alpha = 255; + pLayerCfg.Alpha0 = 0; + pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA; + pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA; + pLayerCfg.FBStartAdress = 0xC0000000; + pLayerCfg.ImageWidth = 800; + pLayerCfg.ImageHeight = 480; + pLayerCfg.Backcolor.Blue = 0; + pLayerCfg.Backcolor.Green = 0; + pLayerCfg.Backcolor.Red = 0; + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK) + { + Error_Handler(); + } + pLayerCfg1.WindowX0 = 0; + pLayerCfg1.WindowX1 = 800; + pLayerCfg1.WindowY0 = 0; + pLayerCfg1.WindowY1 = 480; + pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888; + pLayerCfg1.Alpha = 255; + pLayerCfg1.Alpha0 = 0; + pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA; + pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA; + pLayerCfg1.FBStartAdress = 0xC0177000; + pLayerCfg1.ImageWidth = 800; + pLayerCfg1.ImageHeight = 480; + pLayerCfg1.Backcolor.Blue = 0; + pLayerCfg1.Backcolor.Green = 0; + pLayerCfg1.Backcolor.Red = 0; + if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN LTDC_Init 2 */ + //HAL_LTDC_ProgramLineEvent(&hltdc,0); + //__HAL_LTDC_ENABLE_IT(&hltdc, LTDC_IT_LI); + /* USER CODE END LTDC_Init 2 */ + +} + +void HAL_LTDC_MspInit(LTDC_HandleTypeDef* ltdcHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(ltdcHandle->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspInit 0 */ + + /* USER CODE END LTDC_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; + PeriphClkInitStruct.PLL3.PLL3M = 1; + PeriphClkInitStruct.PLL3.PLL3N = 18; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 2; + PeriphClkInitStruct.PLL3.PLL3R = 5; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOMEDIUM; + PeriphClkInitStruct.PLL3.PLL3FRACN = 6144; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* LTDC clock enable */ + __HAL_RCC_LTDC_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**LTDC GPIO Configuration + PE4 ------> LTDC_B0 + PE5 ------> LTDC_G0 + PE6 ------> LTDC_G1 + PI11 ------> LTDC_G6 + PF10 ------> LTDC_DE + PC0 ------> LTDC_R5 + PA1 ------> LTDC_R2 + PA2 ------> LTDC_R1 + PH2 ------> LTDC_R0 + PH4 ------> LTDC_G5 + PA3 ------> LTDC_B5 + PA4 ------> LTDC_VSYNC + PA5 ------> LTDC_R4 + PA6 ------> LTDC_G2 + PB0 ------> LTDC_R3 + PB1 ------> LTDC_R6 + PB10 ------> LTDC_G4 + PG6 ------> LTDC_R7 + PG7 ------> LTDC_CLK + PC6 ------> LTDC_HSYNC + PC9 ------> LTDC_B2 + PA8 ------> LTDC_B3 + PA10 ------> LTDC_B4 + PD3 ------> LTDC_G7 + PG10 ------> LTDC_G3 + PG12 ------> LTDC_B1 + PB8 ------> LTDC_B6 + PB9 ------> LTDC_B7 + */ + GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_6|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_4; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF13_LTDC; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_LTDC; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF14_LTDC; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_LTDC; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + HAL_I2CEx_EnableFastModePlus(SYSCFG_PMCR_I2C_PB8_FMP); + + HAL_I2CEx_EnableFastModePlus(SYSCFG_PMCR_I2C_PB9_FMP); + + /* LTDC interrupt Init */ + HAL_NVIC_SetPriority(LTDC_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LTDC_IRQn); + /* USER CODE BEGIN LTDC_MspInit 1 */ + + /* USER CODE END LTDC_MspInit 1 */ + } +} + +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* ltdcHandle) +{ + + if(ltdcHandle->Instance==LTDC) + { + /* USER CODE BEGIN LTDC_MspDeInit 0 */ + + /* USER CODE END LTDC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LTDC_CLK_DISABLE(); + + /**LTDC GPIO Configuration + PE4 ------> LTDC_B0 + PE5 ------> LTDC_G0 + PE6 ------> LTDC_G1 + PI11 ------> LTDC_G6 + PF10 ------> LTDC_DE + PC0 ------> LTDC_R5 + PA1 ------> LTDC_R2 + PA2 ------> LTDC_R1 + PH2 ------> LTDC_R0 + PH4 ------> LTDC_G5 + PA3 ------> LTDC_B5 + PA4 ------> LTDC_VSYNC + PA5 ------> LTDC_R4 + PA6 ------> LTDC_G2 + PB0 ------> LTDC_R3 + PB1 ------> LTDC_R6 + PB10 ------> LTDC_G4 + PG6 ------> LTDC_R7 + PG7 ------> LTDC_CLK + PC6 ------> LTDC_HSYNC + PC9 ------> LTDC_B2 + PA8 ------> LTDC_B3 + PA10 ------> LTDC_B4 + PD3 ------> LTDC_G7 + PG10 ------> LTDC_G3 + PG12 ------> LTDC_B1 + PB8 ------> LTDC_B6 + PB9 ------> LTDC_B7 + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6); + + HAL_GPIO_DeInit(GPIOI, GPIO_PIN_11); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10); + + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0|GPIO_PIN_6|GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4 + |GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_8|GPIO_PIN_10); + + HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_4); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_10|GPIO_PIN_8 + |GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_3); + + /* LTDC interrupt Deinit */ + HAL_NVIC_DisableIRQ(LTDC_IRQn); + /* USER CODE BEGIN LTDC_MspDeInit 1 */ + + /* USER CODE END LTDC_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/main.c b/FW/Core/Src/main.c new file mode 100644 index 0000000..193c388 --- /dev/null +++ b/FW/Core/Src/main.c @@ -0,0 +1,338 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "dma.h" +#include "dma2d.h" +#include "fatfs.h" +#include "fdcan.h" +#include "iwdg.h" +#include "jpeg.h" +#include "usart.h" +#include "ltdc.h" +#include "quadspi.h" +#include "rtc.h" +#include "spi.h" +#include "tim.h" +#include "usb_host.h" +#include "gpio.h" +#include "fmc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "HW_config.h" +#include "task.h" + +#include "CnCpp.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MPU_Config(void); +void MX_USB_HOST_Process(void); + +/* USER CODE BEGIN PFP */ +static void MX_CRC_Init(void); +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +/** + * @brief CRC Initialization Function + * @param None + * @retval None + */ +static void MX_CRC_Init(void) +{ + + /* USER CODE BEGIN CRC_Init 0 */ + + /* USER CODE END CRC_Init 0 */ + + /* Peripheral clock enable */ + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_CRC); + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + LL_CRC_SetInputDataReverseMode(CRC, LL_CRC_INDATA_REVERSE_NONE); + LL_CRC_SetOutputDataReverseMode(CRC, LL_CRC_OUTDATA_REVERSE_NONE); + LL_CRC_SetPolynomialCoef(CRC, LL_CRC_DEFAULT_CRC32_POLY); + LL_CRC_SetPolynomialSize(CRC, LL_CRC_POLYLENGTH_32B); + LL_CRC_SetInitialData(CRC, LL_CRC_DEFAULT_CRC_INITVALUE); + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ + +} + +static void WaitSdramRdy() +{ + volatile unsigned int aWait; + for(aWait=0; aWait<1000000; aWait++); +} +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + + /* USER CODE END 1 */ + + /* MPU Configuration--------------------------------------------------------*/ + MPU_Config(); +/* Enable the CPU Cache */ + + /* Enable I-Cache---------------------------------------------------------*/ + SCB_EnableICache(); + + /* Enable D-Cache---------------------------------------------------------*/ + SCB_EnableDCache(); + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + SystemCoreClockUpdate(); + HAL_SYSTICK_Config(SystemCoreClock / 1000);//1ms + //HAL_Delay(100); + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + WaitSdramRdy(); + MX_DMA_Init(); + MX_FMC_Init(); + MX_QUADSPI_Init(); + MX_FDCAN2_Init(); + MX_USART1_UART_Init(); + MX_USART2_UART_Init(); + MX_USART3_UART_Init(); + MX_UART4_Init(); + MX_UART5_Init(); + MX_USART6_UART_Init(); + MX_UART7_Init(); + MX_LPUART1_UART_Init(); + MX_TIM2_Init(); + MX_TIM3_Init(); + MX_TIM12_Init(); + MX_TIM6_Init(); + MX_TIM7_Init(); + MX_DMA2D_Init(); + MX_LTDC_Init(); + MX_SPI1_Init(); + + MX_IWDG1_Init(); + + MX_USB_DEVICE_Init(); + HAL_Delay(5); + MX_USB_DEVICE_DeInit(); + HAL_Delay(5); + UsbConfigSetState(0); + usb_is_host = 1; + + MX_USB_HOST_Init(); + MX_FATFS_Init(); + + //MX_JPEG_Init(); + MX_RTC_Init(); + MX_CRC_Init(); + LL_IWDG_ReloadCounter(IWDG1); + /* USER CODE BEGIN 2 */ + HAL_Delay(10); + HW_init(); + HAL_Delay(10); + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + CppGuiInit(); + while (1) + { + operation_finction(); + /* USER CODE END WHILE */ + MX_USB_HOST_Process(); + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Supply configuration update enable + */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE + |RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 120; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 20; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/* MPU Configuration */ + +void MPU_Config(void) +{ + + /* Disables the MPU */ + LL_MPU_Disable(); + + /** Initializes and configures the Region and the memory to be protected + */ + LL_MPU_ConfigRegion(LL_MPU_REGION_NUMBER0, 0x87, 0x0, LL_MPU_REGION_SIZE_4GB|LL_MPU_TEX_LEVEL0|LL_MPU_REGION_NO_ACCESS|LL_MPU_INSTRUCTION_ACCESS_DISABLE|LL_MPU_ACCESS_SHAREABLE|LL_MPU_ACCESS_NOT_CACHEABLE|LL_MPU_ACCESS_NOT_BUFFERABLE); + + /** Initializes and configures the Region and the memory to be protected + */ + LL_MPU_ConfigRegion(LL_MPU_REGION_NUMBER1, 0x0, 0xC0000000, LL_MPU_REGION_SIZE_64MB|LL_MPU_TEX_LEVEL0|LL_MPU_REGION_FULL_ACCESS|LL_MPU_INSTRUCTION_ACCESS_ENABLE|LL_MPU_ACCESS_NOT_SHAREABLE|LL_MPU_ACCESS_CACHEABLE|LL_MPU_ACCESS_BUFFERABLE); + /* Enables the MPU */ + LL_MPU_Enable(LL_MPU_CTRL_PRIVILEGED_DEFAULT); + +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + GPIOC->ODR ^=0x0020; + HAL_Delay(800); + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/FW/Core/Src/quadspi.c b/FW/Core/Src/quadspi.c new file mode 100644 index 0000000..cc70944 --- /dev/null +++ b/FW/Core/Src/quadspi.c @@ -0,0 +1,212 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file quadspi.c + * @brief This file provides code for the configuration + * of the QUADSPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "quadspi.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +QSPI_HandleTypeDef hqspi; + +/* QUADSPI init function */ +void MX_QUADSPI_Init(void) +{ + + /* USER CODE BEGIN QUADSPI_Init 0 */ + + /* USER CODE END QUADSPI_Init 0 */ + + /* USER CODE BEGIN QUADSPI_Init 1 */ + + /* USER CODE END QUADSPI_Init 1 */ + hqspi.Instance = QUADSPI; + hqspi.Init.ClockPrescaler = 9; + hqspi.Init.FifoThreshold = 4; + hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; + hqspi.Init.FlashSize = 24; + hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE; + hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0; + hqspi.Init.FlashID = QSPI_FLASH_ID_1; + hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + if (HAL_QSPI_Init(&hqspi) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN QUADSPI_Init 2 */ + + /* USER CODE END QUADSPI_Init 2 */ + +} + +void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(qspiHandle->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspInit 0 */ + + /* USER CODE END QUADSPI_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI; + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* QUADSPI clock enable */ + __HAL_RCC_QSPI_CLK_ENABLE(); + + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**QUADSPI GPIO Configuration + PF6 ------> QUADSPI_BK1_IO3 + PF7 ------> QUADSPI_BK1_IO2 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + PB2 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + */ + GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN QUADSPI_MspInit 1 */ + + /* USER CODE END QUADSPI_MspInit 1 */ + } +} + +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef* qspiHandle) +{ + + if(qspiHandle->Instance==QUADSPI) + { + /* USER CODE BEGIN QUADSPI_MspDeInit 0 */ + + /* USER CODE END QUADSPI_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_QSPI_CLK_DISABLE(); + + /**QUADSPI GPIO Configuration + PF6 ------> QUADSPI_BK1_IO3 + PF7 ------> QUADSPI_BK1_IO2 + PF8 ------> QUADSPI_BK1_IO0 + PF9 ------> QUADSPI_BK1_IO1 + PB2 ------> QUADSPI_CLK + PB6 ------> QUADSPI_BK1_NCS + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_2|GPIO_PIN_6); + + /* USER CODE BEGIN QUADSPI_MspDeInit 1 */ + + /* USER CODE END QUADSPI_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +//QSPI发送命令 +//instruction:要发送的指令 +//address:发送到的目的地址 +//dummyCycles:空指令周期数 +// instructionMode:指令模式;QSPI_INSTRUCTION_NONE,QSPI_INSTRUCTION_1_LINE,QSPI_INSTRUCTION_2_LINE,QSPI_INSTRUCTION_4_LINE +// addressMode:地址模式; QSPI_ADDRESS_NONE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_2_LINE,QSPI_ADDRESS_4_LINE +// addressSize:地址长度;QSPI_ADDRESS_8_BITS,QSPI_ADDRESS_16_BITS,QSPI_ADDRESS_24_BITS,QSPI_ADDRESS_32_BITS +// dataMode:数据模式; QSPI_DATA_NONE,QSPI_DATA_1_LINE,QSPI_DATA_2_LINE,QSPI_DATA_4_LINE + +void QSPI_Send_CMD(unsigned int instruction,unsigned int address,unsigned int dummyCycles,unsigned int instructionMode,unsigned int addressMode,unsigned int addressSize,unsigned int dataMode) +{ + QSPI_CommandTypeDef Cmdhandler; + + Cmdhandler.Instruction=instruction; //指令 + Cmdhandler.Address=address; //地址 + Cmdhandler.DummyCycles=dummyCycles; //设置空指令周期数 + Cmdhandler.InstructionMode=instructionMode; //指令模式 + Cmdhandler.AddressMode=addressMode; //地址模式 + Cmdhandler.AddressSize=addressSize; //地址长度 + Cmdhandler.DataMode=dataMode; //数据模式 + Cmdhandler.SIOOMode=QSPI_SIOO_INST_EVERY_CMD; //每次都发送指令 + Cmdhandler.AlternateByteMode=QSPI_ALTERNATE_BYTES_NONE; //无交替字节 + Cmdhandler.DdrMode=QSPI_DDR_MODE_DISABLE; //关闭DDR模式 + Cmdhandler.DdrHoldHalfCycle=QSPI_DDR_HHC_ANALOG_DELAY; + + if(HAL_QSPI_Command(&hqspi,&Cmdhandler,5000) != HAL_OK) + { + Error_Handler(); + } +} + +//QSPI接收指定长度的数据 +//buf:接收数据缓冲区首地址 +//datalen:要传输的数据长度 +//返回值:0,正常 +// 其他,错误代码 +unsigned char QSPI_Receive(unsigned char* buf,unsigned int datalen) +{ + hqspi.Instance->DLR=datalen-1; //配置数据长度 + if(HAL_QSPI_Receive(&hqspi,buf,5000)==HAL_OK) return 0; //接收数据 + else return 1; +} + +//QSPI发送指定长度的数据 +//buf:发送数据缓冲区首地址 +//datalen:要传输的数据长度 +//返回值:0,正常 +// 其他,错误代码 +unsigned char QSPI_Transmit(unsigned char* buf,unsigned int datalen) +{ + hqspi.Instance->DLR=datalen-1; //配置数据长度 + if(HAL_QSPI_Transmit(&hqspi,buf,5000)==HAL_OK) return 0; //发送数据 + else return 1; +} + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/rtc.c b/FW/Core/Src/rtc.c new file mode 100644 index 0000000..ed4b07d --- /dev/null +++ b/FW/Core/Src/rtc.c @@ -0,0 +1,149 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file rtc.c + * @brief This file provides code for the configuration + * of the RTC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "rtc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* RTC init function */ +void MX_RTC_Init(void) +{ + + /* USER CODE BEGIN RTC_Init 0 */ + + /* USER CODE END RTC_Init 0 */ + + LL_RTC_InitTypeDef RTC_InitStruct = {0}; + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_RCC_EnableRTC(); + + /* USER CODE BEGIN RTC_Init 1 */ + + /* USER CODE END RTC_Init 1 */ + RTC_InitStruct.HourFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_InitStruct.AsynchPrescaler = 127; + RTC_InitStruct.SynchPrescaler = 255; + LL_RTC_Init(RTC, &RTC_InitStruct); + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + +/* USER CODE BEGIN 1 */ +LL_RTC_TimeTypeDef RTC_TimeStruct = {0}; +LL_RTC_DateTypeDef RTC_DateStruct = {0}; + +void RTC_Config(void) +{ + LL_RTC_InitTypeDef RTC_InitStruct = {0}; + + LL_RTC_WaitForSynchro(RTC); + + RTC_InitStruct.HourFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_InitStruct.AsynchPrescaler = 127; + RTC_InitStruct.SynchPrescaler = 255; + LL_RTC_Init(RTC, &RTC_InitStruct); + + RTC_TimeStruct.TimeFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_TimeStruct.Hours = 0x10; + RTC_TimeStruct.Minutes = 0x25; + RTC_TimeStruct.Seconds = 0x02; + LL_RTC_TIME_Init(RTC, LL_RTC_FORMAT_BCD, &RTC_TimeStruct); + + RTC_DateStruct.Year = 0x24; + RTC_DateStruct.Month = LL_RTC_MONTH_NOVEMBER; + RTC_DateStruct.Day = 0x05; + RTC_DateStruct.WeekDay = LL_RTC_WEEKDAY_TUESDAY; + LL_RTC_DATE_Init(RTC, LL_RTC_FORMAT_BCD, &RTC_DateStruct); + + LL_RTC_BAK_SetRegister(RTC, LL_RTC_BKP_DR0, 0x32F2); +} + +void RTC_TimeShow(void) +{ + /* Get the current Time */ + RTC_TimeStruct.Hours = LL_RTC_TIME_GetHour(RTC); + RTC_TimeStruct.Minutes = LL_RTC_TIME_GetMinute(RTC); + RTC_TimeStruct.Seconds = LL_RTC_TIME_GetSecond(RTC); + + RTC_DateStruct.Year = LL_RTC_DATE_GetYear(RTC); + RTC_DateStruct.Month = LL_RTC_DATE_GetMonth(RTC); + RTC_DateStruct.Day = LL_RTC_DATE_GetDay(RTC); + RTC_DateStruct.WeekDay = LL_RTC_DATE_GetWeekDay(RTC); + + SystemDataTimeUpdata( RTC_DateStruct.Year, + RTC_DateStruct.Month, + RTC_DateStruct.Day, + RTC_TimeStruct.Hours, + RTC_TimeStruct.Minutes, + RTC_TimeStruct.Seconds + ); +} + +void rtc_init() +{ + if(0x32F2 != (LL_RTC_BAK_GetRegister(RTC, LL_RTC_BKP_DR0))) + { + RTC_Config(); + RTC_TimeShow(); + } + else + { + RTC_TimeShow(); + } +} + +void RTC_DataTimeSet(unsigned char aY, unsigned char aM, unsigned char aD, unsigned char aH, unsigned char aMin, unsigned char aSec, unsigned char aWk) +{ + if((!aY)||(!aM)||(!aD))return; + + LL_RTC_WaitForSynchro(RTC); + + RTC_TimeStruct.Hours = aH; + RTC_TimeStruct.Minutes = aMin; + RTC_TimeStruct.Seconds = aSec; + + RTC_DateStruct.Year = aY; + RTC_DateStruct.Month = aM; + RTC_DateStruct.Day = aD; + + RTC_DateStruct.WeekDay = aWk; + + LL_RTC_DATE_Init(RTC,LL_RTC_FORMAT_BCD, &RTC_DateStruct); + LL_RTC_TIME_Init(RTC,LL_RTC_FORMAT_BCD, &RTC_TimeStruct); + + LL_RTC_BAK_SetRegister(RTC, LL_RTC_BKP_DR0, 0x32F2); +} +/* USER CODE END 1 */ diff --git a/FW/Core/Src/spi.c b/FW/Core/Src/spi.c new file mode 100644 index 0000000..ed4743b --- /dev/null +++ b/FW/Core/Src/spi.c @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.c + * @brief This file provides code for the configuration + * of the SPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2024 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "spi.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* SPI1 init function */ +void MX_SPI1_Init(void) +{ + + /* USER CODE BEGIN SPI1_Init 0 */ + + /* USER CODE END SPI1_Init 0 */ + + LL_SPI_InitTypeDef SPI_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG); + /**SPI1 GPIO Configuration + PD7 ------> SPI1_MOSI + PG9 ------> SPI1_MISO + PG11 ------> SPI1_SCK + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_9|LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_5; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI1_Init 1 */ + + /* USER CODE END SPI1_Init 1 */ + SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct.Mode = LL_SPI_MODE_MASTER; + SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct.ClockPhase = LL_SPI_PHASE_2EDGE; + SPI_InitStruct.NSS = LL_SPI_NSS_SOFT; + SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV16; + SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct.CRCPoly = 0x0; + LL_SPI_Init(SPI1, &SPI_InitStruct); + LL_SPI_SetStandard(SPI1, LL_SPI_PROTOCOL_MOTOROLA); + LL_SPI_EnableNSSPulseMgt(SPI1); + /* USER CODE BEGIN SPI1_Init 2 */ + + /* USER CODE END SPI1_Init 2 */ + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/stm32h7xx_hal_msp.c b/FW/Core/Src/stm32h7xx_hal_msp.c new file mode 100644 index 0000000..1bdee08 --- /dev/null +++ b/FW/Core/Src/stm32h7xx_hal_msp.c @@ -0,0 +1,81 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/stm32h7xx_it.c b/FW/Core/Src/stm32h7xx_it.c new file mode 100644 index 0000000..5d06465 --- /dev/null +++ b/FW/Core/Src/stm32h7xx_it.c @@ -0,0 +1,749 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "HW_config.h" +#include "uart_fecbus_drv.h" +#include "uart_fec_std_drv.h" +#include "uart_lp_test_drv.h" +#include "task.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern HCD_HandleTypeDef hhcd_USB_OTG_FS; +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; +extern FDCAN_HandleTypeDef hfdcan2; +extern LTDC_HandleTypeDef hltdc; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVCall_IRQn 0 */ + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + my_sys_tick(); + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32H7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32h7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles DMA1 stream3 global interrupt. + */ +void DMA1_Stream3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ + + /* USER CODE END DMA1_Stream3_IRQn 0 */ + + /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ + + /* USER CODE END DMA1_Stream3_IRQn 1 */ +} + +/** + * @brief This function handles FDCAN2 interrupt 0. + */ +void FDCAN2_IT0_IRQHandler(void) +{ + /* USER CODE BEGIN FDCAN2_IT0_IRQn 0 */ + + /* USER CODE END FDCAN2_IT0_IRQn 0 */ + HAL_FDCAN_IRQHandler(&hfdcan2); + /* USER CODE BEGIN FDCAN2_IT0_IRQn 1 */ + + /* USER CODE END FDCAN2_IT0_IRQn 1 */ +} + +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[1]; + /* USER CODE END USART1_IRQn 0 */ + /* USER CODE BEGIN USART1_IRQn 1 */ + if(LL_USART_IsActiveFlag_RXNE(USART1)) + { + cc = LL_USART_ReceiveData8(USART1); + + if(p_uart_info->rx_index < UART_RX_BUF_MAX) + { + p_uart_info->rx_buf[p_uart_info->rx_index] = cc; + p_uart_info->rx_index++; + } + } + + if(LL_USART_IsActiveFlag_IDLE(USART1)) + { + LL_USART_ClearFlag_IDLE(USART1); + if(p_uart_info->rx_index) + { + p_uart_info->rx_len = p_uart_info->rx_index; + p_uart_info->rx_index = 0; + p_uart_info->rx_complete = 1; + } + } + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(USART1)) + { + LL_USART_ClearFlag_TC(USART1); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(USART1); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(USART1)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(USART1); + } + else + { + LL_USART_TransmitData8(USART1, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(USART1); + /* USER CODE END USART1_IRQn 1 */ +} + +/** + * @brief This function handles USART2 global interrupt. + */ +void USART2_IRQHandler(void) +{ + /* USER CODE BEGIN USART2_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[2]; + /* USER CODE END USART2_IRQn 0 */ + /* USER CODE BEGIN USART2_IRQn 1 */ + fecbus_rx_irq(); + /* + if(LL_USART_IsActiveFlag_RXNE(USART2)) + { + cc = LL_USART_ReceiveData8(USART2); + + if(p_uart_info->rx_index < UART_RX_BUF_MAX) + { + p_uart_info->rx_buf[p_uart_info->rx_index] = cc; + p_uart_info->rx_index++; + } + } + + if(LL_USART_IsActiveFlag_IDLE(USART2)) + { + LL_USART_ClearFlag_IDLE(USART2); + if(p_uart_info->rx_index) + { + p_uart_info->rx_len = p_uart_info->rx_index; + p_uart_info->rx_index = 0; + p_uart_info->rx_complete = 1; + } + } + */ + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(USART2)) + { + LL_USART_ClearFlag_TC(USART2); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(USART2); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(USART2)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(USART2); + } + else + { + LL_USART_TransmitData8(USART2, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(USART2); + /* USER CODE END USART2_IRQn 1 */ +} + +/** + * @brief This function handles USART3 global interrupt. + */ +void USART3_IRQHandler(void) +{ + /* USER CODE BEGIN USART3_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[3]; + /* USER CODE END USART3_IRQn 0 */ + /* USER CODE BEGIN USART3_IRQn 1 */ + if(LL_USART_IsActiveFlag_RXNE(USART3)) + { + cc = LL_USART_ReceiveData8(USART3); + + if(p_uart_info->rx_index < UART_RX_BUF_MAX) + { + p_uart_info->rx_buf[p_uart_info->rx_index] = cc; + p_uart_info->rx_index++; + } + } + + if(LL_USART_IsActiveFlag_IDLE(USART3)) + { + LL_USART_ClearFlag_IDLE(USART3); + if(p_uart_info->rx_index) + { + p_uart_info->rx_len = p_uart_info->rx_index; + p_uart_info->rx_index = 0; + p_uart_info->rx_complete = 1; + } + } + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(USART3)) + { + LL_USART_ClearFlag_TC(USART3); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(USART3); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(USART3)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(USART3); + } + else + { + LL_USART_TransmitData8(USART3, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(USART3); + /* USER CODE END USART3_IRQn 1 */ +} + +/** + * @brief This function handles UART4 global interrupt. + */ +void UART4_IRQHandler(void) +{ + /* USER CODE BEGIN UART4_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[4]; + /* USER CODE END UART4_IRQn 0 */ + /* USER CODE BEGIN UART4_IRQn 1 */ + fec_std_rx_irq(); + + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(UART4)) + { + LL_USART_ClearFlag_TC(UART4); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(UART4); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(UART4)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(UART4); + } + else + { + LL_USART_TransmitData8(UART4, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(UART4); + /* USER CODE END UART4_IRQn 1 */ +} + +/** + * @brief This function handles UART5 global interrupt. + */ +void UART5_IRQHandler(void) +{ + /* USER CODE BEGIN UART5_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[5]; + /* USER CODE END UART5_IRQn 0 */ + /* USER CODE BEGIN UART5_IRQn 1 */ + if(LL_USART_IsActiveFlag_RXNE(UART5)) + { + cc = LL_USART_ReceiveData8(UART5); + + if(p_uart_info->rx_index < UART_RX_BUF_MAX) + { + p_uart_info->rx_buf[p_uart_info->rx_index] = cc; + p_uart_info->rx_index++; + } + } + + if(LL_USART_IsActiveFlag_IDLE(UART5)) + { + LL_USART_ClearFlag_IDLE(UART5); + if(p_uart_info->rx_index) + { + p_uart_info->rx_len = p_uart_info->rx_index; + p_uart_info->rx_index = 0; + p_uart_info->rx_complete = 1; + } + } + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(UART5)) + { + LL_USART_ClearFlag_TC(UART5); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(UART5); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(UART5)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(UART5); + } + else + { + LL_USART_TransmitData8(UART5, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(UART5); + /* USER CODE END UART5_IRQn 1 */ +} + +/** + * @brief This function handles TIM7 global interrupt. + */ +void TIM7_IRQHandler(void) +{ + /* USER CODE BEGIN TIM7_IRQn 0 */ + + /* USER CODE END TIM7_IRQn 0 */ + /* USER CODE BEGIN TIM7_IRQn 1 */ + if(LL_TIM_IsActiveFlag_UPDATE(TIM7)) + { + LL_TIM_ClearFlag_UPDATE(TIM7); + //GPIOC->ODR^=0x20; + } + /* USER CODE END TIM7_IRQn 1 */ +} + +/** + * @brief This function handles USART6 global interrupt. + */ +void USART6_IRQHandler(void) +{ + /* USER CODE BEGIN USART6_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[6]; + /* USER CODE END USART6_IRQn 0 */ + /* USER CODE BEGIN USART6_IRQn 1 */ + if(LL_USART_IsActiveFlag_RXNE(USART6)) + { + cc = LL_USART_ReceiveData8(USART6); + + p_uart_info->rx_index = 0; + p_uart_info->rx_complete = 1; + p_uart_info->rx_buf[p_uart_info->rx_index] = cc; + p_uart_info->rx_index++; + p_uart_info->rx_len = p_uart_info->rx_index; + p_uart_info->rx_index = 0; + } + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(USART6)) + { + LL_USART_ClearFlag_TC(USART6); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(USART6); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(USART6)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(USART6); + } + else + { + LL_USART_TransmitData8(USART6, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(USART6); + /* USER CODE END USART6_IRQn 1 */ +} + +/** + * @brief This function handles UART7 global interrupt. + */ +void UART7_IRQHandler(void) +{ + /* USER CODE BEGIN UART7_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[7]; + /* USER CODE END UART7_IRQn 0 */ + /* USER CODE BEGIN UART7_IRQn 1 */ + /* + if(LL_USART_IsActiveFlag_RXNE(UART7)) + { + cc = LL_USART_ReceiveData8(UART7); + + if(cc == UART_HEAD) + { + p_uart_info->rx_index = 0; + } + else if(cc == UART_END) + { + p_uart_info->rx_len = p_uart_info->rx_index; + p_uart_info->rx_complete = 1; + } + else + { + if(p_uart_info->rx_index < UART_RX_BUF_MAX) + { + p_uart_info->rx_buf[p_uart_info->rx_index] = cc; + p_uart_info->rx_index++; + } + } + } + + if(LL_USART_IsActiveFlag_IDLE(UART7)) + { + LL_USART_ClearFlag_IDLE(UART7); + } + */ + + if(LL_USART_IsActiveFlag_RXNE(UART7)) + { + cc = LL_USART_ReceiveData8(UART7); + + if(p_uart_info->rx_index < UART_RX_BUF_MAX) + { + p_uart_info->rx_buf[p_uart_info->rx_index] = cc; + p_uart_info->rx_index++; + } + } + + if(LL_USART_IsActiveFlag_IDLE(UART7)) + { + LL_USART_ClearFlag_IDLE(UART7); + if(p_uart_info->rx_index) + { + p_uart_info->rx_len = p_uart_info->rx_index; + p_uart_info->rx_index = 0; + p_uart_info->rx_complete = 1; + } + } + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(UART7)) + { + LL_USART_ClearFlag_TC(UART7); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(UART7); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(UART7)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(UART7); + } + else + { + LL_USART_TransmitData8(UART7, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(UART7); + /* USER CODE END UART7_IRQn 1 */ +} + +/** + * @brief This function handles LTDC global interrupt. + */ +void LTDC_IRQHandler(void) +{ + /* USER CODE BEGIN LTDC_IRQn 0 */ + + /* USER CODE END LTDC_IRQn 0 */ + HAL_LTDC_IRQHandler(&hltdc); + /* USER CODE BEGIN LTDC_IRQn 1 */ + + /* USER CODE END LTDC_IRQn 1 */ +} + +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_HCD_IRQHandler(&hhcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + /* USER CODE END OTG_FS_IRQn 1 */ +} + +/** + * @brief This function handles LPUART1 global interrupt. + */ +void LPUART1_IRQHandler(void) +{ + /* USER CODE BEGIN LPUART1_IRQn 0 */ + unsigned short cc; + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[0]; + /* USER CODE END LPUART1_IRQn 0 */ + /* USER CODE BEGIN LPUART1_IRQn 1 */ + test_rx_irq(); + + //-------------------------------------------------------------------------------------------------- + if(LL_USART_IsActiveFlag_TC(LPUART1)) + { + LL_USART_ClearFlag_TC(LPUART1); + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TC(LPUART1); + p_uart_info->tx_complete = 1; + } + } + + if(LL_USART_IsActiveFlag_TXFE(LPUART1)) + { + if(p_uart_info->tx_index >= p_uart_info->tx_len) + { + LL_USART_DisableIT_TXFE(LPUART1); + } + else + { + LL_USART_TransmitData8(LPUART1, p_uart_info->tx_buf[p_uart_info->tx_index]); + p_uart_info->tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(LPUART1); + /* USER CODE END LPUART1_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/system_stm32h7xx.c b/FW/Core/Src/system_stm32h7xx.c new file mode 100644 index 0000000..86e6784 --- /dev/null +++ b/FW/Core/Src/system_stm32h7xx.c @@ -0,0 +1,450 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock, it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */ +/* #define DATA_IN_D2_SRAM */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +#if defined(DUAL_CORE) && defined(CORE_CM4) +/*!< Uncomment the following line if you need to relocate your vector Table + in D2 AXI SRAM else user remap will be done in FLASH BANK2. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif /* VECT_TAB_SRAM */ +#else +/*!< Uncomment the following line if you need to relocate your vector Table + in D1 AXI SRAM else user remap will be done in FLASH BANK1. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x400. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x400. */ +#endif /* VECT_TAB_SRAM */ +#endif /* DUAL_CORE && CORE_CM4 */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ +#if defined (DATA_IN_D2_SRAM) + __IO uint32_t tmpreg; +#endif /* DATA_IN_D2_SRAM */ + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + + /* Increasing the CPU frequency */ + if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Decreasing the number of wait states because of lower CPU frequency */ + if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + +#if defined(D3_SRAM_BASE) + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; +#else + /* Reset CDCFGR1 register */ + RCC->CDCFGR1 = 0x00000000; + + /* Reset CDCFGR2 register */ + RCC->CDCFGR2 = 0x00000000; + + /* Reset SRDCFGR register */ + RCC->SRDCFGR = 0x00000000; +#endif + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x02020200; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x01FF0000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + +#if (STM32H7_DEV_ID == 0x450UL) + /* dual core CM7 or single core line */ + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } +#endif /* STM32H7_DEV_ID */ + +#if defined(DATA_IN_D2_SRAM) + /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); +#elif defined(RCC_AHB2ENR_D2SRAM2EN) + RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); +#else + RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); +#endif /* RCC_AHB2ENR_D2SRAM3EN */ + + tmpreg = RCC->AHB2ENR; + (void) tmpreg; +#endif /* DATA_IN_D2_SRAM */ + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#else + /* + * Disable the FMC bank1 (enabled after reset). + * This, prevents CPU speculation access on this bank which blocks the use of FMC during + * 24us. During this time the others FMC master (such as LTDC) cannot use it! + */ + FMC_Bank1_R->BTCR[0] = 0x000030D2; + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#endif /*DUAL_CORE && CORE_CM4*/ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + uint32_t common_system_clock; + float_t fracn1, pllvco; + + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + common_system_clock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + common_system_clock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + common_system_clock = 0U; + } + break; + + default: + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ +#if defined (RCC_D1CFGR_D1CPRE) + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +#else + tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; + + /* common_system_clock frequency : CM7 CPU frequency */ + common_system_clock >>= tmp; + + /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Core/Src/tim.c b/FW/Core/Src/tim.c new file mode 100644 index 0000000..5651513 --- /dev/null +++ b/FW/Core/Src/tim.c @@ -0,0 +1,241 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2); + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + TIM_InitStruct.Prescaler = 249; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 254; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(TIM2, &TIM_InitStruct); + LL_TIM_DisableARRPreload(TIM2); + LL_TIM_OC_EnablePreload(TIM2, LL_TIM_CHANNEL_CH1); + TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM1; + TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.CompareValue = 0; + TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH; + LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct); + LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH1); + LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(TIM2); + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA); + /**TIM2 GPIO Configuration + PA15 (JTDI) ------> TIM2_CH1 + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_1; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + +} +/* TIM3 init function */ +void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3); + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + TIM_InitStruct.Prescaler = 699; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 254; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(TIM3, &TIM_InitStruct); + LL_TIM_DisableARRPreload(TIM3); + LL_TIM_OC_EnablePreload(TIM3, LL_TIM_CHANNEL_CH2); + TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM1; + TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.CompareValue = 0; + TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH; + LL_TIM_OC_Init(TIM3, LL_TIM_CHANNEL_CH2, &TIM_OC_InitStruct); + LL_TIM_OC_DisableFast(TIM3, LL_TIM_CHANNEL_CH2); + LL_TIM_SetTriggerOutput(TIM3, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(TIM3); + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB); + /**TIM3 GPIO Configuration + PB5 ------> TIM3_CH2 + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_2; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +} +/* TIM6 init function */ +void MX_TIM6_Init(void) +{ + + /* USER CODE BEGIN TIM6_Init 0 */ + + /* USER CODE END TIM6_Init 0 */ + + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); + + /* USER CODE BEGIN TIM6_Init 1 */ + + /* USER CODE END TIM6_Init 1 */ + TIM_InitStruct.Prescaler = 23; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 65535; + LL_TIM_Init(TIM6, &TIM_InitStruct); + LL_TIM_DisableARRPreload(TIM6); + LL_TIM_SetOnePulseMode(TIM6, LL_TIM_ONEPULSEMODE_SINGLE); + LL_TIM_SetTriggerOutput(TIM6, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(TIM6); + /* USER CODE BEGIN TIM6_Init 2 */ + + /* USER CODE END TIM6_Init 2 */ + +} +/* TIM7 init function */ +void MX_TIM7_Init(void) +{ + + /* USER CODE BEGIN TIM7_Init 0 */ + + /* USER CODE END TIM7_Init 0 */ + + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); + + /* TIM7 interrupt Init */ + NVIC_SetPriority(TIM7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(TIM7_IRQn); + + /* USER CODE BEGIN TIM7_Init 1 */ + + /* USER CODE END TIM7_Init 1 */ + TIM_InitStruct.Prescaler = 23; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 65535; + LL_TIM_Init(TIM7, &TIM_InitStruct); + LL_TIM_DisableARRPreload(TIM7); + LL_TIM_SetTriggerOutput(TIM7, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(TIM7); + /* USER CODE BEGIN TIM7_Init 2 */ + + /* USER CODE END TIM7_Init 2 */ + +} +/* TIM12 init function */ +void MX_TIM12_Init(void) +{ + + /* USER CODE BEGIN TIM12_Init 0 */ + + /* USER CODE END TIM12_Init 0 */ + + LL_TIM_InitTypeDef TIM_InitStruct = {0}; + LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM12); + + /* USER CODE BEGIN TIM12_Init 1 */ + + /* USER CODE END TIM12_Init 1 */ + TIM_InitStruct.Prescaler = 249; + TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct.Autoreload = 254; + TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + LL_TIM_Init(TIM12, &TIM_InitStruct); + LL_TIM_DisableARRPreload(TIM12); + LL_TIM_OC_EnablePreload(TIM12, LL_TIM_CHANNEL_CH1); + TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM1; + TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct.CompareValue = 0; + TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH; + LL_TIM_OC_Init(TIM12, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct); + LL_TIM_OC_DisableFast(TIM12, LL_TIM_CHANNEL_CH1); + LL_TIM_SetTriggerOutput(TIM12, LL_TIM_TRGO_RESET); + LL_TIM_DisableMasterSlaveMode(TIM12); + /* USER CODE BEGIN TIM12_Init 2 */ + + /* USER CODE END TIM12_Init 2 */ + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOH); + /**TIM12 GPIO Configuration + PH6 ------> TIM12_CH1 + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_2; + LL_GPIO_Init(GPIOH, &GPIO_InitStruct); + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/Src/usart.c b/FW/Core/Src/usart.c new file mode 100644 index 0000000..86afa3e --- /dev/null +++ b/FW/Core/Src/usart.c @@ -0,0 +1,733 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* LPUART1 init function */ + +void MX_LPUART1_UART_Init(void) +{ + + /* USER CODE BEGIN LPUART1_Init 0 */ + + /* USER CODE END LPUART1_Init 0 */ + + LL_LPUART_InitTypeDef LPUART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_D3PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_LPUART1); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB); + /**LPUART1 GPIO Configuration + PA9 ------> LPUART1_TX + PB7 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_3; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* LPUART1 interrupt Init */ + NVIC_SetPriority(LPUART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(LPUART1_IRQn); + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + LPUART_InitStruct.PrescalerValue = LL_LPUART_PRESCALER_DIV1; + LPUART_InitStruct.BaudRate = 57600; + LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B; + LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1; + LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE; + LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX; + LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; + LL_LPUART_Init(LPUART1, &LPUART_InitStruct); + LL_LPUART_SetTXFIFOThreshold(LPUART1, LL_LPUART_FIFOTHRESHOLD_1_8); + LL_LPUART_SetRXFIFOThreshold(LPUART1, LL_LPUART_FIFOTHRESHOLD_1_8); + LL_LPUART_EnableFIFO(LPUART1); + LL_LPUART_SetRXPinLevel(LPUART1, LL_LPUART_RXPIN_LEVEL_INVERTED); + LL_LPUART_SetTXPinLevel(LPUART1, LL_LPUART_TXPIN_LEVEL_INVERTED); + + /* USER CODE BEGIN WKUPType LPUART1 */ + + /* USER CODE END WKUPType LPUART1 */ + + LL_LPUART_Enable(LPUART1); + + /* Polling LPUART1 initialisation */ + while((!(LL_LPUART_IsActiveFlag_TEACK(LPUART1))) || (!(LL_LPUART_IsActiveFlag_REACK(LPUART1)))) + { + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ + +} +/* UART4 init function */ +void MX_UART4_Init(void) +{ + + /* USER CODE BEGIN UART4_Init 0 */ + + /* USER CODE END UART4_Init 0 */ + + LL_USART_InitTypeDef UART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART4; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART4); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC); + /**UART4 GPIO Configuration + PA0 ------> UART4_TX + PC11 ------> UART4_RX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* UART4 interrupt Init */ + NVIC_SetPriority(UART4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(UART4_IRQn); + + /* USER CODE BEGIN UART4_Init 1 */ + + /* USER CODE END UART4_Init 1 */ + UART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + UART_InitStruct.BaudRate = 19200; + UART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + UART_InitStruct.StopBits = LL_USART_STOPBITS_1; + UART_InitStruct.Parity = LL_USART_PARITY_NONE; + UART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + UART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + UART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(UART4, &UART_InitStruct); + LL_USART_EnableFIFO(UART4); + LL_USART_SetTXFIFOThreshold(UART4, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(UART4, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_ConfigAsyncMode(UART4); + + /* USER CODE BEGIN WKUPType UART4 */ + + /* USER CODE END WKUPType UART4 */ + + LL_USART_Enable(UART4); + + /* Polling UART4 initialisation */ + while((!(LL_USART_IsActiveFlag_TEACK(UART4))) || (!(LL_USART_IsActiveFlag_REACK(UART4)))) + { + } + /* USER CODE BEGIN UART4_Init 2 */ + + /* USER CODE END UART4_Init 2 */ + +} +/* UART5 init function */ +void MX_UART5_Init(void) +{ + + /* USER CODE BEGIN UART5_Init 0 */ + + /* USER CODE END UART5_Init 0 */ + + LL_USART_InitTypeDef UART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART5; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART5); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD); + /**UART5 GPIO Configuration + PC12 ------> UART5_TX + PD2 ------> UART5_RX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_12; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_2; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_8; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* UART5 interrupt Init */ + NVIC_SetPriority(UART5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(UART5_IRQn); + + /* USER CODE BEGIN UART5_Init 1 */ + + /* USER CODE END UART5_Init 1 */ + UART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + UART_InitStruct.BaudRate = 57600; + UART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + UART_InitStruct.StopBits = LL_USART_STOPBITS_1; + UART_InitStruct.Parity = LL_USART_PARITY_NONE; + UART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + UART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + UART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(UART5, &UART_InitStruct); + LL_USART_EnableFIFO(UART5); + LL_USART_SetTXFIFOThreshold(UART5, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(UART5, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_ConfigAsyncMode(UART5); + + /* USER CODE BEGIN WKUPType UART5 */ + + /* USER CODE END WKUPType UART5 */ + + LL_USART_Enable(UART5); + + /* Polling UART5 initialisation */ + while((!(LL_USART_IsActiveFlag_TEACK(UART5))) || (!(LL_USART_IsActiveFlag_REACK(UART5)))) + { + } + /* USER CODE BEGIN UART5_Init 2 */ + + /* USER CODE END UART5_Init 2 */ + +} +/* UART7 init function */ +void MX_UART7_Init(void) +{ + + /* USER CODE BEGIN UART7_Init 0 */ + + /* USER CODE END UART7_Init 0 */ + + LL_USART_InitTypeDef UART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART7; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_UART7); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB); + /**UART7 GPIO Configuration + PB3 (JTDO/TRACESWO) ------> UART7_RX + PB4 (NJTRST) ------> UART7_TX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_3|LL_GPIO_PIN_4; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_11; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* UART7 interrupt Init */ + NVIC_SetPriority(UART7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(UART7_IRQn); + + /* USER CODE BEGIN UART7_Init 1 */ + + /* USER CODE END UART7_Init 1 */ + UART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + UART_InitStruct.BaudRate = 57600; + UART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + UART_InitStruct.StopBits = LL_USART_STOPBITS_1; + UART_InitStruct.Parity = LL_USART_PARITY_NONE; + UART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + UART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + UART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(UART7, &UART_InitStruct); + LL_USART_EnableFIFO(UART7); + LL_USART_SetTXFIFOThreshold(UART7, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(UART7, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_ConfigAsyncMode(UART7); + + /* USER CODE BEGIN WKUPType UART7 */ + + /* USER CODE END WKUPType UART7 */ + + LL_USART_Enable(UART7); + + /* Polling UART7 initialisation */ + while((!(LL_USART_IsActiveFlag_TEACK(UART7))) || (!(LL_USART_IsActiveFlag_REACK(UART7)))) + { + } + /* USER CODE BEGIN UART7_Init 2 */ + + /* USER CODE END UART7_Init 2 */ + +} +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + LL_USART_InitTypeDef USART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB); + /**USART1 GPIO Configuration + PB14 ------> USART1_TX + PB15 ------> USART1_RX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_4; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_15; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_4; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USART1 interrupt Init */ + NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(USART1_IRQn); + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct.BaudRate = 115200; + USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + USART_InitStruct.Parity = LL_USART_PARITY_NONE; + USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(USART1, &USART_InitStruct); + LL_USART_SetTXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(USART1, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_EnableFIFO(USART1); + LL_USART_ConfigAsyncMode(USART1); + + /* USER CODE BEGIN WKUPType USART1 */ + + /* USER CODE END WKUPType USART1 */ + + LL_USART_Enable(USART1); + + /* Polling USART1 initialisation */ + while((!(LL_USART_IsActiveFlag_TEACK(USART1))) || (!(LL_USART_IsActiveFlag_REACK(USART1)))) + { + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} +/* USART2 init function */ + +void MX_USART2_UART_Init(void) +{ + + /* USER CODE BEGIN USART2_Init 0 */ + + /* USER CODE END USART2_Init 0 */ + + LL_USART_InitTypeDef USART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD); + /**USART2 GPIO Configuration + PD4 ------> USART2_DE + PD5 ------> USART2_TX + PD6 ------> USART2_RX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_4|LL_GPIO_PIN_5; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_6; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USART2 interrupt Init */ + NVIC_SetPriority(USART2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(USART2_IRQn); + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct.BaudRate = 19200; + USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + USART_InitStruct.Parity = LL_USART_PARITY_NONE; + USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(USART2, &USART_InitStruct); + LL_USART_SetTXFIFOThreshold(USART2, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(USART2, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_EnableDEMode(USART2); + LL_USART_SetDESignalPolarity(USART2, LL_USART_DE_POLARITY_HIGH); + LL_USART_SetDEAssertionTime(USART2, 8); + LL_USART_SetDEDeassertionTime(USART2, 8); + LL_USART_EnableFIFO(USART2); + LL_USART_ConfigAsyncMode(USART2); + + /* USER CODE BEGIN WKUPType USART2 */ + + /* USER CODE END WKUPType USART2 */ + + LL_USART_Enable(USART2); + + /* Polling USART2 initialisation */ + while((!(LL_USART_IsActiveFlag_TEACK(USART2))) || (!(LL_USART_IsActiveFlag_REACK(USART2)))) + { + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} +/* USART3 init function */ + +void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + LL_USART_InitTypeDef USART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART3); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC); + /**USART3 GPIO Configuration + PB11 ------> USART3_RX + PC10 ------> USART3_TX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_11; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /* USART3 DMA Init */ + + /* USART3_RX Init */ + LL_DMA_SetPeriphRequest(DMA2, LL_DMA_STREAM_3, LL_DMAMUX1_REQ_USART3_RX); + + LL_DMA_SetDataTransferDirection(DMA2, LL_DMA_STREAM_3, LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + + LL_DMA_SetStreamPriorityLevel(DMA2, LL_DMA_STREAM_3, LL_DMA_PRIORITY_LOW); + + LL_DMA_SetMode(DMA2, LL_DMA_STREAM_3, LL_DMA_MODE_NORMAL); + + LL_DMA_SetPeriphIncMode(DMA2, LL_DMA_STREAM_3, LL_DMA_PERIPH_NOINCREMENT); + + LL_DMA_SetMemoryIncMode(DMA2, LL_DMA_STREAM_3, LL_DMA_MEMORY_INCREMENT); + + LL_DMA_SetPeriphSize(DMA2, LL_DMA_STREAM_3, LL_DMA_PDATAALIGN_BYTE); + + LL_DMA_SetMemorySize(DMA2, LL_DMA_STREAM_3, LL_DMA_MDATAALIGN_BYTE); + + LL_DMA_DisableFifoMode(DMA2, LL_DMA_STREAM_3); + + /* USART3_TX Init */ + LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_3, LL_DMAMUX1_REQ_USART3_TX); + + LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_STREAM_3, LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + + LL_DMA_SetStreamPriorityLevel(DMA1, LL_DMA_STREAM_3, LL_DMA_PRIORITY_LOW); + + LL_DMA_SetMode(DMA1, LL_DMA_STREAM_3, LL_DMA_MODE_NORMAL); + + LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_STREAM_3, LL_DMA_PERIPH_NOINCREMENT); + + LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_STREAM_3, LL_DMA_MEMORY_INCREMENT); + + LL_DMA_SetPeriphSize(DMA1, LL_DMA_STREAM_3, LL_DMA_PDATAALIGN_BYTE); + + LL_DMA_SetMemorySize(DMA1, LL_DMA_STREAM_3, LL_DMA_MDATAALIGN_BYTE); + + LL_DMA_DisableFifoMode(DMA1, LL_DMA_STREAM_3); + + /* USART3 interrupt Init */ + NVIC_SetPriority(USART3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(USART3_IRQn); + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct.BaudRate = 57600; + USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + USART_InitStruct.Parity = LL_USART_PARITY_NONE; + USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(USART3, &USART_InitStruct); + LL_USART_SetTXFIFOThreshold(USART3, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(USART3, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_EnableFIFO(USART3); + LL_USART_ConfigAsyncMode(USART3); + + /* USER CODE BEGIN WKUPType USART3 */ + + /* USER CODE END WKUPType USART3 */ + + LL_USART_Enable(USART3); + + /* Polling USART3 initialisation */ + while((!(LL_USART_IsActiveFlag_TEACK(USART3))) || (!(LL_USART_IsActiveFlag_REACK(USART3)))) + { + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} +/* USART6 init function */ + +void MX_USART6_UART_Init(void) +{ + + /* USER CODE BEGIN USART6_Init 0 */ + + /* USER CODE END USART6_Init 0 */ + + LL_USART_InitTypeDef USART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART6; + PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART6); + + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC); + LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG); + /**USART6 GPIO Configuration + PC7 ------> USART6_RX + PG14 ------> USART6_TX + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_7; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_14; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_7; + LL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USART6 interrupt Init */ + NVIC_SetPriority(USART6_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0)); + NVIC_EnableIRQ(USART6_IRQn); + + /* USER CODE BEGIN USART6_Init 1 */ + + /* USER CODE END USART6_Init 1 */ + USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct.BaudRate = 9600; + USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct.StopBits = LL_USART_STOPBITS_1; + USART_InitStruct.Parity = LL_USART_PARITY_NONE; + USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16; + LL_USART_Init(USART6, &USART_InitStruct); + LL_USART_SetTXFIFOThreshold(USART6, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_SetRXFIFOThreshold(USART6, LL_USART_FIFOTHRESHOLD_1_8); + LL_USART_EnableFIFO(USART6); + LL_USART_ConfigAsyncMode(USART6); + + /* USER CODE BEGIN WKUPType USART6 */ + + /* USER CODE END WKUPType USART6 */ + + LL_USART_Enable(USART6); + + /* Polling USART6 initialisation */ + while((!(LL_USART_IsActiveFlag_TEACK(USART6))) || (!(LL_USART_IsActiveFlag_REACK(USART6)))) + { + } + /* USER CODE BEGIN USART6_Init 2 */ + + /* USER CODE END USART6_Init 2 */ + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/FW/Core/my_src/HW_config.c b/FW/Core/my_src/HW_config.c new file mode 100644 index 0000000..aac3beb --- /dev/null +++ b/FW/Core/my_src/HW_config.c @@ -0,0 +1,709 @@ +#include "main.h" +#include "fdcan.h" +#include "fdcan_task.h" +#include "HW_Config.h" +#include "W25Qxx.h" +#include "internal_flash.h" +#include "user_norflash.h" +#include "load_gui_lib.h" +#include "uart_printer_drv.h" + +#define USER_UART_NUM 8 + +extern void MX_FDCAN2_Init(void); + +uid_union uid_value; + +uart_info_8bit_struct uart_info_8bit[USER_UART_NUM]; +//LPUART1--eth 57600,USART1--wifi 115200,USART2--fecbus 9600,USART3--canouter 57600,UART4--linkage 19200,UART5--memory 57600,USART6--print 9600,UART7--switch 57600 +unsigned char * const p_user_uart[USER_UART_NUM] = {LPUART1,USART1,USART2,USART3,UART4,UART5,USART6,UART7}; +const unsigned int uart_tx_complete_timeup[USER_UART_NUM] = {3,17,17,3,9,3,20,3};//1ms 16bytes FIFO + +unsigned int lcd_update_flag = 0; +unsigned int usb_is_host = 0; + +//unsigned char TEXT_Buffer[]={"ABC12365478903678913"}; +#define SIZE sizeof(TEXT_Buffer) + +/** + * @brief Perform the SDRAM exernal memory inialization sequence + * @param hsdram: SDRAM handle + * @param Command: Pointer to SDRAM command structure + * @retval None + */ +/** + * @brief Perform the SDRAM exernal memory inialization sequence + * @param hsdram: SDRAM handle + * @param Command: Pointer to SDRAM command structure + * @retval None + */ +void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command) +{ + __IO uint32_t tmpmrd =0; + /* Step 1: Configure a clock configuration enable command */ + Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command->AutoRefreshNumber = 1; + Command->ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT); + + /* Step 2: Insert 100 us minimum delay */ + /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ + HAL_Delay(1); + + /* Step 3: Configure a PALL (precharge all) command */ + Command->CommandMode = FMC_SDRAM_CMD_PALL; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command->AutoRefreshNumber = 1; + Command->ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT); + + /* Step 4 : Configure a Auto-Refresh command */ + Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command->AutoRefreshNumber = 8; + Command->ModeRegisterDefinition = 0; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT); + + /* Step 5: Program the external memory mode register */ + tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_3 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; + Command->AutoRefreshNumber = 1; + Command->ModeRegisterDefinition = tmpmrd; + + /* Send the command */ + HAL_SDRAM_SendCommand(hsdram, Command, SDRAM_TIMEOUT); + + /* Step 6: Set the refresh rate counter */ + /* Set the device refresh rate */ + HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT); + +} + +void FDCAN2_Initialization_Sequence(void) +{ + FDCAN_FilterTypeDef sFilterConfig; + + /*##-2- Configure the CAN Filter ###########################################*/ + /* Configure Rx filter */ + sFilterConfig.IdType = FDCAN_EXTENDED_ID; + sFilterConfig.FilterIndex = 0; + sFilterConfig.FilterType = FDCAN_FILTER_MASK; + sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + sFilterConfig.FilterID1 = 0x0000; + sFilterConfig.FilterID2 = 0x0000; + + if(HAL_FDCAN_ConfigFilter(&hfdcan2, &sFilterConfig) != HAL_OK) + { + /* Filter configuration Error */ + Error_Handler(); + } + //HAL_FDCAN_Stop(p_fdcan_handle); + /*##-3- Start the CAN peripheral ###########################################*/ + if (HAL_FDCAN_Start(&hfdcan2) != HAL_OK) + { + /* Start Error */ + //Error_Handler(); + HAL_Delay(100); + HAL_FDCAN_Start(&hfdcan2); + } + + /*##-4- Activate CAN RX TX notification #######################################*/ + if (HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0) != HAL_OK) + { + /* Notification Error */ + Error_Handler(); + } + + if (HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_TX_FIFO_EMPTY, 0) != HAL_OK) + { + Error_Handler(); + } +} + +unsigned int FDCAN2_Reinit(void) +{ + FDCAN_FilterTypeDef sFilterConfig; + + MX_FDCAN2_Init(); + + sFilterConfig.IdType = FDCAN_EXTENDED_ID; + sFilterConfig.FilterIndex = 0; + sFilterConfig.FilterType = FDCAN_FILTER_MASK; + sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + sFilterConfig.FilterID1 = 0x0000; + sFilterConfig.FilterID2 = 0x0000; + + if(HAL_FDCAN_ConfigFilter(&hfdcan2, &sFilterConfig) != HAL_OK)return 2; + HAL_FDCAN_Start(&hfdcan2); + HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0); + HAL_FDCAN_ActivateNotification(&hfdcan2, FDCAN_IT_TX_FIFO_EMPTY, 0); + return 0; +} + +void get_uuid(void) +{ + uid_value.val_32[0] = LL_GetUID_Word0(); + uid_value.val_32[1] = LL_GetUID_Word1(); + uid_value.val_32[2] = LL_GetUID_Word2(); +} + +unsigned short get_open_password(void) +{ + unsigned int pwd; + unsigned short res; + + pwd = uid_value.val_32[0]; + pwd^= uid_value.val_32[1]; + pwd^= uid_value.val_32[2]; + + res = (pwd>>16)&0xFFFF; + res^= (pwd&0xFFFF); + + return res; +} + +void HW_init(void) +{ + unsigned int addr = 0; + unsigned int zk_addr = 0; + unsigned int value = 0; + unsigned int i = 0,x = 0,y = 0, a = 0; + + get_uuid(); + factory_prm.pwr = get_open_password(); + read_factory_prm(); + + //LCD RST + LL_GPIO_SetOutputPin(GPIOE,LL_GPIO_PIN_3);//not rst + + //TIM2 relay + LL_TIM_CC_EnableChannel(TIM2,LL_TIM_CHANNEL_CH1); + LL_TIM_OC_SetCompareCH1(TIM2,0); + LL_TIM_EnableAllOutputs(TIM2); + //LL_TIM_EnableIT_UPDATE(TIM2); + LL_TIM_EnableCounter(TIM2); + + //TIM3 LCD_BL + LL_TIM_CC_EnableChannel(TIM3,LL_TIM_CHANNEL_CH2); + LL_TIM_OC_SetCompareCH2(TIM3,255);//bl + LL_TIM_EnableAllOutputs(TIM3); + LL_TIM_EnableCounter(TIM3); + + //TIM7 random + //LL_TIM_EnableIT_UPDATE(TIM7); + LL_TIM_EnableCounter(TIM7); + + //TIM12 relay + LL_TIM_CC_EnableChannel(TIM12,LL_TIM_CHANNEL_CH1); + LL_TIM_OC_SetCompareCH1(TIM12,0); + LL_TIM_EnableAllOutputs(TIM12); + //LL_TIM_EnableIT_UPDATE(TIM2); + LL_TIM_EnableCounter(TIM12); + + //LPUART1 + LL_USART_EnableIT_RXNE(LPUART1); + LL_USART_ClearFlag_IDLE(LPUART1); + //LL_USART_EnableIT_IDLE(LPUART1); + uart_info_8bit[0].tx_complete = 1; + + //UART1 + LL_USART_EnableIT_RXNE(USART1); + LL_USART_ClearFlag_IDLE(USART1); + LL_USART_EnableIT_IDLE(USART1); + uart_info_8bit[1].tx_complete = 1; + + //UART2 + LL_USART_EnableIT_RXNE(USART2); + LL_USART_ClearFlag_IDLE(USART2); + //LL_USART_EnableIT_IDLE(USART2); + uart_info_8bit[2].tx_complete = 1; + + //UART3 + LL_USART_EnableIT_RXNE(USART3); + LL_USART_ClearFlag_IDLE(USART3); + LL_USART_EnableIT_IDLE(USART3); + uart_info_8bit[3].tx_complete = 1; + + //UART4 + LL_USART_EnableIT_RXNE(UART4); + LL_USART_ClearFlag_IDLE(UART4); + //LL_USART_EnableIT_IDLE(UART4); + uart_info_8bit[4].tx_complete = 1; + + //UART5 + LL_USART_EnableIT_RXNE(UART5); + LL_USART_ClearFlag_IDLE(UART5); + LL_USART_EnableIT_IDLE(UART5); + uart_info_8bit[5].tx_complete = 1; + + //UART6 + LL_USART_EnableIT_RXNE(USART6); + uart_info_8bit[6].tx_complete = 1; + + //UART7 + LL_USART_EnableIT_RXNE(UART7); + LL_USART_ClearFlag_IDLE(UART7); + LL_USART_EnableIT_IDLE(UART7); + uart_info_8bit[7].tx_complete = 1; + + //fdcan2 + FDCAN2_Initialization_Sequence(); + can_prm_init(); + + //LTDC + LTDC_Init(); + //LTDC->IER |= LTDC_IER_LIE; + + //RTC + rtc_init(); + + //I2C + //write_user_eeprom(0, 0x1005, TEXT_Buffer, 16); + //write_user_eeprom(1, 0x10001, &TEXT_Buffer[1], 16); + + //USBFS + usb_is_host = 1; + + //QSPI-HW 24Mhz + nor_flash_init(); + //W25QXX_Init(); + //nor_erase_sector(0,0); + //nor_write_byte(0,0x403,TEXT_Buffer,16); + //nor_write_byte(1,0x207,TEXT_Buffer,16); + + //LCD + LTDC_Layer_Switch(1,0); + //LTDC_Layer_Switch(0,1); + addr = 0xC0000000 + 480*800*4; + for(y=0;y<480;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0; + addr+=4; + } + } + + pic_prm_init(); + + //device_init + printer_init(); + + //------------------------test----------------------------------------- + /* + for(i=0;i<480;i++){ + addr = 50*4 + 0xC0000000 + (800*i*4); + *(unsigned int*)addr = 0xFF00FF00; + } + */ + /* + addr = 0xC0177000 + (10*800*4); + for(y=0;y<10;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000080; + addr+=4; + } + } + addr = 0xC0177000 + (20*800*4); + for(y=0;y<10;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000040; + addr+=4; + } + } + addr = 0xC0177000 + (30*800*4); + for(y=0;y<10;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000020; + addr+=4; + } + } + addr = 0xC0177000 + (40*800*4); + for(y=0;y<10;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000010; + addr+=4; + } + } + */ + /* + LCD_ShowString(0,240,200,24,24,"SD"); + //while(1); + + //erase_internal_one_sector(ADDR_FLASH_SECTOR_6_BANK2); + //write_internal_flash(ADDR_FLASH_SECTOR_6_BANK2,FlashWord); + LCD_ShowString(20,200,200,24,24,"SD"); + Show_Str(20,100,720,24,"STM32H7开0123456789abcuodij发111板",24,0);// + gui_write_string24(20,130,0xFFFF0000,0xFF00FF00,"用户参845数SWEI设aw置"); + + load_pic_16x16_to_dispaly_layer(100,200,45); + load_pic_16x16_to_dispaly_layer(140,200,8); + load_pic_24x24_to_dispaly_layer(100,230,101); + load_pic_24x24_to_dispaly_layer(140,230,14); + load_pic_32x32_to_dispaly_layer(100,260,30); + load_pic_32x32_to_dispaly_layer(140,260,15); + */ + //nor_read_byte(0,0x009C0000,TEXT_Buffer,16); + + //hw_sdram_test(); + + gbk_nor_load_to_sdram(); +} + +void uart_tx_trigger(unsigned int uart_ord) +{ + if(uart_ord > 7)return; + + uart_info_8bit[uart_ord].tx_index = 0; + uart_info_8bit[uart_ord].tx_complete = 0; + uart_info_8bit[uart_ord].tx_complete_delay_flag = 0; + uart_info_8bit[uart_ord].tx_complete_delay_tick = 0; + uart_info_8bit[uart_ord].tx_none_buf = 0; + + LL_USART_ClearFlag_TC(p_user_uart[uart_ord]); + LL_USART_EnableIT_TC(p_user_uart[uart_ord]); + LL_USART_EnableIT_TXFE(p_user_uart[uart_ord]); +} + +void uart_tx_load_data(unsigned int uart_ord, unsigned char * p_data, unsigned int len) +{ + unsigned int i = 0; + unsigned char * pdata; + + if(uart_ord > 7)return; + + pdata = p_data; + + uart_info_8bit[uart_ord].tx_index = 0; + uart_info_8bit[uart_ord].tx_complete = 0; + uart_info_8bit[uart_ord].tx_none_buf = 0; + uart_info_8bit[uart_ord].tx_len = len; + + for(i=0;i 7)return 0; + + return uart_info_8bit[uart_ord].tx_complete; +} + +unsigned int get_uart_tx_complete_delay_flag(unsigned int uart_ord) +{ + if(uart_ord > 7)return 0; + + return uart_info_8bit[uart_ord].tx_complete_delay_flag; +} + +void uart_tx_complete_delay(void)//1ms +{ + unsigned int i; + for(i=0;i uart_tx_complete_timeup[i]){ + uart_info_8bit[i].tx_complete_delay_tick = 0; + uart_info_8bit[i].tx_complete_delay_flag = 1; + } + } + } + } +} + +void uart_tx_over(unsigned int uart_ord, unsigned char * p_data, unsigned int len) +{ + unsigned int i = 0; + unsigned char * pdata; + + if(uart_ord > 7)return; + + pdata = p_data; + + uart_info_8bit[uart_ord].tx_index = 0; + uart_info_8bit[uart_ord].tx_complete = 0; + uart_info_8bit[uart_ord].tx_complete_delay_flag = 0; + uart_info_8bit[uart_ord].tx_complete_delay_tick = 0; + uart_info_8bit[uart_ord].tx_none_buf = 0; + uart_info_8bit[uart_ord].tx_len = len; + + for(i=0;i 7)return; + + pdata = p_data; + + uart_info_8bit[uart_ord].tx_index = 0; + uart_info_8bit[uart_ord].tx_complete = 0; + uart_info_8bit[uart_ord].tx_complete_delay_flag = 0; + uart_info_8bit[uart_ord].tx_complete_delay_tick = 0; + uart_info_8bit[uart_ord].tx_none_buf = 0; + uart_info_8bit[uart_ord].tx_len = len; + + for(i=0;i= uart_info_8bit[i].tx_len) + { + LL_USART_DisableIT_TC(USARTx); + uart_info_8bit[i].tx_complete = 1; + } + } + + if(LL_USART_IsEnabledIT_TXE_TXFNF(USARTx))//LL_USART_IsActiveFlag_TXE_TXFNF + { + if(uart_info_8bit[i].tx_index >= uart_info_8bit[i].tx_len) + { + LL_USART_DisableIT_TXE_TXFNF(USARTx); + } + else + { + LL_USART_TransmitData8(USARTx, uart_info_8bit[i].tx_buf[uart_info_8bit[i].tx_index]); + uart_info_8bit[i].tx_index++; + } + } + //--------------------------------------------------------------------------- + LL_USART_ClearFlag_ORE(USARTx); +} + +unsigned short crc16_data(unsigned char* p_data,unsigned int data_length) +{ + unsigned int x = 0,y = 0; + unsigned short crc = 0xFFFF; + unsigned char data = 0; + + for(x=0;x>=1; + crc ^= 0xA001; + }else{ + crc>>=1; + } + } + p_data++; + } + return crc; +} + +unsigned int check_crc(unsigned char* p_data,unsigned int data_length) +{ + uint16_t crc_data = 0; + + if(data_length < 2)return 0; + + crc_data = *(p_data + data_length - 1); + crc_data<<=8; + crc_data |= *(p_data + data_length - 2); + + if(crc_data == crc16_data(p_data,(data_length - 2))){ + return 0; + } + return 1; +} + +unsigned char sum8_data(unsigned char* p_data,unsigned int data_length) +{ + unsigned int x = 0; + unsigned char sum = 0; + + for(x=0;x 1)return; + factory_prm.auth_function_isenable = able; + write_factory_prm(); +} + +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + lcd_update_flag = 1; + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); +} + +/******************************************************************************* +* Function Name : Crc32Cal +* Description : CRC +* Input : SourceData,Length +* Output : None +* Return : none +*******************************************************************************/ +unsigned int Crc32Cal(unsigned int * SourceData, unsigned int Length) +{ + unsigned int i; + + CRC->CR |= CRC_CR_RESET; + + for (i = 0; i < Length; ++i) + { + CRC->DR = *SourceData; + SourceData++; + } + return CRC->DR; +} + +void Crc32Reset(void) +{ + CRC->CR |= CRC_CR_RESET; +} + +void Crc32Feed(unsigned int aVal) +{ + CRC->DR = aVal; +} + +unsigned int Crc32GetResult() +{ + return CRC->DR; +} + +void usb_host_to_device(void) +{ + if(usb_is_host){ + MX_FATFS_DeInit(); + HAL_Delay(5); + HAL_NVIC_ClearPendingIRQ(OTG_FS_IRQn); + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + MX_USB_HOST_DeInit(); + HAL_Delay(10); + + MX_USB_DEVICE_Init(); + HAL_Delay(5); + + usb_is_host = 0; + + UsbConfigSetState(0); + } +} + +void usb_device_to_host(void) +{ + if(0 == usb_is_host){ + HAL_NVIC_ClearPendingIRQ(OTG_FS_IRQn); + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + MX_USB_DEVICE_DeInit(); + HAL_Delay(5); + + UsbConfigSetState(0); + + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + HAL_NVIC_ClearPendingIRQ(OTG_FS_IRQn); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + + MX_USB_HOST_Init(); + MX_FATFS_Init(); + HAL_Delay(5); + + usb_is_host = 1; + } +} diff --git a/FW/Core/my_src/HW_config.h b/FW/Core/my_src/HW_config.h new file mode 100644 index 0000000..a2dff53 --- /dev/null +++ b/FW/Core/my_src/HW_config.h @@ -0,0 +1,118 @@ +#ifndef HW_CONFIG_H_ +#define HW_CONFIG_H_ + +#include "main.h" + +#define UART_RX_BUF_MAX 512//272 +#define UART_TX_BUF_MAX 512//128 + +#define USB_CDC_BUF_MAX 272 + +typedef struct uart_def_8bit +{ + unsigned char rx_buf[UART_RX_BUF_MAX]; + unsigned short rx_len; + unsigned short rx_index; + unsigned short rx_complete; + unsigned short rsv; + + unsigned char tx_buf[UART_TX_BUF_MAX]; + unsigned short tx_len; + unsigned short tx_index; + unsigned short tx_none_buf; + unsigned short tx_complete; + unsigned short tx_complete_delay_flag; + unsigned short tx_complete_delay_tick; +}uart_info_8bit_struct; + +typedef struct +{ + unsigned char rx_buf[USB_CDC_BUF_MAX]; + unsigned int rx_len; + unsigned int rx_complete; + + unsigned char tx_buf[USB_CDC_BUF_MAX]; + unsigned int tx_len; + unsigned int tx_complete; + unsigned int tx_complete_delay_flag; + unsigned int tx_complete_delay_tick; +}T_usb_cdc_data_struct; + +typedef union{ + unsigned char D8[256]; + unsigned int D32[64]; +}TdataType; + +typedef union{ + uint32_t val_32[3]; + uint8_t val_8[12]; +}uid_union; + +/* Exported types ------------------------------------------------------------*/ +typedef enum {PASSED = 0, FAILED = !PASSED} TestStatus_t; +/* Exported constants --------------------------------------------------------*/ +#define SDRAM_BANK_ADDR ((uint32_t)0xC0000000) + +/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ +/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */ +#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32 + +#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 +/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ + +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) + +//刷新频率计数器(以SDCLK频率计数),计算方法: +//COUNT=SDRAM刷新周期/行数-20=SDRAM刷新周期(us)*SDCLK频率(Mhz)/行数 +//我们使用的SDRAM刷新周期为64ms,SDCLK=240/3=80Mhz,行数为8192(2^13). +//所以,COUNT=64*1000*80/8192-20=677 +#define REFRESH_COUNT ((uint32_t)625) /* SDRAM refresh counter */ + +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +extern uid_union uid_value; + +extern unsigned int usb_is_host; + +extern uart_info_8bit_struct uart_info_8bit[8]; +extern T_usb_cdc_data_struct usb_cdc_data; + +extern void uart_tx_trigger(unsigned int uart_ord); +extern void uart_tx_load_data(unsigned int uart_ord, unsigned char * p_data, unsigned int len); +extern unsigned int get_uart_tx_complete(unsigned int uart_ord); +extern unsigned int get_uart_tx_complete_delay_flag(unsigned int uart_ord); +extern void uart_tx_complete_delay(void); +extern void uart_tx_over(unsigned int uart_ord, unsigned char * p_data, unsigned int len); +extern void uart_load_txbuf(unsigned int uart_ord, unsigned char * p_data, unsigned int len); + +extern void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command); +extern void HW_init(void); + +extern unsigned int check_sum8(unsigned char* p_data,unsigned int data_length); + +extern unsigned int check_open_password(unsigned int check_value); +extern unsigned int check_open_password_isenable(void); +extern unsigned int check_auth_function_isenable(void); +extern void set_open_password_isover(void); +extern void set_auth_function_able(unsigned int able); + +extern void usb_host_to_device(void); +extern void usb_device_to_host(void); + +extern unsigned int Crc32Cal(unsigned int * SourceData, unsigned int Length); +extern void Crc32Reset(void); +extern void Crc32Feed(unsigned int aVal); +extern unsigned int Crc32GetResult(); + + +#endif diff --git a/FW/Core/my_src/HW_test_task.c b/FW/Core/my_src/HW_test_task.c new file mode 100644 index 0000000..b652622 --- /dev/null +++ b/FW/Core/my_src/HW_test_task.c @@ -0,0 +1,1094 @@ +#include "main.h" +#include "HW_config.h" +#include "user_eeprom.h" +#include "user_norflash.h" +#include "uart_printer_drv.h" + +unsigned char tx_text_buf[32]; +unsigned char rx_text_buf[32]; + +unsigned int hw_test_mode = 0; + +static void wait(void) +{ + __nop();__nop();__nop();__nop(); + __nop();__nop();__nop();__nop(); + __nop();__nop();__nop();__nop(); + __nop();__nop();__nop();__nop(); +} + +unsigned int hw_test_init(void) +{ + unsigned int i = 0; + + for(i=0;i<32;i+=2){ + tx_text_buf[i] = 0x55; + tx_text_buf[i+1] = 0xAA; + + rx_text_buf[i] = 0; + rx_text_buf[i+1] = 0; + } +} + +unsigned int hw_test_deinit(void) +{ + unsigned int i = 0; + + for(i=0;i<32;i++){ + tx_text_buf[i] = 0; + rx_text_buf[i] = 0; + } +} + +unsigned int hw_uart_test_all(void)//test uart1-7 +{ + unsigned int res = 0; + unsigned int i = 0; + unsigned char data[4] = {0}; + unsigned int test_tick = 0; + + HAL_Delay(50); + + while(0 == uart_info_8bit[1].tx_complete); + while(0 == uart_info_8bit[2].tx_complete); + while(0 == uart_info_8bit[3].tx_complete); + while(0 == uart_info_8bit[4].tx_complete); + while(0 == uart_info_8bit[5].tx_complete); + while(0 == uart_info_8bit[6].tx_complete); + while(0 == uart_info_8bit[7].tx_complete); + + //UART1 + LL_USART_DisableIT_RXNE(USART1); + LL_USART_ClearFlag_IDLE(USART1); + LL_USART_DisableIT_IDLE(USART1); + while(LL_USART_IsActiveFlag_RXNE(USART1)){ + data[0] = LL_USART_ReceiveData8(USART1); + } + + //UART2 + LL_USART_DisableIT_RXNE(USART2); + LL_USART_ClearFlag_IDLE(USART2); + LL_USART_DisableIT_IDLE(USART2); + while(LL_USART_IsActiveFlag_RXNE(USART2)){ + data[0] = LL_USART_ReceiveData8(USART2); + } + + //UART3 + LL_USART_DisableIT_RXNE(USART3); + LL_USART_ClearFlag_IDLE(USART3); + LL_USART_DisableIT_IDLE(USART3); + while(LL_USART_IsActiveFlag_RXNE(USART3)){ + data[0] = LL_USART_ReceiveData8(USART3); + } + + //UART4 + LL_USART_DisableIT_RXNE(UART4); + LL_USART_ClearFlag_IDLE(UART4); + LL_USART_DisableIT_IDLE(UART4); + while(LL_USART_IsActiveFlag_RXNE(UART4)){ + data[0] = LL_USART_ReceiveData8(UART4); + } + + //UART5 + LL_USART_DisableIT_RXNE(UART5); + LL_USART_ClearFlag_IDLE(UART5); + LL_USART_DisableIT_IDLE(UART5); + while(LL_USART_IsActiveFlag_RXNE(UART5)){ + data[0] = LL_USART_ReceiveData8(UART5); + } + + //UART6 + LL_USART_DisableIT_RXNE(USART6); + LL_USART_ClearFlag_IDLE(USART6); + LL_USART_DisableIT_IDLE(USART6); + while(LL_USART_IsActiveFlag_RXNE(USART6)){ + data[0] = LL_USART_ReceiveData8(USART6); + } + + //UART7 + LL_USART_DisableIT_RXNE(UART7); + LL_USART_ClearFlag_IDLE(UART7); + LL_USART_DisableIT_IDLE(UART7); + while(LL_USART_IsActiveFlag_RXNE(UART7)){ + data[0] = LL_USART_ReceiveData8(UART7); + } + + while(test_tick <= 7){ + test_tick++; + //--------------------------uart1------------------------------ + if(1 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + USART1->TDR = 0xAA; + USART1->TDR = 0x66; + USART1->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(USART1)){ + rx_text_buf[i] = LL_USART_ReceiveData8(USART1); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 1; + test_tick = 10; + } + }else + + //--------------------------uart2------------------------------ + if(2 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + USART2->TDR = 0xAA; + USART2->TDR = 0x66; + USART2->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(USART2)){ + rx_text_buf[i] = LL_USART_ReceiveData8(USART2); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 2; + test_tick = 10; + } + }else + + //--------------------------uart3------------------------------ + if(3 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + USART3->TDR = 0xAA; + USART3->TDR = 0x66; + USART3->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(USART3)){ + rx_text_buf[i] = LL_USART_ReceiveData8(USART3); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 3; + test_tick = 10; + } + }else + + //--------------------------uart4------------------------------ + if(4 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + UART4->TDR = 0xAA; + UART4->TDR = 0x66; + UART4->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(UART4)){ + rx_text_buf[i] = LL_USART_ReceiveData8(UART4); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 4; + test_tick = 10; + } + }else + + //--------------------------uart5------------------------------ + if(5 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + UART5->TDR = 0xAA; + UART5->TDR = 0x66; + UART5->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(UART5)){ + rx_text_buf[i] = LL_USART_ReceiveData8(UART5); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 5; + test_tick = 10; + } + }else + + //--------------------------uart6------------------------------ + if(6 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + USART6->TDR = 0xAA; + USART6->TDR = 0x66; + USART6->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(USART6)){ + rx_text_buf[i] = LL_USART_ReceiveData8(USART6); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 6; + test_tick = 10; + } + }else + + //--------------------------uart7------------------------------ + if(7 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + UART7->TDR = 0xAA; + UART7->TDR = 0x66; + UART7->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(UART7)){ + rx_text_buf[i] = LL_USART_ReceiveData8(UART7); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 7; + test_tick = 10; + } + } + } + //----------------------------------end-------------------------------------------------------- + + //UART1 + LL_USART_EnableIT_RXNE(USART1); + LL_USART_ClearFlag_IDLE(USART1); + LL_USART_EnableIT_IDLE(USART1); + uart_info_8bit[1].tx_complete = 1; + + //UART2 + LL_USART_EnableIT_RXNE(USART2); + LL_USART_ClearFlag_IDLE(USART2); + //LL_USART_EnableIT_IDLE(USART2); + uart_info_8bit[2].tx_complete = 1; + + //UART3 + LL_USART_EnableIT_RXNE(USART3); + LL_USART_ClearFlag_IDLE(USART3); + LL_USART_EnableIT_IDLE(USART3); + uart_info_8bit[3].tx_complete = 1; + + //UART4 + LL_USART_EnableIT_RXNE(UART4); + LL_USART_ClearFlag_IDLE(UART4); + //LL_USART_EnableIT_IDLE(UART4); + uart_info_8bit[4].tx_complete = 1; + + //UART5 + LL_USART_EnableIT_RXNE(UART5); + LL_USART_ClearFlag_IDLE(UART5); + LL_USART_EnableIT_IDLE(UART5); + uart_info_8bit[5].tx_complete = 1; + + //UART6 + LL_USART_EnableIT_RXNE(USART6); + uart_info_8bit[6].tx_complete = 1; + + //UART7 + LL_USART_EnableIT_RXNE(UART7); + LL_USART_ClearFlag_IDLE(UART7); + LL_USART_EnableIT_IDLE(UART7); + uart_info_8bit[7].tx_complete = 1; + + return res; +} + +unsigned int hw_uart_test(void)//test uart1-5 7 +{ + unsigned int res = 0; + unsigned int i = 0; + unsigned char data[4] = {0}; + unsigned int test_tick = 0; + + HAL_Delay(50); + + while(0 == uart_info_8bit[1].tx_complete); + while(0 == uart_info_8bit[2].tx_complete); + while(0 == uart_info_8bit[3].tx_complete); + while(0 == uart_info_8bit[4].tx_complete); + while(0 == uart_info_8bit[5].tx_complete); + while(0 == uart_info_8bit[7].tx_complete); + + //UART1 + LL_USART_DisableIT_RXNE(USART1); + LL_USART_ClearFlag_IDLE(USART1); + LL_USART_DisableIT_IDLE(USART1); + while(LL_USART_IsActiveFlag_RXNE(USART1)){ + data[0] = LL_USART_ReceiveData8(USART1); + } + + //UART2 + LL_USART_DisableIT_RXNE(USART2); + LL_USART_ClearFlag_IDLE(USART2); + LL_USART_DisableIT_IDLE(USART2); + while(LL_USART_IsActiveFlag_RXNE(USART2)){ + data[0] = LL_USART_ReceiveData8(USART2); + } + + //UART3 + LL_USART_DisableIT_RXNE(USART3); + LL_USART_ClearFlag_IDLE(USART3); + LL_USART_DisableIT_IDLE(USART3); + while(LL_USART_IsActiveFlag_RXNE(USART3)){ + data[0] = LL_USART_ReceiveData8(USART3); + } + + //UART4 + LL_USART_DisableIT_RXNE(UART4); + LL_USART_ClearFlag_IDLE(UART4); + LL_USART_DisableIT_IDLE(UART4); + while(LL_USART_IsActiveFlag_RXNE(UART4)){ + data[0] = LL_USART_ReceiveData8(UART4); + } + + //UART5 + LL_USART_DisableIT_RXNE(UART5); + LL_USART_ClearFlag_IDLE(UART5); + LL_USART_DisableIT_IDLE(UART5); + while(LL_USART_IsActiveFlag_RXNE(UART5)){ + data[0] = LL_USART_ReceiveData8(UART5); + } + + //UART7 + LL_USART_DisableIT_RXNE(UART7); + LL_USART_ClearFlag_IDLE(UART7); + LL_USART_DisableIT_IDLE(UART7); + while(LL_USART_IsActiveFlag_RXNE(UART7)){ + data[0] = LL_USART_ReceiveData8(UART7); + } + + while(test_tick <= 7){ + test_tick++; + //--------------------------uart1------------------------------ + if(1 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + USART1->TDR = 0xAA; + USART1->TDR = 0x66; + USART1->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(USART1)){ + rx_text_buf[i] = LL_USART_ReceiveData8(USART1); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 1; + test_tick = 10; + } + }else + + //--------------------------uart2------------------------------ + if(2 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + USART2->TDR = 0xAA; + USART2->TDR = 0x66; + USART2->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(USART2)){ + rx_text_buf[i] = LL_USART_ReceiveData8(USART2); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 2; + test_tick = 10; + } + }else + + //--------------------------uart3------------------------------ + if(3 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + USART3->TDR = 0xAA; + USART3->TDR = 0x66; + USART3->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(USART3)){ + rx_text_buf[i] = LL_USART_ReceiveData8(USART3); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 3; + test_tick = 10; + } + }else + + //--------------------------uart4------------------------------ + if(4 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + UART4->TDR = 0xAA; + UART4->TDR = 0x66; + UART4->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(UART4)){ + rx_text_buf[i] = LL_USART_ReceiveData8(UART4); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 4; + test_tick = 10; + } + }else + + //--------------------------uart5------------------------------ + if(5 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + UART5->TDR = 0xAA; + UART5->TDR = 0x66; + UART5->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(UART5)){ + rx_text_buf[i] = LL_USART_ReceiveData8(UART5); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 5; + test_tick = 10; + } + }else + + //--------------------------uart7------------------------------ + if(7 == test_tick){ + rx_text_buf[0] = 0; + rx_text_buf[1] = 0; + rx_text_buf[2] = 0; + wait(); + UART7->TDR = 0xAA; + UART7->TDR = 0x66; + UART7->TDR = 0x55; + i=0; + HAL_Delay(5); + while(LL_USART_IsActiveFlag_RXNE(UART7)){ + rx_text_buf[i] = LL_USART_ReceiveData8(UART7); + i++; + if(i>3)i=3; + } + if((0xAA != rx_text_buf[0])||(0x66 != rx_text_buf[1])||(0x55 != rx_text_buf[2])){ + res = 7; + test_tick = 10; + } + } + } + //----------------------------------end-------------------------------------------------------- + + //UART1 + LL_USART_EnableIT_RXNE(USART1); + LL_USART_ClearFlag_IDLE(USART1); + LL_USART_EnableIT_IDLE(USART1); + uart_info_8bit[1].tx_complete = 1; + + //UART2 + LL_USART_EnableIT_RXNE(USART2); + LL_USART_ClearFlag_IDLE(USART2); + //LL_USART_EnableIT_IDLE(USART2); + uart_info_8bit[2].tx_complete = 1; + + //UART3 + LL_USART_EnableIT_RXNE(USART3); + LL_USART_ClearFlag_IDLE(USART3); + LL_USART_EnableIT_IDLE(USART3); + uart_info_8bit[3].tx_complete = 1; + + //UART4 + LL_USART_EnableIT_RXNE(UART4); + LL_USART_ClearFlag_IDLE(UART4); + //LL_USART_EnableIT_IDLE(UART4); + uart_info_8bit[4].tx_complete = 1; + + //UART5 + LL_USART_EnableIT_RXNE(UART5); + LL_USART_ClearFlag_IDLE(UART5); + LL_USART_EnableIT_IDLE(UART5); + uart_info_8bit[5].tx_complete = 1; + + //UART7 + LL_USART_EnableIT_RXNE(UART7); + LL_USART_ClearFlag_IDLE(UART7); + LL_USART_EnableIT_IDLE(UART7); + uart_info_8bit[7].tx_complete = 1; + + return res; +} + +unsigned int hw_eeprom_test(void) +{ + unsigned int i = 0; + unsigned int addr = 0x1505; + + unsigned int res = 0; + + eeprom_write_byte_via_page(0, addr, &tx_text_buf[0], 16); + HAL_Delay(5); + + eeprom_write_byte_via_page(1, addr, &tx_text_buf[1], 16); + HAL_Delay(5); + + eeprom_read_byte(0, addr, rx_text_buf, 16); + for(i=0;i<16;i+=2){ + if(0x55 != rx_text_buf[i])res = 1; + if(0xAA != rx_text_buf[i+1])res = 1; + } + + eeprom_read_byte(1, addr, rx_text_buf, 16); + for(i=0;i<16;i+=2){ + if(0xAA != rx_text_buf[i])res = 1; + if(0x55 != rx_text_buf[i+1])res = 1; + } + + return res; +} + +unsigned int hw_nor_flash_test(void) +{ + unsigned int i = 0; + unsigned int nor_sate = 0; + unsigned int addr = 0x1000; + + unsigned int res = 0; + + //------------------------pcs 0--------------------------------------- + nor_erase_sector_4k(0,addr); + do{ + HAL_Delay(5); + nor_sate = nor_get_busy_state(0); + }while(nor_sate); + + nor_write_byte_via_page(0,addr,&tx_text_buf[0],16); + do{ + HAL_Delay(5); + nor_sate = nor_get_busy_state(0); + }while(nor_sate); + + nor_read_byte(0,addr,rx_text_buf,16); + for(i=0;i<16;i+=2){ + if(0x55 != rx_text_buf[i])res = 1; + if(0xAA != rx_text_buf[i+1])res = 1; + } + + //------------------------pcs 1--------------------------------------- + nor_erase_sector_4k(1,addr); + do{ + HAL_Delay(5); + nor_sate = nor_get_busy_state(1); + }while(nor_sate); + + nor_write_byte_via_page(1,addr,&tx_text_buf[1],16); + do{ + HAL_Delay(5); + nor_sate = nor_get_busy_state(1); + }while(nor_sate); + + nor_read_byte(1,addr,rx_text_buf,16); + for(i=0;i<16;i+=2){ + if(0xAA != rx_text_buf[i])res = 1; + if(0x55 != rx_text_buf[i+1])res = 1; + } + + return res; +} + +unsigned int hw_sdram_test(void) +{ + volatile unsigned int sdram_addr = 0xC0000000; + volatile unsigned int i = 0; + //volatile unsigned int value = 0; + volatile unsigned int res = 0; + unsigned int x = 0,y = 0; + + res = 0; + /* + for(i=0;i<0x04000000;i+=4){ + sdram_addr = 0xC0000000 + i; + + *(volatile unsigned int*)sdram_addr = 0x55555555; + wait();wait(); + //value = *(volatile unsigned int*)sdram_addr; + if((*(volatile unsigned int*)sdram_addr) != 0x55555555){ + res = 1; + break; + } + + *(volatile unsigned int*)sdram_addr = 0xAAAAAAAA; + wait();wait(); + //value = *(volatile unsigned int*)sdram_addr; + if((*(volatile unsigned int*)sdram_addr) != 0xAAAAAAAA){ + res = 1; + break; + } + } + */ + HAL_Delay(1); + for(i=0;i<0x04000000;i+=4){ + sdram_addr = 0xC0000000 + i; + + *(volatile unsigned int*)sdram_addr = 0x55555555; + wait(); + } + LL_IWDG_ReloadCounter(IWDG1); + HAL_Delay(3); + for(i=0;i<0x04000000;i+=4){ + sdram_addr = 0xC0000000 + i; + if((*(volatile unsigned int*)sdram_addr) != 0x55555555){ + res = 1; + break; + } + } + + + if(0 == res){ + HAL_Delay(3); + for(i=0;i<0x04000000;i+=4){ + sdram_addr = 0xC0000000 + i; + + *(volatile unsigned int*)sdram_addr = 0xAAAAAAAA; + wait(); + } + LL_IWDG_ReloadCounter(IWDG1); + HAL_Delay(3); + for(i=0;i<0x04000000;i+=4){ + sdram_addr = 0xC0000000 + i; + if((*(volatile unsigned int*)sdram_addr) != 0xAAAAAAAA){ + res = 1; + break; + } + } + } + + sdram_addr = 0xC0000000 + 480*800*4; + for(y=0;y<480;y++){ + for(x=0;x<800;x++){ + *(volatile unsigned int*)sdram_addr = 0; + sdram_addr+=4; + } + } + + return res; +} + +void hw_lcd_test(void) +{ + unsigned int addr = 0xC0000000; + unsigned int res = 0; + unsigned int value = 0; + unsigned int i = 0,x = 0,y = 0; + + //----------------------------R------------------------------- + for(y=0;y<480;y++){ + addr = 0xC0000000 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFFFF0000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 100*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFFE00000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 200*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFFC00000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 300*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFFA00000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 400*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF800000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 500*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF600000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 600*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF400000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 700*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF200000; + addr+=4; + } + } + HAL_Delay(1500); + + //----------------------------G------------------------------- + for(y=0;y<480;y++){ + addr = 0xC0000000 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF00FF00; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 100*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF00E000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 200*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF00C000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 300*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF00A000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 400*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF008000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 500*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF006000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 600*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF004000; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 700*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF002000; + addr+=4; + } + } + HAL_Delay(1500); + + //----------------------------B------------------------------- + for(y=0;y<480;y++){ + addr = 0xC0000000 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF0000FF; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 100*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF0000E0; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 200*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF0000C0; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 300*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF0000A0; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 400*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF000080; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 500*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF000060; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 600*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF000040; + addr+=4; + } + } + for(y=0;y<480;y++){ + addr = 0xC0000000 + 700*4 + y*800*4; + for(x=0;x<100;x++){ + *(unsigned int*)addr = 0xFF000020; + addr+=4; + } + } + HAL_Delay(1500); + + //----------------------------R------------------------------- + addr = 0xC0000000; + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF200000; + addr+=4; + } + } + addr = 0xC0000000 + (60*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF400000; + addr+=4; + } + } + addr = 0xC0000000 + (120*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF600000; + addr+=4; + } + } + addr = 0xC0000000 + (180*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF800000; + addr+=4; + } + } + addr = 0xC0000000 + (240*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFFA00000; + addr+=4; + } + } + addr = 0xC0000000 + (300*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFFC00000; + addr+=4; + } + } + addr = 0xC0000000 + (360*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFFE00000; + addr+=4; + } + } + addr = 0xC0000000 + (420*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFFFF0000; + addr+=4; + } + } + HAL_Delay(1500); + + //----------------------------G------------------------------- + addr = 0xC0000000; + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF002000; + addr+=4; + } + } + addr = 0xC0000000 + (60*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF004000; + addr+=4; + } + } + addr = 0xC0000000 + (120*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF006000; + addr+=4; + } + } + addr = 0xC0000000 + (180*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF008000; + addr+=4; + } + } + addr = 0xC0000000 + (240*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF00A000; + addr+=4; + } + } + addr = 0xC0000000 + (300*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF00C000; + addr+=4; + } + } + addr = 0xC0000000 + (360*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF00E000; + addr+=4; + } + } + addr = 0xC0000000 + (420*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF00FF00; + addr+=4; + } + } + HAL_Delay(1500); + + //----------------------------B------------------------------- + addr = 0xC0000000; + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000020; + addr+=4; + } + } + addr = 0xC0000000 + (60*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000040; + addr+=4; + } + } + addr = 0xC0000000 + (120*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000060; + addr+=4; + } + } + addr = 0xC0000000 + (180*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF000080; + addr+=4; + } + } + addr = 0xC0000000 + (240*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF0000A0; + addr+=4; + } + } + addr = 0xC0000000 + (300*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF0000C0; + addr+=4; + } + } + addr = 0xC0000000 + (360*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF0000E0; + addr+=4; + } + } + addr = 0xC0000000 + (420*800*4); + for(y=0;y<60;y++){ + for(x=0;x<800;x++){ + *(unsigned int*)addr = 0xFF0000FF; + addr+=4; + } + } + HAL_Delay(1500); +} + +void hw_print_test(void) +{ + HAL_Delay(500); + print_text("\r\n\r\n\r\n\r\n"); + HAL_Delay(500); + print_text("\r\n--------------------------------\r\n"); + HAL_Delay(500); + print_text("\r\n----------打印测试页------------\r\n"); + HAL_Delay(500); + print_text("\r\n--------------------------------\r\n"); + HAL_Delay(500); +} + +void hw_relay_test(void) +{ + LL_TIM_OC_SetCompareCH1(TIM2,255);//RELAY1_ON() + LL_TIM_OC_SetCompareCH1(TIM12,255);//RELAY2_ON() + HAL_Delay(3000); + LL_TIM_OC_SetCompareCH1(TIM2,0);//RELAY1_OFF() + LL_TIM_OC_SetCompareCH1(TIM12,0);//RELAY2_OFF() + HAL_Delay(1000); +} diff --git a/FW/Core/my_src/HW_test_task.h b/FW/Core/my_src/HW_test_task.h new file mode 100644 index 0000000..65ad393 --- /dev/null +++ b/FW/Core/my_src/HW_test_task.h @@ -0,0 +1,17 @@ +#ifndef __HW_TEST_TASK_H +#define __HW_TEST_TASK_H + +extern unsigned int hw_test_mode; +extern unsigned char rx_text_buf[32]; + +extern unsigned int hw_test_init(void); +extern unsigned int hw_test_deinit(void); +extern unsigned int hw_uart_test(void); +extern unsigned int hw_eeprom_test(void); +extern unsigned int hw_nor_flash_test(void); +extern unsigned int hw_sdram_test(void); +extern void hw_print_test(void); +extern void hw_relay_test(void); +extern void hw_lcd_test(void); + +#endif diff --git a/FW/Core/my_src/I2C_eeprom.c b/FW/Core/my_src/I2C_eeprom.c new file mode 100644 index 0000000..9c6ebfb --- /dev/null +++ b/FW/Core/my_src/I2C_eeprom.c @@ -0,0 +1,373 @@ +#include "main.h" +#include "I2C_eeprom.h" + +//--------------------------724KHz-----------------sys:480MHz--------stm32H743----------------- + +#define I2C_ADDR_READ 0xA1 +#define I2C_ADDR_WRITE 0xA0 + +#define I2C_WP_PT() LL_GPIO_SetOutputPin(GPIOD,LL_GPIO_PIN_11) +#define I2C_WP_UNPT() LL_GPIO_ResetOutputPin(GPIOD,LL_GPIO_PIN_11) + +#define I2C_SCL_HI() LL_GPIO_SetOutputPin(GPIOD,LL_GPIO_PIN_12) +#define I2C_SCL_LO() LL_GPIO_ResetOutputPin(GPIOD,LL_GPIO_PIN_12) + +#define I2C_SDA_HI() LL_GPIO_SetOutputPin(GPIOD,LL_GPIO_PIN_13) +#define I2C_SDA_LO() LL_GPIO_ResetOutputPin(GPIOD,LL_GPIO_PIN_13) + +#define SDA_VALUE() ((0x2000 & GPIOD->IDR)>>13) + +static volatile unsigned short delay_4_pgm; + +static volatile unsigned char delay_x_tick; + +static void delay_x(void) +{ + for(delay_x_tick=0;delay_x_tick<16;delay_x_tick++); +} + +static void I2C_SCL_hi(void) +{ + I2C_SCL_HI();delay_x(); +} + +static void I2C_SCL_lo(void) +{ + I2C_SCL_LO();delay_x(); +} + +static void I2C_SDA_hi(void) +{ + I2C_SDA_HI();delay_x(); +} + +static void I2C_SDA_lo(void) +{ + I2C_SDA_LO();delay_x(); +} + +static void wait(void) +{ + __nop(); + __nop(); + __nop(); + __nop(); +} + +static void I2C_start(void) +{ + I2C_SCL_lo(); //SCL low + wait(); + I2C_SDA_lo(); //SDA low + wait(); + I2C_SDA_hi(); //SDA high + wait(); + I2C_SCL_hi(); //SCL high + wait(); + I2C_SDA_lo(); //SDA goes low before the clock + wait(); + I2C_SCL_lo(); //SCL low + wait(); +} + +static void I2C_stop(void) +{ + I2C_SDA_lo(); //SDA low + wait(); + I2C_SCL_hi(); //SCL high + wait(); + I2C_SDA_hi(); //SDA goes from low to high when SCL is already high, + wait(); +} + +static unsigned char I2C_send_byte(unsigned char bb) +{ + unsigned int i; + unsigned char noack; + unsigned char b,s; + b=bb; + for (i=8; i>0; i--) + { + I2C_SCL_lo(); //Reset SCL + wait(); + s = b >> 7; //Send data to SDA pin + if(1==(s & 0x01))I2C_SDA_hi();else I2C_SDA_lo(); + wait(); + I2C_SCL_hi(); //Set SCL + wait(); + I2C_SCL_lo(); //Reset SCL + wait(); + b<<=1; //Rotate data + } + I2C_SDA_hi(); + I2C_SCL_lo(); //Reset SCL + wait(); + I2C_SCL_hi(); //Set SCL + wait(); + delay_x(); + delay_x(); + noack = SDA_VALUE(); //Check SDA for ACKN + wait(); + I2C_SCL_lo(); + wait(); + I2C_SDA_lo(); + wait(); + return(noack); +} + +static unsigned char I2C_read_byte(unsigned char ackn) +{ + unsigned int i; + unsigned char ReceivedByte; + + ReceivedByte=0x0000; + I2C_SDA_hi(); //Make SDA an input + I2C_SCL_lo(); //Reset SCL + for (i=8; i>0; i--) + { + wait(); + I2C_SCL_hi(); //Set SCL + ReceivedByte <<= 1; //Rotate data + ReceivedByte |= SDA_VALUE(); //Read SDA -> data + wait(); + I2C_SCL_lo(); //Reset SCL + wait(); + } + if(0==ackn)I2C_SDA_lo();else I2C_SDA_hi(); //SDA = ACK bit + wait(); + I2C_SCL_hi(); //Set SCL + wait(); + I2C_SCL_lo(); //Reset SCL + wait(); + return(ReceivedByte); +} + +unsigned int I2C_byte_write_via_page(unsigned int chip_cs, unsigned int addr, unsigned char *p, unsigned int len) +{ + unsigned int i; + unsigned char data; + unsigned char addr_hi,addr_lo; + unsigned int i2c_page_size; + unsigned char i2c_addr_write_cmd; + unsigned char offset; + + if(chip_cs){ + i2c_page_size = I2C_PAGE_SIZE_24M01; + }else{ + i2c_page_size = I2C_PAGE_SIZE_24512; + } + + offset = addr & (i2c_page_size - 1); + if((offset + len) > i2c_page_size)return 1; + + if(chip_cs)i2c_addr_write_cmd = I2C_ADDR_WRITE | 0x08 | ((addr&0x00010000)>>15); + else i2c_addr_write_cmd = I2C_ADDR_WRITE; + + I2C_WP_UNPT(); + + addr_hi = (unsigned char)(addr >> 8); + addr_lo = (unsigned char)(addr); + + I2C_start(); + if(!I2C_send_byte(i2c_addr_write_cmd)) + { + if(!I2C_send_byte(addr_hi)) + { + if(!I2C_send_byte(addr_lo)) + { + for(i=0;i> 8); + addr_lo = 0; + }else{ + i2c_page_size = I2C_PAGE_SIZE_24512; + addr_hi = (unsigned char)(addr >> 8); + addr_lo = (unsigned char)(addr & 0x80); + } + + if(chip_cs)i2c_addr_write_cmd = I2C_ADDR_WRITE | 0x08 | ((addr&0x00010000)>>15); + else i2c_addr_write_cmd = I2C_ADDR_WRITE; + + I2C_WP_UNPT(); + + I2C_start(); + if(!I2C_send_byte(i2c_addr_write_cmd)) + { + if(!I2C_send_byte(addr_hi)) + { + if(!I2C_send_byte(addr_lo)) + { + for(i=0;i chip_size)return 1; + + if(chip_cs){ + i2c_addr_write_cmd = I2C_ADDR_WRITE | 0x08 | ((addr&0x00010000)>>15); + i2c_addr_read_cmd = I2C_ADDR_READ | 0x08 | ((addr&0x00010000)>>15); + }else{ + i2c_addr_write_cmd = I2C_ADDR_WRITE; + i2c_addr_read_cmd = I2C_ADDR_READ; + } + + addr_hi = (unsigned char)(addr >> 8); + addr_lo = (unsigned char)(addr); + + I2C_start(); + if(!I2C_send_byte(i2c_addr_write_cmd)) + { + if(!I2C_send_byte(addr_hi)) + { + if(!I2C_send_byte(addr_lo)) + { + I2C_stop(); + I2C_start(); + I2C_send_byte(i2c_addr_read_cmd); + for(i=0;i> 8); + addr_lo = (unsigned char)(page_addr&0xFF); + + I2C_start(); + if(!I2C_send_byte(I2C_addr_write)) + { + if(!I2C_send_byte(addr_hi)) + { + if(!I2C_send_byte(addr_lo)) + { + for(i=0;i> 8); + addr_lo = (unsigned char)(page_addr&0xFF); + + I2C_start(); + if(!I2C_send_byte(I2C_addr_write)) + { + if(!I2C_send_byte(addr_hi)) + { + if(!I2C_send_byte(addr_lo)) + { + I2C_stop(); + I2C_start(); + I2C_send_byte(I2C_addr_read); + for(i=0;iMODER&=~0x000C0000 +#define xSPI_SET_MISO_OUTPUT() GPIOG->MODER|=0x00040000 + +#define xSPI_SET_MOSI_INPUT() GPIOD->MODER&=~0x0000C000 +#define xSPI_SET_MOSI_OUTPUT() GPIOD->MODER|=0x00004000 + +#define xSPI_GET_MISO() LL_GPIO_IsInputPinSet(GPIOG,LL_GPIO_PIN_9) +#define xSPI_MOSI_HI() GPIOD->ODR|=(1<<7) +#define xSPI_MOSI_LO() GPIOD->ODR&=~(1<<7) + +#define xSPI_SET_DATA_INPUT() (GPIOG->MODER&=~0x0C0C0000,GPIOE->MODER&=~0x00000030,GPIOD->MODER&=~0x0000C000) +#define xSPI_SET_DATA_OUTPUT() (GPIOG->MODER|=0x04040000,GPIOE->MODER|=0x00000010,GPIOD->MODER|=0x00004000) + +#define xSPI_DIN() (((GPIOE->IDR&0x0004)<<1)|((GPIOG->IDR&0x2000)>>11)|((GPIOG->IDR&0x0200)>>8)|((GPIOD->IDR&0x0080)>>7)) + +#define xSPI_D0_HI() LL_GPIO_SetOutputPin(GPIOD,LL_GPIO_PIN_7) +#define xSPI_D0_LO() LL_GPIO_ResetOutputPin(GPIOD,LL_GPIO_PIN_7) +#define xSPI_D1_HI() LL_GPIO_SetOutputPin(GPIOG,LL_GPIO_PIN_9) +#define xSPI_D1_LO() LL_GPIO_ResetOutputPin(GPIOG,LL_GPIO_PIN_9) +#define xSPI_D2_HI() LL_GPIO_SetOutputPin(GPIOG,LL_GPIO_PIN_13) +#define xSPI_D2_LO() LL_GPIO_ResetOutputPin(GPIOG,LL_GPIO_PIN_13) +#define xSPI_D3_HI() LL_GPIO_SetOutputPin(GPIOE,LL_GPIO_PIN_2) +#define xSPI_D3_LO() LL_GPIO_ResetOutputPin(GPIOE,LL_GPIO_PIN_2) + +static void flash_reset(void); +static void flash_write_enable(void); +static void flash_write_disable(void); +static void flash_quad_enable(void); +static void flash_quad_disable(void); +static uint8_t flash_read_sr1(void); +static uint8_t flash_read_sr2(void); + +static void wait(void) +{ + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); +} + +void w25q_IO_setup(void) +{ + static uint8_t val = 0; + uint32_t i = 0; + /* + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOC); + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOD); + + //PD6 PC10 12 13 14 15 + GPIOC->MODER &=~0xFF300000; + GPIOD->MODER &=~0x00003000; + GPIOC->MODER |= 0x00100000; + GPIOD->MODER |= 0x00001000; //PD6,PC10 GPIO Output Mode + + GPIOC->OTYPER &=~0x0000F400; //Output push-pull + GPIOD->OTYPER &=~0x00000040; + GPIOC->OSPEEDR |= 0xFF300000; //Very High speed + GPIOD->OSPEEDR |= 0x00003000; + */ + xSPI_CS_HI(); + xSPI_CLK_LO(); + + xSPI_SET_DATA_OUTPUT(); + FLASH_WP_H(); + FLASH_HOLD_H(); + for(i=0;i<10000;i++); + + flash_write_enable(); + xSPI_SET_DATA_INPUT(); + + flash_reset(); + + xSPI_SET_DATA_OUTPUT(); + FLASH_WP_H(); + FLASH_HOLD_H(); + for(i=0;i<10000;i++); + flash_write_enable(); + xSPI_SET_DATA_INPUT(); + + do + { + val = flash_read_sr1(); + }while(val&0x01); + + val = flash_read_sr2(); + if(!(val&0x02)) + { + do + { + flash_quad_enable(); + val = flash_read_sr2(); + }while(!(val&0x02)); + } +} + +uint8_t QSPI_D0123_read(void) +{ + return(xSPI_DIN()); +} + +void QSPI_D0123_write(uint8_t x) +{ + if(x&0x01) + { + xSPI_D0_HI(); + } + else + { + xSPI_D0_LO(); + } + + if(x&0x02) + { + xSPI_D1_HI(); + } + else + { + xSPI_D1_LO(); + } + + if(x&0x04) + { + xSPI_D2_HI(); + } + else + { + xSPI_D2_LO(); + } + + if(x&0x08) + { + xSPI_D3_HI(); + } + else + { + xSPI_D3_LO(); + } +} + +void xspi_write_byte(uint8_t data) +{ + uint32_t i; + xSPI_SET_MOSI_OUTPUT(); + for(i=0;i<8;i++) + { + if(data & 0x80)xSPI_MOSI_HI(); + else xSPI_MOSI_LO(); + + xSPI_CLK_HI(); + xSPI_CLK_LO(); + data<<=1; + } + xSPI_MOSI_LO(); + xSPI_SET_MOSI_INPUT(); +} + +uint8_t xspi_read_byte(void) +{ + uint32_t i; + uint8_t data = 0; + for(i=0;i<8;i++) + { + wait(); + data<<=1; + if(xSPI_GET_MISO())data |= 0x01; + xSPI_CLK_HI(); + wait(); + xSPI_CLK_LO(); + } + return data; +} + +void xspi_quad_write_byte(uint8_t data) +{ + xSPI_SET_DATA_OUTPUT(); + QSPI_D0123_write(data>>4); + xSPI_CLK_HI(); + wait(); + xSPI_CLK_LO(); + QSPI_D0123_write(data); + xSPI_CLK_HI(); + wait(); + xSPI_CLK_LO(); + xSPI_SET_DATA_INPUT(); + wait(); +} + +uint8_t xspi_quad_read_byte(void) +{ + uint8_t data; + + data = QSPI_D0123_read(); + xSPI_CLK_HI(); + xSPI_CLK_LO(); + data<<=4; + data |= QSPI_D0123_read(); + xSPI_CLK_HI(); + xSPI_CLK_LO(); + return data; +} + +static void flash_write_enable(void) +{ + uint32_t i = 0; + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x06); + xSPI_CS_HI(); + for(i=0;i<10000;i++); +} + +static void flash_write_disable(void) +{ + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x04); + xSPI_CS_HI(); +} + +static uint8_t flash_read_sr1(void) +{ + uint8_t sr1; + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x05); + + sr1 = xspi_read_byte(); + wait(); + xSPI_CS_HI(); + return sr1; +} + +static uint8_t flash_read_sr2(void) +{ + uint8_t sr2; + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x35); + + sr2 = xspi_read_byte(); + wait(); + xSPI_CS_HI(); + return sr2; +} + +void flash_write_sr(uint8_t sr1,uint8_t sr2) +{ + flash_write_enable(); + + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x01); + xspi_write_byte(sr1); + xspi_write_byte(sr2); + wait(); + xSPI_CS_HI(); + + flash_write_disable(); +} + +static void flash_quad_enable(void) +{ + flash_write_enable(); + flash_write_sr(0x00,0x02); + flash_write_disable(); +} + +static void flash_quad_disable(void) +{ + flash_write_enable(); + flash_write_sr(0x00,0x00); + flash_write_disable(); +} + +uint8_t get_flash_write_status(void) +{ + return(flash_read_sr1() & 0x01); +} + +unsigned int flash_quad_read_data(unsigned int addr, unsigned char * p_data,unsigned int len)//p_data >=256byte +{ + unsigned int i = 0; + + if((addr + len) > NOR_FLASH_SIZE)return 1; + + xSPI_CLK_LO(); + xSPI_CS_LO(); + xspi_write_byte(0x6b); + xspi_write_byte((addr>>16)&0xff); + xspi_write_byte((addr>>8)&0xff); + xspi_write_byte(addr&0xff); + xspi_write_byte(0); + + for(i=0;i>16)&0xff); + xspi_write_byte((addr_page>>8)&0xff); + xspi_write_byte(addr_page&0xff); + xspi_write_byte(0); + + for(i=0;i<256;i++) + { + p_data[i] = xspi_quad_read_byte(); + } + xSPI_CS_HI(); + return &p_data[0]; +} + +void flash_quad_program_page(uint32_t addr,uint8_t* p_data) +{ + uint32_t i = 0; + unsigned int addr_page = addr & 0xFFFFFF00; + //flash_quad_enable(); + //do{ + //i = flash_read_sr1(); + //}while(i&0x01); + + flash_write_enable(); + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x32); + xspi_write_byte((addr_page>>16)&0xff); + xspi_write_byte((addr_page>>8)&0xff); + xspi_write_byte(addr_page&0xff); + + for(i=0;i<256;i++) + { + xspi_quad_write_byte(*p_data); + p_data++; + } + xSPI_CS_HI(); + flash_write_disable(); + + do{ + LL_IWDG_ReloadCounter(IWDG1); + i = flash_read_sr1(); + }while(i&0x01); +} + +void flash_quad_program_page_no_wait(uint32_t addr,uint8_t* p_data) +{ + uint32_t i = 0; + unsigned int addr_page = addr & 0xFFFFFF00; + + flash_write_enable(); + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x32); + xspi_write_byte((addr_page>>16)&0xff); + xspi_write_byte((addr_page>>8)&0xff); + xspi_write_byte(addr_page&0xff); + + for(i=0;i<256;i++) + { + xspi_quad_write_byte(*p_data); + p_data++; + } + xSPI_CS_HI(); + flash_write_disable(); +} + +unsigned int flash_quad_program_no_wait(uint32_t addr,uint8_t* p_data,unsigned int len) +{ + uint32_t i = 0; + + if(((addr&0xFF) + len) > 0x100)return 1; + + flash_write_enable(); + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x32); + xspi_write_byte((addr>>16)&0xff); + xspi_write_byte((addr>>8)&0xff); + xspi_write_byte(addr&0xff); + + for(i=0;i>16); + xspi_write_byte((addr_sector&0x0000FF00)>>8); + xspi_write_byte(addr_sector&0x000000FF); + xSPI_CS_HI(); + flash_write_disable(); + + while(val) + { + LL_IWDG_ReloadCounter(IWDG1); + val = (flash_read_sr1() & 0x01); + } + + for(i=0;i<10000;i++)__nop(); +} + +void flash_sector_erase_no_wait(uint32_t addr) +{ + unsigned char val = 1; + unsigned int i = 0; + unsigned int addr_sector = addr & 0xFFFFF000; + + flash_write_enable(); + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x20); + xspi_write_byte((addr_sector&0x00FF0000)>>16); + xspi_write_byte((addr_sector&0x0000FF00)>>8); + xspi_write_byte(addr_sector&0x000000FF); + xSPI_CS_HI(); + flash_write_disable(); + wait(); +} + +void flash_full_chip_erase(void) // erase chip +{ + uint8_t val = 1; + + flash_write_enable(); + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x60); + xSPI_CS_HI(); + while(val) + { + LL_IWDG_ReloadCounter(IWDG1); + val = (flash_read_sr1() & 0x01); + } +} + +void flash_full_chip_erase_no_wait(void) // erase chip +{ + uint8_t val = 1; + + flash_write_enable(); + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x60); + xSPI_CS_HI(); + wait(); +} + +static void flash_reset(void) +{ + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x66); + xSPI_CS_HI(); + + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x99); + xSPI_CS_HI(); + + HAL_Delay(5); +} + +void flash_read_id(uint8_t *p_ddata) +{ + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + wait(); + xspi_write_byte(0x90); // cmd + xspi_write_byte(0); // h + xspi_write_byte(0); // m + xspi_write_byte(0); // l + + *p_ddata = xspi_read_byte(); + p_ddata++; + *p_ddata = xspi_read_byte(); + //wait(); + xSPI_CS_HI(); +} + +void flash_quad_read_id(uint8_t *p_ddata) +{ + xSPI_CLK_LO(); + xSPI_CS_LO(); + wait(); + xspi_write_byte(0x94); // cmd + xspi_quad_write_byte(0); // h + xspi_quad_write_byte(0); // m + xspi_quad_write_byte(0); // l + xspi_quad_write_byte(0xff); // h + xspi_quad_write_byte(0); // m + xspi_quad_write_byte(0); + + *p_ddata = xspi_quad_read_byte(); + p_ddata++; + *p_ddata = xspi_quad_read_byte(); + wait(); + xSPI_CS_HI(); +} diff --git a/FW/Core/my_src/W25Qxx_iodrv.h b/FW/Core/my_src/W25Qxx_iodrv.h new file mode 100644 index 0000000..92c71d4 --- /dev/null +++ b/FW/Core/my_src/W25Qxx_iodrv.h @@ -0,0 +1,16 @@ +#include "stm32h7xx.h" + +extern void w25q_IO_setup(void); + +extern uint8_t get_flash_write_status(void); +extern void flash_full_chip_erase(void); +extern void flash_full_chip_erase_no_wait(void); +extern void flash_sector_erase(uint32_t addr); +extern void flash_sector_erase_no_wait(uint32_t addr); +extern uint8_t* flash_read(uint32_t addr,uint8_t len); +//extern uint8_t* flash_read_page(uint32_t addr); +//extern void flash_program_page(uint32_t addr,uint8_t* data_point); +extern uint8_t* flash_quad_read_page(uint32_t addr); +extern unsigned int flash_quad_read_data(unsigned int addr, unsigned char * p_data,unsigned int len); +extern void flash_quad_program_page(uint32_t addr,uint8_t* p_data); +extern void flash_quad_program_page_no_wait(uint32_t addr,uint8_t* p_data); diff --git a/FW/Core/my_src/cJSON.c b/FW/Core/my_src/cJSON.c new file mode 100644 index 0000000..ca824f0 --- /dev/null +++ b/FW/Core/my_src/cJSON.c @@ -0,0 +1,3191 @@ +/* + Copyright (c) 2009-2017 Dave Gamble and cJSON contributors + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + +/* cJSON */ +/* JSON parser in C. */ + +/* disable warnings about old C89 functions in MSVC */ +#if !defined(_CRT_SECURE_NO_DEPRECATE) && defined(_MSC_VER) +#define _CRT_SECURE_NO_DEPRECATE +#endif + +#ifdef __GNUC__ +#pragma GCC visibility push(default) +#endif +#if defined(_MSC_VER) +#pragma warning (push) +/* disable warning about single line comments in system headers */ +#pragma warning (disable : 4001) +#endif + +#include +#include +#include +#include +#include +#include +#include + +#ifdef ENABLE_LOCALES +#include +#endif + +#if defined(_MSC_VER) +#pragma warning (pop) +#endif +#ifdef __GNUC__ +#pragma GCC visibility pop +#endif + +#include "cJSON.h" + +/* define our own boolean type */ +#ifdef true +#undef true +#endif +#define true ((cJSON_bool)1) + +#ifdef false +#undef false +#endif +#define false ((cJSON_bool)0) + +/* define isnan and isinf for ANSI C, if in C99 or above, isnan and isinf has been defined in math.h */ +#ifndef isinf +#define isinf(d) (isnan((d - d)) && !isnan(d)) +#endif +#ifndef isnan +#define isnan(d) (d != d) +#endif + +#ifndef NAN +#ifdef _WIN32 +#define NAN sqrt(-1.0) +#else +#define NAN 0.0/0.0 +#endif +#endif + +typedef struct { + const unsigned char *json; + size_t position; +} error; +static error global_error = { NULL, 0 }; + +CJSON_PUBLIC(const char *) cJSON_GetErrorPtr(void) +{ + return (const char*) (global_error.json + global_error.position); +} + +CJSON_PUBLIC(char *) cJSON_GetStringValue(const cJSON * const item) +{ + if (!cJSON_IsString(item)) + { + return NULL; + } + + return item->valuestring; +} + +CJSON_PUBLIC(double) cJSON_GetNumberValue(const cJSON * const item) +{ + if (!cJSON_IsNumber(item)) + { + return (double) NAN; + } + + return item->valuedouble; +} + +/* This is a safeguard to prevent copy-pasters from using incompatible C and header files */ +#if (CJSON_VERSION_MAJOR != 1) || (CJSON_VERSION_MINOR != 7) || (CJSON_VERSION_PATCH != 18) + #error cJSON.h and cJSON.c have different versions. Make sure that both have the same. +#endif + +CJSON_PUBLIC(const char*) cJSON_Version(void) +{ + static char version[15]; + sprintf(version, "%i.%i.%i", CJSON_VERSION_MAJOR, CJSON_VERSION_MINOR, CJSON_VERSION_PATCH); + + return version; +} + +/* Case insensitive string comparison, doesn't consider two NULL pointers equal though */ +static int case_insensitive_strcmp(const unsigned char *string1, const unsigned char *string2) +{ + if ((string1 == NULL) || (string2 == NULL)) + { + return 1; + } + + if (string1 == string2) + { + return 0; + } + + for(; tolower(*string1) == tolower(*string2); (void)string1++, string2++) + { + if (*string1 == '\0') + { + return 0; + } + } + + return tolower(*string1) - tolower(*string2); +} + +typedef struct internal_hooks +{ + void *(CJSON_CDECL *allocate)(size_t size); + void (CJSON_CDECL *deallocate)(void *pointer); + void *(CJSON_CDECL *reallocate)(void *pointer, size_t size); +} internal_hooks; + +#if defined(_MSC_VER) +/* work around MSVC error C2322: '...' address of dllimport '...' is not static */ +static void * CJSON_CDECL internal_malloc(size_t size) +{ + return malloc(size); +} +static void CJSON_CDECL internal_free(void *pointer) +{ + free(pointer); +} +static void * CJSON_CDECL internal_realloc(void *pointer, size_t size) +{ + return realloc(pointer, size); +} +#else +#define internal_malloc malloc +#define internal_free free +#define internal_realloc realloc +#endif + +/* strlen of character literals resolved at compile time */ +#define static_strlen(string_literal) (sizeof(string_literal) - sizeof("")) + +static internal_hooks global_hooks = { internal_malloc, internal_free, internal_realloc }; + +static unsigned char* cJSON_strdup(const unsigned char* string, const internal_hooks * const hooks) +{ + size_t length = 0; + unsigned char *copy = NULL; + + if (string == NULL) + { + return NULL; + } + + length = strlen((const char*)string) + sizeof(""); + copy = (unsigned char*)hooks->allocate(length); + if (copy == NULL) + { + return NULL; + } + memcpy(copy, string, length); + + return copy; +} + +CJSON_PUBLIC(void) cJSON_InitHooks(cJSON_Hooks* hooks) +{ + if (hooks == NULL) + { + /* Reset hooks */ + global_hooks.allocate = malloc; + global_hooks.deallocate = free; + global_hooks.reallocate = realloc; + return; + } + + global_hooks.allocate = malloc; + if (hooks->malloc_fn != NULL) + { + global_hooks.allocate = hooks->malloc_fn; + } + + global_hooks.deallocate = free; + if (hooks->free_fn != NULL) + { + global_hooks.deallocate = hooks->free_fn; + } + + /* use realloc only if both free and malloc are used */ + global_hooks.reallocate = NULL; + if ((global_hooks.allocate == malloc) && (global_hooks.deallocate == free)) + { + global_hooks.reallocate = realloc; + } +} + +/* Internal constructor. */ +static cJSON *cJSON_New_Item(const internal_hooks * const hooks) +{ + cJSON* node = (cJSON*)hooks->allocate(sizeof(cJSON)); + if (node) + { + memset(node, '\0', sizeof(cJSON)); + } + + return node; +} + +/* Delete a cJSON structure. */ +CJSON_PUBLIC(void) cJSON_Delete(cJSON *item) +{ + cJSON *next = NULL; + while (item != NULL) + { + next = item->next; + if (!(item->type & cJSON_IsReference) && (item->child != NULL)) + { + cJSON_Delete(item->child); + } + if (!(item->type & cJSON_IsReference) && (item->valuestring != NULL)) + { + global_hooks.deallocate(item->valuestring); + item->valuestring = NULL; + } + if (!(item->type & cJSON_StringIsConst) && (item->string != NULL)) + { + global_hooks.deallocate(item->string); + item->string = NULL; + } + global_hooks.deallocate(item); + item = next; + } +} + +/* get the decimal point character of the current locale */ +static unsigned char get_decimal_point(void) +{ +#ifdef ENABLE_LOCALES + struct lconv *lconv = localeconv(); + return (unsigned char) lconv->decimal_point[0]; +#else + return '.'; +#endif +} + +typedef struct +{ + const unsigned char *content; + size_t length; + size_t offset; + size_t depth; /* How deeply nested (in arrays/objects) is the input at the current offset. */ + internal_hooks hooks; +} parse_buffer; + +/* check if the given size is left to read in a given parse buffer (starting with 1) */ +#define can_read(buffer, size) ((buffer != NULL) && (((buffer)->offset + size) <= (buffer)->length)) +/* check if the buffer can be accessed at the given index (starting with 0) */ +#define can_access_at_index(buffer, index) ((buffer != NULL) && (((buffer)->offset + index) < (buffer)->length)) +#define cannot_access_at_index(buffer, index) (!can_access_at_index(buffer, index)) +/* get a pointer to the buffer at the position */ +#define buffer_at_offset(buffer) ((buffer)->content + (buffer)->offset) + +/* Parse the input text to generate a number, and populate the result into item. */ +static cJSON_bool parse_number(cJSON * const item, parse_buffer * const input_buffer) +{ + double number = 0; + unsigned char *after_end = NULL; + unsigned char *number_c_string; + unsigned char decimal_point = get_decimal_point(); + size_t i = 0; + size_t number_string_length = 0; + cJSON_bool has_decimal_point = false; + + if ((input_buffer == NULL) || (input_buffer->content == NULL)) + { + return false; + } + + /* copy the number into a temporary buffer and replace '.' with the decimal point + * of the current locale (for strtod) + * This also takes care of '\0' not necessarily being available for marking the end of the input */ + for (i = 0; can_access_at_index(input_buffer, i); i++) + { + switch (buffer_at_offset(input_buffer)[i]) + { + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case '+': + case '-': + case 'e': + case 'E': + number_string_length++; + break; + + case '.': + number_string_length++; + has_decimal_point = true; + break; + + default: + goto loop_end; + } + } +loop_end: + /* malloc for temporary buffer, add 1 for '\0' */ + number_c_string = (unsigned char *) input_buffer->hooks.allocate(number_string_length + 1); + if (number_c_string == NULL) + { + return false; /* allocation failure */ + } + + memcpy(number_c_string, buffer_at_offset(input_buffer), number_string_length); + number_c_string[number_string_length] = '\0'; + + if (has_decimal_point) + { + for (i = 0; i < number_string_length; i++) + { + if (number_c_string[i] == '.') + { + /* replace '.' with the decimal point of the current locale (for strtod) */ + number_c_string[i] = decimal_point; + } + } + } + + number = strtod((const char*)number_c_string, (char**)&after_end); + if (number_c_string == after_end) + { + /* free the temporary buffer */ + input_buffer->hooks.deallocate(number_c_string); + return false; /* parse_error */ + } + + item->valuedouble = number; + + /* use saturation in case of overflow */ + if (number >= INT_MAX) + { + item->valueint = INT_MAX; + } + else if (number <= (double)INT_MIN) + { + item->valueint = INT_MIN; + } + else + { + item->valueint = (int)number; + } + + item->type = cJSON_Number; + + input_buffer->offset += (size_t)(after_end - number_c_string); + /* free the temporary buffer */ + input_buffer->hooks.deallocate(number_c_string); + return true; +} + +/* don't ask me, but the original cJSON_SetNumberValue returns an integer or double */ +CJSON_PUBLIC(double) cJSON_SetNumberHelper(cJSON *object, double number) +{ + if (number >= INT_MAX) + { + object->valueint = INT_MAX; + } + else if (number <= (double)INT_MIN) + { + object->valueint = INT_MIN; + } + else + { + object->valueint = (int)number; + } + + return object->valuedouble = number; +} + +/* Note: when passing a NULL valuestring, cJSON_SetValuestring treats this as an error and return NULL */ +CJSON_PUBLIC(char*) cJSON_SetValuestring(cJSON *object, const char *valuestring) +{ + char *copy = NULL; + size_t v1_len; + size_t v2_len; + /* if object's type is not cJSON_String or is cJSON_IsReference, it should not set valuestring */ + if ((object == NULL) || !(object->type & cJSON_String) || (object->type & cJSON_IsReference)) + { + return NULL; + } + /* return NULL if the object is corrupted or valuestring is NULL */ + if (object->valuestring == NULL || valuestring == NULL) + { + return NULL; + } + + v1_len = strlen(valuestring); + v2_len = strlen(object->valuestring); + + if (v1_len <= v2_len) + { + /* strcpy does not handle overlapping string: [X1, X2] [Y1, Y2] => X2 < Y1 or Y2 < X1 */ + if (!( valuestring + v1_len < object->valuestring || object->valuestring + v2_len < valuestring )) + { + return NULL; + } + strcpy(object->valuestring, valuestring); + return object->valuestring; + } + copy = (char*) cJSON_strdup((const unsigned char*)valuestring, &global_hooks); + if (copy == NULL) + { + return NULL; + } + if (object->valuestring != NULL) + { + cJSON_free(object->valuestring); + } + object->valuestring = copy; + + return copy; +} + +typedef struct +{ + unsigned char *buffer; + size_t length; + size_t offset; + size_t depth; /* current nesting depth (for formatted printing) */ + cJSON_bool noalloc; + cJSON_bool format; /* is this print a formatted print */ + internal_hooks hooks; +} printbuffer; + +/* realloc printbuffer if necessary to have at least "needed" bytes more */ +static unsigned char* ensure(printbuffer * const p, size_t needed) +{ + unsigned char *newbuffer = NULL; + size_t newsize = 0; + + if ((p == NULL) || (p->buffer == NULL)) + { + return NULL; + } + + if ((p->length > 0) && (p->offset >= p->length)) + { + /* make sure that offset is valid */ + return NULL; + } + + if (needed > INT_MAX) + { + /* sizes bigger than INT_MAX are currently not supported */ + return NULL; + } + + needed += p->offset + 1; + if (needed <= p->length) + { + return p->buffer + p->offset; + } + + if (p->noalloc) { + return NULL; + } + + /* calculate new buffer size */ + if (needed > (INT_MAX / 2)) + { + /* overflow of int, use INT_MAX if possible */ + if (needed <= INT_MAX) + { + newsize = INT_MAX; + } + else + { + return NULL; + } + } + else + { + newsize = needed * 2; + } + + if (p->hooks.reallocate != NULL) + { + /* reallocate with realloc if available */ + newbuffer = (unsigned char*)p->hooks.reallocate(p->buffer, newsize); + if (newbuffer == NULL) + { + p->hooks.deallocate(p->buffer); + p->length = 0; + p->buffer = NULL; + + return NULL; + } + } + else + { + /* otherwise reallocate manually */ + newbuffer = (unsigned char*)p->hooks.allocate(newsize); + if (!newbuffer) + { + p->hooks.deallocate(p->buffer); + p->length = 0; + p->buffer = NULL; + + return NULL; + } + + memcpy(newbuffer, p->buffer, p->offset + 1); + p->hooks.deallocate(p->buffer); + } + p->length = newsize; + p->buffer = newbuffer; + + return newbuffer + p->offset; +} + +/* calculate the new length of the string in a printbuffer and update the offset */ +static void update_offset(printbuffer * const buffer) +{ + const unsigned char *buffer_pointer = NULL; + if ((buffer == NULL) || (buffer->buffer == NULL)) + { + return; + } + buffer_pointer = buffer->buffer + buffer->offset; + + buffer->offset += strlen((const char*)buffer_pointer); +} + +/* securely comparison of floating-point variables */ +static cJSON_bool compare_double(double a, double b) +{ + double maxVal = fabs(a) > fabs(b) ? fabs(a) : fabs(b); + return (fabs(a - b) <= maxVal * DBL_EPSILON); +} + +/* Render the number nicely from the given item into a string. */ +static cJSON_bool print_number(const cJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output_pointer = NULL; + double d = item->valuedouble; + int length = 0; + size_t i = 0; + unsigned char number_buffer[26] = {0}; /* temporary buffer to print the number into */ + unsigned char decimal_point = get_decimal_point(); + double test = 0.0; + + if (output_buffer == NULL) + { + return false; + } + + /* This checks for NaN and Infinity */ + if (isnan(d) || isinf(d)) + { + length = sprintf((char*)number_buffer, "null"); + } + else if(d == (double)item->valueint) + { + length = sprintf((char*)number_buffer, "%d", item->valueint); + } + else + { + /* Try 15 decimal places of precision to avoid nonsignificant nonzero digits */ + length = sprintf((char*)number_buffer, "%1.15g", d); + + /* Check whether the original double can be recovered */ + if ((sscanf((char*)number_buffer, "%lg", &test) != 1) || !compare_double((double)test, d)) + { + /* If not, print with 17 decimal places of precision */ + length = sprintf((char*)number_buffer, "%1.17g", d); + } + } + + /* sprintf failed or buffer overrun occurred */ + if ((length < 0) || (length > (int)(sizeof(number_buffer) - 1))) + { + return false; + } + + /* reserve appropriate space in the output */ + output_pointer = ensure(output_buffer, (size_t)length + sizeof("")); + if (output_pointer == NULL) + { + return false; + } + + /* copy the printed number to the output and replace locale + * dependent decimal point with '.' */ + for (i = 0; i < ((size_t)length); i++) + { + if (number_buffer[i] == decimal_point) + { + output_pointer[i] = '.'; + continue; + } + + output_pointer[i] = number_buffer[i]; + } + output_pointer[i] = '\0'; + + output_buffer->offset += (size_t)length; + + return true; +} + +/* parse 4 digit hexadecimal number */ +static unsigned parse_hex4(const unsigned char * const input) +{ + unsigned int h = 0; + size_t i = 0; + + for (i = 0; i < 4; i++) + { + /* parse digit */ + if ((input[i] >= '0') && (input[i] <= '9')) + { + h += (unsigned int) input[i] - '0'; + } + else if ((input[i] >= 'A') && (input[i] <= 'F')) + { + h += (unsigned int) 10 + input[i] - 'A'; + } + else if ((input[i] >= 'a') && (input[i] <= 'f')) + { + h += (unsigned int) 10 + input[i] - 'a'; + } + else /* invalid */ + { + return 0; + } + + if (i < 3) + { + /* shift left to make place for the next nibble */ + h = h << 4; + } + } + + return h; +} + +/* converts a UTF-16 literal to UTF-8 + * A literal can be one or two sequences of the form \uXXXX */ +static unsigned char utf16_literal_to_utf8(const unsigned char * const input_pointer, const unsigned char * const input_end, unsigned char **output_pointer) +{ + long unsigned int codepoint = 0; + unsigned int first_code = 0; + const unsigned char *first_sequence = input_pointer; + unsigned char utf8_length = 0; + unsigned char utf8_position = 0; + unsigned char sequence_length = 0; + unsigned char first_byte_mark = 0; + + if ((input_end - first_sequence) < 6) + { + /* input ends unexpectedly */ + goto fail; + } + + /* get the first utf16 sequence */ + first_code = parse_hex4(first_sequence + 2); + + /* check that the code is valid */ + if (((first_code >= 0xDC00) && (first_code <= 0xDFFF))) + { + goto fail; + } + + /* UTF16 surrogate pair */ + if ((first_code >= 0xD800) && (first_code <= 0xDBFF)) + { + const unsigned char *second_sequence = first_sequence + 6; + unsigned int second_code = 0; + sequence_length = 12; /* \uXXXX\uXXXX */ + + if ((input_end - second_sequence) < 6) + { + /* input ends unexpectedly */ + goto fail; + } + + if ((second_sequence[0] != '\\') || (second_sequence[1] != 'u')) + { + /* missing second half of the surrogate pair */ + goto fail; + } + + /* get the second utf16 sequence */ + second_code = parse_hex4(second_sequence + 2); + /* check that the code is valid */ + if ((second_code < 0xDC00) || (second_code > 0xDFFF)) + { + /* invalid second half of the surrogate pair */ + goto fail; + } + + + /* calculate the unicode codepoint from the surrogate pair */ + codepoint = 0x10000 + (((first_code & 0x3FF) << 10) | (second_code & 0x3FF)); + } + else + { + sequence_length = 6; /* \uXXXX */ + codepoint = first_code; + } + + /* encode as UTF-8 + * takes at maximum 4 bytes to encode: + * 11110xxx 10xxxxxx 10xxxxxx 10xxxxxx */ + if (codepoint < 0x80) + { + /* normal ascii, encoding 0xxxxxxx */ + utf8_length = 1; + } + else if (codepoint < 0x800) + { + /* two bytes, encoding 110xxxxx 10xxxxxx */ + utf8_length = 2; + first_byte_mark = 0xC0; /* 11000000 */ + } + else if (codepoint < 0x10000) + { + /* three bytes, encoding 1110xxxx 10xxxxxx 10xxxxxx */ + utf8_length = 3; + first_byte_mark = 0xE0; /* 11100000 */ + } + else if (codepoint <= 0x10FFFF) + { + /* four bytes, encoding 1110xxxx 10xxxxxx 10xxxxxx 10xxxxxx */ + utf8_length = 4; + first_byte_mark = 0xF0; /* 11110000 */ + } + else + { + /* invalid unicode codepoint */ + goto fail; + } + + /* encode as utf8 */ + for (utf8_position = (unsigned char)(utf8_length - 1); utf8_position > 0; utf8_position--) + { + /* 10xxxxxx */ + (*output_pointer)[utf8_position] = (unsigned char)((codepoint | 0x80) & 0xBF); + codepoint >>= 6; + } + /* encode first byte */ + if (utf8_length > 1) + { + (*output_pointer)[0] = (unsigned char)((codepoint | first_byte_mark) & 0xFF); + } + else + { + (*output_pointer)[0] = (unsigned char)(codepoint & 0x7F); + } + + *output_pointer += utf8_length; + + return sequence_length; + +fail: + return 0; +} + +/* Parse the input text into an unescaped cinput, and populate item. */ +static cJSON_bool parse_string(cJSON * const item, parse_buffer * const input_buffer) +{ + const unsigned char *input_pointer = buffer_at_offset(input_buffer) + 1; + const unsigned char *input_end = buffer_at_offset(input_buffer) + 1; + unsigned char *output_pointer = NULL; + unsigned char *output = NULL; + + /* not a string */ + if (buffer_at_offset(input_buffer)[0] != '\"') + { + goto fail; + } + + { + /* calculate approximate size of the output (overestimate) */ + size_t allocation_length = 0; + size_t skipped_bytes = 0; + while (((size_t)(input_end - input_buffer->content) < input_buffer->length) && (*input_end != '\"')) + { + /* is escape sequence */ + if (input_end[0] == '\\') + { + if ((size_t)(input_end + 1 - input_buffer->content) >= input_buffer->length) + { + /* prevent buffer overflow when last input character is a backslash */ + goto fail; + } + skipped_bytes++; + input_end++; + } + input_end++; + } + if (((size_t)(input_end - input_buffer->content) >= input_buffer->length) || (*input_end != '\"')) + { + goto fail; /* string ended unexpectedly */ + } + + /* This is at most how much we need for the output */ + allocation_length = (size_t) (input_end - buffer_at_offset(input_buffer)) - skipped_bytes; + output = (unsigned char*)input_buffer->hooks.allocate(allocation_length + sizeof("")); + if (output == NULL) + { + goto fail; /* allocation failure */ + } + } + + output_pointer = output; + /* loop through the string literal */ + while (input_pointer < input_end) + { + if (*input_pointer != '\\') + { + *output_pointer++ = *input_pointer++; + } + /* escape sequence */ + else + { + unsigned char sequence_length = 2; + if ((input_end - input_pointer) < 1) + { + goto fail; + } + + switch (input_pointer[1]) + { + case 'b': + *output_pointer++ = '\b'; + break; + case 'f': + *output_pointer++ = '\f'; + break; + case 'n': + *output_pointer++ = '\n'; + break; + case 'r': + *output_pointer++ = '\r'; + break; + case 't': + *output_pointer++ = '\t'; + break; + case '\"': + case '\\': + case '/': + *output_pointer++ = input_pointer[1]; + break; + + /* UTF-16 literal */ + case 'u': + sequence_length = utf16_literal_to_utf8(input_pointer, input_end, &output_pointer); + if (sequence_length == 0) + { + /* failed to convert UTF16-literal to UTF-8 */ + goto fail; + } + break; + + default: + goto fail; + } + input_pointer += sequence_length; + } + } + + /* zero terminate the output */ + *output_pointer = '\0'; + + item->type = cJSON_String; + item->valuestring = (char*)output; + + input_buffer->offset = (size_t) (input_end - input_buffer->content); + input_buffer->offset++; + + return true; + +fail: + if (output != NULL) + { + input_buffer->hooks.deallocate(output); + output = NULL; + } + + if (input_pointer != NULL) + { + input_buffer->offset = (size_t)(input_pointer - input_buffer->content); + } + + return false; +} + +/* Render the cstring provided to an escaped version that can be printed. */ +static cJSON_bool print_string_ptr(const unsigned char * const input, printbuffer * const output_buffer) +{ + const unsigned char *input_pointer = NULL; + unsigned char *output = NULL; + unsigned char *output_pointer = NULL; + size_t output_length = 0; + /* numbers of additional characters needed for escaping */ + size_t escape_characters = 0; + + if (output_buffer == NULL) + { + return false; + } + + /* empty string */ + if (input == NULL) + { + output = ensure(output_buffer, sizeof("\"\"")); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "\"\""); + + return true; + } + + /* set "flag" to 1 if something needs to be escaped */ + for (input_pointer = input; *input_pointer; input_pointer++) + { + switch (*input_pointer) + { + case '\"': + case '\\': + case '\b': + case '\f': + case '\n': + case '\r': + case '\t': + /* one character escape sequence */ + escape_characters++; + break; + default: + if (*input_pointer < 32) + { + /* UTF-16 escape sequence uXXXX */ + escape_characters += 5; + } + break; + } + } + output_length = (size_t)(input_pointer - input) + escape_characters; + + output = ensure(output_buffer, output_length + sizeof("\"\"")); + if (output == NULL) + { + return false; + } + + /* no characters have to be escaped */ + if (escape_characters == 0) + { + output[0] = '\"'; + memcpy(output + 1, input, output_length); + output[output_length + 1] = '\"'; + output[output_length + 2] = '\0'; + + return true; + } + + output[0] = '\"'; + output_pointer = output + 1; + /* copy the string */ + for (input_pointer = input; *input_pointer != '\0'; (void)input_pointer++, output_pointer++) + { + if ((*input_pointer > 31) && (*input_pointer != '\"') && (*input_pointer != '\\')) + { + /* normal character, copy */ + *output_pointer = *input_pointer; + } + else + { + /* character needs to be escaped */ + *output_pointer++ = '\\'; + switch (*input_pointer) + { + case '\\': + *output_pointer = '\\'; + break; + case '\"': + *output_pointer = '\"'; + break; + case '\b': + *output_pointer = 'b'; + break; + case '\f': + *output_pointer = 'f'; + break; + case '\n': + *output_pointer = 'n'; + break; + case '\r': + *output_pointer = 'r'; + break; + case '\t': + *output_pointer = 't'; + break; + default: + /* escape and print as unicode codepoint */ + sprintf((char*)output_pointer, "u%04x", *input_pointer); + output_pointer += 4; + break; + } + } + } + output[output_length + 1] = '\"'; + output[output_length + 2] = '\0'; + + return true; +} + +/* Invoke print_string_ptr (which is useful) on an item. */ +static cJSON_bool print_string(const cJSON * const item, printbuffer * const p) +{ + return print_string_ptr((unsigned char*)item->valuestring, p); +} + +/* Predeclare these prototypes. */ +static cJSON_bool parse_value(cJSON * const item, parse_buffer * const input_buffer); +static cJSON_bool print_value(const cJSON * const item, printbuffer * const output_buffer); +static cJSON_bool parse_array(cJSON * const item, parse_buffer * const input_buffer); +static cJSON_bool print_array(const cJSON * const item, printbuffer * const output_buffer); +static cJSON_bool parse_object(cJSON * const item, parse_buffer * const input_buffer); +static cJSON_bool print_object(const cJSON * const item, printbuffer * const output_buffer); + +/* Utility to jump whitespace and cr/lf */ +static parse_buffer *buffer_skip_whitespace(parse_buffer * const buffer) +{ + if ((buffer == NULL) || (buffer->content == NULL)) + { + return NULL; + } + + if (cannot_access_at_index(buffer, 0)) + { + return buffer; + } + + while (can_access_at_index(buffer, 0) && (buffer_at_offset(buffer)[0] <= 32)) + { + buffer->offset++; + } + + if (buffer->offset == buffer->length) + { + buffer->offset--; + } + + return buffer; +} + +/* skip the UTF-8 BOM (byte order mark) if it is at the beginning of a buffer */ +static parse_buffer *skip_utf8_bom(parse_buffer * const buffer) +{ + if ((buffer == NULL) || (buffer->content == NULL) || (buffer->offset != 0)) + { + return NULL; + } + + if (can_access_at_index(buffer, 4) && (strncmp((const char*)buffer_at_offset(buffer), "\xEF\xBB\xBF", 3) == 0)) + { + buffer->offset += 3; + } + + return buffer; +} + +CJSON_PUBLIC(cJSON *) cJSON_ParseWithOpts(const char *value, const char **return_parse_end, cJSON_bool require_null_terminated) +{ + size_t buffer_length; + + if (NULL == value) + { + return NULL; + } + + /* Adding null character size due to require_null_terminated. */ + buffer_length = strlen(value) + sizeof(""); + + return cJSON_ParseWithLengthOpts(value, buffer_length, return_parse_end, require_null_terminated); +} + +/* Parse an object - create a new root, and populate. */ +CJSON_PUBLIC(cJSON *) cJSON_ParseWithLengthOpts(const char *value, size_t buffer_length, const char **return_parse_end, cJSON_bool require_null_terminated) +{ + parse_buffer buffer = { 0, 0, 0, 0, { 0, 0, 0 } }; + cJSON *item = NULL; + + /* reset error position */ + global_error.json = NULL; + global_error.position = 0; + + if (value == NULL || 0 == buffer_length) + { + goto fail; + } + + buffer.content = (const unsigned char*)value; + buffer.length = buffer_length; + buffer.offset = 0; + buffer.hooks = global_hooks; + + item = cJSON_New_Item(&global_hooks); + if (item == NULL) /* memory fail */ + { + goto fail; + } + + if (!parse_value(item, buffer_skip_whitespace(skip_utf8_bom(&buffer)))) + { + /* parse failure. ep is set. */ + goto fail; + } + + /* if we require null-terminated JSON without appended garbage, skip and then check for a null terminator */ + if (require_null_terminated) + { + buffer_skip_whitespace(&buffer); + if ((buffer.offset >= buffer.length) || buffer_at_offset(&buffer)[0] != '\0') + { + goto fail; + } + } + if (return_parse_end) + { + *return_parse_end = (const char*)buffer_at_offset(&buffer); + } + + return item; + +fail: + if (item != NULL) + { + cJSON_Delete(item); + } + + if (value != NULL) + { + error local_error; + local_error.json = (const unsigned char*)value; + local_error.position = 0; + + if (buffer.offset < buffer.length) + { + local_error.position = buffer.offset; + } + else if (buffer.length > 0) + { + local_error.position = buffer.length - 1; + } + + if (return_parse_end != NULL) + { + *return_parse_end = (const char*)local_error.json + local_error.position; + } + + global_error = local_error; + } + + return NULL; +} + +/* Default options for cJSON_Parse */ +CJSON_PUBLIC(cJSON *) cJSON_Parse(const char *value) +{ + return cJSON_ParseWithOpts(value, 0, 0); +} + +CJSON_PUBLIC(cJSON *) cJSON_ParseWithLength(const char *value, size_t buffer_length) +{ + return cJSON_ParseWithLengthOpts(value, buffer_length, 0, 0); +} + +#define cjson_min(a, b) (((a) < (b)) ? (a) : (b)) + +static unsigned char *print(const cJSON * const item, cJSON_bool format, const internal_hooks * const hooks) +{ + static const size_t default_buffer_size = 256; + printbuffer buffer[1]; + unsigned char *printed = NULL; + + memset(buffer, 0, sizeof(buffer)); + + /* create buffer */ + buffer->buffer = (unsigned char*) hooks->allocate(default_buffer_size); + buffer->length = default_buffer_size; + buffer->format = format; + buffer->hooks = *hooks; + if (buffer->buffer == NULL) + { + goto fail; + } + + /* print the value */ + if (!print_value(item, buffer)) + { + goto fail; + } + update_offset(buffer); + + /* check if reallocate is available */ + if (hooks->reallocate != NULL) + { + printed = (unsigned char*) hooks->reallocate(buffer->buffer, buffer->offset + 1); + if (printed == NULL) { + goto fail; + } + buffer->buffer = NULL; + } + else /* otherwise copy the JSON over to a new buffer */ + { + printed = (unsigned char*) hooks->allocate(buffer->offset + 1); + if (printed == NULL) + { + goto fail; + } + memcpy(printed, buffer->buffer, cjson_min(buffer->length, buffer->offset + 1)); + printed[buffer->offset] = '\0'; /* just to be sure */ + + /* free the buffer */ + hooks->deallocate(buffer->buffer); + buffer->buffer = NULL; + } + + return printed; + +fail: + if (buffer->buffer != NULL) + { + hooks->deallocate(buffer->buffer); + buffer->buffer = NULL; + } + + if (printed != NULL) + { + hooks->deallocate(printed); + printed = NULL; + } + + return NULL; +} + +/* Render a cJSON item/entity/structure to text. */ +CJSON_PUBLIC(char *) cJSON_Print(const cJSON *item) +{ + return (char*)print(item, true, &global_hooks); +} + +CJSON_PUBLIC(char *) cJSON_PrintUnformatted(const cJSON *item) +{ + return (char*)print(item, false, &global_hooks); +} + +CJSON_PUBLIC(char *) cJSON_PrintBuffered(const cJSON *item, int prebuffer, cJSON_bool fmt) +{ + printbuffer p = { 0, 0, 0, 0, 0, 0, { 0, 0, 0 } }; + + if (prebuffer < 0) + { + return NULL; + } + + p.buffer = (unsigned char*)global_hooks.allocate((size_t)prebuffer); + if (!p.buffer) + { + return NULL; + } + + p.length = (size_t)prebuffer; + p.offset = 0; + p.noalloc = false; + p.format = fmt; + p.hooks = global_hooks; + + if (!print_value(item, &p)) + { + global_hooks.deallocate(p.buffer); + p.buffer = NULL; + return NULL; + } + + return (char*)p.buffer; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_PrintPreallocated(cJSON *item, char *buffer, const int length, const cJSON_bool format) +{ + printbuffer p = { 0, 0, 0, 0, 0, 0, { 0, 0, 0 } }; + + if ((length < 0) || (buffer == NULL)) + { + return false; + } + + p.buffer = (unsigned char*)buffer; + p.length = (size_t)length; + p.offset = 0; + p.noalloc = true; + p.format = format; + p.hooks = global_hooks; + + return print_value(item, &p); +} + +/* Parser core - when encountering text, process appropriately. */ +static cJSON_bool parse_value(cJSON * const item, parse_buffer * const input_buffer) +{ + if ((input_buffer == NULL) || (input_buffer->content == NULL)) + { + return false; /* no input */ + } + + /* parse the different types of values */ + /* null */ + if (can_read(input_buffer, 4) && (strncmp((const char*)buffer_at_offset(input_buffer), "null", 4) == 0)) + { + item->type = cJSON_NULL; + input_buffer->offset += 4; + return true; + } + /* false */ + if (can_read(input_buffer, 5) && (strncmp((const char*)buffer_at_offset(input_buffer), "false", 5) == 0)) + { + item->type = cJSON_False; + input_buffer->offset += 5; + return true; + } + /* true */ + if (can_read(input_buffer, 4) && (strncmp((const char*)buffer_at_offset(input_buffer), "true", 4) == 0)) + { + item->type = cJSON_True; + item->valueint = 1; + input_buffer->offset += 4; + return true; + } + /* string */ + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '\"')) + { + return parse_string(item, input_buffer); + } + /* number */ + if (can_access_at_index(input_buffer, 0) && ((buffer_at_offset(input_buffer)[0] == '-') || ((buffer_at_offset(input_buffer)[0] >= '0') && (buffer_at_offset(input_buffer)[0] <= '9')))) + { + return parse_number(item, input_buffer); + } + /* array */ + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '[')) + { + return parse_array(item, input_buffer); + } + /* object */ + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '{')) + { + return parse_object(item, input_buffer); + } + + return false; +} + +/* Render a value to text. */ +static cJSON_bool print_value(const cJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output = NULL; + + if ((item == NULL) || (output_buffer == NULL)) + { + return false; + } + + switch ((item->type) & 0xFF) + { + case cJSON_NULL: + output = ensure(output_buffer, 5); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "null"); + return true; + + case cJSON_False: + output = ensure(output_buffer, 6); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "false"); + return true; + + case cJSON_True: + output = ensure(output_buffer, 5); + if (output == NULL) + { + return false; + } + strcpy((char*)output, "true"); + return true; + + case cJSON_Number: + return print_number(item, output_buffer); + + case cJSON_Raw: + { + size_t raw_length = 0; + if (item->valuestring == NULL) + { + return false; + } + + raw_length = strlen(item->valuestring) + sizeof(""); + output = ensure(output_buffer, raw_length); + if (output == NULL) + { + return false; + } + memcpy(output, item->valuestring, raw_length); + return true; + } + + case cJSON_String: + return print_string(item, output_buffer); + + case cJSON_Array: + return print_array(item, output_buffer); + + case cJSON_Object: + return print_object(item, output_buffer); + + default: + return false; + } +} + +/* Build an array from input text. */ +static cJSON_bool parse_array(cJSON * const item, parse_buffer * const input_buffer) +{ + cJSON *head = NULL; /* head of the linked list */ + cJSON *current_item = NULL; + + if (input_buffer->depth >= CJSON_NESTING_LIMIT) + { + return false; /* to deeply nested */ + } + input_buffer->depth++; + + if (buffer_at_offset(input_buffer)[0] != '[') + { + /* not an array */ + goto fail; + } + + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ']')) + { + /* empty array */ + goto success; + } + + /* check if we skipped to the end of the buffer */ + if (cannot_access_at_index(input_buffer, 0)) + { + input_buffer->offset--; + goto fail; + } + + /* step back to character in front of the first element */ + input_buffer->offset--; + /* loop through the comma separated array elements */ + do + { + /* allocate next item */ + cJSON *new_item = cJSON_New_Item(&(input_buffer->hooks)); + if (new_item == NULL) + { + goto fail; /* allocation failure */ + } + + /* attach next item to list */ + if (head == NULL) + { + /* start the linked list */ + current_item = head = new_item; + } + else + { + /* add to the end and advance */ + current_item->next = new_item; + new_item->prev = current_item; + current_item = new_item; + } + + /* parse next value */ + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (!parse_value(current_item, input_buffer)) + { + goto fail; /* failed to parse value */ + } + buffer_skip_whitespace(input_buffer); + } + while (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ',')); + + if (cannot_access_at_index(input_buffer, 0) || buffer_at_offset(input_buffer)[0] != ']') + { + goto fail; /* expected end of array */ + } + +success: + input_buffer->depth--; + + if (head != NULL) { + head->prev = current_item; + } + + item->type = cJSON_Array; + item->child = head; + + input_buffer->offset++; + + return true; + +fail: + if (head != NULL) + { + cJSON_Delete(head); + } + + return false; +} + +/* Render an array to text */ +static cJSON_bool print_array(const cJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output_pointer = NULL; + size_t length = 0; + cJSON *current_element = item->child; + + if (output_buffer == NULL) + { + return false; + } + + /* Compose the output array. */ + /* opening square bracket */ + output_pointer = ensure(output_buffer, 1); + if (output_pointer == NULL) + { + return false; + } + + *output_pointer = '['; + output_buffer->offset++; + output_buffer->depth++; + + while (current_element != NULL) + { + if (!print_value(current_element, output_buffer)) + { + return false; + } + update_offset(output_buffer); + if (current_element->next) + { + length = (size_t) (output_buffer->format ? 2 : 1); + output_pointer = ensure(output_buffer, length + 1); + if (output_pointer == NULL) + { + return false; + } + *output_pointer++ = ','; + if(output_buffer->format) + { + *output_pointer++ = ' '; + } + *output_pointer = '\0'; + output_buffer->offset += length; + } + current_element = current_element->next; + } + + output_pointer = ensure(output_buffer, 2); + if (output_pointer == NULL) + { + return false; + } + *output_pointer++ = ']'; + *output_pointer = '\0'; + output_buffer->depth--; + + return true; +} + +/* Build an object from the text. */ +static cJSON_bool parse_object(cJSON * const item, parse_buffer * const input_buffer) +{ + cJSON *head = NULL; /* linked list head */ + cJSON *current_item = NULL; + + if (input_buffer->depth >= CJSON_NESTING_LIMIT) + { + return false; /* to deeply nested */ + } + input_buffer->depth++; + + if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != '{')) + { + goto fail; /* not an object */ + } + + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == '}')) + { + goto success; /* empty object */ + } + + /* check if we skipped to the end of the buffer */ + if (cannot_access_at_index(input_buffer, 0)) + { + input_buffer->offset--; + goto fail; + } + + /* step back to character in front of the first element */ + input_buffer->offset--; + /* loop through the comma separated array elements */ + do + { + /* allocate next item */ + cJSON *new_item = cJSON_New_Item(&(input_buffer->hooks)); + if (new_item == NULL) + { + goto fail; /* allocation failure */ + } + + /* attach next item to list */ + if (head == NULL) + { + /* start the linked list */ + current_item = head = new_item; + } + else + { + /* add to the end and advance */ + current_item->next = new_item; + new_item->prev = current_item; + current_item = new_item; + } + + if (cannot_access_at_index(input_buffer, 1)) + { + goto fail; /* nothing comes after the comma */ + } + + /* parse the name of the child */ + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (!parse_string(current_item, input_buffer)) + { + goto fail; /* failed to parse name */ + } + buffer_skip_whitespace(input_buffer); + + /* swap valuestring and string, because we parsed the name */ + current_item->string = current_item->valuestring; + current_item->valuestring = NULL; + + if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != ':')) + { + goto fail; /* invalid object */ + } + + /* parse the value */ + input_buffer->offset++; + buffer_skip_whitespace(input_buffer); + if (!parse_value(current_item, input_buffer)) + { + goto fail; /* failed to parse value */ + } + buffer_skip_whitespace(input_buffer); + } + while (can_access_at_index(input_buffer, 0) && (buffer_at_offset(input_buffer)[0] == ',')); + + if (cannot_access_at_index(input_buffer, 0) || (buffer_at_offset(input_buffer)[0] != '}')) + { + goto fail; /* expected end of object */ + } + +success: + input_buffer->depth--; + + if (head != NULL) { + head->prev = current_item; + } + + item->type = cJSON_Object; + item->child = head; + + input_buffer->offset++; + return true; + +fail: + if (head != NULL) + { + cJSON_Delete(head); + } + + return false; +} + +/* Render an object to text. */ +static cJSON_bool print_object(const cJSON * const item, printbuffer * const output_buffer) +{ + unsigned char *output_pointer = NULL; + size_t length = 0; + cJSON *current_item = item->child; + + if (output_buffer == NULL) + { + return false; + } + + /* Compose the output: */ + length = (size_t) (output_buffer->format ? 2 : 1); /* fmt: {\n */ + output_pointer = ensure(output_buffer, length + 1); + if (output_pointer == NULL) + { + return false; + } + + *output_pointer++ = '{'; + output_buffer->depth++; + if (output_buffer->format) + { + *output_pointer++ = '\n'; + } + output_buffer->offset += length; + + while (current_item) + { + if (output_buffer->format) + { + size_t i; + output_pointer = ensure(output_buffer, output_buffer->depth); + if (output_pointer == NULL) + { + return false; + } + for (i = 0; i < output_buffer->depth; i++) + { + *output_pointer++ = '\t'; + } + output_buffer->offset += output_buffer->depth; + } + + /* print key */ + if (!print_string_ptr((unsigned char*)current_item->string, output_buffer)) + { + return false; + } + update_offset(output_buffer); + + length = (size_t) (output_buffer->format ? 2 : 1); + output_pointer = ensure(output_buffer, length); + if (output_pointer == NULL) + { + return false; + } + *output_pointer++ = ':'; + if (output_buffer->format) + { + *output_pointer++ = '\t'; + } + output_buffer->offset += length; + + /* print value */ + if (!print_value(current_item, output_buffer)) + { + return false; + } + update_offset(output_buffer); + + /* print comma if not last */ + length = ((size_t)(output_buffer->format ? 1 : 0) + (size_t)(current_item->next ? 1 : 0)); + output_pointer = ensure(output_buffer, length + 1); + if (output_pointer == NULL) + { + return false; + } + if (current_item->next) + { + *output_pointer++ = ','; + } + + if (output_buffer->format) + { + *output_pointer++ = '\n'; + } + *output_pointer = '\0'; + output_buffer->offset += length; + + current_item = current_item->next; + } + + output_pointer = ensure(output_buffer, output_buffer->format ? (output_buffer->depth + 1) : 2); + if (output_pointer == NULL) + { + return false; + } + if (output_buffer->format) + { + size_t i; + for (i = 0; i < (output_buffer->depth - 1); i++) + { + *output_pointer++ = '\t'; + } + } + *output_pointer++ = '}'; + *output_pointer = '\0'; + output_buffer->depth--; + + return true; +} + +/* Get Array size/item / object item. */ +CJSON_PUBLIC(int) cJSON_GetArraySize(const cJSON *array) +{ + cJSON *child = NULL; + size_t size = 0; + + if (array == NULL) + { + return 0; + } + + child = array->child; + + while(child != NULL) + { + size++; + child = child->next; + } + + /* FIXME: Can overflow here. Cannot be fixed without breaking the API */ + + return (int)size; +} + +static cJSON* get_array_item(const cJSON *array, size_t index) +{ + cJSON *current_child = NULL; + + if (array == NULL) + { + return NULL; + } + + current_child = array->child; + while ((current_child != NULL) && (index > 0)) + { + index--; + current_child = current_child->next; + } + + return current_child; +} + +CJSON_PUBLIC(cJSON *) cJSON_GetArrayItem(const cJSON *array, int index) +{ + if (index < 0) + { + return NULL; + } + + return get_array_item(array, (size_t)index); +} + +static cJSON *get_object_item(const cJSON * const object, const char * const name, const cJSON_bool case_sensitive) +{ + cJSON *current_element = NULL; + + if ((object == NULL) || (name == NULL)) + { + return NULL; + } + + current_element = object->child; + if (case_sensitive) + { + while ((current_element != NULL) && (current_element->string != NULL) && (strcmp(name, current_element->string) != 0)) + { + current_element = current_element->next; + } + } + else + { + while ((current_element != NULL) && (case_insensitive_strcmp((const unsigned char*)name, (const unsigned char*)(current_element->string)) != 0)) + { + current_element = current_element->next; + } + } + + if ((current_element == NULL) || (current_element->string == NULL)) { + return NULL; + } + + return current_element; +} + +CJSON_PUBLIC(cJSON *) cJSON_GetObjectItem(const cJSON * const object, const char * const string) +{ + return get_object_item(object, string, false); +} + +CJSON_PUBLIC(cJSON *) cJSON_GetObjectItemCaseSensitive(const cJSON * const object, const char * const string) +{ + return get_object_item(object, string, true); +} + +CJSON_PUBLIC(cJSON_bool) cJSON_HasObjectItem(const cJSON *object, const char *string) +{ + return cJSON_GetObjectItem(object, string) ? 1 : 0; +} + +/* Utility for array list handling. */ +static void suffix_object(cJSON *prev, cJSON *item) +{ + prev->next = item; + item->prev = prev; +} + +/* Utility for handling references. */ +static cJSON *create_reference(const cJSON *item, const internal_hooks * const hooks) +{ + cJSON *reference = NULL; + if (item == NULL) + { + return NULL; + } + + reference = cJSON_New_Item(hooks); + if (reference == NULL) + { + return NULL; + } + + memcpy(reference, item, sizeof(cJSON)); + reference->string = NULL; + reference->type |= cJSON_IsReference; + reference->next = reference->prev = NULL; + return reference; +} + +static cJSON_bool add_item_to_array(cJSON *array, cJSON *item) +{ + cJSON *child = NULL; + + if ((item == NULL) || (array == NULL) || (array == item)) + { + return false; + } + + child = array->child; + /* + * To find the last item in array quickly, we use prev in array + */ + if (child == NULL) + { + /* list is empty, start new one */ + array->child = item; + item->prev = item; + item->next = NULL; + } + else + { + /* append to the end */ + if (child->prev) + { + suffix_object(child->prev, item); + array->child->prev = item; + } + } + + return true; +} + +/* Add item to array/object. */ +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToArray(cJSON *array, cJSON *item) +{ + return add_item_to_array(array, item); +} + +#if defined(__clang__) || (defined(__GNUC__) && ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ > 5)))) + #pragma GCC diagnostic push +#endif +#ifdef __GNUC__ +#pragma GCC diagnostic ignored "-Wcast-qual" +#endif +/* helper function to cast away const */ +static void* cast_away_const(const void* string) +{ + return (void*)string; +} +#if defined(__clang__) || (defined(__GNUC__) && ((__GNUC__ > 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ > 5)))) + #pragma GCC diagnostic pop +#endif + + +static cJSON_bool add_item_to_object(cJSON * const object, const char * const string, cJSON * const item, const internal_hooks * const hooks, const cJSON_bool constant_key) +{ + char *new_key = NULL; + int new_type = cJSON_Invalid; + + if ((object == NULL) || (string == NULL) || (item == NULL) || (object == item)) + { + return false; + } + + if (constant_key) + { + new_key = (char*)cast_away_const(string); + new_type = item->type | cJSON_StringIsConst; + } + else + { + new_key = (char*)cJSON_strdup((const unsigned char*)string, hooks); + if (new_key == NULL) + { + return false; + } + + new_type = item->type & ~cJSON_StringIsConst; + } + + if (!(item->type & cJSON_StringIsConst) && (item->string != NULL)) + { + hooks->deallocate(item->string); + } + + item->string = new_key; + item->type = new_type; + + return add_item_to_array(object, item); +} + +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToObject(cJSON *object, const char *string, cJSON *item) +{ + return add_item_to_object(object, string, item, &global_hooks, false); +} + +/* Add an item to an object with constant string as key */ +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToObjectCS(cJSON *object, const char *string, cJSON *item) +{ + return add_item_to_object(object, string, item, &global_hooks, true); +} + +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item) +{ + if (array == NULL) + { + return false; + } + + return add_item_to_array(array, create_reference(item, &global_hooks)); +} + +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemReferenceToObject(cJSON *object, const char *string, cJSON *item) +{ + if ((object == NULL) || (string == NULL)) + { + return false; + } + + return add_item_to_object(object, string, create_reference(item, &global_hooks), &global_hooks, false); +} + +CJSON_PUBLIC(cJSON*) cJSON_AddNullToObject(cJSON * const object, const char * const name) +{ + cJSON *null = cJSON_CreateNull(); + if (add_item_to_object(object, name, null, &global_hooks, false)) + { + return null; + } + + cJSON_Delete(null); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddTrueToObject(cJSON * const object, const char * const name) +{ + cJSON *true_item = cJSON_CreateTrue(); + if (add_item_to_object(object, name, true_item, &global_hooks, false)) + { + return true_item; + } + + cJSON_Delete(true_item); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddFalseToObject(cJSON * const object, const char * const name) +{ + cJSON *false_item = cJSON_CreateFalse(); + if (add_item_to_object(object, name, false_item, &global_hooks, false)) + { + return false_item; + } + + cJSON_Delete(false_item); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddBoolToObject(cJSON * const object, const char * const name, const cJSON_bool boolean) +{ + cJSON *bool_item = cJSON_CreateBool(boolean); + if (add_item_to_object(object, name, bool_item, &global_hooks, false)) + { + return bool_item; + } + + cJSON_Delete(bool_item); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddNumberToObject(cJSON * const object, const char * const name, const double number) +{ + cJSON *number_item = cJSON_CreateNumber(number); + if (add_item_to_object(object, name, number_item, &global_hooks, false)) + { + return number_item; + } + + cJSON_Delete(number_item); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddStringToObject(cJSON * const object, const char * const name, const char * const string) +{ + cJSON *string_item = cJSON_CreateString(string); + if (add_item_to_object(object, name, string_item, &global_hooks, false)) + { + return string_item; + } + + cJSON_Delete(string_item); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddRawToObject(cJSON * const object, const char * const name, const char * const raw) +{ + cJSON *raw_item = cJSON_CreateRaw(raw); + if (add_item_to_object(object, name, raw_item, &global_hooks, false)) + { + return raw_item; + } + + cJSON_Delete(raw_item); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddObjectToObject(cJSON * const object, const char * const name) +{ + cJSON *object_item = cJSON_CreateObject(); + if (add_item_to_object(object, name, object_item, &global_hooks, false)) + { + return object_item; + } + + cJSON_Delete(object_item); + return NULL; +} + +CJSON_PUBLIC(cJSON*) cJSON_AddArrayToObject(cJSON * const object, const char * const name) +{ + cJSON *array = cJSON_CreateArray(); + if (add_item_to_object(object, name, array, &global_hooks, false)) + { + return array; + } + + cJSON_Delete(array); + return NULL; +} + +CJSON_PUBLIC(cJSON *) cJSON_DetachItemViaPointer(cJSON *parent, cJSON * const item) +{ + if ((parent == NULL) || (item == NULL) || (item != parent->child && item->prev == NULL)) + { + return NULL; + } + + if (item != parent->child) + { + /* not the first element */ + item->prev->next = item->next; + } + if (item->next != NULL) + { + /* not the last element */ + item->next->prev = item->prev; + } + + if (item == parent->child) + { + /* first element */ + parent->child = item->next; + } + else if (item->next == NULL) + { + /* last element */ + parent->child->prev = item->prev; + } + + /* make sure the detached item doesn't point anywhere anymore */ + item->prev = NULL; + item->next = NULL; + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromArray(cJSON *array, int which) +{ + if (which < 0) + { + return NULL; + } + + return cJSON_DetachItemViaPointer(array, get_array_item(array, (size_t)which)); +} + +CJSON_PUBLIC(void) cJSON_DeleteItemFromArray(cJSON *array, int which) +{ + cJSON_Delete(cJSON_DetachItemFromArray(array, which)); +} + +CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObject(cJSON *object, const char *string) +{ + cJSON *to_detach = cJSON_GetObjectItem(object, string); + + return cJSON_DetachItemViaPointer(object, to_detach); +} + +CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObjectCaseSensitive(cJSON *object, const char *string) +{ + cJSON *to_detach = cJSON_GetObjectItemCaseSensitive(object, string); + + return cJSON_DetachItemViaPointer(object, to_detach); +} + +CJSON_PUBLIC(void) cJSON_DeleteItemFromObject(cJSON *object, const char *string) +{ + cJSON_Delete(cJSON_DetachItemFromObject(object, string)); +} + +CJSON_PUBLIC(void) cJSON_DeleteItemFromObjectCaseSensitive(cJSON *object, const char *string) +{ + cJSON_Delete(cJSON_DetachItemFromObjectCaseSensitive(object, string)); +} + +/* Replace array/object items with new ones. */ +CJSON_PUBLIC(cJSON_bool) cJSON_InsertItemInArray(cJSON *array, int which, cJSON *newitem) +{ + cJSON *after_inserted = NULL; + + if (which < 0 || newitem == NULL) + { + return false; + } + + after_inserted = get_array_item(array, (size_t)which); + if (after_inserted == NULL) + { + return add_item_to_array(array, newitem); + } + + if (after_inserted != array->child && after_inserted->prev == NULL) { + /* return false if after_inserted is a corrupted array item */ + return false; + } + + newitem->next = after_inserted; + newitem->prev = after_inserted->prev; + after_inserted->prev = newitem; + if (after_inserted == array->child) + { + array->child = newitem; + } + else + { + newitem->prev->next = newitem; + } + return true; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemViaPointer(cJSON * const parent, cJSON * const item, cJSON * replacement) +{ + if ((parent == NULL) || (parent->child == NULL) || (replacement == NULL) || (item == NULL)) + { + return false; + } + + if (replacement == item) + { + return true; + } + + replacement->next = item->next; + replacement->prev = item->prev; + + if (replacement->next != NULL) + { + replacement->next->prev = replacement; + } + if (parent->child == item) + { + if (parent->child->prev == parent->child) + { + replacement->prev = replacement; + } + parent->child = replacement; + } + else + { /* + * To find the last item in array quickly, we use prev in array. + * We can't modify the last item's next pointer where this item was the parent's child + */ + if (replacement->prev != NULL) + { + replacement->prev->next = replacement; + } + if (replacement->next == NULL) + { + parent->child->prev = replacement; + } + } + + item->next = NULL; + item->prev = NULL; + cJSON_Delete(item); + + return true; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInArray(cJSON *array, int which, cJSON *newitem) +{ + if (which < 0) + { + return false; + } + + return cJSON_ReplaceItemViaPointer(array, get_array_item(array, (size_t)which), newitem); +} + +static cJSON_bool replace_item_in_object(cJSON *object, const char *string, cJSON *replacement, cJSON_bool case_sensitive) +{ + if ((replacement == NULL) || (string == NULL)) + { + return false; + } + + /* replace the name in the replacement */ + if (!(replacement->type & cJSON_StringIsConst) && (replacement->string != NULL)) + { + cJSON_free(replacement->string); + } + replacement->string = (char*)cJSON_strdup((const unsigned char*)string, &global_hooks); + if (replacement->string == NULL) + { + return false; + } + + replacement->type &= ~cJSON_StringIsConst; + + return cJSON_ReplaceItemViaPointer(object, get_object_item(object, string, case_sensitive), replacement); +} + +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInObject(cJSON *object, const char *string, cJSON *newitem) +{ + return replace_item_in_object(object, string, newitem, false); +} + +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInObjectCaseSensitive(cJSON *object, const char *string, cJSON *newitem) +{ + return replace_item_in_object(object, string, newitem, true); +} + +/* Create basic types: */ +CJSON_PUBLIC(cJSON *) cJSON_CreateNull(void) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type = cJSON_NULL; + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateTrue(void) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type = cJSON_True; + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateFalse(void) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type = cJSON_False; + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateBool(cJSON_bool boolean) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type = boolean ? cJSON_True : cJSON_False; + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateNumber(double num) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type = cJSON_Number; + item->valuedouble = num; + + /* use saturation in case of overflow */ + if (num >= INT_MAX) + { + item->valueint = INT_MAX; + } + else if (num <= (double)INT_MIN) + { + item->valueint = INT_MIN; + } + else + { + item->valueint = (int)num; + } + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateString(const char *string) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type = cJSON_String; + item->valuestring = (char*)cJSON_strdup((const unsigned char*)string, &global_hooks); + if(!item->valuestring) + { + cJSON_Delete(item); + return NULL; + } + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateStringReference(const char *string) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if (item != NULL) + { + item->type = cJSON_String | cJSON_IsReference; + item->valuestring = (char*)cast_away_const(string); + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateObjectReference(const cJSON *child) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if (item != NULL) { + item->type = cJSON_Object | cJSON_IsReference; + item->child = (cJSON*)cast_away_const(child); + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateArrayReference(const cJSON *child) { + cJSON *item = cJSON_New_Item(&global_hooks); + if (item != NULL) { + item->type = cJSON_Array | cJSON_IsReference; + item->child = (cJSON*)cast_away_const(child); + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateRaw(const char *raw) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type = cJSON_Raw; + item->valuestring = (char*)cJSON_strdup((const unsigned char*)raw, &global_hooks); + if(!item->valuestring) + { + cJSON_Delete(item); + return NULL; + } + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateArray(void) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if(item) + { + item->type=cJSON_Array; + } + + return item; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateObject(void) +{ + cJSON *item = cJSON_New_Item(&global_hooks); + if (item) + { + item->type = cJSON_Object; + } + + return item; +} + +/* Create Arrays: */ +CJSON_PUBLIC(cJSON *) cJSON_CreateIntArray(const int *numbers, int count) +{ + size_t i = 0; + cJSON *n = NULL; + cJSON *p = NULL; + cJSON *a = NULL; + + if ((count < 0) || (numbers == NULL)) + { + return NULL; + } + + a = cJSON_CreateArray(); + + for(i = 0; a && (i < (size_t)count); i++) + { + n = cJSON_CreateNumber(numbers[i]); + if (!n) + { + cJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p, n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateFloatArray(const float *numbers, int count) +{ + size_t i = 0; + cJSON *n = NULL; + cJSON *p = NULL; + cJSON *a = NULL; + + if ((count < 0) || (numbers == NULL)) + { + return NULL; + } + + a = cJSON_CreateArray(); + + for(i = 0; a && (i < (size_t)count); i++) + { + n = cJSON_CreateNumber((double)numbers[i]); + if(!n) + { + cJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p, n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateDoubleArray(const double *numbers, int count) +{ + size_t i = 0; + cJSON *n = NULL; + cJSON *p = NULL; + cJSON *a = NULL; + + if ((count < 0) || (numbers == NULL)) + { + return NULL; + } + + a = cJSON_CreateArray(); + + for(i = 0; a && (i < (size_t)count); i++) + { + n = cJSON_CreateNumber(numbers[i]); + if(!n) + { + cJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p, n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +CJSON_PUBLIC(cJSON *) cJSON_CreateStringArray(const char *const *strings, int count) +{ + size_t i = 0; + cJSON *n = NULL; + cJSON *p = NULL; + cJSON *a = NULL; + + if ((count < 0) || (strings == NULL)) + { + return NULL; + } + + a = cJSON_CreateArray(); + + for (i = 0; a && (i < (size_t)count); i++) + { + n = cJSON_CreateString(strings[i]); + if(!n) + { + cJSON_Delete(a); + return NULL; + } + if(!i) + { + a->child = n; + } + else + { + suffix_object(p,n); + } + p = n; + } + + if (a && a->child) { + a->child->prev = n; + } + + return a; +} + +/* Duplication */ +cJSON * cJSON_Duplicate_rec(const cJSON *item, size_t depth, cJSON_bool recurse); + +CJSON_PUBLIC(cJSON *) cJSON_Duplicate(const cJSON *item, cJSON_bool recurse) +{ + return cJSON_Duplicate_rec(item, 0, recurse ); +} + +cJSON * cJSON_Duplicate_rec(const cJSON *item, size_t depth, cJSON_bool recurse) +{ + cJSON *newitem = NULL; + cJSON *child = NULL; + cJSON *next = NULL; + cJSON *newchild = NULL; + + /* Bail on bad ptr */ + if (!item) + { + goto fail; + } + /* Create new item */ + newitem = cJSON_New_Item(&global_hooks); + if (!newitem) + { + goto fail; + } + /* Copy over all vars */ + newitem->type = item->type & (~cJSON_IsReference); + newitem->valueint = item->valueint; + newitem->valuedouble = item->valuedouble; + if (item->valuestring) + { + newitem->valuestring = (char*)cJSON_strdup((unsigned char*)item->valuestring, &global_hooks); + if (!newitem->valuestring) + { + goto fail; + } + } + if (item->string) + { + newitem->string = (item->type&cJSON_StringIsConst) ? item->string : (char*)cJSON_strdup((unsigned char*)item->string, &global_hooks); + if (!newitem->string) + { + goto fail; + } + } + /* If non-recursive, then we're done! */ + if (!recurse) + { + return newitem; + } + /* Walk the ->next chain for the child. */ + child = item->child; + while (child != NULL) + { + if(depth >= CJSON_CIRCULAR_LIMIT) { + goto fail; + } + newchild = cJSON_Duplicate_rec(child, depth + 1, true); /* Duplicate (with recurse) each item in the ->next chain */ + if (!newchild) + { + goto fail; + } + if (next != NULL) + { + /* If newitem->child already set, then crosswire ->prev and ->next and move on */ + next->next = newchild; + newchild->prev = next; + next = newchild; + } + else + { + /* Set newitem->child and move to it */ + newitem->child = newchild; + next = newchild; + } + child = child->next; + } + if (newitem && newitem->child) + { + newitem->child->prev = newchild; + } + + return newitem; + +fail: + if (newitem != NULL) + { + cJSON_Delete(newitem); + } + + return NULL; +} + +static void skip_oneline_comment(char **input) +{ + *input += static_strlen("//"); + + for (; (*input)[0] != '\0'; ++(*input)) + { + if ((*input)[0] == '\n') { + *input += static_strlen("\n"); + return; + } + } +} + +static void skip_multiline_comment(char **input) +{ + *input += static_strlen("/*"); + + for (; (*input)[0] != '\0'; ++(*input)) + { + if (((*input)[0] == '*') && ((*input)[1] == '/')) + { + *input += static_strlen("*/"); + return; + } + } +} + +static void minify_string(char **input, char **output) { + (*output)[0] = (*input)[0]; + *input += static_strlen("\""); + *output += static_strlen("\""); + + + for (; (*input)[0] != '\0'; (void)++(*input), ++(*output)) { + (*output)[0] = (*input)[0]; + + if ((*input)[0] == '\"') { + (*output)[0] = '\"'; + *input += static_strlen("\""); + *output += static_strlen("\""); + return; + } else if (((*input)[0] == '\\') && ((*input)[1] == '\"')) { + (*output)[1] = (*input)[1]; + *input += static_strlen("\""); + *output += static_strlen("\""); + } + } +} + +CJSON_PUBLIC(void) cJSON_Minify(char *json) +{ + char *into = json; + + if (json == NULL) + { + return; + } + + while (json[0] != '\0') + { + switch (json[0]) + { + case ' ': + case '\t': + case '\r': + case '\n': + json++; + break; + + case '/': + if (json[1] == '/') + { + skip_oneline_comment(&json); + } + else if (json[1] == '*') + { + skip_multiline_comment(&json); + } else { + json++; + } + break; + + case '\"': + minify_string(&json, (char**)&into); + break; + + default: + into[0] = json[0]; + json++; + into++; + } + } + + /* and null-terminate. */ + *into = '\0'; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsInvalid(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_Invalid; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsFalse(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_False; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsTrue(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xff) == cJSON_True; +} + + +CJSON_PUBLIC(cJSON_bool) cJSON_IsBool(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & (cJSON_True | cJSON_False)) != 0; +} +CJSON_PUBLIC(cJSON_bool) cJSON_IsNull(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_NULL; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsNumber(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_Number; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsString(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_String; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsArray(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_Array; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsObject(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_Object; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_IsRaw(const cJSON * const item) +{ + if (item == NULL) + { + return false; + } + + return (item->type & 0xFF) == cJSON_Raw; +} + +CJSON_PUBLIC(cJSON_bool) cJSON_Compare(const cJSON * const a, const cJSON * const b, const cJSON_bool case_sensitive) +{ + if ((a == NULL) || (b == NULL) || ((a->type & 0xFF) != (b->type & 0xFF))) + { + return false; + } + + /* check if type is valid */ + switch (a->type & 0xFF) + { + case cJSON_False: + case cJSON_True: + case cJSON_NULL: + case cJSON_Number: + case cJSON_String: + case cJSON_Raw: + case cJSON_Array: + case cJSON_Object: + break; + + default: + return false; + } + + /* identical objects are equal */ + if (a == b) + { + return true; + } + + switch (a->type & 0xFF) + { + /* in these cases and equal type is enough */ + case cJSON_False: + case cJSON_True: + case cJSON_NULL: + return true; + + case cJSON_Number: + if (compare_double(a->valuedouble, b->valuedouble)) + { + return true; + } + return false; + + case cJSON_String: + case cJSON_Raw: + if ((a->valuestring == NULL) || (b->valuestring == NULL)) + { + return false; + } + if (strcmp(a->valuestring, b->valuestring) == 0) + { + return true; + } + + return false; + + case cJSON_Array: + { + cJSON *a_element = a->child; + cJSON *b_element = b->child; + + for (; (a_element != NULL) && (b_element != NULL);) + { + if (!cJSON_Compare(a_element, b_element, case_sensitive)) + { + return false; + } + + a_element = a_element->next; + b_element = b_element->next; + } + + /* one of the arrays is longer than the other */ + if (a_element != b_element) { + return false; + } + + return true; + } + + case cJSON_Object: + { + cJSON *a_element = NULL; + cJSON *b_element = NULL; + cJSON_ArrayForEach(a_element, a) + { + /* TODO This has O(n^2) runtime, which is horrible! */ + b_element = get_object_item(b, a_element->string, case_sensitive); + if (b_element == NULL) + { + return false; + } + + if (!cJSON_Compare(a_element, b_element, case_sensitive)) + { + return false; + } + } + + /* doing this twice, once on a and b to prevent true comparison if a subset of b + * TODO: Do this the proper way, this is just a fix for now */ + cJSON_ArrayForEach(b_element, b) + { + a_element = get_object_item(a, b_element->string, case_sensitive); + if (a_element == NULL) + { + return false; + } + + if (!cJSON_Compare(b_element, a_element, case_sensitive)) + { + return false; + } + } + + return true; + } + + default: + return false; + } +} + +CJSON_PUBLIC(void *) cJSON_malloc(size_t size) +{ + return global_hooks.allocate(size); +} + +CJSON_PUBLIC(void) cJSON_free(void *object) +{ + global_hooks.deallocate(object); + object = NULL; +} diff --git a/FW/Core/my_src/cJSON.h b/FW/Core/my_src/cJSON.h new file mode 100644 index 0000000..37520bb --- /dev/null +++ b/FW/Core/my_src/cJSON.h @@ -0,0 +1,306 @@ +/* + Copyright (c) 2009-2017 Dave Gamble and cJSON contributors + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to deal + in the Software without restriction, including without limitation the rights + to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + THE SOFTWARE. +*/ + +#ifndef cJSON__h +#define cJSON__h + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if !defined(__WINDOWS__) && (defined(WIN32) || defined(WIN64) || defined(_MSC_VER) || defined(_WIN32)) +#define __WINDOWS__ +#endif + +#ifdef __WINDOWS__ + +/* When compiling for windows, we specify a specific calling convention to avoid issues where we are being called from a project with a different default calling convention. For windows you have 3 define options: + +CJSON_HIDE_SYMBOLS - Define this in the case where you don't want to ever dllexport symbols +CJSON_EXPORT_SYMBOLS - Define this on library build when you want to dllexport symbols (default) +CJSON_IMPORT_SYMBOLS - Define this if you want to dllimport symbol + +For *nix builds that support visibility attribute, you can define similar behavior by + +setting default visibility to hidden by adding +-fvisibility=hidden (for gcc) +or +-xldscope=hidden (for sun cc) +to CFLAGS + +then using the CJSON_API_VISIBILITY flag to "export" the same symbols the way CJSON_EXPORT_SYMBOLS does + +*/ + +#define CJSON_CDECL __cdecl +#define CJSON_STDCALL __stdcall + +/* export symbols by default, this is necessary for copy pasting the C and header file */ +#if !defined(CJSON_HIDE_SYMBOLS) && !defined(CJSON_IMPORT_SYMBOLS) && !defined(CJSON_EXPORT_SYMBOLS) +#define CJSON_EXPORT_SYMBOLS +#endif + +#if defined(CJSON_HIDE_SYMBOLS) +#define CJSON_PUBLIC(type) type CJSON_STDCALL +#elif defined(CJSON_EXPORT_SYMBOLS) +#define CJSON_PUBLIC(type) __declspec(dllexport) type CJSON_STDCALL +#elif defined(CJSON_IMPORT_SYMBOLS) +#define CJSON_PUBLIC(type) __declspec(dllimport) type CJSON_STDCALL +#endif +#else /* !__WINDOWS__ */ +#define CJSON_CDECL +#define CJSON_STDCALL + +#if (defined(__GNUC__) || defined(__SUNPRO_CC) || defined (__SUNPRO_C)) && defined(CJSON_API_VISIBILITY) +#define CJSON_PUBLIC(type) __attribute__((visibility("default"))) type +#else +#define CJSON_PUBLIC(type) type +#endif +#endif + +/* project version */ +#define CJSON_VERSION_MAJOR 1 +#define CJSON_VERSION_MINOR 7 +#define CJSON_VERSION_PATCH 18 + +#include + +/* cJSON Types: */ +#define cJSON_Invalid (0) +#define cJSON_False (1 << 0) +#define cJSON_True (1 << 1) +#define cJSON_NULL (1 << 2) +#define cJSON_Number (1 << 3) +#define cJSON_String (1 << 4) +#define cJSON_Array (1 << 5) +#define cJSON_Object (1 << 6) +#define cJSON_Raw (1 << 7) /* raw json */ + +#define cJSON_IsReference 256 +#define cJSON_StringIsConst 512 + +/* The cJSON structure: */ +typedef struct cJSON +{ + /* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */ + struct cJSON *next; + struct cJSON *prev; + /* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */ + struct cJSON *child; + + /* The type of the item, as above. */ + int type; + + /* The item's string, if type==cJSON_String and type == cJSON_Raw */ + char *valuestring; + /* writing to valueint is DEPRECATED, use cJSON_SetNumberValue instead */ + int valueint; + /* The item's number, if type==cJSON_Number */ + double valuedouble; + + /* The item's name string, if this item is the child of, or is in the list of subitems of an object. */ + char *string; +} cJSON; + +typedef struct cJSON_Hooks +{ + /* malloc/free are CDECL on Windows regardless of the default calling convention of the compiler, so ensure the hooks allow passing those functions directly. */ + void *(CJSON_CDECL *malloc_fn)(size_t sz); + void (CJSON_CDECL *free_fn)(void *ptr); +} cJSON_Hooks; + +typedef int cJSON_bool; + +/* Limits how deeply nested arrays/objects can be before cJSON rejects to parse them. + * This is to prevent stack overflows. */ +#ifndef CJSON_NESTING_LIMIT +#define CJSON_NESTING_LIMIT 1000 +#endif + +/* Limits the length of circular references can be before cJSON rejects to parse them. + * This is to prevent stack overflows. */ +#ifndef CJSON_CIRCULAR_LIMIT +#define CJSON_CIRCULAR_LIMIT 10000 +#endif + +/* returns the version of cJSON as a string */ +CJSON_PUBLIC(const char*) cJSON_Version(void); + +/* Supply malloc, realloc and free functions to cJSON */ +CJSON_PUBLIC(void) cJSON_InitHooks(cJSON_Hooks* hooks); + +/* Memory Management: the caller is always responsible to free the results from all variants of cJSON_Parse (with cJSON_Delete) and cJSON_Print (with stdlib free, cJSON_Hooks.free_fn, or cJSON_free as appropriate). The exception is cJSON_PrintPreallocated, where the caller has full responsibility of the buffer. */ +/* Supply a block of JSON, and this returns a cJSON object you can interrogate. */ +CJSON_PUBLIC(cJSON *) cJSON_Parse(const char *value); +CJSON_PUBLIC(cJSON *) cJSON_ParseWithLength(const char *value, size_t buffer_length); +/* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */ +/* If you supply a ptr in return_parse_end and parsing fails, then return_parse_end will contain a pointer to the error so will match cJSON_GetErrorPtr(). */ +CJSON_PUBLIC(cJSON *) cJSON_ParseWithOpts(const char *value, const char **return_parse_end, cJSON_bool require_null_terminated); +CJSON_PUBLIC(cJSON *) cJSON_ParseWithLengthOpts(const char *value, size_t buffer_length, const char **return_parse_end, cJSON_bool require_null_terminated); + +/* Render a cJSON entity to text for transfer/storage. */ +CJSON_PUBLIC(char *) cJSON_Print(const cJSON *item); +/* Render a cJSON entity to text for transfer/storage without any formatting. */ +CJSON_PUBLIC(char *) cJSON_PrintUnformatted(const cJSON *item); +/* Render a cJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */ +CJSON_PUBLIC(char *) cJSON_PrintBuffered(const cJSON *item, int prebuffer, cJSON_bool fmt); +/* Render a cJSON entity to text using a buffer already allocated in memory with given length. Returns 1 on success and 0 on failure. */ +/* NOTE: cJSON is not always 100% accurate in estimating how much memory it will use, so to be safe allocate 5 bytes more than you actually need */ +CJSON_PUBLIC(cJSON_bool) cJSON_PrintPreallocated(cJSON *item, char *buffer, const int length, const cJSON_bool format); +/* Delete a cJSON entity and all subentities. */ +CJSON_PUBLIC(void) cJSON_Delete(cJSON *item); + +/* Returns the number of items in an array (or object). */ +CJSON_PUBLIC(int) cJSON_GetArraySize(const cJSON *array); +/* Retrieve item number "index" from array "array". Returns NULL if unsuccessful. */ +CJSON_PUBLIC(cJSON *) cJSON_GetArrayItem(const cJSON *array, int index); +/* Get item "string" from object. Case insensitive. */ +CJSON_PUBLIC(cJSON *) cJSON_GetObjectItem(const cJSON * const object, const char * const string); +CJSON_PUBLIC(cJSON *) cJSON_GetObjectItemCaseSensitive(const cJSON * const object, const char * const string); +CJSON_PUBLIC(cJSON_bool) cJSON_HasObjectItem(const cJSON *object, const char *string); +/* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when cJSON_Parse() returns 0. 0 when cJSON_Parse() succeeds. */ +CJSON_PUBLIC(const char *) cJSON_GetErrorPtr(void); + +/* Check item type and return its value */ +CJSON_PUBLIC(char *) cJSON_GetStringValue(const cJSON * const item); +CJSON_PUBLIC(double) cJSON_GetNumberValue(const cJSON * const item); + +/* These functions check the type of an item */ +CJSON_PUBLIC(cJSON_bool) cJSON_IsInvalid(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsFalse(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsTrue(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsBool(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsNull(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsNumber(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsString(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsArray(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsObject(const cJSON * const item); +CJSON_PUBLIC(cJSON_bool) cJSON_IsRaw(const cJSON * const item); + +/* These calls create a cJSON item of the appropriate type. */ +CJSON_PUBLIC(cJSON *) cJSON_CreateNull(void); +CJSON_PUBLIC(cJSON *) cJSON_CreateTrue(void); +CJSON_PUBLIC(cJSON *) cJSON_CreateFalse(void); +CJSON_PUBLIC(cJSON *) cJSON_CreateBool(cJSON_bool boolean); +CJSON_PUBLIC(cJSON *) cJSON_CreateNumber(double num); +CJSON_PUBLIC(cJSON *) cJSON_CreateString(const char *string); +/* raw json */ +CJSON_PUBLIC(cJSON *) cJSON_CreateRaw(const char *raw); +CJSON_PUBLIC(cJSON *) cJSON_CreateArray(void); +CJSON_PUBLIC(cJSON *) cJSON_CreateObject(void); + +/* Create a string where valuestring references a string so + * it will not be freed by cJSON_Delete */ +CJSON_PUBLIC(cJSON *) cJSON_CreateStringReference(const char *string); +/* Create an object/array that only references it's elements so + * they will not be freed by cJSON_Delete */ +CJSON_PUBLIC(cJSON *) cJSON_CreateObjectReference(const cJSON *child); +CJSON_PUBLIC(cJSON *) cJSON_CreateArrayReference(const cJSON *child); + +/* These utilities create an Array of count items. + * The parameter count cannot be greater than the number of elements in the number array, otherwise array access will be out of bounds.*/ +CJSON_PUBLIC(cJSON *) cJSON_CreateIntArray(const int *numbers, int count); +CJSON_PUBLIC(cJSON *) cJSON_CreateFloatArray(const float *numbers, int count); +CJSON_PUBLIC(cJSON *) cJSON_CreateDoubleArray(const double *numbers, int count); +CJSON_PUBLIC(cJSON *) cJSON_CreateStringArray(const char *const *strings, int count); + +/* Append item to the specified array/object. */ +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToArray(cJSON *array, cJSON *item); +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToObject(cJSON *object, const char *string, cJSON *item); +/* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the cJSON object. + * WARNING: When this function was used, make sure to always check that (item->type & cJSON_StringIsConst) is zero before + * writing to `item->string` */ +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToObjectCS(cJSON *object, const char *string, cJSON *item); +/* Append reference to item to the specified array/object. Use this when you want to add an existing cJSON to a new cJSON, but don't want to corrupt your existing cJSON. */ +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item); +CJSON_PUBLIC(cJSON_bool) cJSON_AddItemReferenceToObject(cJSON *object, const char *string, cJSON *item); + +/* Remove/Detach items from Arrays/Objects. */ +CJSON_PUBLIC(cJSON *) cJSON_DetachItemViaPointer(cJSON *parent, cJSON * const item); +CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromArray(cJSON *array, int which); +CJSON_PUBLIC(void) cJSON_DeleteItemFromArray(cJSON *array, int which); +CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObject(cJSON *object, const char *string); +CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObjectCaseSensitive(cJSON *object, const char *string); +CJSON_PUBLIC(void) cJSON_DeleteItemFromObject(cJSON *object, const char *string); +CJSON_PUBLIC(void) cJSON_DeleteItemFromObjectCaseSensitive(cJSON *object, const char *string); + +/* Update array items. */ +CJSON_PUBLIC(cJSON_bool) cJSON_InsertItemInArray(cJSON *array, int which, cJSON *newitem); /* Shifts pre-existing items to the right. */ +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemViaPointer(cJSON * const parent, cJSON * const item, cJSON * replacement); +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInArray(cJSON *array, int which, cJSON *newitem); +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem); +CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInObjectCaseSensitive(cJSON *object,const char *string,cJSON *newitem); + +/* Duplicate a cJSON item */ +CJSON_PUBLIC(cJSON *) cJSON_Duplicate(const cJSON *item, cJSON_bool recurse); +/* Duplicate will create a new, identical cJSON item to the one you pass, in new memory that will + * need to be released. With recurse!=0, it will duplicate any children connected to the item. + * The item->next and ->prev pointers are always zero on return from Duplicate. */ +/* Recursively compare two cJSON items for equality. If either a or b is NULL or invalid, they will be considered unequal. + * case_sensitive determines if object keys are treated case sensitive (1) or case insensitive (0) */ +CJSON_PUBLIC(cJSON_bool) cJSON_Compare(const cJSON * const a, const cJSON * const b, const cJSON_bool case_sensitive); + +/* Minify a strings, remove blank characters(such as ' ', '\t', '\r', '\n') from strings. + * The input pointer json cannot point to a read-only address area, such as a string constant, + * but should point to a readable and writable address area. */ +CJSON_PUBLIC(void) cJSON_Minify(char *json); + +/* Helper functions for creating and adding items to an object at the same time. + * They return the added item or NULL on failure. */ +CJSON_PUBLIC(cJSON*) cJSON_AddNullToObject(cJSON * const object, const char * const name); +CJSON_PUBLIC(cJSON*) cJSON_AddTrueToObject(cJSON * const object, const char * const name); +CJSON_PUBLIC(cJSON*) cJSON_AddFalseToObject(cJSON * const object, const char * const name); +CJSON_PUBLIC(cJSON*) cJSON_AddBoolToObject(cJSON * const object, const char * const name, const cJSON_bool boolean); +CJSON_PUBLIC(cJSON*) cJSON_AddNumberToObject(cJSON * const object, const char * const name, const double number); +CJSON_PUBLIC(cJSON*) cJSON_AddStringToObject(cJSON * const object, const char * const name, const char * const string); +CJSON_PUBLIC(cJSON*) cJSON_AddRawToObject(cJSON * const object, const char * const name, const char * const raw); +CJSON_PUBLIC(cJSON*) cJSON_AddObjectToObject(cJSON * const object, const char * const name); +CJSON_PUBLIC(cJSON*) cJSON_AddArrayToObject(cJSON * const object, const char * const name); + +/* When assigning an integer value, it needs to be propagated to valuedouble too. */ +#define cJSON_SetIntValue(object, number) ((object) ? (object)->valueint = (object)->valuedouble = (number) : (number)) +/* helper for the cJSON_SetNumberValue macro */ +CJSON_PUBLIC(double) cJSON_SetNumberHelper(cJSON *object, double number); +#define cJSON_SetNumberValue(object, number) ((object != NULL) ? cJSON_SetNumberHelper(object, (double)number) : (number)) +/* Change the valuestring of a cJSON_String object, only takes effect when type of object is cJSON_String */ +CJSON_PUBLIC(char*) cJSON_SetValuestring(cJSON *object, const char *valuestring); + +/* If the object is not a boolean type this does nothing and returns cJSON_Invalid else it returns the new type*/ +#define cJSON_SetBoolValue(object, boolValue) ( \ + (object != NULL && ((object)->type & (cJSON_False|cJSON_True))) ? \ + (object)->type=((object)->type &(~(cJSON_False|cJSON_True)))|((boolValue)?cJSON_True:cJSON_False) : \ + cJSON_Invalid\ +) + +/* Macro for iterating over an array or object */ +#define cJSON_ArrayForEach(element, array) for(element = (array != NULL) ? (array)->child : NULL; element != NULL; element = element->next) + +/* malloc/free objects using the malloc/free functions that have been set with cJSON_InitHooks */ +CJSON_PUBLIC(void *) cJSON_malloc(size_t size); +CJSON_PUBLIC(void) cJSON_free(void *object); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FW/Core/my_src/delay.c b/FW/Core/my_src/delay.c new file mode 100644 index 0000000..2a5e11f --- /dev/null +++ b/FW/Core/my_src/delay.c @@ -0,0 +1,22 @@ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_tim.h" + +void delay_us(unsigned int nus) +{ + LL_TIM_SetCounter(TIM6,0); + LL_TIM_SetAutoReload(TIM6,(10*nus-1)); + LL_TIM_EnableCounter(TIM6); + while(!(LL_TIM_IsActiveFlag_UPDATE(TIM6))){ + ; + } + LL_TIM_ClearFlag_UPDATE(TIM6); + LL_TIM_DisableCounter(TIM6); +} + +void delay_ms(unsigned int nms) +{ + unsigned int i = 0; + for(i=0;itx_len > 8)return; + + p_fdcan_handle = &hfdcan2; + p_fdcan_tx_handle = &FDCAN_TxHeader; + +/*##-4- Start the Transmission process #####################################*/ + if(READ_BIT(p_fdcan_handle->Instance->CCCR, FDCAN_CCCR_DAR)){ + HAL_FDCAN_Stop(p_fdcan_handle); + CLEAR_BIT(p_fdcan_handle->Instance->CCCR, FDCAN_CCCR_DAR);//AUTO retransmission + HAL_FDCAN_Start(p_fdcan_handle); + } + + p_fdcan_tx_handle->Identifier = can_handle->tx_cmd; //32位ID + p_fdcan_tx_handle->IdType = FDCAN_EXTENDED_ID; + p_fdcan_tx_handle->TxFrameType = FDCAN_DATA_FRAME; //数据帧 + p_fdcan_tx_handle->DataLength = (can_handle->tx_len<<16); //数据长度 + p_fdcan_tx_handle->ErrorStateIndicator = FDCAN_ESI_ACTIVE; + p_fdcan_tx_handle->BitRateSwitch = FDCAN_BRS_OFF; //关闭速率切换 + p_fdcan_tx_handle->FDFormat = FDCAN_CLASSIC_CAN; //传统的CAN模式 + p_fdcan_tx_handle->TxEventFifoControl = FDCAN_NO_TX_EVENTS; //无发送事件 + p_fdcan_tx_handle->MessageMarker = 0; + + /* Request transmission */ + if(HAL_FDCAN_AddMessageToTxFifoQ(p_fdcan_handle, p_fdcan_tx_handle, can_handle->tx_buf) != HAL_OK) + { + /* Transmission request Error */ + //Error_Handler(); + } + + /* Wait transmission complete */ + //while(HAL_CAN_GetTxMailboxesFreeLevel(&CanHandle) != 3) + //{ + //__nop(); + //} +} + +void can_send_time_handle(void)//100ms +{ + if(0 == can_handle.tx_complete){ + can_handle.tx_timer_count++; + if(can_handle.tx_timer_count > 2){ + can_handle.tx_timer_count = 0; + can_handle.tx_complete = 1; + + HAL_FDCAN_Stop(&hfdcan2); + FDCAN2_Reinit(); + /* + HAL_Delay(5); + HAL_FDCAN_Start(&hfdcan2); + + if(!READ_BIT(hfdcan2.Instance->CCCR, FDCAN_CCCR_DAR)){ + SET_BIT(hfdcan2.Instance->CCCR, FDCAN_CCCR_DAR);//NO AUTO retransmission + } + */ + } + } +} + +void can_tx_task(void) +{ + if(can_handle.tx_msg_falg){ + if(can_handle.tx_complete){ + can_handle.tx_complete = 0; + + can_sent(&can_handle); + + can_handle.tx_msg_falg = 0; + } + } +} + +void can_task(void) +{ + can_tx_task(); + + fdcan_test_task(); +} + +void can_prm_init(void) +{ + can_handle.rx_complete = 0; + + can_handle.tx_msg_falg = 0; + can_handle.tx_complete = 1; +} + +void can_send_test(void) +{ + can_handle.tx_msg_falg = 1; + + can_handle.tx_cmd = CAN_EXTEND_ID; + + can_handle.tx_buf[0] = 0x01; + can_handle.tx_buf[1] = 0x06; + can_handle.tx_buf[2] = 0xF0; + can_handle.tx_buf[3] = 0x55; + can_handle.tx_buf[4] = 0xaa; + can_handle.tx_buf[5] = 0xc0; + can_handle.tx_buf[6] = 0x40; + can_handle.tx_buf[7] = 0x88; + + can_handle.tx_len = 8; + can_handle.tx_timer_count = 0; +} + +unsigned int internal_can_send_data(unsigned int head, unsigned char * pdata, unsigned int len) +{ + unsigned int i = 0; + if(len > 8)return 1; + if(can_handle.tx_msg_falg)return 1; + //if(!can_handle.tx_complete)return 1; + if(!can_handle.tx_complete_delay_flag)return 1; + + can_handle.tx_msg_falg = 1; + can_handle.tx_cmd = head; + for(i=0;i 2){ + can_handle.tx_complete_delay_tick = 0; + can_handle.tx_complete_delay_flag = 1; + } + } + } +} + +void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) +{ + if(hfdcan == (&hfdcan2)){ + can_handle.tx_complete = 1; + } +} + +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) +{ + unsigned int i=0; + unsigned char rxdata[8]; + + if(hfdcan == (&hfdcan2)){ + if((RxFifo0ITs&FDCAN_IT_RX_FIFO0_NEW_MESSAGE)!=RESET) //FIFO1新数据中断 + { + //提取FIFO0中接收到的数据 + HAL_FDCAN_GetRxMessage(hfdcan,FDCAN_RX_FIFO0,&FDCAN_RxHeader,can_handle.rx_buf); + + if(FDCAN_EXTENDED_ID == FDCAN_RxHeader.IdType){ + can_handle.rx_len = FDCAN_RxHeader.DataLength>>16; + if(can_handle.rx_len <= 8){ + can_handle.rx_complete = 1; + can_handle.rx_cmd = FDCAN_RxHeader.Identifier; + LoadInnerCanRxMsg(can_handle.rx_cmd, can_handle.rx_buf, can_handle.rx_len); + + if(hw_test_mode){ + if(0xFA == (can_handle.rx_cmd & 0xFF)){ + if(0x23 == can_handle.rx_buf[3]){ + rx_text_buf[31] = 0xA5; + } + } + } + } + } + + //HAL_FDCAN_ActivateNotification(hfdcan,FDCAN_IT_RX_FIFO0_NEW_MESSAGE,0); + } + } +} + +void fdcan_test_task(void) +{ + if(hw_test_mode){ + if(get_can_tx_complete_delay_flag()){ + if(0xA5 == rx_text_buf[31]){ + rx_text_buf[31] = 0; + rx_text_buf[0] = 0xA0; + rx_text_buf[1] = 0x02; + rx_text_buf[2] = 0; + rx_text_buf[3] = 0x23; + rx_text_buf[4] = 1; + internal_can_send_data(0xFA, rx_text_buf, 5); + } + } + } +} + diff --git a/FW/Core/my_src/fdcan_task.h b/FW/Core/my_src/fdcan_task.h new file mode 100644 index 0000000..a6ed140 --- /dev/null +++ b/FW/Core/my_src/fdcan_task.h @@ -0,0 +1,44 @@ +typedef union can_ide +{ + unsigned int D32; + unsigned char D8[4]; + struct{ + unsigned int Cmd :8; + unsigned int dAddr :7; + unsigned int sAddr :7; + unsigned int dLvl :3; + unsigned int sLvl :2; + unsigned int Pri :2; + unsigned int Dump :3; + }BitF; +}can_ide_struct; + +typedef struct can_def +{ + unsigned int rx_cmd; + unsigned char rx_buf[8]; + unsigned int rx_len; + unsigned int rx_complete; + + unsigned int tx_cmd; + unsigned char tx_buf[8]; + unsigned int tx_len; + unsigned int tx_complete; + unsigned int tx_complete_delay_flag; + unsigned int tx_complete_delay_tick; + unsigned int tx_err; + unsigned int tx_msg_falg; + unsigned int tx_tick; + unsigned int tx_timer_count; +}can_info_struct; + +extern can_info_struct can_handle; + +extern void can_prm_init(void); +extern void can_send_time_handle(void); +extern void can_task(void); + +extern unsigned int internal_can_send_data(unsigned int head, unsigned char * pdata, unsigned int len); +extern unsigned int get_can_tx_complete(void); +extern unsigned int get_can_tx_complete_delay_flag(void); +extern void can_tx_complete_delay(void); diff --git a/FW/Core/my_src/file_cache.c b/FW/Core/my_src/file_cache.c new file mode 100644 index 0000000..e2e74c4 --- /dev/null +++ b/FW/Core/my_src/file_cache.c @@ -0,0 +1,405 @@ +#include "file_cache.h" +#include "sdram_addr_map.h" +#include "lcd_base_display.h" + +static uint32_t const sdram_cache_buffer_address = SDRAM_BUF_CACHE_ADDRESS; + +uint8_t sector[512]; +uint32_t BytesRead; + +unsigned int load_file_to_sdramcache(const TCHAR* path, unsigned int cache_buffer_address, int *pState) +{ + uint32_t index = 0, file_size = 0, size = 0, i1 = 0; + uint32_t BmpAddress; + uint32_t Address = cache_buffer_address; + FIL F1; + + if(pState != 0)return 0; + + if(f_open (&F1, path, FA_READ)){ + /* Set the Text Color */ + set_font_color(0xFFFF0000, 0xFFFFFFFF); + + *pState = -1; + return 0; + } + + file_size = F1.obj.objsize; + size = file_size; + if(0 == size){ + *pState = -2; + return 0; + } + + do{ + //256*2 + if (size < 512){ + i1 = size; + }else{ + i1 = 512;//256*2 + } + size -= i1; + + f_read (&F1, sector, i1, &BytesRead); + + for (index = 0; index < i1; index++){ + *(__IO uint8_t*) (Address) = *(__IO uint8_t *)BmpAddress; + + BmpAddress++; + Address++; + } + + BmpAddress = (uint32_t)sector; + }while (size > 0); + + f_close (&F1); + *pState =0; + return file_size; +} + +void load_bmpfile_to_sdramcache(const TCHAR* path,uint32_t cache_buffer_address) +{ + uint32_t index = 0, size = 0, i1 = 0; + uint32_t BmpAddress; + uint32_t Address = cache_buffer_address; + FIL F1; + + if(f_open (&F1, path, FA_READ)) + { + set_font_color(0xFFFF0000, 0xFFFFFFFF); + + LCD_ShowString(20,360,400,24,24,"File type or name not supported!"); + + while(1); + } + f_read (&F1, sector, 32, &BytesRead); + + BmpAddress = (uint32_t)sector; + + /* Read bitmap size */ + size = *(uint16_t *) (BmpAddress + 2); + size |= (*(uint16_t *) (BmpAddress + 4)) << 16; + + /* Get bitmap data address offset */ + index = *(uint16_t *) (BmpAddress + 10); + index |= (*(uint16_t *) (BmpAddress + 12)) << 16; + + f_close (&F1); + + f_open (&F1, path, FA_READ); + + do + { + if (size < 512)//256*2 + { + i1 = size; + } + else + { + i1 = 512;//256*2 + } + size -= i1; + + f_read (&F1, sector, i1, &BytesRead); + + for (index = 0; index < i1; index++) + { + *(__IO uint8_t*) (Address) = *(__IO uint8_t *)BmpAddress; + + BmpAddress++; + Address++; + } + + BmpAddress = (uint32_t)sector; + } + while (size > 0); + + f_close (&F1); +} + +void load_bmpfile_sdramcache_to_sdramaddress(uint32_t BmpCacheAddress,Bmp_Parameter_TypeDef* bmp_parameter)//24bit bmp +{ + uint16_t temp_rg; + uint16_t temp_b; + uint32_t temp; + + uint16_t temp_r; + uint16_t temp_g; + + uint32_t index = 0, size = 0, width = 0, height = 0, bit_pixel = 0; + uint32_t Address; + uint32_t currentline = 0, linenumber = 0; + + uint32_t read_width = 0; + uint32_t index_width = 0; + uint32_t index_height = 0; + + uint32_t fifo_32bit = 0; + uint32_t point_32bit_data = 0; + uint32_t bit1_index = 0; + uint32_t bit1_size = 0; + uint32_t bit4_index = 0; + uint32_t bit4_size = 0; + uint32_t Bmp4BitColor = 0; + uint32_t read_width_index = 0; + uint32_t max_value = 0; + uint32_t i = 0; + + Address = bmp_parameter->start_address; + + /* Read bitmap size */ + size = *(__IO uint16_t *) (BmpCacheAddress + 2); + size |= (*(__IO uint16_t *) (BmpCacheAddress + 4)) << 16; + + /* Get bitmap data address offset */ + index = *(__IO uint16_t *) (BmpCacheAddress + 10); + index |= (*(__IO uint16_t *) (BmpCacheAddress + 12)) << 16; + + /* Read bitmap width */ + width = *(uint16_t *) (BmpCacheAddress + 18); + width |= (*(uint16_t *) (BmpCacheAddress + 20)) << 16; + + /* Read bitmap height */ + height = *(uint16_t *) (BmpCacheAddress + 22); + height |= (*(uint16_t *) (BmpCacheAddress + 24)) << 16; + + bmp_parameter->pic_width = width; + bmp_parameter->pic_height= height; + + /* Read bit/pixel */ + bit_pixel = *(uint16_t *) (BmpCacheAddress + 28); + + /* compute the real size of the picture (without the header)) */ + size = (size - index); + + /* bypass the bitmap header */ + BmpCacheAddress += index; + + //16bit bmp + if(16 == bit_pixel) + { + if(width & 0x01) + { + read_width = width + 1;// 2 byte + } + else + { + read_width = width + 0; + } + size = read_width*height*2; + BmpCacheAddress+=(size-(read_width*2)); + + for(index_height = 0; index_height < height; index_height++) + { + for(index_width = 0; index_width < width; index_width++) + { + temp = *(__IO uint16_t *)BmpCacheAddress; + temp_r = (temp&0x7C00)>>7; + temp_g = (temp&0x03E0)>>2; + temp_b = (temp&0x001F)<<3; + temp = temp_r; + temp<<=8; + temp|=temp_g; + temp<<=8; + temp|=temp_b; + *(__IO uint32_t*) (Address) = (temp | 0xFF000000); + //jump on point pixel + BmpCacheAddress+=2; + Address+=4; + } + BmpCacheAddress-=((read_width + width)*2); + } + } + + //24bit bmp + else if(24 == bit_pixel) + { + if((width * 3) & 0x03) + { + read_width = (((width * 3)>>2) + 1)<<2;// 4 byte + } + else + { + read_width = width * 3; + } + size = read_width*height; + BmpCacheAddress+=(size-read_width); + + for(index_height = 0; index_height < height; index_height++) + { + for(index_width = 0; index_width < width; index_width++) + { + temp_b = *(__IO uint8_t *)BmpCacheAddress; + BmpCacheAddress++; + temp_g = *(__IO uint8_t *)BmpCacheAddress; + BmpCacheAddress++; + temp_r = *(__IO uint8_t *)BmpCacheAddress; + BmpCacheAddress++; + temp = temp_r; + temp<<=8; + temp|=temp_g; + temp<<=8; + temp|=temp_b; + *(__IO uint32_t*) (Address) = (temp | 0xFF000000); + //jump on point pixel + Address+=4; + } + BmpCacheAddress-=(read_width + width * 3); + } + } + + //4bit bmp + else if(4 == bit_pixel) + { + if(width & 0x07) + { + read_width = (width>>3) + 1;//read length 32bit + } + else + { + read_width = (width>>3) + 0; + } + size = read_width * height * 4;// 4 byte + BmpCacheAddress +=(size - (read_width * 4));//from bottom to top + bit4_size = width * height;//total 4bit size + index_height = height; + read_width_index = read_width; + do + { + point_32bit_data = (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + point_32bit_data = (point_32bit_data<<8) | (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + point_32bit_data = (point_32bit_data<<8) | (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + point_32bit_data = (point_32bit_data<<8) | (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + + read_width_index--; + if(0 == read_width_index) + { + max_value = width - ((read_width-1)<<3); + read_width_index = read_width; + index_height--; + BmpCacheAddress -=(read_width * 4 * 2);//read from bottom address to top address + if(0 == index_height) + { + ; + } + } + else + { + max_value = 8; + } + + for(i = 0;i < max_value;i++) + { + switch((point_32bit_data & 0xF0000000)>>28){ + case 0 : *(__IO uint32_t*)(Address) = 0xFF000000;break; + case 1 : *(__IO uint32_t*)(Address) = 0xFF800000;break; + case 2 : *(__IO uint32_t*)(Address) = 0xFF008000;break; + case 3 : *(__IO uint32_t*)(Address) = 0xFF808000;break; + case 4 : *(__IO uint32_t*)(Address) = 0xFF000080;break; + case 5 : *(__IO uint32_t*)(Address) = 0xFF800080;break; + case 6 : *(__IO uint32_t*)(Address) = 0xFF008080;break; + case 7 : *(__IO uint32_t*)(Address) = 0xFF808080;break; + case 8 : *(__IO uint32_t*)(Address) = 0xFFC0C0C0;break; + case 9 : *(__IO uint32_t*)(Address) = 0xFFFF0000;break; + case 10: *(__IO uint32_t*)(Address) = 0xFF00FF00;break; + case 11: *(__IO uint32_t*)(Address) = 0xFFFFFF00;break; + case 12: *(__IO uint32_t*)(Address) = 0xFF0000FF;break; + case 13: *(__IO uint32_t*)(Address) = 0xFFFF00FF;break; + case 14: *(__IO uint32_t*)(Address) = 0xFF00FFFF;break; + case 15: *(__IO uint32_t*)(Address) = 0xFFFFFFFF;break; + default : break; + } + point_32bit_data<<=4; + bit4_index++; + Address+=4; + if(bit4_index == bit4_size) + { + break; + } + } + }while(bit4_index < bit4_size); + } + + //1bit bmp + else if(1 == bit_pixel) + { + if(width & 0x1F) + { + read_width = (width>>5) + 1;//read length 32bit + } + else + { + read_width = (width>>5) + 0; + } + size = read_width * height * 4;// 4 byte + BmpCacheAddress +=(size - (read_width * 4));//from bottom to top + bit1_size = width * height;//total bit size + index_height = height; + read_width_index = read_width; + do + { + point_32bit_data = (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + point_32bit_data = (point_32bit_data<<8) | (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + point_32bit_data = (point_32bit_data<<8) | (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + point_32bit_data = (point_32bit_data<<8) | (*(__IO uint8_t *)BmpCacheAddress); + BmpCacheAddress++; + + read_width_index--; + if(0 == read_width_index) + { + max_value = width - ((read_width-1)<<5); + read_width_index = read_width; + index_height--; + BmpCacheAddress -=(read_width * 4 * 2);//read from bottom address to top address + if(0 == index_height) + { + ; + } + } + else + { + max_value = 32; + } + + for(i = 0;i < max_value;i++) + { + fifo_32bit<<=1; + if(point_32bit_data & 0x80000000) + { + fifo_32bit|=0x01; + } + else + { + fifo_32bit&=~0x01; + } + point_32bit_data<<=1; + bit1_index++; + if(!(bit1_index & 0x1f)) + { + *(__IO uint32_t*)(Address) = fifo_32bit; + Address+=4; + } + else if(bit1_index == bit1_size) + { + fifo_32bit<<=(32-(bit1_index & 0x1F)); + *(__IO uint32_t*)(Address) = fifo_32bit; + Address+=4; + break; + } + } + }while(bit1_index < bit1_size); + } +} + +void load_bmpfile_to_sdram(Bmp_Parameter_TypeDef* BmpFileParameter) +{ + load_bmpfile_to_sdramcache((const char *)BmpFileParameter->name_str,sdram_cache_buffer_address); + load_bmpfile_sdramcache_to_sdramaddress(sdram_cache_buffer_address,BmpFileParameter); +} diff --git a/FW/Core/my_src/file_cache.h b/FW/Core/my_src/file_cache.h new file mode 100644 index 0000000..b74064f --- /dev/null +++ b/FW/Core/my_src/file_cache.h @@ -0,0 +1,5 @@ +#include "ff.h" +#include "load_gui_lib.h" + +extern void load_bmpfile_to_sdram(Bmp_Parameter_TypeDef* BmpFileParameter); +extern unsigned int load_file_to_sdramcache(const TCHAR* path,unsigned int cache_buffer_address, int *State); diff --git a/FW/Core/my_src/font.h b/FW/Core/my_src/font.h new file mode 100644 index 0000000..1f82ced --- /dev/null +++ b/FW/Core/my_src/font.h @@ -0,0 +1,403 @@ +#ifndef __FONT_H +#define __FONT_H +//常用ASCII表 +//偏移量32 +//ASCII字符集: !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ +//PC2LCD2002取模方式设置：阴码+逐列式+顺向+C51格式 +//总共：3个字符集（12*12、16*16、24*24和32*32），用户可以自行新增其他分辨率的字符集。 +//每个字符所占用的字节数为:(size/8+((size%8)?1:0))*(size/2),其中size:是字库生成时的点阵大小(12/16/24/32...) + +//12*12 ASCII字符集点阵 +const unsigned char asc2_1206[95][12]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*""",2*/ +{0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*"#",3*/ +{0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*"$",4*/ +{0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*"%",5*/ +{0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*"&",6*/ +{0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*"(",8*/ +{0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*")",9*/ +{0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*"*",10*/ +{0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*"+",11*/ +{0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*"-",13*/ +{0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*"/",15*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*"2",18*/ +{0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"3",19*/ +{0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*"4",20*/ +{0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*"5",21*/ +{0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*"6",22*/ +{0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*"7",23*/ +{0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"8",24*/ +{0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*"<",28*/ +{0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*">",30*/ +{0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"?",31*/ +{0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*"@",32*/ +{0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*"A",33*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"B",34*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*"C",35*/ +{0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"D",36*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*"E",37*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*"F",38*/ +{0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*"G",39*/ +{0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*"H",40*/ +{0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*"I",41*/ +{0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*"J",42*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*"K",43*/ +{0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*"L",44*/ +{0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*"M",45*/ +{0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*"N",46*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"O",47*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"P",48*/ +{0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*"Q",49*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*"R",50*/ +{0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*"S",51*/ +{0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*"T",52*/ +{0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*"U",53*/ +{0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*"V",54*/ +{0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*"W",55*/ +{0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*"X",56*/ +{0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*"Y",57*/ +{0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*"_",63*/ +{0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*"a",65*/ +{0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*"d",68*/ +{0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*"f",70*/ +{0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*"g",71*/ +{0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"h",72*/ +{0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*"k",75*/ +{0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*"l",76*/ +{0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*"m",77*/ +{0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"n",78*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"o",79*/ +{0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*"q",81*/ +{0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*"t",84*/ +{0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*"u",85*/ +{0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*"v",86*/ +{0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*"w",87*/ +{0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*"x",88*/ +{0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*"y",89*/ +{0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*"~",94*/ +}; +//16*16 ASCII字符集点阵 +const unsigned char asc2_1608[95][16]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*""",2*/ +{0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*"#",3*/ +{0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*"$",4*/ +{0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*"%",5*/ +{0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*"&",6*/ +{0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*"(",8*/ +{0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ +{0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*"*",10*/ +{0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*"+",11*/ +{0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"-",13*/ +{0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*"/",15*/ +{0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*"2",18*/ +{0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*"3",19*/ +{0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*"4",20*/ +{0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*"5",21*/ +{0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*"6",22*/ +{0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*"7",23*/ +{0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*"8",24*/ +{0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*"<",28*/ +{0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*">",30*/ +{0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*"?",31*/ +{0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*"@",32*/ +{0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*"A",33*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*"B",34*/ +{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*"C",35*/ +{0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"D",36*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*"E",37*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*"F",38*/ +{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*"G",39*/ +{0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*"H",40*/ +{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*"I",41*/ +{0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*"J",42*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*"K",43*/ +{0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*"L",44*/ +{0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*"M",45*/ +{0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*"N",46*/ +{0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"O",47*/ +{0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*"P",48*/ +{0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*"Q",49*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*"R",50*/ +{0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*"S",51*/ +{0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*"T",52*/ +{0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*"U",53*/ +{0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*"V",54*/ +{0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*"W",55*/ +{0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*"X",56*/ +{0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*"Y",57*/ +{0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*"_",63*/ +{0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*"a",65*/ +{0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*"d",68*/ +{0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*"f",70*/ +{0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*"g",71*/ +{0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"h",72*/ +{0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*"k",75*/ +{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"l",76*/ +{0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*"m",77*/ +{0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"n",78*/ +{0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*"o",79*/ +{0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*"q",81*/ +{0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*"t",84*/ +{0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*"u",85*/ +{0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*"v",86*/ +{0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*"w",87*/ +{0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*"x",88*/ +{0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*"y",89*/ +{0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*"~",94*/ +}; +//24*24 ASICII字符集点阵 +const unsigned char asc2_2412[95][36]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x38,0x0F,0xFE,0x38,0x0F,0x80,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x31,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*""",2*/ +{0x00,0x00,0x00,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x00,0x00},/*"#",3*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xE0,0xF0,0x06,0x30,0x08,0x04,0x18,0x08,0x1F,0xFF,0xFE,0x04,0x0E,0x08,0x07,0x87,0xF0,0x03,0x81,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/ +{0x01,0xF0,0x00,0x06,0x0C,0x00,0x04,0x04,0x08,0x06,0x0C,0x70,0x01,0xF9,0xC0,0x00,0x0E,0x00,0x00,0x3B,0xE0,0x00,0xEC,0x18,0x07,0x08,0x08,0x04,0x0C,0x18,0x00,0x03,0xE0,0x00,0x00,0x00},/*"%",5*/ +{0x00,0x01,0xE0,0x00,0x07,0xF0,0x03,0xF8,0x18,0x04,0x1C,0x08,0x04,0x17,0x08,0x07,0xE1,0xD0,0x03,0xC0,0xE0,0x00,0x23,0xB0,0x00,0x3C,0x08,0x00,0x20,0x08,0x00,0x00,0x10,0x00,0x00,0x00},/*"&",6*/ +{0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x01,0xFF,0xC0,0x07,0x80,0xF0,0x0C,0x00,0x18,0x10,0x00,0x04,0x20,0x00,0x02,0x00,0x00,0x00},/*"(",8*/ +{0x00,0x00,0x00,0x20,0x00,0x02,0x10,0x00,0x04,0x0C,0x00,0x18,0x07,0x80,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ +{0x00,0x00,0x00,0x00,0x42,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x3C,0x00,0x00,0x18,0x00,0x03,0xFF,0xC0,0x00,0x18,0x00,0x00,0x3C,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x42,0x00},/*"*",10*/ +{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x01,0xFF,0xC0,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00},/*"+",11*/ +{0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*"-",13*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x1C,0x00,0x00,0x70,0x00,0x01,0x80,0x00,0x0E,0x00,0x00,0x38,0x00,0x00,0xC0,0x00,0x07,0x00,0x00,0x1C,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*"/",15*/ +{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x03,0xFF,0xF8,0x07,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x00,0x00,0x00,0x01,0xC0,0x38,0x02,0xC0,0x58,0x04,0x00,0x98,0x04,0x01,0x18,0x04,0x02,0x18,0x04,0x04,0x18,0x06,0x1C,0x18,0x03,0xF8,0x18,0x01,0xE0,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/ +{0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xC0,0xF0,0x04,0x00,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/ +{0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x0D,0x00,0x00,0x11,0x00,0x00,0x61,0x00,0x00,0x81,0x08,0x03,0x01,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x08,0x00,0x01,0x08,0x00,0x00,0x00},/*"4",20*/ +{0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xFC,0xD0,0x06,0x08,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x18,0x38,0x06,0x0F,0xF0,0x06,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x84,0x30,0x02,0x08,0x18,0x04,0x10,0x08,0x04,0x10,0x08,0x04,0x10,0x08,0x07,0x18,0x10,0x03,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"6",22*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x06,0x00,0xF8,0x06,0x07,0xF8,0x06,0x18,0x00,0x06,0xE0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x00,0x00,0x00},/*"7",23*/ +{0x00,0x00,0x00,0x01,0xE1,0xE0,0x03,0xF7,0xF0,0x06,0x34,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x06,0x16,0x18,0x03,0xF3,0xF0,0x01,0xC1,0xE0,0x00,0x00,0x00},/*"8",24*/ +{0x00,0x00,0x00,0x00,0xF8,0x00,0x03,0xFC,0x30,0x03,0x06,0x38,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x04,0x10,0x03,0x08,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x1A,0x00,0x30,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x00,0x22,0x00,0x00,0x41,0x00,0x00,0x80,0x80,0x01,0x00,0x40,0x02,0x00,0x20,0x04,0x00,0x10,0x08,0x00,0x08,0x00,0x00,0x00},/*"<",28*/ +{0x00,0x00,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0x04,0x00,0x10,0x02,0x00,0x20,0x01,0x00,0x40,0x00,0x80,0x80,0x00,0x41,0x00,0x00,0x22,0x00,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*">",30*/ +{0x00,0x00,0x00,0x03,0xC0,0x00,0x04,0xC0,0x00,0x04,0x00,0x00,0x08,0x00,0x38,0x08,0x0F,0x38,0x08,0x08,0x38,0x08,0x10,0x00,0x0C,0x30,0x00,0x07,0xE0,0x00,0x03,0xC0,0x00,0x00,0x00,0x00},/*"?",31*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x00,0xFF,0xE0,0x03,0x80,0x70,0x02,0x0F,0x10,0x06,0x70,0x88,0x04,0xC0,0x88,0x04,0x83,0x08,0x04,0x7F,0x88,0x02,0xC0,0x90,0x03,0x01,0x20,0x00,0xFE,0x40},/*"@",32*/ +{0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x01,0xF8,0x00,0x3E,0x08,0x01,0xC2,0x00,0x07,0x02,0x00,0x07,0xE2,0x00,0x00,0xFE,0x00,0x00,0x1F,0xC8,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x00,0x08},/*"A",33*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00},/*"B",34*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x02,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x10,0x06,0x00,0x20,0x07,0x80,0xC0,0x00,0x00,0x00},/*"C",35*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x18,0x02,0x00,0x10,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"D",36*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x3E,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x01,0x00,0x60,0x00,0x00,0x00},/*"E",37*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x3E,0x00,0x06,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"F",38*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x02,0x03,0xF0,0x07,0x83,0xF0,0x00,0x02,0x00,0x00,0x02,0x00},/*"G",39*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x04,0x08,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"H",40*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/ +{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x07,0x00,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x03,0x07,0xFF,0xFE,0x07,0xFF,0xFC,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00},/*"J",42*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x0C,0x08,0x00,0x18,0x00,0x00,0x3E,0x00,0x04,0xC7,0x80,0x05,0x03,0xC8,0x06,0x00,0xF8,0x04,0x00,0x38,0x04,0x00,0x18,0x00,0x00,0x08},/*"K",43*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x00},/*"L",44*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x80,0x08,0x07,0xFC,0x00,0x00,0x7F,0xC0,0x00,0x03,0xF8,0x00,0x07,0xC0,0x00,0x78,0x00,0x07,0x80,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"M",45*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x00,0x08,0x03,0xC0,0x00,0x00,0xE0,0x00,0x00,0x38,0x00,0x00,0x1E,0x00,0x00,0x07,0x00,0x00,0x01,0xC0,0x04,0x00,0xF0,0x07,0xFF,0xF8,0x04,0x00,0x00},/*"N",46*/ +{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x00,0x30,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"O",47*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x04,0x08,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x06,0x0C,0x00,0x03,0xF8,0x00,0x01,0xF0,0x00,0x00,0x00,0x00},/*"P",48*/ +{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x88,0x04,0x00,0x88,0x04,0x00,0xC8,0x06,0x00,0x3C,0x03,0x00,0x3E,0x01,0xFF,0xE6,0x00,0x7F,0x84,0x00,0x00,0x00},/*"Q",49*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x0C,0x00,0x04,0x0F,0x00,0x04,0x0B,0xC0,0x06,0x10,0xF0,0x03,0xF0,0x38,0x01,0xE0,0x08,0x00,0x00,0x08},/*"R",50*/ +{0x00,0x00,0x00,0x01,0xE0,0xF8,0x03,0xF0,0x30,0x06,0x30,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x02,0x06,0x18,0x02,0x07,0xF0,0x07,0x81,0xE0,0x00,0x00,0x00},/*"S",51*/ +{0x01,0x80,0x00,0x06,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x00,0x04,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00},/*"T",52*/ +{0x04,0x00,0x00,0x07,0xFF,0xE0,0x07,0xFF,0xF0,0x04,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x04,0x00,0x10,0x07,0xFF,0xE0,0x04,0x00,0x00},/*"U",53*/ +{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0xE0,0x00,0x07,0xFE,0x00,0x04,0x1F,0xE0,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x01,0xE0,0x04,0x3E,0x00,0x07,0xC0,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"V",54*/ +{0x04,0x00,0x00,0x07,0xE0,0x00,0x07,0xFF,0xC0,0x04,0x1F,0xF8,0x00,0x07,0xC0,0x07,0xF8,0x00,0x07,0xFF,0x80,0x04,0x3F,0xF8,0x00,0x07,0xC0,0x04,0xF8,0x00,0x07,0x00,0x00,0x04,0x00,0x00},/*"W",55*/ +{0x00,0x00,0x00,0x04,0x00,0x08,0x06,0x00,0x18,0x07,0xC0,0x78,0x05,0xF1,0xC8,0x00,0x3E,0x00,0x00,0x1F,0x80,0x04,0x63,0xE8,0x07,0x80,0xF8,0x06,0x00,0x18,0x04,0x00,0x08,0x00,0x00,0x00},/*"X",56*/ +{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0x80,0x00,0x07,0xE0,0x08,0x04,0x7C,0x08,0x00,0x1F,0xF8,0x00,0x07,0xF8,0x00,0x18,0x08,0x04,0xE0,0x08,0x07,0x00,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"Y",57*/ +{0x00,0x00,0x00,0x01,0x00,0x08,0x06,0x00,0x38,0x04,0x00,0xF8,0x04,0x03,0xE8,0x04,0x0F,0x08,0x04,0x7C,0x08,0x05,0xF0,0x08,0x07,0xC0,0x08,0x07,0x00,0x18,0x04,0x00,0x60,0x00,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x00,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x07,0x00,0x00,0x00,0xC0,0x00,0x00,0x38,0x00,0x00,0x06,0x00,0x00,0x01,0xC0,0x00,0x00,0x30,0x00,0x00,0x0E,0x00,0x00,0x01,0x00,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x30,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01},/*"_",63*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x19,0xF8,0x00,0x1B,0x18,0x00,0x22,0x08,0x00,0x26,0x08,0x00,0x24,0x08,0x00,0x24,0x10,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x18},/*"a",65*/ +{0x00,0x00,0x00,0x04,0x00,0x00,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x18,0x18,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x18,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x18,0x30,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3C,0x08,0x00,0x1C,0x10,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x04,0x10,0x10,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"d",68*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x12,0x30,0x00,0x22,0x18,0x00,0x22,0x08,0x00,0x22,0x08,0x00,0x32,0x08,0x00,0x1E,0x10,0x00,0x0E,0x20,0x00,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x01,0xFF,0xF8,0x03,0xFF,0xF8,0x06,0x20,0x08,0x04,0x20,0x08,0x04,0x20,0x08,0x07,0x20,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"f",70*/ +{0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x0E,0x6E,0x00,0x1F,0xF3,0x00,0x31,0xB1,0x00,0x20,0xB1,0x00,0x20,0xB1,0x00,0x31,0x91,0x00,0x1F,0x13,0x00,0x2E,0x1E,0x00,0x20,0x0E,0x00,0x30,0x00},/*"g",71*/ +{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"h",72*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x06,0x3F,0xF8,0x06,0x3F,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x03,0x00,0x20,0x01,0x00,0x20,0x01,0x00,0x20,0x03,0x06,0x3F,0xFE,0x06,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x88,0x00,0x03,0x00,0x00,0x2F,0xC0,0x00,0x38,0xF8,0x00,0x20,0x38,0x00,0x20,0x08,0x00,0x00,0x08,0x00,0x00,0x00},/*"k",75*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/ +{0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x00,0x08},/*"m",77*/ +{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x10,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"n",78*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x0F,0xF0,0x00,0x18,0x30,0x00,0x30,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x08,0x00,0x18,0x30,0x00,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"o",79*/ +{0x00,0x00,0x00,0x00,0x20,0x01,0x00,0x3F,0xFF,0x00,0x3F,0xFF,0x00,0x10,0x11,0x00,0x20,0x09,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x38,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x09,0x00,0x10,0x11,0x00,0x1F,0xFF,0x00,0x3F,0xFF,0x00,0x00,0x01,0x00,0x00,0x00},/*"q",81*/ +{0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x08,0x08,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x30,0x00,0x00,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x78,0x00,0x1E,0x18,0x00,0x33,0x08,0x00,0x23,0x08,0x00,0x21,0x08,0x00,0x21,0x88,0x00,0x21,0x98,0x00,0x30,0xF0,0x00,0x38,0x60,0x00,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0xFF,0xF0,0x03,0xFF,0xF8,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x3F,0xF0,0x00,0x7F,0xF8,0x00,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x20,0x10,0x00,0x3F,0xF8,0x00,0x7F,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"u",85*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x3C,0x00,0x00,0x3F,0x80,0x00,0x23,0xF0,0x00,0x00,0x78,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x30,0x00,0x00,0x20,0x00},/*"v",86*/ +{0x00,0x20,0x00,0x00,0x3C,0x00,0x00,0x3F,0xE0,0x00,0x23,0xF8,0x00,0x00,0xE0,0x00,0x27,0x00,0x00,0x3E,0x00,0x00,0x3F,0xE0,0x00,0x21,0xF8,0x00,0x01,0xE0,0x00,0x3E,0x00,0x00,0x20,0x00},/*"w",87*/ +{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x38,0x38,0x00,0x3E,0x68,0x00,0x27,0x80,0x00,0x03,0xC8,0x00,0x2C,0xF8,0x00,0x38,0x38,0x00,0x20,0x18,0x00,0x20,0x08,0x00,0x00,0x00},/*"x",88*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x03,0x00,0x3C,0x01,0x00,0x3F,0x83,0x00,0x23,0xEC,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"y",89*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x08,0x00,0x20,0x38,0x00,0x20,0xF8,0x00,0x23,0xE8,0x00,0x2F,0x88,0x00,0x3E,0x08,0x00,0x38,0x08,0x00,0x20,0x18,0x00,0x00,0x70,0x00,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x1F,0xF7,0xFC,0x30,0x00,0x06,0x20,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x30,0x00,0x06,0x1F,0xF7,0xFC,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x00,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x0C,0x00,0x00,0x10,0x00,0x00},/*"~",94*/ +}; + +//32*32 ASCII字符集点阵 +const unsigned char asc2_3216[95][128]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x00,0xC0,0x07,0xFF,0xE1,0xE0,0x07,0xF0,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/ +{0x00,0x00,0x00,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x00,0x00,0x00},/*"#",3*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x78,0x07,0xC0,0x00,0xFC,0x06,0x40,0x01,0x0E,0x00,0x20,0x03,0x07,0x00,0x20,0x02,0x03,0x80,0x20,0x0F,0xFF,0xFF,0xFC,0x02,0x01,0xC0,0x20,0x02,0x00,0xE0,0x60,0x01,0x30,0x70,0x40,0x01,0xF0,0x3F,0x80,0x00,0xF0,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/ +{0x00,0xFE,0x00,0x00,0x01,0xFF,0x00,0x00,0x03,0x01,0x80,0x00,0x02,0x00,0x80,0x60,0x03,0x01,0x81,0xC0,0x01,0xFF,0x07,0x00,0x00,0xFE,0x18,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0xBF,0x00,0x00,0x0C,0xFF,0xC0,0x00,0x71,0x80,0x60,0x01,0xC1,0x00,0x20,0x03,0x01,0x80,0x60,0x00,0x00,0xFF,0xC0,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00},/*"%",5*/ +{0x00,0x00,0x1F,0x00,0x00,0x00,0x7F,0xC0,0x00,0xFC,0xC0,0xC0,0x01,0xFF,0x80,0x60,0x03,0x03,0xE0,0x20,0x02,0x02,0x78,0x20,0x02,0x06,0x1E,0x20,0x03,0xFC,0x07,0x40,0x01,0xF0,0x03,0x80,0x00,0x01,0x03,0xC0,0x00,0x01,0x1C,0x60,0x00,0x01,0xE0,0x20,0x00,0x01,0x00,0x20,0x00,0x01,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"&",6*/ +{0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x1C,0x60,0x00,0x00,0x1C,0x40,0x00,0x00,0x1F,0x80,0x00,0x00,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x78,0x07,0xC0,0x01,0xC0,0x00,0xE0,0x03,0x00,0x00,0x30,0x04,0x00,0x00,0x08,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00},/*"(",8*/ +{0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x04,0x00,0x00,0x08,0x03,0x00,0x00,0x30,0x01,0xC0,0x00,0xE0,0x00,0x78,0x07,0xC0,0x00,0x3F,0xFF,0x00,0x00,0x07,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x18,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x61,0x43,0x80,0x00,0xFF,0xFF,0x80,0x00,0x61,0x43,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x0C,0x18,0x00,0x00,0x00,0x00,0x00},/*"*",10*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"+",11*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xE3,0x00,0x00,0x00,0xE2,0x00,0x00,0x00,0xFC,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"-",13*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x00,0x00,0x01,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"/",15*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x03,0x00,0x00,0x60,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x80,0x00,0xC0,0x00,0xE0,0x03,0x80,0x00,0x7F,0xFF,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x60,0x01,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0xE0,0x00,0x98,0x01,0x60,0x01,0x00,0x02,0x60,0x02,0x00,0x04,0x60,0x02,0x00,0x08,0x60,0x02,0x00,0x10,0x60,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0x60,0x03,0x00,0x80,0x60,0x01,0x83,0x00,0x60,0x01,0xFE,0x00,0xE0,0x00,0x7C,0x07,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x80,0x01,0xF0,0x07,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x80,0x20,0x01,0x86,0x80,0x40,0x01,0xFC,0xC0,0xC0,0x00,0x78,0x7F,0x80,0x00,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x48,0x00,0x00,0x01,0x88,0x00,0x00,0x06,0x08,0x00,0x00,0x0C,0x08,0x10,0x00,0x30,0x08,0x10,0x00,0x40,0x08,0x10,0x01,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x00,0x00},/*"4",20*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x1F,0x86,0x40,0x03,0xE1,0x00,0x20,0x03,0x02,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x06,0x00,0x40,0x03,0x03,0x01,0xC0,0x03,0x01,0xFF,0x80,0x03,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0xC3,0x80,0x00,0x81,0x80,0xC0,0x01,0x01,0x00,0x60,0x03,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x03,0x00,0x40,0x01,0xC1,0x80,0xC0,0x00,0xC0,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"6",22*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x03,0xC0,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x03,0x00,0x07,0xE0,0x03,0x00,0x3F,0xE0,0x03,0x01,0xC0,0x00,0x03,0x06,0x00,0x00,0x03,0x18,0x00,0x00,0x03,0x60,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"7",23*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x00,0x78,0x3F,0x80,0x00,0xFC,0x60,0xC0,0x01,0x8E,0xC0,0x40,0x03,0x07,0x80,0x20,0x02,0x03,0x00,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0xC0,0x20,0x03,0x01,0xE0,0x40,0x01,0x86,0x70,0xC0,0x00,0xFC,0x3F,0x80,0x00,0x78,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"8",24*/ +{0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0xFF,0x81,0xC0,0x01,0xC0,0xC1,0xC0,0x01,0x00,0x60,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0xC0,0x01,0x00,0xC1,0x80,0x00,0xC1,0x8F,0x00,0x00,0x7F,0xFE,0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0xC0,0x00,0x07,0x81,0xE0,0x00,0x07,0x81,0xE0,0x00,0x03,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x66,0x00,0x06,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0xC0,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0x00,0x30,0x06,0x00,0x00,0x60,0x03,0x00,0x00,0xC0,0x01,0x80,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x04,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"<",28*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x00,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x10,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x00,0xC0,0x01,0x80,0x00,0x60,0x03,0x00,0x00,0x30,0x06,0x00,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x01,0xC0,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*">",30*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x02,0x38,0x00,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0xC0,0x04,0x00,0x79,0xE0,0x04,0x00,0x81,0xE0,0x04,0x01,0x00,0xC0,0x04,0x03,0x00,0x00,0x02,0x02,0x00,0x00,0x03,0x06,0x00,0x00,0x01,0xFC,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"?",31*/ +{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x01,0xF8,0x40,0x03,0x07,0xFC,0x20,0x02,0x1E,0x04,0x20,0x02,0x30,0x08,0x20,0x02,0x20,0x30,0x20,0x02,0x3F,0xFC,0x20,0x01,0x3F,0x04,0x40,0x01,0x80,0x0C,0xC0,0x00,0xE0,0x31,0x80,0x00,0x1F,0xC2,0x00,0x00,0x00,0x00,0x00},/*"@",32*/ +{0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x03,0x80,0x20,0x00,0x07,0xFC,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x03,0xFE,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"A",33*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x00,0x20,0x01,0x86,0x80,0x60,0x01,0xFC,0xC0,0xC0,0x00,0xF8,0x7F,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x00,0x00},/*"B",34*/ +{0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x03,0xC0,0x01,0x80,0x00,0x30,0x06,0x00,0x00,0x00,0x00,0x00},/*"C",35*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x07,0x80,0x00,0x7F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"D",36*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x03,0x80,0x20,0x02,0x0F,0xE0,0x20,0x03,0x00,0x00,0x60,0x03,0xC0,0x00,0xE0,0x00,0x60,0x03,0x00,0x00,0x00,0x00,0x00},/*"E",37*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x03,0x80,0x00,0x03,0x0F,0xE0,0x00,0x03,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x00,0x60,0x00,0x00},/*"F",38*/ +{0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x01,0xC0,0x01,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x20,0x20,0x01,0x00,0x20,0x40,0x03,0xC0,0x3F,0x80,0x00,0x30,0x3F,0x80,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00},/*"G",39*/ +{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"H",40*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x03,0x02,0x00,0x00,0x06,0x03,0xFF,0xFF,0xFC,0x03,0xFF,0xFF,0xF8,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"J",42*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0xC0,0x20,0x02,0x01,0x00,0x20,0x00,0x07,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x30,0xF8,0x00,0x02,0x60,0x3E,0x20,0x03,0x80,0x0F,0x20,0x03,0x00,0x03,0xE0,0x02,0x00,0x00,0xE0,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"K",43*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"L",44*/ +{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xE0,0x00,0x20,0x03,0xFF,0x00,0x20,0x00,0x1F,0xF0,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x1E,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x00,0x20,0x03,0xE0,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20},/*"M",45*/ +{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0x80,0x00,0x20,0x03,0xF0,0x00,0x20,0x00,0xFC,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x01,0xF0,0x00,0x00,0x00,0x7C,0x00,0x02,0x00,0x1F,0x80,0x02,0x00,0x07,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"N",46*/ +{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x03,0x80,0x00,0x3F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"O",47*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x02,0x00,0x80,0x00,0x03,0x01,0x80,0x00,0x01,0x83,0x00,0x00,0x00,0xFE,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00},/*"P",48*/ +{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0xF0,0x03,0x80,0x01,0x80,0x01,0xC0,0x01,0x00,0x06,0x40,0x02,0x00,0x04,0x20,0x02,0x00,0x04,0x20,0x02,0x00,0x06,0x20,0x02,0x00,0x03,0xE0,0x01,0x00,0x00,0xF8,0x01,0x80,0x00,0x5C,0x00,0xE0,0x03,0x8C,0x00,0x3F,0xFF,0x0C,0x00,0x0F,0xFC,0x18,0x00,0x00,0x00,0x00},/*"Q",49*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x80,0x00,0x02,0x01,0xE0,0x00,0x02,0x01,0xFC,0x00,0x03,0x03,0x3F,0x80,0x01,0x86,0x07,0xE0,0x01,0xFC,0x00,0xE0,0x00,0xF8,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"R",50*/ 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+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x00,0xE3,0x3E,0x00,0x03,0xFF,0xC2,0x00,0x02,0x0C,0xC3,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x06,0x0C,0xC1,0x00,0x03,0xF8,0xC3,0x00,0x05,0xF0,0x62,0x00,0x06,0x00,0x7E,0x00,0x06,0x00,0x3C,0x00,0x00,0x00,0x00},/*"g",71*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"h",72*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x03,0x87,0xFF,0xE0,0x03,0x8F,0xFF,0xE0,0x03,0x80,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x03,0x00,0x04,0x00,0x06,0x03,0x87,0xFF,0xFC,0x03,0x8F,0xFF,0xF8,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x08,0x20,0x00,0x00,0x10,0x20,0x00,0x00,0x30,0x00,0x00,0x00,0xFC,0x00,0x00,0x05,0x8E,0x00,0x00,0x07,0x07,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0xE0,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"k",75*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"m",77*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"n",78*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0xFF,0x80,0x00,0x03,0x81,0xC0,0x00,0x02,0x00,0x40,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x02,0x00,0x40,0x00,0x03,0x81,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"o",79*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x07,0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0x00,0x01,0x00,0xC1,0x00,0x02,0x00,0x41,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x40,0x00,0x03,0x01,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x80,0xC0,0x00,0x02,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x02,0x00,0x41,0x00,0x03,0x00,0xC1,0x00,0x03,0xFF,0xFF,0x00,0x07,0xFF,0xFF,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01},/*"q",81*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x0F,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x00,0xC0,0x20,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x00,0x01,0xC0,0xE0,0x00,0x03,0xE0,0x40,0x00,0x06,0x30,0x20,0x00,0x04,0x30,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x0C,0x20,0x00,0x02,0x0C,0x60,0x00,0x03,0x07,0xC0,0x00,0x07,0x83,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0xFF,0xFF,0xC0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x04,0x00,0x80,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40},/*"u",85*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x80,0x00,0x00,0x07,0xF0,0x00,0x00,0x04,0xFE,0x00,0x00,0x04,0x1F,0xC0,0x00,0x00,0x03,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x1C,0x00,0x00,0x04,0x60,0x00,0x00,0x07,0x80,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"v",86*/ +{0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x07,0xFC,0x00,0x00,0x04,0x3F,0x80,0x00,0x00,0x03,0xE0,0x00,0x04,0x0F,0x80,0x00,0x06,0xF0,0x00,0x00,0x07,0xF0,0x00,0x00,0x07,0xFF,0x80,0x00,0x04,0x0F,0xE0,0x00,0x00,0x03,0x80,0x00,0x04,0x3C,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00},/*"w",87*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x60,0x00,0x07,0x00,0xE0,0x00,0x07,0x83,0x20,0x00,0x07,0xE6,0x00,0x00,0x04,0xF8,0x00,0x00,0x00,0x3C,0x00,0x00,0x04,0x5E,0x20,0x00,0x05,0x87,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"x",88*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x03,0x00,0x07,0x00,0x03,0x00,0x07,0xE0,0x01,0x00,0x04,0xF8,0x01,0x00,0x04,0x1F,0x02,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0xE0,0x00,0x00,0x07,0x00,0x00,0x04,0x38,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00},/*"y",89*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x60,0x00,0x06,0x00,0xE0,0x00,0x04,0x03,0xE0,0x00,0x04,0x07,0xA0,0x00,0x04,0x0E,0x20,0x00,0x04,0x3C,0x20,0x00,0x04,0x70,0x20,0x00,0x05,0xE0,0x20,0x00,0x07,0x80,0x20,0x00,0x07,0x00,0x60,0x00,0x04,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0x40,0x00,0x07,0xFE,0x3F,0xF8,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x07,0xFE,0x3F,0xF8,0x00,0x01,0x40,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/ +}; +#endif diff --git a/FW/Core/my_src/font_text.c b/FW/Core/my_src/font_text.c new file mode 100644 index 0000000..ffa2113 --- /dev/null +++ b/FW/Core/my_src/font_text.c @@ -0,0 +1,163 @@ +#include "w25qxx.h" +#include "ltdc_drv.h" +#include "font_text.h" +#include "string.h" +#include "lcd_base_display.h" +#include "file_cache.h" +#include "internal_flash.h" + +#define F24addr FLASH_FONT_START_ADDR + +void set_font_color(unsigned int point_color, unsigned int back_color) +{ + POINT_COLOR = point_color; + BACK_COLOR = back_color; +} + +//code 字符指针开始 +//从字库中查找出字模 +//code 字符串的开始地址,GBK码 +//mat 数据存放地址 (size/8+((size%8)?1:0))*(size) bytes大小 +//size:字体大小 +void Get_HzMat(unsigned char *code,unsigned char *mat,unsigned char size) +{ + static unsigned char kkk[256]; + unsigned char qh,ql; + unsigned char i; + unsigned long foffset; + unsigned char csize=(size/8+((size%8)?1:0))*(size);//得到字体一个字符对应点阵集所占的字节数 + qh=*code; + ql=*(++code); + /* + if(qh<0x81||ql<0x40||ql==0xff||qh==0xff)//非常用汉字 + { + for(i=0;i0x80)bHz=1;//中文 + else //字符 + { + if(x>(x0+width-size/2))//换行 + { + y+=size; + x=x0; + } + if(y>(y0+height-size))break;//越界返回 + if(*str==13)//换行符号 + { + y+=size; + x=x0; + str++; + } + else LCD_ShowChar(x,y,*str,size,mode);//有效部分写入 + str++; + x+=size/2; //字符,为全字的一半 + } + }else//中文 + { + bHz=0;//有汉字库 + if(x>(x0+width-size))//换行 + { + y+=size; + x=x0; + } + if(y>(y0+height-size))break;//越界返回 + Show_Font(x,y,str,size,mode); //显示这个汉字,空心显示 + str+=2; + x+=size;//下一个汉字偏移 + } + } +} +//在指定宽度的中间显示字符串 +//如果字符长度超过了len,则用Show_Str显示 +//len:指定要显示的宽度 +void Show_Str_Mid(unsigned short x,unsigned short y,unsigned char*str,unsigned char size,unsigned char len) +{ + unsigned short strlenth=0; + strlenth=strlen((const char*)str); + strlenth*=size/2; + /* + if(strlenth>len)Show_Str(x,y,lcddev.width,lcddev.height,str,size,1); + else + { + strlenth=(len-strlenth)/2; + Show_Str(strlenth+x,y,lcddev.width,lcddev.height,str,size,1); + } + */ +} diff --git a/FW/Core/my_src/font_text.h b/FW/Core/my_src/font_text.h new file mode 100644 index 0000000..cbbe3b0 --- /dev/null +++ b/FW/Core/my_src/font_text.h @@ -0,0 +1,20 @@ +#ifndef __TEXT_H__ +#define __TEXT_H__ +////////////////////////////////////////////////////////////////////////////////// +//本程序只供学习使用，未经作者许可，不得用于其它任何用途 +//ALIENTEK STM32开发板 +//汉字显示 驱动代码 +//正点原子@ALIENTEK +//技术论坛:www.openedv.com +//创建日期:2016/1/7 +//版本：V1.0 +//版权所有，盗版必究。 +//Copyright(C) 广州市星翼电子科技有限公司 2014-2024 +//All rights reserved +////////////////////////////////////////////////////////////////////////////////// + +void Get_HzMat(unsigned char *code,unsigned char *mat,unsigned char size); //得到汉字的点阵码 +void Show_Font(unsigned short x,unsigned short y,unsigned char *font,unsigned char size,unsigned char mode); //在指定位置显示一个汉字 +void Show_Str(unsigned short x,unsigned short y,unsigned short width,unsigned short height,unsigned char*str,unsigned char size,unsigned char mode); //在指定位置显示一个字符串 +void Show_Str_Mid(unsigned short x,unsigned short y,unsigned char*str,unsigned char size,unsigned char len); +#endif diff --git a/FW/Core/my_src/internal_flash.c b/FW/Core/my_src/internal_flash.c new file mode 100644 index 0000000..478dccb --- /dev/null +++ b/FW/Core/my_src/internal_flash.c @@ -0,0 +1,232 @@ +#include "main.h" +#include "internal_flash.h" + +T_Factory_Prm factory_prm; + +static FLASH_EraseInitTypeDef EraseInitStruct; + +unsigned int FirstSector = 0, BankNum = FLASH_BANK_1, NbOfSectors = 0; +unsigned int Address = 0, SECTORError = 0, Index = 0; +__IO unsigned int MemoryProgramStatus = 0; +__IO uint64_t data64 = 0; + +/** + * @brief Gets the sector of a given address + * @param Address Address of the FLASH Memory + * @retval The sector of a given address + */ +unsigned int GetSector(unsigned int Address) +{ + unsigned int sector = 0; + + if(((Address < ADDR_FLASH_SECTOR_1_BANK1) && (Address >= ADDR_FLASH_SECTOR_0_BANK1)) || \ + ((Address < ADDR_FLASH_SECTOR_1_BANK2) && (Address >= ADDR_FLASH_SECTOR_0_BANK2))) + { + sector = FLASH_SECTOR_0; + } + else if(((Address < ADDR_FLASH_SECTOR_2_BANK1) && (Address >= ADDR_FLASH_SECTOR_1_BANK1)) || \ + ((Address < ADDR_FLASH_SECTOR_2_BANK2) && (Address >= ADDR_FLASH_SECTOR_1_BANK2))) + { + sector = FLASH_SECTOR_1; + } + else if(((Address < ADDR_FLASH_SECTOR_3_BANK1) && (Address >= ADDR_FLASH_SECTOR_2_BANK1)) || \ + ((Address < ADDR_FLASH_SECTOR_3_BANK2) && (Address >= ADDR_FLASH_SECTOR_2_BANK2))) + { + sector = FLASH_SECTOR_2; + } + else if(((Address < ADDR_FLASH_SECTOR_4_BANK1) && (Address >= ADDR_FLASH_SECTOR_3_BANK1)) || \ + ((Address < ADDR_FLASH_SECTOR_4_BANK2) && (Address >= ADDR_FLASH_SECTOR_3_BANK2))) + { + sector = FLASH_SECTOR_3; + } + else if(((Address < ADDR_FLASH_SECTOR_5_BANK1) && (Address >= ADDR_FLASH_SECTOR_4_BANK1)) || \ + ((Address < ADDR_FLASH_SECTOR_5_BANK2) && (Address >= ADDR_FLASH_SECTOR_4_BANK2))) + { + sector = FLASH_SECTOR_4; + } + else if(((Address < ADDR_FLASH_SECTOR_6_BANK1) && (Address >= ADDR_FLASH_SECTOR_5_BANK1)) || \ + ((Address < ADDR_FLASH_SECTOR_6_BANK2) && (Address >= ADDR_FLASH_SECTOR_5_BANK2))) + { + sector = FLASH_SECTOR_5; + } + else if(((Address < ADDR_FLASH_SECTOR_7_BANK1) && (Address >= ADDR_FLASH_SECTOR_6_BANK1)) || \ + ((Address < ADDR_FLASH_SECTOR_7_BANK2) && (Address >= ADDR_FLASH_SECTOR_6_BANK2))) + { + sector = FLASH_SECTOR_6; + } + else if(((Address < ADDR_FLASH_SECTOR_0_BANK2) && (Address >= ADDR_FLASH_SECTOR_7_BANK1)) || \ + ((Address < FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_7_BANK2))) + { + sector = FLASH_SECTOR_7; + } + else + { + sector = FLASH_SECTOR_7; + } + + return sector; +} + +unsigned int GetBank(unsigned int Address) +{ + unsigned int bank = 0; + + if(IS_FLASH_PROGRAM_ADDRESS_BANK1(Address)) + { + bank = FLASH_BANK_1; + } + else + { + bank = FLASH_BANK_2; + } + + return bank; +} + +void erase_internal_one_sector(unsigned int Address) +{ + HAL_FLASH_Unlock(); + + /* -3- Erase the user Flash area + (area defined by FLASH_USER_START_ADDR and FLASH_USER_END_ADDR) ***********/ + + /* Get the 1st sector to erase */ + FirstSector = GetSector(Address); + /* Get the number of sector to erase from 1st sector*/ + NbOfSectors = 1; + + BankNum = GetBank(Address); + + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS; + EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3; + EraseInitStruct.Banks = BankNum; + EraseInitStruct.Sector = FirstSector; + EraseInitStruct.NbSectors = NbOfSectors; + + if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK) + { + /* + Error occurred while sector erase. + User can add here some code to deal with this error. + SECTORError will contain the faulty sector and then to know the code error on this sector, + user can call function 'HAL_FLASH_GetError()' + */ + /* Infinite loop */ + while (1) + { + __nop(); + } + } + HAL_FLASH_Lock(); +} + +void write_internal_flash(unsigned int Address, unsigned int val_addr)//Address 32uint, write 32byte +{ + uint64_t val_check; + + //HAL_FLASH_Unlock(); + + if(HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, Address, (uint64_t)val_addr) == HAL_OK) + { + __nop(); + } + else + { + /* Error occurred while writing data in Flash memory. + User can add here some code to deal with this error */ + while (1) + { + __nop(); + } + } + //HAL_FLASH_Lock(); +} + +void read_internal_flash(unsigned int start_address, unsigned int * val_addr, unsigned int num)//num 8byte multiple +{ + unsigned int i = 0; + unsigned int * p_val_addr; + p_val_addr = val_addr; + + for(i=0;i>8) & 0xFF; + factory_prm.pid[2] = (pid_temp>>16) & 0xFF; + factory_prm.pid[3] = (pid_temp>>24) & 0xFF; + + pid_temp = *(__IO uint32_t *)(falsh_addr + 16); + factory_prm.pid[4] = pid_temp & 0xFF; + factory_prm.pid[5] = (pid_temp>>8) & 0xFF; + factory_prm.pid[6] = (pid_temp>>16) & 0xFF; + factory_prm.pid[7] = (pid_temp>>24) & 0xFF; + + pid_temp = *(__IO uint32_t *)(falsh_addr + 20); + factory_prm.pid[8] = pid_temp & 0xFF; + factory_prm.pid[9] = (pid_temp>>8) & 0xFF; + factory_prm.pid[10] = (pid_temp>>16) & 0xFF; + factory_prm.pid[11] = (pid_temp>>24) & 0xFF; + } + + factory_prm.ctl_type = (*(__IO uint32_t *)(falsh_addr + 24))&0xFF; + if((0 == factory_prm.ctl_type)||(0xFF == factory_prm.ctl_type))factory_prm.ctl_type = 1; + + if(factory_prm.open_password_isenable > 1)factory_prm.open_password_isenable = 1; + if(factory_prm.auth_function_isenable > 1)factory_prm.auth_function_isenable = 0; + factory_prm.open_password_isenable = 0; +} diff --git a/FW/Core/my_src/internal_flash.h b/FW/Core/my_src/internal_flash.h new file mode 100644 index 0000000..bb004af --- /dev/null +++ b/FW/Core/my_src/internal_flash.h @@ -0,0 +1,52 @@ +#ifndef INTERNAL_FALSH_H +#define INTERNAL_FALSH_H + +#define FLASH_USER_FONT_24X24 ADDR_FLASH_SECTOR_2_BANK2 // +#define FLASH_USER_FONT_24X24_SECTOR_NUM 4 + +#define FLASH_USER_FACTORY_PRM ADDR_FLASH_SECTOR_6_BANK2 // +#define FLASH_USER_FACTORY_PRM_SECTOR_NUM 1 + +#define FLASH_USER_PIC ADDR_FLASH_SECTOR_7_BANK2 + +#define FLASH_USER_PIC_16X16 FLASH_USER_PIC //one sector 128 pic, use half +#define FLASH_USER_PIC_16X16_UINT 1024//16*16*4 byte +#define FLASH_USER_PIC_16X16_COUNT_MAX 32 +//#define FLASH_USER_PIC_16X16_SECTOR_NUM 1 + +#define FLASH_USER_PIC_24X24 FLASH_USER_PIC_16X16 + (FLASH_USER_PIC_16X16_UINT * FLASH_USER_PIC_16X16_COUNT_MAX) //one sector 56 pic +#define FLASH_USER_PIC_24X24_UINT 2304//24*24*4 byte +#define FLASH_USER_PIC_24X24_COUNT_MAX 24 +//#define FLASH_USER_PIC_24X24_SECTOR_NUM 2 + +#define FLASH_USER_PIC_32X32 FLASH_USER_PIC_24X24 + (FLASH_USER_PIC_24X24_UINT * FLASH_USER_PIC_24X24_COUNT_MAX) //one sector 32 pic +#define FLASH_USER_PIC_32X32_UINT 4096//32*32*4 byte +#define FLASH_USER_PIC_32X32_COUNT_MAX 4 +//#define FLASH_USER_PIC_32X32_SECTOR_NUM 1 + +#define FLASH_USER_PIC_LOGO FLASH_USER_PIC_32X32 + (FLASH_USER_PIC_32X32_UINT * FLASH_USER_PIC_32X32_COUNT_MAX) +#define FLASH_USER_PIC_LOGO24_UINT 8640//24*90*4 byte +#define FLASH_USER_PIC_LOGO32_UINT 15616//32*122*4 byte +#define FLASH_USER_PIC_LOGO24 FLASH_USER_PIC_LOGO +#define FLASH_USER_PIC_LOGO32 (FLASH_USER_PIC_LOGO + FLASH_USER_PIC_LOGO24_UINT) + +typedef struct{//32byte + unsigned int open_password_isenable; + unsigned int rsv1; + unsigned int auth_function_isenable; + unsigned char pid[12]; + unsigned int ctl_type; + unsigned int pwr; +}T_Factory_Prm; + +extern T_Factory_Prm factory_prm; + +extern void reset_factory_prm(void); +extern void write_factory_prm(void); +extern void read_factory_prm(void); + +extern void erase_internal_one_sector(unsigned int Address); +extern void write_internal_flash(unsigned int Address, unsigned int val_addr); +extern void read_internal_flash(unsigned int start_address, unsigned int * val_addr, unsigned int num); + +#endif diff --git a/FW/Core/my_src/lcd_base_display.c b/FW/Core/my_src/lcd_base_display.c new file mode 100644 index 0000000..05a7db3 --- /dev/null +++ b/FW/Core/my_src/lcd_base_display.c @@ -0,0 +1,311 @@ +#include "lcd_base_display.h" +#include "stdlib.h" +#include "font.h" +//#include "delay.h" +#include "ltdc_drv.h" + +//LCD的画笔颜色和背景色 +unsigned int POINT_COLOR=0xFFFF00FF; //画笔颜色 +unsigned int BACK_COLOR =0xFF00FF00; //背景色 + +//管理LCD重要参数 +//默认为竖屏 +_lcd_dev lcddev; + +unsigned short LCD_BGR2RGB(unsigned short c) +{ + unsigned short r,g,b,rgb; + b=(c>>0)&0x1f; + g=(c>>5)&0x3f; + r=(c>>11)&0x1f; + rgb=(b<<11)+(g<<5)+(r<<0); + return(rgb); +} +//当mdk -O1时间优化时需要设置 +//延时i +void opt_delay(unsigned char i) +{ + while(i--); +} + +//LCD开启显示 +void LCD_DisplayOn(void) +{ + LTDC_Switch(1);//开启LCD +} +//LCD关闭显示 +void LCD_DisplayOff(void) +{ + LTDC_Switch(0);//关闭LCD +} +//画点 +//x,y:坐标 +//POINT_COLOR:此点的颜色 +void LCD_DrawPoint(unsigned short x,unsigned short y) +{ + LTDC_Draw_Point(x,y,POINT_COLOR); +} +//快速画点 +//x,y:坐标 +//color:颜色 +void LCD_Fast_DrawPoint(unsigned short x,unsigned short y,unsigned int color) +{ + LTDC_Draw_Point(x,y,color); +} + +//设置LCD显示方向 +//dir:0,竖屏；1,横屏 +void LCD_Display_Dir(unsigned char dir) +{ + lcddev.dir=dir; //横屏/竖屏 + if(lcdltdc.pwidth!=0) //如果是RGB屏 + { + LTDC_Display_Dir(dir); + lcddev.width=lcdltdc.width; + lcddev.height=lcdltdc.height; + return; + } +} + +//清屏函数 +//color:要清屏的填充色 +void LCD_Clear(unsigned int color) +{ + LTDC_Clear(color); +} +//在指定区域内填充单个颜色 +//(sx,sy),(ex,ey):填充矩形对角坐标,区域大小为:(ex-sx+1)*(ey-sy+1) +//color:要填充的颜色 +void LCD_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned int color) +{ + LTDC_Fill(sx,sy,ex,ey,color); +} +//在指定区域内填充指定颜色块 +//(sx,sy),(ex,ey):填充矩形对角坐标,区域大小为:(ex-sx+1)*(ey-sy+1) +//color:要填充的颜色 +void LCD_Color_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned short *color) +{ + LTDC_Color_Fill(sx,sy,ex,ey,color); +} +//画线 +//x1,y1:起点坐标 +//x2,y2:终点坐标 +void LCD_DrawLine(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2) +{ + unsigned short t; + int xerr=0,yerr=0,delta_x,delta_y,distance; + int incx,incy,uRow,uCol; + delta_x=x2-x1; //计算坐标增量 + delta_y=y2-y1; + uRow=x1; + uCol=y1; + if(delta_x>0)incx=1; //设置单步方向 + else if(delta_x==0)incx=0;//垂直线 + else {incx=-1;delta_x=-delta_x;} + if(delta_y>0)incy=1; + else if(delta_y==0)incy=0;//水平线 + else{incy=-1;delta_y=-delta_y;} + if( delta_x>delta_y)distance=delta_x; //选取基本增量坐标轴 + else distance=delta_y; + for(t=0;t<=distance+1;t++ )//画线输出 + { + LCD_DrawPoint(uRow,uCol);//画点 + xerr+=delta_x ; + yerr+=delta_y ; + if(xerr>distance) + { + xerr-=distance; + uRow+=incx; + } + if(yerr>distance) + { + yerr-=distance; + uCol+=incy; + } + } +} +//画矩形 +//(x1,y1),(x2,y2):矩形的对角坐标 +void LCD_DrawRectangle(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2) +{ + LCD_DrawLine(x1,y1,x2,y1); + LCD_DrawLine(x1,y1,x1,y2); + LCD_DrawLine(x1,y2,x2,y2); + LCD_DrawLine(x2,y1,x2,y2); +} +//在指定位置画一个指定大小的圆 +//(x,y):中心点 +//r :半径 +void LCD_Draw_Circle(unsigned short x0,unsigned short y0,unsigned char r) +{ + int a,b; + int di; + a=0;b=r; + di=3-(r<<1); //判断下个点位置的标志 + while(a<=b) + { + LCD_DrawPoint(x0+a,y0-b); //5 + LCD_DrawPoint(x0+b,y0-a); //0 + LCD_DrawPoint(x0+b,y0+a); //4 + LCD_DrawPoint(x0+a,y0+b); //6 + LCD_DrawPoint(x0-a,y0+b); //1 + LCD_DrawPoint(x0-b,y0+a); + LCD_DrawPoint(x0-a,y0-b); //2 + LCD_DrawPoint(x0-b,y0-a); //7 + a++; + //使用Bresenham算法画圆 + if(di<0)di +=4*a+6; + else + { + di+=10+4*(a-b); + b--; + } + } +} +//在指定位置显示一个字符 +//x,y:起始坐标 +//num:要显示的字符:" "--->"~" +//size:字体大小 12/16/24/32 +//mode:叠加方式(1)还是非叠加方式(0) +void LCD_ShowChar(unsigned short x,unsigned short y,unsigned char num,unsigned char size,unsigned char mode) +{ + unsigned char temp,t1,t; + unsigned short y0=y; + unsigned char csize=(size/8+((size%8)?1:0))*(size/2); //得到字体一个字符对应点阵集所占的字节数 + num=num-' ';//得到偏移后的值（ASCII字库是从空格开始取模，所以-' '就是对应字符的字库） + for(t=0;t=lcddev.height)return; //超区域了 + if((y-y0)==size) + { + y=y0; + x++; + if(x>=lcddev.width)return; //超区域了 + break; + } + } + } +} +//m^n函数 +//返回值:m^n次方. +unsigned int LCD_Pow(unsigned char m,unsigned char n) +{ + unsigned int result=1; + while(n--)result*=m; + return result; +} +//显示数字,高位为0,则不显示 +//x,y :起点坐标 +//len :数字的位数 +//size:字体大小 +//color:颜色 +//num:数值(0~4294967295); +void LCD_ShowNum(unsigned short x,unsigned short y,unsigned int num,unsigned char len,unsigned char size) +{ + unsigned char t,temp; + unsigned char enshow=0; + for(t=0;t=' '))//判断是不是非法字符! + { + if(x>=width){x=x0;y+=size;} + if(y>=height)break;//退出 + LCD_ShowChar(x,y,*p,size,0); + x+=size/2; + p++; + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FW/Core/my_src/lcd_base_display.h b/FW/Core/my_src/lcd_base_display.h new file mode 100644 index 0000000..21d2db1 --- /dev/null +++ b/FW/Core/my_src/lcd_base_display.h @@ -0,0 +1,143 @@ +#ifndef __LCD_H +#define __LCD_H +#include "stdlib.h" +////////////////////////////////////////////////////////////////////////////////// +//本程序只供学习使用，未经作者许可，不得用于其它任何用途 +//ALIENTEK STM32开发板 +//2.8寸/3.5寸/4.3寸/7寸 TFT液晶驱动 +//支持驱动IC型号包括:ILI9341/NT35310/NT35510/SSD1963等 +//正点原子@ALIENTEK +//技术论坛:www.openedv.com +//创建日期:2015/12/10 +//版本：V1.0 +//版权所有，盗版必究。 +//Copyright(C) 广州市星翼电子科技有限公司 2014-2024 +//All rights reserved +////////////////////////////////////////////////////////////////////////////////// + +//LCD重要参数集 +typedef struct +{ + unsigned short width; //LCD 宽度 + unsigned short height; //LCD 高度 + unsigned short id; //LCD ID + unsigned char dir; //横屏还是竖屏控制：0，竖屏；1，横屏。 + unsigned short wramcmd; //开始写gram指令 + unsigned short setxcmd; //设置x坐标指令 + unsigned short setycmd; //设置y坐标指令 +}_lcd_dev; + +//LCD参数 +extern _lcd_dev lcddev; //管理LCD重要参数 +//LCD的画笔颜色和背景色 +extern unsigned int POINT_COLOR;//默认红色 +extern unsigned int BACK_COLOR; //背景颜色.默认为白色 + +//LCD MPU保护参数 +#define LCD_REGION_NUMBER MPU_REGION_NUMBER0 //LCD使用region0 +#define LCD_ADDRESS_START (0X60000000) //LCD区的首地址 +#define LCD_REGION_SIZE MPU_REGION_SIZE_256MB //LCD区大小 + +////////////////////////////////////////////////////////////////////////////////// +//-----------------MCU屏 LCD端口定义---------------- +//LCD背光 PB5 +#define LCD_LED(n) (n?HAL_GPIO_WritePin(GPIOB,GPIO_PIN_5,GPIO_PIN_SET):HAL_GPIO_WritePin(GPIOB,GPIO_PIN_5,GPIO_PIN_RESET)) +//LCD地址结构体 + +//使用NOR/SRAM的 Bank1.sector4,地址位HADDR[27,26]=11 A18作为数据命令区分线 +//注意设置时STM32内部会右移一位对其! +#define LCD_BASE ((unsigned int)(0x60000000 | 0x0007FFFE)) +#define LCD ((LCD_TypeDef *) LCD_BASE) +////////////////////////////////////////////////////////////////////////////////// + +//扫描方向定义 +#define L2R_U2D 0 //从左到右,从上到下 +#define L2R_D2U 1 //从左到右,从下到上 +#define R2L_U2D 2 //从右到左,从上到下 +#define R2L_D2U 3 //从右到左,从下到上 + +#define U2D_L2R 4 //从上到下,从左到右 +#define U2D_R2L 5 //从上到下,从右到左 +#define D2U_L2R 6 //从下到上,从左到右 +#define D2U_R2L 7 //从下到上,从右到左 + +#define DFT_SCAN_DIR L2R_U2D //默认的扫描方向 + +//画笔颜色 +#define WHITE 0xFFFF +#define BLACK 0x0000 +#define BLUE 0x001F +#define BRED 0XF81F +#define GRED 0XFFE0 +#define GBLUE 0X07FF +#define RED 0xF800 +#define MAGENTA 0xF81F +#define GREEN 0x07E0 +#define CYAN 0x7FFF +#define YELLOW 0xFFE0 +#define BROWN 0XBC40 //棕色 +#define BRRED 0XFC07 //棕红色 +#define GRAY 0X8430 //灰色 +//GUI颜色 + +#define DARKBLUE 0X01CF //深蓝色 +#define LIGHTBLUE 0X7D7C //浅蓝色 +#define GRAYBLUE 0X5458 //灰蓝色 +//以上三色为PANEL的颜色 + +#define LIGHTGREEN 0X841F //浅绿色 +//#define LIGHTGRAY 0XEF5B //浅灰色(PANNEL) +#define LGRAY 0XC618 //浅灰色(PANNEL),窗体背景色 + +#define LGRAYBLUE 0XA651 //浅灰蓝色(中间层颜色) +#define LBBLUE 0X2B12 //浅棕蓝色(选择条目的反色) + +void LCD_Init(void); //初始化 +void LCD_DisplayOn(void); //开显示 +void LCD_DisplayOff(void); //关显示 +void LCD_Clear(unsigned int Color); //清屏 +void LCD_SetCursor(unsigned short Xpos, unsigned short Ypos); //设置光标 +void LCD_DrawPoint(unsigned short x,unsigned short y); //画点 +void LCD_Fast_DrawPoint(unsigned short x,unsigned short y,unsigned int color); //快速画点 +unsigned int LCD_ReadPoint(unsigned short x,unsigned short y); //读点 +void LCD_Draw_Circle(unsigned short x0,unsigned short y0,unsigned char r); //画圆 +void LCD_DrawLine(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2); //画线 +void LCD_DrawRectangle(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2); //画矩形 +void LCD_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned int color); //填充单色 +void LCD_Color_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned short *color); //填充指定颜色 +void LCD_ShowChar(unsigned short x,unsigned short y,unsigned char num,unsigned char size,unsigned char mode); //显示一个字符 +void LCD_ShowNum(unsigned short x,unsigned short y,unsigned int num,unsigned char len,unsigned char size); //显示一个数字 +void LCD_ShowxNum(unsigned short x,unsigned short y,unsigned int num,unsigned char len,unsigned char size,unsigned char mode); //显示 数字 +void LCD_ShowString(unsigned short x,unsigned short y,unsigned short width,unsigned short height,unsigned char size,unsigned char *p); //显示一个字符串,12/16字体 + +void LCD_WriteReg(unsigned short LCD_Reg, unsigned short LCD_RegValue); +unsigned short LCD_ReadReg(unsigned short LCD_Reg); +void LCD_WriteRAM_Prepare(void); +void LCD_WriteRAM(unsigned short RGB_Code); +void LCD_SSD_BackLightSet(unsigned char pwm); //SSD1963 背光控制 +void LCD_Scan_Dir(unsigned char dir); //设置屏扫描方向 +void LCD_Display_Dir(unsigned char dir); //设置屏幕显示方向 +void LCD_Set_Window(unsigned short sx,unsigned short sy,unsigned short width,unsigned short height); //设置窗口 +//LCD分辨率设置 +#define SSD_HOR_RESOLUTION 800 //LCD水平分辨率 +#define SSD_VER_RESOLUTION 480 //LCD垂直分辨率 +//LCD驱动参数设置 +#define SSD_HOR_PULSE_WIDTH 1 //水平脉宽 +#define SSD_HOR_BACK_PORCH 46 //水平前廊 +#define SSD_HOR_FRONT_PORCH 210 //水平后廊 + +#define SSD_VER_PULSE_WIDTH 1 //垂直脉宽 +#define SSD_VER_BACK_PORCH 23 //垂直前廊 +#define SSD_VER_FRONT_PORCH 22 //垂直前廊 +//如下几个参数，自动计算 +#define SSD_HT (SSD_HOR_RESOLUTION+SSD_HOR_BACK_PORCH+SSD_HOR_FRONT_PORCH) +#define SSD_HPS (SSD_HOR_BACK_PORCH) +#define SSD_VT (SSD_VER_RESOLUTION+SSD_VER_BACK_PORCH+SSD_VER_FRONT_PORCH) +#define SSD_VPS (SSD_VER_BACK_PORCH) + +#endif + + + + + diff --git a/FW/Core/my_src/lcd_text.c b/FW/Core/my_src/lcd_text.c new file mode 100644 index 0000000..b9c0e3d --- /dev/null +++ b/FW/Core/my_src/lcd_text.c @@ -0,0 +1,457 @@ +#include "main.h" +#include "internal_flash.h" +#include "lcd_base_display.h" +#include "my_font.h" + +#define BIT8(n) ((unsigned char)((unsigned char)1<>4)>9) + gui_write_EN1608(x,y,CharColor,BackColor,(((hex&0xF0)>>4) - 0x0A +'A')); + else + gui_write_EN1608(x,y,CharColor,BackColor,(((hex&0xF0)>>4)+'0')); + + if((hex&0x0F)>9) + gui_write_EN1608((x+8),y,CharColor,BackColor,((hex&0x0F) - 0x0A +'A')); + else + gui_write_EN1608((x+8),y,CharColor,BackColor,((hex&0x0F)+'0')); +} + +void gui_write_num16(unsigned short x, unsigned short y, unsigned int CharColor, unsigned int BackColor, unsigned char num) +{ + gui_write_EN1608(x,y,CharColor,BackColor,(num+'0')); +} + +void gui_write_num(unsigned short x, unsigned short y, unsigned int CharColor, unsigned int BackColor, unsigned short num, unsigned char bit) +{ + if((bit > 4)||(0==bit))return; + LCD_Fill(x,y,(x+(bit<<3)-1),(y+8-1),BackColor); + if(4 == bit) + { + gui_write_num16(x,y,CharColor,BackColor,(num/1000%10)); + gui_write_num16((x+8),y,CharColor,BackColor,(num/100%10)); + gui_write_num16((x+16),y,CharColor,BackColor,(num/10%10)); + gui_write_num16((x+24),y,CharColor,BackColor,(num%10)); + } + else if(3 == bit) + { + gui_write_num16((x),y,CharColor,BackColor,(num/100%10)); + gui_write_num16((x+8),y,CharColor,BackColor,(num/10%10)); + gui_write_num16((x+16),y,CharColor,BackColor,(num%10)); + } + else if(2 == bit) + { + gui_write_num16(x,y,CharColor,BackColor,(num/10%10)); + gui_write_num16((x+8),y,CharColor,BackColor,(num%10)); + } + else if(1 == bit) + { + gui_write_num16(x,y,CharColor,BackColor,(num%10)); + } +} + +void gui_write_string16(unsigned short x, unsigned short y, unsigned int CharColor, unsigned int BackColor, const unsigned char* p) +{ + unsigned char dat; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN1608(x, y, CharColor, BackColor, dat); + x+=8; + } + else//?? + { + gui_write_CN16(x, y, CharColor, BackColor, (unsigned char*)p); + x+=16; + p++; + } + } +} + +unsigned int get_chinese_offset_24(const unsigned char *p) +{ + unsigned int d; + + d=72UL*( ((*p)-15-0xa1)*94 + ((*(p+1))-0xa1) ); + + return d; +} + +void gui_write_CN24(unsigned short x, unsigned short y, unsigned int CharColor, unsigned int BackColor, const unsigned char *p) +{ + const unsigned char* pbuf; + unsigned short ix, iy; + unsigned int address; + unsigned int offset = 0; + + offset = get_chinese_offset_24( p); + + text_buf = Hzk_24_data; + pbuf = &text_buf[offset]; //______________________________fill location + + for(ix=0; ix<24; ix++) + { + for(iy=0; iy<8; iy++) + { + if( isBit8(*pbuf, (7-iy))==0 ) + { + gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x, y+iy, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + for(iy=0; iy<8; iy++) + { + if( isBit8(*pbuf, (7-iy))==0 ) + { + gui_put_pixel(x, y+iy+8, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x, y+iy+8, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + for(iy=0; iy<8; iy++) + { + if( isBit8(*pbuf, (7-iy))==0 ) + { + gui_put_pixel(x, y+iy+16, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x, y+iy+16, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + x++; + } +} + +void gui_write_EN2412(unsigned short x, unsigned short y, unsigned int CharColor, unsigned int BackColor,unsigned char num) +{ + const unsigned char* pbuf; + unsigned short ix, iy; + unsigned int offset = 0; + + //num=num-' ';//得到偏移后的值（ASCII字库是从空格开始取模，所以-' '就是对应字符的字库） + offset = (num-' '); + pbuf = &asc2_2412[offset][0]; + + for(ix=0; ix<12; ix++) + { + for(iy=0; iy<8; iy++) + { + if( isBit8(*pbuf, (7-iy))==0 ) + { + gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x, y+iy, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + + for(iy=0; iy<8; iy++) + { + if( isBit8(*pbuf, (7-iy))==0 ) + { + gui_put_pixel(x, y+8+iy, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x, y+8+iy, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + + for(iy=0; iy<8; iy++) + { + if( isBit8(*pbuf, (7-iy))==0 ) + { + gui_put_pixel(x, y+16+iy, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x, y+16+iy, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + x++; + } +} + +void gui_write_EN2417(unsigned short x, unsigned short y, unsigned int CharColor, unsigned int BackColor,unsigned char num) +{ + const unsigned char* pbuf; + unsigned short ix, iy; + unsigned int offset = 0; + + //num=num-' ';//得到偏移后的值（ASCII字库是从空格开始取模，所以-' '就是对应字符的字库） + offset = (num-' ')*72; + text_buf = ascii_17x24_table; + pbuf = &text_buf[offset]; + + for(iy=0; iy<24; iy++) + { + for(ix=0; ix<8; ix++) + { + if( isBit8(*pbuf, (7-ix))==0 ) + { + gui_put_pixel(x+ix, y, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x+ix, y, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + for(ix=0; ix<8; ix++)//?1????8? + { + if( isBit8(*pbuf, (7-ix))==0 ) + { + gui_put_pixel(x+ix+8, y, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x+ix+8, y, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + for(ix=0; ix<8; ix++)//?1????8? + { + if( isBit8(*pbuf, (7-ix))==0 ) + { + gui_put_pixel(x+ix+16, y, 0, BackColor); //______________________________put pixel here + } + else + { + gui_put_pixel(x+ix+16, y, 0, CharColor); //______________________________put pixel here + } + } + + pbuf++; + y++; + } +} + +void gui_write_string24(unsigned short x, unsigned short y, unsigned int CharColor, unsigned int BackColor, const unsigned char* p) +{ + unsigned char dat; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN2412(x, y, CharColor, BackColor, dat); + x+=12; + //gui_write_EN2417(x, y, CharColor, BackColor, dat); + //x+=17; + } + + else//?? + { + gui_write_CN24(x, y, CharColor, BackColor, (unsigned char*)p); + x+=24; + p++; + } + } +} diff --git a/FW/Core/my_src/lcd_text.h b/FW/Core/my_src/lcd_text.h new file mode 100644 index 0000000..cdaa292 --- /dev/null +++ b/FW/Core/my_src/lcd_text.h @@ -0,0 +1,7 @@ + +extern void gui_write_EN1608(unsigned short x, unsigned short y, unsigned short CharColor, unsigned short BackColor,unsigned char num); +extern void gui_write_string16(unsigned short x, unsigned short y, unsigned short CharColor, unsigned short BackColor, const unsigned char* p); +extern void gui_write_hex16(unsigned short x, unsigned short y, unsigned short CharColor, unsigned short BackColor, unsigned char hex); +extern void gui_write_num16(unsigned short x, unsigned short y, unsigned short CharColor, unsigned short BackColor, unsigned char num); +extern void gui_write_num(unsigned short x, unsigned short y, unsigned short CharColor, unsigned short BackColor, unsigned short num, unsigned char bit); +extern void gui_write_star(unsigned short x, unsigned short y, unsigned short CharColor, unsigned short BackColor); diff --git a/FW/Core/my_src/load_gui_lib.c b/FW/Core/my_src/load_gui_lib.c new file mode 100644 index 0000000..727f294 --- /dev/null +++ b/FW/Core/my_src/load_gui_lib.c @@ -0,0 +1,517 @@ +#include "HW_config.h" +#include "fatfs.h" +#include "ff.h" +#include "internal_flash.h" +#include "sdram_addr_map.h" +#include "file_cache.h" +#include "w25qxx.h" +#include "usb_host.h" +#include "usb_device.h" + +//#define FLASH_SECTOR_SIZE 0x00020000 + +#define FONT_24X24_PATH "HZK/HZK24S" + +#define PIC_16X16_BMP_NUM 32 +#define PIC_24X24_BMP_NUM 24 +#define PIC_32X32_BMP_NUM 4 + +#define LCD_TOTAL_WIDTH 800 +#define LCD_LAYER1_ADDR 0xC0000000 + +Bmp_Parameter_TypeDef pic_16x16_bmp_prm[PIC_16X16_BMP_NUM]; +Bmp_Parameter_TypeDef pic_24x24_bmp_prm[PIC_24X24_BMP_NUM]; +Bmp_Parameter_TypeDef pic_32x32_bmp_prm[PIC_32X32_BMP_NUM]; +Bmp_Parameter_TypeDef pic_logo24_bmp_prm; +Bmp_Parameter_TypeDef pic_logo32_bmp_prm; + +extern ApplicationTypeDef Appli_state; +//volatile BYTE ReadBuffer[256]={0}; /* 读缓冲区 */ + +void load_pic_logo_bmp_to_flash(void); + +void pic_prm_init(void) +{ + unsigned int i = 0; + + for(i=0;i '9') + { + str_name[9] = '0'; + str_name[8] +=1; + if(str_name[8] > '9') + { + str_name[8] = '0'; + str_name[7] +=1; + } + } + } + + LL_IWDG_ReloadCounter(IWDG1); +} + +void load_pic_16x16_bmp_to_flash(void) +{ + unsigned int i = 0, size = 0; + unsigned int load_falsh_addr = 0; + unsigned int load_sdram_addr = 0; + + for(i=0;i '9') + { + str_name[9] = '0'; + str_name[8] +=1; + if(str_name[8] > '9') + { + str_name[8] = '0'; + str_name[7] +=1; + } + } + } + LL_IWDG_ReloadCounter(IWDG1); +} + +void load_pic_24x24_bmp_to_flash(void) +{ + unsigned int i = 0, size = 0; + unsigned int load_falsh_addr = 0; + unsigned int load_sdram_addr = 0; + + for(i=0;i '9') + { + str_name[9] = '0'; + str_name[8] +=1; + if(str_name[8] > '9') + { + str_name[8] = '0'; + str_name[7] +=1; + } + } + } + LL_IWDG_ReloadCounter(IWDG1); +} + +void load_pic_32x32_bmp_to_flash(void) +{ + unsigned int i = 0, size = 0; + unsigned int load_falsh_addr = 0; + unsigned int load_sdram_addr = 0; + + for(i=0;ipic_width; + uint32_t area_height = zone_pic->pic_height; + + uint32_t back_start_adress = pic_start_adress; + //uint32_t surface_start_adress = zone_pic->start_address; + uint32_t surface_start_adress = zone_pic->flash_address; + + back_start_adress = back_start_adress + (LCD_TOTAL_WIDTH * start_y * 4) + (start_x * 4); + + for(index_height = 0; index_height < area_height; index_height++) + { + for (index_width = 0; index_width < area_width; index_width++) + { + *(__IO uint32_t*) (back_start_adress) = *(__IO uint32_t *)surface_start_adress; + + back_start_adress+=4; + surface_start_adress+=4; + } + back_start_adress = back_start_adress + ((LCD_TOTAL_WIDTH - area_width) * 4); + } +} + +void load_pic_16x16_to_dispaly_layer(uint32_t start_x,uint32_t start_y,uint8_t pic_ord) +{ + if(pic_ord >= PIC_16X16_BMP_NUM)return; + load_pic_zone_on_full_screen(LCD_LAYER1_ADDR,start_x,start_y,&pic_16x16_bmp_prm[pic_ord]); +} + +void load_pic_24x24_to_dispaly_layer(uint32_t start_x,uint32_t start_y,uint8_t pic_ord) +{ + if(pic_ord >= PIC_24X24_BMP_NUM)return; + load_pic_zone_on_full_screen(LCD_LAYER1_ADDR,start_x,start_y,&pic_24x24_bmp_prm[pic_ord]); +} + +void load_pic_32x32_to_dispaly_layer(uint32_t start_x,uint32_t start_y,uint8_t pic_ord) +{ + if(pic_ord >= PIC_32X32_BMP_NUM)return; + load_pic_zone_on_full_screen(LCD_LAYER1_ADDR,start_x,start_y,&pic_32x32_bmp_prm[pic_ord]); +} + +void load_pic_logo24_to_dispaly_layer(uint32_t start_x,uint32_t start_y) +{ + load_pic_zone_on_full_screen(LCD_LAYER1_ADDR,start_x,start_y,&pic_logo24_bmp_prm); +} + +void load_pic_logo32_to_dispaly_layer(uint32_t start_x,uint32_t start_y) +{ + load_pic_zone_on_full_screen(LCD_LAYER1_ADDR,start_x,start_y,&pic_logo32_bmp_prm); +} + +void read_bmp_load_to_flash(void) +{ + load_pic_16x16_bmp(); + load_pic_24x24_bmp(); + load_pic_32x32_bmp(); + load_pic_logo_bmp(); + + load_pic_bmp_to_flash(); +} + +void load_hzk_pic_task(void)//100ms +{ + static unsigned int time_count = 80; + static unsigned int once_init = 1; + + if(time_count){ + time_count--; + + if(APPLICATION_READY == Appli_state){ + if(!(GPIOH->IDR & 0x0008)){//KEY + gui_write_string24(20,0,0xff000000,0xffff0000,"LOADING_HZK_PIC"); + //mount_usb_file_sys(); + //read_hzk_load_to_flash(); + read_bmp_load_to_flash(); + gui_write_string24(20,0,0xff000000,0xffff0000,"LOAD_COMPLETE "); + time_count = 0; + }else{ + pic_prm_init(); + } + } + }else{ + if(once_init){ + once_init = 0; + + usb_host_to_device(); + } + } +} diff --git a/FW/Core/my_src/load_gui_lib.h b/FW/Core/my_src/load_gui_lib.h new file mode 100644 index 0000000..fe01487 --- /dev/null +++ b/FW/Core/my_src/load_gui_lib.h @@ -0,0 +1,18 @@ +#define FONT_NOR_FLASH_START_ADDR 0 + +typedef struct Bmp_Parameter_struct +{ + char name_str[32]; + unsigned int start_address; + unsigned int pic_width; + unsigned int pic_height; + unsigned int flash_address; +}Bmp_Parameter_TypeDef; + +extern void pic_prm_init(void); + +extern void mount_usb_file_sys(void); +extern int read_hzk_load_to_flash(void); +extern void read_bmp_load_to_flash(void); + +extern void load_hzk_pic_task(void); diff --git a/FW/Core/my_src/ltdc_drv.c b/FW/Core/my_src/ltdc_drv.c new file mode 100644 index 0000000..4da2664 --- /dev/null +++ b/FW/Core/my_src/ltdc_drv.c @@ -0,0 +1,373 @@ +#include "lcd_base_display.h" +#include "ltdc_drv.h" +////////////////////////////////////////////////////////////////////////////////// +//本程序只供学习使用，未经作者许可，不得用于其它任何用途 +//ALIENTEK 阿波罗STM32H7开发板 +//LTDC驱动代码 +//正点原子@ALIENTEK +//技术论坛:www.openedv.com +//创建日期:2017/8/12 +//版本：V1.0 +//版权所有，盗版必究。 +//Copyright(C) 广州市星翼电子科技有限公司 2014-2024 +//All rights reserved +////////////////////////////////////////////////////////////////////////////////// +LTDC_HandleTypeDef LTDC_Handler; //LTDC句柄 + +//根据不同的颜色格式,定义帧缓存数组 +#if LCD_PIXFORMAT==LCD_PIXFORMAT_ARGB8888||LCD_PIXFORMAT==LCD_PIXFORMAT_RGB888 + //unsigned int ltdc_lcd_framebuf[800][480] __attribute__((at(LCD_FRAME_BUF_ADDR))); //定义最大屏分辨率时,LCD所需的帧缓存数组大小 + static unsigned int * const my_address = (unsigned int *) (LCD_FRAME_BUF_ADDR); + #define ltdc_lcd_framebuf (*my_address) + + static unsigned int * const my_address_2 = (unsigned int *) (LCD_FRAME_BUF_2_ADDR); + #define ltdc_lcd_framebuf_2 (*my_address_2) +#else + unsigned short ltdc_lcd_framebuf[1280][800] __attribute__((at(LCD_FRAME_BUF_ADDR))); //定义最大屏分辨率时,LCD所需的帧缓存数组大小 +#endif + +unsigned int *ltdc_framebuf[2]; //LTDC LCD帧缓存数组指针,必须指向对应大小的内存区域 +_ltdc_dev lcdltdc; //管理LCD LTDC的重要参数 + +//打开LCD开关 +//lcd_switch:1 打开,0，关闭 +void LTDC_Switch(unsigned char sw) +{ + if(sw==1) __HAL_LTDC_ENABLE(<DC_Handler); + else if(sw==0)__HAL_LTDC_DISABLE(<DC_Handler); +} + +//开关指定层 +//layerx:层号,0,第一层; 1,第二层 +//sw:1 打开;0关闭 +void LTDC_Layer_Switch(unsigned char layerx,unsigned char sw) +{ + if(sw==1) __HAL_LTDC_LAYER_ENABLE(<DC_Handler,layerx); + else if(sw==0) __HAL_LTDC_LAYER_DISABLE(<DC_Handler,layerx); + __HAL_LTDC_RELOAD_CONFIG(<DC_Handler); +} + +//选择层 +//layerx:层号;0,第一层;1,第二层; +void LTDC_Select_Layer(unsigned char layerx) +{ + lcdltdc.activelayer=layerx; +} + +//设置LCD显示方向 +//dir:0,竖屏；1,横屏 +void LTDC_Display_Dir(unsigned char dir) +{ + lcdltdc.dir=dir; //显示方向 + if(dir==0) //竖屏 + { + lcdltdc.width=lcdltdc.pheight; + lcdltdc.height=lcdltdc.pwidth; + }else if(dir==1) //横屏 + { + lcdltdc.width=lcdltdc.pwidth; + lcdltdc.height=lcdltdc.pheight; + } +} + +//画点函数 +//x,y:坐标 +//color:颜色值 +void LTDC_Draw_Point(unsigned short x,unsigned short y,unsigned int color) +{ +#if LCD_PIXFORMAT==LCD_PIXFORMAT_ARGB8888||LCD_PIXFORMAT==LCD_PIXFORMAT_RGB888 + if(lcdltdc.dir) //横屏 + { + *(unsigned int*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*y+x))=color; + }else //竖屏 + { + *(unsigned int*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*(lcdltdc.pheight-x-1)+y))=color; + } +#else + if(lcdltdc.dir) //横屏 + { + *(unsigned short*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*y+x))=color; + }else //竖屏 + { + *(unsigned short*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*(lcdltdc.pheight-x-1)+y))=color; + } +#endif +} + +//读点函数 +//返回值:颜色值 +unsigned int LTDC_Read_Point(unsigned short x,unsigned short y) +{ +#if LCD_PIXFORMAT==LCD_PIXFORMAT_ARGB8888||LCD_PIXFORMAT==LCD_PIXFORMAT_RGB888 + if(lcdltdc.dir) //横屏 + { + return *(unsigned int*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*y+x)); + }else //竖屏 + { + return *(unsigned int*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*(lcdltdc.pheight-x-1)+y)); + } +#else + if(lcdltdc.dir) //横屏 + { + return *(unsigned short*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*y+x)); + }else //竖屏 + { + return *(unsigned short*)((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*(lcdltdc.pheight-x-1)+y)); + } +#endif +} + +//LTDC填充矩形,DMA2D填充 +//(sx,sy),(ex,ey):填充矩形对角坐标,区域大小为:(ex-sx+1)*(ey-sy+1) +//注意:sx,ex,不能大于lcddev.width-1;sy,ey,不能大于lcddev.height-1!!! +//color:要填充的颜色 +void LTDC_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned int color) +{ + unsigned int psx,psy,pex,pey; //以LCD面板为基准的坐标系,不随横竖屏变化而变化 + unsigned int timeout=0; + unsigned short offline; + unsigned int addr; + //坐标系转换 + if(lcdltdc.dir) //横屏 + { + psx=sx;psy=sy; + pex=ex;pey=ey; + }else //竖屏 + { + psx=sy;psy=lcdltdc.pheight-ex-1; + pex=ey;pey=lcdltdc.pheight-sx-1; + } + offline=lcdltdc.pwidth-(pex-psx+1); + addr=((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*psy+psx)); + RCC->AHB1ENR|=1<<23; //使能DM2D时钟 + DMA2D->CR=3<<16; //寄存器到存储器模式 + DMA2D->OPFCCR=LCD_PIXFORMAT; //设置颜色格式 + DMA2D->OOR=offline; //设置行偏移 + DMA2D->CR&=~(1<<0); //先停止DMA2D + DMA2D->OMAR=addr; //输出存储器地址 + DMA2D->NLR=(pey-psy+1)|((pex-psx+1)<<16); //设定行数寄存器 + DMA2D->OCOLR=color; //设定输出颜色寄存器 + DMA2D->CR|=1<<0; //启动DMA2D + while((DMA2D->ISR&(1<<1))==0) //等待传输完成 + { + timeout++; + if(timeout>0X1FFFFF)break; //超时退出 + } + DMA2D->IFCR|=1<<1; //清除传输完成标志 +} +//在指定区域内填充单个颜色 +//(sx,sy),(ex,ey):填充矩形对角坐标,区域大小为:(ex-sx+1)*(ey-sy+1) +//color:要填充的颜色 +//void LTDC_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned int color) +//{ +// unsigned int psx,psy,pex,pey; //以LCD面板为基准的坐标系,不随横竖屏变化而变化 +// unsigned int timeout=0; +// unsigned short offline; +// unsigned int addr; +// if(ex>=lcdltdc.width)ex=lcdltdc.width-1; +// if(ey>=lcdltdc.height)ey=lcdltdc.height-1; +// //坐标系转换 +// if(lcdltdc.dir) //横屏 +// { +// psx=sx;psy=sy; +// pex=ex;pey=ey; +// }else //竖屏 +// { +// psx=sy;psy=lcdltdc.pheight-ex-1; +// pex=ey;pey=lcdltdc.pheight-sx-1; +// } +// offline=lcdltdc.pwidth-(pex-psx+1); +// addr=((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*psy+psx)); +// if(LCD_PIXFORMAT==LCD_PIXEL_FORMAT_RGB565) //如果是RGB565格式的话需要进行颜色转换，将16bit转换为32bit的 +// { +// color=((color&0X0000F800)<<8)|((color&0X000007E0)<<5)|((color&0X0000001F)<<3); +// } +// //配置DMA2D的模式 +// DMA2D_Handler.Instance=DMA2D; +// DMA2D_Handler.Init.Mode=DMA2D_R2M; //内存到存储器模式 +// DMA2D_Handler.Init.ColorMode=LCD_PIXFORMAT; //设置颜色格式 +// DMA2D_Handler.Init.OutputOffset=offline; //输出偏移 +// HAL_DMA2D_Init(&DMA2D_Handler); //初始化DMA2D +// HAL_DMA2D_ConfigLayer(&DMA2D_Handler,lcdltdc.activelayer); //层配置 +// HAL_DMA2D_Start(&DMA2D_Handler,color,(unsigned int)addr,pex-psx+1,pey-psy+1);//开启传输 +// HAL_DMA2D_PollForTransfer(&DMA2D_Handler,1000);//传输数据 +// while((__HAL_DMA2D_GET_FLAG(&DMA2D_Handler,DMA2D_FLAG_TC)==0)&&(timeout<0X5000))//等待DMA2D完成 +// { +// timeout++; +// } +// __HAL_DMA2D_CLEAR_FLAG(&DMA2D_Handler,DMA2D_FLAG_TC); //清除传输完成标志 +//} + +//在指定区域内填充指定颜色块,DMA2D填充 +//此函数仅支持unsigned short,RGB565格式的颜色数组填充. +//(sx,sy),(ex,ey):填充矩形对角坐标,区域大小为:(ex-sx+1)*(ey-sy+1) +//注意:sx,ex,不能大于lcddev.width-1;sy,ey,不能大于lcddev.height-1!!! +//color:要填充的颜色数组首地址 +void LTDC_Color_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned short *color) +{ + unsigned int psx,psy,pex,pey; //以LCD面板为基准的坐标系,不随横竖屏变化而变化 + unsigned int timeout=0; + unsigned short offline; + unsigned int addr; + //坐标系转换 + if(lcdltdc.dir) //横屏 + { + psx=sx;psy=sy; + pex=ex;pey=ey; + }else //竖屏 + { + psx=sy;psy=lcdltdc.pheight-ex-1; + pex=ey;pey=lcdltdc.pheight-sx-1; + } + offline=lcdltdc.pwidth-(pex-psx+1); + addr=((unsigned int)ltdc_framebuf[lcdltdc.activelayer]+lcdltdc.pixsize*(lcdltdc.pwidth*psy+psx)); + RCC->AHB1ENR|=1<<23; //使能DM2D时钟 + DMA2D->CR=0<<16; //存储器到存储器模式 + DMA2D->FGPFCCR=LCD_PIXFORMAT; //设置颜色格式 + DMA2D->FGOR=0; //前景层行偏移为0 + DMA2D->OOR=offline; //设置行偏移 + DMA2D->CR&=~(1<<0); //先停止DMA2D + DMA2D->FGMAR=(unsigned int)color; //源地址 + DMA2D->OMAR=addr; //输出存储器地址 + DMA2D->NLR=(pey-psy+1)|((pex-psx+1)<<16); //设定行数寄存器 + DMA2D->CR|=1<<0; //启动DMA2D + while((DMA2D->ISR&(1<<1))==0) //等待传输完成 + { + timeout++; + if(timeout>0X1FFFFF)break; //超时退出 + } + DMA2D->IFCR|=1<<1; //清除传输完成标志 +} + +//LCD清屏 +//color:颜色值 +void LTDC_Clear(unsigned int color) +{ + LTDC_Fill(0,0,lcdltdc.width-1,lcdltdc.height-1,color); +} + +//LTDC时钟(Fdclk)设置函数 +//PLL3_VCO Input=HSE_VALUE/PLL3M +//PLL3_VCO Output=PLL3_VCO Input * PLL3N +//PLLLCDCLK = PLL3_VCO Output/PLL3R +//假如HSE_VALUE=25MHz，PLL3M=5，PLL3N=160,PLL3R=88 +//LTDCLK=PLLLCDCLK=25/5*160/88=9MHz +//返回值:0,成功;1,失败。 +unsigned char LTDC_Clk_Set(unsigned int pll3m,unsigned int pll3n,unsigned int pll3r) +{ + RCC_PeriphCLKInitTypeDef PeriphClkIniture; + PeriphClkIniture.PeriphClockSelection = RCC_PERIPHCLK_LTDC; + PeriphClkIniture.PLL3.PLL3M = pll3m; + PeriphClkIniture.PLL3.PLL3N = pll3n; + PeriphClkIniture.PLL3.PLL3P = 2; + PeriphClkIniture.PLL3.PLL3Q = 2; + PeriphClkIniture.PLL3.PLL3R = pll3r; + if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkIniture)==HAL_OK) //配置像素时钟，这里配置为时钟为18.75MHZ + { + return 0; //成功 + } + else return 1; //失败 +} + +//LTDC,层颜窗口设置,窗口以LCD面板坐标系为基准 +//注意:此函数必须在LTDC_Layer_Parameter_Config之后再设置. +//layerx:层值,0/1. +//sx,sy:起始坐标 +//width,height:宽度和高度 +void LTDC_Layer_Window_Config(unsigned char layerx,unsigned short sx,unsigned short sy,unsigned short width,unsigned short height) +{ + HAL_LTDC_SetWindowPosition(<DC_Handler,sx,sy,layerx); //设置窗口的位置 + HAL_LTDC_SetWindowSize(<DC_Handler,width,height,layerx);//设置窗口大小 +} + +//LTDC,基本参数设置. +//注意:此函数,必须在LTDC_Layer_Window_Config之前设置. +//layerx:层值,0/1. +//bufaddr:层颜色帧缓存起始地址 +//pixformat:颜色格式.0,ARGB8888;1,RGB888;2,RGB565;3,ARGB1555;4,ARGB4444;5,L8;6;AL44;7;AL88 +//alpha:层颜色Alpha值,0,全透明;255,不透明 +//alpha0:默认颜色Alpha值,0,全透明;255,不透明 +//bfac1:混合系数1,4(100),恒定的Alpha;6(101),像素Alpha*恒定Alpha +//bfac2:混合系数2,5(101),恒定的Alpha;7(111),像素Alpha*恒定Alpha +//bkcolor:层默认颜色,32位,低24位有效,RGB888格式 +//返回值:无 +void LTDC_Layer_Parameter_Config(unsigned char layerx,unsigned int bufaddr,unsigned char pixformat,unsigned char alpha,unsigned char alpha0,unsigned char bfac1,unsigned char bfac2,unsigned int bkcolor) +{ + LTDC_LayerCfgTypeDef pLayerCfg; + + pLayerCfg.WindowX0=0; //窗口起始X坐标 + pLayerCfg.WindowY0=0; //窗口起始Y坐标 + pLayerCfg.WindowX1=lcdltdc.pwidth; //窗口终止X坐标 + pLayerCfg.WindowY1=lcdltdc.pheight; //窗口终止Y坐标 + pLayerCfg.PixelFormat=pixformat; //像素格式 + pLayerCfg.Alpha=alpha; //Alpha值设置，0~255,255为完全不透明 + pLayerCfg.Alpha0=alpha0; //默认Alpha值 + pLayerCfg.BlendingFactor1=(unsigned int)bfac1<<8; //设置层混合系数 + pLayerCfg.BlendingFactor2=(unsigned int)bfac2<<8; //设置层混合系数 + pLayerCfg.FBStartAdress=bufaddr; //设置层颜色帧缓存起始地址 + pLayerCfg.ImageWidth=lcdltdc.pwidth; //设置颜色帧缓冲区的宽度 + pLayerCfg.ImageHeight=lcdltdc.pheight; //设置颜色帧缓冲区的高度 + pLayerCfg.Backcolor.Red=(unsigned char)(bkcolor&0X00FF0000)>>16; //背景颜色红色部分 + pLayerCfg.Backcolor.Green=(unsigned char)(bkcolor&0X0000FF00)>>8; //背景颜色绿色部分 + pLayerCfg.Backcolor.Blue=(unsigned char)bkcolor&0X000000FF; //背景颜色蓝色部分 + HAL_LTDC_ConfigLayer(<DC_Handler,&pLayerCfg,layerx); //设置所选中的层 +} + +//LCD初始化函数 +void LTDC_Init(void) +{ + unsigned short lcdid=0; + + lcdltdc.pwidth=800; //面板宽度,单位:像素 + lcdltdc.pheight=480; //面板高度,单位:像素 + lcdltdc.hsw=1; //水平同步宽度 + lcdltdc.hbp=46; //水平后廊 + lcdltdc.hfp=210; //水平前廊 + lcdltdc.vsw=1; //垂直同步宽度 + lcdltdc.vbp=23; //垂直后廊 + lcdltdc.vfp=22; //垂直前廊 + //LTDC_Clk_Set(5,160,47);//设置像素时钟 17Mhz + + lcddev.width=lcdltdc.pwidth; + lcddev.height=lcdltdc.pheight; + +#if LCD_PIXFORMAT==LCD_PIXFORMAT_ARGB8888||LCD_PIXFORMAT==LCD_PIXFORMAT_RGB888 + ltdc_framebuf[0]=(unsigned int*)<dc_lcd_framebuf; + ltdc_framebuf[1]=(unsigned int*)<dc_lcd_framebuf_2; + lcdltdc.pixsize=4; //每个像素占4个字节 +#else + lcdltdc.pixsize=2; //每个像素占2个字节 + ltdc_framebuf[0]=(unsigned int*)<dc_lcd_framebuf; +#endif + /* + //LTDC配置 + LTDC_Handler.Instance=LTDC; + LTDC_Handler.Init.HSPolarity=LTDC_HSPOLARITY_AL; //水平同步极性 + LTDC_Handler.Init.VSPolarity=LTDC_VSPOLARITY_AL; //垂直同步极性 + LTDC_Handler.Init.DEPolarity=LTDC_DEPOLARITY_AL; //数据使能极性 + LTDC_Handler.Init.PCPolarity=LTDC_PCPOLARITY_IPC; //像素时钟极性 + //if(lcdid==0X1018)LTDC_Handler.Init.PCPolarity=LTDC_PCPOLARITY_IIPC; //像素时钟极性相反 + LTDC_Handler.Init.HorizontalSync=lcdltdc.hsw-1; //水平同步宽度 + LTDC_Handler.Init.VerticalSync=lcdltdc.vsw-1; //垂直同步宽度 + LTDC_Handler.Init.AccumulatedHBP=lcdltdc.hsw+lcdltdc.hbp-1; //水平同步后沿宽度 + LTDC_Handler.Init.AccumulatedVBP=lcdltdc.vsw+lcdltdc.vbp-1; //垂直同步后沿高度 + LTDC_Handler.Init.AccumulatedActiveW=lcdltdc.hsw+lcdltdc.hbp+lcdltdc.pwidth-1;//有效宽度 + LTDC_Handler.Init.AccumulatedActiveH=lcdltdc.vsw+lcdltdc.vbp+lcdltdc.pheight-1;//有效高度 + LTDC_Handler.Init.TotalWidth=lcdltdc.hsw+lcdltdc.hbp+lcdltdc.pwidth+lcdltdc.hfp-1; //总宽度 + LTDC_Handler.Init.TotalHeigh=lcdltdc.vsw+lcdltdc.vbp+lcdltdc.pheight+lcdltdc.vfp-1; //总高度 + LTDC_Handler.Init.Backcolor.Red=0; //屏幕背景层红色部分 + LTDC_Handler.Init.Backcolor.Green=0; //屏幕背景层绿色部分 + LTDC_Handler.Init.Backcolor.Blue=0; //屏幕背景色蓝色部分 + HAL_LTDC_Init(<DC_Handler); + + //层配置 + //LTDC_Layer_Parameter_Config(0,(unsigned int)ltdc_framebuf[0],LCD_PIXFORMAT,255,0,6,7,0X000000);//层参数配置 + //LTDC_Layer_Window_Config(0,0,0,lcdltdc.pwidth,lcdltdc.pheight); //层窗口配置,以LCD面板坐标系为基准,不要随便修改! + */ + + LTDC_Display_Dir(1); //默认横屏 + LTDC_Select_Layer(1); //选择第2层 + LTDC_Clear(0); //清屏 + LTDC_Select_Layer(0); //选择第1层 + LTDC_Clear(0XFF000000); //清屏 +} diff --git a/FW/Core/my_src/ltdc_drv.h b/FW/Core/my_src/ltdc_drv.h new file mode 100644 index 0000000..dcda652 --- /dev/null +++ b/FW/Core/my_src/ltdc_drv.h @@ -0,0 +1,76 @@ +#ifndef _LCD_H +#define _LCD_H +//#include "sys.h" +#include "main.h" +////////////////////////////////////////////////////////////////////////////////// +//本程序只供学习使用，未经作者许可，不得用于其它任何用途 +//ALIENTEK STM32H7开发板 +//LCD驱动代码 +//正点原子@ALIENTEK +//技术论坛:www.openedv.com +//创建日期:2017/8/12 +//版本：V1.0 +//版权所有，盗版必究。 +//Copyright(C) 广州市星翼电子科技有限公司 2014-2024 +//All rights reserved +////////////////////////////////////////////////////////////////////////////////// +#define LCD_LED(n) (n?HAL_GPIO_WritePin(GPIOB,GPIO_PIN_5,GPIO_PIN_SET):HAL_GPIO_WritePin(GPIOB,GPIO_PIN_5,GPIO_PIN_RESET)) //LCD背光PD13 //LCD背光PD13 + +//LCD LTDC重要参数集 +typedef struct +{ + unsigned int pwidth; //LCD面板的宽度,固定参数,不随显示方向改变,如果为0,说明没有任何RGB屏接入 + unsigned int pheight; //LCD面板的高度,固定参数,不随显示方向改变 + unsigned short hsw; //水平同步宽度 + unsigned short vsw; //垂直同步宽度 + unsigned short hbp; //水平后廊 + unsigned short vbp; //垂直后廊 + unsigned short hfp; //水平前廊 + unsigned short vfp; //垂直前廊 + unsigned char activelayer; //当前层编号:0/1 + unsigned char dir; //0,竖屏;1,横屏; + unsigned short width; //LCD宽度 + unsigned short height; //LCD高度 + unsigned int pixsize; //每个像素所占字节数 +}_ltdc_dev; + +extern _ltdc_dev lcdltdc; //管理LCD LTDC参数 +extern LTDC_HandleTypeDef LTDC_Handler; //LTDC句柄 +extern unsigned int *ltdc_framebuf[2]; //LTDC LCD帧缓存数组指针,必须指向对应大小的内存区域 + +#define LCD_PIXEL_FORMAT_ARGB8888 0X00 +#define LCD_PIXEL_FORMAT_RGB888 0X01 +#define LCD_PIXEL_FORMAT_RGB565 0X02 +#define LCD_PIXEL_FORMAT_ARGB1555 0X03 +#define LCD_PIXEL_FORMAT_ARGB4444 0X04 +#define LCD_PIXEL_FORMAT_L8 0X05 +#define LCD_PIXEL_FORMAT_AL44 0X06 +#define LCD_PIXEL_FORMAT_AL88 0X07 + +/////////////////////////////////////////////////////////////////////// +//用户修改配置部分: + +//定义颜色像素格式,一般用RGB565 +#define LCD_PIXFORMAT LCD_PIXEL_FORMAT_ARGB8888 +//定义默认背景层颜色 +#define LTDC_BACKLAYERCOLOR 0X00000000 +//LCD帧缓冲区首地址,这里定义在SDRAM里面. +#define LCD_FRAME_BUF_ADDR 0XC0000000 +#define LCD_FRAME_BUF_2_ADDR 0XC0177000 + +void LTDC_Switch(unsigned char sw); //LTDC开关 +void LTDC_Layer_Switch(unsigned char layerx,unsigned char sw); //层开关 +void LTDC_Select_Layer(unsigned char layerx); //层选择 +void LTDC_Display_Dir(unsigned char dir); //显示方向控制 +void LTDC_Draw_Point(unsigned short x,unsigned short y,unsigned int color);//画点函数 +unsigned int LTDC_Read_Point(unsigned short x,unsigned short y); //读点函数 +void LTDC_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned int color); //矩形单色填充函数 +void LTDC_Color_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned short *color); //矩形彩色填充函数 +void LTDC_Clear(unsigned int color); //清屏函数 +unsigned char LTDC_Clk_Set(unsigned int pll3m,unsigned int pll3n,unsigned int pll3r);//LTDC时钟配置 +//unsigned char LTDC_Clk_Set(unsigned int pllsain,unsigned int pllsair,unsigned int pllsaidivr);//LTDC时钟配置 +void LTDC_Layer_Window_Config(unsigned char layerx,unsigned short sx,unsigned short sy,unsigned short width,unsigned short height);//LTDC层窗口设置 +void LTDC_Layer_Parameter_Config(unsigned char layerx,unsigned int bufaddr,unsigned char pixformat,unsigned char alpha,unsigned char alpha0,unsigned char bfac1,unsigned char bfac2,unsigned int bkcolor);//LTDC基本参数设置 +unsigned short LTDC_PanelID_Read(void); //LCD ID读取函数 +void LTDC_Init(void); //LTDC初始化函数 +#endif diff --git a/FW/Core/my_src/relay_task.c b/FW/Core/my_src/relay_task.c new file mode 100644 index 0000000..7b9114a --- /dev/null +++ b/FW/Core/my_src/relay_task.c @@ -0,0 +1,66 @@ +#include "main.h" +#include "relay_task.h" + +#define RELAY1_ON() LL_TIM_OC_SetCompareCH1(TIM2,255) +#define RELAY1_OFF() LL_TIM_OC_SetCompareCH1(TIM2,0) +#define RELAY1_HOLD() LL_TIM_OC_SetCompareCH1(TIM2,200) + +#define RELAY2_ON() LL_TIM_OC_SetCompareCH1(TIM12,255) +#define RELAY2_OFF() LL_TIM_OC_SetCompareCH1(TIM12,0) +#define RELAY2_HOLD() LL_TIM_OC_SetCompareCH1(TIM12,200) + +typedef struct +{ + unsigned char fault; + unsigned char alarm; + unsigned char dump0; + unsigned char dump1; +}TSys_Relay_State_Struct; + +TSys_Relay_State_Struct relay_state = {0,0}; + +void set_Relay_alarm_state(unsigned char aSta) +{ + relay_state.alarm = aSta; +} + +void set_Relay_fault_state(unsigned char aSta) +{ + relay_state.fault = aSta; +} + +void alarm_relay_output_handle(void) +{ + static unsigned int relay_tick = 0; + + if(relay_state.alarm){ + if(relay_tick < 200)relay_tick++; + }else{ + relay_tick = 0; + } + + if(0 == relay_tick)RELAY1_OFF(); + else if(relay_tick < 100)RELAY1_ON(); + else RELAY1_HOLD(); +} + +void fault_relay_output_handle(void) +{ + static unsigned int relay_tick = 0; + + if(relay_state.fault){ + if(relay_tick < 200)relay_tick++; + }else{ + relay_tick = 0; + } + + if(0 == relay_tick)RELAY2_OFF(); + else if(relay_tick < 100)RELAY2_ON(); + else RELAY2_HOLD(); +} + +void relay_output_handle(void)//100ms +{ + alarm_relay_output_handle(); + fault_relay_output_handle(); +} diff --git a/FW/Core/my_src/relay_task.h b/FW/Core/my_src/relay_task.h new file mode 100644 index 0000000..1238122 --- /dev/null +++ b/FW/Core/my_src/relay_task.h @@ -0,0 +1,8 @@ +#ifndef RELAY_TASK_H_ +#define RELAY_TASK_H_ + +extern void relay_output_handle(void); +extern void set_Relay_alarm_state(unsigned char aSta); +extern void set_Relay_fault_state(unsigned char aSta); + +#endif diff --git a/FW/Core/my_src/sdram_addr_map.h b/FW/Core/my_src/sdram_addr_map.h new file mode 100644 index 0000000..2d98df5 --- /dev/null +++ b/FW/Core/my_src/sdram_addr_map.h @@ -0,0 +1,24 @@ +#ifndef __SDRAM_ADDR_MAP_H +#define __SDRAM_ADDR_MAP_H + +//#define SDRAM_BUF_RECORD_ADDRESS ((uint32_t)0xC2000000) +//#define SDRAM_BUF_RECORD_SIZE ((uint32_t)0x00020000)//128kbyte + +#define SDRAM_PIC_16X16_ADDR_START ((uint32_t)0xC3E00000) //num128(16*16) 24bit +#define SDRAM_PIC_16X16_MEM_UNIT ((uint32_t)0x400) + +#define SDRAM_PIC_24X24_ADDR_START ((uint32_t)0xC3E20000)//num128(24*24) 24bit +#define SDRAM_PIC_24X24_MEM_UNIT ((uint32_t)0x900) + +#define SDRAM_PIC_32X32_ADDR_START ((uint32_t)0xC3E60000)//num32(32*32) 24bit +#define SDRAM_PIC_32X32_MEM_UNIT ((uint32_t)0x1000) + +#define SDRAM_PIC_LOGO24_ADDR_START ((uint32_t)0xC3E80000)//num1(24*90) 24bit +#define SDRAM_PIC_LOGO24_MEM_UNIT ((uint32_t)0x2800) + +#define SDRAM_PIC_LOGO32_ADDR_START ((uint32_t)0xC3E90000)//num1(122*32) 24bit +#define SDRAM_PIC_LOGO32_MEM_UNIT ((uint32_t)0x4000) + +#define SDRAM_BUF_CACHE_ADDRESS ((uint32_t)0xC3F00000) + +#endif diff --git a/FW/Core/my_src/task.c b/FW/Core/my_src/task.c new file mode 100644 index 0000000..df4a768 --- /dev/null +++ b/FW/Core/my_src/task.c @@ -0,0 +1,179 @@ +#include "main.h" +#include "rtc.h" +#include "HW_config.h" +#include "w25qxx.h" +#include "load_gui_lib.h" +#include "fdcan_task.h" +#include "uart_printer_drv.h" +#include "uart_fecbus_drv.h" +#include "uart_fec_std_drv.h" +#include "uart_lp_test_drv.h" +#include "uart_task.h" +#include "relay_task.h" +#include "CnCpp.h" + +unsigned int sys_tick_1ms_rdy = 0; +unsigned int sys_tick_10ms_rdy = 0; +unsigned int sys_tick_100ms_rdy = 0; +unsigned int sys_tick_200ms_rdy = 0; +unsigned int sys_tick_1s_rdy = 0; +unsigned int sys_tick_600S_rdy = 0; + +volatile unsigned int sys_oldtime = 0; +volatile unsigned int sys_free_run_ms = 0; +volatile unsigned int sys_test_sp_time = 0; + +unsigned int UserRequestReset = 0; +unsigned int SysLoopTick = 0; + +unsigned char datatemp[128]; +unsigned char tx_test_data[16] = {0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55,\ + 0x55,0x55,0x55,0x55,0x55,0x55,0x55,0x55}; + +void my_sys_tick(void) +{ + static unsigned int sys_tick_10ms_tick = 0; + static unsigned int sys_tick_100ms_tick = 0; + static unsigned int sys_tick_200ms_tick = 0; + static unsigned int sys_tick_1s_tick = 0; + static unsigned int sys_tick_600S_tick = 0; + + static unsigned int norflash_err_tick[2] = {0,0}; + + sys_tick_1ms_rdy = 1; + sys_free_run_ms++; + + fecbus_rx_timeout_tick(); + fec_std_rx_timeout_tick(); + test_rx_timeout_tick(); + + Cpp_1Ms_Task(); + + uart_tx_complete_delay(); + can_tx_complete_delay(); + + if(norflash_get_busy_flag[0]){ + norflash_err_tick[0]++; + if(norflash_err_tick[0] > 201000){ + norflash_err_tick[0] = 0; + norflash_err_flag[0] = 1; + } + }else{ + norflash_err_tick[0] = 0; + norflash_err_flag[0] = 0; + } + + if(norflash_get_busy_flag[1]){ + norflash_err_tick[1]++; + if(norflash_err_tick[1] > 201000){ + norflash_err_tick[1] = 0; + norflash_err_flag[1] = 1; + } + }else{ + norflash_err_tick[1] = 0; + norflash_err_flag[1] = 0; + } + + sys_tick_10ms_tick++; + if(sys_tick_10ms_tick > 9){ + sys_tick_10ms_tick = 0; + sys_tick_10ms_rdy = 1; + } + + sys_tick_100ms_tick++; + if(sys_tick_100ms_tick > 99){ + sys_tick_100ms_tick = 0; + sys_tick_100ms_rdy = 1; + + if(UserRequestReset != 0x12345678){ + SysLoopTick++; + if(SysLoopTick < 100) + LL_IWDG_ReloadCounter(IWDG1); + } + + can_send_time_handle(); + } + + sys_tick_200ms_tick++; + if(sys_tick_200ms_tick > 199){ + sys_tick_200ms_tick = 0; + sys_tick_200ms_rdy = 1; + } + + sys_tick_1s_tick++; + if(sys_tick_1s_tick > 999){ + sys_tick_1s_tick = 0; + sys_tick_1s_rdy = 1; + + sys_tick_600S_tick++; + if(sys_tick_600S_tick > 599){ + sys_tick_600S_tick = 0; + sys_tick_600S_rdy = 1; + } + } +} + +void sys_error_led_task(void) +{ + if(!GetSystemErrorState()){ + //GPIOE->ODR ^=0x04;; + } +} + +void DoUpdataRtc() +{ + RTC_TimeShow(); +} + +void operation_finction(void) +{ + static unsigned int color_tick = 0; + + static unsigned int addr = 0; + unsigned int i = 0; + + CppFreRun(); + + if(sys_tick_1ms_rdy){ + sys_tick_1ms_rdy = 0; + + uart_interval_send(); + } + + if(sys_tick_10ms_rdy){ + sys_tick_10ms_rdy = 0; + sys_error_led_task(); + Cpp_10Ms_Task(); + } + + if(sys_tick_100ms_rdy){ + sys_tick_100ms_rdy = 0; + + GPIOC->ODR ^=0x0020; + + Cpp_100Ms_Task(); + load_hzk_pic_task(); + + relay_output_handle(); + } + + if(sys_tick_1s_rdy){ + sys_tick_1s_rdy = 0; + Sys_1s_Load_Rdy(); + + printer_task(); + DoUpdataRtc(); + + sys_oldtime = sys_free_run_ms; + CppIn(); + sys_test_sp_time = sys_free_run_ms - sys_oldtime; + } + + uart_task(); + can_task(); + + if(sys_tick_600S_rdy){ + sys_tick_600S_rdy = 0; + } +} + diff --git a/FW/Core/my_src/uart_can_drv.c b/FW/Core/my_src/uart_can_drv.c new file mode 100644 index 0000000..e69de29 diff --git a/FW/Core/my_src/uart_can_drv.h b/FW/Core/my_src/uart_can_drv.h new file mode 100644 index 0000000..e69de29 diff --git a/FW/Core/my_src/uart_fec_std_drv.c b/FW/Core/my_src/uart_fec_std_drv.c new file mode 100644 index 0000000..a181bdf --- /dev/null +++ b/FW/Core/my_src/uart_fec_std_drv.c @@ -0,0 +1,146 @@ +#include "HW_Config.h" +#include "uart_fec_std_drv.h" +#include "CnCpp.h" + +#define FEC_STD_UART 4 + +#define FEC_STD_RX_TIMEOUT 25//12:19200 25:9600 //9600 19byte:20ms + +T_FEC_STD_RX_Prm fec_std_rx_prm; + +unsigned char fec_std_uart_tx[32]; + +static unsigned int set_crc_error_flag = 0; + +unsigned int fec_std_tx_is_busy(void)//1:is busy 0:no busy +{ + if(!get_uart_tx_complete_delay_flag(FEC_STD_UART))return 1; + + return 0; +} + +void set_fec_std_tx_data(unsigned char * pdata)//fec格式，加上后面crc 2byte 与end +{ + unsigned int i = 0; + unsigned int len = 0; + + len = pdata[7]; + if(len > 8)return; + len += 8; + for(i=0;i 30){//9600 19byte:20ms + fec_std_rx_prm.state = 0; + fec_std_rx_prm.starttime_flag = 0; + fec_std_rx_prm.timecount = 0; + } + } +} + +void fec_std_rx_irq(void) +{ + unsigned short cc; + + if(LL_USART_IsActiveFlag_RXNE(UART4)) + { + cc = LL_USART_ReceiveData8(UART4); + + switch(fec_std_rx_prm.state){ + case 0 : + if(FEC_STD_UART_HEAD == cc){ + uart_info_8bit[FEC_STD_UART].rx_index = 0; + uart_info_8bit[FEC_STD_UART].rx_buf[uart_info_8bit[FEC_STD_UART].rx_index] = cc; + uart_info_8bit[FEC_STD_UART].rx_len = 25;//>19 + fec_std_rx_prm.starttime_flag = 1; + fec_std_rx_prm.state++; + set_crc_error_flag = 0; + } + break; + + case 1: + uart_info_8bit[FEC_STD_UART].rx_index++; + uart_info_8bit[FEC_STD_UART].rx_buf[uart_info_8bit[FEC_STD_UART].rx_index] = cc; + if(7 == uart_info_8bit[FEC_STD_UART].rx_index){ + uart_info_8bit[FEC_STD_UART].rx_len = 11 + cc; + if(uart_info_8bit[FEC_STD_UART].rx_len > 19){ + fec_std_rx_prm.state = 0; + fec_std_rx_prm.starttime_flag = 0; + fec_std_rx_prm.timecount = 0; + }else{ + fec_std_rx_prm.state++; + } + }else + if(uart_info_8bit[FEC_STD_UART].rx_index > 7){ + fec_std_rx_prm.state = 0; + fec_std_rx_prm.starttime_flag = 0; + fec_std_rx_prm.timecount = 0; + } + break; + + case 2: + uart_info_8bit[FEC_STD_UART].rx_index++; + uart_info_8bit[FEC_STD_UART].rx_buf[uart_info_8bit[FEC_STD_UART].rx_index] = cc; + if(((uart_info_8bit[FEC_STD_UART].rx_len - 1) == uart_info_8bit[FEC_STD_UART].rx_index)&&(fec_std_rx_prm.timecount < FEC_STD_RX_TIMEOUT)&&(cc == FEC_STD_UART_END)){ + uart_info_8bit[FEC_STD_UART].rx_complete = 1; + fec_std_rx_prm.state = 0; + fec_std_rx_prm.starttime_flag = 0; + fec_std_rx_prm.timecount = 0; + }else + if(uart_info_8bit[FEC_STD_UART].rx_index > 19){ + fec_std_rx_prm.state = 0; + fec_std_rx_prm.starttime_flag = 0; + fec_std_rx_prm.timecount = 0; + } + break; + + default: + fec_std_rx_prm.state = 0; + fec_std_rx_prm.starttime_flag = 0; + fec_std_rx_prm.timecount = 0; + break; + } + } +} + +void uart4_rx_task(void) +{ + if(uart_info_8bit[FEC_STD_UART].rx_complete){ + uart_info_8bit[FEC_STD_UART].rx_complete = 0; + if(!check_crc(uart_info_8bit[FEC_STD_UART].rx_buf,(uart_info_8bit[FEC_STD_UART].rx_len-1))){ + LoadStdViaFECBus(uart_info_8bit[FEC_STD_UART].rx_buf); + }else{ + if((FEC_STD_UART_HEAD == uart_info_8bit[FEC_STD_UART].rx_buf[0])&&\ + (FEC_STD_UART_END == uart_info_8bit[FEC_STD_UART].rx_buf[uart_info_8bit[FEC_STD_UART].rx_len-1])&&\ + (0 == uart_info_8bit[FEC_STD_UART].rx_buf[1])){ + + set_crc_error_flag = 1; + } + } + + if((set_crc_error_flag)&&(0 == uart_info_8bit[FEC_STD_UART].rx_buf[6])){ + set_crc_error_flag = 0; + SetRpyFECStdCRCError(); + } + } +} + +void uart_fec_std_task(void) +{ + uart4_rx_task(); +} + diff --git a/FW/Core/my_src/uart_fec_std_drv.h b/FW/Core/my_src/uart_fec_std_drv.h new file mode 100644 index 0000000..6a0c5c6 --- /dev/null +++ b/FW/Core/my_src/uart_fec_std_drv.h @@ -0,0 +1,23 @@ +#ifndef UART_FEC_STD_DRV_H_ +#define UART_FEC_STD_DRV_H_ + +#define FEC_STD_UART_HEAD 0x7E +#define FEC_STD_UART_END 0x7E + +typedef struct{ + unsigned int state; + unsigned int starttime_flag; + unsigned int timecount; +}T_FEC_STD_RX_Prm; + +extern T_FEC_STD_RX_Prm fec_std_rx_prm; + +extern unsigned int fec_std_tx_is_busy(void); +extern void set_fec_std_tx_data(unsigned char * pdata); + +extern void fec_std_rx_timeout_tick(void); +extern void fec_std_rx_irq(void); +extern void uart_fec_std_task(void); +extern void fec_std_rx_timeout_tick(void); + +#endif diff --git a/FW/Core/my_src/uart_fecbus_drv.c b/FW/Core/my_src/uart_fecbus_drv.c new file mode 100644 index 0000000..ef68b82 --- /dev/null +++ b/FW/Core/my_src/uart_fecbus_drv.c @@ -0,0 +1,147 @@ +#include "HW_Config.h" +#include "uart_fecbus_drv.h" +#include "CnCpp.h" + +#define FECBUS_UART 2 + +#define FECBUS_RX_TIMEOUT 25//12:19200 25:9600 //9600 19byte:20ms + +#define FECBUS_UART_HEAD 0x7E +#define FECBUS_UART_END 0x7E + +T_FECBus_RX_Prm fecbus_rx_prm; + +unsigned char fecbus_uart_tx[32]; + +unsigned int fecbus_tx_is_busy(void)//1:is busy 0:no busy +{ + if(!get_uart_tx_complete_delay_flag(FECBUS_UART))return 1; + + return 0; +} + +void set_fecbus_tx_data(unsigned char * pdata)//fec??ê?￡??óé?oó??crc 2byte ó?end +{ + unsigned int i = 0; + unsigned int len = 0; + + len = pdata[7]; + if(len > 8)return; + len += 8; + for(i=0;i 30){//9600 19byte:20ms + fecbus_rx_prm.state = 0; + fecbus_rx_prm.starttime_flag = 0; + fecbus_rx_prm.timecount = 0; + } + } +} + +void fecbus_rx_irq(void) +{ + unsigned short cc; + + if(LL_USART_IsActiveFlag_RXNE(USART2)) + { + cc = LL_USART_ReceiveData8(USART2); + + switch(fecbus_rx_prm.state){ + case 0 : + if(0x7E == cc){ + uart_info_8bit[FECBUS_UART].rx_index = 0; + uart_info_8bit[FECBUS_UART].rx_buf[uart_info_8bit[FECBUS_UART].rx_index] = cc; + uart_info_8bit[FECBUS_UART].rx_len = 25;//>19 + fecbus_rx_prm.starttime_flag = 1; + fecbus_rx_prm.state++; + } + break; + + case 1: + uart_info_8bit[FECBUS_UART].rx_index++; + uart_info_8bit[FECBUS_UART].rx_buf[uart_info_8bit[FECBUS_UART].rx_index] = cc; + if(7 == uart_info_8bit[FECBUS_UART].rx_index){ + uart_info_8bit[FECBUS_UART].rx_len = 11 + cc; + if(uart_info_8bit[FECBUS_UART].rx_len > 19){ + fecbus_rx_prm.state = 0; + fecbus_rx_prm.starttime_flag = 0; + fecbus_rx_prm.timecount = 0; + }else{ + fecbus_rx_prm.state++; + } + }else + if(uart_info_8bit[FECBUS_UART].rx_index > 7){ + fecbus_rx_prm.state = 0; + fecbus_rx_prm.starttime_flag = 0; + fecbus_rx_prm.timecount = 0; + } + break; + + case 2: + uart_info_8bit[FECBUS_UART].rx_index++; + uart_info_8bit[FECBUS_UART].rx_buf[uart_info_8bit[FECBUS_UART].rx_index] = cc; + if(((uart_info_8bit[FECBUS_UART].rx_len - 1) == uart_info_8bit[FECBUS_UART].rx_index)&&(fecbus_rx_prm.timecount < FECBUS_RX_TIMEOUT)&&(cc == 0x7E)){ + uart_info_8bit[FECBUS_UART].rx_complete = 1; + fecbus_rx_prm.state = 0; + fecbus_rx_prm.starttime_flag = 0; + fecbus_rx_prm.timecount = 0; + }else + if(uart_info_8bit[FECBUS_UART].rx_index > 19){ + fecbus_rx_prm.state = 0; + fecbus_rx_prm.starttime_flag = 0; + fecbus_rx_prm.timecount = 0; + } + break; + + default: + fecbus_rx_prm.state = 0; + fecbus_rx_prm.starttime_flag = 0; + fecbus_rx_prm.timecount = 0; + break; + } + } +} + +void uart2_rx_task(void) +{ + static unsigned int set_crc_error_flag = 0; + + if(uart_info_8bit[FECBUS_UART].rx_complete){ + uart_info_8bit[FECBUS_UART].rx_complete = 0; + if(!check_crc(uart_info_8bit[FECBUS_UART].rx_buf,(uart_info_8bit[FECBUS_UART].rx_len-1))){ + LoadCRTViaFECBbus(uart_info_8bit[FECBUS_UART].rx_buf); + }else{ + if((0x7E == uart_info_8bit[FECBUS_UART].rx_buf[0])&&\ + (0x7E == uart_info_8bit[FECBUS_UART].rx_buf[uart_info_8bit[FECBUS_UART].rx_len-1])&&\ + (0 == uart_info_8bit[FECBUS_UART].rx_buf[1])){ + + set_crc_error_flag = 0; + } + } + + if((set_crc_error_flag)&&(0 == uart_info_8bit[FECBUS_UART].rx_buf[6])){ + set_crc_error_flag = 0; + //SetRpyFECBusCRCError(); + } + } +} +void uart_fecbus_task(void) +{ + uart2_rx_task(); +} + diff --git a/FW/Core/my_src/uart_fecbus_drv.h b/FW/Core/my_src/uart_fecbus_drv.h new file mode 100644 index 0000000..580fe52 --- /dev/null +++ b/FW/Core/my_src/uart_fecbus_drv.h @@ -0,0 +1,19 @@ +#ifndef UART_FECBUS_DRV_H_ +#define UART_FECBUS_DRV_H_ + +typedef struct{ + unsigned int state; + unsigned int starttime_flag; + unsigned int timecount; +}T_FECBus_RX_Prm; + +extern T_FECBus_RX_Prm fecbus_rx_prm; + +extern unsigned int fecbus_tx_is_busy(void); +extern void set_fecbus_tx_data(unsigned char * pdata); + +extern void fecbus_rx_tick(void); +extern void fecbus_rx_irq(void); +extern void uart_fecbus_task(void); + +#endif diff --git a/FW/Core/my_src/uart_key_drv.c b/FW/Core/my_src/uart_key_drv.c new file mode 100644 index 0000000..27d7bf1 --- /dev/null +++ b/FW/Core/my_src/uart_key_drv.c @@ -0,0 +1,388 @@ +#include "HW_config.h" +#include "uart_key_drv.h" +#include "relay_task.h" +#include "uart_task.h" +#include "CnCpp.h" + +#define KEY_UART 7 + +typedef enum{ + SEND_CMD_40H_SET_STATE = 0x001, + SEND_CMD_41H_SELF_CHECK = 0x002, + SEND_CMD_42H_RESET = 0x004, + SEND_CMD_42H_RESET_DUMP = 0x008, + SEND_CMD_43H_SET_POWER_COUNT = 0x010, + SEND_CMD_44H_GET_POWER0_VER = 0x020, + SEND_CMD_44H_GET_POWER1_VER = 0x040, + SEND_CMD_44H_GET_POWER2_VER = 0x080, + SEND_CMD_45H_GET_BRD_VER = 0x100, + SEND_CMD_46H_GET_BRD_DESCP = 0x200, + SEND_CMD_47H_SCAN_POWER = 0x400, + SEND_CMD_60H_ASK_POWER_CNT = 0x800, +}; + +unsigned int send_cmd_flag = 0; +Sys_State_Struct p_d2u_data; + +unsigned char set_power_count = 0; + +//key brd +void uart7_rx_task(void) +{ + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[7]; + unsigned int aLen; + unsigned int cmd; + + if(p_uart_info->rx_complete){ + p_uart_info->rx_complete = 0; + if((p_uart_info->rx_len <= UART_RX_BUF_MAX)&&(p_uart_info->rx_len > 3)){ + if(((p_uart_info->rx_len - 4) == p_uart_info->rx_buf[1]) && + (KEY_UART_HEAD == p_uart_info->rx_buf[0]) && + (KEY_UART_END == p_uart_info->rx_buf[p_uart_info->rx_len-1]) && + (!check_sum8(p_uart_info->rx_buf,(p_uart_info->rx_len - 2)))) + { + aLen = p_uart_info->rx_buf[1]; + cmd = p_uart_info->rx_buf[2]; + if(aLen == 4){ + if(1 == p_uart_info->rx_buf[3]){ + KeyRdy = 1; + KeyValue = p_uart_info->rx_buf[4]; + } + LoadBatStateViaKeyPad(p_uart_info->rx_buf[5]); + KeyPadSilenceTickClear(); + }else + if(aLen == 1){ + if(0x43 == cmd){ + KeyPadAskPowerCount(); + KeyPadSilenceTickClear(); + } + }else + if(aLen == 14){ + if(p_uart_info->rx_buf[2] == 0){ + LoadPsBatStateViaKeyPad(&p_uart_info->rx_buf[4]); + KeyPadSilenceTickClear(); + }else if(p_uart_info->rx_buf[2] == 1){ + LoadPsBatStateViaKeyPadSub1(&p_uart_info->rx_buf[3]); + KeyPadSilenceTickClear(); + }else if(p_uart_info->rx_buf[2] == 2){ + LoadPsBatStateViaKeyPadSub2(&p_uart_info->rx_buf[3]); + KeyPadSilenceTickClear(); + } + }else + if(aLen == 9){ + if(0x44 == cmd){ + GetHwInfo(p_uart_info->rx_buf[3],1,&p_uart_info->rx_buf[3]); + }else + if(0x45 == cmd){ + GetHwInfo(p_uart_info->rx_buf[3],1,&p_uart_info->rx_buf[3]); + }else + if(0x46 == cmd){ + GetHwInfo(p_uart_info->rx_buf[3],0,&p_uart_info->rx_buf[3]); + } + }else + if(aLen == 5){ + if(0x60 == cmd){ + GetPowerCount(p_uart_info->rx_buf[3], p_uart_info->rx_buf[4], p_uart_info->rx_buf[5], 0); + } + } + } + } + } +} + +void uart_key_task(void) +{ + uart7_rx_task(); +} + +void sys_display_led_state(unsigned int aState) +{ + p_d2u_data.D32 = aState; + send_cmd_flag |= SEND_CMD_40H_SET_STATE; +} + +void sys_set_key_self_detect_state(unsigned char self_det_state) +{ + send_cmd_flag |= SEND_CMD_41H_SELF_CHECK; +} + +void sys_set_key_reset_dump_state(void) +{ + send_cmd_flag |= SEND_CMD_42H_RESET_DUMP; +} + +void sys_set_key_reset_state(void) +{ + send_cmd_flag |= SEND_CMD_42H_RESET; +} + +void sys_set_power_suply_count(unsigned char aCnt) +{ + if(aCnt > 3)return; + + set_power_count = aCnt; + send_cmd_flag |= SEND_CMD_43H_SET_POWER_COUNT; +} + +void sys_get_power_ver(unsigned char power_ord) +{ + if(power_ord > 2)return; + + if(0 == power_ord){ + send_cmd_flag |= SEND_CMD_44H_GET_POWER0_VER; + }else + if(1 == power_ord){ + send_cmd_flag |= SEND_CMD_44H_GET_POWER1_VER; + }else + if(2 == power_ord){ + send_cmd_flag |= SEND_CMD_44H_GET_POWER2_VER; + } +} + +void sys_get_sw_brd_ver(void) +{ + send_cmd_flag |= SEND_CMD_45H_GET_BRD_VER; +} + +void sys_get_sw_brd_descp(void) +{ + send_cmd_flag |= SEND_CMD_46H_GET_BRD_DESCP; +} + +void sys_set_scan_power(void) +{ + send_cmd_flag |= SEND_CMD_47H_SCAN_POWER; +} + +void sys_get_power_Count(void) +{ + send_cmd_flag |= SEND_CMD_60H_ASK_POWER_CNT; +} + +void sys_key_uart_tx_task(void)//1ms +{ + static unsigned int send_tick = 0; + unsigned char check_sum = 0; + + send_tick++; + if(send_tick > 8){ + send_tick = 0; + + if(send_cmd_flag & SEND_CMD_40H_SET_STATE){ + send_cmd_flag &=~SEND_CMD_40H_SET_STATE; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x40; + UART7->TDR = 0x04; + UART7->TDR = p_d2u_data.state_val[0]; + UART7->TDR = p_d2u_data.state_val[1]; + UART7->TDR = p_d2u_data.state_val[2]; + UART7->TDR = p_d2u_data.state_val[3]; + + check_sum = KEY_UART_HEAD+0x40+0x04+p_d2u_data.state_val[0]+p_d2u_data.state_val[1]+p_d2u_data.state_val[2]+p_d2u_data.state_val[3]; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_41H_SELF_CHECK){ + send_cmd_flag &=~SEND_CMD_41H_SELF_CHECK; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x41; + UART7->TDR = 0x04; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x41+0x04; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_42H_RESET){ + send_cmd_flag &=~SEND_CMD_42H_RESET; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x42; + UART7->TDR = 0x04; + UART7->TDR = 0; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x42+0x04; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_42H_RESET_DUMP){ + send_cmd_flag &=~SEND_CMD_42H_RESET_DUMP; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x42; + UART7->TDR = 0x04; + UART7->TDR = 0xAA; + UART7->TDR = 0x55; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x42+0x04+0xAA+0x55; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_43H_SET_POWER_COUNT){ + send_cmd_flag &=~SEND_CMD_43H_SET_POWER_COUNT; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x43; + UART7->TDR = 0x04; + UART7->TDR = set_power_count; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x43+0x04+set_power_count; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_44H_GET_POWER0_VER){ + send_cmd_flag &=~SEND_CMD_44H_GET_POWER0_VER; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x44; + UART7->TDR = 0x04; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x44+0x04+0x00; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_44H_GET_POWER1_VER){ + send_cmd_flag &=~SEND_CMD_44H_GET_POWER1_VER; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x44; + UART7->TDR = 0x04; + UART7->TDR = 0x01; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x44+0x04+0x01; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_44H_GET_POWER2_VER){ + send_cmd_flag &=~SEND_CMD_44H_GET_POWER2_VER; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x44; + UART7->TDR = 0x04; + UART7->TDR = 0x02; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x44+0x04+0x02; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_45H_GET_BRD_VER){ + send_cmd_flag &=~SEND_CMD_45H_GET_BRD_VER; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x45; + UART7->TDR = 0x04; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x45+0x04+0; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_46H_GET_BRD_DESCP){ + send_cmd_flag &=~SEND_CMD_46H_GET_BRD_DESCP; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x46; + UART7->TDR = 0x04; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x46+0x04+0; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_47H_SCAN_POWER){ + send_cmd_flag &=~SEND_CMD_47H_SCAN_POWER; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x47; + UART7->TDR = 0x04; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x47+0x04+0; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + }else + + if(send_cmd_flag & SEND_CMD_60H_ASK_POWER_CNT){ + send_cmd_flag &=~SEND_CMD_60H_ASK_POWER_CNT; + + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x60; + UART7->TDR = 0x04; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + + check_sum = KEY_UART_HEAD+0x60+0x04+0; + UART7->TDR = check_sum; + + UART7->TDR = KEY_UART_END; + } + } +} + +void lcd_bl_on(void) +{ + LL_TIM_OC_SetCompareCH2(TIM3,255);//bl; +} + +void lcd_bl_off(void) +{ + LL_TIM_OC_SetCompareCH2(TIM3,0);//bl; +} + + diff --git a/FW/Core/my_src/uart_key_drv.h b/FW/Core/my_src/uart_key_drv.h new file mode 100644 index 0000000..40fae92 --- /dev/null +++ b/FW/Core/my_src/uart_key_drv.h @@ -0,0 +1,28 @@ +#ifndef UART_KEY_DRV_H_ +#define UART_KEY_DRV_H_ + +//UART7 key use +#define KEY_UART_HEAD 0xFF +#define KEY_UART_END 0xFE + +extern void sys_display_led_state(unsigned int aState); +extern void sys_set_key_self_detect_state(unsigned char self_det_state); +extern void sys_set_key_reset_state(void); +extern void sys_set_key_reset_dump_state(void); +extern void sys_set_power_suply_count(unsigned char aCnt); +extern void sys_get_power_ver(unsigned char power_ord); +extern void sys_get_sw_brd_ver(void); +extern void sys_get_sw_brd_descp(void); +extern void sys_set_scan_power(void); +extern void sys_get_power_Count(void); + +extern void sys_error_led_task(void); + +extern void sys_key_uart_tx_task(void); + +extern void lcd_bl_on(void); +extern void lcd_bl_off(void); + +extern void uart_key_task(void); + +#endif diff --git a/FW/Core/my_src/uart_linkage_drv.c b/FW/Core/my_src/uart_linkage_drv.c new file mode 100644 index 0000000..c29885d --- /dev/null +++ b/FW/Core/my_src/uart_linkage_drv.c @@ -0,0 +1,144 @@ +#include "HW_Config.h" +#include "uart_linkage_drv.h" +#include "CnCpp.h" + +#define LINKAGE_UART 3 + +typedef union{ + unsigned int D32; + unsigned char D8[4]; + struct{ + unsigned char Cmd; + unsigned char Order; + unsigned char CarryByte; + unsigned char PriRoutingIdf; + }Id; +}TC2CIdBody; + +static unsigned int uart_tx_error_flag = 0; + +unsigned int get_uart_tx_error_flag(void) +{ + return uart_tx_error_flag; +} + +void uart3_rx_task(void) +{ + unsigned int Cmd; + + if(uart_info_8bit[LINKAGE_UART].rx_complete){ + uart_info_8bit[LINKAGE_UART].rx_complete = 0; + if((uart_info_8bit[LINKAGE_UART].rx_len <= 13)&&(uart_info_8bit[LINKAGE_UART].rx_len >= 5)){ + if((uart_info_8bit[LINKAGE_UART].rx_len - 5) == uart_info_8bit[LINKAGE_UART].rx_buf[4]){ + Cmd = uart_info_8bit[LINKAGE_UART].rx_buf[3]; + Cmd<<=8; + Cmd |= uart_info_8bit[LINKAGE_UART].rx_buf[2]; + Cmd<<=8; + Cmd |= uart_info_8bit[LINKAGE_UART].rx_buf[1]; + Cmd<<=8; + Cmd |= uart_info_8bit[LINKAGE_UART].rx_buf[0]; + LoadOuterCanRxMsg(Cmd, (&uart_info_8bit[LINKAGE_UART].rx_buf[5]), uart_info_8bit[LINKAGE_UART].rx_buf[4]); + }else + if(5 == uart_info_8bit[LINKAGE_UART].rx_len){ + if(14 == uart_info_8bit[LINKAGE_UART].rx_buf[4]){//ALL_FULL_FLAG + uart_tx_error_flag = 3; + }else + if(12 == uart_info_8bit[LINKAGE_UART].rx_buf[4]){//CLOSE_FULL_FLAG + uart_tx_error_flag = 2; + }else + if(16 == uart_info_8bit[LINKAGE_UART].rx_buf[4]){//ERR_HANDLE_FLAG can send fail + uart_tx_error_flag = 1; + }else + if(20 == uart_info_8bit[LINKAGE_UART].rx_buf[4]){//recover from error + uart_tx_error_flag = 0; + } + SetOuterCanTxMsgState(uart_tx_error_flag); + } + }else{ + if((0x5A == uart_info_8bit[LINKAGE_UART].rx_buf[uart_info_8bit[LINKAGE_UART].rx_len-1]) && \ + (0xA5 == uart_info_8bit[LINKAGE_UART].rx_buf[0]) && \ + ((uart_info_8bit[LINKAGE_UART].rx_buf[2] + 4) == uart_info_8bit[LINKAGE_UART].rx_len)){ + GetHwInfo(uart_info_8bit[LINKAGE_UART].rx_buf[3],1,&uart_info_8bit[LINKAGE_UART].rx_buf[3]); + GetHwInfo(uart_info_8bit[LINKAGE_UART].rx_buf[11],0,&uart_info_8bit[LINKAGE_UART].rx_buf[11]); + } + } + } +} + +void uart_linkage_task(void) +{ + uart3_rx_task(); +} + +unsigned int get_excan_linkage_tx_complete(void) +{ + return get_uart_tx_complete_delay_flag(LINKAGE_UART); +} + +void uart_linkage_tx_data(unsigned char * pdata, unsigned int len) +{ + uart_tx_over(LINKAGE_UART, pdata, len); +} + +unsigned int outer_can_send_data(volatile unsigned int head, volatile unsigned char * pdata, volatile unsigned int len) +{ + unsigned int i = 0; + + static TC2CIdBody exId; + + if(len > 8)return 1; + if(!get_excan_linkage_tx_complete())return 1; + + exId.D32 = head; + + USART3->TDR = exId.Id.Cmd; + USART3->TDR = exId.Id.Order; + USART3->TDR = exId.Id.CarryByte; + USART3->TDR = exId.Id.PriRoutingIdf & 0b00011111; + USART3->TDR = len; + for(i=0;iTDR = pdata[i]; + } + uart_info_8bit[LINKAGE_UART].tx_complete = 1; + uart_info_8bit[LINKAGE_UART].tx_complete_delay_flag = 0; + uart_info_8bit[LINKAGE_UART].tx_complete_delay_tick= 0; + return 0; +} + +void get_commbrd_ver_modle(void) +{ + while(0 == get_excan_linkage_tx_complete()); + USART3->TDR = 0xA5; + USART3->TDR = 0x50; + USART3->TDR = 0; + USART3->TDR = 0x5A; + uart_info_8bit[LINKAGE_UART].tx_complete = 1; + uart_info_8bit[LINKAGE_UART].tx_complete_delay_flag = 0; + uart_info_8bit[LINKAGE_UART].tx_complete_delay_tick= 0; +} + +unsigned int outer_can_send_data_(unsigned int head, unsigned char * pdata, unsigned int len) +{ + unsigned int i = 0; + unsigned char data[16] = {0}; + + TC2CIdBody exId; + + if(len > 8)return 1; + if(!get_excan_linkage_tx_complete())return 1; + + exId.D32 = head; + + data[0] = exId.Id.Cmd; + data[1] = 0; + data[2] = 0; + data[3] = (exId.Id.PriRoutingIdf) & (0b00011111); + data[4] = len; + for(i=0;i>8); + + uart_info_8bit[TEST_UART].tx_buf[len+2] = TEST_UART_END; + uart_info_8bit[TEST_UART].tx_len = len+3; + + uart_tx_trigger(TEST_UART); +} + +void test_rx_timeout_tick(void)//1ms in irq +{ + if(rx_starttime_flag){ + rx_timecount++; + if(rx_timecount > 55){//57600 272byte:48ms + rx_state = 0; + rx_starttime_flag = 0; + rx_timecount = 0; + } + } + + if(rpy_usb_state){ + if(rpy_usb_state_tick > 3000){ + rpy_usb_state_tick = 0; + rpy_usb_state = 0; + + if(UsbConfigGetState()){ + gbk_tx_pkg->prm.data[1] = 1; + }else{ + gbk_tx_pkg->prm.data[1] = 0; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = 0xA0; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = 0x22; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else{ + rpy_usb_state_tick++; + } + }else{ + rpy_usb_state_tick = 0; + } +} + +void test_rx_irq(void) +{ + unsigned short cc; + + if(LL_USART_IsActiveFlag_RXNE(LPUART1)) + { + cc = LL_USART_ReceiveData8(LPUART1); + switch(rx_state){ + case 0 : + if(TEST_UART_HEAD == cc){ + uart_info_8bit[TEST_UART].rx_index = 0; + uart_info_8bit[TEST_UART].rx_buf[uart_info_8bit[TEST_UART].rx_index] = cc; + uart_info_8bit[TEST_UART].rx_len = UART_RX_BUF_MAX; + rx_starttime_flag = 1; + rx_state++; + } + break; + + case 1: + uart_info_8bit[TEST_UART].rx_index++; + uart_info_8bit[TEST_UART].rx_buf[uart_info_8bit[TEST_UART].rx_index] = cc; + if(3 == uart_info_8bit[TEST_UART].rx_index){ + if(uart_info_8bit[TEST_UART].rx_buf[1] > 0x80){ + uart_info_8bit[TEST_UART].rx_len = uart_info_8bit[TEST_UART].rx_buf[3]; + uart_info_8bit[TEST_UART].rx_len<<=8; + uart_info_8bit[TEST_UART].rx_len |= uart_info_8bit[TEST_UART].rx_buf[2]; + uart_info_8bit[TEST_UART].rx_len +=7; + if(uart_info_8bit[TEST_UART].rx_len > (260+8)){ + rx_state = 0; + rx_starttime_flag = 0; + rx_timecount = 0; + }else{ + rx_state++; + } + }else{ + uart_info_8bit[TEST_UART].rx_len = 7 + cc; + if(uart_info_8bit[TEST_UART].rx_len > 128){ + rx_state = 0; + rx_starttime_flag = 0; + rx_timecount = 0; + }else{ + rx_state++; + } + } + }else + if(uart_info_8bit[TEST_UART].rx_index > 3){ + rx_state = 0; + rx_starttime_flag = 0; + rx_timecount = 0; + } + break; + + case 2: + uart_info_8bit[TEST_UART].rx_index++; + uart_info_8bit[TEST_UART].rx_buf[uart_info_8bit[TEST_UART].rx_index] = cc; + if(((uart_info_8bit[TEST_UART].rx_len - 1) == uart_info_8bit[TEST_UART].rx_index)&&(rx_timecount < TEST_RX_TIMEOUT)&&(cc == TEST_UART_END)){ + uart_info_8bit[TEST_UART].rx_complete = 1; + rx_state = 0; + rx_starttime_flag = 0; + rx_timecount = 0; + }else + if(uart_info_8bit[TEST_UART].rx_index > uart_info_8bit[TEST_UART].rx_len){ + rx_state = 0; + rx_starttime_flag = 0; + rx_timecount = 0; + } + break; + + default: + rx_state = 0; + rx_starttime_flag = 0; + rx_timecount = 0; + break; + } + } +} + +void lpuart_rx_task(void) +{ + if(uart_info_8bit[TEST_UART].rx_complete){ + uart_info_8bit[TEST_UART].rx_complete = 0; + + //LoadDebugViaFECTest(uart_info_8bit[TEST_UART].rx_buf); + if(!check_crc(uart_info_8bit[TEST_UART].rx_buf,(uart_info_8bit[TEST_UART].rx_len-1))){ + if(uart_info_8bit[TEST_UART].rx_buf[1] < 0x80){ + //-----------------config app handle------------------ + config_app_handle(); + }else{ + //-----------------gbk download handle---------------- + gbk_download_handle(); + } + } + } +} + +void uart_test_task(void) +{ + lpuart_rx_task(); +} + +void gbk_nor_load_to_sdram(void) +{ + unsigned int x,y; + for(y = 0;y < SIZE_OF_PAGE_GBK_LIB;y++){ + nor_read_page(0, (NORFLASH_GBK_ADDR + (y * 256)), load_data.D8); + for(x = 0;x < 64;x++){ + *(volatile unsigned int *)(SDRAM_GBK_ADDR + (y * 256) + (x * 4)) = load_data.D32[x]; + } + } +} + +void gbk_download_handle(void) +{ + unsigned int i,aFlashState; + + gbk_tx_pkg = (Tcom_gbk_pkg_gbk *)test_uart_tx; + gbk_rx_pkg = (Tcom_gbk_pkg_gbk *)uart_info_8bit[TEST_UART].rx_buf; + + if(0x88 == gbk_rx_pkg->prm.cmd){ + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 0; + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x90 == gbk_rx_pkg->prm.cmd){ + for(i=0;iprm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 4; + gbk_tx_pkg->prm.data[0] = 0xAA; + gbk_tx_pkg->prm.data[1] = 0; + gbk_tx_pkg->prm.data[2] = 0; + gbk_tx_pkg->prm.data[3] = 0; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x91 == gbk_rx_pkg->prm.cmd){ + nor_write_page(dFlashGBKChipX,(NORFLASH_GBK_ADDR + (gbk_rx_pkg->D32[1] * 256)),&gbk_rx_pkg->prm.data[4]); + do{ + HAL_Delay(2); + aFlashState = nor_get_busy_state(dFlashGBKChipX); + }while(aFlashState); + + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 4; + gbk_tx_pkg->prm.data[0] = 0xAA; + gbk_tx_pkg->prm.data[1] = 0; + gbk_tx_pkg->prm.data[2] = 0; + gbk_tx_pkg->prm.data[3] = 0; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + //-------------------------------------------------test(测试板子)-------------------------------------------------- + if(0xA0 == gbk_rx_pkg->prm.cmd){ + if(0x20 == gbk_rx_pkg->prm.data[0]){//测试uart1-7 + hw_test_mode = 1; + hw_test_init(); + + gbk_tx_pkg->prm.data[1] = (unsigned char)hw_uart_test_all() + 1; + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x21 == gbk_rx_pkg->prm.data[0]){//退出测试 + hw_test_mode = 0; + hw_test_deinit(); + + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + gbk_tx_pkg->prm.data[1] = 1; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x22 == gbk_rx_pkg->prm.data[0]){//检测U盘 + if(hw_test_mode){ + if(usb_is_host){ + if(UsbConfigGetState()){ + gbk_tx_pkg->prm.data[1] = 1; + }else{ + gbk_tx_pkg->prm.data[1] = 0; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else{ + usb_device_to_host(); + rpy_usb_state = 1; + } + }else{ + usb_host_to_device(); + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + gbk_tx_pkg->prm.data[1] = 0x55; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + } + }else + if(0x24 == gbk_rx_pkg->prm.data[0]){//测试显示屏 + if(hw_test_mode){ + hw_lcd_test(); + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + gbk_tx_pkg->prm.data[1] = hw_test_mode; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x25 == gbk_rx_pkg->prm.data[0]){//测试nor flash读写 + if(hw_test_mode){ + if(hw_nor_flash_test()){ + gbk_tx_pkg->prm.data[1] = 0; + }else{ + gbk_tx_pkg->prm.data[1] = 1; + } + }else{ + gbk_tx_pkg->prm.data[1] = 0x55; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x26 == gbk_rx_pkg->prm.data[0]){//测试eeprom读写 + if(hw_test_mode){ + if(hw_eeprom_test()){ + gbk_tx_pkg->prm.data[1] = 0; + }else{ + gbk_tx_pkg->prm.data[1] = 1; + } + }else{ + gbk_tx_pkg->prm.data[1] = 0x55; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x27 == gbk_rx_pkg->prm.data[0]){//测试sdram读写 + if(hw_test_mode){ + if(hw_sdram_test()){ + gbk_tx_pkg->prm.data[1] = 0; + }else{ + gbk_tx_pkg->prm.data[1] = 1; + } + }else{ + gbk_tx_pkg->prm.data[1] = 0x55; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x28 == gbk_rx_pkg->prm.data[0]){//测试print + if(hw_test_mode){ + hw_print_test(); + gbk_tx_pkg->prm.data[1] = 1; + }else{ + gbk_tx_pkg->prm.data[1] = 0x55; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x29 == gbk_rx_pkg->prm.data[0]){//测试继电器 + if(hw_test_mode){ + hw_relay_test(); + gbk_tx_pkg->prm.data[1] = 1; + }else{ + gbk_tx_pkg->prm.data[1] = 0x55; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0x2A == gbk_rx_pkg->prm.data[0]){//测试uart1-7 除uart6 + hw_test_mode = 1; + hw_test_init(); + + gbk_tx_pkg->prm.data[1] = (unsigned char)hw_uart_test() + 1; + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 2; + gbk_tx_pkg->prm.data[0] = gbk_rx_pkg->prm.data[0]; + + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + } + }else + //-------------------------------------------------读写编码-------------------------------------------------- + if(0xB0 == gbk_rx_pkg->prm.cmd){ + if((gbk_rx_pkg->prm.data[0] > 0)&&(gbk_rx_pkg->prm.data[0] < 255)){ + factory_prm.ctl_type = gbk_rx_pkg->prm.data[0]; + for(i=0;i<7;i++)factory_prm.pid[i] = gbk_rx_pkg->prm.data[i+4]; + factory_prm.pid[7] = 0; + + write_factory_prm(); + + gbk_tx_pkg->prm.data[0] = 1; + }else{ + gbk_tx_pkg->prm.data[0] = 0; + } + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 1; + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + }else + if(0xB1 == gbk_rx_pkg->prm.cmd){ + gbk_tx_pkg->prm.head = TEST_UART_HEAD; + gbk_tx_pkg->prm.cmd = gbk_rx_pkg->prm.cmd; + gbk_tx_pkg->prm.len = 16; + gbk_tx_pkg->prm.data[0] = factory_prm.ctl_type & 0xFF; + gbk_tx_pkg->prm.data[1] = 0; + gbk_tx_pkg->prm.data[2] = 0; + gbk_tx_pkg->prm.data[3] = 0; + gbk_tx_pkg->prm.data[4] = factory_prm.pid[0]; + gbk_tx_pkg->prm.data[5] = factory_prm.pid[1]; + gbk_tx_pkg->prm.data[6] = factory_prm.pid[2]; + gbk_tx_pkg->prm.data[7] = factory_prm.pid[3]; + gbk_tx_pkg->prm.data[8] = factory_prm.pid[4]; + gbk_tx_pkg->prm.data[9] = factory_prm.pid[5]; + gbk_tx_pkg->prm.data[10] = factory_prm.pid[6]; + gbk_tx_pkg->prm.data[11] = 0; + gbk_tx_pkg->prm.data[12] = 0; + gbk_tx_pkg->prm.data[13] = 0; + gbk_tx_pkg->prm.data[14] = 0; + gbk_tx_pkg->prm.data[15] = 0; + set_test_tx_data(gbk_tx_pkg->D8, (gbk_tx_pkg->prm.len + 4)); + } +} + +void config_app_handle(void) +{ + GetCfgViaUartRx(); +} diff --git a/FW/Core/my_src/uart_lp_test_drv.h b/FW/Core/my_src/uart_lp_test_drv.h new file mode 100644 index 0000000..91ac573 --- /dev/null +++ b/FW/Core/my_src/uart_lp_test_drv.h @@ -0,0 +1,108 @@ +#ifndef UART_LP_TEST_DRV_H_ +#define UART_LP_TEST_DRV_H_ + +#define TEST_UART_HEAD 0xD7 +#define TEST_UART_END 0xEE + +#define TEST_UART 0 + +typedef union{ + unsigned char D8[64]; + unsigned int D32[16]; + struct{ + unsigned char Head; + unsigned char Cmd; + unsigned char count; + unsigned char Len; + union{ + unsigned char Data8[60]; + unsigned int Data32[15]; + struct{ + unsigned char loopCount; + unsigned char busPanelCount; + unsigned char dirPanelCount; + unsigned char areaCount; + char desc[32]; + unsigned char rsv[24]; + }CmdCtl; + struct{ + unsigned char id; + unsigned char devId;//dev for device + unsigned char devType; + unsigned char assignType; + unsigned char devProperty; + unsigned char areaId; + unsigned short delayTime; + unsigned int devNum; + char desc[32]; + unsigned char rsv[16]; + }CmdLoop; + struct{ + unsigned char id; + unsigned char keyId; + unsigned short rsv; + union{ + unsigned char d8[4]; + unsigned int d32; + struct{ + unsigned char val; + unsigned char loopId; + unsigned char startAddr; + unsigned char endAddr; + }methodAddr; + struct{ + unsigned char val; + unsigned char loopId; + unsigned char devType; + unsigned char rsv; + }methodType; + struct{ + unsigned char val; + unsigned char loopId; + unsigned char areaId; + unsigned char rsv; + }methodArea; + }prm; + unsigned int Num; + char desc[32]; + unsigned char rsv2[16]; + }CmdBus; + struct{ + unsigned char Id; + unsigned char keyId; + unsigned char outProp; + unsigned char ctlDevType; + unsigned char errDetFlag; + unsigned char areaId; + unsigned short rsv; + unsigned int Num; + char desc[32]; + unsigned char rsv2[16]; + }CmdDir; + struct{ + unsigned char id; + unsigned char rsv; + unsigned short rsv2; + unsigned int Num; + char desc[32]; + unsigned char rsv3[20]; + }CmdArea; + }Frm; + }Cfg; +}TConfigUartData; + +extern unsigned int deviceCfgCount; +extern unsigned int BusPanelKeyCfgCount; +extern unsigned int DirPanelKeyCfgCount; +extern unsigned int AreaCfgCount; + +extern unsigned int test_tx_is_busy(void); +extern void set_test_tx_data(unsigned char * pdata, unsigned int len); + +extern void test_rx_timeout_tick(void); +extern void test_rx_irq(void); +extern void uart_test_task(void); + +extern void gbk_nor_load_to_sdram(void); + +#endif diff --git a/FW/Core/my_src/uart_memory_drv.c b/FW/Core/my_src/uart_memory_drv.c new file mode 100644 index 0000000..6afd546 --- /dev/null +++ b/FW/Core/my_src/uart_memory_drv.c @@ -0,0 +1,60 @@ +#include "HW_Config.h" +#include "uart_memory_drv.h" +#include "CnCpp.h" + +#define MEMORY_UART 5 + +unsigned char memory_uart_tx[32]; + +unsigned int memory_is_busy(void)//1:is busy 0:no busy +{ + if(!get_uart_tx_complete_delay_flag(MEMORY_UART))return 1; + + return 0; +} + +void set_memory_tx_data(unsigned char cmd, unsigned char * pdata, unsigned int len) +{ + unsigned int i = 0; + + if(len > 32)return; + + memory_uart_tx[0] = MEMORY_UART_HEAD; + memory_uart_tx[1] = 0x55; + memory_uart_tx[2] = cmd; + memory_uart_tx[3] = len; + for(i=0;irx_complete){ + p_uart_info->rx_complete = 0; + if((p_uart_info->rx_len <= UART_RX_BUF_MAX)&&(p_uart_info->rx_len >= 6)){ + if(((p_uart_info->rx_len - 6) == p_uart_info->rx_buf[3])&&(0xAA == p_uart_info->rx_buf[1])&&\ + (MEMORY_UART_HEAD == p_uart_info->rx_buf[0])&&(MEMORY_UART_END == p_uart_info->rx_buf[p_uart_info->rx_len-1])){ + if(0 == (check_sum8(p_uart_info->rx_buf, (p_uart_info->rx_len-2)))){ + LoadExRecordViaMemory(&(p_uart_info->rx_buf[2])); + } + } + } + } +} + +void uart_memory_task(void) +{ + uart5_rx_task(); +} + + diff --git a/FW/Core/my_src/uart_memory_drv.h b/FW/Core/my_src/uart_memory_drv.h new file mode 100644 index 0000000..bd50e6f --- /dev/null +++ b/FW/Core/my_src/uart_memory_drv.h @@ -0,0 +1,12 @@ +#ifndef UART_MEMORY_DRV_H_ +#define UART_MEMORY_DRV_H_ + +//UART5 memory use +#define MEMORY_UART_HEAD 0x48 +#define MEMORY_UART_END 0x41 + +extern void uart_memory_task(void); +extern unsigned int memory_is_busy(void); +extern void set_memory_tx_data(unsigned char cmd, unsigned char * pdata, unsigned int len); + +#endif diff --git a/FW/Core/my_src/uart_printer_drv.c b/FW/Core/my_src/uart_printer_drv.c new file mode 100644 index 0000000..41c0f88 --- /dev/null +++ b/FW/Core/my_src/uart_printer_drv.c @@ -0,0 +1,233 @@ +#include "HW_Config.h" +#include "uart_printer_drv.h" + +#define PRINT_UART 6 + +#define GET_PRINTER_PAPER_FLAG 0x01 + +unsigned char print_init_data[16]; +unsigned int print_init_data_len = 0; + +unsigned int get_printer_status_falg = 0; + +unsigned int printer_flag_no_paper = 0; +unsigned int printer_flag_err = 0; +unsigned int printer_Rpy = 0; +unsigned int printer_offline = 0; +unsigned int PrinterDivTick =0; + +void uart6_rx_task(void) +{ + uart_info_8bit_struct * p_uart_info; + p_uart_info = &uart_info_8bit[PRINT_UART]; + + if(p_uart_info->rx_complete){ + p_uart_info->rx_complete = 0; + + if(get_printer_status_falg & GET_PRINTER_PAPER_FLAG){ + get_printer_status_falg &=~GET_PRINTER_PAPER_FLAG; + if(0x04 == p_uart_info->rx_buf[0]){ + printer_flag_no_paper = 0; + printer_Rpy = 1; + }else + if(0x00 == p_uart_info->rx_buf[0]){ + printer_flag_no_paper = 1; + printer_Rpy = 1; + } + } + } +} + +unsigned int printer_is_busy(void)//1:is busy 0:no busy +{ + if((!get_uart_tx_complete_delay_flag(PRINT_UART))||(GET_PRINTER_STATUS()))return 1; + + return 0; +} + +void printer_reset_int(void) +{ + //系统复位 + print_init_data[0] = 0x10; + print_init_data[1] = 0x04; + print_init_data[2] = 0x03; + + print_init_data_len = 3; + + uart_tx_over(PRINT_UART, print_init_data, print_init_data_len); +} + +void printer_set_int(void) +{ + //初始化指令 + print_init_data[0] = 0x1B; + print_init_data[1] = 0x40; + //方向指令 + print_init_data[2] = 0x1B; + print_init_data[3] = 0x63; + print_init_data[4] = 0x01; + //字间距0 + print_init_data[5] = 0x1B; + print_init_data[6] = 0x70; + print_init_data[7] = 0x00; + //设置左限0 + print_init_data[8] = 0x1B; + print_init_data[9] = 0x6C; + print_init_data[10]= 0x00; + //设置右限0 + print_init_data[11]= 0x1B; + print_init_data[12]= 0x51; + print_init_data[13]= 0x00; + + print_init_data_len = 14; + + uart_tx_over(PRINT_UART, print_init_data, print_init_data_len); +} + +void get_printer_paper_status(void) +{ + //实时查询有无纸 + print_init_data[0] = 0x10; + print_init_data[1] = 0x04; + print_init_data[2] = 0x02; + + print_init_data_len = 3; + + //非实时查询有无纸 + print_init_data[0] = 0x1C; + print_init_data[1] = 0x76; + + print_init_data_len = 2; + + uart_tx_over(PRINT_UART, print_init_data, print_init_data_len); + + get_printer_status_falg |= GET_PRINTER_PAPER_FLAG; +} + +unsigned int set_print_text(char * p_data, unsigned int len) +{ + unsigned int i = 0; + + if(printer_is_busy())return 1; + if((!len)||(len > 16))return 1; + + for(i = 0;iTDR = *p_data; + p_data++; + } + uart_info_8bit[PRINT_UART].tx_complete = 1; + uart_info_8bit[PRINT_UART].tx_complete_delay_flag = 0; + uart_info_8bit[PRINT_UART].tx_complete_delay_tick= 0; + + return 0; +} + +unsigned int print_text(char * p_data) +{ + volatile char * pdata; + + pdata = p_data; + + print_init_data_len = 0; + while(*pdata){ + pdata++; + print_init_data_len++; + if(print_init_data_len > (UART_TX_BUF_MAX-1))break; + } + print_init_data_len+=1; + + if(printer_is_busy())return 1; + + if(print_init_data_len <= UART_TX_BUF_MAX){ + uart_tx_over(PRINT_UART, p_data, print_init_data_len); + return 0; + } + return 1; +} + +void printer_init(void) +{ + PRINTER_DRV_ENABLE(); + HAL_Delay(10); + printer_reset_int(); + HAL_Delay(500); + printer_set_int(); + HAL_Delay(20); + print_text("\r\n\r\n\r\n"); + HAL_Delay(5); +} + +void printer_task(void)//1S +{ + static unsigned int clear_tick = 0; + static unsigned int err_tick = 0; + static unsigned int no_rpy_times = 0; + static unsigned int HasStartCheck = 0; + + PrinterDivTick++; + if(PrinterDivTick>9){ + PrinterDivTick = 0; + if(HasStartCheck){ + HasStartCheck = 0; + if(printer_Rpy == 0){ + no_rpy_times++; + if(no_rpy_times >1){ + no_rpy_times = 2; + printer_offline = 1; + } + }else{ + no_rpy_times = 0; + printer_offline = 0; + } + PrcDevPrinterState(printer_offline , printer_flag_no_paper); + } + if(!printer_is_busy()){ + //if(0 == get_printer_status_falg){ + if(1){ + get_printer_paper_status(); + printer_Rpy = 0; + HasStartCheck =1; + }else{ + //clear_tick++; + //if(clear_tick > 9){ + // clear_tick = 0; + get_printer_status_falg = 0; + //} + } + err_tick = 0; + printer_flag_err = 0; + }else{ + err_tick++; + if(err_tick > 2 ){ + err_tick = 0; + printer_flag_err = 1; + } + } + } +} + +void printer_reset_callback(void) +{ + PrinterDivTick =0; +} + +void uart_printer_task(void) +{ + uart6_rx_task(); +} + +unsigned int get_printer_flag_no_paper(void)//1:no paper or err +{ + if(printer_flag_no_paper + printer_flag_err)return 1; + return 0; +} + +void set_enable_printer(void) +{ + PRINTER_DRV_ENABLE(); +} + +void set_disable_printer(void) +{ + PRINTER_DRV_DISABLE(); +} diff --git a/FW/Core/my_src/uart_printer_drv.h b/FW/Core/my_src/uart_printer_drv.h new file mode 100644 index 0000000..f229452 --- /dev/null +++ b/FW/Core/my_src/uart_printer_drv.h @@ -0,0 +1,23 @@ +#ifndef _PRINTER_UART_DRV_H +#define _PRINTER_UART_DRV_H +//#include "sys.h" +#include "main.h" + +#define PRINTER_DRV_ENABLE() LL_GPIO_SetOutputPin(GPIOA, LL_GPIO_PIN_7) +#define PRINTER_DRV_DISABLE() LL_GPIO_ResetOutputPin(GPIOA, LL_GPIO_PIN_7) + +#define GET_PRINTER_STATUS() LL_GPIO_IsInputPinSet(GPIOC, LL_GPIO_PIN_4) + + + +extern void printer_init(void); +extern void printer_task(void);//1S +extern void uart_printer_task(void); + +extern unsigned int printer_is_busy(void); +extern unsigned int print_text(char * p_data); +extern unsigned int set_print_text(char * p_data, unsigned int len); + +extern void printer_reset_callback(void); + +#endif diff --git a/FW/Core/my_src/uart_task.c b/FW/Core/my_src/uart_task.c new file mode 100644 index 0000000..3f3837f --- /dev/null +++ b/FW/Core/my_src/uart_task.c @@ -0,0 +1,49 @@ +#include "HW_config.h" +#include "uart_key_drv.h" +#include "uart_linkage_drv.h" +#include "uart_memory_drv.h" +#include "uart_printer_drv.h" +#include "uart_fecbus_drv.h" +#include "uart_fec_std_drv.h" +#include "uart_lp_test_drv.h" +#include "usb_cdc_task.h" +#include "CnCpp.h" + +void uart_task(void) +{ + uart_printer_task(); + uart_key_task(); + uart_linkage_task(); + uart_memory_task(); + uart_fecbus_task(); + uart_fec_std_task(); + uart_test_task(); + + usb_cdc_rx_handle(); +} + +void uart_interval_send(void)//1ms +{ + sys_key_uart_tx_task(); +} + + + + + + + + + + + + + + + + + + + + + diff --git a/FW/Core/my_src/uart_task.h b/FW/Core/my_src/uart_task.h new file mode 100644 index 0000000..b63539f --- /dev/null +++ b/FW/Core/my_src/uart_task.h @@ -0,0 +1,27 @@ +typedef union +{ + unsigned int D32; + volatile unsigned char state_val[4]; + struct + { + volatile unsigned int take_charge : 2; /* [0] */ + volatile unsigned int feedback : 2; /* [1] */ + volatile unsigned int start_delay : 2; /* [2] */ + volatile unsigned int start : 2; /* [3] */ + volatile unsigned int mute : 2; /* [4] */ + volatile unsigned int fault : 2; /* [5] */ + volatile unsigned int alarm : 2; /* [6] */ + volatile unsigned int rsv1 : 2; /* [7] */ + volatile unsigned int linkage : 2; /* [8] */ + volatile unsigned int rx : 2; /* [9] */ + volatile unsigned int tx : 2; /* [10] */ + volatile unsigned int self_check : 2; /* [11] */ + volatile unsigned int alarm_fault : 2; /* [12] */ + volatile unsigned int alarm_start : 2; /* [13] */ + volatile unsigned int shield : 2; /* [14] */ + volatile unsigned int rsv2 : 2; /* [15] */ + }state; +}Sys_State_Struct; + +extern void uart_task(void); +extern void uart_interval_send(void); diff --git a/FW/Core/my_src/uart_wifi_drv.c b/FW/Core/my_src/uart_wifi_drv.c new file mode 100644 index 0000000..8d1405c --- /dev/null +++ b/FW/Core/my_src/uart_wifi_drv.c @@ -0,0 +1,39 @@ +#include "HW_config.h" +#include "uart_wifi_drv.h" +#include "uart_task.h" +#include "CnCpp.h" + +unsigned int wifi_tx_is_busy(void)//1:is busy 0:no busy +{ + if(!get_uart_tx_complete_delay_flag(WIFI_UART))return 1; + + return 0; +} + +void set_wifi_tx_data(unsigned char * pdata, unsigned int len) +{ + unsigned int i = 0; + + if(len > UART_TX_BUF_MAX)return; + + uart_tx_over(WIFI_UART, pdata, len); +} + +void wifi_app_handle(void) +{ + GetWifiViaUartRx(); +} + +void uart1_rx_task(void) +{ + if(uart_info_8bit[WIFI_UART].rx_complete){ + uart_info_8bit[WIFI_UART].rx_complete = 0; + + wifi_app_handle(); + } +} + +void uart_wifi_task(void) +{ + uart1_rx_task(); +} diff --git a/FW/Core/my_src/uart_wifi_drv.h b/FW/Core/my_src/uart_wifi_drv.h new file mode 100644 index 0000000..7e67391 --- /dev/null +++ b/FW/Core/my_src/uart_wifi_drv.h @@ -0,0 +1,11 @@ +#ifndef __UART_WIFI_DRV +#define __UART_WIFI_DRV + +#define WIFI_UART 1 + +extern unsigned int wifi_tx_is_busy(void); +extern void set_wifi_tx_data(unsigned char * pdata, unsigned int len); + +extern void uart_wifi_task(void); + +#endif diff --git a/FW/Core/my_src/usb_cdc_task.c b/FW/Core/my_src/usb_cdc_task.c new file mode 100644 index 0000000..55fdf51 --- /dev/null +++ b/FW/Core/my_src/usb_cdc_task.c @@ -0,0 +1,76 @@ +#include "HW_Config.h" +#include "usbd_cdc_if.h" +#include "task.h" +#include "CnCpp.h" + +#define USB_CDC_HEAD 0xD7 +#define USB_CDC_END 0xEE + +T_usb_cdc_data_struct usb_cdc_data; + +void usccdc_config_app_handle(void); + +void usb_cdc_rx_data(unsigned char *buf, unsigned int len) +{ + unsigned int i; + + if((len < 7)||(len > USB_CDC_BUF_MAX))return; + + usb_cdc_data.rx_len = len; + for(i=0;i 0x80){ + len = usb_cdc_data.rx_buf[3]; + len<<=8; + len |= usb_cdc_data.rx_buf[2]; + len +=7; + if(len == usb_cdc_data.rx_len){ + ;//gbk + } + }else{ + if((usb_cdc_data.rx_buf[3] + 7) == usb_cdc_data.rx_len){ + usccdc_config_app_handle();//cfg + } + } + } +} + +void usb_cdc_tx(unsigned char * pdata, unsigned int len) +{ + unsigned int i = 0; + unsigned short crc_value = 0; + + for(i=0;i>8); + + usb_cdc_data.tx_buf[len+2] = USB_CDC_END; + usb_cdc_data.tx_len = len+3; + + CDC_Transmit_FS(usb_cdc_data.tx_buf, usb_cdc_data.tx_len); +} + +void usccdc_config_app_handle(void) +{ + GetCfgViaUsbCdcRx(); +} diff --git a/FW/Core/my_src/usb_cdc_task.h b/FW/Core/my_src/usb_cdc_task.h new file mode 100644 index 0000000..9fa28cf --- /dev/null +++ b/FW/Core/my_src/usb_cdc_task.h @@ -0,0 +1,9 @@ +#ifndef USB_CDC_TASK_H_ +#define USB_CDC_TASK_H_ + +extern void usb_cdc_rx_data(unsigned char *buf, unsigned int len); +extern void usb_cdc_rx_handle(void); + +extern void usb_cdc_tx(unsigned char * pdata, unsigned int len); + +#endif diff --git a/FW/Core/my_src/user_eeprom.c b/FW/Core/my_src/user_eeprom.c new file mode 100644 index 0000000..3c30da2 --- /dev/null +++ b/FW/Core/my_src/user_eeprom.c @@ -0,0 +1,27 @@ +#include "I2C_eeprom.h" +#include "user_eeprom.h" + +//Chip_CS: 0 = 512KBits, 1 = 1MBits + +unsigned int eeprom_write_byte_via_page(unsigned int chip_cs, unsigned int addr, unsigned char *pdata, unsigned int len) +{ + return I2C_byte_write_via_page(chip_cs, addr, pdata, len); +} + +unsigned int eeprom_write_page(unsigned int chip_cs, unsigned int addr, unsigned char *pdata) +{ + return I2C_page_write(chip_cs, addr, pdata); +} + +unsigned int eeprom_read_byte(unsigned int chip_cs, unsigned int addr, unsigned char *pdata, unsigned int len) +{ + return I2C_page_read(chip_cs, addr, pdata, len); +} + + + + + + + + diff --git a/FW/Core/my_src/user_eeprom.h b/FW/Core/my_src/user_eeprom.h new file mode 100644 index 0000000..7bd0fe8 --- /dev/null +++ b/FW/Core/my_src/user_eeprom.h @@ -0,0 +1,9 @@ +#ifndef USER_EEPROM_H_ +#define USER_EEPROM_H_ + +extern unsigned int eeprom_write_byte_via_page(unsigned int chip_cs, unsigned int addr, unsigned char *pdata, unsigned int len); +extern unsigned int eeprom_write_page(unsigned int chip_cs, unsigned int addr, unsigned char *pdata); +extern unsigned int eeprom_read_byte(unsigned int chip_cs, unsigned int addr, unsigned char *pdata, unsigned int len); + +#endif + diff --git a/FW/Core/my_src/user_norflash.c b/FW/Core/my_src/user_norflash.c new file mode 100644 index 0000000..aa75180 --- /dev/null +++ b/FW/Core/my_src/user_norflash.c @@ -0,0 +1,133 @@ +#include "W25Qxx.h" +#include "user_norflash.h" + +#define CHIP_SELECT_0() LL_GPIO_ResetOutputPin(GPIOC,LL_GPIO_PIN_1) +#define CHIP_SELECT_1() LL_GPIO_SetOutputPin(GPIOC,LL_GPIO_PIN_1) + +static void wait(void) +{ + __nop();__nop(); + __nop();__nop(); +} + +static void wait_50ns(void) +{ + __nop();__nop();__nop();__nop();__nop(); + __nop();__nop();__nop();__nop();__nop(); + __nop();__nop();__nop();__nop();__nop(); + __nop();__nop();__nop();__nop();__nop(); + __nop();__nop();__nop();__nop();__nop(); +} + +void nor_flash_init(void) +{ + CHIP_SELECT_0(); + wait(); + W25QXX_Init(); + CHIP_SELECT_1(); + wait(); + W25QXX_Init(); +} + +unsigned int nor_get_busy_state(unsigned int chip_cs) +{ + unsigned int state; + + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + + state = W25QXX_ReadSR(1)&0x01; + + if(state)norflash_get_busy_flag[chip_cs] = 1; + else norflash_get_busy_flag[chip_cs] = 0; + + if(norflash_err_flag[chip_cs])return 0; + + return (state); +} + +void nor_erase_full_chip(unsigned int chip_cs) +{ + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Erase_Chip_no_wait(); + wait_50ns(); +} + +void nor_erase_sector_4k(unsigned int chip_cs,unsigned int addr) +{ + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Erase_Sector_4k_no_wait(addr&0x00FFFFFF); + wait_50ns(); +} + +void nor_erase_sector_32k(unsigned int chip_cs,unsigned int addr) +{ + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Erase_Sector_32k_no_wait(addr&0x00FFFFFF); + wait_50ns(); +} + +void nor_erase_sector_64k(unsigned int chip_cs,unsigned int addr) +{ + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Erase_Sector_64k_no_wait(addr&0x00FFFFFF); + wait_50ns(); +} + +void nor_read_byte(unsigned int chip_cs,unsigned int addr,unsigned char * p_read_data,unsigned int len) +{ + if((addr+len) > NOR_FLASH_SIZE)return; + + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Read(p_read_data,addr,len); + wait_50ns(); +} + +void nor_read_page(unsigned int chip_cs,unsigned int addr,unsigned char * p_read_data) +{ + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Read(p_read_data,(addr&0x00FFFF00),256); + wait_50ns(); +} + +void nor_write_byte_via_page(unsigned int chip_cs,unsigned int addr,unsigned char * p_write_data,unsigned int len) +{ + if(((addr&0xFF) + len) > 0x100)return; + + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Write_Byte_no_wait(p_write_data,addr,len); + wait_50ns(); +} + +void nor_write_page(unsigned int chip_cs,unsigned int addr,unsigned char * p_write_data) +{ + if(chip_cs)CHIP_SELECT_1(); + else CHIP_SELECT_0(); + + wait(); + W25QXX_Write_Byte_no_wait(p_write_data,(addr&0x00FFFF00),256); + wait_50ns(); +} diff --git a/FW/Core/my_src/user_norflash.h b/FW/Core/my_src/user_norflash.h new file mode 100644 index 0000000..126c066 --- /dev/null +++ b/FW/Core/my_src/user_norflash.h @@ -0,0 +1,16 @@ +#ifndef USER_NORFLASH_H_ +#define USER_NORFLASH_H_ + +extern void nor_flash_init(void); +extern unsigned int nor_get_busy_state(unsigned int chip_cs); +extern void nor_erase_full_chip(unsigned int chip_cs); +extern void nor_erase_sector_4k(unsigned int chip_cs,unsigned int addr); +extern void nor_erase_sector_32k(unsigned int chip_cs,unsigned int addr); +extern void nor_erase_sector_64k(unsigned int chip_cs,unsigned int addr); +extern void nor_read_byte(unsigned int chip_cs,unsigned int addr,unsigned char * p_read_data,unsigned int len); +extern void nor_read_page(unsigned int chip_cs,unsigned int addr,unsigned char * p_read_data); +extern void nor_write_byte_via_page(unsigned int chip_cs,unsigned int addr,unsigned char * p_write_data,unsigned int len); +extern void nor_write_page(unsigned int chip_cs,unsigned int addr,unsigned char * p_write_data); + +#endif + diff --git a/FW/Core/my_src/w25qxx.c b/FW/Core/my_src/w25qxx.c new file mode 100644 index 0000000..51aa9d4 --- /dev/null +++ b/FW/Core/my_src/w25qxx.c @@ -0,0 +1,351 @@ +#include "w25qxx.h" + +#define GET_CHIP_SELECT() LL_GPIO_IsOutputPinSet(GPIOC,LL_GPIO_PIN_1) + +unsigned short W25QXX_TYPE = 1; + +unsigned short norflash_get_busy_flag[2] = {0,0}; +unsigned short norflash_err_flag[2] = {0,0}; + +//4Kbytes为一个Sector +//16个扇区为1个Block +//W25Q128 +//容量为16M字节,共有256个Block,4096个Sector + +static void wait(void) +{ + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); + __nop(); +} + +//初始化SPI FLASH的IO口 +void W25QXX_Init(void) +{ + W25QXX_Write_Enable(); + W25QXX_Reset(); + HAL_Delay(10); + + W25QXX_Write_Enable(); + W25QXX_Qspi_Enable(); //使能QSPI模式 + W25QXX_TYPE = W25QXX_ReadID(); //读取FLASH ID. + W25QXX_Wait_Busy(); + HAL_Delay(2); +} + +void W25QXX_Qspi_Enable(void) +{ + unsigned char stareg2; + stareg2=W25QXX_ReadSR(2); + + do{ + W25QXX_Write_Enable(); + stareg2 |= 0x02; + W25QXX_Write_SR(2,stareg2); + HAL_Delay(1); + stareg2 = W25QXX_ReadSR(2); + }while(!(stareg2 & 0x02)); +} + +void W25QXX_Qspi_Disable(void) +{ + unsigned char stareg2; + stareg2=W25QXX_ReadSR(2); + + do{ + W25QXX_Write_Enable(); + stareg2 &=~0x02; + W25QXX_Write_SR(2,stareg2); + HAL_Delay(1); + stareg2 = W25QXX_ReadSR(2); + }while(stareg2 & 0x02); +} + +unsigned char W25QXX_ReadSR(unsigned char regno) +{ + unsigned char byte=0,command=0; + + switch(regno){ + case 1: + command = W25Qx_CMD_ReadStatusReg1; //读状态寄存器1指令 + break; + case 2: + command = W25Qx_CMD_ReadStatusReg2; //读状态寄存器2指令 + break; + case 3: + command = W25Qx_CMD_ReadStatusReg3; //读状态寄存器3指令 + break; + default: + command = W25Qx_CMD_ReadStatusReg1; + break; + } + wait(); + QSPI_Send_CMD(command,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_1_LINE); + QSPI_Receive(&byte,1); + return byte; +} + +//写W25QXX状态寄存器 +void W25QXX_Write_SR(unsigned char regno,unsigned char sr) +{ + unsigned char command=0; + + switch(regno){ + case 1: + command = W25Qx_CMD_WriteStatusReg1; //写状态寄存器1指令 + break; + case 2: + command = W25Qx_CMD_WriteStatusReg2; //写状态寄存器2指令 + break; + case 3: + command = W25Qx_CMD_WriteStatusReg3; //写状态寄存器3指令 + break; + default: + command = W25Qx_CMD_WriteStatusReg1; + break; + } + QSPI_Send_CMD(command,0,0, QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_1_LINE); + QSPI_Transmit(&sr,1); +} + +void W25QXX_Write_Enable(void) +{ + unsigned char stareg1; + stareg1=W25QXX_ReadSR(1); //先读出状态寄存器1的原始值 + do{ + QSPI_Send_CMD(W25Qx_CMD_WriteEnable,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); + wait(); + stareg1 = W25QXX_ReadSR(1); + }while(!(stareg1 & 0x02)); //WE位未使能 +} + +void W25QXX_Write_Disable(void) +{ + QSPI_Send_CMD(W25Qx_CMD_WriteDisable,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); +} + +//返回值如下: +//0XEF13,表示芯片型号为W25Q80 +//0XEF14,表示芯片型号为W25Q16 +//0XEF15,表示芯片型号为W25Q32 +//0XEF16,表示芯片型号为W25Q64 +//0XEF17,表示芯片型号为W25Q128 +//0XEF18,表示芯片型号为W25Q256 +unsigned short W25QXX_ReadID(void) +{ + unsigned char temp[2]; + unsigned short deviceid; + QSPI_Send_CMD(W25Qx_CMD_ManufactDeviceID,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_1_LINE); + QSPI_Receive(temp,2); + deviceid=(temp[0]<<8)|temp[1]; + return deviceid; +} + +//读取SPI FLASH,仅支持QPI模式 +//在指定地址开始读取指定长度的数据 +//pBuffer:数据存储区 +//ReadAddr:开始读取的地址(最大32bit) +//NumByteToRead:要读取的字节数(最大65535) +void W25QXX_Read(unsigned char* pBuffer,unsigned int ReadAddr,unsigned short NumByteToRead) +{ + if((ReadAddr + NumByteToRead) > NOR_FLASH_SIZE)return; + + QSPI_Send_CMD(W25Qx_CMD_Quad_Read,ReadAddr,8,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_4_LINES); + QSPI_Receive(pBuffer,NumByteToRead); +} + +//SPI在一页(0~65535)内写入少于256个字节的数据 +//在指定地址开始写入最大256字节的数据 +//pBuffer:数据存储区 +//WriteAddr:开始写入的地址(最大32bit) +//NumByteToWrite:要写入的字节数(最大256),该数不应该超过该页的剩余字节数!!! +void W25QXX_Write_Page(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite) +{ + if((WriteAddr + NumByteToWrite) > NOR_FLASH_SIZE)return; + + W25QXX_Write_Enable(); + QSPI_Send_CMD(W25Qx_CMD_Quad_PageProgram,WriteAddr,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_4_LINES); + QSPI_Transmit(pBuffer,NumByteToWrite); + wait(); + W25QXX_Wait_Busy(); +} + +void W25QXX_Write_Byte_no_wait(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite) +{ + if(((WriteAddr&0xFF) + NumByteToWrite) > NOR_PAGE_SIZE)return; + + W25QXX_Write_Enable(); + QSPI_Send_CMD(W25Qx_CMD_Quad_PageProgram,WriteAddr,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_4_LINES); + QSPI_Transmit(pBuffer,NumByteToWrite); + wait(); +} + +//无检验写SPI FLASH +//必须确保所写的地址范围内的数据全部为0XFF,否则在非0XFF处写入的数据将失败! +//具有自动换页功能 +//在指定地址开始写入指定长度的数据,但是要确保地址不越界! +//pBuffer:数据存储区 +//WriteAddr:开始写入的地址(最大32bit) +//NumByteToWrite:要写入的字节数(最大65535) +//CHECK OK +void W25QXX_Write_NoCheck(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite) +{ + unsigned short pageremain; + + if((WriteAddr + NumByteToWrite) > NOR_FLASH_SIZE)return; + + pageremain=256-WriteAddr%256; //单页剩余的字节数 + if(NumByteToWrite<=pageremain)pageremain=NumByteToWrite;//不大于256个字节 + + while(1){ + W25QXX_Write_Page(pBuffer,WriteAddr,pageremain); + + if(NumByteToWrite==pageremain)break;//写入结束了 + else //NumByteToWrite>pageremain + { + pBuffer+=pageremain; + WriteAddr+=pageremain; + + NumByteToWrite-=pageremain; //减去已经写入了的字节数 + if(NumByteToWrite>256)pageremain=256; //一次可以写入256个字节 + else pageremain=NumByteToWrite; //不够256个字节了 + } + } +} + +//写SPI FLASH +//在指定地址开始写入指定长度的数据 +//该函数带擦除操作! +//pBuffer:数据存储区 +//WriteAddr:开始写入的地址(最大32bit) +//NumByteToWrite:要写入的字节数(最大65535) +unsigned char W25QXX_BUFFER[4096]; +void W25QXX_Write(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite) +{ + unsigned int secpos; + unsigned short secoff; + unsigned short secremain; + unsigned short i; + unsigned char * W25QXX_BUF; + + if((WriteAddr + NumByteToWrite) > NOR_FLASH_SIZE)return; + + W25QXX_BUF=W25QXX_BUFFER; + secpos=WriteAddr/4096;//扇区地址 + secoff=WriteAddr%4096;//在扇区内的偏移 + secremain=4096-secoff;//扇区剩余空间大小 + //printf("ad:%X,nb:%X\r\n",WriteAddr,NumByteToWrite);//测试用 + if(NumByteToWrite<=secremain)secremain=NumByteToWrite;//不大于4096个字节 + + while(1){ + W25QXX_Read(W25QXX_BUF,secpos*4096,4096);//读出整个扇区的内容 + for(i=0;i4096)secremain=4096; //下一个扇区还是写不完 + else secremain=NumByteToWrite; //下一个扇区可以写完了 + } + } +} + +//擦除整个芯片 +//等待时间超长... +void W25QXX_Erase_Chip(void) +{ + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25Qx_CMD_ChipErase,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); + HAL_Delay(100); + W25QXX_Wait_Busy(); +} + +void W25QXX_Erase_Chip_no_wait(void) +{ + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25Qx_CMD_ChipErase,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); + __nop(); +} + +//擦除一个扇区 +//Dst_Addr:扇区地址 根据实际容量设置 +//擦除一个扇区的最少时间:150ms +void W25QXX_Erase_Sector(unsigned int addr) +{ + unsigned int addr_sector = addr & 0x00FFF000; + + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25Qx_CMD_SectorErase_4K,addr_sector,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_NONE); + HAL_Delay(5); + W25QXX_Wait_Busy(); +} + +void W25QXX_Erase_Sector_4k_no_wait(unsigned int addr) +{ + unsigned int addr_sector = addr & 0x00FFF000; + + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25Qx_CMD_SectorErase_4K,addr_sector,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_NONE); + __nop(); +} + +void W25QXX_Erase_Sector_32k_no_wait(unsigned int addr) +{ + unsigned int addr_sector = addr & 0x00FF8000; + + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25Qx_CMD_SectorErase_32K,addr_sector,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_NONE); + __nop(); +} + +void W25QXX_Erase_Sector_64k_no_wait(unsigned int addr) +{ + unsigned int addr_sector = addr & 0x00FF0000; + + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25Qx_CMD_SectorErase_64K,addr_sector,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_NONE); + __nop(); +} + +//等待空闲 +void W25QXX_Wait_Busy(void) +{ + while((W25QXX_ReadSR(1)&0x01)==0x01){ + LL_IWDG_ReloadCounter(IWDG1); // 等待BUSY位清空 + + norflash_get_busy_flag[GET_CHIP_SELECT()] = 1; + if(norflash_err_flag[GET_CHIP_SELECT()])return; + + wait(); + } + norflash_get_busy_flag[GET_CHIP_SELECT()] = 0; +} + +void W25QXX_Reset(void) +{ + QSPI_Send_CMD(W25Qx_CMD_Reset_Enble,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); + QSPI_Send_CMD(W25Qx_CMD_Reset_Memory,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); +} diff --git a/FW/Core/my_src/w25qxx.h b/FW/Core/my_src/w25qxx.h new file mode 100644 index 0000000..35e6a2a --- /dev/null +++ b/FW/Core/my_src/w25qxx.h @@ -0,0 +1,100 @@ +#ifndef __W25QXX_H +#define __W25QXX_H + +#include "main.h" + +//W25X系列/Q系列芯片列表 ID码 +#define W25Q80 0xEF13 +#define W25Q16 0xEF14 +#define W25Q32 0xEF15 +#define W25Q64 0xEF16 +#define W25Q128 0xEF17 +#define W25Q256 0xEF18 + +#define W25Q128_FLASH_SIZE 0x01000000 +#define W25Q128_ADDR_BIT_NUM 24 + +#define NOR_FLASH_SIZE W25Q128_FLASH_SIZE +#define NOR_PAGE_SIZE 0x100 + +extern unsigned short W25QXX_TYPE; //定义W25QXX芯片型号 + +////////////////////////////////////////////////////////////////////////////////// +//指令表 +#define W25Qx_CMD_Reset_Enble 0x66 +#define W25Qx_CMD_Reset_Memory 0x99 + +#define W25Qx_CMD_ManufactDeviceID 0x90 + +#define W25Qx_CMD_ReadStatusReg1 0x05 +#define W25Qx_CMD_ReadStatusReg2 0x35 +#define W25Qx_CMD_ReadStatusReg3 0x15 +#define W25Qx_CMD_WriteStatusReg1 0x01 +#define W25Qx_CMD_WriteStatusReg2 0x31 +#define W25Qx_CMD_WriteStatusReg3 0x11 + +#define W25Qx_CMD_WriteEnable 0x06 +#define W25Qx_CMD_WriteDisable 0x04 + +#define W25Qx_CMD_ChipErase 0x60 +#define W25Qx_CMD_SectorErase_4K 0x20 +#define W25Qx_CMD_SectorErase_32K 0x52 +#define W25Qx_CMD_SectorErase_64K 0xD8 +#define W25Qx_CMD_Quad_PageProgram 0x32 +#define W25Qx_CMD_Quad_Read 0x6B + +/* +#define W25X_WriteEnable 0x06 +#define W25X_WriteDisable 0x04 + +#define W25X_ReadStatusReg1 0x05 +#define W25X_ReadStatusReg2 0x35 +#define W25X_ReadStatusReg3 0x15 +#define W25X_WriteStatusReg1 0x01 +#define W25X_WriteStatusReg2 0x31 +#define W25X_WriteStatusReg3 0x11 + +#define W25X_ReadData 0x03 +#define W25X_FastReadData 0x0B +#define W25X_FastReadDual 0x3B +#define W25X_FastReadQuad 0x6B +#define W25X_PageProgram 0x32 +#define W25X_BlockErase 0xD8 +#define W25X_SectorErase 0x20 +#define W25X_ChipErase 0x60 +#define W25X_PowerDown 0xB9 +#define W25X_ReleasePowerDown 0xAB +#define W25X_DeviceID 0xAB +#define W25X_ManufactDeviceID 0x90 +#define W25X_JedecDeviceID 0x9F +#define W25X_Enable4ByteAddr 0xB7 +#define W25X_Exit4ByteAddr 0xE9 +#define W25X_EnterQPIMode 0x38 +#define W25X_ExitQPIMode 0xFF +*/ + +extern unsigned short norflash_get_busy_flag[2]; +extern unsigned short norflash_err_flag[2]; + +extern void W25QXX_Init(void); +extern void W25QXX_Qspi_Enable(void); +extern void W25QXX_Qspi_Disable(void); +extern unsigned short W25QXX_ReadID(void); +extern unsigned char W25QXX_ReadSR(unsigned char regno); +extern void W25QXX_Write_SR(unsigned char regno,unsigned char sr); +extern void W25QXX_Write_Enable(void); +extern void W25QXX_Write_Disable(void); +extern void W25QXX_Write_NoCheck(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite);//写flash,不校验 +extern void W25QXX_Read(unsigned char* pBuffer,unsigned int ReadAddr,unsigned short NumByteToRead); +extern void W25QXX_Write(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite); +extern void W25QXX_Write_Byte_no_wait(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite); +extern void W25QXX_Erase_Chip(void); +extern void W25QXX_Erase_Chip_no_wait(void); +extern void W25QXX_Erase_Sector(unsigned int addr); +extern void W25QXX_Erase_Sector_4k_no_wait(unsigned int addr); +extern void W25QXX_Erase_Sector_32k_no_wait(unsigned int addr); +extern void W25QXX_Erase_Sector_64k_no_wait(unsigned int addr); +extern void W25QXX_Wait_Busy(void); +extern void W25QXX_Reset(void); + +#endif diff --git a/FW/Core/my_src/w25qxx_qspi.c b/FW/Core/my_src/w25qxx_qspi.c new file mode 100644 index 0000000..f350598 --- /dev/null +++ b/FW/Core/my_src/w25qxx_qspi.c @@ -0,0 +1,365 @@ +#include "quadspi.h" +#include "w25qxx_qspi.h" + +/** + * @brief This function send a Write Enable and wait it is effective. + * @param hqspi: QSPI handle + * @retval None + */ +static void QSPI_WriteEnable(void) +{ + QSPI_CommandTypeDef sCommand; + QSPI_AutoPollingTypeDef sConfig; + + /* Enable write operations ------------------------------------------ */ + sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; + sCommand.Instruction = WRITE_ENABLE_CMD; + sCommand.AddressMode = QSPI_ADDRESS_NONE; + sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + sCommand.DataMode = QSPI_DATA_NONE; + sCommand.DummyCycles = 0; + sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; + sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + if (HAL_QSPI_Command(&hqspi, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + Error_Handler(); + } + + /* Configure automatic polling mode to wait for write enabling ---- */ + sConfig.Match = 0x02; + sConfig.Mask = 0x02; + sConfig.MatchMode = QSPI_MATCH_MODE_AND; + sConfig.StatusBytesSize = 1; + sConfig.Interval = 0x10; + sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + sCommand.Instruction = READ_STATUS_REG1_CMD; + sCommand.DataMode = QSPI_DATA_1_LINE; + + if (HAL_QSPI_AutoPolling(&hqspi, &sCommand, &sConfig, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + Error_Handler(); + } +} + +static void QSPI_WriteDisable(void) +{ + QSPI_CommandTypeDef sCommand; + QSPI_AutoPollingTypeDef sConfig; + + /* Enable write operations ------------------------------------------ */ + sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; + sCommand.Instruction = WRITE_DISABLE_CMD; + sCommand.AddressMode = QSPI_ADDRESS_NONE; + sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + sCommand.DataMode = QSPI_DATA_NONE; + sCommand.DummyCycles = 0; + sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; + sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + if (HAL_QSPI_Command(&hqspi, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + Error_Handler(); + } + + /* Configure automatic polling mode to wait for write enabling ---- */ + sConfig.Match = 0x00; + sConfig.Mask = 0x02; + sConfig.MatchMode = QSPI_MATCH_MODE_AND; + sConfig.StatusBytesSize = 1; + sConfig.Interval = 0x10; + sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + sCommand.Instruction = READ_STATUS_REG1_CMD; + sCommand.DataMode = QSPI_DATA_1_LINE; + + if (HAL_QSPI_AutoPolling(&hqspi, &sCommand, &sConfig, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + Error_Handler(); + } +} + +void QSPI_AutoPollingMemReady(void)//SR1 ready +{ + QSPI_CommandTypeDef sCommand; + QSPI_AutoPollingTypeDef sConfig; + + /* Configure automatic polling mode to wait for memory ready ------ */ + sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE; + sCommand.Instruction = READ_STATUS_REG1_CMD; + sCommand.AddressMode = QSPI_ADDRESS_NONE; + sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + sCommand.DataMode = QSPI_DATA_1_LINE; + sCommand.DummyCycles = 0; + sCommand.DdrMode = QSPI_DDR_MODE_DISABLE; + sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + sConfig.Match = 0x00; + sConfig.Mask = 0x01; + sConfig.MatchMode = QSPI_MATCH_MODE_AND; + sConfig.StatusBytesSize = 1; + sConfig.Interval = 0x10; + sConfig.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + if (HAL_QSPI_AutoPolling_IT(&hqspi, &sCommand, &sConfig) != HAL_OK) + { + Error_Handler(); + } +} + +static unsigned char QSPI_Read_SR(unsigned char sr) +{ + unsigned char cmd; + unsigned char byte = 0xF1; + + if(2 == sr)cmd = READ_STATUS_REG2_CMD; + else if(3 == sr)cmd = READ_STATUS_REG3_CMD; + else cmd = READ_STATUS_REG1_CMD; + + QSPI_Send_CMD(cmd,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); + QSPI_Transmit(&byte,1); + return byte; +} + +static void QSPI_Write_SR(unsigned char sr, unsigned char val) +{ + unsigned char cmd; + + if(2 == sr)cmd = WRITE_STATUS_REG2_CMD; + else if(3 == sr)cmd = WRITE_STATUS_REG3_CMD; + else cmd = WRITE_STATUS_REG1_CMD; + + QSPI_Send_CMD(cmd,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); + QSPI_Transmit(&val,1); +} + +void w25qxx_write_enable(void) +{ + QSPI_WriteEnable(); +} + +void w25qxx_write_disable(void) +{ + QSPI_WriteDisable(); +} + +void w25qxx_reset(void) +{ + QSPI_Send_CMD(RESET_ENABLE_CMD,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); + QSPI_Send_CMD(RESET_MEMORY_CMD,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE); +} + +void w25qxx_wait_ready(void) +{ + QSPI_AutoPollingMemReady(); +} + +void w25qxx_qspi_enable(void) +{ + unsigned char reg; + + reg = QSPI_Read_SR(2); + + if(!(reg & 0x02)){ + QSPI_Write_SR(2, (reg | 0x02)); + } +} + +void w25qxx_qspi_disable(void) +{ + unsigned char reg; + + reg = QSPI_Read_SR(2); + + if(reg & 0x02){ + QSPI_Write_SR(2, (reg & (~0x02))); + } +} + +void w25qxx_qspi_setup(void) +{ + unsigned char temp; + + w25qxx_write_enable(); + w25qxx_reset(); + HAL_Delay(5); + + w25qxx_write_enable(); + w25qxx_wait_ready(); + + while(!(QSPI_Read_SR(2) & 0x02)) + { + w25qxx_qspi_enable(); + HAL_Delay(5); + } +} + +unsigned short w25qxx_qspi_read_id(void) +{ + unsigned char temp[2]; + unsigned short deviceid; + + QSPI_Send_CMD(READ_ID_CMD,0,0,QSPI_INSTRUCTION_1_LINE,QSPI_ADDRESS_1_LINE,QSPI_ADDRESS_24_BITS,QSPI_DATA_1_LINE);//QPI,读id,地址为0,4线传输数据_24位地址_4线传输地址_4线传输指令,无空周期,2个字节数据 + QSPI_Receive(temp,2); + deviceid=(temp[0]<<8)|temp[1]; + + return deviceid; +} + +/* +//返回值如下: +//0XEF13,表示芯片型号为W25Q80 +//0XEF14,表示芯片型号为W25Q16 +//0XEF15,表示芯片型号为W25Q32 +//0XEF16,表示芯片型号为W25Q64 +//0XEF17,表示芯片型号为W25Q128 +//0XEF18,表示芯片型号为W25Q256 +unsigned short W25QXX_ReadID(void) +{ + unsigned char temp[2]; + unsigned short deviceid; + QSPI_Send_CMD(W25X_ManufactDeviceID,0,0,QSPI_INSTRUCTION_4_LINES,QSPI_ADDRESS_4_LINES,QSPI_ADDRESS_24_BITS,QSPI_DATA_4_LINES);//QPI,读id,地址为0,4线传输数据_24位地址_4线传输地址_4线传输指令,无空周期,2个字节数据 + QSPI_Receive(temp,2); + deviceid=(temp[0]<<8)|temp[1]; + return deviceid; +} + +//读取SPI FLASH,仅支持QPI模式 +//在指定地址开始读取指定长度的数据 +//pBuffer:数据存储区 +//ReadAddr:开始读取的地址(最大32bit) +//NumByteToRead:要读取的字节数(最大65535) +void W25QXX_Read(unsigned char* pBuffer,unsigned int ReadAddr,unsigned short NumByteToRead) +{ + QSPI_Send_CMD(W25X_FastReadData,ReadAddr,8,QSPI_INSTRUCTION_4_LINES,QSPI_ADDRESS_4_LINES,QSPI_ADDRESS_32_BITS,QSPI_DATA_4_LINES); //QPI,快速读数据,地址为ReadAddr,4线传输数据_32位地址_4线传输地址_4线传输指令,8空周期,NumByteToRead个数据 + QSPI_Receive(pBuffer,NumByteToRead); +} + +//SPI在一页(0~65535)内写入少于256个字节的数据 +//在指定地址开始写入最大256字节的数据 +//pBuffer:数据存储区 +//WriteAddr:开始写入的地址(最大32bit) +//NumByteToWrite:要写入的字节数(最大256),该数不应该超过该页的剩余字节数!!! +void W25QXX_Write_Page(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite) +{ + W25QXX_Write_Enable(); //写使能 + QSPI_Send_CMD(W25X_PageProgram,WriteAddr,0,QSPI_INSTRUCTION_4_LINES,QSPI_ADDRESS_4_LINES,QSPI_ADDRESS_32_BITS,QSPI_DATA_4_LINES); //QPI,页写指令,地址为WriteAddr,4线传输数据_32位地址_4线传输地址_4线传输指令,无空周期,NumByteToWrite个数据 + QSPI_Transmit(pBuffer,NumByteToWrite); + W25QXX_Wait_Busy(); //等待写入结束 +} + +//无检验写SPI FLASH +//必须确保所写的地址范围内的数据全部为0XFF,否则在非0XFF处写入的数据将失败! +//具有自动换页功能 +//在指定地址开始写入指定长度的数据,但是要确保地址不越界! +//pBuffer:数据存储区 +//WriteAddr:开始写入的地址(最大32bit) +//NumByteToWrite:要写入的字节数(最大65535) +//CHECK OK +void W25QXX_Write_NoCheck(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite) +{ + unsigned short pageremain; + pageremain=256-WriteAddr%256; //单页剩余的字节数 + if(NumByteToWrite<=pageremain)pageremain=NumByteToWrite;//不大于256个字节 + while(1) + { + W25QXX_Write_Page(pBuffer,WriteAddr,pageremain); + if(NumByteToWrite==pageremain)break;//写入结束了 + else //NumByteToWrite>pageremain + { + pBuffer+=pageremain; + WriteAddr+=pageremain; + + NumByteToWrite-=pageremain; //减去已经写入了的字节数 + if(NumByteToWrite>256)pageremain=256; //一次可以写入256个字节 + else pageremain=NumByteToWrite; //不够256个字节了 + } + } +} + +//写SPI FLASH +//在指定地址开始写入指定长度的数据 +//该函数带擦除操作! +//pBuffer:数据存储区 +//WriteAddr:开始写入的地址(最大32bit) +//NumByteToWrite:要写入的字节数(最大65535) +unsigned char W25QXX_BUFFER[4096]; +void W25QXX_Write(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite) +{ + unsigned int secpos; + unsigned short secoff; + unsigned short secremain; + unsigned short i; + unsigned char * W25QXX_BUF; + W25QXX_BUF=W25QXX_BUFFER; + secpos=WriteAddr/4096;//扇区地址 + secoff=WriteAddr%4096;//在扇区内的偏移 + secremain=4096-secoff;//扇区剩余空间大小 + //printf("ad:%X,nb:%X\r\n",WriteAddr,NumByteToWrite);//测试用 + if(NumByteToWrite<=secremain)secremain=NumByteToWrite;//不大于4096个字节 + while(1) + { + W25QXX_Read(W25QXX_BUF,secpos*4096,4096);//读出整个扇区的内容 + for(i=0;i4096)secremain=4096; //下一个扇区还是写不完 + else secremain=NumByteToWrite; //下一个扇区可以写完了 + } + }; +} + +//擦除整个芯片 +//等待时间超长... +void W25QXX_Erase_Chip(void) +{ + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25X_ChipErase,0,0,QSPI_INSTRUCTION_4_LINES,QSPI_ADDRESS_NONE,QSPI_ADDRESS_8_BITS,QSPI_DATA_NONE);//QPI,写全片擦除指令,地址为0,无数据_8位地址_无地址_4线传输指令,无空周期,0个字节数据 + W25QXX_Wait_Busy(); //等待芯片擦除结束 +} + +//擦除一个扇区 +//Dst_Addr:扇区地址 根据实际容量设置 +//擦除一个扇区的最少时间:150ms +void W25QXX_Erase_Sector(unsigned int Dst_Addr) +{ + + //printf("fe:%x\r\n",Dst_Addr); //监视falsh擦除情况,测试用 + Dst_Addr*=4096; + W25QXX_Write_Enable(); //SET WEL + W25QXX_Wait_Busy(); + QSPI_Send_CMD(W25X_SectorErase,Dst_Addr,0,QSPI_INSTRUCTION_4_LINES,QSPI_ADDRESS_4_LINES,QSPI_ADDRESS_32_BITS,QSPI_DATA_NONE);//QPI,写扇区擦除指令,地址为0,无数据_32位地址_4线传输地址_4线传输指令,无空周期,0个字节数据 + W25QXX_Wait_Busy(); //等待擦除完成 +} + +//等待空闲 +void W25QXX_Wait_Busy(void) +{ + while((W25QXX_ReadSR(1)&0x01)==0x01); // 等待BUSY位清空 +} +*/ diff --git a/FW/Core/my_src/w25qxx_qspi.h b/FW/Core/my_src/w25qxx_qspi.h new file mode 100644 index 0000000..8198f3d --- /dev/null +++ b/FW/Core/my_src/w25qxx_qspi.h @@ -0,0 +1,175 @@ +#ifndef __W25QXX_QSPI_H +#define __W25QXX_QSPI_H + +/* Definition for QSPI clock resources */ +#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE() +#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE() +#define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() +#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() +#define QSPI_BK1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() +#define QSPI_BK1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() +#define QSPI_BK1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() +#define QSPI_BK1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() + +#define QSPI_MDMA_CLK_ENABLE() __HAL_RCC_MDMA_CLK_ENABLE() + +#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET() +#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET() + +/* Definition for QSPI Pins */ +#define QSPI_CS_PIN GPIO_PIN_6 +#define QSPI_CS_GPIO_PORT GPIOG +#define QSPI_CLK_PIN GPIO_PIN_2 +#define QSPI_CLK_GPIO_PORT GPIOB +#define QSPI_BK1_D0_PIN GPIO_PIN_8 +#define QSPI_BK1_D0_GPIO_PORT GPIOF +#define QSPI_BK1_D1_PIN GPIO_PIN_9 +#define QSPI_BK1_D1_GPIO_PORT GPIOF +#define QSPI_BK1_D2_PIN GPIO_PIN_7 +#define QSPI_BK1_D2_GPIO_PORT GPIOF +#define QSPI_BK1_D3_PIN GPIO_PIN_6 +#define QSPI_BK1_D3_GPIO_PORT GPIOF + + +/* MT25TL01GHBA8ESF Micron memory */ +/* Size of the flash */ +#define QSPI_FLASH_SIZE 25 +#define QSPI_PAGE_SIZE 256 + +/* Reset Operations */ +#define RESET_ENABLE_CMD 0x66 +#define RESET_MEMORY_CMD 0x99 + +/* Identification Operations */ +#define READ_ID_CMD 0x90 +#define READ_ID_CMD2 0x9F +#define MULTIPLE_IO_READ_ID_CMD 0xAF +#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A + +/* Read Operations */ +#define READ_CMD 0x03 +#define READ_4_BYTE_ADDR_CMD 0x13 + +#define FAST_READ_CMD 0x0B +#define FAST_READ_DTR_CMD 0x0D +#define FAST_READ_4_BYTE_ADDR_CMD 0x0C + +#define DUAL_OUT_FAST_READ_CMD 0x3B +#define DUAL_OUT_FAST_READ_DTR_CMD 0x3D +#define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C + +#define DUAL_INOUT_FAST_READ_CMD 0xBB +#define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD +#define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC + +#define QUAD_OUT_FAST_READ_CMD 0x6B +#define QUAD_OUT_FAST_READ_DTR_CMD 0x6D +#define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C + +#define QUAD_INOUT_FAST_READ_CMD 0xEB +#define QUAD_INOUT_FAST_READ_DTR_CMD 0xED +#define QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xEC + +/* Write Operations */ +#define WRITE_ENABLE_CMD 0x06 +#define WRITE_DISABLE_CMD 0x04 + +/* Register Operations */ +#define READ_STATUS_REG1_CMD 0x05 +#define WRITE_STATUS_REG1_CMD 0x01 + +#define READ_STATUS_REG2_CMD 0x35 +#define WRITE_STATUS_REG2_CMD 0x31 + +#define READ_STATUS_REG3_CMD 0x15 +#define WRITE_STATUS_REG3_CMD 0x11 + +#define READ_LOCK_REG_CMD 0xE8 +#define WRITE_LOCK_REG_CMD 0xE5 + +#define READ_FLAG_STATUS_REG_CMD 0x70 +#define CLEAR_FLAG_STATUS_REG_CMD 0x50 + +#define READ_NONVOL_CFG_REG_CMD 0xB5 +#define WRITE_NONVOL_CFG_REG_CMD 0xB1 + +#define READ_VOL_CFG_REG_CMD 0x85 +#define WRITE_VOL_CFG_REG_CMD 0x81 + +#define READ_ENHANCED_VOL_CFG_REG_CMD 0x65 +#define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61 + +#define READ_EXT_ADDR_REG_CMD 0xC8 +#define WRITE_EXT_ADDR_REG_CMD 0xC5 + +/* Program Operations */ +#define PAGE_PROG_CMD 0x02 +#define PAGE_PROG_4_BYTE_ADDR_CMD 0x12 + +#define DUAL_IN_FAST_PROG_CMD 0xA2 +#define EXT_DUAL_IN_FAST_PROG_CMD 0xD2 + +#define QUAD_IN_FAST_PROG_CMD 0x32 +#define EXT_QUAD_IN_FAST_PROG_CMD 0x12 /*0x38*/ +#define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x34 + +/* Erase Operations */ +#define SUBSECTOR_ERASE_CMD 0x20 +#define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 + +#define SECTOR_ERASE_CMD 0xD8 +#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC + +#define BULK_ERASE_CMD 0xC7 + +#define PROG_ERASE_RESUME_CMD 0x7A +#define PROG_ERASE_SUSPEND_CMD 0x75 + +/* One-Time Programmable Operations */ +#define READ_OTP_ARRAY_CMD 0x4B +#define PROG_OTP_ARRAY_CMD 0x42 + +/* 4-byte Address Mode Operations */ +#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7 +#define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9 + +/* Quad Operations */ +#define ENTER_QUAD_CMD 0x35 +#define EXIT_QUAD_CMD 0xF5 + +/* Default dummy clocks cycles */ +#define DUMMY_CLOCK_CYCLES_READ 8 +#define DUMMY_CLOCK_CYCLES_READ_QUAD 8 + +#define DUMMY_CLOCK_CYCLES_READ_DTR 6 +#define DUMMY_CLOCK_CYCLES_READ_QUAD_DTR 8 + +/* End address of the QSPI memory */ +#define QSPI_END_ADDR (1 << QSPI_FLASH_SIZE) + +/* Size of buffers */ +#define BUFFERSIZE (COUNTOF(aTxBuffer) - 1) + +/* Exported macro ------------------------------------------------------------*/ +#define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__))) + +/* Exported functions ------------------------------------------------------- */ +extern void w25qxx_qspi_setup(void); +extern unsigned short w25qxx_qspi_read_id(void); + +void W25QXX_Init(void); +void W25QXX_Qspi_Enable(void); +void W25QXX_Qspi_Disable(void); +unsigned short W25QXX_ReadID(void); +unsigned char W25QXX_ReadSR(unsigned char regno); +void W25QXX_Write_SR(unsigned char regno,unsigned char sr); +void W25QXX_Write_Enable(void); +void W25QXX_Write_Disable(void); +void W25QXX_Write_NoCheck(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite);//写flash,不校验 +void W25QXX_Read(unsigned char* pBuffer,unsigned int ReadAddr,unsigned short NumByteToRead); +void W25QXX_Write(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite); +void W25QXX_Erase_Chip(void); +void W25QXX_Erase_Sector(unsigned int addr); +void W25QXX_Wait_Busy(void); + +#endif diff --git a/FW/Drivers/CMSIS/Core/Include/cmsis_armcc.h b/FW/Drivers/CMSIS/Core/Include/cmsis_armcc.h new file mode 100644 index 0000000..59f173a --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/FW/Drivers/CMSIS/Core/Include/cmsis_armclang.h b/FW/Drivers/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000..e917f35 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/FW/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h b/FW/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..feec324 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/FW/Drivers/CMSIS/Core/Include/cmsis_compiler.h b/FW/Drivers/CMSIS/Core/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/FW/Drivers/CMSIS/Core/Include/cmsis_gcc.h b/FW/Drivers/CMSIS/Core/Include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/FW/Drivers/CMSIS/Core/Include/cmsis_iccarm.h b/FW/Drivers/CMSIS/Core/Include/cmsis_iccarm.h new file mode 100644 index 0000000..12d68fd --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/FW/Drivers/CMSIS/Core/Include/cmsis_version.h b/FW/Drivers/CMSIS/Core/Include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/FW/Drivers/CMSIS/Core/Include/core_armv81mml.h b/FW/Drivers/CMSIS/Core/Include/core_armv81mml.h new file mode 100644 index 0000000..8441e57 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_armv8mbl.h b/FW/Drivers/CMSIS/Core/Include/core_armv8mbl.h new file mode 100644 index 0000000..344dca5 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_armv8mml.h b/FW/Drivers/CMSIS/Core/Include/core_armv8mml.h new file mode 100644 index 0000000..5ddb8ae --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm0.h b/FW/Drivers/CMSIS/Core/Include/core_cm0.h new file mode 100644 index 0000000..cafae5a --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm0plus.h b/FW/Drivers/CMSIS/Core/Include/core_cm0plus.h new file mode 100644 index 0000000..d104965 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm1.h b/FW/Drivers/CMSIS/Core/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm23.h b/FW/Drivers/CMSIS/Core/Include/core_cm23.h new file mode 100644 index 0000000..b79c6af --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm3.h b/FW/Drivers/CMSIS/Core/Include/core_cm3.h new file mode 100644 index 0000000..8157ca7 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm33.h b/FW/Drivers/CMSIS/Core/Include/core_cm33.h new file mode 100644 index 0000000..7fed59a --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm35p.h b/FW/Drivers/CMSIS/Core/Include/core_cm35p.h new file mode 100644 index 0000000..5579c82 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm4.h b/FW/Drivers/CMSIS/Core/Include/core_cm4.h new file mode 100644 index 0000000..12c023b --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_cm7.h b/FW/Drivers/CMSIS/Core/Include/core_cm7.h new file mode 100644 index 0000000..c4515d8 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_sc000.h b/FW/Drivers/CMSIS/Core/Include/core_sc000.h new file mode 100644 index 0000000..cf92577 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/core_sc300.h b/FW/Drivers/CMSIS/Core/Include/core_sc300.h new file mode 100644 index 0000000..40f3af8 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core/Include/mpu_armv7.h b/FW/Drivers/CMSIS/Core/Include/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/FW/Drivers/CMSIS/Core/Include/mpu_armv8.h b/FW/Drivers/CMSIS/Core/Include/mpu_armv8.h new file mode 100644 index 0000000..0041d4d --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/FW/Drivers/CMSIS/Core/Include/tz_context.h b/FW/Drivers/CMSIS/Core/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/FW/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c b/FW/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c new file mode 100644 index 0000000..273607b --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c @@ -0,0 +1,58 @@ +/****************************************************************************** + * @file main_s.c + * @brief Code template for secure main function + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Use CMSE intrinsics */ +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/FW/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c b/FW/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c new file mode 100644 index 0000000..e2e8294 --- /dev/null +++ b/FW/Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c @@ -0,0 +1,200 @@ +/****************************************************************************** + * @file tz_context.c + * @brief Context Management for Armv8-M TrustZone - Sample implementation + * @version V1.1.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2016-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/FW/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h b/FW/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h new file mode 100644 index 0000000..ec17393 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/cmsis_armcc.h @@ -0,0 +1,547 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.3 + * @date 15. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1)) + #define __ARM_ARCH_7A__ 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __wfi + +/** + \brief Wait For Event + */ +#define __WFE __wfe + +/** + \brief Send Event + */ +#define __SEV __sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + +/** + \brief Rotate Right in unsigned value (32 bit) + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR (Floating Point Status/Control) + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + +/** + \brief Set FPSCR (Floating Point Status/Control) + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +/** \brief Get CPSR (Current Program Status Register) + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +/** \brief Set CPSR (Current Program Status Register) + \param [in] cpsr CPSR value to set + */ +__STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + register uint32_t __regCPSR __ASM("cpsr"); + __regCPSR = cpsr; +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_INLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_INLINE __ASM void __set_mode(uint32_t mode) +{ + MOV r1, lr + MSR CPSR_C, r0 + BX r1 +} + +/** \brief Get Stack Pointer + \return Stack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP(void) +{ + MOV r0, sp + BX lr +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP(uint32_t stack) +{ + MOV sp, r0 + BX lr +} + + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYSStack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV R0, SP + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) +{ + ARM + PRESERVE8 + + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/** \brief Get FPEXC (Floating Point Exception Control Register) + \return Floating Point Exception Control Register value + */ +__STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + return(__regfpexc); +#else + return(0); +#endif +} + +/** \brief Set FPEXC (Floating Point Exception Control Register) + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + __regfpexc = (fpexc); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0) +#define __get_CP64(cp, op1, Rt, CRm) \ + do { \ + uint32_t ltmp, htmp; \ + __ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + (Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \ + } while(0) + +#define __set_CP64(cp, op1, Rt, CRm) \ + do { \ + const uint64_t tmp = (Rt); \ + const uint32_t ltmp = (uint32_t)(tmp); \ + const uint32_t htmp = (uint32_t)(tmp >> 32U); \ + __ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \ + } while(0) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE __ASM void __FPU_Enable(void) +{ + ARM + + //Permit access to VFP/NEON, registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + ISB + + //Enable VFP/NEON + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP/NEON registers to 0 + MOV R2,#0 + + //Initialise D16 registers to 0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + //Initialise D32 registers to 0 + VMOV D16,R2,R2 + VMOV D17,R2,R2 + VMOV D18,R2,R2 + VMOV D19,R2,R2 + VMOV D20,R2,R2 + VMOV D21,R2,R2 + VMOV D22,R2,R2 + VMOV D23,R2,R2 + VMOV D24,R2,R2 + VMOV D25,R2,R2 + VMOV D26,R2,R2 + VMOV D27,R2,R2 + VMOV D28,R2,R2 + VMOV D29,R2,R2 + VMOV D30,R2,R2 + VMOV D31,R2,R2 + ENDIF + + //Initialise FPSCR to a known state + VMRS R1,FPSCR + LDR R2,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R1,R1,R2 + VMSR FPSCR,R1 + + BX LR +} + +#endif /* __CMSIS_ARMCC_H */ diff --git a/FW/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h b/FW/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h new file mode 100644 index 0000000..0a53c4e --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h @@ -0,0 +1,585 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.1.1 + * @date 15. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + */ +#define __WFI __builtin_arm_wfi + +/** + \brief Wait For Event + */ +#define __WFE __builtin_arm_wfe + +/** + \brief Send Event + */ +#define __SEV __builtin_arm_sev + +/** + \brief Instruction Synchronization Barrier + */ +#define __ISB() do {\ + __schedule_barrier();\ + __builtin_arm_isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + */ +#define __DSB() do {\ + __schedule_barrier();\ + __builtin_arm_dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + */ +#define __DMB() do {\ + __schedule_barrier();\ + __builtin_arm_dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __QADD8 __builtin_arm_qadd8 +#define __QSUB8 __builtin_arm_qsub8 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __SXTB16 __builtin_arm_sxtb16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSDX __builtin_arm_smlsdx + + + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP() +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr() +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : : "memory" + ); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %0 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory" + ); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if __ARM_NEON == 1 + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/FW/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h b/FW/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h new file mode 100644 index 0000000..dfd07a2 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h @@ -0,0 +1,213 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.2 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/FW/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h b/FW/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h new file mode 100644 index 0000000..891bec2 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h @@ -0,0 +1,514 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] mvbar Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar) +{ + __set_CP(15, 0, mvbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CCSIDR + \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead. + */ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ + __set_CSSELR(value); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory") + __set_CP(15, 0, value, 7, 14, 2); +} + +#endif diff --git a/FW/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h b/FW/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h new file mode 100644 index 0000000..0c407c2 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h @@ -0,0 +1,814 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.2.0 + * @date 17. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ + +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + + + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} +#endif + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return result; +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value +*/ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) + // Re-enable using built-in when GCC has been fixed + // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/FW/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h b/FW/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h new file mode 100644 index 0000000..7d44107 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h @@ -0,0 +1,571 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 15. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2018-2019 Arm Limited +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) + { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) + { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) + { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) + { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#if 0 +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma language=save + #pragma language=extended + __packed struct __iar_u32 { uint32_t v; }; + #pragma language=restore + #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if __FPU_PRESENT + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #else + #define __get_FPSCR() ( 0 ) + #endif + + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE)) + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !__FPU_PRESENT + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if !__FPU_PRESENT + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#ifdef __ARM_ADVANCED_SIMD__ + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 \n" + : : : "cc", "r1", "r2" + ); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/FW/Drivers/CMSIS/Core_A/Include/core_ca.h b/FW/Drivers/CMSIS/Core_A/Include/core_ca.h new file mode 100644 index 0000000..0bef549 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/core_ca.h @@ -0,0 +1,2613 @@ +/**************************************************************************//** + * @file core_ca.h + * @brief CMSIS Cortex-A Core Peripheral Access Layer Header File + * @version V1.0.2 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CA_H_GENERIC +#define __CORE_CA_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ + +/* CMSIS CA definitions */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA_H_DEPENDANT +#define __CORE_CA_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA_REV + #define __CA_REV 0x0000U + #warning "__CA_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< \brief Defines 'read only' permissions */ +#else + #define __I volatile const /*!< \brief Defines 'read only' permissions */ +#endif +#define __O volatile /*!< \brief Defines 'write only' permissions */ +#define __IO volatile /*!< \brief Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ +#define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ +#define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + RESERVED(1:1, uint32_t) + uint32_t B:1; /*!< \brief bit: 7 Endianness model */ + RESERVED(2:2, uint32_t) + uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ + RESERVED(3:2, uint32_t) + uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ + RESERVED(4:1, uint32_t) + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< \brief bit: 22 Alignment model */ + RESERVED(5:1, uint32_t) + uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(6:1, uint32_t) + uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(7:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< \brief SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< \brief SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< \brief SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< \brief SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< \brief SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< \brief SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + +/* CP15 Register CPACR */ +typedef union +{ + struct + { + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) + uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ + +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ + +/* CP15 Register DFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ + +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + +#define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ + +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + +/* CP15 Register IFSR */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ + RESERVED(1:1, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ + uint32_t w; /*!< \brief Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ + +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + +#define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ + +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + +/* CP15 Register ISR */ +typedef union +{ + struct + { + RESERVED(0:6, uint32_t) + uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ + RESERVED(1:23, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< \brief ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< \brief ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< \brief ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ + +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + + +/** + \brief Union type to access the L2C_310 Cache Controller. +*/ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +typedef struct +{ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ +} L2C_310_TypeDef; + +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ +#endif + +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ +} GICDistributor_Type; + +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ + +/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) +*/ +typedef struct +{ + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ +} GICInterface_Type; + +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ +#endif + +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Structure type to access the Private Timer +*/ +typedef struct +{ + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register +} Timer_Type; +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ +#endif +#endif + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) { + __set_DCCMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) { + __set_DCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) { + __set_DCCIMVAC((uint32_t)va); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Calculate log2 rounded up +* - log(0) => 0 +* - log(1) => 0 +* - log(2) => 1 +* - log(3) => 2 +* - log(4) => 2 +* - log(5) => 3 +* : : +* - log(16) => 4 +* - log(32) => 5 +* : : +* \param [in] n input value parameter +* \return log2(n) +*/ +__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n) +{ + if (n < 2U) { + return 0U; + } + uint8_t log = 0U; + uint32_t t = n; + while(t > 1U) + { + log++; + t >>= 1U; + } + if (n & 1U) { log++; } + return log; +} + +/** \brief Apply cache maintenance to given cache level. +* \param [in] level cache level to be maintained +* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + uint32_t Dummy; + uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + int32_t log2_num_ways; + + Dummy = level << 1U; + /* set csselr, select ccsidr register */ + __set_CSSELR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U; + num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U; + log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U; + log2_num_ways = __log2_up(num_ways); + if ((log2_num_ways < 0) || (log2_num_ways > 32)) { + return; // FATAL ERROR + } + shift_way = 32U - (uint32_t)log2_num_ways; + for(int32_t way = num_ways-1; way >= 0; way--) + { + for(int32_t set = num_sets-1; set >= 0; set--) + { + Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way); + switch (maint) + { + case 0U: __set_DCISW(Dummy); break; + case 1U: __set_DCCSW(Dummy); break; + default: __set_DCCISW(Dummy); break; + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +*/ +__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) { + uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0U; i<7U; i++) + { + cache_type = (clidr >> i*3U) & 0x7UL; + if ((cache_type >= 2U) && (cache_type <= 4U)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } +} + +/** \brief Clean and Invalidate the entire data or unified cache +* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \deprecated Use generic L1C_CleanInvalidateCache instead. +*/ +CMSIS_DEPRECATED +__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) { + L1C_CleanInvalidateCache(op); +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(0); +} + +/** \brief Clean the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) { + L1C_CleanInvalidateCache(1); +} + +/** \brief Clean and invalidate the whole data cache. + */ +__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) { + L1C_CleanInvalidateCache(2); +} + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ +__STATIC_INLINE void L2C_Sync(void) +{ + L2C_310->CACHE_SYNC = 0x0; +} + +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ +__STATIC_INLINE int L2C_GetID (void) +{ + return L2C_310->CACHE_ID; +} + +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ +__STATIC_INLINE int L2C_GetType (void) +{ + return L2C_310->CACHE_TYPE; +} + +/** \brief Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_InvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Clean and Invalidate all cache by way +*/ +__STATIC_INLINE void L2C_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate + + L2C_Sync(); +} + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + L2C_310->CONTROL = 0; + L2C_310->INTERRUPT_CLEAR = 0x000001FFuL; + L2C_310->DEBUG_CONTROL = 0; + L2C_310->DATA_LOCK_0_WAY = 0; + L2C_310->CACHE_SYNC = 0; + L2C_310->CONTROL = 0x01; + L2C_Sync(); +} + +/** \brief Disable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Disable(void) +{ + L2C_310->CONTROL = 0x00; + L2C_Sync(); +} + +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_InvPa (void *pa) +{ + L2C_310->INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanPa (void *pa) +{ + L2C_310->CLEAN_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} + +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ +__STATIC_INLINE void L2C_CleanInvPa (void *pa) +{ + L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; + L2C_Sync(); +} +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_EnableDistributor(void) +{ + GICDistributor->CTLR |= 1U; +} + +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ +__STATIC_INLINE void GIC_DisableDistributor(void) +{ + GICDistributor->CTLR &=~1U; +} + +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ +__STATIC_INLINE uint32_t GIC_DistributorInfo(void) +{ + return (GICDistributor->TYPER); +} + +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_DistributorImplementer(void) +{ + return (GICDistributor->IIDR); +} + +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ +__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ +__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Enable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_EnableInterface(void) +{ + GICInterface->CTLR |= 1U; //enable interface +} + +/** \brief Disable the CPU's interrupt interface. +*/ +__STATIC_INLINE void GIC_DisableInterface(void) +{ + GICInterface->CTLR &=~1U; //disable distributor +} + +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ +__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->IAR); +} + +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ +__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->EOIR = IRQn; +} + +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ +__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); +} + +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ +__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } +} + +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} + +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); +} + +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ +__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); +} + +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ +__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; +} + +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) +{ + GICInterface->PMR = priority & 0xFFUL; //set priority mask +} + +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ +__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->BPR = binary_point & 7U; //set binary point +} + +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) +{ + return GICInterface->BPR; +} + +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ +__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + + return ((active<<1U) | pending); +} + +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ +__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} +#define GIC_GetSecurity GIC_GetGroup + +/** \brief Initialize the interrupt distributor. +*/ +__STATIC_INLINE void GIC_DistInit(void) +{ + uint32_t i; + uint32_t num_irq = 0U; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + for (i = 32U; i < num_irq; i++) + { + //Disable the SPI interrupt + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive (and N-N model) + GIC_SetConfiguration((IRQn_Type)i, 0U); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + //Set target list to CPU0 + GIC_SetTarget((IRQn_Type)i, 1U); + } + //Enable distributor + GIC_EnableDistributor(); +} + +/** \brief Initialize the CPU's interrupt interface +*/ +__STATIC_INLINE void GIC_CPUInterfaceInit(void) +{ + uint32_t i; + uint32_t priority_field; + + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0U, 0xFFU); + priority_field = GIC_GetPriority((IRQn_Type)0U); + + //SGI and PPI + for (i = 0U; i < 32U; i++) + { + if(i > 15U) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration((IRQn_Type)i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2U); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0U); + //Set priority mask + GIC_SetInterfacePriorityMask(0xFFU); +} + +/** \brief Initialize and enable the GIC +*/ +__STATIC_INLINE void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +/* PL1 Physical Timer */ +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ + __set_CNTP_TVAL(value); + __ISB(); +} + +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue(void) +{ + return(__get_CNTP_TVAL()); +} + +/** \brief Get the current physical counter value. +* \return Current physical counter value. +*/ +__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void) +{ + return(__get_CNTPCT()); +} + +/** \brief Set the physical compare value. +* \param [in] value New physical timer compare value. +*/ +__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value) +{ + __set_CNTP_CVAL(value); + __ISB(); +} + +/** \brief Get the physical compare value. +* \return Physical compare value. +*/ +__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void) +{ + return(__get_CNTP_CVAL()); +} + +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ + __set_CNTP_CTL(value); + __ISB(); +} + +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl(void) +{ + return(__get_CNTP_CTL()); +} +#endif + +/* Private Timer */ +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ + PTIM->LOAD = value; +} + +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ + return(PTIM->LOAD); +} + +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ + return(PTIM->COUNTER); +} + +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ + PTIM->CONTROL = value; +} + +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ + return(PTIM->CONTROL); +} + +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ + PTIM->ISR = 1; +} +#endif +#endif + +/* ########################## MMU functions ###################################### */ + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +//Following macros define the descriptors and attributes +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0 +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0 +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0 +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetSectionDescriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +/** \brief Set section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 +*/ +__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 +*/ +__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 +*/ +__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 +*/ +__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 +*/ +__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 +*/ +__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 +*/ +__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 +*/ +__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + +/** \brief Set Section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 +*/ +__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] page Page size + + \return 0 +*/ +__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + MMU_MemorySection(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + \param [out] descriptor L1 descriptor + \param [in] reg Section attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + MMU_XNSection(descriptor,reg.xn_t); + MMU_DomainSection(descriptor, reg.domain); + MMU_PSection(descriptor, reg.e_t); + MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1); + MMU_SharedSection(descriptor,reg.sh_t); + MMU_GlobalSection(descriptor,reg.g_t); + MMU_SecureSection(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 +*/ +__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k); + MMU_DomainPage(descriptor, reg.domain); + MMU_PPage(descriptor, reg.e_t); + MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1); + MMU_SharedPage(descriptor2,reg.sh_t); + MMU_GlobalPage(descriptor2,reg.g_t); + MMU_SecurePage(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + } + + return 0; +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + +*/ +__STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + { + //4 bytes aligned + *ttb_l2++ = entry2; + } + entry2 += OFFSET_64K; + } +} + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + __set_TLBIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Core_A/Include/irq_ctrl.h b/FW/Drivers/CMSIS/Core_A/Include/irq_ctrl.h new file mode 100644 index 0000000..b171ef0 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Include/irq_ctrl.h @@ -0,0 +1,186 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.0.0 + * @date 23. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/FW/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c b/FW/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c new file mode 100644 index 0000000..25d1359 --- /dev/null +++ b/FW/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c @@ -0,0 +1,410 @@ +/**************************************************************************//** + * @file irq_ctrl_gic.c + * @brief Interrupt controller handling implementation for GIC + * @version V1.0.1 + * @date 9. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "irq_ctrl.h" + +#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) + +/// Number of implemented interrupt lines +#ifndef IRQ_GIC_LINE_COUNT +#define IRQ_GIC_LINE_COUNT (1020U) +#endif + +static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; +static uint32_t IRQ_ID0; + +/// Initialize interrupt controller. +__WEAK int32_t IRQ_Initialize (void) { + uint32_t i; + + for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { + IRQTable[i] = (IRQHandler_t)NULL; + } + GIC_Enable(); + return (0); +} + + +/// Register interrupt handler. +__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + IRQTable[irqn] = handler; + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get the registered interrupt handler. +__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { + IRQHandler_t h; + + // Ignore CPUID field (software generated interrupts) + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + h = IRQTable[irqn]; + } else { + h = (IRQHandler_t)0; + } + + return (h); +} + + +/// Enable interrupt. +__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EnableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Disable interrupt. +__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_DisableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt enable state. +__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { + uint32_t enable; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + enable = GIC_GetEnableIRQ((IRQn_Type)irqn); + } else { + enable = 0U; + } + + return (enable); +} + + +/// Configure interrupt request mode. +__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { + uint32_t val; + uint8_t cfg; + uint8_t secure; + uint8_t cpu; + int32_t status = 0; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + // Check triggering mode + val = (mode & IRQ_MODE_TRIG_Msk); + + if (val == IRQ_MODE_TRIG_LEVEL) { + cfg = 0x00U; + } else if (val == IRQ_MODE_TRIG_EDGE) { + cfg = 0x02U; + } else { + cfg = 0x00U; + status = -1; + } + + // Check interrupt type + val = mode & IRQ_MODE_TYPE_Msk; + + if (val != IRQ_MODE_TYPE_IRQ) { + status = -1; + } + + // Check interrupt domain + val = mode & IRQ_MODE_DOMAIN_Msk; + + if (val == IRQ_MODE_DOMAIN_NONSECURE) { + secure = 0U; + } else { + // Check security extensions support + val = GIC_DistributorInfo() & (1UL << 10U); + + if (val != 0U) { + // Security extensions are supported + secure = 1U; + } else { + secure = 0U; + status = -1; + } + } + + // Check interrupt CPU targets + val = mode & IRQ_MODE_CPU_Msk; + + if (val == IRQ_MODE_CPU_ALL) { + cpu = 0xFFU; + } else { + cpu = val >> IRQ_MODE_CPU_Pos; + } + + // Apply configuration if no mode error + if (status == 0) { + GIC_SetConfiguration((IRQn_Type)irqn, cfg); + GIC_SetTarget ((IRQn_Type)irqn, cpu); + + if (secure != 0U) { + GIC_SetGroup ((IRQn_Type)irqn, secure); + } + } + } + + return (status); +} + + +/// Get interrupt mode configuration. +__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { + uint32_t mode; + uint32_t val; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + mode = IRQ_MODE_TYPE_IRQ; + + // Get trigger mode + val = GIC_GetConfiguration((IRQn_Type)irqn); + + if ((val & 2U) != 0U) { + // Corresponding interrupt is edge triggered + mode |= IRQ_MODE_TRIG_EDGE; + } else { + // Corresponding interrupt is level triggered + mode |= IRQ_MODE_TRIG_LEVEL; + } + + // Get interrupt CPU targets + mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; + + } else { + mode = IRQ_MODE_ERROR; + } + + return (mode); +} + + +/// Get ID number of current interrupt request (IRQ). +__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { + IRQn_ID_t irqn; + uint32_t prio; + + /* Dummy read to avoid GIC 390 errata 801120 */ + GIC_GetHighPendingIRQ(); + + irqn = GIC_AcknowledgePending(); + + __DSB(); + + /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ + /* The following workaround code is for a single-core system. It would be */ + /* different in a multi-core system. */ + /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ + /* so unlock it, otherwise service the interrupt as normal. */ + /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ + /* so will not occur here. */ + + if ((irqn == 0) || (irqn >= 0x3FE)) { + /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ + prio = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority ((IRQn_Type)0, prio); + + __DSB(); + + if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { + /* If the ID is 0, is active and has not been seen before */ + IRQ_ID0 = 1U; + } + /* End of Workaround GIC 390 errata 733075 */ + } + + return (irqn); +} + + +/// Get ID number of current fast interrupt request (FIQ). +__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { + return ((IRQn_ID_t)-1); +} + + +/// Signal end of interrupt processing. +__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { + int32_t status; + IRQn_Type irq = (IRQn_Type)irqn; + + irqn &= 0x3FFU; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EndInterrupt (irq); + + if (irqn == 0) { + IRQ_ID0 = 0U; + } + + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt pending flag. +__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + +/// Get interrupt pending flag. +__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { + uint32_t pending; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); + } else { + pending = 0U; + } + + return (pending & 1U); +} + + +/// Clear interrupt pending flag. +__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_ClearPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt priority value. +__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPriority ((IRQn_Type)irqn, priority); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt priority. +__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { + uint32_t priority; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + priority = GIC_GetPriority ((IRQn_Type)irqn); + } else { + priority = IRQ_PRIORITY_ERROR; + } + + return (priority); +} + + +/// Set priority masking threshold. +__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { + GIC_SetInterfacePriorityMask (priority); + return (0); +} + + +/// Get priority masking threshold +__WEAK uint32_t IRQ_GetPriorityMask (void) { + return GIC_GetInterfacePriorityMask(); +} + + +/// Set priority grouping field split point +__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { + int32_t status; + + if (bits == IRQ_PRIORITY_Msk) { + bits = 7U; + } + + if (bits < 8U) { + GIC_SetBinaryPoint (7U - bits); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get priority grouping field split point +__WEAK uint32_t IRQ_GetPriorityGroupBits (void) { + uint32_t bp; + + bp = GIC_GetBinaryPoint() & 0x07U; + + return (7U - bp); +} + +#endif diff --git a/FW/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/FW/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h new file mode 100644 index 0000000..3802024 --- /dev/null +++ b/FW/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h @@ -0,0 +1,26564 @@ +/** + ****************************************************************************** + * @file stm32h743xx.h + * @author MCD Application Team + * @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h743xx + * @{ + */ + +#ifndef STM32H743xx_H +#define STM32H743xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */ + OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */ + OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */ + OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +}EXTI_TypeDef; + +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Cortex-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ + __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ + uint32_t RESERVED2; /*!< Reserved, 0x108 */ + __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ + __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ + __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ + __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ + __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ + __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ + __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ + __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ + __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ + uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ + __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ + __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ + __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ + __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ + __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */ + uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */ + __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */ + __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief High resolution Timer (HRTIM) + */ +/* HRTIM master registers definition */ +typedef struct +{ + __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ + __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */ + __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ + __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ + __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ + __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ + __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ + __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ + __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ + __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ + uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ +}HRTIM_Master_TypeDef; + +/* HRTIM Timer A to E registers definition */ +typedef struct +{ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ + __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ + __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ + __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ + __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ + __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ + __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ + __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ + __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ + __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ + __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ + __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ + __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ + __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ +}HRTIM_Timerx_TypeDef; + +/* HRTIM common register definition */ +typedef struct +{ + __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ + __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ + __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ + __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ + __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ + __IO uint32_t BMTRGR; /*!< HRTIM Burst mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ + __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ + __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ + __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ + __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ + __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ + __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ + __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ + __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ + __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ + __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ + __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ + __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ + __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ + __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ + __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ + __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ +}HRTIM_Common_TypeDef; + +/* HRTIM register definition */ +typedef struct { + HRTIM_Master_TypeDef sMasterRegs; + HRTIM_Timerx_TypeDef sTimerxRegs[5]; + uint32_t RESERVED0[32]; + HRTIM_Common_TypeDef sCommonRegs; +}HRTIM_TypeDef; +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */ + +#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */ +#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */ +#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */ + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL) +#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL) +#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) +#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL) +#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL) +#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL) +#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL) +#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL) +#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL) +#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) +#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL) +#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define SAI3 ((SAI_TypeDef *) SAI3_BASE) +#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) +#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) +#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE) +#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) +#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE +#define USB_OTG_FS USB2_OTG_FS +#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE + +#define GPV ((GPV_TypeDef *) GPV_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC LDO output voltage ready bit */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1 MB */ +#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ +#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */ +#define DUAL_BANK /* Dual-bank Flash */ + +/******************* Bits definition for FLASH_ACR register **********************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F: bit4 is kept only for legacy purpose */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000UL) +#define FLASH_ACR_LATENCY_1WS (0x00000001UL) +#define FLASH_ACR_LATENCY_2WS (0x00000002UL) +#define FLASH_ACR_LATENCY_3WS (0x00000003UL) +#define FLASH_ACR_LATENCY_4WS (0x00000004UL) +#define FLASH_ACR_LATENCY_5WS (0x00000005UL) +#define FLASH_ACR_LATENCY_6WS (0x00000006UL) +#define FLASH_ACR_LATENCY_7WS (0x00000007UL) + +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ + +/* Legacy FLASH Latency defines */ +#define FLASH_ACR_LATENCY_8WS (0x00000008UL) +#define FLASH_ACR_LATENCY_9WS (0x00000009UL) +#define FLASH_ACR_LATENCY_10WS (0x0000000AUL) +#define FLASH_ACR_LATENCY_11WS (0x0000000BUL) +#define FLASH_ACR_LATENCY_12WS (0x0000000CUL) +#define FLASH_ACR_LATENCY_13WS (0x0000000DUL) +#define FLASH_ACR_LATENCY_14WS (0x0000000EUL) +#define FLASH_ACR_LATENCY_15WS (0x0000000FUL) +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_PSIZE_Pos (4U) +#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */ +#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */ +#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */ +#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */ +#define FLASH_CR_FW_Pos (6U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (7U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (8U) +#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_CRC_EN_Pos (15U) +#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */ +#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (21U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OPERRIE_Pos (22U) +#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */ +#define FLASH_CR_RDPERRIE_Pos (23U) +#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */ +#define FLASH_CR_RDSERRIE_Pos (24U) +#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */ +#define FLASH_CR_SNECCERRIE_Pos (25U) +#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */ +#define FLASH_CR_DBECCERRIE_Pos (26U) +#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */ +#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */ +#define FLASH_CR_CRCENDIE_Pos (27U) +#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */ +#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */ +#define FLASH_CR_CRCRDERRIE_Pos (28U) +#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */ +#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_QW_Pos (2U) +#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */ +#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */ +#define FLASH_SR_CRC_BUSY_Pos (3U) +#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */ +#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (21U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OPERR_Pos (22U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */ +#define FLASH_SR_RDPERR_Pos (23U) +#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */ +#define FLASH_SR_RDSERR_Pos (24U) +#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */ +#define FLASH_SR_SNECCERR_Pos (25U) +#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */ +#define FLASH_SR_DBECCERR_Pos (26U) +#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */ +#define FLASH_SR_CRCEND_Pos (27U) +#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */ +#define FLASH_SR_CRCRDERR_Pos (28U) +#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (21U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OPERR_Pos (22U) +#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */ +#define FLASH_CCR_CLR_RDPERR_Pos (23U) +#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */ +#define FLASH_CCR_CLR_RDSERR_Pos (24U) +#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */ +#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */ +#define FLASH_CCR_CLR_SNECCERR_Pos (25U) +#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */ +#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */ +#define FLASH_CCR_CLR_DBECCERR_Pos (26U) +#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */ +#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */ +#define FLASH_CCR_CLR_CRCEND_Pos (27U) +#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */ +#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */ +#define FLASH_CCR_CLR_CRCRDERR_Pos (28U) +#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */ +#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_MER_Pos (4U) +#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */ +#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */ +#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) +#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_OPT_BUSY_Pos (0U) +#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */ +#define FLASH_OPTSR_BOR_LEV_Pos (2U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG1_SW_Pos (4U) +#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */ +#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */ +#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U) +#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */ +#define FLASH_OPTSR_RDP_Pos (8U) +#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */ +#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) +#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */ +#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) +#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */ +#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U) +#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */ +#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */ +#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */ +#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_SECURITY_Pos (21U) +#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */ +#define FLASH_OPTSR_IO_HSLV_Pos (29U) +#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */ +#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ +#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */ + +/******************* Bits definition for FLASH_OPTCCR register *******************/ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) +#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ +#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */ + +/******************* Bits definition for FLASH_PRAR register *********************/ +#define FLASH_PRAR_PROT_AREA_START_Pos (0U) +#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */ +#define FLASH_PRAR_PROT_AREA_END_Pos (16U) +#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */ +#define FLASH_PRAR_DMEP_Pos (31U) +#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */ +#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */ + +/******************* Bits definition for FLASH_SCAR register *********************/ +#define FLASH_SCAR_SEC_AREA_START_Pos (0U) +#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */ +#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */ +#define FLASH_SCAR_SEC_AREA_END_Pos (16U) +#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */ +#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */ +#define FLASH_SCAR_DMES_Pos (31U) +#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */ +#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */ + +/******************* Bits definition for FLASH_WPSN register *********************/ +#define FLASH_WPSN_WRPSN_Pos (0U) +#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */ +#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */ + +/******************* Bits definition for FLASH_BOOT_CUR register ****************/ +#define FLASH_BOOT_ADD0_Pos (0U) +#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */ +#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */ +#define FLASH_BOOT_ADD1_Pos (16U) +#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */ +#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */ + + +/******************* Bits definition for FLASH_CRCCR register ********************/ +#define FLASH_CRCCR_CRC_SECT_Pos (0U) +#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */ +#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */ +#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U) +#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */ +#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */ +#define FLASH_CRCCR_ADD_SECT_Pos (9U) +#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */ +#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */ +#define FLASH_CRCCR_CLEAN_SECT_Pos (10U) +#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */ +#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */ +#define FLASH_CRCCR_START_CRC_Pos (16U) +#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */ +#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */ +#define FLASH_CRCCR_CLEAN_CRC_Pos (17U) +#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */ +#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */ +#define FLASH_CRCCR_CRC_BURST_Pos (20U) +#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */ +#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */ +#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */ +#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */ +#define FLASH_CRCCR_ALL_BANK_Pos (22U) +#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */ +#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */ + +/******************* Bits definition for FLASH_CRCSADD register ****************/ +#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U) +#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */ + +/******************* Bits definition for FLASH_CRCEADD register ****************/ +#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U) +#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */ + +/******************* Bits definition for FLASH_CRCDATA register ***************/ +#define FLASH_CRCDATA_CRC_DATA_Pos (0U) +#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */ + +/******************* Bits definition for FLASH_ECC_FA register *******************/ +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) +#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */ +#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/FW/Drivers/CMSIS/Include/cmsis_armclang.h b/FW/Drivers/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000..e917f35 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/FW/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/FW/Drivers/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000..feec324 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/FW/Drivers/CMSIS/Include/cmsis_compiler.h b/FW/Drivers/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000..adbf296 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/FW/Drivers/CMSIS/Include/cmsis_gcc.h b/FW/Drivers/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000..3ddcc58 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/FW/Drivers/CMSIS/Include/cmsis_iccarm.h b/FW/Drivers/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000..12d68fd --- /dev/null +++ b/FW/Drivers/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/FW/Drivers/CMSIS/Include/cmsis_version.h b/FW/Drivers/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000..f2e2746 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/FW/Drivers/CMSIS/Include/core_armv81mml.h b/FW/Drivers/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000..8441e57 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_armv8mbl.h b/FW/Drivers/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000..344dca5 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_armv8mml.h b/FW/Drivers/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000..5ddb8ae --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm0.h b/FW/Drivers/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000..cafae5a --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm0plus.h b/FW/Drivers/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000..d104965 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm1.h b/FW/Drivers/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000..76b4569 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm23.h b/FW/Drivers/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000..b79c6af --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm3.h b/FW/Drivers/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000..8157ca7 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm33.h b/FW/Drivers/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000..7fed59a --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm35p.h b/FW/Drivers/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000..5579c82 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm4.h b/FW/Drivers/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000..12c023b --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_cm7.h b/FW/Drivers/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000..c4515d8 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_sc000.h b/FW/Drivers/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000..cf92577 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/core_sc300.h b/FW/Drivers/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000..40f3af8 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FW/Drivers/CMSIS/Include/mpu_armv7.h b/FW/Drivers/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000..66ef59b --- /dev/null +++ b/FW/Drivers/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/FW/Drivers/CMSIS/Include/mpu_armv8.h b/FW/Drivers/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000..0041d4d --- /dev/null +++ b/FW/Drivers/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/FW/Drivers/CMSIS/Include/tz_context.h b/FW/Drivers/CMSIS/Include/tz_context.h new file mode 100644 index 0000000..0d09749 --- /dev/null +++ b/FW/Drivers/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/FW/Drivers/CMSIS/LICENSE.txt b/FW/Drivers/CMSIS/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/FW/Drivers/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 +// <1048576=>1048576 +// Configure size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=1048576) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 1 + +// SysTick Configuration +// Configure values when Time Stamp Source is set to SysTick + +// SysTick Input Clock Frequency [Hz] <1-1000000000> +// Defines SysTick input clock (typical identical with processor clock) +#define SYSTICK_CLOCK 100000000U + +// SysTick Interrupt Period [us] <1-1000000000> +// Defines time period of the SysTick timer interrupt +#define SYSTICK_PERIOD_US 1000U + +// + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..9fc447d --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,242 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66829ad --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..16e56b0 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f08df7a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..dae6439 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..070fa1e --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..26edb9f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup_ARMCM7.s + * @brief CMSIS Core Device Startup File for + * ARMCM7 Device Series + * @version V5.00 + * @date 26. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __etext; +extern uint32_t __data_start__; +extern uint32_t __data_end__; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __StackTop; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#endif + +#ifndef __NO_SYSTEM_INIT +extern void SystemInit (void); /* CMSIS System Initialization */ +#endif + + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void); /* Default empty handler */ +void Reset_Handler(void); /* Reset Handler */ + + +/*---------------------------------------------------------------------------- + User Initial Stack & Heap + *----------------------------------------------------------------------------*/ +#ifndef __STACK_SIZE + #define __STACK_SIZE 0x00000400 +#endif +static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +#ifndef __HEAP_SIZE + #define __HEAP_SIZE 0x00000C00 +#endif +#if __HEAP_SIZE > 0 +static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M7 Processor Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* ARMCM7 Specific Interrupts */ +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { + /* Cortex-M7 Exceptions Handler */ + (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External interrupts */ + WDT_IRQHandler, /* 0: Watchdog Timer */ + RTC_IRQHandler, /* 1: Real Time Clock */ + TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ + TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ + MCIA_IRQHandler, /* 4: MCIa */ + MCIB_IRQHandler, /* 5: MCIb */ + UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ + UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ + UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ + UART4_IRQHandler, /* 9: UART4 - not connected */ + AACI_IRQHandler, /* 10: AACI / AC97 */ + CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ + ENET_IRQHandler, /* 12: Ethernet */ + USBDC_IRQHandler, /* 13: USB Device */ + USBHC_IRQHandler, /* 14: USB Host Controller */ + CHLCD_IRQHandler, /* 15: Character LCD */ + FLEXRAY_IRQHandler, /* 16: Flexray */ + CAN_IRQHandler, /* 17: CAN */ + LIN_IRQHandler, /* 18: LIN */ + I2C_IRQHandler, /* 19: I2C ADC/DAC */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + 0, /* 27: Reserved */ + CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ + 0, /* 29: Reserved - CPU FPGA */ + UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ + SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0UL; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + SystemInit(); +#endif + +#ifndef __START +#define __START _start +#endif + __START(); + +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + + while(1); +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..b69f038 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..65bfaca --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..0c062ad --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..62755a7 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..835cb37 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..d275f41 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp new file mode 100644 index 0000000..471899c --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_cifar10.cpp +* +* Description: Convolutional Neural Network Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup CNNExample Convolutional Neural Network Example + * + * \par Description: + * \par + * Demonstrates a convolutional neural network (CNN) example with the use of convolution, + * ReLU activation, pooling and fully-connected functions. + * + * \par Model definition: + * \par + * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. + * The neural network consists + * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a + * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will + * be classified into one of the 10 output classes. + * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and + * 3.1 KB for storing the \c im2col data. + * + * \image html CIFAR10_CNN.gif "Neural Network model definition" + * + * \par Variables Description: + * \par + * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices + * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays + * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases + * \li \c input_data points to the input image data + * \li \c output_data points to the classification output + * \li \c col_buffer is a buffer to store the \c im2col output + * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs) + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_convolve_HWC_q7_RGB() + * - arm_convolve_HWC_q7_fast() + * - arm_relu_q7() + * - arm_maxpool_q7_HWC() + * - arm_avepool_q7_HWC() + * - arm_fully_connected_q7_opt() + * - arm_fully_connected_q7() + * + * Refer + * \link arm_nnexamples_cifar10.cpp \endlink + * + * \par [1] https://github.com/BVLC/caffe + */ + +#include +#include +#include "arm_math.h" +#include "arm_nnexamples_cifar10_parameter.h" +#include "arm_nnexamples_cifar10_weights.h" + +#include "arm_nnfunctions.h" +#include "arm_nnexamples_cifar10_inputs.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +// include the input and weights + +static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT; +static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS; + +static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT; +static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS; + +static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT; +static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS; + +static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT; +static q7_t ip1_bias[IP1_OUT] = IP1_BIAS; + +/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */ +uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA; +q7_t output_data[IP1_OUT]; + +//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer) +q7_t col_buffer[2 * 5 * 5 * 32 * 2]; + +q7_t scratch_buffer[32 * 32 * 10 * 4]; + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("start execution\n"); + /* start the execution */ + + q7_t *img_buffer1 = scratch_buffer; + q7_t *img_buffer2 = img_buffer1 + 32 * 32 * 32; + + /* input pre-processing */ + int mean_data[3] = INPUT_MEAN_SHIFT; + unsigned int scale_data[3] = INPUT_RIGHT_SHIFT; + for (int i=0;i<32*32*3; i+=3) { + img_buffer2[i] = (q7_t)__SSAT( ((((int)image_data[i] - mean_data[0])<<7) + (0x1<<(scale_data[0]-1))) + >> scale_data[0], 8); + img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1))) + >> scale_data[1], 8); + img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1))) + >> scale_data[2], 8); + } + + // conv1 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING, + CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM, + (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH); + + // pool1 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM, + POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2); + + // conv2 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM, + CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1, + CONV2_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH); + + // pool2 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM, + POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2); + +// conv3 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM, + CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1, + CONV3_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH); + + // pool3 img_buffer-> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM, + POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2); + + arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias, + output_data, (q15_t *) img_buffer1); + + arm_softmax_q7(output_data, 10, output_data); + + for (int i = 0; i < 10; i++) + { + printf("%d: %d\n", i, output_data[i]); + } + + return 0; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h new file mode 100644 index 0000000..c600c5a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h @@ -0,0 +1,6 @@ +/* Here are two different test images */ + +//#define IMG_DATA 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3,71,107,133,49,89,114,31,77,105,27,71,105,38,82,117,49,93,128,56,100,135,58,102,137,53,92,128,56,94,131,60,99,137,57,99,139,53,97,138,50,95,137,45,94,136,39,88,131,33,83,125,42,91,133,62,112,154,79,132,179,73,131,181,56,116,168,38,97,146,13,64,108,40,85,127,61,116,168,49,102,148,35,85,132,43,91,143,39,90,139,42,92,134,44,88,125,40,81,112,42,85,115,27,72,104,23,67,102,30,74,109,27,71,106,29,73,108,36,80,115,47,86,120,56,95,128,62,101,135,66,109,144,75,119,156,69,113,152,49,95,134,43,88,127,43,88,127,60,105,144,85,130,170,109,156,197,93,145,190,60,115,164,26,82,130,29,82,126,20,64,107,54,107,160,56,105,149,45,89,132,43,86,134,40,89,134,40,92,132,40,87,123,38,81,115,36,79,114,26,69,105,22,66,101,29,73,108,25,69,104,29,73,108,19,63,98,18,58,89,32,70,100,47,87,118,61,104,137,74,119,152,66,111,145,53,96,131,52,95,130,45,87,123,67,109,145,89,131,167,105,146,182,89,135,175,48,99,145,24,77,124,34,84,129,21,67,110} + + +#define IMG_DATA {235,235,235,231,231,231,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,232,233,233,231,233,232,231,233,231,233,233,230,233,232,232,232,234,232,231,234,232,232,232,233,233,230,232,233,231,233,233,233,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,232,232,232,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,237,234,233,236,234,233,236,236,234,234,236,234,234,235,237,234,234,238,235,236,237,236,236,235,236,236,234,236,236,236,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,235,235,235,237,237,237,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,234,234,236,233,231,236,234,231,235,235,234,234,235,236,227,230,233,231,235,238,231,233,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,234,233,233,230,232,232,231,228,230,232,223,226,231,186,192,197,209,216,219,207,210,213,228,228,230,236,235,235,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,237,237,237,234,234,234,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,236,238,236,233,237,237,219,225,230,203,210,219,163,172,179,195,205,208,214,218,221,230,229,232,237,235,237,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,239,239,238,236,235,235,236,235,235,236,235,235,236,235,235,236,235,235,235,236,235,235,235,235,234,234,234,235,235,235,237,236,236,237,236,236,234,235,236,232,233,234,235,237,237,229,231,232,208,216,218,194,205,210,185,198,207,174,188,200,165,179,189,184,196,202,207,215,220,226,228,232,236,235,237,236,236,235,236,236,235,236,236,235,236,236,236,237,237,237,237,237,237,237,237,237,228,229,229,228,227,228,232,230,231,231,228,230,234,232,233,237,236,236,237,237,235,236,237,235,237,235,236,237,235,236,239,236,237,239,237,238,225,229,230,224,228,229,233,237,238,221,226,228,183,197,204,161,180,190,159,180,191,154,176,190,144,163,177,143,159,171,156,169,177,198,206,211,233,238,239,236,237,234,235,236,233,235,235,235,235,236,236,236,238,237,237,237,237,239,237,238,212,220,222,224,230,233,230,234,238,227,232,234,229,234,234,234,237,236,237,238,235,238,237,236,239,237,238,239,237,238,239,236,237,240,238,239,201,204,203,219,222,221,233,236,235,214,218,218,193,204,210,185,201,210,184,201,211,173,191,203,165,182,196,159,174,187,162,176,185,186,199,204,229,239,240,234,239,238,233,238,237,233,238,238,234,239,238,236,239,238,237,239,238,238,238,238,216,234,241,221,236,243,225,238,246,225,239,243,227,240,240,231,238,237,236,237,235,238,236,235,238,236,237,238,236,237,237,237,237,239,239,239,197,198,196,220,221,218,233,234,231,230,231,229,209,213,217,209,216,222,219,228,235,208,218,227,209,221,234,210,224,235,217,233,240,218,235,241,225,240,243,228,238,240,228,239,240,230,240,240,230,240,239,235,240,239,237,240,239,238,238,238,118,140,149,119,138,148,124,142,153,136,155,161,172,188,191,225,234,233,235,236,233,237,234,232,236,233,234,235,235,235,235,237,236,233,237,235,214,216,214,226,228,226,232,234,232,236,237,236,228,230,232,227,230,235,231,236,241,225,232,239,225,237,247,217,233,243,201,219,226,185,204,211,172,189,195,167,179,186,167,180,185,186,199,201,223,235,235,235,241,239,236,240,239,238,240,239,109,130,141,103,121,133,108,125,137,111,127,137,146,159,165,222,229,231,227,228,225,229,226,224,236,232,233,234,234,234,231,236,234,230,237,235,229,234,235,231,235,236,232,237,238,230,235,236,231,236,238,231,237,240,229,237,241,223,232,238,191,206,213,164,184,191,146,165,172,137,156,163,134,149,159,128,140,153,121,133,143,149,162,166,216,228,229,234,241,239,235,240,238,237,240,239,195,212,224,188,202,215,199,211,224,200,211,223,209,217,227,223,227,231,213,213,211,211,209,206,216,213,214,220,222,222,219,226,225,210,221,219,209,219,223,211,221,225,216,225,230,220,229,233,225,234,237,226,236,239,225,237,241,218,231,237,183,204,208,175,198,203,181,200,207,178,194,202,186,197,211,170,178,196,142,151,164,185,195,202,219,230,233,231,240,238,234,241,239,236,240,239,193,207,222,191,202,217,202,211,224,214,217,234,223,225,241,214,219,227,203,208,208,171,174,174,177,180,183,207,213,214,174,184,188,98,112,121,93,114,126,101,121,132,111,129,139,122,138,147,137,152,161,153,167,174,202,216,220,223,236,237,218,232,235,220,233,238,223,234,240,217,226,233,221,228,237,212,219,229,196,203,212,222,230,237,219,227,234,221,230,233,232,239,242,235,241,242,113,130,152,111,125,147,113,125,141,125,131,151,138,145,165,170,182,193,191,201,205,190,199,204,208,219,226,216,230,234,158,172,183,54,71,92,45,70,91,49,73,91,53,73,90,66,84,98,102,114,129,159,168,179,221,227,233,234,239,241,233,237,241,227,231,237,223,228,233,207,211,217,202,208,212,211,218,220,212,219,223,199,206,214,179,186,196,188,197,205,211,221,227,221,231,234,61,81,108,69,86,114,63,79,100,68,85,102,123,141,155,139,155,164,151,157,164,195,200,207,214,228,234,206,223,228,163,180,190,103,121,138,95,112,131,101,117,135,138,151,168,181,192,207,207,212,223,221,222,232,219,219,227,205,203,212,183,186,195,158,166,174,147,154,163,131,138,147,125,133,140,130,139,144,136,146,152,133,142,151,128,137,147,138,153,160,182,197,203,197,212,216,40,53,77,58,70,94,85,98,116,127,144,153,132,151,156,96,107,110,119,115,118,163,158,161,173,180,182,184,194,197,182,194,198,181,193,200,183,194,202,198,209,217,218,228,236,200,210,217,174,181,186,159,165,172,145,150,159,132,136,149,116,125,138,98,111,123,94,106,118,99,111,123,105,118,128,107,121,130,122,135,145,138,151,161,150,164,174,157,174,184,188,206,213,185,203,208,13,15,35,26,29,47,134,140,151,206,216,220,138,150,150,118,123,123,141,133,134,172,162,162,181,181,180,207,209,211,220,224,225,228,234,233,224,234,232,230,241,240,226,238,238,176,189,190,144,159,163,138,154,162,142,158,170,145,163,177,154,171,187,149,165,182,149,165,182,154,171,187,157,174,189,160,177,191,173,190,204,187,204,217,190,207,218,178,196,208,165,183,193,157,175,183,5,5,24,58,62,79,200,207,217,225,232,239,197,205,212,199,207,211,212,212,218,226,224,229,229,230,237,233,236,246,232,238,245,230,238,239,209,221,220,223,238,239,221,238,241,210,228,234,198,217,228,180,200,214,193,216,230,188,213,229,189,212,231,194,214,234,192,212,232,184,204,224,172,193,212,171,191,209,161,181,197,144,165,179,136,156,169,131,146,161,128,143,158,138,154,165,39,45,71,145,155,179,190,204,222,186,196,216,184,197,217,192,211,229,194,211,230,194,208,227,194,206,227,191,203,228,192,207,228,190,207,221,177,193,207,180,198,215,154,176,193,147,169,188,145,161,184,156,171,195,146,163,186,113,133,156,114,137,161,132,157,180,126,150,173,111,135,158,92,115,138,91,112,135,93,114,133,94,116,131,105,125,140,121,133,151,129,141,158,129,142,156,122,135,161,162,179,207,143,160,194,137,154,189,131,152,187,128,152,190,127,150,192,130,150,193,131,150,192,128,147,190,127,147,189,129,149,189,129,149,188,124,145,186,104,126,163,100,122,154,102,120,154,118,134,170,112,128,163,94,109,145,94,112,148,94,117,153,87,112,144,83,103,136,80,97,130,83,103,134,93,111,139,101,117,141,108,121,144,115,125,146,121,133,148,130,144,156,73,87,109,76,90,113,77,90,122,80,93,127,84,98,134,87,102,142,87,102,147,90,105,150,94,111,152,102,119,160,107,124,165,113,131,172,115,137,181,118,136,186,118,132,180,120,133,175,115,136,172,110,133,168,106,127,163,100,119,155,95,109,148,85,101,139,79,97,132,80,92,127,80,94,129,77,100,133,80,100,129,82,98,122,92,104,126,113,119,138,125,135,146,136,149,156,13,25,41,3,11,25,9,16,35,18,26,48,18,26,52,21,25,56,20,25,58,22,30,61,26,36,62,34,43,70,42,51,77,48,59,87,52,69,106,60,75,121,66,77,126,70,79,126,71,87,127,72,88,126,67,81,120,60,72,112,55,67,106,53,68,104,53,69,103,57,69,102,57,71,105,57,78,110,72,89,115,87,100,119,104,113,128,120,124,136,130,136,141,137,146,149,36,46,55,11,16,20,8,13,19,32,44,53,36,45,58,22,25,41,8,11,30,3,8,24,1,4,17,0,2,15,0,2,15,0,4,20,6,13,42,5,18,56,1,19,60,3,23,62,13,29,71,24,38,81,21,33,77,21,31,76,21,38,78,22,44,79,30,50,83,39,58,90,57,70,101,85,90,118,113,115,138,123,123,138,116,115,125,122,123,128,134,139,137,153,160,158,35,41,45,26,27,26,13,19,18,27,41,41,71,81,84,70,70,76,49,50,57,27,31,37,15,15,21,5,5,11,2,2,7,0,0,7,17,17,35,57,64,91,31,50,78,10,36,62,4,30,60,4,30,62,7,30,63,14,35,69,25,43,74,41,55,83,62,71,99,86,97,123,122,124,146,144,131,149,132,120,135,114,105,114,117,111,116,132,134,133,146,152,146,172,179,175,16,15,17,13,10,9,4,10,8,3,12,11,45,44,46,65,52,57,54,43,47,36,33,35,18,18,20,4,4,7,2,2,4,0,1,3,7,8,15,118,117,134,161,158,179,131,128,148,112,112,131,105,105,125,105,103,124,109,105,127,118,107,126,138,115,133,154,126,144,151,126,141,127,106,116,105,86,91,106,94,97,120,116,116,129,130,129,142,147,144,164,172,165,184,194,190,40,40,35,12,10,7,0,3,3,0,4,4,12,6,7,30,12,17,32,12,17,21,10,12,7,6,7,2,1,3,2,1,2,3,2,3,0,0,2,68,58,64,182,128,146,205,130,148,196,127,144,194,123,141,195,119,137,187,113,129,172,110,122,150,96,106,123,75,83,103,66,69,95,71,70,104,93,88,122,118,113,129,132,126,132,141,135,152,162,158,171,182,176,185,197,194,69,77,64,26,29,21,1,1,1,1,1,2,4,1,0,12,2,5,18,3,9,12,2,5,4,1,2,2,0,0,2,0,0,4,0,1,1,1,1,32,12,11,153,45,59,203,47,68,195,46,67,191,48,69,179,50,67,155,49,59,119,42,49,91,38,42,81,48,46,94,77,71,117,110,102,125,126,116,125,128,120,129,135,128,144,153,147,162,176,171,173,187,183,184,198,196,83,94,82,47,52,43,1,1,1,2,1,2,2,0,0,5,1,2,7,1,5,4,0,2,1,0,0,1,0,0,1,0,0,3,0,0,1,2,0,27,3,2,142,25,38,205,32,54,198,25,46,169,25,43,121,25,36,85,29,34,74,41,39,85,66,56,102,92,82,121,113,105,128,124,115,122,126,115,121,127,118,132,139,131,147,157,150,165,179,174,176,191,187,186,201,199,92,102,93,54,60,50,6,7,3,3,2,1,2,2,0,1,3,1,1,3,3,1,2,2,1,1,1,1,0,0,1,0,0,1,1,1,0,3,2,15,1,0,102,19,28,157,31,47,117,17,23,74,13,12,56,27,22,74,58,55,99,90,81,115,115,99,122,126,111,124,124,112,123,123,113,125,130,119,128,135,126,136,145,137,148,159,151,162,176,171,177,192,188,188,202,201,87,99,89,43,51,37,19,23,11,11,12,4,8,10,2,5,11,4,2,10,4,2,7,2,3,4,1,3,4,1,3,4,1,2,3,2,0,6,6,4,5,2,42,13,13,71,21,24,53,27,25,57,50,41,80,77,62,113,98,82,132,113,101,134,126,113,123,126,112,116,125,111,120,128,115,131,138,126,139,148,137,143,154,145,156,168,161,169,184,179,182,197,193,188,202,201,82,96,82,46,57,36,36,44,22,31,35,17,27,30,15,22,28,15,17,26,13,16,23,12,18,21,12,19,21,13,20,22,14,19,23,15,19,27,20,23,31,21,37,40,27,64,55,45,87,70,67,104,88,81,116,102,85,128,112,88,139,121,105,131,122,110,117,122,107,115,127,112,123,133,119,131,139,127,139,149,138,148,160,151,159,172,164,174,189,183,185,200,196,187,202,200,85,101,83,62,75,48,58,67,38,55,61,37,51,56,35,47,53,33,46,53,34,48,55,38,49,55,40,51,56,41,53,58,44,55,62,46,59,67,45,68,71,48,81,84,59,104,96,74,116,103,83,127,109,92,133,116,97,127,121,97,127,127,107,118,124,106,114,125,108,122,131,117,129,136,123,136,145,133,141,152,141,149,162,153,158,171,163,168,183,178,180,195,191,186,200,199} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h new file mode 100644 index 0000000..09d0ca3 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h @@ -0,0 +1,43 @@ +#define CONV1_IM_DIM 32 +#define CONV1_IM_CH 3 +#define CONV1_KER_DIM 5 +#define CONV1_PADDING 2 +#define CONV1_STRIDE 1 +#define CONV1_OUT_CH 32 +#define CONV1_OUT_DIM 32 + +#define POOL1_KER_DIM 3 +#define POOL1_STRIDE 2 +#define POOL1_PADDING 0 +#define POOL1_OUT_DIM 16 + +#define CONV2_IM_DIM 16 +#define CONV2_IM_CH 32 +#define CONV2_KER_DIM 5 +#define CONV2_PADDING 2 +#define CONV2_STRIDE 1 +#define CONV2_OUT_CH 16 +#define CONV2_OUT_DIM 16 + +#define POOL2_KER_DIM 3 +#define POOL2_STRIDE 2 +#define POOL2_PADDING 0 +#define POOL2_OUT_DIM 8 + +#define CONV3_IM_DIM 8 +#define CONV3_IM_CH 16 +#define CONV3_KER_DIM 5 +#define CONV3_PADDING 2 +#define CONV3_STRIDE 1 +#define CONV3_OUT_CH 32 +#define CONV3_OUT_DIM 8 + +#define POOL3_KER_DIM 3 +#define POOL3_STRIDE 2 +#define POOL3_PADDING 0 +#define POOL3_OUT_DIM 4 + +#define IP1_DIM 4*4*32 +#define IP1_IM_DIM 4 +#define IP1_IM_CH 32 +#define IP1_OUT 10 diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h new file mode 100644 index 0000000..8d92d21 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h @@ -0,0 +1,26 @@ +#define CONV1_WT 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+ +#define CONV1_BIAS {-49,-18,-7,-20,-12,-15,7,2,-10,-84,-72,-65,-53,-6,-87,-63,-64,-28,-28,-4,-3,-10,-52,-15,-5,-7,-31,-44,-102,-19,-5,-65} + +#define CONV2_WT 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+ +#define CONV2_BIAS {55,50,34,43,-37,35,-21,10,35,-53,-76,7,14,-1,92,20} + +#define CONV3_WT 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+ +#define CONV3_BIAS {18,36,-46,-45,64,8,13,-19,28,1,14,-57,23,20,-2,32,48,-11,85,73,-7,52,125,33,125,13,92,-72,89,-1,11,70} + +#define IP1_WT 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34,-1,-20} + +#define IP1_BIAS {30,-121,-51,77,40,20,46,-35,28,-33} + +#define CONV1_BIAS_LSHIFT 6 +#define CONV1_OUT_RSHIFT 9 +#define CONV2_BIAS_LSHIFT 4 +#define CONV2_OUT_RSHIFT 9 +#define CONV3_BIAS_LSHIFT 1 +#define CONV3_OUT_RSHIFT 7 +#define IP1_BIAS_LSHIFT 1 +#define IP1_OUT_RSHIFT 8 +#define INPUT_MEAN_SHIFT {125,123,114} +#define INPUT_RIGHT_SHIFT {8,8,8} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt new file mode 100644 index 0000000..774fef8 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_cifar10 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h new file mode 100644 index 0000000..ddf354d --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h @@ -0,0 +1,44 @@ +/*------------------------------------------------------------------------------ + * MDK - Component ::Event Recorder + * Copyright (c) 2016 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 +// <1048576=>1048576 +// Configure size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=1048576) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 1 + +// SysTick Configuration +// Configure values when Time Stamp Source is set to SysTick + +// SysTick Input Clock Frequency [Hz] <1-1000000000> +// Defines SysTick input clock (typical identical with processor clock) +#define SYSTICK_CLOCK 100000000U + +// SysTick Interrupt Period [us] <1-1000000000> +// Defines time period of the SysTick timer interrupt +#define SYSTICK_PERIOD_US 1000U + +// + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..9fc447d --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,242 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66829ad --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..16e56b0 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f08df7a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..dae6439 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..070fa1e --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..26edb9f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup_ARMCM7.s + * @brief CMSIS Core Device Startup File for + * ARMCM7 Device Series + * @version V5.00 + * @date 26. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __etext; +extern uint32_t __data_start__; +extern uint32_t __data_end__; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __StackTop; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#endif + +#ifndef __NO_SYSTEM_INIT +extern void SystemInit (void); /* CMSIS System Initialization */ +#endif + + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void); /* Default empty handler */ +void Reset_Handler(void); /* Reset Handler */ + + +/*---------------------------------------------------------------------------- + User Initial Stack & Heap + *----------------------------------------------------------------------------*/ +#ifndef __STACK_SIZE + #define __STACK_SIZE 0x00000400 +#endif +static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +#ifndef __HEAP_SIZE + #define __HEAP_SIZE 0x00000C00 +#endif +#if __HEAP_SIZE > 0 +static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M7 Processor Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* ARMCM7 Specific Interrupts */ +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { + /* Cortex-M7 Exceptions Handler */ + (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External interrupts */ + WDT_IRQHandler, /* 0: Watchdog Timer */ + RTC_IRQHandler, /* 1: Real Time Clock */ + TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ + TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ + MCIA_IRQHandler, /* 4: MCIa */ + MCIB_IRQHandler, /* 5: MCIb */ + UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ + UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ + UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ + UART4_IRQHandler, /* 9: UART4 - not connected */ + AACI_IRQHandler, /* 10: AACI / AC97 */ + CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ + ENET_IRQHandler, /* 12: Ethernet */ + USBDC_IRQHandler, /* 13: USB Device */ + USBHC_IRQHandler, /* 14: USB Host Controller */ + CHLCD_IRQHandler, /* 15: Character LCD */ + FLEXRAY_IRQHandler, /* 16: Flexray */ + CAN_IRQHandler, /* 17: CAN */ + LIN_IRQHandler, /* 18: LIN */ + I2C_IRQHandler, /* 19: I2C ADC/DAC */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + 0, /* 27: Reserved */ + CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ + 0, /* 29: Reserved - CPU FPGA */ + UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ + SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0UL; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + SystemInit(); +#endif + +#ifndef __START +#define __START _start +#endif + __START(); + +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + + while(1); +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..b69f038 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..65bfaca --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..b3b3076 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..2df6879 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..f29db07 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..6cd8e76 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp new file mode 100644 index 0000000..340dc33 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_gru.cpp +* +* Description: Gated Recurrent Unit Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GRUExample Gated Recurrent Unit Example + * + * \par Description: + * \par + * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected, + * Tanh/Sigmoid activation functions. + * + * \par Model definition: + * \par + * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden + * state. + * \par + * The computation can be summarized as: + * 
z[t] = sigmoid( W_z ⋅ {h[t-1],x[t]} )
+ * r[t] = sigmoid( W_r ⋅ {h[t-1],x[t]} ) 
+ * n[t] = tanh( W_n ⋅ [r[t] × {h[t-1], x[t]} ) 
+ * h[t] = (1 - z[t]) × h[t-1] + z[t] × n[t]
+ * \image html GRU.gif "Gate Recurrent Unit Diagram" + * + * \par Variables Description: + * \par + * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n). + * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays + * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history + * + * \par + * The buffer is allocated as: + * \par + * | reset | input | history | update | hidden_state | + * \par + * In this way, the concatination is automatically done since (reset, input) and (input, history) + * are physically concatinated in memory. + * \par + * The ordering of the weight matrix should be adjusted accordingly. + * + * + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fully_connected_mat_q7_vec_q15_opt() + * - arm_nn_activations_direct_q15() + * - arm_mult_q15() + * - arm_offset_q15() + * - arm_sub_q15() + * - arm_copy_q15() + * + * Refer + * \link arm_nnexamples_gru.cpp \endlink + * + */ + +#include +#include +#include +#include "arm_nnexamples_gru_test_data.h" +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +#define DIM_HISTORY 32 +#define DIM_INPUT 32 +#define DIM_VEC 64 + +#define USE_X4 + +#ifndef USE_X4 +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2; +#else +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4; +#endif + +static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS; +static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS; +static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS; + +static q15_t test_input1[DIM_INPUT] = INPUT_DATA1; +static q15_t test_input2[DIM_INPUT] = INPUT_DATA2; +static q15_t test_history[DIM_HISTORY] = HISTORY_DATA; + +q15_t scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT]; + +void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size, + q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state, + q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state) +{ + q15_t *reset = scratch_input; + q15_t *input = scratch_input + history_size; + q15_t *history = scratch_input + history_size + input_size; + q15_t *update = scratch_input + 2 * history_size + input_size; + q15_t *hidden_state = scratch_input + 3 * history_size + input_size; + + // reset gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset, + reset, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15, + bias_reset, reset, NULL); +#endif + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID); + arm_mult_q15(history, reset, reset, history_size); + + // update gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#endif + + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID); + + // hidden state calculation +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#endif + + // tanh function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH); + arm_mult_q15(update, hidden_state, hidden_state, history_size); + + // we calculate z - 1 here + // so final addition becomes substraction + arm_offset_q15(update, 0x8000, update, history_size); + // multiply history + arm_mult_q15(history, update, update, history_size); + // calculate history_out + arm_sub_q15(hidden_state, update, history, history_size); + + return; +} + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("Start GRU execution\n"); + int input_size = DIM_INPUT; + int history_size = DIM_HISTORY; + + // copy over the input data + arm_copy_q15(test_input1, scratch_buffer + history_size, input_size); + arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size); + + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete first iteration on GRU\n"); + + arm_copy_q15(test_input2, scratch_buffer + history_size, input_size); + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete second iteration on GRU\n"); + + return 0; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h new file mode 100644 index 0000000..4fd2bb0 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h @@ -0,0 +1,23 @@ +#define UPDATE_GATE_WEIGHT_X2 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+ +#define UPDATE_GATE_WEIGHT_X4 {-62,78,83,104,-68,28,-33,-63,-58,104,-89,17,-70,83,-16,-85,-80,-116,1,-40,-42,101,-9,40,-93,-83,31,4,-104,23,107,-39,101,88,95,-110,-81,74,-16,-99,121,-111,-83,-98,42,73,-74,50,71,18,18,-89,-63,-20,-4,123,-98,120,-5,-84,-128,-88,-109,-13,44,66,-100,-69,-105,-126,55,-25,-16,-8,-73,-22,-51,70,-68,-11,25,-91,62,-29,-88,16,19,-28,34,-41,-22,110,-39,121,116,-29,-16,55,42,-124,-7,20,66,-69,9,-67,-125,103,52,104,-29,117,60,-40,-78,-100,63,-40,-94,-1,15,1,-76,-25,71,-97,-2,-12,-76,-68,-63,-62,-127,31,31,32,71,-89,-25,-75,-103,15,120,-32,78,-20,-66,-78,124,77,41,31,38,101,-118,-92,-13,16,-23,40,-71,-51,-120,-97,127,107,59,-52,-80,-54,28,59,-22,-52,54,-89,33,-78,51,41,-2,-17,32,124,82,34,-105,-102,-87,-95,-109,54,26,-9,-47,-53,85,48,-31,-40,38,56,86,103,-5,37,-59,24,-114,-55,44,13,-122,-46,-97,42,90,81,-98,-75,-14,119,-88,5,105,-20,-123,-37,-19,-118,43,-45,24,29,95,36,-30,-10,115,106,-12,110,11,84,42,83,14,57,49,-80,-35,-127,10,-74,121,-10,-56,-8,85,50,-120,37,44,-34,37,15,-25,-44,98,-114,16,-88,83,-87,-31,6,-98,-53,25,88,-54,18,111,8,127,115,88,19,-78,61,-96,66,-111,7,-49,-67,-114,-108,-65,-67,114,93,111,80,-100,-6,28,107,-17,-48,-74,-11,-31,-68,-111,25,40,-61,-18,31,33,25,66,25,35,38,19,29,74,-82,-43,71,31,-59,48,-70,112,62,119,121,-23,0,53,25,-80,-31,-26,-4,102,106,41,-7,74,17,-81,-6,89,-44,-27,53,-123,-60,55,-17,87,62,-54,19,-126,116,32,-67,-121,-64,-113,109,-66,45,110,117,97,70,125,-103,-86,-90,-118,12,125,-114,-108,97,-21,-68,15,20,58,57,-17,112,16,121,26,-65,8,24,70,-66,13,-43,-109,74,-67,-127,-55,29,41,-104,-16,-42,59,29,42,-31,88,-69,81,35,-85,-87,78,-125,-82,4,-55,-17,27,54,16,-98,-89,5,109,95,66,101,67,-39,-52,-82,118,18,54,56,-74,-88,-39,65,57,43,33,-63,-19,-113,-16,-57,86,89,72,-73,77,-91,-68,1,-10,-8,126,80,-122,112,-19,37,110,-51,-7,-27,-109,-75,-50,10,-17,67,58,-42,78,-5,-84,4,103,-50,-88,79,15,60,-3,-18,94,81,2,-55,16,23,-61,-16,66,68,-52,44,-23,-114,51,-103,39,-111,-110,-88,34,92,-91,-23,96,-123,-35,111,31,72,-60,-80,-64,24,61,43,88,58,-1,-17,75,-7,-108,42,-38,-125,55,53,-108,23,31,-11,117,96,73,114,38,-13,-26,126,38,25,75,-105,-113,-88,-57,96,65,-105,-9,120,-92,13,9,-128,0,-70,-92,-25,-3,-40,59,85,124,-82,-30,29,93,-38,14,-17,-39,103,-27,-43,-100,3,-95,23,-91,-37,-55,2,125,-121,107,76,-34,58,52,-110,72,54,85,108,-83,16,110,-43,12,30,-31,-116,-68,-44,84,66,-83,28,-78,22,-86,89,65,60,-79,-81,21,0,-118,6,92,-6,11,-8,56,-108,60,27,87,126,-106,-80,-3,-34,-116,88,35,64,-38,-42,33,-125,53,22,-24,126,-79,75,-94,-45,85,-116,15,-69,-11,-116,77,28,91,-29,-109,-41,-22,81,-94,-70,100,-3,95,94,82,31,-89,-81,97,-80,-1,-116,-2,5,88,42,111,119,-113,-46,116,5,36,105,74,-40,-64,-21,93,-105,-110,-109,7,105,-62,78,-11,-20,-74,64,91,5,101,-34,35,54,-112,72,21,-32,-91,46,51,-124,32,-95,-59,90,-6,120,21,-83,98,60,36,6,29,44,25,-17,10,-29,-41,40,-19,-18,57,65,110,4,-56,51,89,87,-50,112,-12,109,109,-50,34,38,-123,-115,-88,-38,85,25,-32,-27,-18,37,-30,-13,87,-52,20,-84,9,1,18,-106,118,87,-19,103,-81,85,23,76,21,44,-45,-50,-120,36,106,78,40,101,-120,-49,20,-119,115,16,78,-102,2,68,18,20,-72,-20,-103,104,70,119,75,-113,11,23,83,107,100,43,64,-67,44,-88,117,18,126,105,-9,44,-63,-85,98,119,63,4,-82,-48,30,-21,115,-53,114,16,-62,-42,123,-84,-39,-7,106,83,-11,-39,25,-8,15,-114,104,106,-9,31,84,23,52,-54,-13,-34,88,-76,46,74,77,80,-40,-51,101,68,64,77,-104,-40,73,82,108,-111,125,19,-13,-75,52,-116,33,-104,34,-41,125,60,116,-118,-54,109,65,77,6,82,-114,-29,-47,-6,57,-96,-128,-121,85,-91,2,81,-2,-43,115,114,-117,-102,-80,-76,7,-124,-65,-1,100,-82,-20,64,-73,-75,82,32,98,121,-75,27,72,34,-109,-117,-83,-98,-24,-24,99,21,43,64,-125,-88,-91,36,-94,-87,-106,-100,-97,115,95,59,-39,-29,-4,-36,-46,-84,15,-121,-127,-45,58,-46,-94,4,-21,29,123,-111,-128,4,53,45,-27,73,29,-44,-80,-94,-117,-109,100,-78,-84,-18,53,101,-25,-7,-27,84,44,101,28,108,105,60,95,-95,-126,-24,-59,-61,15,15,88,-71,-11,-90,94,-59,25,112,-38,126,58,-48,-64,-114,-88,71,122,36,112,1,82,-14,62,39,-62,-42,127,106,58,52,-28,-85,95,-126,50,109,5,-45,-86,-68,125,105,-6,-100,-102,74,-83,-18,-9,-127,90,-33,-18,-68,-100,48,101,-41,-86,-94,104,-68,-124,57,22,-93,17,-22,108,-99,21,13,-91,-25,-64,31,-22,-86,50,-71,-100,66,73,85,-102,-27,-27,-43,-92,-23,-17,-70,-31,69,115,122,86,4,-11,127,-105,92,85,-70,33,123,-40,125,-49,-95,-112,115,-43,124,84,117,-82,-87,61,-61,114,-32,104,-8,57,-71,62,18,-31,-18,30,18,112,94,-84,49,-7,123,-119,-90,-92,103,5,-101,-26,37,78,-31,-92,-1,-10,-50,-21,-111,35,-50,90,-60,-89,-73,60,124,-45,-2,-13,96,-96,-18,48,54,-75,31,-125,-1,-34,-64,88,93,-19,-98,-83,75,-80,-69,-91,16,-75,104,29,-6,92,112,12,21,15,-38,-33,-24,118,-56,-2,56,127,127,-14,94,-38,127,83,113,29,-48,-80,97,-50,-48,-109,-57,61,-96,41,4,-111,-4,-26,85,67,-108,-14,106,76,-113,-31,-12,-2,-30,-29,-76,-7,80,-41,26,63,94,-5,116,58,-39,-13,-76,95,44,-79,-109,-72,-101,-81,-104,26,-122,-42,38,-116,-6,-24,48,-91,112,-109,-103,-45,38,46,-82,-19,99,107,-119,-20,-52,114,-91,-102,49,62,35,97,-38,-14,112,111,107,-35,108,125,110,11,115,80,47,36,54,22,76,26,69,55,11,-65,-50,27,100,-2,-116,26,-73,76,37,-88,109,-2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+ +#define RESET_GATE_WEIGHT_X2 {65,-28,-36,70,67,55,86,-53,23,25,-19,59,67,43,-92,48,94,-113,60,-58,24,76,-15,-19,15,36,-74,115,-59,3,34,-43,21,-125,-45,127,92,-5,-65,-103,-83,51,42,109,-51,-39,-97,-64,-4,57,79,-42,88,-4,-108,83,-4,20,86,82,-87,95,12,-69,28,30,-97,-13,-33,-48,75,119,18,31,-83,-59,-114,-21,127,34,-27,-26,-47,86,-83,-49,8,29,-48,-31,-94,-59,-49,-36,0,28,-64,113,65,-8,47,-55,-49,112,-40,-39,-100,-42,32,82,27,-78,-105,3,19,88,15,-121,-120,7,-9,-107,-23,104,114,66,113,-102,-90,24,80,-34,106,48,-91,-11,22,-96,-82,75,26,-42,59,-45,23,78,79,-76,6,20,63,-118,-125,-42,111,-80,-79,-59,-121,-79,83,49,-95,-49,81,15,-11,-54,-45,64,-30,-49,81,-57,71,91,113,-46,-63,-4,-96,-95,-27,5,-52,35,67,112,58,-62,48,112,106,80,-19,103,4,-32,-118,-74,12,13,-126,-20,-5,115,-74,-30,123,-74,-66,11,-99,-16,-102,-100,-81,-20,-24,92,-79,-31,44,-24,-85,-123,5,-52,-111,73,29,28,-19,18,23,-112,-32,-52,-38,99,-59,-52,-31,87,124,28,-42,-39,81,-87,-24,16,47,20,36,1,-70,121,124,13,1,30,112,87,-86,11,36,-18,74,-104,-100,-14,0,-24,28,-53,53,66,-63,-109,-10,-50,-15,63,34,82,-59,85,-44,105,-10,-27,99,5,-105,-69,-75,2,-47,-66,71,-30,73,-11,-45,93,47,-37,-34,-8,90,-106,103,112,65,-100,-25,-13,38,74,54,27,-81,-8,19,49,94,118,-121,-116,120,-71,-87,36,-65,-112,8,-59,-106,-40,-16,68,87,-109,53,12,-7,9,6,67,78,8,-42,-123,79,-93,-102,-40,12,-66,-109,47,15,-8,-5,51,-62,111,8,-66,-82,-102,120,68,-67,9,-73,-69,-79,56,-36,-10,-69,-99,-2,-11,-66,76,37,4,92,1,-89,74,85,-124,-25,40,106,-102,42,-19,-30,0,-70,82,84,106,-84,48,16,37,33,-114,38,-29,-117,51,101,26,56,127,-81,-76,38,-124,103,-25,54,-21,-112,40,102,3,63,36,-54,16,-18,114,39,5,105,83,117,-92,-5,-14,-102,-87,-48,-77,-19,-82,-55,119,-95,-43,97,126,-48,-50,-97,-25,-102,-53,47,111,66,-82,-16,-38,76,-15,23,20,88,-19,125,-90,107,-31,102,107,30,-111,71,38,26,43,-85,82,29,-99,126,-109,21,-42,-107,-115,-123,30,-46,39,4,-19,-44,-69,86,41,4,33,57,-110,95,-22,123,71,1,119,77,90,105,81,-68,74,-38,-109,6,-82,-20,-115,-104,38,27,-44,82,-107,99,-41,-28,-55,100,10,-42,7,91,56,-91,113,-91,70,-66,-48,-18,109,-27,42,-89,-20,-63,-41,77,-13,73,10,-74,-51,88,28,50,-5,7,92,18,-98,-41,-14,8,-16,99,30,-109,7,52,110,-120,-17,33,53,1,106,-99,-14,-93,-46,-60,7,-54,100,91,93,89,-84,118,58,-84,38,57,-24,-25,22,-52,119,-85,-75,-79,60,-97,1,-13,54,-43,98,-92,65,37,-110,64,21,-18,-111,-9,86,90,42,-71,-29,86,-10,-15,-20,106,-45,-22,44,105,55,-61,-89,-119,31,93,-97,-35,9,-113,86,-113,22,-68,-29,-36,-123,98,79,34,-29,71,44,49,56,93,4,63,-3,45,12,54,-96,27,-55,-72,84,69,27,-28,-111,-57,-41,92,-106,-90,55,105,-60,94,34,94,-1,112,-86,-55,-58,68,-65,37,110,-107,-62,66,61,-69,-52,27,-61,70,-56,-116,-101,-103,127,-98,-79,25,-117,40,33,111,10,-3,-65,1,84,-41,5,-93,-85,-96,78,54,43,70,77,-53,-71,-38,48,103,-88,115,94,20,-5,-125,-7,-61,30,-25,-57,-42,-100,63,-114,40,-53,123,50,-7,121,75,67,75,3,-38,-101,-44,-46,54,38,-22,4,18,102,-126,44,86,-10,-1,118,98,102,-125,74,32,18,74,73,72,64,47,105,-72,5,73,98,9,39,18,10,-68,81,-128,-89,27,-51,51,16,119,-71,-53,51,-84,107,-116,7,73,106,20,52,-85,-74,-103,-18,29,-13,73,106,-92,107,-115,5,65,83,-79,-7,98,-42,-33,82,-64,75,-32,100,-67,-122,84,43,-111,114,-99,46,12,99,43,50,-24,-88,-60,111,68,64,54,-105,-120,119,68,5,51,63,89,-57,-75,-25,-35,-28,42,-64,101,-103,-35,-99,-96,-18,-64,-94,-46,89,-65,-38,-1,-97,127,-67,84,-18,86,115,60,-78,-109,-61,-93,-67,-87,-80,124,26,-9,111,115,-88,-71,-86,-71,-65,-15,108,-25,111,9,86,-115,-55,-23,57,27,103,108,-28,65,86,68,114,62,126,-4,33,-34,-123,87,-76,-104,-126,26,-13,44,108,105,12,-35,-58,3,-5,-32,91,49,89,88,37,38,119,-125,-48,37,53,85,-73,67,116,-116,-127,103,127,-115,92,-35,-83,-45,25,-96,-13,-90,41,-27,105,119,85,27,-3,-64,93,17,-53,104,-70,-43,65,45,-90,61,-31,-49,-99,84,46,93,-37,84,-79,13,-59,-76,62,19,-11,-96,-104,-3,-8,-78,92,98,50,-7,-39,-82,37,-126,127,-113,67,94,115,-9,-33,-57,26,-67,9,28,-8,81,-98,-10,84,34,111,-95,127,75,38,-7,-2,-71,-62,-72,99,-74,25,123,114,51,-28,103,-110,43,113,7,58,75,-95,-52,19,-112,101,26,65,-115,-91,85,-5,-45,110,-103,-34,-69,50,-15,-19,-110,-44,-7,-112,-93,29,50,-84,-55,-41,11,19,-31,-47,-62,-12,-105,-47,68,-124,-47,-113,-55,30,25,55,-14,85,-66,-5,-105,62,-27,-89,-124,-84,112,34,52,25,104,32,-30,84,-46,-38,60,-2,-107,-95,-86,-25,117,60,-121,32,84,8,-88,-1,91,-46,-76,81,44,79,105,-105,82,20,59,-115,96,21,-113,19,92,122,76,36,-112,78,16,38,73,69,54,97,41,-49,78,-71,-69,95,-85,117,10,-98,25,72,126,47,-17,4,-44,-32,-16,-12,105,76,4,-82,-91,-21,-117,30,-67,46,-8,-125,84,-51,94,0,-60,127,99,43,60,16,55,-16,-121,-61,-115,38,25,17,35,23,68,9,-107,-44,118,119,43,99,-95,40,42,-70,54,19,92,-36,82,-35,122,-96,54,-29,-50,100,-79,-71,-99,-60,-2,-100,41,97,-93,-58,-123,126,-102,81,-5,83,110,-50,58,-86,41,-126,43,-49,98,-59,94,-91,115,16,-3,-58,-30,-109,110,-114,124,22,-88,-79,-29,-100,54,-33,23,-1,-77,52,-126,114,70,-50,90,82,-13,-25,-125,16,48,101,-93,19,-103,67,-1,-32,28,-72,-26,73,45,-22,83,-68,-61,89,57,-37,90,16,-38,-124,47,-5,-113,81,71,-30,-46,-18,-52,-104,-40,49,-101,106,38,6,125,-70,25,-88,-50,-77,-12,53,110,-84,23,-109,-53,112,2,88,101,-55,-10,-72,123,-35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+ +#define RESET_GATE_WEIGHT_X4 {65,28,-28,30,-90,106,24,80,-36,-97,70,-13,80,-19,-34,103,67,-33,55,-48,106,4,48,-32,86,75,-53,119,-91,-118,-11,-74,23,18,25,31,22,12,-96,13,-19,-83,59,-59,-82,-126,75,-20,67,-114,43,-21,26,-5,-42,115,-92,127,48,34,59,-74,-45,-30,94,-27,-113,-26,23,123,78,-74,60,-47,-58,86,79,-66,-76,11,24,-83,76,-49,6,-99,20,-16,-15,8,-19,29,63,-102,-118,-100,15,-48,36,-31,-125,-81,-42,-20,-74,-94,115,-59,111,-24,-80,92,-59,-49,3,-36,-79,-79,-59,-31,34,0,-43,28,-121,44,-79,-24,21,-64,-125,113,83,-85,49,-123,-45,65,127,-8,-95,5,-49,-52,92,47,-5,-55,81,-111,15,73,-65,-49,-103,112,-11,29,-54,28,-83,-40,51,-39,-45,-19,64,18,42,-100,109,-42,-30,23,-49,-112,-51,32,-39,82,81,-32,-57,-52,-97,27,-64,-78,71,-38,91,99,-4,-105,57,3,113,-59,-46,-52,79,19,-42,88,-63,-31,-4,87,88,15,-4,-121,-96,124,-95,28,-108,-120,83,7,-27,-42,5,-39,-4,-9,20,-107,-52,81,35,-87,86,-23,82,104,67,-24,112,16,-87,114,95,66,58,47,-62,20,12,113,-69,-102,48,36,112,1,-70,54,121,27,-2,-102,-11,-87,124,-81,13,-8,-66,-48,76,-77,1,19,30,49,37,-19,4,-82,112,94,87,118,92,-55,1,119,-86,-121,11,-116,-89,-95,74,-43,36,120,-18,-71,85,97,-124,126,74,-87,-104,36,-25,-48,40,-50,-100,-65,-14,-112,106,-97,-102,-25,0,8,-24,-59,42,-102,-19,-53,28,-106,-53,-40,-30,47,0,111,53,-16,66,68,-70,66,82,-82,-63,87,-109,-109,84,-16,106,-38,-10,53,-50,12,-84,76,48,-15,-15,-7,63,9,16,23,37,20,34,6,82,67,33,88,-114,-19,-59,78,85,8,38,125,-29,-90,-44,-42,105,-123,-117,107,51,-31,-10,79,-27,-93,101,102,26,107,99,-102,5,-40,56,30,127,-111,-105,12,-69,-66,-81,71,-76,38,-75,-109,2,47,38,26,-124,43,-47,15,-66,-8,103,-85,-25,82,71,-5,-30,51,54,29,-21,-99,73,-62,-11,111,-112,126,40,-109,-45,8,93,-66,102,21,3,-42,47,-82,-37,-102,63,-107,36,-115,-34,120,-8,68,-54,-123,16,30,90,-67,-106,9,-18,-46,114,39,103,-73,112,-69,39,4,5,-19,65,-79,-100,56,105,-44,83,-69,-25,-36,-13,-10,117,86,-92,41,38,-69,74,-99,-5,4,-14,33,57,-41,-110,-14,-15,68,-20,-65,95,8,-22,-16,106,37,-45,110,123,99,71,30,-22,-107,44,-62,1,-109,119,7,105,66,55,61,77,52,90,110,-61,-69,-89,-52,105,-120,81,-17,-119,27,31,-61,-68,33,74,53,93,70,-97,-56,-38,1,-109,106,-35,-116,9,-101,6,-99,-82,-14,-113,-103,86,127,-20,-93,-115,-46,-113,-98,22,-79,-104,-60,38,7,-68,25,-29,-117,27,-54,-44,100,-36,40,-123,33,82,91,-107,93,98,111,79,10,99,89,-41,-84,34,-3,-29,-65,-28,118,-55,58,71,1,44,84,100,-84,10,38,49,-41,56,5,-42,57,7,-24,93,-93,4,-85,91,-25,56,22,63,-96,-3,78,-91,-52,113,119,45,54,12,43,-91,-85,70,-75,54,70,-96,77,-66,-79,-48,60,27,-53,-55,-71,-18,-97,109,1,-72,-38,84,48,-27,-13,42,54,69,103,27,-88,-89,-43,-20,98,-28,115,-111,94,-63,-92,-41,65,-57,20,-41,-5,77,37,-13,-110,92,-125,-106,-7,73,64,10,21,-90,-61,55,30,-74,-18,-51,-111,105,-25,-60,-57,88,-9,28,86,94,-42,34,-100,50,90,-5,42,94,63,-1,-114,7,-71,92,-29,112,40,-86,-53,18,86,-98,-10,-55,123,-58,50,-7,-103,121,-18,-46,-35,89,-58,75,29,67,-13,-65,3,-38,-5,75,73,3,106,-1,-32,-97,91,-38,-92,-101,107,127,49,-67,89,-44,-115,-46,5,84,88,-18,37,54,65,38,83,86,38,115,119,-22,-79,4,-7,60,-125,-78,-48,18,98,102,-42,-109,37,-61,53,-126,-33,44,82,-93,85,-67,-73,86,-64,-10,75,-87,67,-80,116,-1,-32,118,100,124,-116,26,-127,98,-67,102,-122,-9,103,111,127,-125,84,74,43,115,-115,-88,92,32,-111,18,114,-71,-35,-86,-83,74,-99,73,46,-71,-45,-65,25,72,12,64,99,-15,-96,108,-13,47,43,105,50,-25,-90,111,41,-72,-24,5,-88,9,-27,86,105,73,-60,98,111,-115,119,-55,85,9,68,39,64,-23,27,57,-3,18,54,10,-105,27,-64,103,93,-68,-120,81,119,108,17,-28,-53,-128,68,-89,5,65,104,86,-70,27,51,-51,63,68,-43,114,65,51,89,16,-57,62,45,126,-90,119,-75,-71,-25,-4,61,33,-31,-53,-35,51,-28,-34,-49,-123,-99,-84,42,107,-64,87,84,-76,46,-116,101,7,-103,-104,93,-126,-37,73,-35,106,-99,26,84,-13,-79,20,-96,52,-18,44,13,108,-59,-85,-64,-74,-94,105,-76,12,62,19,-115,-11,-91,117,-67,60,46,-96,85,-104,-5,-121,-8,32,-125,-3,-45,-8,110,84,84,8,-51,-78,-103,92,-34,-88,94,-1,0,98,-69,50,50,91,-60,-46,127,-7,-15,-39,-19,-76,99,81,43,-82,-110,37,-44,44,60,79,16,-126,-7,127,-112,105,55,-105,-16,-113,-93,67,29,82,-121,20,-61,94,50,115,-84,59,-115,-115,38,-9,-55,-33,-41,96,25,21,17,-57,11,26,19,-113,35,19,23,-67,-31,9,-47,92,68,122,9,28,-62,-8,-12,76,-107,36,-44,81,-105,-98,-47,-112,118,78,119,-10,68,84,-124,16,43,38,99,34,-47,111,-113,73,-95,69,40,-95,-55,127,30,54,42,97,-70,75,25,38,55,41,54,-49,19,-7,-14,-2,85,78,92,-71,-36,-71,-66,-62,-5,-69,82,95,-35,-72,-105,99,62,-85,122,117,-96,-74,-27,25,-89,10,54,-98,-29,123,-124,114,-84,25,-50,72,100,51,112,-28,34,126,-79,47,-71,103,52,-110,25,-17,-99,4,-60,43,104,113,32,-44,-2,-32,-100,7,-30,58,84,-16,41,-12,97,75,-46,-95,-38,105,-93,76,-58,-52,60,19,-2,4,-123,-82,126,-112,-107,101,-95,-91,-102,-21,81,26,-86,65,-25,-117,-5,30,83,110,-38,-50,-124,57,-31,-16,13,58,47,-86,-5,114,71,-98,63,41,-113,-126,81,101,-126,81,107,43,71,-49,-30,34,115,-83,-100,98,-46,-59,-18,-8,27,3,39,94,-52,-91,-104,-27,10,5,75,115,-40,16,49,110,-128,-24,58,-3,-101,-58,106,-80,103,9,-104,-30,38,-109,6,85,126,-108,-59,110,125,-114,-70,96,31,-93,89,124,25,22,-88,-34,-67,76,97,-88,-50,-79,-77,-107,-96,71,-69,-29,-12,-100,53,84,87,-98,19,5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+ +#define HIDDEN_STATE_WEIGHT_X2 {-3,-33,59,21,117,70,0,44,108,108,-47,-80,-118,34,88,-91,-123,-108,8,51,26,82,-80,107,-100,-69,97,-90,17,19,63,111,-40,-125,110,24,58,-69,26,-31,-65,-37,-47,-41,-109,106,-100,108,-99,108,116,104,86,-50,-45,10,-53,112,34,96,-10,-39,-32,-25,69,102,-2,-4,-25,121,-1,-28,-48,-100,0,-128,60,-73,42,-32,118,-88,-113,-112,-113,70,-98,118,95,77,-52,123,-99,72,26,-102,-32,120,113,22,6,-68,84,-33,103,66,111,60,-76,33,10,25,-43,93,41,-79,110,13,67,107,-113,90,58,64,-125,79,-85,-18,76,80,-59,11,-18,-74,15,-102,99,-19,117,99,65,-50,-108,-121,-9,-104,33,94,-95,110,-48,-97,76,36,1,-58,86,-115,45,-88,38,51,123,-23,-20,-43,-37,15,91,-85,-88,6,-96,58,78,13,23,1,-43,62,-70,-108,44,30,74,90,79,-80,-20,71,-21,0,60,19,-59,-52,44,-14,77,92,-69,121,-123,-27,119,-84,79,87,24,85,118,1,-51,-96,60,102,-6,15,96,120,-109,6,35,11,-119,-109,-18,16,-112,91,-126,71,-29,121,-21,-120,37,57,-117,-39,93,56,-73,-104,77,-107,-52,111,-61,-4,44,-119,67,72,-66,36,-127,-113,-124,123,21,98,84,86,76,23,78,7,-127,-4,1,-46,-107,59,-21,53,-65,-99,-15,-98,53,-31,7,64,7,105,51,-75,50,-52,48,101,-126,-120,5,34,3,81,-39,70,41,112,25,30,79,-6,107,-11,-97,92,-84,67,49,107,60,101,-37,27,-91,-61,-96,120,-113,87,-46,68,64,102,-86,-60,13,-71,56,-105,90,-9,-35,27,103,120,39,23,-39,-1,-85,-95,-6,119,-41,-2,-69,102,102,-119,-3,-11,-125,-111,40,-115,-41,-117,-44,-7,83,123,-21,23,99,-107,43,100,-99,-3,89,3,-113,103,47,-94,-69,-38,-28,-37,49,-117,-49,-126,17,-98,37,92,55,-116,-70,-50,77,120,47,124,78,114,67,-48,6,-42,-115,85,116,-114,-46,-50,-13,70,-101,110,-55,20,-51,125,-19,-9,-15,46,30,-27,-123,114,-50,-30,-72,76,-83,71,47,-45,74,102,44,108,-26,108,-113,-43,110,-91,37,-69,76,-33,106,-76,-96,20,-117,63,-33,-5,11,-121,-51,63,-56,59,-16,-33,114,74,124,73,99,-50,51,-71,118,106,30,-92,26,-40,119,-121,2,-45,9,0,-5,-2,-89,88,-11,-85,-60,19,81,-96,75,82,-40,124,89,-36,-117,-100,-2,-34,112,101,39,-101,-106,60,59,-126,-32,96,68,-53,87,20,54,-24,46,-95,65,-112,22,60,122,-22,-106,-124,97,-37,-86,95,-110,-8,44,58,-12,-120,-45,-86,-32,-86,-94,-14,15,29,-8,-114,71,70,-93,-69,100,-123,-18,-47,-12,127,104,-102,93,-11,-73,121,87,-79,-92,46,92,-108,-107,79,121,-71,-89,16,-11,-52,72,-114,-32,-60,-9,-57,-4,10,-81,-22,68,74,76,-68,-127,96,-84,69,-3,-26,-106,-3,-87,-65,105,109,122,-103,31,-108,-86,-5,-39,85,88,67,-82,0,-25,93,61,-62,5,-54,-114,-51,-9,-114,20,49,-26,38,19,39,-103,33,-120,37,-97,32,-89,119,111,-124,-99,78,-49,-128,76,-18,-12,-109,96,90,-73,-104,59,-59,-92,123,55,54,-120,-80,-48,-16,-95,96,36,118,-119,-58,93,45,-43,-75,64,38,-2,-72,-111,22,-89,-75,-120,-42,45,108,59,-105,40,27,32,-66,121,-22,-71,-9,118,124,60,-96,47,4,14,-27,64,70,47,-91,-70,1,-44,94,-46,53,4,23,-124,-92,-95,83,-49,-81,40,-80,48,0,39,1,-113,32,40,-21,-1,-110,102,1,-74,-51,40,108,-35,-36,89,84,123,-48,-115,-115,83,-61,114,-127,-61,114,100,-82,-45,60,87,60,19,86,97,-68,40,-66,75,86,-32,-128,88,-57,-27,77,3,-27,43,-39,-62,66,5,-82,45,-104,-78,34,57,96,89,-90,66,-10,37,-110,-30,82,-58,13,94,12,115,35,117,0,80,61,-7,107,-104,-21,21,-70,-93,-94,-51,-61,39,-62,64,-82,-109,76,84,58,-47,-100,52,46,-51,88,91,8,-47,108,-80,25,-58,111,-59,-83,-75,92,98,110,54,106,65,-47,-120,-5,90,-123,101,-61,-85,-93,109,88,0,8,59,86,56,126,17,-26,58,-101,-25,35,0,-123,-3,-56,112,-128,8,17,-52,88,31,-3,105,-56,68,-1,-94,96,-19,10,-22,-88,-10,119,-44,19,42,75,-86,18,-107,89,-82,-120,76,40,84,-122,29,33,-47,17,-50,-13,23,-66,-46,85,-29,-110,42,-68,8,99,-93,-29,101,16,52,-13,127,0,86,-117,-92,-70,-32,-27,127,-123,1,34,-13,92,114,-11,29,-103,-121,-54,20,73,16,74,108,16,-61,89,50,-30,-14,116,44,-31,16,96,24,-51,7,39,-87,-69,-61,-98,61,-46,113,85,-95,103,67,99,-66,-45,-42,-70,96,104,5,-111,69,-25,99,-118,23,109,11,4,-41,-94,73,100,96,6,90,-75,-25,79,-13,-43,-6,-12,51,12,40,124,-56,81,-8,59,-60,-26,-54,33,122,85,53,-99,125,19,-26,94,41,-5,46,-48,-70,-10,41,102,-1,-98,-9,15,29,46,-66,-118,-53,45,119,-127,94,53,-58,90,124,5,-110,-98,-80,-77,77,29,19,105,-121,92,9,-124,50,-119,59,40,67,104,-12,13,103,101,47,-51,34,-66,-101,-117,112,-5,118,-48,-60,-114,38,-71,2,51,114,80,115,-5,116,20,16,-47,-19,30,24,-68,7,-30,-3,-64,-7,-34,-12,44,34,-91,-97,116,112,-99,108,-75,17,26,-14,-61,80,22,-7,34,47,-93,45,106,121,78,43,-97,39,-99,-68,-72,-7,64,-49,-82,-127,78,-64,48,18,15,126,-125,-111,-69,-111,10,-46,111,-75,123,-44,-67,-31,-96,-67,-53,-53,-106,67,-101,23,62,30,9,-114,-12,-57,-38,-78,95,-10,-3,110,88,123,-26,78,-125,114,53,10,-57,26,38,-51,73,92,-124,79,15,75,-62,109,-113,-67,1,35,52,-36,55,7,111,-43,109,101,88,122,-21,-32,-87,59,16,-122,-109,-118,17,-22,-39,53,-105,77,90,-24,-65,43,-27,113,30,-117,-30,106,37,55,59,54,-70,99,99,-73,120,97,-39,-88,-54,101,51,-76,70,-121,-68,23,-73,-31,75,-8,-63,-123,-93,96,-81,99,-95,28,-36,55,-104,32,-64,41,-97,95,-89,126,-26,-25,126,2,-26,-54,110,-86,110,74,-3,-110,56,-60,-49,117,-82,-55,-103,-112,70,-85,85,-63,82,7,75,-61,90,32,35,-115,72,73,-121,63,-84,-52,-29,-59,-4,29,64,119,127,58,-117,48,126,120,-115,-15,-10,27,27,-81,117,-5,121,-72,113,31,-13,10,27,-106,-51,81,-96,-22,19,-78,6,71,-34,123,118,75,-23,-72,-97,111,-121,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+ +#define HIDDEN_STATE_WEIGHT_X4 {-3,69,-33,102,76,60,80,19,59,-2,21,-4,-59,-59,11,-52,117,-25,70,121,-18,44,-74,-14,0,-1,44,-28,15,77,-102,92,108,-48,108,-100,99,-69,-19,121,-47,0,-80,-128,117,-123,99,-27,-118,60,34,-73,65,119,-50,-84,88,42,-91,-32,-108,79,-121,87,-123,118,-108,-88,-9,24,-104,85,8,-113,51,-112,33,118,94,1,26,-113,82,70,-95,-51,110,-96,-80,-98,107,118,-48,60,-97,102,-100,95,-69,77,76,-6,36,15,97,-52,-90,123,1,96,-58,120,17,-99,19,72,86,-109,-115,6,63,26,111,-102,45,35,-88,11,-40,-32,-125,120,38,-119,51,-109,110,113,24,22,123,-18,-23,16,58,6,-69,-68,-20,-112,-43,91,26,84,-31,-33,-37,-126,15,71,-65,103,-37,66,91,-29,-85,121,-47,111,-41,60,-88,-21,6,-120,-109,-76,106,33,-96,37,58,57,-100,10,108,25,78,-117,13,-39,-99,-43,108,93,23,93,1,56,116,41,104,-79,-43,-73,62,-104,86,110,-50,13,-70,77,-108,-107,-45,67,10,107,44,-52,30,111,-53,-113,112,90,74,-61,90,-4,34,58,96,64,79,44,-80,-119,-10,-125,-39,79,-20,67,71,72,-32,-85,-25,-18,-21,-66,0,36,-127,-96,-113,120,49,76,-117,-33,-124,-113,123,87,-49,106,-126,-76,21,-46,98,68,17,-96,-98,20,84,64,86,102,37,-117,92,63,76,-86,23,-60,55,-33,-116,-5,78,13,7,-71,-70,11,-50,-121,-127,56,-4,-105,77,-51,120,63,1,90,-46,-9,47,-56,124,59,-107,-35,59,27,78,-16,114,-33,-21,103,53,120,67,114,-48,74,-65,39,-99,23,6,124,-42,73,-15,-39,-98,-1,-115,99,85,-50,53,-85,-31,-95,116,51,-114,-71,7,-6,64,119,-46,118,-50,106,7,-41,105,-2,-13,30,70,-92,51,-69,-75,102,-101,26,110,-40,50,102,-52,-119,-55,119,20,-121,48,-3,101,-11,-51,2,125,-45,-126,-125,-120,-111,-19,9,-9,0,5,40,34,-115,-15,-5,46,-2,3,-41,81,-117,30,-89,-27,88,-39,-44,70,-7,-123,-11,114,-85,41,83,112,123,-50,-60,-30,19,25,-21,30,23,-72,81,76,-96,79,99,-6,-107,-83,75,71,82,107,43,-11,100,47,-40,-45,124,-97,-99,92,-3,74,89,102,-36,-84,89,67,3,44,-117,108,-100,49,-113,107,103,-26,-2,108,-34,60,47,101,-94,-113,112,-43,101,-37,-69,27,-38,110,39,-91,-101,-91,-28,-61,-37,37,-106,-69,60,59,121,-126,-71,-97,47,32,4,-32,-89,96,16,-89,14,119,-27,68,-11,-53,-52,111,64,-124,70,87,72,20,-114,-99,47,78,-91,54,-32,-24,-60,-49,-70,-128,1,46,-9,-95,-57,76,-44,-18,94,65,-4,-112,10,-12,-46,-109,53,22,-81,60,-22,96,4,90,23,122,68,-22,74,-73,-124,-104,-92,-106,76,-124,-68,59,-95,-59,83,97,-127,-37,96,-92,-49,123,-81,-86,-84,95,69,55,40,54,-80,-110,-3,-8,-26,-120,48,-80,0,44,-106,58,-3,-48,39,-16,1,-12,-87,-120,-65,-95,-113,96,32,-45,105,-86,109,36,40,118,-21,-32,122,-86,-103,-119,-1,-58,-110,-94,31,-14,-108,93,102,45,1,15,-86,29,-5,-43,-74,-75,-51,-8,-39,-114,85,64,40,38,108,71,88,70,67,-2,-35,-72,-36,-93,-82,-69,0,-111,89,22,84,100,-25,-123,93,-89,123,-75,-48,-18,61,-47,-62,-120,-115,-42,-115,-12,5,127,-54,45,83,108,-61,104,-114,-102,-51,59,114,-105,-127,93,-9,-11,-114,40,-61,27,114,-73,20,121,49,32,100,-66,-82,87,-26,-79,38,121,-45,-22,60,-92,19,46,39,-71,87,-9,60,92,-103,-108,33,118,19,124,86,-107,-120,79,37,60,97,-96,-68,40,-51,-66,88,-10,-61,119,89,75,91,86,8,-44,50,19,-30,-32,-47,-128,108,42,-14,75,116,88,-80,-57,25,-86,44,18,-31,-27,-58,77,111,-107,16,89,96,3,-59,-27,-83,-82,24,-120,-51,43,-75,-39,92,76,7,40,39,-62,98,66,110,84,-87,-122,-69,5,54,-82,106,29,-61,33,-98,45,65,-104,-47,-47,61,17,-46,-78,-120,34,-5,-50,113,-13,85,57,90,96,-123,23,-95,-66,103,89,101,-90,-61,-46,67,85,99,66,-85,-10,-93,-29,-66,-110,-45,37,109,-110,88,42,-42,-68,-70,-30,0,82,8,8,96,99,104,-58,59,13,86,-93,5,-29,-111,94,56,12,126,101,69,16,-25,115,17,35,-26,52,99,-13,-118,117,58,0,-101,127,23,0,109,80,-25,61,35,86,11,-117,4,-7,0,107,-123,-92,-41,-70,-94,-104,-3,-21,-56,-32,73,-27,100,21,112,-70,-128,127,96,-123,6,-93,8,-94,17,1,90,34,-75,-51,-52,-61,88,-13,-25,92,79,39,31,-62,-3,114,-13,-11,-43,64,105,-82,-56,29,-6,-103,-12,-109,68,76,-1,-121,51,-54,12,84,-94,58,96,20,40,73,124,-47,-19,-100,10,16,-56,74,81,52,-22,46,-88,108,-8,16,59,-60,-101,-26,-117,-127,-36,78,55,-54,112,33,-5,-64,7,48,111,122,118,85,-48,18,-43,15,109,53,-60,-99,-114,126,101,-125,88,125,38,19,-71,-111,122,-69,-21,-26,2,94,51,-111,-32,10,-87,41,114,-5,80,-46,59,111,16,46,115,-48,-5,-75,-122,123,-109,-70,116,-10,20,-44,-118,-67,17,41,16,102,-47,-31,-22,-96,-39,-1,-19,-98,30,-67,53,-53,-105,-9,24,15,-68,-53,77,-106,90,29,7,46,-30,67,-24,-101,-65,-66,-3,-118,-64,23,43,62,-27,-53,-7,45,-34,30,113,9,30,119,-12,-127,44,-114,-117,-12,-30,94,34,53,-91,-57,106,-38,37,-58,-97,90,116,-78,55,95,59,124,112,5,-99,-10,54,-3,-70,-110,108,-98,-75,110,99,88,99,-80,17,-77,26,123,-73,-26,120,77,-14,29,-61,78,97,-125,-39,19,80,105,22,114,-88,53,-54,-121,-7,92,34,10,101,-57,51,9,47,-124,-93,26,-76,38,70,50,45,-119,106,-51,-121,73,-68,59,121,40,78,92,23,-124,-73,67,43,104,-97,79,-31,15,75,-12,39,13,-99,75,-8,-62,-63,103,-68,101,-72,109,-123,-113,-93,47,-7,-51,64,-67,96,1,-81,34,-49,-66,-82,35,99,52,-95,28,27,-36,27,-93,-15,52,-68,55,-81,-104,117,67,-3,53,102,32,-5,-64,121,-31,-10,19,-123,41,-72,-97,113,45,-10,-111,-71,95,31,-89,-13,36,-111,39,86,126,10,-26,27,-91,48,-77,-45,-25,-106,126,-51,104,101,71,81,2,81,-26,-96,7,-114,-44,-94,-54,-22,110,19,-76,77,3,-127,-86,-78,110,6,-62,-96,121,-100,74,71,-3,-34,43,86,37,109,-110,123,56,118,-7,-33,-96,15,-60,75,-49,-23,-6,-34,57,60,117,-72,-82,-97,-104,88,30,-86,-55,111,-103,-121,-126,-63,-94,-103,-112,0,70,80,118,-46,-44,101,-85,28,85,52,91,-127,29,-88,-63,95,82,59,124,90,-86,-37,7,-116,75,72,-13,82,55,-125,-61,80,90,-75,41,-28,-41,-6,32,-62,35,88,91,61,-112,-104,-115,23,72,-102,-25,77,103,0,73,13,-121,6,81,-52,-70,59,63,113,-84,-85,-112,-9,113,-82,-52,98,-29,45,-25,59,-73,-78,-59,-96,-4,-32,-82,79,16,80,29,94,64,-7,67,-77,-5,-125,119,12,127,-9,104,-95,56,16,58,86,-117,18,66,26,-115,-55,48,59,126,-15,-90,-16,-126,15,120,75,-115,13,106,-76,80,-9,-15,-70,-10,50,-78,56,-51,110,85,-29,-102,20,15,-56,-73,-64,-23,-66,-12,-80,-128,-6,-121,-103,-6,-122,-97,40,46,-36,30,-2,-34,-2,32,116,-93,-59,-109,34,-79,126,-95,-120,-15,-40,-86,-64,71,-48,126,124,-2,-39,75,-64,127,57,30,-107,1,-74,-32,-105,-112,104,-115,80,-27,50,-86,-86,75,-13,-8,81,-13,-66,-38,-14,125,118,103,33,48,-71,10,35,-118,88,65,119,-36,-116,-107,-20,-43,-110,107,33,-27,15,-48,-119,46,-35,96,-75,88,-12,-7,90,-41,-6,-87,89,-88,-117,98,-29,-64,-41,-18,99,-83,13,61,-8,126,46,82,127,-81,-75,20,57,10,-36,81,54,-123,67,18,124,45,-55,95,50,-41,-38,-127,66,61,24,9,51,-55,113,-66,-80,28,49,-113,-71,24,113,-107,105,-71,37,47,-117,73,45,30,-74,117,114,26,6,-42,-80,-74,108,-81,110,73,88,124,-24,-43,-3,49,84,-55,-30,-125,36,102,62,-126,-45,-33,-50,98,-8,6,109,62,113,-84,-12,32,-40,24,-101,-87,-57,-56,59,-123,106,32,12,-71,-18,97,49,113,-47,105,-113,49,99,-124,-124,-81,-118,117,-12,-76,46,-9,-48,-41,-3,-54,-86,97,88,119,-82,-113,-52,-126,-93,-23,-121,127,-97,-28,-24,31,-62,-119,52,-93,75,7,33,-101,-67,67,-45,39,74,-83,127,-115,-66,4,-6,-18,-29,29,-23,68,-123,-103,31,24,117,49,8,-70,41,1,20,71,99,-40,-21,-116,-30,93,66,95,27,63,117,-49,20,-113,-92,-7,127,115,-85,97,-39,34,-67,-10,-53,123,-87,119,2,-77,68,-74,-66,22,96,-13,-12,96,-26,86,35,47,-128,-4,83,52,114,-2,-84,-14,67,-94,-53,-45,-74,-71,-94,94,-101,-122,3,-48,-14,124,-43,56,-3,58,-22,-97,-106,1,-32,57,-16,-127,51,23,-67,-59,-27,-60,125,-46,-125,-117,28,-74,29,29,-76,94,25,58,-32,-31,-101,-105,42,49,101,-115,-60,114,-55,-72,101,94,35,-14,-6,-115,-101,20,-36,-8,103,77,-42,82,61,104,85,35,-71,100,111,67,107,-90,-24,19,6,117,-87,-16,-67,-26,26,24,105,-64,102,105,-36,-7,60,109,112,-19,119,59,-81,10,-91,-9,69,124,-54,124,52,80,13,-105,21,-116,-114,-33,5,0,10,126,-93,22,-26,-115,115,94,22,105,-111,30,-7,102,44,63,0,85,-38,91,-30,98,-21,43,4,-63,-34,-124,-67,38,33,-2,45,-32,-86,12,-92,-38,29,39,121,-119,-42,-23,-30,-106,3,-12,-54,-108,7} + +#define UPDATE_GATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define RESET_GATE_BIAS {-77,67,-93,-3,98,59,-121,33,49,50,41,91,-115,-33,71,47,-70,45,89,-115,72,106,-22,100,97,-100,-95,108,-33,3,14,30} + +#define HIDDEN_STATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define INPUT_DATA1 {-367,-338,0,-89,453,-413,-343,-16,42,418,201,274,-352,477,-290,-92,266,-49,342,453,-398,247,-153,328,217,342,85,69,-38,351,73,128} + +#define INPUT_DATA2 {280,41,-322,61,315,350,504,-227,-221,-483,352,252,455,-236,344,364,-378,229,-187,-498,295,357,-511,58,-349,-458,-420,-66,-400,-379,477,-60} + +#define HISTORY_DATA {-38,53,105,-79,-463,51,-343,-226,-435,-282,218,441,-299,-215,-109,335,340,-471,-109,273,33,-245,-469,170,-26,-59,192,-119,76,-6,236,-145} diff --git a/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt new file mode 100644 index 0000000..fdfe60f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_gru0 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10.cpp b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10.cpp new file mode 100644 index 0000000..471899c --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10.cpp @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_cifar10.cpp +* +* Description: Convolutional Neural Network Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup CNNExample Convolutional Neural Network Example + * + * \par Description: + * \par + * Demonstrates a convolutional neural network (CNN) example with the use of convolution, + * ReLU activation, pooling and fully-connected functions. + * + * \par Model definition: + * \par + * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. + * The neural network consists + * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a + * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will + * be classified into one of the 10 output classes. + * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and + * 3.1 KB for storing the \c im2col data. + * + * \image html CIFAR10_CNN.gif "Neural Network model definition" + * + * \par Variables Description: + * \par + * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices + * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays + * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases + * \li \c input_data points to the input image data + * \li \c output_data points to the classification output + * \li \c col_buffer is a buffer to store the \c im2col output + * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs) + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_convolve_HWC_q7_RGB() + * - arm_convolve_HWC_q7_fast() + * - arm_relu_q7() + * - arm_maxpool_q7_HWC() + * - arm_avepool_q7_HWC() + * - arm_fully_connected_q7_opt() + * - arm_fully_connected_q7() + * + * Refer + * \link arm_nnexamples_cifar10.cpp \endlink + * + * \par [1] https://github.com/BVLC/caffe + */ + +#include +#include +#include "arm_math.h" +#include "arm_nnexamples_cifar10_parameter.h" +#include "arm_nnexamples_cifar10_weights.h" + +#include "arm_nnfunctions.h" +#include "arm_nnexamples_cifar10_inputs.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +// include the input and weights + +static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT; +static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS; + +static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT; +static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS; + +static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT; +static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS; + +static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT; +static q7_t ip1_bias[IP1_OUT] = IP1_BIAS; + +/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */ +uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA; +q7_t output_data[IP1_OUT]; + +//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer) +q7_t col_buffer[2 * 5 * 5 * 32 * 2]; + +q7_t scratch_buffer[32 * 32 * 10 * 4]; + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("start execution\n"); + /* start the execution */ + + q7_t *img_buffer1 = scratch_buffer; + q7_t *img_buffer2 = img_buffer1 + 32 * 32 * 32; + + /* input pre-processing */ + int mean_data[3] = INPUT_MEAN_SHIFT; + unsigned int scale_data[3] = INPUT_RIGHT_SHIFT; + for (int i=0;i<32*32*3; i+=3) { + img_buffer2[i] = (q7_t)__SSAT( ((((int)image_data[i] - mean_data[0])<<7) + (0x1<<(scale_data[0]-1))) + >> scale_data[0], 8); + img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1))) + >> scale_data[1], 8); + img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1))) + >> scale_data[2], 8); + } + + // conv1 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING, + CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM, + (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH); + + // pool1 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM, + POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2); + + // conv2 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM, + CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1, + CONV2_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH); + + // pool2 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM, + POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2); + +// conv3 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM, + CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1, + CONV3_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH); + + // pool3 img_buffer-> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM, + POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2); + + arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias, + output_data, (q15_t *) img_buffer1); + + arm_softmax_q7(output_data, 10, output_data); + + for (int i = 0; i < 10; i++) + { + printf("%d: %d\n", i, output_data[i]); + } + + return 0; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_inputs.h b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_inputs.h new file mode 100644 index 0000000..c600c5a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_inputs.h @@ -0,0 +1,6 @@ +/* Here are two different test images */ + +//#define IMG_DATA {158,112,49,159,111,47,165,116,51,166,118,53,160,112,46,156,109,41,162,115,47,159,113,45,158,111,44,159,113,41,161,116,41,160,111,52,161,111,49,166,117,41,169,117,45,170,119,44,167,117,40,162,113,38,160,111,39,160,112,43,156,109,44,149,107,45,150,107,45,148,106,43,149,107,44,143,101,39,140,98,43,141,97,41,143,97,38,137,95,36,126,91,36,116,85,33,152,112,51,151,110,40,159,114,45,166,116,56,162,112,49,160,113,43,164,117,47,162,114,45,163,116,46,156,110,38,155,111,41,159,110,54,163,113,52,170,119,41,171,117,40,171,115,33,169,115,30,160,111,33,154,112,41,151,115,50,145,110,53,139,104,55,140,102,52,141,100,48,149,105,50,147,102,46,145,102,45,142,97,38,143,98,34,136,95,31,125,91,32,119,88,34,151,110,47,151,109,33,158,111,36,167,111,48,160,106,42,163,115,44,165,117,45,165,117,45,163,115,43,162,115,43,158,114,48,157,109,57,161,111,51,166,115,38,167,114,37,169,113,35,170,116,39,159,114,47,145,111,54,121,96,49,110,90,52,98,78,50,101,77,47,114,85,50,120,86,48,134,96,55,143,103,51,140,99,39,142,99,35,139,98,34,130,95,34,120,89,33,155,107,40,155,110,32,160,109,31,174,112,44,167,110,43,167,117,46,169,120,48,169,119,48,165,115,44,165,117,45,167,123,57,191,146,95,177,130,75,157,111,41,162,115,47,164,114,54,158,112,58,149,111,67,104,80,47,103,87,65,98,90,76,92,90,84,80,75,66,74,63,50,86,70,52,83,62,39,113,85,45,132,98,46,140,102,43,140,101,39,136,99,39,127,94,36,155,107,41,156,114,48,161,115,49,170,114,47,169,114,43,163,113,40,169,120,47,166,116,44,164,113,41,164,116,42,173,128,59,246,214,164,195,156,107,151,114,56,146,111,60,142,108,71,111,80,50,78,53,31,85,69,56,113,103,98,112,110,111,106,114,118,97,102,105,93,94,93,74,72,67,84,78,70,85,73,47,105,83,45,128,96,48,138,101,46,133,94,36,129,93,36,148,109,54,133,104,64,130,100,57,147,112,53,161,115,44,165,113,39,167,116,41,167,115,41,163,111,37,165,116,39,163,118,42,180,138,85,157,122,78,128,102,58,97,75,43,66,50,31,69,58,43,66,56,45,89,83,76,118,113,110,122,121,120,119,122,122,114,116,116,94,96,96,99,100,97,91,91,86,58,58,47,67,58,37,108,84,49,140,105,58,138,98,44,134,95,40,127,100,57,109,95,80,47,37,17,88,74,28,153,117,48,170,118,43,168,115,40,170,118,43,169,117,42,166,116,37,164,120,39,147,107,52,129,98,59,127,108,75,100,87,70,68,67,57,78,83,72,72,75,64,83,84,74,132,130,121,146,142,132,124,118,108,105,99,90,107,102,94,115,111,103,85,83,77,63,71,69,46,47,39,79,61,36,132,98,58,141,99,48,134,93,39,131,115,90,99,96,92,42,43,38,70,64,41,143,111,56,167,117,42,165,114,36,168,116,39,171,119,49,161,113,51,140,109,51,120,94,49,130,110,77,144,131,107,116,106,93,88,87,79,91,95,88,85,88,82,77,77,69,124,118,107,163,153,140,136,124,112,102,93,81,106,98,88,100,93,84,85,81,74,54,60,58,49,53,49,57,47,32,107,83,50,138,103,51,136,97,39,170,161,144,103,105,105,54,58,59,124,121,113,153,124,82,161,113,43,163,117,41,166,122,50,165,121,66,174,135,95,113,89,59,125,105,78,157,141,121,156,143,128,121,111,101,86,80,74,82,81,77,84,85,82,80,78,73,81,71,61,138,125,112,146,135,123,113,103,93,87,79,70,83,77,69,86,82,76,71,73,67,56,57,53,40,35,27,74,59,35,133,106,59,137,103,45,180,176,163,134,139,143,94,100,105,154,154,149,174,149,112,158,116,51,156,116,47,153,118,60,207,180,146,237,214,198,207,180,166,156,131,119,174,153,145,148,131,125,125,110,107,93,85,79,86,84,79,74,74,71,59,57,53,76,68,58,137,125,112,143,133,122,133,124,114,106,98,89,86,81,74,87,85,78,84,85,78,75,76,71,50,49,43,40,30,15,95,75,44,132,103,57,183,183,175,108,116,122,142,151,158,165,169,168,177,156,122,155,112,50,159,118,51,122,89,47,213,197,179,237,224,226,220,191,188,164,135,131,183,159,155,156,137,132,125,108,104,120,111,104,78,76,69,80,80,77,45,44,40,91,85,77,175,165,154,157,147,137,155,147,138,107,100,92,87,83,77,103,102,96,88,88,79,78,79,73,59,59,59,41,36,33,59,46,31,104,81,46,188,191,189,100,108,116,135,144,153,170,175,178,187,167,136,166,120,59,173,123,55,134,93,44,117,95,80,194,182,188,199,171,164,170,142,133,185,161,151,189,171,159,134,119,106,117,107,95,102,98,89,84,84,79,38,38,34,125,121,113,210,201,192,160,152,142,146,139,130,93,89,82,83,80,75,94,93,88,104,104,94,85,87,81,73,75,78,55,53,55,62,55,48,76,56,26,189,194,194,90,96,105,127,134,144,175,180,185,174,156,133,166,123,68,178,123,53,159,109,47,97,68,44,168,154,152,168,144,126,137,114,94,186,166,148,216,202,183,160,149,129,123,113,98,120,114,105,115,114,109,50,50,47,150,147,140,194,187,178,155,149,140,123,118,111,91,88,83,84,83,79,84,84,80,95,95,85,86,87,81,84,87,89,73,73,73,79,74,64,73,55,24,189,192,193,93,95,103,152,154,163,185,188,192,119,110,98,136,106,66,173,124,58,167,116,50,103,72,39,147,132,120,145,125,103,167,149,127,189,174,155,226,216,200,180,172,157,141,131,117,126,117,107,117,114,109,71,71,68,154,152,147,186,181,174,149,144,136,114,110,104,87,85,80,80,80,76,72,73,70,80,80,72,99,100,94,100,101,99,90,88,81,97,89,69,94,73,34,194,196,196,108,107,112,168,167,172,186,186,188,105,109,109,99,89,67,156,119,62,167,122,55,100,74,34,115,106,88,138,123,103,198,185,169,190,180,169,172,165,159,145,140,140,154,143,134,146,136,125,103,100,95,71,71,70,152,152,149,179,175,170,137,13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3,71,107,133,49,89,114,31,77,105,27,71,105,38,82,117,49,93,128,56,100,135,58,102,137,53,92,128,56,94,131,60,99,137,57,99,139,53,97,138,50,95,137,45,94,136,39,88,131,33,83,125,42,91,133,62,112,154,79,132,179,73,131,181,56,116,168,38,97,146,13,64,108,40,85,127,61,116,168,49,102,148,35,85,132,43,91,143,39,90,139,42,92,134,44,88,125,40,81,112,42,85,115,27,72,104,23,67,102,30,74,109,27,71,106,29,73,108,36,80,115,47,86,120,56,95,128,62,101,135,66,109,144,75,119,156,69,113,152,49,95,134,43,88,127,43,88,127,60,105,144,85,130,170,109,156,197,93,145,190,60,115,164,26,82,130,29,82,126,20,64,107,54,107,160,56,105,149,45,89,132,43,86,134,40,89,134,40,92,132,40,87,123,38,81,115,36,79,114,26,69,105,22,66,101,29,73,108,25,69,104,29,73,108,19,63,98,18,58,89,32,70,100,47,87,118,61,104,137,74,119,152,66,111,145,53,96,131,52,95,130,45,87,123,67,109,145,89,131,167,105,146,182,89,135,175,48,99,145,24,77,124,34,84,129,21,67,110} + + +#define IMG_DATA {235,235,235,231,231,231,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,232,233,233,231,233,232,231,233,231,233,233,230,233,232,232,232,234,232,231,234,232,232,232,233,233,230,232,233,231,233,233,233,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,232,232,232,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,237,234,233,236,234,233,236,236,234,234,236,234,234,235,237,234,234,238,235,236,237,236,236,235,236,236,234,236,236,236,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,235,235,235,237,237,237,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,234,234,236,233,231,236,234,231,235,235,234,234,235,236,227,230,233,231,235,238,231,233,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,234,233,233,230,232,232,231,228,230,232,223,226,231,186,192,197,209,216,219,207,210,213,228,228,230,236,235,235,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,237,237,237,234,234,234,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,236,238,236,233,237,237,219,225,230,203,210,219,163,172,179,195,205,208,214,218,221,230,229,232,237,235,237,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,239,239,238,236,235,235,236,235,235,236,235,235,236,235,235,236,235,235,235,236,235,235,235,235,234,234,234,235,235,235,237,236,236,237,236,236,234,235,236,232,233,234,235,237,237,229,231,232,208,216,218,194,205,210,185,198,207,174,188,200,165,179,189,184,196,202,207,215,220,226,228,232,236,235,237,236,236,235,236,236,235,236,236,235,236,236,236,237,237,237,237,237,237,237,237,237,228,229,229,228,227,228,232,230,231,231,228,230,234,232,233,237,236,236,237,237,235,236,237,235,237,235,236,237,235,236,239,236,237,239,237,238,225,229,230,224,228,229,233,237,238,221,226,228,183,197,204,161,180,190,159,180,191,154,176,190,144,163,177,143,159,171,156,169,177,198,206,211,233,238,239,236,237,234,235,236,233,235,235,235,235,236,236,236,238,237,237,237,237,239,237,238,212,220,222,224,230,233,230,234,238,227,232,234,229,234,234,234,237,236,237,238,235,238,237,236,239,237,238,239,237,238,239,236,237,240,238,239,201,204,203,219,222,221,233,236,235,214,218,218,193,204,210,185,201,210,184,201,211,173,191,203,165,182,196,159,174,187,162,176,185,186,199,204,229,239,240,234,239,238,233,238,237,233,238,238,234,239,238,236,239,238,237,239,238,238,238,238,216,234,241,221,236,243,225,238,246,225,239,243,227,240,240,231,238,237,236,237,235,238,236,235,238,236,237,238,236,237,237,237,237,239,239,239,197,198,196,220,221,218,233,234,231,230,231,229,209,213,217,209,216,222,219,228,235,208,218,227,209,221,234,210,224,235,217,233,240,218,235,241,225,240,243,228,238,240,228,239,240,230,240,240,230,240,239,235,240,239,237,240,239,238,238,238,118,140,149,119,138,148,124,142,153,136,155,161,172,188,191,225,234,233,235,236,233,237,234,232,236,233,234,235,235,235,235,237,236,233,237,235,214,216,214,226,228,226,232,234,232,236,237,236,228,230,232,227,230,235,231,236,241,225,232,239,225,237,247,217,233,243,201,219,226,185,204,211,172,189,195,167,179,186,167,180,185,186,199,201,223,235,235,235,241,239,236,240,239,238,240,239,109,130,141,103,121,133,108,125,137,111,127,137,146,159,165,222,229,231,227,228,225,229,226,224,236,232,233,234,234,234,231,236,234,230,237,235,229,234,235,231,235,236,232,237,238,230,235,236,231,236,238,231,237,240,229,237,241,223,232,238,191,206,213,164,184,191,146,165,172,137,156,163,134,149,159,128,140,153,121,133,143,149,162,166,216,228,229,234,241,239,235,240,238,237,240,239,195,212,224,188,202,215,199,211,224,200,211,223,209,217,227,223,227,231,213,213,211,211,209,206,216,213,214,220,222,222,219,226,225,210,221,219,209,219,223,211,221,225,216,225,230,220,229,233,225,234,237,226,236,239,225,237,241,218,231,237,183,204,208,175,198,203,181,200,207,178,194,202,186,197,211,170,178,196,142,151,164,185,195,202,219,230,233,231,240,238,234,241,239,236,240,239,193,207,222,191,202,217,202,211,224,214,217,234,223,225,241,214,219,227,203,208,208,171,174,174,177,180,183,207,213,214,174,184,188,98,112,121,93,114,126,101,121,132,111,129,139,122,138,147,137,152,161,153,167,174,202,216,220,223,236,237,218,232,235,220,233,238,223,234,240,217,226,233,221,228,237,212,219,229,196,203,212,222,230,237,219,227,234,221,230,233,232,239,242,235,241,242,113,130,152,111,125,147,113,125,141,125,131,151,138,145,165,170,182,193,191,201,205,190,199,204,208,219,226,216,230,234,158,172,183,54,71,92,45,70,91,49,73,91,53,73,90,66,84,98,102,114,129,159,168,179,221,227,233,234,239,241,233,237,241,227,231,237,223,228,233,207,211,217,202,208,212,211,218,220,212,219,223,199,206,214,179,186,196,188,197,205,211,221,227,221,231,234,61,81,108,69,86,114,63,79,100,68,85,102,123,141,155,139,155,164,151,157,164,195,200,207,214,228,234,206,223,228,163,180,190,103,121,138,95,112,131,101,117,135,138,151,168,181,192,207,207,212,223,221,222,232,219,219,227,205,203,212,183,186,195,158,166,174,147,154,163,131,138,147,125,133,140,130,139,144,136,146,152,133,142,151,128,137,147,138,153,160,182,197,203,197,212,216,40,53,77,58,70,94,85,98,116,127,144,153,132,151,156,96,107,110,119,115,118,163,158,161,173,180,182,184,194,197,182,194,198,181,193,200,183,194,202,198,209,217,218,228,236,200,210,217,174,181,186,159,165,172,145,150,159,132,136,149,116,125,138,98,111,123,94,106,118,99,111,123,105,118,128,107,121,130,122,135,145,138,151,161,150,164,174,157,174,184,188,206,213,185,203,208,13,15,35,26,29,47,134,140,151,206,216,220,138,150,150,118,123,123,141,133,134,172,162,162,181,181,180,207,209,211,220,224,225,228,234,233,224,234,232,230,241,240,226,238,238,176,189,190,144,159,163,138,154,162,142,158,170,145,163,177,154,171,187,149,165,182,149,165,182,154,171,187,157,174,189,160,177,191,173,190,204,187,204,217,190,207,218,178,196,208,165,183,193,157,175,183,5,5,24,58,62,79,200,207,217,225,232,239,197,205,212,199,207,211,212,212,218,226,224,229,229,230,237,233,236,246,232,238,245,230,238,239,209,221,220,223,238,239,221,238,241,210,228,234,198,217,228,180,200,214,193,216,230,188,213,229,189,212,231,194,214,234,192,212,232,184,204,224,172,193,212,171,191,209,161,181,197,144,165,179,136,156,169,131,146,161,128,143,158,138,154,165,39,45,71,145,155,179,190,204,222,186,196,216,184,197,217,192,211,229,194,211,230,194,208,227,194,206,227,191,203,228,192,207,228,190,207,221,177,193,207,180,198,215,154,176,193,147,169,188,145,161,184,156,171,195,146,163,186,113,133,156,114,137,161,132,157,180,126,150,173,111,135,158,92,115,138,91,112,135,93,114,133,94,116,131,105,125,140,121,133,151,129,141,158,129,142,156,122,135,161,162,179,207,143,160,194,137,154,189,131,152,187,128,152,190,127,150,192,130,150,193,131,150,192,128,147,190,127,147,189,129,149,189,129,149,188,124,145,186,104,126,163,100,122,154,102,120,154,118,134,170,112,128,163,94,109,145,94,112,148,94,117,153,87,112,144,83,103,136,80,97,130,83,103,134,93,111,139,101,117,141,108,121,144,115,125,146,121,133,148,130,144,156,73,87,109,76,90,113,77,90,122,80,93,127,84,98,134,87,102,142,87,102,147,90,105,150,94,111,152,102,119,160,107,124,165,113,131,172,115,137,181,118,136,186,118,132,180,120,133,175,115,136,172,110,133,168,106,127,163,100,119,155,95,109,148,85,101,139,79,97,132,80,92,127,80,94,129,77,100,133,80,100,129,82,98,122,92,104,126,113,119,138,125,135,146,136,149,156,13,25,41,3,11,25,9,16,35,18,26,48,18,26,52,21,25,56,20,25,58,22,30,61,26,36,62,34,43,70,42,51,77,48,59,87,52,69,106,60,75,121,66,77,126,70,79,126,71,87,127,72,88,126,67,81,120,60,72,112,55,67,106,53,68,104,53,69,103,57,69,102,57,71,105,57,78,110,72,89,115,87,100,119,104,113,128,120,124,136,130,136,141,137,146,149,36,46,55,11,16,20,8,13,19,32,44,53,36,45,58,22,25,41,8,11,30,3,8,24,1,4,17,0,2,15,0,2,15,0,4,20,6,13,42,5,18,56,1,19,60,3,23,62,13,29,71,24,38,81,21,33,77,21,31,76,21,38,78,22,44,79,30,50,83,39,58,90,57,70,101,85,90,118,113,115,138,123,123,138,116,115,125,122,123,128,134,139,137,153,160,158,35,41,45,26,27,26,13,19,18,27,41,41,71,81,84,70,70,76,49,50,57,27,31,37,15,15,21,5,5,11,2,2,7,0,0,7,17,17,35,57,64,91,31,50,78,10,36,62,4,30,60,4,30,62,7,30,63,14,35,69,25,43,74,41,55,83,62,71,99,86,97,123,122,124,146,144,131,149,132,120,135,114,105,114,117,111,116,132,134,133,146,152,146,172,179,175,16,15,17,13,10,9,4,10,8,3,12,11,45,44,46,65,52,57,54,43,47,36,33,35,18,18,20,4,4,7,2,2,4,0,1,3,7,8,15,118,117,134,161,158,179,131,128,148,112,112,131,105,105,125,105,103,124,109,105,127,118,107,126,138,115,133,154,126,144,151,126,141,127,106,116,105,86,91,106,94,97,120,116,116,129,130,129,142,147,144,164,172,165,184,194,190,40,40,35,12,10,7,0,3,3,0,4,4,12,6,7,30,12,17,32,12,17,21,10,12,7,6,7,2,1,3,2,1,2,3,2,3,0,0,2,68,58,64,182,128,146,205,130,148,196,127,144,194,123,141,195,119,137,187,113,129,172,110,122,150,96,106,123,75,83,103,66,69,95,71,70,104,93,88,122,118,113,129,132,126,132,141,135,152,162,158,171,182,176,185,197,194,69,77,64,26,29,21,1,1,1,1,1,2,4,1,0,12,2,5,18,3,9,12,2,5,4,1,2,2,0,0,2,0,0,4,0,1,1,1,1,32,12,11,153,45,59,203,47,68,195,46,67,191,48,69,179,50,67,155,49,59,119,42,49,91,38,42,81,48,46,94,77,71,117,110,102,125,126,116,125,128,120,129,135,128,144,153,147,162,176,171,173,187,183,184,198,196,83,94,82,47,52,43,1,1,1,2,1,2,2,0,0,5,1,2,7,1,5,4,0,2,1,0,0,1,0,0,1,0,0,3,0,0,1,2,0,27,3,2,142,25,38,205,32,54,198,25,46,169,25,43,121,25,36,85,29,34,74,41,39,85,66,56,102,92,82,121,113,105,128,124,115,122,126,115,121,127,118,132,139,131,147,157,150,165,179,174,176,191,187,186,201,199,92,102,93,54,60,50,6,7,3,3,2,1,2,2,0,1,3,1,1,3,3,1,2,2,1,1,1,1,0,0,1,0,0,1,1,1,0,3,2,15,1,0,102,19,28,157,31,47,117,17,23,74,13,12,56,27,22,74,58,55,99,90,81,115,115,99,122,126,111,124,124,112,123,123,113,125,130,119,128,135,126,136,145,137,148,159,151,162,176,171,177,192,188,188,202,201,87,99,89,43,51,37,19,23,11,11,12,4,8,10,2,5,11,4,2,10,4,2,7,2,3,4,1,3,4,1,3,4,1,2,3,2,0,6,6,4,5,2,42,13,13,71,21,24,53,27,25,57,50,41,80,77,62,113,98,82,132,113,101,134,126,113,123,126,112,116,125,111,120,128,115,131,138,126,139,148,137,143,154,145,156,168,161,169,184,179,182,197,193,188,202,201,82,96,82,46,57,36,36,44,22,31,35,17,27,30,15,22,28,15,17,26,13,16,23,12,18,21,12,19,21,13,20,22,14,19,23,15,19,27,20,23,31,21,37,40,27,64,55,45,87,70,67,104,88,81,116,102,85,128,112,88,139,121,105,131,122,110,117,122,107,115,127,112,123,133,119,131,139,127,139,149,138,148,160,151,159,172,164,174,189,183,185,200,196,187,202,200,85,101,83,62,75,48,58,67,38,55,61,37,51,56,35,47,53,33,46,53,34,48,55,38,49,55,40,51,56,41,53,58,44,55,62,46,59,67,45,68,71,48,81,84,59,104,96,74,116,103,83,127,109,92,133,116,97,127,121,97,127,127,107,118,124,106,114,125,108,122,131,117,129,136,123,136,145,133,141,152,141,149,162,153,158,171,163,168,183,178,180,195,191,186,200,199} diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_parameter.h b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_parameter.h new file mode 100644 index 0000000..09d0ca3 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_parameter.h @@ -0,0 +1,43 @@ +#define CONV1_IM_DIM 32 +#define CONV1_IM_CH 3 +#define CONV1_KER_DIM 5 +#define CONV1_PADDING 2 +#define CONV1_STRIDE 1 +#define CONV1_OUT_CH 32 +#define CONV1_OUT_DIM 32 + +#define POOL1_KER_DIM 3 +#define POOL1_STRIDE 2 +#define POOL1_PADDING 0 +#define POOL1_OUT_DIM 16 + +#define CONV2_IM_DIM 16 +#define CONV2_IM_CH 32 +#define CONV2_KER_DIM 5 +#define CONV2_PADDING 2 +#define CONV2_STRIDE 1 +#define CONV2_OUT_CH 16 +#define CONV2_OUT_DIM 16 + +#define POOL2_KER_DIM 3 +#define POOL2_STRIDE 2 +#define POOL2_PADDING 0 +#define POOL2_OUT_DIM 8 + +#define CONV3_IM_DIM 8 +#define CONV3_IM_CH 16 +#define CONV3_KER_DIM 5 +#define CONV3_PADDING 2 +#define CONV3_STRIDE 1 +#define CONV3_OUT_CH 32 +#define CONV3_OUT_DIM 8 + +#define POOL3_KER_DIM 3 +#define POOL3_STRIDE 2 +#define POOL3_PADDING 0 +#define POOL3_OUT_DIM 4 + +#define IP1_DIM 4*4*32 +#define IP1_IM_DIM 4 +#define IP1_IM_CH 32 +#define IP1_OUT 10 diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_weights.h b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_weights.h new file mode 100644 index 0000000..8d92d21 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/arm_nnexamples_cifar10_weights.h @@ -0,0 +1,26 @@ +#define CONV1_WT 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+ +#define CONV1_BIAS {-49,-18,-7,-20,-12,-15,7,2,-10,-84,-72,-65,-53,-6,-87,-63,-64,-28,-28,-4,-3,-10,-52,-15,-5,-7,-31,-44,-102,-19,-5,-65} + +#define CONV2_WT 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+ +#define CONV2_BIAS {55,50,34,43,-37,35,-21,10,35,-53,-76,7,14,-1,92,20} + +#define CONV3_WT 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+ +#define CONV3_BIAS {18,36,-46,-45,64,8,13,-19,28,1,14,-57,23,20,-2,32,48,-11,85,73,-7,52,125,33,125,13,92,-72,89,-1,11,70} + +#define IP1_WT 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34,-1,-20} + +#define IP1_BIAS {30,-121,-51,77,40,20,46,-35,28,-33} + +#define CONV1_BIAS_LSHIFT 6 +#define CONV1_OUT_RSHIFT 9 +#define CONV2_BIAS_LSHIFT 4 +#define CONV2_OUT_RSHIFT 9 +#define CONV3_BIAS_LSHIFT 1 +#define CONV3_OUT_RSHIFT 7 +#define IP1_BIAS_LSHIFT 1 +#define IP1_OUT_RSHIFT 8 +#define INPUT_MEAN_SHIFT {125,123,114} +#define INPUT_RIGHT_SHIFT {8,8,8} diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/readme_iar.txt b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/readme_iar.txt new file mode 100644 index 0000000..8ca1d5c --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-cifar10/readme_iar.txt @@ -0,0 +1,7 @@ +CMSIS NN Lib example arm_nnexample_cifar10 for + Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for IAR Embedded Workbench for ARM Simulator. + +When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT +Preprocessor defines for C/C++ Compiler diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru.cpp b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru.cpp new file mode 100644 index 0000000..340dc33 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru.cpp @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_gru.cpp +* +* Description: Gated Recurrent Unit Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GRUExample Gated Recurrent Unit Example + * + * \par Description: + * \par + * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected, + * Tanh/Sigmoid activation functions. + * + * \par Model definition: + * \par + * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden + * state. + * \par + * The computation can be summarized as: + * 
z[t] = sigmoid( W_z ⋅ {h[t-1],x[t]} )
+ * r[t] = sigmoid( W_r ⋅ {h[t-1],x[t]} ) 
+ * n[t] = tanh( W_n ⋅ [r[t] × {h[t-1], x[t]} ) 
+ * h[t] = (1 - z[t]) × h[t-1] + z[t] × n[t]
+ * \image html GRU.gif "Gate Recurrent Unit Diagram" + * + * \par Variables Description: + * \par + * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n). + * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays + * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history + * + * \par + * The buffer is allocated as: + * \par + * | reset | input | history | update | hidden_state | + * \par + * In this way, the concatination is automatically done since (reset, input) and (input, history) + * are physically concatinated in memory. + * \par + * The ordering of the weight matrix should be adjusted accordingly. + * + * + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fully_connected_mat_q7_vec_q15_opt() + * - arm_nn_activations_direct_q15() + * - arm_mult_q15() + * - arm_offset_q15() + * - arm_sub_q15() + * - arm_copy_q15() + * + * Refer + * \link arm_nnexamples_gru.cpp \endlink + * + */ + +#include +#include +#include +#include "arm_nnexamples_gru_test_data.h" +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +#define DIM_HISTORY 32 +#define DIM_INPUT 32 +#define DIM_VEC 64 + +#define USE_X4 + +#ifndef USE_X4 +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2; +#else +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4; +#endif + +static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS; +static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS; +static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS; + +static q15_t test_input1[DIM_INPUT] = INPUT_DATA1; +static q15_t test_input2[DIM_INPUT] = INPUT_DATA2; +static q15_t test_history[DIM_HISTORY] = HISTORY_DATA; + +q15_t scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT]; + +void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size, + q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state, + q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state) +{ + q15_t *reset = scratch_input; + q15_t *input = scratch_input + history_size; + q15_t *history = scratch_input + history_size + input_size; + q15_t *update = scratch_input + 2 * history_size + input_size; + q15_t *hidden_state = scratch_input + 3 * history_size + input_size; + + // reset gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset, + reset, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15, + bias_reset, reset, NULL); +#endif + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID); + arm_mult_q15(history, reset, reset, history_size); + + // update gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#endif + + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID); + + // hidden state calculation +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#endif + + // tanh function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH); + arm_mult_q15(update, hidden_state, hidden_state, history_size); + + // we calculate z - 1 here + // so final addition becomes substraction + arm_offset_q15(update, 0x8000, update, history_size); + // multiply history + arm_mult_q15(history, update, update, history_size); + // calculate history_out + arm_sub_q15(hidden_state, update, history, history_size); + + return; +} + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("Start GRU execution\n"); + int input_size = DIM_INPUT; + int history_size = DIM_HISTORY; + + // copy over the input data + arm_copy_q15(test_input1, scratch_buffer + history_size, input_size); + arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size); + + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete first iteration on GRU\n"); + + arm_copy_q15(test_input2, scratch_buffer + history_size, input_size); + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete second iteration on GRU\n"); + + return 0; +} diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru_test_data.h b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru_test_data.h new file mode 100644 index 0000000..4fd2bb0 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/arm_nnexamples_gru_test_data.h @@ -0,0 +1,23 @@ +#define UPDATE_GATE_WEIGHT_X2 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+ +#define UPDATE_GATE_WEIGHT_X4 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+ +#define RESET_GATE_WEIGHT_X2 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+ +#define RESET_GATE_WEIGHT_X4 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+ +#define HIDDEN_STATE_WEIGHT_X2 {-3,-33,59,21,117,70,0,44,108,108,-47,-80,-118,34,88,-91,-123,-108,8,51,26,82,-80,107,-100,-69,97,-90,17,19,63,111,-40,-125,110,24,58,-69,26,-31,-65,-37,-47,-41,-109,106,-100,108,-99,108,116,104,86,-50,-45,10,-53,112,34,96,-10,-39,-32,-25,69,102,-2,-4,-25,121,-1,-28,-48,-100,0,-128,60,-73,42,-32,118,-88,-113,-112,-113,70,-98,118,95,77,-52,123,-99,72,26,-102,-32,120,113,22,6,-68,84,-33,103,66,111,60,-76,33,10,25,-43,93,41,-79,110,13,67,107,-113,90,58,64,-125,79,-85,-18,76,80,-59,11,-18,-74,15,-102,99,-19,117,99,65,-50,-108,-121,-9,-104,33,94,-95,110,-48,-97,76,36,1,-58,86,-115,45,-88,38,51,123,-23,-20,-43,-37,15,91,-85,-88,6,-96,58,78,13,23,1,-43,62,-70,-108,44,30,74,90,79,-80,-20,71,-21,0,60,19,-59,-52,44,-14,77,92,-69,121,-123,-27,119,-84,79,87,24,85,118,1,-51,-96,60,102,-6,15,96,120,-109,6,35,11,-119,-109,-18,16,-112,91,-126,71,-29,121,-21,-120,37,57,-117,-39,93,56,-73,-104,77,-107,-52,111,-61,-4,44,-119,67,72,-66,36,-127,-113,-124,123,21,98,84,86,76,23,78,7,-127,-4,1,-46,-107,59,-21,53,-65,-99,-15,-98,53,-31,7,64,7,105,51,-75,50,-52,48,101,-126,-120,5,34,3,81,-39,70,41,112,25,30,79,-6,107,-11,-97,92,-84,67,49,107,60,101,-37,27,-91,-61,-96,120,-113,87,-46,68,64,102,-86,-60,13,-71,56,-105,90,-9,-35,27,103,120,39,23,-39,-1,-85,-95,-6,119,-41,-2,-69,102,102,-119,-3,-11,-125,-111,40,-115,-41,-117,-44,-7,83,123,-21,23,99,-107,43,100,-99,-3,89,3,-113,103,47,-94,-69,-38,-28,-37,49,-117,-49,-126,17,-98,37,92,55,-116,-70,-50,77,120,47,124,78,114,67,-48,6,-42,-115,85,116,-114,-46,-50,-13,70,-101,110,-55,20,-51,125,-19,-9,-15,46,30,-27,-123,114,-50,-30,-72,76,-83,71,47,-45,74,102,44,108,-26,108,-113,-43,110,-91,37,-69,76,-33,106,-76,-96,20,-117,63,-33,-5,11,-121,-51,63,-56,59,-16,-33,114,74,124,73,99,-50,51,-71,118,106,30,-92,26,-40,119,-121,2,-45,9,0,-5,-2,-89,88,-11,-85,-60,19,81,-96,75,82,-40,124,89,-36,-117,-100,-2,-34,112,101,39,-101,-106,60,59,-126,-32,96,68,-53,87,20,54,-24,46,-95,65,-112,22,60,122,-22,-106,-124,97,-37,-86,95,-110,-8,44,58,-12,-120,-45,-86,-32,-86,-94,-14,15,29,-8,-114,71,70,-93,-69,100,-123,-18,-47,-12,127,104,-102,93,-11,-73,121,87,-79,-92,46,92,-108,-107,79,121,-71,-89,16,-11,-52,72,-114,-32,-60,-9,-57,-4,10,-81,-22,68,74,76,-68,-127,96,-84,69,-3,-26,-106,-3,-87,-65,105,109,122,-103,31,-108,-86,-5,-39,85,88,67,-82,0,-25,93,61,-62,5,-54,-114,-51,-9,-114,20,49,-26,38,19,39,-103,33,-120,37,-97,32,-89,119,111,-124,-99,78,-49,-128,76,-18,-12,-109,96,90,-73,-104,59,-59,-92,123,55,54,-120,-80,-48,-16,-95,96,36,118,-119,-58,93,45,-43,-75,64,38,-2,-72,-111,22,-89,-75,-120,-42,45,108,59,-105,40,27,32,-66,121,-22,-71,-9,118,124,60,-96,47,4,14,-27,64,70,47,-91,-70,1,-44,94,-46,53,4,23,-124,-92,-95,83,-49,-81,40,-80,48,0,39,1,-113,32,40,-21,-1,-110,102,1,-74,-51,40,108,-35,-36,89,84,123,-48,-115,-115,83,-61,114,-127,-61,114,100,-82,-45,60,87,60,19,86,97,-68,40,-66,75,86,-32,-128,88,-57,-27,77,3,-27,43,-39,-62,66,5,-82,45,-104,-78,34,57,96,89,-90,66,-10,37,-110,-30,82,-58,13,94,12,115,35,117,0,80,61,-7,107,-104,-21,21,-70,-93,-94,-51,-61,39,-62,64,-82,-109,76,84,58,-47,-100,52,46,-51,88,91,8,-47,108,-80,25,-58,111,-59,-83,-75,92,98,110,54,106,65,-47,-120,-5,90,-123,101,-61,-85,-93,109,88,0,8,59,86,56,126,17,-26,58,-101,-25,35,0,-123,-3,-56,112,-128,8,17,-52,88,31,-3,105,-56,68,-1,-94,96,-19,10,-22,-88,-10,119,-44,19,42,75,-86,18,-107,89,-82,-120,76,40,84,-122,29,33,-47,17,-50,-13,23,-66,-46,85,-29,-110,42,-68,8,99,-93,-29,101,16,52,-13,127,0,86,-117,-92,-70,-32,-27,127,-123,1,34,-13,92,114,-11,29,-103,-121,-54,20,73,16,74,108,16,-61,89,50,-30,-14,116,44,-31,16,96,24,-51,7,39,-87,-69,-61,-98,61,-46,113,85,-95,103,67,99,-66,-45,-42,-70,96,104,5,-111,69,-25,99,-118,23,109,11,4,-41,-94,73,100,96,6,90,-75,-25,79,-13,-43,-6,-12,51,12,40,124,-56,81,-8,59,-60,-26,-54,33,122,85,53,-99,125,19,-26,94,41,-5,46,-48,-70,-10,41,102,-1,-98,-9,15,29,46,-66,-118,-53,45,119,-127,94,53,-58,90,124,5,-110,-98,-80,-77,77,29,19,105,-121,92,9,-124,50,-119,59,40,67,104,-12,13,103,101,47,-51,34,-66,-101,-117,112,-5,118,-48,-60,-114,38,-71,2,51,114,80,115,-5,116,20,16,-47,-19,30,24,-68,7,-30,-3,-64,-7,-34,-12,44,34,-91,-97,116,112,-99,108,-75,17,26,-14,-61,80,22,-7,34,47,-93,45,106,121,78,43,-97,39,-99,-68,-72,-7,64,-49,-82,-127,78,-64,48,18,15,126,-125,-111,-69,-111,10,-46,111,-75,123,-44,-67,-31,-96,-67,-53,-53,-106,67,-101,23,62,30,9,-114,-12,-57,-38,-78,95,-10,-3,110,88,123,-26,78,-125,114,53,10,-57,26,38,-51,73,92,-124,79,15,75,-62,109,-113,-67,1,35,52,-36,55,7,111,-43,109,101,88,122,-21,-32,-87,59,16,-122,-109,-118,17,-22,-39,53,-105,77,90,-24,-65,43,-27,113,30,-117,-30,106,37,55,59,54,-70,99,99,-73,120,97,-39,-88,-54,101,51,-76,70,-121,-68,23,-73,-31,75,-8,-63,-123,-93,96,-81,99,-95,28,-36,55,-104,32,-64,41,-97,95,-89,126,-26,-25,126,2,-26,-54,110,-86,110,74,-3,-110,56,-60,-49,117,-82,-55,-103,-112,70,-85,85,-63,82,7,75,-61,90,32,35,-115,72,73,-121,63,-84,-52,-29,-59,-4,29,64,119,127,58,-117,48,126,120,-115,-15,-10,27,27,-81,117,-5,121,-72,113,31,-13,10,27,-106,-51,81,-96,-22,19,-78,6,71,-34,123,118,75,-23,-72,-97,111,-121,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+ +#define HIDDEN_STATE_WEIGHT_X4 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+ +#define UPDATE_GATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define RESET_GATE_BIAS {-77,67,-93,-3,98,59,-121,33,49,50,41,91,-115,-33,71,47,-70,45,89,-115,72,106,-22,100,97,-100,-95,108,-33,3,14,30} + +#define HIDDEN_STATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define INPUT_DATA1 {-367,-338,0,-89,453,-413,-343,-16,42,418,201,274,-352,477,-290,-92,266,-49,342,453,-398,247,-153,328,217,342,85,69,-38,351,73,128} + +#define INPUT_DATA2 {280,41,-322,61,315,350,504,-227,-221,-483,352,252,455,-236,344,364,-378,229,-187,-498,295,357,-511,58,-349,-458,-420,-66,-400,-379,477,-60} + +#define HISTORY_DATA {-38,53,105,-79,-463,51,-343,-226,-435,-282,218,441,-299,-215,-109,335,340,-471,-109,273,33,-245,-469,170,-26,-59,192,-119,76,-6,236,-145} diff --git a/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/readme_iar.txt b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/readme_iar.txt new file mode 100644 index 0000000..a73e193 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Examples/IAR/iar_nn_examples/NN-example-gru/readme_iar.txt @@ -0,0 +1,7 @@ +CMSIS NN Lib example arm_nnexample_gru0 for + Cortex-M0, Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for IAR Embedded Workbench for ARM Simulator. + +When changing target, remember to change the ARM_MATH_CMx and __FPU_PRESENT +Preprocessor defines for C/C++ Compiler \ No newline at end of file diff --git a/FW/Drivers/CMSIS/NN/Include/arm_nn_tables.h b/FW/Drivers/CMSIS/NN/Include/arm_nn_tables.h new file mode 100644 index 0000000..36be5a8 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Include/arm_nn_tables.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_tables.h + * Description: Extern declaration for NN tables + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_NN_TABLES_H +#define _ARM_NN_TABLES_H + +#include "arm_math.h" + +/** +* @brief tables for various activation functions +* +*/ + +extern const q15_t sigmoidTable_q15[256]; +extern const q7_t sigmoidTable_q7[256]; + +extern const q7_t tanhTable_q7[256]; +extern const q15_t tanhTable_q15[256]; + + /** + * @brief 2-way tables for various activation functions + * + * 2-way table, H table for value larger than 1/4 + * L table for value smaller than 1/4, H table for remaining + * We have this only for the q15_t version. It does not make + * sense to have it for q7_t type + */ +extern const q15_t sigmoidHTable_q15[192]; +extern const q15_t sigmoidLTable_q15[128]; + +#endif /* ARM_NN_TABLES_H */ diff --git a/FW/Drivers/CMSIS/NN/Include/arm_nnfunctions.h b/FW/Drivers/CMSIS/NN/Include/arm_nnfunctions.h new file mode 100644 index 0000000..331255b --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Include/arm_nnfunctions.h @@ -0,0 +1,1075 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnfunctions.h + * Description: Public header file for CMSIS NN Library + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS NN Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS NN software library, + * a collection of efficient neural network kernels developed to maximize the + * performance and minimize the memory footprint of neural networks on Cortex-M processor cores. + * + * The library is divided into a number of functions each covering a specific category: + * - Neural Network Convolution Functions + * - Neural Network Activation Functions + * - Fully-connected Layer Functions + * - Neural Network Pooling Functions + * - Softmax Functions + * - Neural Network Support Functions + * + * The library has separate functions for operating on different weight and activation data + * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the + * kernels are included in the function description. The implementation details are also + * described in this paper [1]. + * + * Block Diagram + * -------- + * \image html CMSIS-NN-OVERVIEW.PNG + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - ARM_MATH_DSP: + * + * Define macro ARM_MATH_DSP, If the silicon supports DSP instructions. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_NN_TRUNCATE: + * + * Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2018 Arm Limited. All rights reserved. + * + * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601 + */ + +/** + * @defgroup groupNN Neural Network Functions + * These functions perform basic operations for neural network layers. + */ + +#ifndef _ARM_NNFUNCTIONS_H +#define _ARM_NNFUNCTIONS_H + +#include "arm_nnsupportfunctions.h" +#include "arm_nn_tables.h" + +#define USE_INTRINSIC + +//#define ARM_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup NNConv Neural Network Convolution Functions + * + * Perform convolution layer + * + * The convolution is implemented in 2 steps: im2col and GEMM + * + * im2col is a process of converting each patch of image data into + * a column. After im2col, the convolution is computed as matrix-matrix + * multiplication. + * + * To reduce the memory footprint, the im2col is performed partially. + * Each iteration, only a few column (i.e., patches) are generated and + * computed with GEMM kernels similar to CMSIS-DSP arm_mat_mult functions. + * + */ + + /** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_convolve_HWC_q7_basic(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ + + arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_convolve_HWC_q15_basic(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q7_fast(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for + * second half of MobileNets after depthwise separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 version of convolution for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + + arm_status arm_convolve_HWC_q7_RGB(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q15_fast(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + + arm_status + arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + + arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + +/** + * @defgroup FC Fully-connected Layer Functions + * + * Perform fully-connected layer + * + * Fully-connected layer is basically a matrix-vector multiplication + * with bias. The matrix is the weights and the input/output vectors + * are the activation values. Supported {weight, activation} precisions + * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}. + * + * Here we have two types of kernel functions. The basic function + * implements the function using regular GEMV approach. The opt functions + * operates with weights in interleaved formats. + * + */ + + /** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q7(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q7_opt(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q15 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q15(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + */ + + arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + +/** + * @brief Matrix-Multiplication Kernels for Convolution + * + * These functions are used within convolution layer functions for + * matrix multiplication. + * + * The implementation is similar to CMSIS-DSP arm_mat_mult functions + * with one Q7 and one Q15 operands. The Q15 operand is the im2col + * output which is always with 2 columns. + * + */ + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + + q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + + q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + +#ifdef __cplusplus +} +#endif + +/* + * Other functions + * These layers are typically not timing critical + * Basic implementation is supported here + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup Acti Neural Network Activation Functions + * + * Perform activation layers, including ReLU (Rectified Linear Unit), + * sigmoid and tanh + * + */ + + /** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + + void arm_relu_q7(q7_t * data, uint16_t size); + + /** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + + void arm_relu_q15(q15_t * data, uint16_t size); + + /** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + + void arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, + arm_nn_activation_type type); + + /** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + + void arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width, + arm_nn_activation_type type); + +/** + * @defgroup Pooling Neural Network Pooling Functions + * + * Perform pooling functions, including max pooling and average pooling + * + */ + + /** + * @brief Q7 max pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + + void arm_maxpool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t * bufferA, + q7_t * Im_out); + + /** + * @brief Q7 average pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + + void arm_avepool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t * bufferA, + q7_t * Im_out); + +/** + * @defgroup Softmax Softmax Functions + * + * EXP(2) based softmax function + * + */ + + /** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + */ + + void arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out); + + /** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + */ + + void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out); + + /** + * @brief uint8 depthwise convolution function with asymmetric quantization for even number of channel multiplier + * and input channels. Unless specified otherwise, arguments are mandatory. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * ARM_MATH_SUCCESS - Successful operation + * ARM_MATH_ARGUMENT_ERROR - Implementation not available + * + * Input constraints + * ch_mult is multiple of 2 + * kernel_x is multiple of 2 + * + */ + arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FW/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h b/FW/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h new file mode 100644 index 0000000..af426e1 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Include/arm_nnsupportfunctions.h @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnsupportfunctions.h + * Description: Public header file of support functions for CMSIS NN Library + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NNSUPPORTFUNCTIONS_H_ +#define _ARM_NNSUPPORTFUNCTIONS_H_ + +#include "arm_math.h" +#include "arm_common_tables.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define LEFT_SHIFT(_shift) (_shift > 0 ? _shift : 0) +#define RIGHT_SHIFT(_shift) (_shift > 0 ? 0 : -_shift) +#define Q31_MIN (0x80000000L) +#define Q31_MAX (0x7FFFFFFFL) + +/** + * @brief Union for SIMD access of Q31/Q15/Q7 types + */ +union arm_nnword +{ + q31_t word; + /**< Q31 type */ + q15_t half_words[2]; + /**< Q15 type */ + q7_t bytes[4]; + /**< Q7 type */ +}; + +/** + * @brief Struct for specifying activation function types + * + */ +typedef enum +{ + ARM_SIGMOID = 0, + /**< Sigmoid activation function */ + ARM_TANH = 1, + /**< Tanh activation function */ +} arm_nn_activation_type; + +/** + * @defgroup nndata_convert Neural Network Data Conversion Functions + * + * Perform data type conversion in-between neural network operations + * + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ + +void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize); + +#if defined (ARM_MATH_DSP) + +/** + * @brief read and expand one Q7 word into two Q15 words + */ + +__STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2) +{ + q31_t inA = *__SIMD32(source)++; + q31_t inAbuf1 = __SXTB16(__ROR(inA, 8)); + q31_t inAbuf2 = __SXTB16(inA); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __PKHTB(inAbuf1, inAbuf2, 16); + *out1 = __PKHBT(inAbuf2, inAbuf1, 16); +#else + *out1 = __PKHTB(inAbuf1, inAbuf2, 16); + *out2 = __PKHBT(inAbuf2, inAbuf1, 16); +#endif + + return source; +} + +/** + * @brief read and expand one Q7 word into two Q15 words with reordering + */ + +__STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2) +{ + q31_t inA = *__SIMD32(source)++; +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR(inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR(inA, 8)); + *out2 = __SXTB16(inA); +#endif + + return source; +} +#endif + +/** + * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation + * + * Basic Math Functions for Neural Network Computation + * + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize); + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize); + +/** + * @brief macro for adding rounding offset + */ +#ifndef ARM_NN_TRUNCATE + #define NN_ROUND(out_shift) ( (0x1u << out_shift) >> 1 ) +#else + #define NN_ROUND(out_shift) 0 +#endif + +/** + * @brief Saturating doubling high multiply. Result matches + * NEON instruction VQRDMULH. + * @param[in] m1 Multiplicand + * @param[in] m2 Multiplier + * @return Result of multiplication. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_sat_doubling_high_mult(const q31_t m1, const q31_t m2) +{ + q31_t result = 0; + // Rounding offset to add for a right shift of 31 + q63_t mult = 1 << 30; + + if ((m1 < 0) ^ (m2 < 0)) + { + mult = 1 - mult; + } + // Gets resolved as a SMLAL instruction + mult = mult + (q63_t)m1 * m2; + + // Utilize all of the upper 32 bits. This is the doubling step + // as well. + result = mult / (1UL << 31); + + if ((m1 == m2) && (m1 == Q31_MIN)) + { + result = Q31_MAX; + } + return result; +} + +/** + * @brief Rounding divide by power of two. + * @param[in] dividend - Dividend + * @param[in] exponent - Divisor = power(2, exponent) + * Range: [0, 31] + * @return Rounded result of division. Midpoint is rounded away from zero. + * + */ +__STATIC_FORCEINLINE q31_t arm_nn_divide_by_power_of_two(const q31_t dividend, const q31_t exponent) +{ + q31_t result = 0; + const q31_t remainder_mask = (1l << exponent) - 1; + int32_t remainder = remainder_mask & dividend; + + // Basic division + result = dividend >> exponent; + + // Adjust 'result' for rounding (mid point away from zero) + q31_t threshold = remainder_mask >> 1; + if (result < 0) + { + threshold++; + } + if (remainder > threshold) + { + result++; + } + + return result; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s new file mode 100644 index 0000000..9fc447d --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s @@ -0,0 +1,242 @@ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..66829ad --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s new file mode 100644 index 0000000..e3ea17f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM3.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM3 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00080000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.c new file mode 100644 index 0000000..f08df7a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s new file mode 100644 index 0000000..dae6439 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000C00 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.c new file mode 100644 index 0000000..af23005 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 07. September 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */ + (3U << 11U*2U) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..116c5cb --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00100000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..070fa1e --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,83 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#elif defined (ARMCM4_FP) + #include "ARMCM4_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.c new file mode 100644 index 0000000..26edb9f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.c @@ -0,0 +1,295 @@ +/**************************************************************************//** + * @file startup_ARMCM7.s + * @brief CMSIS Core Device Startup File for + * ARMCM7 Device Series + * @version V5.00 + * @date 26. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + + +/*---------------------------------------------------------------------------- + Linker generated Symbols + *----------------------------------------------------------------------------*/ +extern uint32_t __etext; +extern uint32_t __data_start__; +extern uint32_t __data_end__; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; +extern uint32_t __bss_start__; +extern uint32_t __bss_end__; +extern uint32_t __StackTop; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#endif + +#ifndef __NO_SYSTEM_INIT +extern void SystemInit (void); /* CMSIS System Initialization */ +#endif + + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void); /* Default empty handler */ +void Reset_Handler(void); /* Reset Handler */ + + +/*---------------------------------------------------------------------------- + User Initial Stack & Heap + *----------------------------------------------------------------------------*/ +#ifndef __STACK_SIZE + #define __STACK_SIZE 0x00000400 +#endif +static uint8_t stack[__STACK_SIZE] __attribute__ ((aligned(8), used, section(".stack"))); + +#ifndef __HEAP_SIZE + #define __HEAP_SIZE 0x00000C00 +#endif +#if __HEAP_SIZE > 0 +static uint8_t heap[__HEAP_SIZE] __attribute__ ((aligned(8), used, section(".heap"))); +#endif + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Cortex-M7 Processor Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/* ARMCM7 Specific Interrupts */ +void WDT_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void RTC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void TIM2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIA_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MCIB_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART0_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART1_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART2_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART4_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void AACI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void ENET_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBDC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void USBHC_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CHLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FLEXRAY_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CAN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void LIN_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void I2C_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void CPU_CLCD_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UART3_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SPI_IRQHandler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc __Vectors[] __attribute__ ((section(".vectors"))) = { + /* Cortex-M7 Exceptions Handler */ + (pFunc)((uint32_t)&__StackTop), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* NMI Handler */ + HardFault_Handler, /* Hard Fault Handler */ + MemManage_Handler, /* MPU Fault Handler */ + BusFault_Handler, /* Bus Fault Handler */ + UsageFault_Handler, /* Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* SVCall Handler */ + DebugMon_Handler, /* Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* PendSV Handler */ + SysTick_Handler, /* SysTick Handler */ + + /* External interrupts */ + WDT_IRQHandler, /* 0: Watchdog Timer */ + RTC_IRQHandler, /* 1: Real Time Clock */ + TIM0_IRQHandler, /* 2: Timer0 / Timer1 */ + TIM2_IRQHandler, /* 3: Timer2 / Timer3 */ + MCIA_IRQHandler, /* 4: MCIa */ + MCIB_IRQHandler, /* 5: MCIb */ + UART0_IRQHandler, /* 6: UART0 - DUT FPGA */ + UART1_IRQHandler, /* 7: UART1 - DUT FPGA */ + UART2_IRQHandler, /* 8: UART2 - DUT FPGA */ + UART4_IRQHandler, /* 9: UART4 - not connected */ + AACI_IRQHandler, /* 10: AACI / AC97 */ + CLCD_IRQHandler, /* 11: CLCD Combined Interrupt */ + ENET_IRQHandler, /* 12: Ethernet */ + USBDC_IRQHandler, /* 13: USB Device */ + USBHC_IRQHandler, /* 14: USB Host Controller */ + CHLCD_IRQHandler, /* 15: Character LCD */ + FLEXRAY_IRQHandler, /* 16: Flexray */ + CAN_IRQHandler, /* 17: CAN */ + LIN_IRQHandler, /* 18: LIN */ + I2C_IRQHandler, /* 19: I2C ADC/DAC */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + 0, /* 26: Reserved */ + 0, /* 27: Reserved */ + CPU_CLCD_IRQHandler, /* 28: Reserved - CPU FPGA CLCD */ + 0, /* 29: Reserved - CPU FPGA */ + UART3_IRQHandler, /* 30: UART3 - CPU FPGA */ + SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) { + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0UL; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + SystemInit(); +#endif + +#ifndef __START +#define __START _start +#endif + __START(); + +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + + while(1); +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s new file mode 100644 index 0000000..0170ef4 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s @@ -0,0 +1,262 @@ +;/**************************************************************************//** +; * @file startup_ARMCM7.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM7 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00080000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WDT_IRQHandler ; 0: Watchdog Timer + DCD RTC_IRQHandler ; 1: Real Time Clock + DCD TIM0_IRQHandler ; 2: Timer0 / Timer1 + DCD TIM2_IRQHandler ; 3: Timer2 / Timer3 + DCD MCIA_IRQHandler ; 4: MCIa + DCD MCIB_IRQHandler ; 5: MCIb + DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA + DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA + DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA + DCD UART4_IRQHandler ; 9: UART4 - not connected + DCD AACI_IRQHandler ; 10: AACI / AC97 + DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt + DCD ENET_IRQHandler ; 12: Ethernet + DCD USBDC_IRQHandler ; 13: USB Device + DCD USBHC_IRQHandler ; 14: USB Host Controller + DCD CHLCD_IRQHandler ; 15: Character LCD + DCD FLEXRAY_IRQHandler ; 16: Flexray + DCD CAN_IRQHandler ; 17: CAN + DCD LIN_IRQHandler ; 18: LIN + DCD I2C_IRQHandler ; 19: I2C ADC/DAC + DCD 0 ; 20: Reserved + DCD 0 ; 21: Reserved + DCD 0 ; 22: Reserved + DCD 0 ; 23: Reserved + DCD 0 ; 24: Reserved + DCD 0 ; 25: Reserved + DCD 0 ; 26: Reserved + DCD 0 ; 27: Reserved + DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD + DCD 0 ; 29: Reserved - CPU FPGA + DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA + DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WDT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT TIM0_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT MCIA_IRQHandler [WEAK] + EXPORT MCIB_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT UART3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT AACI_IRQHandler [WEAK] + EXPORT CLCD_IRQHandler [WEAK] + EXPORT ENET_IRQHandler [WEAK] + EXPORT USBDC_IRQHandler [WEAK] + EXPORT USBHC_IRQHandler [WEAK] + EXPORT CHLCD_IRQHandler [WEAK] + EXPORT FLEXRAY_IRQHandler [WEAK] + EXPORT CAN_IRQHandler [WEAK] + EXPORT LIN_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT CPU_CLCD_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + +WDT_IRQHandler +RTC_IRQHandler +TIM0_IRQHandler +TIM2_IRQHandler +MCIA_IRQHandler +MCIB_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +UART4_IRQHandler +AACI_IRQHandler +CLCD_IRQHandler +ENET_IRQHandler +USBDC_IRQHandler +USBHC_IRQHandler +CHLCD_IRQHandler +FLEXRAY_IRQHandler +CAN_IRQHandler +LIN_IRQHandler +I2C_IRQHandler +CPU_CLCD_IRQHandler +SPI_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.c new file mode 100644 index 0000000..65bfaca --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device Series + * @version V5.00 + * @date 08. April 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#elif defined (ARMCM7_SP) + #include "ARMCM7_SP.h" +#elif defined (ARMCM7_DP) + #include "ARMCM7_DP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1) + SCB->CPACR |= ((3U << 10*2) | /* set CP10 Full Access */ + (3U << 11*2) ); /* set CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s new file mode 100644 index 0000000..9b70614 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s @@ -0,0 +1,395 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f411xe.s +;* Author : MCD Application Team +;* Version : V2.6.0 +;* Date : 04-November-2016 +;* Description : STM32F411xExx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.c new file mode 100644 index 0000000..bca0633 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.c @@ -0,0 +1,763 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.6.0 + * @date 04-November-2016 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..4459a74 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..f12e4f3 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..d4542f5 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..97ef09a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c new file mode 100644 index 0000000..0089709 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q15_ref(const q15_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q15_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q15_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c new file mode 100644 index 0000000..e355ebf --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void +arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) + +{ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} + + diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c new file mode 100644 index 0000000..560cd23 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c new file mode 100644 index 0000000..1e2d19e --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c new file mode 100644 index 0000000..1672a4e --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef ARM_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c new file mode 100644 index 0000000..6ebd1f0 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef ARM_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c new file mode 100644 index 0000000..09dd653 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c new file mode 100644 index 0000000..8fc74d4 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c new file mode 100644 index 0000000..2118f99 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c new file mode 100644 index 0000000..99ab4d9 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q15_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c new file mode 100644 index 0000000..567f964 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q7_opt_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 2; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c new file mode 100644 index 0000000..f59f3db --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q7_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c new file mode 100644 index 0000000..2cc6b72 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +void arm_nn_mult_q7_ref(q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) { + uint16_t i; + +for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; +#ifndef ARM_NN_TRUNCATE + pDst[i] = (q7_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 8); +#else + pDst[i] = (q7_t)__SSAT(product >> out_shift, 8); +#endif + } +} + +void arm_nn_mult_q15_ref(q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) { + uint16_t i; + +for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; +#ifndef ARM_NN_TRUNCATE + pDst[i] = (q15_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 16); +#else + pDst[i] = (q15_t)__SSAT(product >> out_shift, 16); +#endif + + + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c new file mode 100644 index 0000000..9a4adb2 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_avepool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } +} + +void arm_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c new file mode 100644 index 0000000..323fc11 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +void arm_relu_q7_ref(q7_t * data, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} + +void arm_relu_q15_ref(q15_t * data, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h new file mode 100644 index 0000000..74b79f8 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h @@ -0,0 +1,7 @@ +#define IP2_WEIGHT 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+ +#define IP4_WEIGHT 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+ +#define IP4_q7_q15_WEIGHT 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+ +#define IP4_WEIGHT_Q15 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diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h new file mode 100644 index 0000000..4a0647a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _REF_FUNCTIONS_H_ +#define _REF_FUNCTIONS_H_ + +#include "arm_math.h" +#include "arm_nnfunctions.h" +//#include "arm_nnsupportfunctions.h" +#include "fully_connected_testing_weights.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* + * + * Convolution reference implemenation + * + */ + + void arm_convolve_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + + void arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + + void arm_convolve_HWC_q15_ref(const q15_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q15_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q15_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + void arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + void arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + void arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + +/* + * + * Fully-connected reference implemenation + * + */ + + void arm_fully_connected_q7_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q15_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q7_opt_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + +/* + * + * Pooling reference implemenation + * + */ + + void arm_avepool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out); + + void arm_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out); + +/* + * + * Other reference implemenation + * + */ + + void arm_relu_q7_ref(q7_t * data, uint16_t size); + + void arm_relu_q15_ref(q15_t * data, uint16_t size); + + void arm_nn_mult_q7_ref(q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, const uint16_t out_shift, uint32_t blockSize); + + void arm_nn_mult_q15_ref(q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp new file mode 100644 index 0000000..5cf72a2 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp @@ -0,0 +1,801 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_nn_test.cpp +* +* Description: Example code for NN kernel testing. +* +* Target Processor: Cortex-M cores +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#include "arm_nnexamples_nn_test.h" + +//#define TEST_SIGMOID +//#define TEST_TANH +#define TEST_POOL +#define TEST_RELU +#define TEST_IP +#define TEST_CONV +#define TEST_NONSQUARE +#define TEST_NNMULT + +int test_index = 0; +q7_t test_flags[50]; +bool test_pass; + +int main() +{ + printf("start tests\n"); + + srand(1); + + // common pointers for testing data + q7_t *test1; + q15_t *test2; + q7_t *test3; + q15_t *test4; + + for (test_index = 0; test_index<50; test_index++) { + test_flags[test_index] = -1; + } + test_index = 0; + +#ifdef TEST_NNMULT +#define NNMULT_DIM 128 + test1 = new q7_t[NNMULT_DIM*2]; + test2 = new q15_t[NNMULT_DIM*2]; + test3 = new q7_t[NNMULT_DIM*2]; + test4 = new q15_t[NNMULT_DIM*2]; + + q7_t * mult_out_q7 = test3; + q7_t * mult_ref_q7 = test3 + NNMULT_DIM; + q15_t * mult_out_q15 = test4; + q15_t * mult_ref_q15 = test4 + NNMULT_DIM; + + for (int i=0;i= 2 || pool_out_opt[i] - pool_out_ref[i] >= 2) + { + printf("Output mismatch at %d, expected %d, actual %d\n", i, pool_out_ref[i], pool_out_opt[i]); + if_ave_pool_match = false; + } + } + if (if_ave_pool_match == true) + { + printf("Outputs match.\n"); + } + + delete[]test1; + delete[]test2; + delete[]test3; + +#endif + +#ifdef TEST_RELU + +#define RELU_DIM 127 + + test1 = new q7_t[RELU_DIM]; + test2 = new q15_t[RELU_DIM]; + test3 = new q7_t[RELU_DIM]; + test4 = new q15_t[RELU_DIM]; + + for (int i = 0; i < RELU_DIM; i++) + { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + q7_t *relu_ref_data_q7 = test1; + q7_t *relu_opt_data_q7 = test3; + q15_t *relu_ref_data_q15 = test2; + q15_t *relu_opt_data_q15 = test4; + + printf("Start ref relu q7 implementation\n"); + + arm_relu_q7_ref(relu_ref_data_q7, RELU_DIM); + + printf("Start opt relu q7 implementation\n"); + + arm_relu_q7(relu_opt_data_q7, RELU_DIM); + + verify_results_q7(relu_ref_data_q7, relu_opt_data_q7, RELU_DIM); + + printf("Start ref relu q15 implementation\n"); + + arm_relu_q15_ref(relu_ref_data_q15, RELU_DIM); + + printf("Start opt relu q15 implementation\n"); + + arm_relu_q15(relu_opt_data_q15, RELU_DIM); + + verify_results_q15(relu_ref_data_q15, relu_opt_data_q15, RELU_DIM); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_IP + +#define IP_ROW_DIM 127 +#define IP_COL_DIM 127 + + q7_t ip_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q7_t ip_q7_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT; + q7_t ip_q7_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_q7_q15_WEIGHT; + q15_t ip_q15_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q15_t ip_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT_Q15; + + test1 = new q7_t[IP_COL_DIM + IP_ROW_DIM]; + test2 = new q15_t[IP_COL_DIM]; + test3 = new q7_t[IP_ROW_DIM * 3]; + test4 = new q15_t[IP_COL_DIM + IP_ROW_DIM * 2]; + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) + { + test1[i] = rand() % 256 - 100; + } + for (int i = 0; i < IP_ROW_DIM * 3; i++) + { + test3[i] = 0; + } + + q7_t *ip_bias_q7 = test1 + IP_COL_DIM; + + q7_t *ip_out_q7_ref = test3; + q7_t *ip_out_q7_opt = test3 + IP_ROW_DIM; + q7_t *ip_out_q7_opt_fast = test3 + 2 * IP_ROW_DIM; + q15_t *ip_out_q15_ref = test4 + IP_COL_DIM; + q15_t *ip_out_q15_opt = test4 + IP_COL_DIM + IP_ROW_DIM; + + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start ref q7 implementation\n"); + + arm_fully_connected_q7_ref(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_ref, test2); + + printf("Start q7 implementation\n"); + + arm_fully_connected_q7(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt, test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + + printf("Start q7 ref opt implementation\n"); + + arm_fully_connected_q7_opt_ref(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q7_opt_fast, test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start q7 opt implementation\n"); + + arm_fully_connected_q7_opt(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt_fast, + test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) + { + test4[i] = (rand() % 65536 - 32768); + } + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q15 implementation\n"); + + arm_fully_connected_q15_ref(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_ref, NULL); + + printf("Start q15 implementation\n"); + + arm_fully_connected_q15(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q15 implementation\n"); + + arm_fully_connected_q15_opt_ref(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, + NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q15 implementation\n"); + + arm_fully_connected_q15_opt(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_ref(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_ref, + test2); + + printf("Start q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_opt, + test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_opt_ref(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_opt(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_NONSQUARE + +/* Use RCONV to differential with square CONV */ + +#define RCONV_IM_DIM_X 10 +#define RCONV_IM_DIM_Y 8 +#define RCONV_IM_CH 4 +#define RCONV_KER_DIM_X 5 +#define RCONV_KER_DIM_Y 3 +#define RCONV_STRIDE_X 1 +#define RCONV_STRIDE_Y 1 +#define RCONV_PADDING_X 2 +#define RCONV_PADDING_Y 1 +#define RCONV_OUT_CH 4 +#define RCONV_OUT_DIM_X 10 +#define RCONV_OUT_DIM_Y 8 + + test1 = new q7_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; + test2 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH]; + test3 = + new q7_t[RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) + { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; i++) + { + test3[i] = rand() % 256 - 100; + } + + q7_t *rconv_weight_q7 = test1; + q7_t *rconv_bias_q7 = test1 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + q15_t *rconv_buf = test2; + + q7_t *rconv_im_in_q7 = test3; + q7_t *rconv_im_out_ref_q7 = test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q7_t *rconv_im_out_opt_q7 = + test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q7 nonsquare opt implementation\n"); + arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q7 nonsquare basic implementation\n"); + arm_convolve_HWC_q7_basic_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start 1x1 conv q7 nonsquare fast implementation\n"); + arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start 1x1 conv q7 nonsquare dedicated function implementation\n"); + arm_convolve_1x1_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start depthwise separable conv q7 nonsquare ref implementation\n"); + arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start depthwise separable conv q7 nonsquare opt implementation\n"); + arm_depthwise_separable_conv_HWC_q7_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete[]test1; + delete[]test2; + delete[]test3; + + test2 = new q15_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; // weights + bias + test4 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH //buffer + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; // i/o + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) + { + test2[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + i++) + { + test4[i] = rand() % 256 - 100; + } + + q15_t *rconv_weight_q15 = test2; + q15_t *rconv_bias_q15 = test2 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + rconv_buf = test4; + + q15_t *rconv_im_in_q15 = test4 + 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_ref_q15 = rconv_im_in_q15 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_opt_q15 = rconv_im_out_ref_q15 + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q15 nonsquare ref implementation\n"); + arm_convolve_HWC_q15_nonsquare_ref(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_ref_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q5 nonsquare opt implementation\n"); + arm_convolve_HWC_q15_fast_nonsquare(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_opt_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete [] test2; + delete [] test4; +#endif + +#ifdef TEST_CONV + +#define CONV_IM_DIM 16 +#define CONV_IM_CH 16 +#define CONV_KER_DIM 5 +#define CONV_OUT_CH 16 +#define CONV_OUT_DIM 16 + + test1 = new q7_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test2 = + new q15_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test3 = new q7_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + test4 = new q15_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + + for (int i = 0; i < CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) + { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) + { + test2[i] = (rand() % 65536 - 32768); + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) + { + test3[i] = rand() % 256 - 100; + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) + { + test4[i] = (rand() % 65536 - 32768); + } + + q7_t *conv_weight_q7 = test1; + q7_t *conv_bias_q7 = test1 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q15_t *conv_weight_q15 = test2; + q15_t *conv_buf = test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + q15_t *conv_bias_q15 = + test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q7_t *conv_im_in_q7 = test3; + q7_t *conv_im_out_ref_q7 = test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q7_t *conv_im_out_opt_q7 = + test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + q15_t *conv_im_in_q15 = test4; + q15_t *conv_im_out_ref_q15 = test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q15_t *conv_im_out_opt_q15 = + test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 ref implementation\n"); + + arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 basic implementation\n"); + + arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 fast implementation\n"); + + arm_convolve_HWC_q7_fast(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing with RGB + printf("start q7 ref implementation for RGB\n"); + + arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 basic implementation for RGB\n"); + + arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 RGB implementation for RGB\n"); + + arm_convolve_HWC_q7_RGB(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing q15 + initialize_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 ref implementation\n"); + + arm_convolve_HWC_q15_ref(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_ref_q15, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q15 basic implementation\n"); + + arm_convolve_HWC_q15_basic(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 fast implementation\n"); + + arm_convolve_HWC_q15_fast(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // depthwise separable conv + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 depthwise_separable_conv ref implementation\n"); + + arm_depthwise_separable_conv_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 depthwise_separable_conv implementation\n"); + + arm_depthwise_separable_conv_HWC_q7(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + + test_pass = true; + test_index = 0; + while (test_flags[test_index] != -1) { + if (test_flags[test_index]) { + test_pass = false; + } + test_index ++; + } + if (test_pass) { + printf("All tests passed\n"); + } else { + printf("Test failed passed\n"); + } + + return 0; +} diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h new file mode 100644 index 0000000..264b755 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h @@ -0,0 +1,78 @@ +#ifndef _MAIN_H_ +#define _MAIN_H_ + +#include +#include +#include + +#include "arm_math.h" + +#include "arm_nnfunctions.h" +#include "ref_functions.h" + +extern int test_index; +extern q7_t test_flags[50]; + +void initialize_results_q7(q7_t * ref, q7_t * opt, int length) +{ + arm_fill_q7(0, ref, length); + arm_fill_q7(37, opt, length); +} + +void initialize_results_q15(q15_t * ref, q15_t * opt, int length) +{ + arm_fill_q15(0, ref, length); + arm_fill_q15(0x5F5, opt, length); +} + +void verify_results_q7(q7_t * ref, q7_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +void verify_results_q15(q15_t * ref, q15_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +#endif diff --git a/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt new file mode 100644 index 0000000..2e9e171 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_nnexample_nn_test for + Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c new file mode 100644 index 0000000..9c64e2a --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t) in & bit_mask; + q15_t value = lookup_table[__USAT(in >> shift_size, 8)]; + q15_t value2 = lookup_table[__USAT(1 + (in >> shift_size), 8)]; + + /* doing the interpolation here for better accuracy */ + out = ((q31_t) (full_frac - frac) * value + (q31_t) value2 * frac) >> shift_size; + + *pOut++ = out; + i--; + } + +} + +/** + * @} end of Acti group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c new file mode 100644 index 0000000..1ca429f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t) (in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c new file mode 100644 index 0000000..571d51c --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q15(q15_t * data, uint16_t size) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + uint16_t i = size >> 1; + q15_t *pIn = data; + q15_t *pOut = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = *__SIMD32(pIn)++; + + /* extract the first bit */ + buf = __ROR(in & 0x80008000, 15); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB16(0x00000000, buf); + + *__SIMD32(pOut)++ = in & (~mask); + i--; + } + + if (size & 0x1) + { + if (*pIn < 0) + { + *pIn = 0; + } + pIn++; + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Acti group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c new file mode 100644 index 0000000..013325c --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q7(q7_t * data, uint16_t size) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + uint16_t i = size >> 2; + q7_t *pIn = data; + q7_t *pOut = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = *__SIMD32(pIn)++; + + /* extract the first bit */ + buf = __ROR(in & 0x80808080, 7); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB8(0x00000000, buf); + + *__SIMD32(pOut)++ = in & (~mask); + i--; + } + + i = size & 0x3; + while (i) + { + if (*pIn < 0) + { + *pIn = 0; + } + pIn++; + i--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Acti group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..2f4133c --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise + * separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + * + * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications + * https://arxiv.org/abs/1704.04861 + */ + +arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ch_out; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 + || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer, + ch_im_in); + pBuffer += ch_im_in; + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + q31_t sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 + || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c new file mode 100644 index 0000000..00b5aa5 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status +arm_convolve_HWC_q15_basic(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + uint16_t im2col_out_pixel_index = 0; + q15_t *pBuffer = bufferA; + q15_t *pOut = Im_out; + q15_t *im_buffer = bufferA; + const q15_t *pA; + int i; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + pA = wt; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = im_buffer; + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA)++; + q31_t inB2 = *__SIMD32(pB)++; + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q15_t) __SSAT((sum >> out_shift), 16); + pOut++; + } + + /* counter reset */ + pBuffer = im_buffer; + im2col_out_pixel_index++; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c new file mode 100644 index 0000000..c9873c1 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status +arm_convolve_HWC_q15_fast(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA2)++; + q31_t inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel * dim_kernel; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c new file mode 100644 index 0000000..0274202 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 24. May 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status +arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA2)++; + q31_t inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c new file mode 100644 index 0000000..42bfb1f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Q7 convolution function for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals 3 + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_status +arm_convolve_HWC_q7_RGB(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, const uint16_t dim_im_out, q15_t * bufferA, q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + // This part implements the im2col function + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */ + *__SIMD32(pBuffer) = 0x0; + *(pBuffer + 2) = 0; + pBuffer += 3; + } else + { + /* + * Equivalent to: + * arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3); + */ + + const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3; + q31_t buf = *__SIMD32(pPixel); + + union arm_nnword top; + union arm_nnword bottom; + + top.word = __SXTB16(buf); + bottom.word = __SXTB16(__ROR(buf, 8)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * little-endian, | omit | 3rd | 2nd | 1st | + * MSB LSB + * top | 3rd | 1st |; bottom | omit | 2nd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = top.word; + * *(pBuffer+2) = bottom.half_words[0]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = top.half_words[0]; + *__SIMD32(pBuffer) = __PKHBT(bottom.word, top.word, 0); +#else + /* + * big-endian, | 1st | 2nd | 3rd | omit | + * MSB LSB + * top | 2nd | omit |; bottom | 1st | 3rd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = bottom.word; + * *(pBuffer+2) = top.half_words[1]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = bottom.half_words[0]; + *__SIMD32(pBuffer) = __PKHTB(top.word, bottom.word, 0); +#endif + pBuffer += 2; + } + } + } + + if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + 3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = 3 * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = 3 * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c new file mode 100644 index 0000000..a926086 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status +arm_convolve_HWC_q7_basic(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + ch_im_in * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c new file mode 100644 index 0000000..b426b92 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns ARM_MATH_SUCCESS + */ + +arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + ch_im_in * + dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c new file mode 100644 index 0000000..7b59d79 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in is multiple of 4 ( because of the SIMD32 read and swap ) + * + * ch_im_out is multipe of 2 ( bacause 2x2 mat_mult kernel ) + * + * The im2col converts the Q7 tensor input into Q15 column, which is stored in + * bufferA. There is reordering happenning during this im2col process with + * arm_q7_to_q15_reordered_no_shift. For every four elements, the second and + * third elements are swapped. + * + * The computation kernel arm_nn_mat_mult_kernel_q7_q15_reordered does the + * GEMM computation with the reordered columns. + * + * To speed-up the determination of the padding condition, we split the + * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}. + * This reduces the total number of boundary condition checks and improves + * the data copying performance. + */ + +arm_status +arm_convolve_HWC_q7_fast(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out - padding; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out - padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + + + (i_ker_y * + dim_im_in + + i_out_x * + stride - padding) * ch_im_in, pBuffer, ch_im_in * dim_kernel); + pBuffer += ch_im_in * dim_kernel; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..f2aa4a2 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out_y - padding_y; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out_x - padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + + (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in, + pBuffer, ch_im_in * dim_kernel_x); + pBuffer += ch_im_in * dim_kernel_x; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c new file mode 100644 index 0000000..b6cd573 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_conv_u8_basic_ver1.c + * Description: u8 depthwise convolution function + * + * $Date: June, 2019 + * $Revision: V.0.8.0 + * + * Target : Cortex-M cores with DSP extension + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" +#include +#include + +#define DILATION_X (1) +#define DILATION_Y (1) + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief uint8 depthwise convolution function with asymmetric quantization for even number of channel multiplier + * and input channels. Unless specified otherwise, arguments are mandatory. Both square and non-square inputs + * are accepted. + * + * @param[in] input Pointer to input tensor + * @param[in] input_x Width of input tensor + * @param[in] input_y Height of input tensor + * @param[in] input_ch Channels in input tensor + * @param[in] kernel Pointer to kernel weights + * @param[in] kernel_x Width of kernel + * @param[in] kernel_y Height of kernel + * @param[in] ch_mult Number of channel multiplier + * @param[in] pad_x Padding sizes x + * @param[in] pad_y Padding sizes y + * @param[in] stride_x Convolution stride along the width + * @param[in] stride_y Convolution stride along the height + * @param[in] dilation_x Dilation along width. Not used and intended for future enhancement. + * @param[in] dilation_y Dilation along height. Not used and intended for future enhancement. + * @param[in] bias Pointer to optional bias values. If no bias is + * availble, NULL is expected + * @param[in] input_offset Input tensor zero offset + * @param[in] filter_offset Kernel tensor zero offset + * @param[in] output_offset Output tensor zero offset + * @param[in,out] output Pointer to output tensor + * @param[in] output_x Width of output tensor + * @param[in] output_y Height of output tensor + * @param[in] output_activation_min Minimum value to clamp the output to. Range : {0, 255} + * @param[in] output_activation_max Minimum value to clamp the output to. Range : {0, 255} + * @param[in] out_shift Amount of right-shift for output + * @param[in] out_mult Output multiplier for requantization + * @return The function returns one of the following + * ARM_MATH_SIZE_MISMATCH - Not supported dimension of tensors + * ARM_MATH_SUCCESS - Successful operation + * ARM_MATH_ARGUMENT_ERROR - Implementation not available + * + * Input constraints + * ch_mult is multiple of 2 + * kernel_x is multiple of 2 + * + */ + +arm_status arm_depthwise_conv_u8_basic_ver1(const uint8_t *input, + const uint16_t input_x, + const uint16_t input_y, + const uint16_t input_ch, + const uint8_t *kernel, + const uint16_t kernel_x, + const uint16_t kernel_y, + const int16_t ch_mult, + const int16_t pad_x, + const int16_t pad_y, + const int16_t stride_x, + const int16_t stride_y, + const int16_t dilation_x, + const int16_t dilation_y, + const int32_t *bias, + const int32_t input_offset, + const int32_t filter_offset, + const int32_t output_offset, + uint8_t *output, + const uint16_t output_x, + const uint16_t output_y, + const int32_t output_activation_min, + const int32_t output_activation_max, + const int32_t out_shift, + const int32_t out_mult) +{ + arm_status status = ARM_MATH_SUCCESS; + #if defined (ARM_MATH_DSP) + int i_out = 0; + (void)dilation_x; + (void)dilation_y; + + const int32_t input_offset_pkd = (input_offset & 0xFFFF) | (input_offset & 0xFFFF) << 16; + const int32_t kernel_offset_pkd = (filter_offset & 0xFFFF) | (filter_offset & 0xFFFF) << 16; + + if (0 != ch_mult % 2 || 0 != kernel_x % 2) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (int i_out_y = 0; i_out_y < output_y; i_out_y++) + { + const int16_t base_idx_y = (i_out_y * stride_y) - pad_y; + for (int i_out_x = 0; i_out_x < output_x; i_out_x++) + { + const int16_t base_idx_x = (i_out_x * stride_x) - pad_x; + for (int i_input_ch = 0; i_input_ch < input_ch; i_input_ch++) + { + for (int i_ch_mult = 0; i_ch_mult < ch_mult; i_ch_mult += 2) + { + const int idx_out_ch = i_ch_mult + i_input_ch * ch_mult; + + int32_t acc_0 = 0; + int32_t acc_1 = 0; + if (NULL != bias) + { + acc_0 = bias[idx_out_ch]; + acc_1 = bias[idx_out_ch + 1]; + } + + for (int i_ker_y = 0; i_ker_y < kernel_y; i_ker_y++) + { + const int32_t idx_y = base_idx_y + DILATION_Y * i_ker_y; + const int32_t y_in_range = (idx_y >= 0) && (idx_y < input_y); + + for (int i_ker_x = 0; i_ker_x < kernel_x; i_ker_x += 2) + { + if (1 == y_in_range) + { + const int32_t idx_x = base_idx_x + DILATION_X * i_ker_x; + const int32_t idx_x1 = base_idx_x + DILATION_X * (i_ker_x + 1); + /* Range check for first input */ + if (idx_x >= 0 && idx_x < input_x) + { + const int32_t idx_0 = (idx_y * input_x + idx_x) * input_ch + i_input_ch; + + const int32_t ker_idx_0 = + (i_ker_y * kernel_x + i_ker_x) * (input_ch * ch_mult) + idx_out_ch; + const int32_t ker_idx_1 = ker_idx_0 + input_ch * ch_mult; + + int32_t input_pkd = input[idx_0] | (input[idx_0 + input_ch] << 16); + int32_t kernel_pkd = kernel[ker_idx_0] | (kernel[ker_idx_1] << 16); + + input_pkd = __SADD16(input_pkd, input_offset_pkd); + kernel_pkd = __SADD16(kernel_pkd, kernel_offset_pkd); + /* Range check for second input */ + if (idx_x1 >= input_x) + { + input_pkd &= 0xFFFF; + } + acc_0 = __SMLAD(input_pkd, kernel_pkd, acc_0); + + kernel_pkd = kernel[ker_idx_0 + 1] | (kernel[ker_idx_1 + 1] << 16); + kernel_pkd = __SADD16(kernel_pkd, kernel_offset_pkd); + acc_1 = __SMLAD(input_pkd, kernel_pkd, acc_1); + } + } + } + } + + /* Requantize and clamp output to provided range */ + acc_0 = arm_nn_divide_by_power_of_two(arm_nn_sat_doubling_high_mult( + acc_0 * (1 << LEFT_SHIFT(out_shift)), out_mult), + RIGHT_SHIFT(out_shift)); + + acc_0 += output_offset; + + if (output_activation_min > acc_0) + { + acc_0 = output_activation_min; + } + + if (acc_0 > output_activation_max) + { + acc_0 = output_activation_max; + } + output[i_out++] = acc_0; + + /* Requantize and clamp output to provided range */ + acc_1 = arm_nn_divide_by_power_of_two(arm_nn_sat_doubling_high_mult( + acc_1 * (1 << LEFT_SHIFT(out_shift)), out_mult), + RIGHT_SHIFT(out_shift)); + acc_1 += output_offset; + + if (output_activation_min > acc_1) + { + acc_1 = output_activation_min; + } + + if (acc_1 > output_activation_max) + { + acc_1 = output_activation_max; + } + output[i_out++] = acc_1; + } + } + } + } +#else + /* No available implementation. */ + status = ARM_MATH_ARGUMENT_ERROR; +#endif + return status; +} + +/** + * @} end of NNConv group + */ + + diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c new file mode 100644 index 0000000..68ebeb8 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c @@ -0,0 +1,418 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * Input dimension constraints: + * + * ch_im_in equals ch_im_out + * + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + */ + +arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *) bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel * dim_kernel) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] + "+r"(sum),[sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB), + [pA] "+r"(pA):[colCnt] + "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#else + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] + "+r"(sum),[sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB), + [pA] "+r"(pA):[colCnt] + "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel * dim_kernel) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = *__SIMD32(pA); + pA += ch_im_in; + inB.word = *__SIMD32(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel * dim_kernel); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + rowCnt--; + } + + /* clear counter and pointers */ + pBuffer = colBuffer; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; + int conv_out; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += + Im_in[(in_row * + dim_im_in + + in_col) * + ch_im_in + + i_ch_out] * wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + + i_out_x) * ch_im_out + i_ch_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; + +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c new file mode 100644 index 0000000..397f233 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c @@ -0,0 +1,411 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + +/* + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + * + */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *) bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile ("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt), + [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#else + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile ("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt), + [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#endif /*ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel_x * dim_kernel_y) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = *__SIMD32(pA); + pA += ch_im_in; + inB.word = *__SIMD32(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + rowCnt--; + } + + // clear counter and pointers + pBuffer = colBuffer; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + + /* Return to application */ + return ARM_MATH_SUCCESS; + +} + +/** + * @} end of NNConv group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c new file mode 100644 index 0000000..a4adc5d --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function does the matrix multiplication with weight matrix + * and 2 columns from im2col. + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ +#if defined (ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; + + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12); + pA2 = (q7_t *) read_and_pad((void *)pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inA11, inA12; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + } + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ + +} diff --git a/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c new file mode 100644 index 0000000..deef7c6 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_math.h" + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function assumes that data in pInBuffer are reordered + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ + +#if defined (ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA11, &inA12); + pA2 = (q7_t *) read_and_pad_reordered((void *)pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} diff --git a/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c new file mode 100644 index 0000000..2746967 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + */ + +arm_status +arm_fully_connected_mat_q7_vec_q15(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + pB2 = (q7_t *) read_and_pad((void *)pB2, &inM21, &inM22); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + + /*adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c new file mode 100644 index 0000000..7be156f --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + * Limitation: x4 version requires weight reordering to work + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 | + * + * | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 | + * + * | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 | + * + * The column left over will be in-order. + * which is: + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a12 | a22 | a31 | a41 | + * + * | a32 | a42 | a13 | a23 | a14 | a24 | + * + * | a33 | a43 | a34 | a44 | a15 | a25 | + * + * | a16 | a26 | a35 | a45 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + */ + +arm_status +arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, const q7_t * bias, q15_t * pOut, q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } + +#else + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#else + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c new file mode 100644 index 0000000..c3e7cf2 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + */ + +arm_status +arm_fully_connected_q15(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + const q15_t *pB2 = pB + dim_vec; + q15_t *pO = pOut; + const q15_t *pA; + const q15_t *pBias = bias; + uint16_t rowCnt = num_of_rows >> 1; + + /* this loop loops over different output */ + while (rowCnt) { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV1, inM1, inM2; + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + inM2 = *__SIMD32(pB2)++; + sum2 = __SMLAD(inV1, inM2, sum2); + + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + inM2 = *__SIMD32(pB2)++; + sum2 = __SMLAD(inV1, inM2, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2>> out_shift), 16)); + + /* adjust the pointers and counters */ + pB = pB + dim_vec; + rowCnt --; + } + + rowCnt = num_of_rows & 0x1; + + while (rowCnt) { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) { + q31_t inV1, inM1; + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while(colCnt) { + q15_t inV = *pA++; + q15_t inM = *pB++; + + sum += inV * inM; + + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt --; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c new file mode 100644 index 0000000..f7a3915 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * + * @details + * + * Buffer size: + * + * vec_buffer size: 0 + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original matrix looks like this: + * + * | a11 | a12 | a13 | + * + * | a21 | a22 | a23 | + * + * | a31 | a32 | a33 | + * + * | a41 | a42 | a43 | + * + * | a51 | a52 | a53 | + * + * | a61 | a62 | a63 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | + * + * Remaining rows are kept the same original order. + * + * So the stored weight matrix looks like this: + * + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 | + * + * | a62 | a63 | + */ + +arm_status +arm_fully_connected_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + q15_t *pO = pOut; + const q15_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + sum = __SMLAD(inV, inM11, sum); + inM12 = *__SIMD32(pB)++; + sum2 = __SMLAD(inV, inM12, sum2); + inM13 = *__SIMD32(pB)++; + sum3 = __SMLAD(inV, inM13, sum3); + inM14 = *__SIMD32(pB)++; + sum4 = __SMLAD(inV, inM14, sum4); + colCnt--; + } + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r0, [%[pB]], #16\n" + "smlad %[sum], r4, r0, %[sum]\n" + "ldr.w r1, [%[pB] , #-12]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r2, [%[pB] , #-8]\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "ldr.w r3, [%[pB] , #-4]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB++; + q15_t inM3 = *pB++; + q15_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM1, inM2; + + inM1 = *__SIMD32(pB)++; + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM1, sum); + + inM2 = *__SIMD32(pB)++; + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM2, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c new file mode 100644 index 0000000..d8efc04 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This basic function is designed to work with regular weight + * matrix without interleaving. + * + */ + +arm_status +arm_fully_connected_q7(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, const q7_t * bias, q7_t * pOut, q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q15_t *pA; + uint16_t rowCnt = num_of_rows >> 1; + + /* expand the vector into the buffer */ + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + pB2 = (q7_t *) read_and_pad_reordered((void *)pB2, &inM21, &inM22); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8)); + + /* adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + uint16_t colCnt = dim_vec >> 2; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + int i, j; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c new file mode 100644 index 0000000..e3d0874 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c @@ -0,0 +1,484 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns ARM_MATH_SUCCESS + * + * @details + * + * Buffer size: + * + * vec_buffer size: dim_vec + * + * This opt function is designed to work with interleaved weight + * matrix. The vector input is assumed in q7_t format, we call + * arm_q7_to_q15_no_shift_shuffle function to expand into + * q15_t format with certain weight re-ordering, refer to the function + * comments for more details. + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 | + * + * | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 | + * + * | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 | + * + * So within the kernel, we first read the re-ordered vector in as: + * + * | b1 | b3 | and | b2 | b4 | + * + * the four q31_t weights will look like + * + * | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 | + * + * | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 | + * + * The column left over will be in-order. + * which is: + * + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a13 | a23 | a31 | a41 | + * + * | a33 | a43 | a12 | a22 | a14 | a24 | + * + * | a32 | a42 | a34 | a44 | a15 | a25 | + * + * | a35 | a45 | a16 | a26 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + */ + +arm_status +arm_fully_connected_q7_opt(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q15_t *pA; + uint16_t rowCnt = num_of_rows >> 2; + + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } +#else + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#else + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum3 >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum4 >> out_shift), 8)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c new file mode 100644 index 0000000..5a60459 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ + q15_t out1, out2, out3, out4; /* temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* temporary variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read two samples at a time from sourceA */ + inA1 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB1 = *__SIMD32(pSrcB)++; + /* read two samples at a time from sourceA */ + inA2 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB2 = *__SIMD32(pSrcB)++; + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT((mul1 + NN_ROUND(out_shift)) >> out_shift, 16); + out2 = (q15_t) __SSAT((mul2 + NN_ROUND(out_shift)) >> out_shift, 16); + out3 = (q15_t) __SSAT((mul3 + NN_ROUND(out_shift)) >> out_shift, 16); + out4 = (q15_t) __SSAT((mul4 + NN_ROUND(out_shift)) >> out_shift, 16); + + /* store the result */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ + diff --git a/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c new file mode 100644 index 0000000..3735c04 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c new file mode 100644 index 0000000..c28f1a6 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, + 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, + 0x5e, 0x5f, 0x61, 0x62, 0x63, 0x65, 0x66, 0x67, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, 0x75, 0x76, + 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, + 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, + 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, + 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, + 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, 0x2e, + 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, + 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, 0x5a57, 0x5bfb, + 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, + 0x68a6, 0x69d2, 0x6af1, 0x6c05, 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, + 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, 0x1f5f, 0x20e0, + 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, + 0x3053, 0x3238, 0x3424, 0x3615, 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, + 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, 0x4cd3, 0x4dc8, 0x4ebb, + 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, + 0x56ef, 0x57cd, 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, + 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, 0x62cc, + 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, + 0x68a6, 0x693d, 0x69d2, 0x6a63, 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, + 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, + 0x0f42, 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, + 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, 0x162e, 0x16c3, + 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, + 0x1c81, 0x1d34, 0x1dea, 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, + 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, + 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, 0x351b, 0x3615, 0x370f, + 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, + 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, + 0x61, 0x65, 0x68, 0x6a, 0x6d, 0x6f, 0x71, 0x72, + 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, + 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, + 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, + 0x85, 0x85, 0x86, 0x87, 0x88, 0x88, 0x8a, 0x8b, + 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, + 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, 0xbf, + 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, + 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, 0x5a1a, 0x5df6, + 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, + 0x73dc, 0x753a, 0x7672, 0x7788, 0x787f, 0x795b, 0x7a1e, 0x7acb, + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, + 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, 0x9869, 0x9b50, + 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, + 0xc4d9, 0xcb52, 0xd221, 0xd941, 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, + 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, 0x3151, 0x34ae, 0x37f6, + 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, + 0x514d, 0x53a3, 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, + 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, 0x6b6e, + 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, + 0x73dc, 0x7490, 0x753a, 0x75da, 0x7672, 0x7701, 0x7788, 0x7807, + 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, + 0x849b, 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, + 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, 0x8ac6, 0x8b70, + 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, + 0x936b, 0x9492, 0x95c9, 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, + 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, + 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, 0xd5a8, 0xd941, 0xdcec, + 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; diff --git a/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c new file mode 100644 index 0000000..264e760 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * 
    
+ * 	pDst[n] = (q15_t) pSrc[n];   0 <= n < blockSize.    
+ *
+ * + */ + +void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0_FAMILY + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); + +#else + + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in2, in1, 16); + +#endif + + *__SIMD32(pDst)++ = out1; + *__SIMD32(pDst)++ = out2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of nndata_convert group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c new file mode 100644 index 0000000..7d29aa4 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * @details + * + * This function does the q7 to q15 expansion with re-ordering + * + * 
+ *                          |   A1   |   A2   |   A3   |   A4   |
+ *
+ *                           0      7 8     15 16    23 24    31
+ *
+ * + * is converted into: + * + * 
+ *  |       A1       |       A3       |   and  |       A2       |       A4       |
+ *
+ *   0             15 16            31          0             15 16            31
+ *
+ * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0_FAMILY + q31_t in; + q31_t in1, in2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + *__SIMD32(pDst)++ = in2; + *__SIMD32(pDst)++ = in1; +#else + *__SIMD32(pDst)++ = in1; + *__SIMD32(pDst)++ = in2; +#endif + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of q7_to_x group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/FW/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c new file mode 100644 index 0000000..2956774 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#if defined (ARM_MATH_DSP) + +/** + * @brief A few utility functions used by pooling functions + * + * + */ + +static void buffer_scale_back_q15_to_q7(q15_t * buffer, q7_t * target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t) (buffer[i] / scale); + } +} + +static void compare_and_replace_if_larger_q7(q7_t * base, // base data + const q7_t * target, // compare target + const uint16_t length // data length + ) +{ + q7_t *pIn = base; + const q7_t *pCom = target; + union arm_nnword in; + union arm_nnword com; + uint16_t cnt = length >> 2; + + while (cnt > 0u) + { + in.word = *__SIMD32(pIn); + com.word = *__SIMD32(pCom)++; + + // if version + if (com.bytes[0] > in.bytes[0]) + in.bytes[0] = com.bytes[0]; + if (com.bytes[1] > in.bytes[1]) + in.bytes[1] = com.bytes[1]; + if (com.bytes[2] > in.bytes[2]) + in.bytes[2] = com.bytes[2]; + if (com.bytes[3] > in.bytes[3]) + in.bytes[3] = com.bytes[3]; + + *__SIMD32(pIn)++ = in.word; + + cnt--; + } + + cnt = length & 0x3; + while (cnt > 0u) + { + if (*pCom > *pIn) + { + *pIn = *pCom; + } + pIn++; + pCom++; + cnt--; + } +} + +static void accumulate_q7_to_q15(q15_t * base, q7_t * target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; + uint16_t cnt = length >> 2; + q31_t in; + + while (cnt > 0u) + { + q31_t value = *__SIMD32(pV)++; + v1 = __SXTB16(__ROR(value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + + vo2 = __PKHTB(v1, v2, 16); + vo1 = __PKHBT(v2, v1, 16); + +#else + + vo1 = __PKHTB(v1, v2, 16); + vo2 = __PKHBT(v2, v1, 16); + +#endif + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __QADD16(vo1, in); + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __QADD16(vo2, in); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + +#endif // ARM_MATH_DSP + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + + /** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + * @details + * + * Buffer size: + * + * bufferA size: 0 + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void +arm_maxpool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_x, i_y; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + /* arm_copy_q7(win_start, target, ch_im_in); */ + memmove(target, win_start, ch_im_in); + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + compare_and_replace_if_larger_q7(target, win_start, ch_im_in); + } + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + /* arm_copy_q7(row_start, target, dim_im_out * ch_im_in); */ + memmove(target, row_start, dim_im_out * ch_im_in); + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in); + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } + +#endif /* ARM_MATH_DSP */ + +} + + /** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + * @details + * + * Buffer size: + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void +arm_avepool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + q15_t *buffer = (q15_t *) bufferA; + int16_t i_x, i_y; + int16_t count = 0; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + arm_q7_to_q15_no_shift(win_start, buffer, ch_im_in); + count = 1; + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + accumulate_q7_to_q15(buffer, win_start, ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + arm_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + count = 1; + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Pooling group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/FW/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c new file mode 100644 index 0000000..abc2737 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 20. February 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + * @details + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17+base-vec_in[i], 5); + p_out[i] = (q15_t) __SSAT((output_base >> shift), 16); + } else + { + p_out[i] = 0; + } + } + +} + +/** + * @} end of Softmax group + */ diff --git a/FW/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/FW/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c new file mode 100644 index 0000000..a4e2548 --- /dev/null +++ b/FW/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: 20. February 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -257; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - 8; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = 0x100000 / sum; + + /* + * Final confidence will be output_base >> ( 13 - (vec_in[i] - base) ) + * so 128 (0x1<<7) -> 100% confidence when sum = 0x1 << 8, output_base = 0x1 << 12 + * and vec_in[i]-base = 8 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13+base-vec_in[i], 5); + p_out[i] = (q7_t) __SSAT((output_base >> shift), 8); + } else { + p_out[i] = 0; + } + } +} + +/** + * @} end of Softmax group + */ diff --git a/FW/Drivers/CMSIS/RTOS/Template/cmsis_os.h b/FW/Drivers/CMSIS/RTOS/Template/cmsis_os.h new file mode 100644 index 0000000..30068d3 --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS/Template/cmsis_os.h @@ -0,0 +1,698 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. February 2013 + * $Revision: V1.02 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + *---------------------------------------------------------------------------- + * + * Copyright (c) 2013-2017 ARM LIMITED + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value. +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value. +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + +#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter +/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS. +/// \return RTOS kernel system timer as 32-bit value +uint32_t osKernelSysTick (void); + +/// The RTOS kernel system timer frequency in Hz +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#define osKernelSysTickFrequency 100000000 + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) + +#endif // System Timer available + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof (type) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/FW/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h b/FW/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h new file mode 100644 index 0000000..e0b602c --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS2/Include/cmsis_os2.h @@ -0,0 +1,756 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 18. June 2018 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS2 API + * Title: cmsis_os2.h header file + * + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.0.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as null-terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as null-terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as null-terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as null-terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as null-terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as null-terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as null-terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Memory Pool. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/FW/Drivers/CMSIS/RTOS2/Include/os_tick.h b/FW/Drivers/CMSIS/RTOS2/Include/os_tick.h new file mode 100644 index 0000000..8f7cdf6 --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS2/Include/os_tick.h @@ -0,0 +1,71 @@ +/**************************************************************************//** + * @file os_tick.h + * @brief CMSIS OS Tick header file + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef OS_TICK_H +#define OS_TICK_H + +#include + +/// IRQ Handler. +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +typedef void (*IRQHandler_t) (void); +#endif + +/// Setup OS Tick timer to generate periodic RTOS Kernel Ticks +/// \param[in] freq tick frequency in Hz +/// \param[in] handler tick IRQ handler +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); + +/// Enable OS Tick timer interrupt +void OS_Tick_Enable (void); + +/// Disable OS Tick timer interrupt +void OS_Tick_Disable (void); + +/// Acknowledge execution of OS Tick timer interrupt +void OS_Tick_AcknowledgeIRQ (void); + +/// Get OS Tick timer IRQ number +/// \return OS Tick IRQ number +int32_t OS_Tick_GetIRQn (void); + +/// Get OS Tick timer clock frequency +/// \return OS Tick timer clock frequency in Hz +uint32_t OS_Tick_GetClock (void); + +/// Get OS Tick timer interval reload value +/// \return OS Tick timer interval reload value +uint32_t OS_Tick_GetInterval (void); + +/// Get OS Tick timer counter value +/// \return OS Tick timer counter value +uint32_t OS_Tick_GetCount (void); + +/// Get OS Tick timer overflow status +/// \return OS Tick overflow status (1 - overflow, 0 - no overflow). +uint32_t OS_Tick_GetOverflow (void); + +#endif /* OS_TICK_H */ diff --git a/FW/Drivers/CMSIS/RTOS2/Source/os_systick.c b/FW/Drivers/CMSIS/RTOS2/Source/os_systick.c new file mode 100644 index 0000000..985a9d9 --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS2/Source/os_systick.c @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file os_systick.c + * @brief CMSIS OS Tick SysTick implementation + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" + +//lint -emacro((923,9078),SCB,SysTick) "cast from unsigned long to pointer" +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifdef SysTick + +#ifndef SYSTICK_IRQ_PRIORITY +#define SYSTICK_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PendST; + +// Setup OS Tick. +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + (void)handler; + + if (freq == 0U) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + load = (SystemCoreClock / freq) - 1U; + if (load > 0x00FFFFFFU) { + //lint -e{904} "Return statement before end of function" + return (-1); + } + + // Set SysTick Interrupt Priority +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ != 0)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ != 0)) + SCB->SHPR[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ != 0)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ != 0))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ != 0)) + SCB->SHP[1] |= ((uint32_t)SYSTICK_IRQ_PRIORITY << 24); +#else +#error "Unknown ARM Core!" +#endif + + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->LOAD = load; + SysTick->VAL = 0U; + + PendST = 0U; + + return (0); +} + +/// Enable OS Tick. +__WEAK void OS_Tick_Enable (void) { + + if (PendST != 0U) { + PendST = 0U; + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } + + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; +} + +/// Disable OS Tick. +__WEAK void OS_Tick_Disable (void) { + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + PendST = 1U; + } +} + +// Acknowledge OS Tick IRQ. +__WEAK void OS_Tick_AcknowledgeIRQ (void) { + (void)SysTick->CTRL; +} + +// Get OS Tick IRQ number. +__WEAK int32_t OS_Tick_GetIRQn (void) { + return ((int32_t)SysTick_IRQn); +} + +// Get OS Tick clock. +__WEAK uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +__WEAK uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +// Get OS Tick count value. +__WEAK uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +// Get OS Tick overflow status. +__WEAK uint32_t OS_Tick_GetOverflow (void) { + return ((SysTick->CTRL >> 16) & 1U); +} + +#endif // SysTick diff --git a/FW/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c b/FW/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c new file mode 100644 index 0000000..22cfa93 --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c @@ -0,0 +1,187 @@ +/**************************************************************************//** + * @file os_tick_gtim.c + * @brief CMSIS OS Tick implementation for Generic Timer + * @version V1.0.1 + * @date 24. November 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include "RTE_Components.h" +#include CMSIS_device_header + +#ifndef GTIM_IRQ_PRIORITY +#define GTIM_IRQ_PRIORITY 0xFFU +#endif + +#ifndef GTIM_IRQ_NUM +#define GTIM_IRQ_NUM SecurePhyTimer_IRQn +#endif + +// Timer interrupt pending flag +static uint8_t GTIM_PendIRQ; + +// Timer tick frequency +static uint32_t GTIM_Clock; + +// Timer load value +static uint32_t GTIM_Load; + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t prio, bits; + + if (freq == 0U) { + return (-1); + } + + GTIM_PendIRQ = 0U; + + // Get timer clock +#ifdef SCTR_BASE + GTIM_Clock = *(uint32_t*)(SCTR_BASE+0x20); +#else + // FVP REFCLK CNTControl 100MHz + GTIM_Clock = 100000000UL; +#endif + + PL1_SetCounterFrequency(GTIM_Clock); + + // Calculate load value + GTIM_Load = (GTIM_Clock / freq) - 1U; + + // Disable Generic Timer and set load value + PL1_SetControl(0U); + PL1_SetLoadValue(GTIM_Load); + + // Disable corresponding IRQ + IRQ_Disable(GTIM_IRQ_NUM); + IRQ_ClearPending(GTIM_IRQ_NUM); + + // Determine number of implemented priority bits + IRQ_SetPriority(GTIM_IRQ_NUM, 0xFFU); + + prio = IRQ_GetPriority(GTIM_IRQ_NUM); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (GTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(GTIM_IRQ_NUM, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(GTIM_IRQ_NUM, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(GTIM_IRQ_NUM, handler); + + // Enable corresponding interrupt + IRQ_Enable(GTIM_IRQ_NUM); + + // Enable system counter and timer control +#ifdef SCTR_BASE + *(uint32_t*)SCTR_BASE |= 3U; +#endif + + // Enable timer control + PL1_SetControl(1U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (GTIM_PendIRQ != 0U) { + GTIM_PendIRQ = 0U; + IRQ_SetPending (GTIM_IRQ_NUM); + } + + // Start the Private Timer + ctrl = PL1_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PL1_SetControl(ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PL1_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PL1_SetControl(ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(GTIM_IRQ_NUM) != 0) { + IRQ_ClearPending(GTIM_IRQ_NUM); + GTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + IRQ_ClearPending (GTIM_IRQ_NUM); + PL1_SetLoadValue(GTIM_Load); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (GTIM_IRQ_NUM); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (GTIM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (GTIM_Load + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + return (GTIM_Load - PL1_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + CNTP_CTL_Type cntp_ctl; + cntp_ctl.w = PL1_GetControl(); + return (cntp_ctl.b.ISTATUS); +} diff --git a/FW/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c b/FW/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c new file mode 100644 index 0000000..e75ac3a --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c @@ -0,0 +1,165 @@ +/**************************************************************************//** + * @file os_tick_ptim.c + * @brief CMSIS OS Tick implementation for Private Timer + * @version V1.0.2 + * @date 02. March 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#if defined(PTIM) + +#include "os_tick.h" +#include "irq_ctrl.h" + +#ifndef PTIM_IRQ_PRIORITY +#define PTIM_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PTIM_PendIRQ; // Timer interrupt pending flag + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + PTIM_PendIRQ = 0U; + + // Private Timer runs with the system frequency + load = (SystemCoreClock / freq) - 1U; + + // Disable Private Timer and set load value + PTIM_SetControl (0U); + PTIM_SetLoadValue (load); + + // Disable corresponding IRQ + IRQ_Disable (PrivTimer_IRQn); + IRQ_ClearPending(PrivTimer_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (PrivTimer_IRQn, 0xFFU); + + prio = IRQ_GetPriority (PrivTimer_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(PrivTimer_IRQn, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(PrivTimer_IRQn, handler); + + // Enable corresponding interrupt + IRQ_Enable (PrivTimer_IRQn); + + // Set bits: IRQ enable and Auto reload + PTIM_SetControl (0x06U); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (PTIM_PendIRQ != 0U) { + PTIM_PendIRQ = 0U; + IRQ_SetPending (PrivTimer_IRQn); + } + + // Start the Private Timer + ctrl = PTIM_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PTIM_SetControl (ctrl); +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PTIM_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PTIM_SetControl (ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(PrivTimer_IRQn) != 0) { + IRQ_ClearPending (PrivTimer_IRQn); + PTIM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) { + PTIM_ClearEventFlag(); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (PrivTimer_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (PTIM_GetLoadValue() + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + uint32_t load = PTIM_GetLoadValue(); + return (load - PTIM_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return (PTIM->ISR & 1); +} + +#endif // PTIM diff --git a/FW/Drivers/CMSIS/RTOS2/Template/cmsis_os.h b/FW/Drivers/CMSIS/RTOS2/Template/cmsis_os.h new file mode 100644 index 0000000..376dbf7 --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS2/Template/cmsis_os.h @@ -0,0 +1,922 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 18. June 2018 + * $Revision: V2.1.3 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h template header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedefs + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * Version 2.0.0 + * OS objects creation without macros (dynamic creation and resource allocation): + * - added: osXxxxNew functions which replace osXxxxCreate + * - added: osXxxxAttr_t structures + * - deprecated: osXxxxCreate functions, osXxxxDef_t structures + * - deprecated: osXxxxDef and osXxxx macros + * osStatus codes simplified and renamed to osStatus_t + * osEvent return structure deprecated + * Kernel: + * - added: osKernelInfo_t and osKernelGetInfo + * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning) + * - added: osKernelLock, osKernelUnlock + * - added: osKernelSuspend, osKernelResume + * - added: osKernelGetTickCount, osKernelGetTickFreq + * - renamed osKernelSysTick to osKernelGetSysTimerCount + * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq + * - deprecated osKernelSysTickMicroSec + * Thread: + * - extended number of thread priorities + * - renamed osPrioriry to osPrioriry_t + * - replaced osThreadCreate with osThreadNew + * - added: osThreadGetName + * - added: osThreadState_t and osThreadGetState + * - added: osThreadGetStackSize, osThreadGetStackSpace + * - added: osThreadSuspend, osThreadResume + * - added: osThreadJoin, osThreadDetach, osThreadExit + * - added: osThreadGetCount, osThreadEnumerate + * - added: Thread Flags (moved from Signals) + * Signals: + * - renamed osSignals to osThreadFlags (moved to Thread Flags) + * - changed return value of Set/Clear/Wait functions + * - Clear function limited to current running thread + * - extended Wait function (options) + * - added: osThreadFlagsGet + * Event Flags: + * - added new independent object for handling Event Flags + * Delay and Wait functions: + * - added: osDelayUntil + * - deprecated: osWait + * Timer: + * - replaced osTimerCreate with osTimerNew + * - added: osTimerGetName, osTimerIsRunning + * Mutex: + * - extended: attributes (Recursive, Priority Inherit, Robust) + * - replaced osMutexCreate with osMutexNew + * - renamed osMutexWait to osMutexAcquire + * - added: osMutexGetName, osMutexGetOwner + * Semaphore: + * - extended: maximum and initial token count + * - replaced osSemaphoreCreate with osSemaphoreNew + * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value) + * - added: osSemaphoreGetName, osSemaphoreGetCount + * Memory Pool: + * - using osMemoryPool prefix instead of osPool + * - replaced osPoolCreate with osMemoryPoolNew + * - extended osMemoryPoolAlloc (timeout) + * - added: osMemoryPoolGetName + * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize + * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace + * - added: osMemoryPoolDelete + * - deprecated: osPoolCAlloc + * Message Queue: + * - extended: fixed size message instead of a single 32-bit value + * - using osMessageQueue prefix instead of osMessage + * - replaced osMessageCreate with osMessageQueueNew + * - updated: osMessageQueuePut, osMessageQueueGet + * - added: osMessageQueueGetName + * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize + * - added: osMessageQueueGetCount, osMessageQueueGetSpace + * - added: osMessageQueueReset, osMessageQueueDelete + * Mail Queue: + * - deprecated (superseded by extended Message Queue functionality) + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil + * Version 2.1.2 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetInfo, osKernelGetState + * Version 2.1.3 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osThreadGetId + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS_H_ +#define CMSIS_OS_H_ + +/// \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_KERNEL 0x10000U ///< RTOS identification and version (main[31:16].sub[15:0]) + +/// \note CAN BE CHANGED: \b osKernelSystemId identifies the underlying RTOS kernel. +#define osKernelSystemId "KERNEL V1.0" ///< RTOS identification string + +/// \note CAN BE CHANGED: \b osFeature_xxx identifies RTOS features. +#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Signals 16U ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available + +#if (osCMSIS >= 0x20000U) +#include "cmsis_os2.h" +#else +#include +#include +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Priority values. +#if (osCMSIS < 0x20000U) +typedef enum { + osPriorityIdle = -3, ///< Priority: idle (lowest) + osPriorityLow = -2, ///< Priority: low + osPriorityBelowNormal = -1, ///< Priority: below normal + osPriorityNormal = 0, ///< Priority: normal (default) + osPriorityAboveNormal = +1, ///< Priority: above normal + osPriorityHigh = +2, ///< Priority: high + osPriorityRealtime = +3, ///< Priority: realtime (highest) + osPriorityError = 0x84, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority; +#else +#define osPriority osPriority_t +#endif + +/// Entry point of a thread. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +typedef void (*os_ptimer) (void const *argument); + +/// Timer type. +#if (osCMSIS < 0x20000U) +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} os_timer_type; +#else +#define os_timer_type osTimerType_t +#endif + +/// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +/// Status code values returned by CMSIS-RTOS functions. +#if (osCMSIS < 0x20000U) +typedef enum { + osOK = 0, ///< Function completed; no error or event occurred. + osEventSignal = 0x08, ///< Function completed; signal event occurred. + osEventMessage = 0x10, ///< Function completed; message event occurred. + osEventMail = 0x20, ///< Function completed; mail event occurred. + osEventTimeout = 0x40, ///< Function completed; timeout occurred. + osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< Resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< Value of a parameter is out of range. + osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus; +#else +typedef int32_t osStatus; +#define osEventSignal (0x08) +#define osEventMessage (0x10) +#define osEventMail (0x20) +#define osEventTimeout (0x40) +#define osErrorOS osError +#define osErrorTimeoutResource osErrorTimeout +#define osErrorISRRecursive (-126) +#define osErrorValue (-127) +#define osErrorPriority (-128) +#endif + + +// >>> the following data type definitions may be adapted towards a specific RTOS + +/// Thread ID identifies the thread. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osThreadId; +#else +#define osThreadId osThreadId_t +#endif + +/// Timer ID identifies the timer. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osTimerId; +#else +#define osTimerId osTimerId_t +#endif + +/// Mutex ID identifies the mutex. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osMutexId; +#else +#define osMutexId osMutexId_t +#endif + +/// Semaphore ID identifies the semaphore. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef void *osSemaphoreId; +#else +#define osSemaphoreId osSemaphoreId_t +#endif + +/// Pool ID identifies the memory pool. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osPoolId; + +/// Message ID identifies the message queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMessageQId; + +/// Mail ID identifies the mail queue. +/// \note CAN BE CHANGED: \b implementation specific in every CMSIS-RTOS. +typedef void *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; +#else +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osThreadAttr_t attr; ///< thread attributes +} osThreadDef_t; +#endif + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; +#else +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + osTimerAttr_t attr; ///< timer attributes +} osTimerDef_t; +#endif + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value +} osMutexDef_t; +#else +#define osMutexDef_t osMutexAttr_t +#endif + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value +} osSemaphoreDef_t; +#else +#define osSemaphoreDef_t osSemaphoreAttr_t +#endif + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; +#else +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + osMemoryPoolAttr_t attr; ///< memory pool attributes +} osPoolDef_t; +#endif + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; +#else +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + osMessageQueueAttr_t attr; ///< message queue attributes +} osMessageQDef_t; +#endif + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +#if (osCMSIS < 0x20000U) +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; +#else +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *mail; ///< pointer to mail + osMemoryPoolAttr_t mp_attr; ///< memory pool attributes + osMessageQueueAttr_t mq_attr; ///< message queue attributes +} osMailQDef_t; +#endif + + +/// Event structure contains detailed information about an event. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelInitialize (void); +#endif + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelStart (void); +#endif + +/// Check if the RTOS kernel is already started. +/// \return 0 RTOS is not started, 1 RTOS is started. +#if (osCMSIS < 0x20000U) +int32_t osKernelRunning(void); +#endif + +#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter. +/// \return RTOS kernel system timer as 32-bit value +#if (osCMSIS < 0x20000U) +uint32_t osKernelSysTick (void); +#else +#define osKernelSysTick osKernelGetSysTimerCount +#endif + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#if (osCMSIS < 0x20000U) +#define osKernelSysTickFrequency 100000000 +#endif + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#if (osCMSIS < 0x20000U) +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +#else +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) +#endif + +#endif // System Timer available + + +// ==== Thread Management Functions ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#else +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), \ + { NULL, osThreadDetached, NULL, 0U, NULL, 8*((stacksz+7)/8), (priority), 0U, 0U } } +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +#if (osCMSIS < 0x20000U) +osThreadId osThreadGetId (void); +#endif + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); +#endif + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the specified thread. +#if (osCMSIS < 0x20000U) +osPriority osThreadGetPriority (osThreadId thread_id); +#endif + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadYield (void); +#endif + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadTerminate (osThreadId thread_id); +#endif + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osDelay (uint32_t millisec); +#endif + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== + +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = { (function) } +#else +#define osTimerDef(name, function) \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), { NULL, 0U, NULL, 0U } } +#endif +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create and Initialize a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); +#endif + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStop (osTimerId timer_id); +#endif + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerDelete (osTimerId timer_id); +#endif + + +// ==== Mutex Management Functions ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = { 0 } +#else +#define osMutexDef(name) \ +const osMutexDef_t os_mutex_def_##name = \ +{ NULL, osMutexRecursive | osMutexPrioInherit | osMutexRobust, NULL, 0U } +#endif +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); +#else +#define osMutexWait osMutexAcquire +#endif + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexRelease (osMutexId mutex_id); +#endif + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexDelete (osMutexId mutex_id); +#endif + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = { 0 } +#else +#define osSemaphoreDef(name) \ +const osSemaphoreDef_t os_semaphore_def_##name = \ +{ NULL, 0U, NULL, 0U } +#endif +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count maximum and initial number of available tokens. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); +#endif + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); +#endif + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), NULL } +#else +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a Memory Pool object. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a Memory Pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool available + + +// ==== Message Queue Management Functions ==== + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), NULL } +#else +#define osMessageQDef(name, queue_sz, type) \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue object. +/// \param[in] queue_def message queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queue available + + +// ==== Mail Queue Management Functions ==== + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of mails in the queue. +/// \param type data type of a single mail element. +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#if (osCMSIS < 0x20000U) +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), NULL } +#else +#define osMailQDef(name, queue_sz, type) \ +static void *os_mail_p_##name[2]; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), (&os_mail_p_##name), \ + { NULL, 0U, NULL, 0U, NULL, 0U }, \ + { NULL, 0U, NULL, 0U, NULL, 0U } } +#endif +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize a Mail Queue object. +/// \param[in] queue_def mail queue definition referenced with \ref osMailQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block for mail from a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block for mail from a mail memory pool and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a Mail into a Queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory with mail to put into a queue. +/// \return status code that indicates the execution status of the function. +osStatus osMailPut (osMailQId queue_id, const void *mail); + +/// Get a Mail from a Queue or timeout if Queue is empty. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block by returning it to a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queue available + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS_H_ diff --git a/FW/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c b/FW/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c new file mode 100644 index 0000000..de1650c --- /dev/null +++ b/FW/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V1.2 + * + * Project: CMSIS-RTOS API V1 + * Title: cmsis_os_v1.c V1 module file + *---------------------------------------------------------------------------*/ + +#include +#include "cmsis_os.h" + +#if (osCMSIS >= 0x20000U) + + +// Thread +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { + + if (thread_def == NULL) { + return (osThreadId)NULL; + } + return osThreadNew((osThreadFunc_t)thread_def->pthread, argument, &thread_def->attr); +} + + +// Signals + +#define SignalMask ((1U< 0U) && (flags < 0x80000000U)) { + event.status = osEventSignal; + event.value.signals = (int32_t)flags; + } else { + switch ((int32_t)flags) { + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + case osErrorParameter: + event.status = osErrorValue; + break; + default: + event.status = (osStatus)flags; + break; + } + } + return event; +} + + +// Timer +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) { + + if (timer_def == NULL) { + return (osTimerId)NULL; + } + return osTimerNew((osTimerFunc_t)timer_def->ptimer, type, argument, &timer_def->attr); +} + + +// Mutex +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) { + + if (mutex_def == NULL) { + return (osMutexId)NULL; + } + return osMutexNew(mutex_def); +} + + +// Semaphore + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) + +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { + + if (semaphore_def == NULL) { + return (osSemaphoreId)NULL; + } + return osSemaphoreNew((uint32_t)count, (uint32_t)count, semaphore_def); +} + +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + osStatus_t status; + uint32_t count; + + status = osSemaphoreAcquire(semaphore_id, millisec); + switch (status) { + case osOK: + count = osSemaphoreGetCount(semaphore_id); + return ((int32_t)count + 1); + case osErrorResource: + case osErrorTimeout: + return 0; + default: + break; + } + return -1; +} + +#endif // Semaphore + + +// Memory Pool + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) + +osPoolId osPoolCreate (const osPoolDef_t *pool_def) { + + if (pool_def == NULL) { + return (osPoolId)NULL; + } + return ((osPoolId)(osMemoryPoolNew(pool_def->pool_sz, pool_def->item_sz, &pool_def->attr))); +} + +void *osPoolAlloc (osPoolId pool_id) { + return osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); +} + +void *osPoolCAlloc (osPoolId pool_id) { + void *block; + uint32_t block_size; + + block_size = osMemoryPoolGetBlockSize((osMemoryPoolId_t)pool_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc((osMemoryPoolId_t)pool_id, 0U); + if (block != NULL) { + memset(block, 0, block_size); + } + return block; +} + +osStatus osPoolFree (osPoolId pool_id, void *block) { + return osMemoryPoolFree((osMemoryPoolId_t)pool_id, block); +} + +#endif // Memory Pool + + +// Message Queue + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) + +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { + (void)thread_id; + + if (queue_def == NULL) { + return (osMessageQId)NULL; + } + return ((osMessageQId)(osMessageQueueNew(queue_def->queue_sz, sizeof(uint32_t), &queue_def->attr))); +} + +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + return osMessageQueuePut((osMessageQueueId_t)queue_id, &info, 0U, millisec); +} + +osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { + osStatus_t status; + osEvent event; + uint32_t message; + + status = osMessageQueueGet((osMessageQueueId_t)queue_id, &message, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMessage; + event.value.v = message; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +#endif // Message Queue + + +// Mail Queue + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) + +typedef struct os_mail_queue_s { + osMemoryPoolId_t mp_id; + osMessageQueueId_t mq_id; +} os_mail_queue_t; + +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { + os_mail_queue_t *ptr; + (void)thread_id; + + if (queue_def == NULL) { + return (osMailQId)NULL; + } + + ptr = queue_def->mail; + if (ptr == NULL) { + return (osMailQId)NULL; + } + + ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr); + ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr); + if ((ptr->mp_id == (osMemoryPoolId_t)NULL) || (ptr->mq_id == (osMessageQueueId_t)NULL)) { + if (ptr->mp_id != (osMemoryPoolId_t)NULL) { + osMemoryPoolDelete(ptr->mp_id); + } + if (ptr->mq_id != (osMessageQueueId_t)NULL) { + osMessageQueueDelete(ptr->mq_id); + } + return (osMailQId)NULL; + } + + return (osMailQId)ptr; +} + +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return NULL; + } + return osMemoryPoolAlloc(ptr->mp_id, millisec); +} + +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + void *block; + uint32_t block_size; + + if (ptr == NULL) { + return NULL; + } + block_size = osMemoryPoolGetBlockSize(ptr->mp_id); + if (block_size == 0U) { + return NULL; + } + block = osMemoryPoolAlloc(ptr->mp_id, millisec); + if (block != NULL) { + memset(block, 0, block_size); + } + + return block; + +} + +osStatus osMailPut (osMailQId queue_id, const void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMessageQueuePut(ptr->mq_id, &mail, 0U, 0U); +} + +osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + osStatus_t status; + osEvent event; + void *mail; + + if (ptr == NULL) { + event.status = osErrorParameter; + return event; + } + + status = osMessageQueueGet(ptr->mq_id, &mail, NULL, millisec); + switch (status) { + case osOK: + event.status = osEventMail; + event.value.p = mail; + break; + case osErrorResource: + event.status = osOK; + break; + case osErrorTimeout: + event.status = osEventTimeout; + break; + default: + event.status = status; + break; + } + return event; +} + +osStatus osMailFree (osMailQId queue_id, void *mail) { + os_mail_queue_t *ptr = (os_mail_queue_t *)queue_id; + + if (ptr == NULL) { + return osErrorParameter; + } + if (mail == NULL) { + return osErrorValue; + } + return osMemoryPoolFree(ptr->mp_id, mail); +} + +#endif // Mail Queue + + +#endif // osCMSIS diff --git a/FW/Drivers/CMSIS/docs/General/html/LICENSE.txt b/FW/Drivers/CMSIS/docs/General/html/LICENSE.txt new file mode 100644 index 0000000..8dada3e --- /dev/null +++ b/FW/Drivers/CMSIS/docs/General/html/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4027 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) || defined(STM32MP2) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32C0) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h new file mode 100644 index 0000000..ef50a4a --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -0,0 +1,1185 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_H +#define STM32H7xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_conf.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ +/** @defgroup REV_ID device revision ID + * @{ + */ +#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ +#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ +#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ +#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ + + +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) + + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) + +/** + * @} + */ + +#if !defined(SYSCFG_PMCR_BOOSTEN) +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + +/** + * @} + */ +#endif /* ! SYSCFG_PMCR_BOOSTEN */ + + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) || defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +/** @defgroup SYSCFG_Adc2_Alternate_Connection SYSCFG ADC2 Alternate Connection + * @{ + */ + +/** @brief Adc2 Alternate Connection on Vinp[16] and Vinp[17] + */ +#define SYSCFG_ADC2_ROUT0_DAC1_1 ((uint32_t)0x00000000) /*!< DAC1_out1 connected to ADC2 VINP[16] */ +#define SYSCFG_ADC2_ROUT0_VBAT4 SYSCFG_ADC2ALT_ADC2_ROUT0 /*!< VBAT/4 connected to ADC2 VINP[16] */ +#define SYSCFG_ADC2_ROUT1_DAC1_2 ((uint32_t)0x00000000) /*!< DAC1_out2 connected to ADC2 VINP[17] */ +#define SYSCFG_ADC2_ROUT1_VREFINT SYSCFG_ADC2ALT_ADC2_ROUT1 /*!< VREFINT connected to ADC2 VINP[17] */ + +#define IS_SYSCFG_ADC2ALT_ROUT0(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT0_DAC1_1) || \ + ((__VALUE__) == SYSCFG_ADC2_ROUT0_VBAT4)) +#define IS_SYSCFG_ADC2ALT_ROUT1(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT1_DAC1_2) || \ + ((__VALUE__) == SYSCFG_ADC2_ROUT1_VREFINT)) + +/** + * @} + */ +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0 || SYSCFG_ADC2ALT_ADC2_ROUT1*/ + + +/** @defgroup SYSCFG_Ethernet_Config Ethernet Config + * @{ + */ +#define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */ +#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */ + +#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \ + ((CONFIG) == SYSCFG_ETH_RMII)) + +/** + * @} + */ + + +/** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config + * @{ + */ +#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */ +#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */ +#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */ +#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */ + + + + +#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */ +#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */ +#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */ +#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/ +#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */ +#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */ +#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */ +#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */ + +/** + * @} + */ + +#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \ + (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \ + (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \ + (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3)) + + +#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \ + (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \ + (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE)) + + +/** @defgroup SYSCFG_Boot_Config Boot Config + * @{ + */ +#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */ +#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */ + +#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \ + ((REGISTER) == SYSCFG_BOOT_ADDR1)) + +#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE) + +/** + * @} + */ + + +/** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config + * @{ + */ +#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ +#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */ + +#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \ + ((SELECT) == SYSCFG_REGISTER_CODE)) + +#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup EXTI_Event_Input_Config Event Input Config + * @{ + */ + +#define EXTI_MODE_IT ((uint32_t)0x00010000) +#define EXTI_MODE_EVT ((uint32_t)0x00020000) +#define EXTI_RISING_EDGE ((uint32_t)0x00100000) +#define EXTI_FALLING_EDGE ((uint32_t)0x00200000) + +#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE)) +#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT)) + +#define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */ +#define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */ +#define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */ +#define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */ +#define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */ +#define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */ +#define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */ +#define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */ +#define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */ +#define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */ +#define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */ +#define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */ +#define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */ +#define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */ +#define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */ +#define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */ +#define EXTI_LINE16 ((uint32_t)0x10) +#define EXTI_LINE17 ((uint32_t)0x11) +#define EXTI_LINE18 ((uint32_t)0x12) +#define EXTI_LINE19 ((uint32_t)0x13) +#define EXTI_LINE20 ((uint32_t)0x14) +#define EXTI_LINE21 ((uint32_t)0x15) +#define EXTI_LINE22 ((uint32_t)0x16) +#define EXTI_LINE23 ((uint32_t)0x17) +#define EXTI_LINE24 ((uint32_t)0x18) +#define EXTI_LINE25 ((uint32_t)0x19) +#define EXTI_LINE26 ((uint32_t)0x1A) +#define EXTI_LINE27 ((uint32_t)0x1B) +#define EXTI_LINE28 ((uint32_t)0x1C) +#define EXTI_LINE29 ((uint32_t)0x1D) +#define EXTI_LINE30 ((uint32_t)0x1E) +#define EXTI_LINE31 ((uint32_t)0x1F) +#define EXTI_LINE32 ((uint32_t)0x20) +#define EXTI_LINE33 ((uint32_t)0x21) +#define EXTI_LINE34 ((uint32_t)0x22) +#define EXTI_LINE35 ((uint32_t)0x23) +#define EXTI_LINE36 ((uint32_t)0x24) +#define EXTI_LINE37 ((uint32_t)0x25) +#define EXTI_LINE38 ((uint32_t)0x26) +#define EXTI_LINE39 ((uint32_t)0x27) + +#define EXTI_LINE40 ((uint32_t)0x28) +#define EXTI_LINE41 ((uint32_t)0x29) +#define EXTI_LINE42 ((uint32_t)0x2A) +#define EXTI_LINE43 ((uint32_t)0x2B) +#define EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */ +/* EXTI_LINE45 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE46 ((uint32_t)0x2E) +#else +/* EXTI_LINE46 Reserved */ +#endif /* DUAL_CORE */ +#define EXTI_LINE47 ((uint32_t)0x2F) +#define EXTI_LINE48 ((uint32_t)0x30) +#define EXTI_LINE49 ((uint32_t)0x31) +#define EXTI_LINE50 ((uint32_t)0x32) +#define EXTI_LINE51 ((uint32_t)0x33) +#define EXTI_LINE52 ((uint32_t)0x34) +#define EXTI_LINE53 ((uint32_t)0x35) +#define EXTI_LINE54 ((uint32_t)0x36) +#define EXTI_LINE55 ((uint32_t)0x37) +#define EXTI_LINE56 ((uint32_t)0x38) +#define EXTI_LINE57 ((uint32_t)0x39) +#define EXTI_LINE58 ((uint32_t)0x3A) +#define EXTI_LINE59 ((uint32_t)0x3B) +#define EXTI_LINE60 ((uint32_t)0x3C) +#define EXTI_LINE61 ((uint32_t)0x3D) +#define EXTI_LINE62 ((uint32_t)0x3E) +#define EXTI_LINE63 ((uint32_t)0x3F) +#define EXTI_LINE64 ((uint32_t)0x40) +#define EXTI_LINE65 ((uint32_t)0x41) +#define EXTI_LINE66 ((uint32_t)0x42) +#define EXTI_LINE67 ((uint32_t)0x43) +#define EXTI_LINE68 ((uint32_t)0x44) +#define EXTI_LINE69 ((uint32_t)0x45) +#define EXTI_LINE70 ((uint32_t)0x46) +#define EXTI_LINE71 ((uint32_t)0x47) +#define EXTI_LINE72 ((uint32_t)0x48) +#define EXTI_LINE73 ((uint32_t)0x49) +#define EXTI_LINE74 ((uint32_t)0x4A) +#define EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */ +#define EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */ +#if defined(DUAL_CORE) +#define EXTI_LINE77 ((uint32_t)0x4D) +#define EXTI_LINE78 ((uint32_t)0x4E) +#define EXTI_LINE79 ((uint32_t)0x4F) +#define EXTI_LINE80 ((uint32_t)0x50) +#else +/* EXTI_LINE77 Reserved */ +/* EXTI_LINE78 Reserved */ +/* EXTI_LINE79 Reserved */ +/* EXTI_LINE80 Reserved */ +#endif /* DUAL_CORE */ +/* EXTI_LINE81 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE82 ((uint32_t)0x52) +#else +/* EXTI_LINE82 Reserved */ +#endif /* DUAL_CORE */ +/* EXTI_LINE83 Reserved */ +#if defined(DUAL_CORE) +#define EXTI_LINE84 ((uint32_t)0x54) +#else +/* EXTI_LINE84 Reserved */ +#endif /* DUAL_CORE */ +#define EXTI_LINE85 ((uint32_t)0x55) +#define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */ +#define EXTI_LINE87 ((uint32_t)0x57) +#define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */ +#define EXTI_LINE89 ((uint32_t)0x59) /* Not available in all family lines */ +#define EXTI_LINE90 ((uint32_t)0x5A) /* Not available in all family lines */ +#define EXTI_LINE91 ((uint32_t)0x5B) /* Not available in all family lines */ + +#if defined(DUAL_CORE) +#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ + ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84) || \ + ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) +#else +#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ + ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) +#endif /* DUAL_CORE */ + +#if defined(DUAL_CORE) +#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ + ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE78) || \ + ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82)) +#else +#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ + ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ + ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) +#else +#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ + ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ + ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ + ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ + ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ + ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ + ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ + ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ + ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ + ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ + ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ + ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ + ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ + ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ + ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ + ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ + ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ + ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ + ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ + ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ + ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ + ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ + ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ + ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ + ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ + ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ + ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \ + ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \ + ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53)) +#elif (POWER_DOMAINS_NUMBER == 3U) +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ + ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE88)) +#else +#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ + ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ + ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ + ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ + ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ + ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ + ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ + ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ + ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ + ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ + ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ + ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ + ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ + ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88)) +#endif /*DUAL_CORE*/ + + +#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/ +#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/ +#if defined (LPTIM4) +#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/ +#else +#define LPTIM2_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM2 out selected as D3 domain pendclear source*/ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/ +#else +#define LPTIM3_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM3 out selected as D3 domain pendclear source*/ +#endif /* LPTIM5 */ +#if defined (LPTIM4) && defined (LPTIM5) +#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ + ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR)) +#else +#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ + ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR)) +#endif /* LPTIM4 LPTIM5 */ +/** + * @} + */ + + +/** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config + * @{ + */ +#define FMC_SWAPBMAP_DISABLE (0x00000000U) +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0 +#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1 + +#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \ + ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \ + ((__MODE__) == FMC_SWAPBMAP_SDRAMB2)) +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ +#if defined(DUAL_CORE) +/** @defgroup ART_Exported_Macros ART Exported Macros + * @{ + */ + +/** @brief ART Enable Macro. + * Enable the Cortex-M4 ART cache. + */ +#define __HAL_ART_ENABLE() SET_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Disable Macro. + * Disable the Cortex-M4 ART cache. + */ +#define __HAL_ART_DISABLE() CLEAR_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Cache BaseAddress Config. + * Configure the Cortex-M4 ART cache Base Address. + */ +#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL)) + +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief SYSCFG Break AXIRAM double ECC lock. + * Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML) + +/** @brief SYSCFG Break ITCM double ECC lock. + * Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML) + +/** @brief SYSCFG Break DTCM double ECC lock. + * Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML) + +/** @brief SYSCFG Break SRAM1 double ECC lock. + * Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L) + +/** @brief SYSCFG Break SRAM2 double ECC lock. + * Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L) + +/** @brief SYSCFG Break SRAM3 double ECC lock. + * Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L) + +/** @brief SYSCFG Break SRAM4 double ECC lock. + * Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L) + +/** @brief SYSCFG Break Backup SRAM double ECC lock. + * Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML) + +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L) + +/** @brief SYSCFG Break FLASH double ECC lock. + * Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL) + +#if defined(DUAL_CORE) +/** @brief SYSCFG Break Cortex-M4 Lockup lock. + * Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + This feature is available on STM32H7 rev.B and above. + */ +#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L) +#endif /* DUAL_CORE */ + +#if !defined(SYSCFG_PMCR_BOOSTEN) +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of : + * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 + * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 + * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 + * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ + }while(0) + +#endif /* !SYSCFG_PMCR_BOOSTEN */ +/** + * @} + */ + +/** @defgroup DBG_Exported_Macros DBG Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1)) + +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14)) +#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1)) +#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1)) +#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2)) +#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_FREEZE_I2C5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) +#define __HAL_DBGMCU_FREEZE_TIM23() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_FREEZE_TIM24() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ + +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8)) +#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15)) +#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16)) +#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17)) +#define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM)) + +#define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4)) +#define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2)) +#define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3)) +#define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4)) +#define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC)) +#define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1)) + + +#define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1)) + +#define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2)) +#define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3)) +#define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4)) +#define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5)) +#define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6)) +#define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7)) +#define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12)) +#define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13)) +#define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14)) +#define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1)) +#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1)) +#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2)) +#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3)) +#if defined(I2C5) +#define __HAL_DBGMCU_UnFreeze_I2C5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C5)) +#endif /*I2C5*/ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN)) +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) +#define __HAL_DBGMCU_UnFreeze_TIM23() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM23)) +#endif /*TIM23*/ +#if defined(TIM24) +#define __HAL_DBGMCU_UnFreeze_TIM24() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM24)) +#endif /*TIM24*/ + +#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1)) +#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8)) +#define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15)) +#define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16)) +#define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17)) +#define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM)) + +#define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4)) +#define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2)) +#define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3)) +#define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4)) +#define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5)) +#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC)) +#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1)) + + +#if defined(DUAL_CORE) +#define __HAL_DBGMCU_FREEZE2_IWDG2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG2)) +#define __HAL_DBGMCU_FREEZE2_WWDG2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2)) + +#define __HAL_DBGMCU_UnFreeze2_IWDG2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2)) +#define __HAL_DBGMCU_UnFreeze2_WWDG2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2)) + + +#define __HAL_DBGMCU_FREEZE2_WWDG1() (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1)) + +#define __HAL_DBGMCU_FREEZE2_TIM2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2)) +#define __HAL_DBGMCU_FREEZE2_TIM3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3)) +#define __HAL_DBGMCU_FREEZE2_TIM4() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4)) +#define __HAL_DBGMCU_FREEZE2_TIM5() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5)) +#define __HAL_DBGMCU_FREEZE2_TIM6() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6)) +#define __HAL_DBGMCU_FREEZE2_TIM7() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7)) +#define __HAL_DBGMCU_FREEZE2_TIM12() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12)) +#define __HAL_DBGMCU_FREEZE2_TIM13() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13)) +#define __HAL_DBGMCU_FREEZE2_TIM14() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14)) +#define __HAL_DBGMCU_FREEZE2_LPTIM1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1)) +#define __HAL_DBGMCU_FREEZE2_I2C1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1)) +#define __HAL_DBGMCU_FREEZE2_I2C2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2)) +#define __HAL_DBGMCU_FREEZE2_I2C3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3)) +#define __HAL_DBGMCU_FREEZE2_FDCAN() (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN)) + + +#define __HAL_DBGMCU_FREEZE2_TIM1() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1)) +#define __HAL_DBGMCU_FREEZE2_TIM8() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8)) +#define __HAL_DBGMCU_FREEZE2_TIM15() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15)) +#define __HAL_DBGMCU_FREEZE2_TIM16() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16)) +#define __HAL_DBGMCU_FREEZE2_TIM17() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17)) +#define __HAL_DBGMCU_FREEZE2_HRTIM() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM)) + +#define __HAL_DBGMCU_FREEZE2_I2C4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4)) +#define __HAL_DBGMCU_FREEZE2_LPTIM2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2)) +#define __HAL_DBGMCU_FREEZE2_LPTIM3() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3)) +#define __HAL_DBGMCU_FREEZE2_LPTIM4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4)) +#define __HAL_DBGMCU_FREEZE2_LPTIM5() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5)) +#define __HAL_DBGMCU_FREEZE2_RTC() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC)) +#define __HAL_DBGMCU_FREEZE2_IWDG1() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1)) + +#define __HAL_DBGMCU_UnFreeze2_WWDG1() (DBGMCU->APB3FZ2 &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1)) + +#define __HAL_DBGMCU_UnFreeze2_TIM2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2)) +#define __HAL_DBGMCU_UnFreeze2_TIM3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3)) +#define __HAL_DBGMCU_UnFreeze2_TIM4() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4)) +#define __HAL_DBGMCU_UnFreeze2_TIM5() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5)) +#define __HAL_DBGMCU_UnFreeze2_TIM6() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6)) +#define __HAL_DBGMCU_UnFreeze2_TIM7() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7)) +#define __HAL_DBGMCU_UnFreeze2_TIM12() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12)) +#define __HAL_DBGMCU_UnFreeze2_TIM13() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13)) +#define __HAL_DBGMCU_UnFreeze2_TIM14() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1)) +#define __HAL_DBGMCU_UnFreeze2_I2C1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1)) +#define __HAL_DBGMCU_UnFreeze2_I2C2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2)) +#define __HAL_DBGMCU_UnFreeze2_I2C3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3)) +#define __HAL_DBGMCU_UnFreeze2_FDCAN() (DBGMCU->APB1HFZ2 &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN)) + + +#define __HAL_DBGMCU_UnFreeze2_TIM1() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM1)) +#define __HAL_DBGMCU_UnFreeze2_TIM8() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM8)) +#define __HAL_DBGMCU_UnFreeze2_TIM15() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM15)) +#define __HAL_DBGMCU_UnFreeze2_TIM16() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM16)) +#define __HAL_DBGMCU_UnFreeze2_TIM17() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM17)) +#define __HAL_DBGMCU_UnFreeze2_HRTIM() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM)) + +#define __HAL_DBGMCU_UnFreeze2_I2C4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_I2C4)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM3() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4)) +#define __HAL_DBGMCU_UnFreeze2_LPTIM5() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5)) +#define __HAL_DBGMCU_UnFreeze2_RTC() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_RTC)) +#define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1)) + +#endif /*DUAL_CORE*/ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +/** @defgroup HAL_Group1 Initialization and de-initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); + +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @defgroup HAL_Group2 HAL Control functions + * + */ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +#if defined(SYSCFG_PMCR_EPIS_SEL) +void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); +#endif /* SYSCFG_PMCR_EPIS_SEL */ +void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); +#if defined(SYSCFG_PMCR_BOOSTEN) +void HAL_SYSCFG_EnableBOOST(void); +void HAL_SYSCFG_DisableBOOST(void); +#endif /* SYSCFG_PMCR_BOOSTEN */ + +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) +void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/ + +#if defined(DUAL_CORE) +void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); +void HAL_SYSCFG_EnableCM7BOOT(void); +void HAL_SYSCFG_DisableCM7BOOT(void); +void HAL_SYSCFG_EnableCM4BOOT(void); +void HAL_SYSCFG_DisableCM4BOOT(void); +#endif /*DUAL_CORE*/ +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +void HAL_SYSCFG_EnableIOSpeedOptimize(void); +void HAL_SYSCFG_DisableIOSpeedOptimize(void); +void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode); +void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#if defined(SYSCFG_CCCR_NCC_MMC) +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); +#endif /* SYSCFG_CCCR_NCC_MMC */ +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +#if defined(DUAL_CORE) +void HAL_EnableDomain2DBGSleepMode(void); +void HAL_DisableDomain2DBGSleepMode(void); +void HAL_EnableDomain2DBGStopMode(void); +void HAL_DisableDomain2DBGStopMode(void); +void HAL_EnableDomain2DBGStandbyMode(void); +void HAL_DisableDomain2DBGStandbyMode(void); +#endif /*DUAL_CORE*/ +#if defined(DBGMCU_CR_DBG_STOPD3) +void HAL_EnableDomain3DBGStopMode(void); +void HAL_DisableDomain3DBGStopMode(void); +#endif /*DBGMCU_CR_DBG_STOPD3*/ +#if defined(DBGMCU_CR_DBG_STANDBYD3) +void HAL_EnableDomain3DBGStandbyMode(void); +void HAL_DisableDomain3DBGStandbyMode(void); +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ +void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ); +void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +#if defined(DUAL_CORE) +void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line); +#endif /*DUAL_CORE*/ +void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line); +void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); +#if defined(DUAL_CORE) +void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); +#endif /*DUAL_CORE*/ +void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc); +void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig); +uint32_t HAL_GetFMCMemorySwappingConfig(void); +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1); +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_H */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h new file mode 100644 index 0000000..2645c28 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h @@ -0,0 +1,459 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_CORTEX_H +#define STM32H7xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +#if !defined(CORE_CM4) +#define MPU_REGION_NUMBER8 ((uint8_t)0x08) +#define MPU_REGION_NUMBER9 ((uint8_t)0x09) +#define MPU_REGION_NUMBER10 ((uint8_t)0x0A) +#define MPU_REGION_NUMBER11 ((uint8_t)0x0B) +#define MPU_REGION_NUMBER12 ((uint8_t)0x0C) +#define MPU_REGION_NUMBER13 ((uint8_t)0x0D) +#define MPU_REGION_NUMBER14 ((uint8_t)0x0E) +#define MPU_REGION_NUMBER15 ((uint8_t)0x0F) +#endif /* !defined(CORE_CM4) */ + +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + + + +/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier + * @{ + */ +#define CM7_CPUID ((uint32_t)0x00000003) + +#if defined(DUAL_CORE) +#define CM4_CPUID ((uint32_t)0x00000001) +#endif /*DUAL_CORE*/ +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +uint32_t HAL_GetCurrentCPUID(void); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) + +#define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#if !defined(CORE_CM4) +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7) || \ + ((NUMBER) == MPU_REGION_NUMBER8) || \ + ((NUMBER) == MPU_REGION_NUMBER9) || \ + ((NUMBER) == MPU_REGION_NUMBER10) || \ + ((NUMBER) == MPU_REGION_NUMBER11) || \ + ((NUMBER) == MPU_REGION_NUMBER12) || \ + ((NUMBER) == MPU_REGION_NUMBER13) || \ + ((NUMBER) == MPU_REGION_NUMBER14) || \ + ((NUMBER) == MPU_REGION_NUMBER15)) +#else +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) +#endif /* !defined(CORE_CM4) */ + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_CORTEX_H */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h new file mode 100644 index 0000000..69101d6 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h @@ -0,0 +1,220 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DEF +#define STM32H7xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +#define UNUSED(x) ((void)(x)) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__: specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) + #error " USE_RTOS should be 0 in the current HAL release " +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5 */ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__CC_ARM) /* ARM Compiler */ + #define ALIGN_32BYTES(buf) __align(32) buf +#endif + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DEF */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h new file mode 100644 index 0000000..82f6f21 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -0,0 +1,1333 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DMA_H +#define STM32H7xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified stream. + This parameter can be a value of @ref DMA_Request_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Transfer complete level structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + void *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */ +#define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */ +#define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */ +#define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */ + +/** + * @} + */ + +/** @defgroup DMA_Request_selection DMA Request selection + * @brief DMA Request selection + * @{ + */ +/* DMAMUX1 requests */ +#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ + +#define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ +#define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ +#define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ +#define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ +#define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ + +#define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */ +#define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */ + +#define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ +#define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ +#define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ + +#define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ + +#define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ +#define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ + +#define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ +#define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ +#define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ +#define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ + +#define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ + +#define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ + +#define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ +#define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ +#define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ +#define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ +#define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ +#define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ + +#define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ +#define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ +#define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ +#define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ +#define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ +#define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ +#define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ + +#define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ +#define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ +#define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ +#define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ +#define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ +#define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ + +#define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ +#define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ + +#define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ +#define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ +#define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ +#define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ + +#define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ +#define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ + +#define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ +#define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ + +#define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ +#define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ + +#define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ + +#if defined (PSSI) +#define DMA_REQUEST_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ +#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */ +#else +#define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif /* PSSI */ + +#define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ +#define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ + +#define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ + +#define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ +#define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ +#define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ +#define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ + +#define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ +#define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ +#define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ +#define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ + +#define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ +#define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ + +#if defined(SAI2) +#define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ +#define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ +#endif /* SAI2 */ + +#define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ +#define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ + +#define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/ +#define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/ + +#if defined(HRTIM1) +#define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ +#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6*/ +#endif /* HRTIM1 */ + +#define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ +#define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */ +#define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */ +#define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */ + +#define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ +#define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ +#define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ + +#define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ + +#define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ + +#if defined(SAI3) +#define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ +#define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif /* SAI3 */ + +#if defined(ADC3) +#define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */ +#endif /* ADC3 */ + +#if defined(UART9) +#define DMA_REQUEST_UART9_RX 116U /*!< DMAMUX1 UART9 request */ +#define DMA_REQUEST_UART9_TX 117U /*!< DMAMUX1 UART9 request */ +#endif /* UART9 */ + +#if defined(USART10) +#define DMA_REQUEST_USART10_RX 118U /*!< DMAMUX1 USART10 request */ +#define DMA_REQUEST_USART10_TX 119U /*!< DMAMUX1 USART10 request */ +#endif /* USART10 */ + +#if defined(FMAC) +#define DMA_REQUEST_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ +#define DMA_REQUEST_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ +#endif /* FMAC */ + +#if defined(CORDIC) +#define DMA_REQUEST_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ +#define DMA_REQUEST_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ +#endif /* CORDIC */ + +#if defined(I2C5) +#define DMA_REQUEST_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ +#define DMA_REQUEST_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ +#endif /* I2C5 */ + +#if defined(TIM23) +#define DMA_REQUEST_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ +#define DMA_REQUEST_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ +#define DMA_REQUEST_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ +#define DMA_REQUEST_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ +#define DMA_REQUEST_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ +#define DMA_REQUEST_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ +#endif /* TIM23 */ + +#if defined(TIM24) +#define DMA_REQUEST_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ +#define DMA_REQUEST_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ +#define DMA_REQUEST_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ +#define DMA_REQUEST_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ +#define DMA_REQUEST_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ +#define DMA_REQUEST_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ +#endif /* TIM24 */ + +/* DMAMUX2 requests */ +#define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ +#define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ +#define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ +#define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ +#define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ +#define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ +#define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ +#define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ +#define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ +#define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ +#define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ +#define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ +#define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ +#define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ +#define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ +#if defined(SAI4) +#define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ +#define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ +#endif /* SAI4 */ +#if defined(ADC3) +#define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */ +#endif /* ADC3 */ +#if defined(DAC2) +#define BDMA_REQUEST_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ +#endif /* DAC2 */ +#if defined(DFSDM2_Channel0) +#define BDMA_REQUEST_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 request */ +#endif /* DFSDM1_Channel0 */ + +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ +#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ +#define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) /*!< Double buffer mode with first target memory M0 */ +#define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U) +#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) +#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) +#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U) +#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) +#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) +#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) +#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) +#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) +#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) +#define DMA_IT_FE ((uint32_t)0x00000080U) +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U) +#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U) +#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U) +#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U) +#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U) +#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U) +#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U) +#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U) +#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U) +#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U) +#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U) +#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U) +#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U) +#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U) +#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U) +#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U) +#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U) +#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U) +#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U) +#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U) +/** + * @} + */ + +/** @defgroup BDMA_flag_definitions BDMA flag definitions + * @brief BDMA flag definitions + * @{ + */ +#define BDMA_FLAG_GL0 ((uint32_t)0x00000001) +#define BDMA_FLAG_TC0 ((uint32_t)0x00000002) +#define BDMA_FLAG_HT0 ((uint32_t)0x00000004) +#define BDMA_FLAG_TE0 ((uint32_t)0x00000008) +#define BDMA_FLAG_GL1 ((uint32_t)0x00000010) +#define BDMA_FLAG_TC1 ((uint32_t)0x00000020) +#define BDMA_FLAG_HT1 ((uint32_t)0x00000040) +#define BDMA_FLAG_TE1 ((uint32_t)0x00000080) +#define BDMA_FLAG_GL2 ((uint32_t)0x00000100) +#define BDMA_FLAG_TC2 ((uint32_t)0x00000200) +#define BDMA_FLAG_HT2 ((uint32_t)0x00000400) +#define BDMA_FLAG_TE2 ((uint32_t)0x00000800) +#define BDMA_FLAG_GL3 ((uint32_t)0x00001000) +#define BDMA_FLAG_TC3 ((uint32_t)0x00002000) +#define BDMA_FLAG_HT3 ((uint32_t)0x00004000) +#define BDMA_FLAG_TE3 ((uint32_t)0x00008000) +#define BDMA_FLAG_GL4 ((uint32_t)0x00010000) +#define BDMA_FLAG_TC4 ((uint32_t)0x00020000) +#define BDMA_FLAG_HT4 ((uint32_t)0x00040000) +#define BDMA_FLAG_TE4 ((uint32_t)0x00080000) +#define BDMA_FLAG_GL5 ((uint32_t)0x00100000) +#define BDMA_FLAG_TC5 ((uint32_t)0x00200000) +#define BDMA_FLAG_HT5 ((uint32_t)0x00400000) +#define BDMA_FLAG_TE5 ((uint32_t)0x00800000) +#define BDMA_FLAG_GL6 ((uint32_t)0x01000000) +#define BDMA_FLAG_TC6 ((uint32_t)0x02000000) +#define BDMA_FLAG_HT6 ((uint32_t)0x04000000) +#define BDMA_FLAG_TE6 ((uint32_t)0x08000000) +#define BDMA_FLAG_GL7 ((uint32_t)0x10000000) +#define BDMA_FLAG_TC7 ((uint32_t)0x20000000) +#define BDMA_FLAG_HT7 ((uint32_t)0x40000000) +#define BDMA_FLAG_TE7 ((uint32_t)0x80000000) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__: specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__: DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ +((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN)) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__: DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ +((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN)) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer complete flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__: DMA handle + * @retval The specified half transfer complete flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__: DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\ + (uint32_t)0x00000000) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__: DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\ + (uint32_t)0x00000000) + +/** + * @brief Returns the current BDMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(BDMA1) +#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\ + (uint32_t)0x00000000) +#else +#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\ + (uint32_t)0x00000000) +#endif /* BDMA1 */ + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#if defined(BDMA1) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#else +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) +#endif /* BDMA1 */ + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__: DMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#if defined(BDMA1) +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#else +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) +#endif /* BDMA1 */ + +#define DMA_TO_BDMA_IT(__DMA_IT__) \ +((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ + (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\ + (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\ + (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\ + ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\ + ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\ + ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\ + (uint32_t)0x00000000) + + +#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ +(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__))) + +#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ + (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__))) + +#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\ + (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__)))) + + +#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__)))) + +#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or not. + * @param __HANDLE__: DMA handle + * @param __INTERRUPT__: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\ + (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__)))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__: DMA handle + * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\ + (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__))) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__: DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \ + (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\ + (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR)) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32h7xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Types DMA Private Types + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ + +#if defined(TIM24) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG)) +#elif defined(ADC3) +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3)) +#else +#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX)) +#endif /* TIM24 */ + +#if defined(ADC3) +#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3)) +#else +#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0)) +#endif /* ADC3 */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL) || \ + ((MODE) == DMA_DOUBLE_BUFFER_M0) || \ + ((MODE) == DMA_DOUBLE_BUFFER_M1)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DMA_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h new file mode 100644 index 0000000..cde5755 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_DMA_EX_H +#define STM32H7xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ + +}HAL_DMA_MemoryTypeDef; + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE*/ + + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event. + This parameters can be in the range 1 to 32 */ + +}HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event. + This parameters can be in the range 1 to 32 */ + +}HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMAEx_Exported_Constants DMA Exported Constants + * @brief DMAEx Exported constants + * @{ + */ + +/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection + * @brief DMAEx MUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ + +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */ +#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */ +#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */ +#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */ +#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */ +#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */ +#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */ +#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */ +#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */ +#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */ +#define HAL_DMAMUX2_SYNC_EXTI0 14U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */ +#define HAL_DMAMUX2_SYNC_EXTI2 15U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */ + +/** + * @} + */ + +/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection + * @brief DMAEx MUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + + +/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection + * @brief DMAEx MUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ + +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */ +#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */ +#if defined(LPTIM4) +#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */ +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */ +#endif /* LPTIM5 */ +#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */ +#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */ +#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */ +#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */ +#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */ +#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */ +#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */ +#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */ +#if defined(ADC3) +#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */ +#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */ +#endif /* ADC3 */ +#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */ +#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */ + + +/** + * @} + */ + +/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection + * @brief DMAEx MUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO) +#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO) +#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_DMA_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h new file mode 100644 index 0000000..91d7d95 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h @@ -0,0 +1,537 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_EXTI_H +#define STM32H7xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ + + uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD + domain. This parameter can be a value of @ref + EXTI_PendClear_Source */ + +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x00U) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x01U) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x02U) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x03U) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x04U) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x05U) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x06U) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x07U) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x08U) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x09U) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0AU) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0BU) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0CU) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0DU) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0EU) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x0FU) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U) +#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x13U) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x14U) +#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x15U) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL | 0x19U) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) +#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x02U) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x03U) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) +#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) +#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) +#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) +#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) +#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x09U) +#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) +#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) +#if !defined(USB2_OTG_FS) +#define EXTI_LINE_44 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0CU) +#else +#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#endif /* USB2_OTG_FS */ +#define EXTI_LINE_45 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0DU) +#if defined(DSI) +#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU) +#else +#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x0EU) +#endif /* DSI */ +#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU) +#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x10U) +#define EXTI_LINE_49 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x11U) +#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x12U) +#define EXTI_LINE_51 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x13U) +#if defined(LPTIM4) +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x14U) +#else +#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL | 0x15U) +#else +#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#endif /*LPTIM5*/ +#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U) +#if defined(EXTI_IMR2_IM57) +#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#else +#define EXTI_LINE_57 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x19U) +#endif /*EXTI_IMR2_IM57*/ +#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#if defined(EXTI_IMR2_IM59) +#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#else +#define EXTI_LINE_59 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE | 0x1BU) +#endif /*EXTI_IMR2_IM59*/ +#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU) +#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU) +#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU) +#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU) +#define EXTI_LINE_64 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U) +#define EXTI_LINE_65 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U) +#define EXTI_LINE_66 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U) +#define EXTI_LINE_67 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U) +#define EXTI_LINE_68 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U) +#define EXTI_LINE_69 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U) +#define EXTI_LINE_70 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U) +#define EXTI_LINE_71 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U) +#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U) +#define EXTI_LINE_73 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U) +#define EXTI_LINE_74 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU) +#if defined(ADC3) +#define EXTI_LINE_75 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU) +#else +#define EXTI_LINE_75 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0BU) +#endif /* ADC3 */ +#if defined(SAI4) +#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU) +#else +#define EXTI_LINE_76 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE | 0x0CU) +#endif /* SAI4 */ +#if defined (DUAL_CORE) +#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU) +#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU) +#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU) +#define EXTI_LINE_80 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U) +#else +#define EXTI_LINE_77 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU) +#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU) +#define EXTI_LINE_79 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU) +#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U) +#if defined (DUAL_CORE) +#define EXTI_LINE_82 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U) +#else +#define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U) +#if defined (DUAL_CORE) +#define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U) +#else +#define EXTI_LINE_84 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U) +#endif /* DUAL_CORE */ +#define EXTI_LINE_85 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U) +#if defined(ETH) +#define EXTI_LINE_86 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U) +#else +#define EXTI_LINE_86 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U) +#endif /* ETH */ +#define EXTI_LINE_87 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U) +#if defined(DTS) +#define EXTI_LINE_88 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U) +#endif /* DTS */ +#if defined(EXTI_IMR3_IM89) +#define EXTI_LINE_89 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x19U) +#endif /*EXTI_IMR3_IM89*/ +#if defined(EXTI_IMR3_IM90) +#define EXTI_LINE_90 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU) +#endif /*EXTI_IMR3_IM90*/ +#if defined(I2C5) +#define EXTI_LINE_91 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU) +#endif /*I2C5*/ + +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +#if defined(DUAL_CORE) +#define EXTI_MODE_CORE1_INTERRUPT EXTI_MODE_INTERRUPT +#define EXTI_MODE_CORE1_EVENT EXTI_MODE_EVENT +#define EXTI_MODE_CORE2_INTERRUPT 0x00000010U +#define EXTI_MODE_CORE2_EVENT 0x00000020U +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOD 0x00000003U +#define EXTI_GPIOE 0x00000004U +#define EXTI_GPIOF 0x00000005U +#define EXTI_GPIOG 0x00000006U +#define EXTI_GPIOH 0x00000007U +#if defined(GPIOI) +#define EXTI_GPIOI 0x00000008U +#endif /*GPIOI*/ +#define EXTI_GPIOJ 0x00000009U +#define EXTI_GPIOK 0x0000000AU + +/** + * @} + */ + +/** @defgroup EXTI_PendClear_Source EXTI PendClear Source + * @brief + * @{ + */ +#define EXTI_D3_PENDCLR_SRC_NONE 0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero */ +#define EXTI_D3_PENDCLR_SRC_DMACH6 0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#define EXTI_D3_PENDCLR_SRC_DMACH7 0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/ +#if defined (LPTIM4) +#define EXTI_D3_PENDCLR_SRC_LPTIM4 0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM2 0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif +#if defined (LPTIM5) +#define EXTI_D3_PENDCLR_SRC_LPTIM5 0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#else +#define EXTI_D3_PENDCLR_SRC_LPTIM3 0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1 */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24U +#define EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Event presence definition + */ +#define EXTI_EVENT_PRESENCE_SHIFT 28U +#define EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT) +#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16U +#define EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) +#define EXTI_REG3 (0x02UL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) +#define EXTI_PIN_MASK 0x0000001FUL + +/** + * @brief EXTI Target and bit usage + */ +#define EXTI_TARGET_SHIFT 20U +#define EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT) +#if defined (DUAL_CORE) +#define EXTI_TARGET_MSK_CPU2 (0x04UL << EXTI_TARGET_SHIFT) +#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2) +#define EXTI_TARGET_MSK_ALL_CPU (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2) +#else +#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1) +#define EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1 +#endif /* DUAL_CORE */ +#define EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#if defined (DUAL_CORE) +#define EXTI_MODE_MASK (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT) +#else +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) +#endif /* DUAL_CORE */ + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if (STM32H7_DEV_ID == 0x483UL) +#define EXTI_LINE_NB 92UL +#elif (STM32H7_DEV_ID == 0x480UL) +#define EXTI_LINE_NB 89UL +#else +#define EXTI_LINE_NB 88UL +#endif /* EXTI_LINE_91 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_PROPERTY(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) +#if defined (DUAL_CORE) +#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)) +#else +#define IS_EXTI_TARGET(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \ + (((__EXTI_LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)) +#endif + +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK |\ + EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \ + IS_EXTI_PROPERTY(__EXTI_LINE__) && IS_EXTI_TARGET(__EXTI_LINE__) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL)))) + +#define IS_EXTI_MODE(__MODE__) (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)|| \ + ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00UL) + +#if defined(GPIOI) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#endif /*GPIOI*/ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16UL) +#if defined (LPTIM4) && defined (LPTIM5) +#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5)) +#else +#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \ + ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3)) +#endif /* LPTIM4 && LPTIM5 */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_EXTI_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h new file mode 100644 index 0000000..47f1fac --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h @@ -0,0 +1,2422 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_fdcan.h + * @author MCD Application Team + * @brief Header file of FDCAN HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FDCAN_H +#define STM32H7xx_HAL_FDCAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FDCAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Types FDCAN Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ + HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ + HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ + HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ +} HAL_FDCAN_StateTypeDef; + +/** + * @brief FDCAN Init structure definition + */ +typedef struct +{ + uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. + This parameter can be a value of @ref FDCAN_frame_format */ + + uint32_t Mode; /*!< Specifies the FDCAN mode. + This parameter can be a value of @ref FDCAN_operating_mode */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the nominal bit time quanta. + This parameter must be a number between 1 and 512 */ + + uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a bit to perform + resynchronization. + This parameter must be a number between 1 and 128 */ + + uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter must be a number between 2 and 256 */ + + uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter must be a number between 2 and 128 */ + + uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the data bit time quanta. + This parameter must be a number between 1 and 32 */ + + uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a data bit to + perform resynchronization. + This parameter must be a number between 1 and 16 */ + + uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. + This parameter must be a number between 1 and 32 */ + + uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. + This parameter must be a number between 1 and 16 */ + + uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address. + This parameter must be a number between 0 and 2560 */ + + uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. + This parameter must be a number between 0 and 128 */ + + uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. + This parameter must be a number between 0 and 64 */ + + uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements. + This parameter must be a number between 0 and 64 */ + + uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element. + This parameter can be a value of @ref FDCAN_data_field_size */ + + uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements. + This parameter must be a number between 0 and 64 */ + + uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element. + This parameter can be a value of @ref FDCAN_data_field_size */ + + uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements. + This parameter must be a number between 0 and 64 */ + + uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element. + This parameter can be a value of @ref FDCAN_data_field_size */ + + uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements. + This parameter must be a number between 0 and 32 */ + + uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers. + This parameter must be a number between 0 and 32 */ + + uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue. + This parameter must be a number between 0 and 32 */ + + uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. + This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ + + uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element. + This parameter can be a value of @ref FDCAN_data_field_size */ + +} FDCAN_InitTypeDef; + +/** + * @brief FDCAN clock calibration unit structure definition + */ +typedef struct +{ + uint32_t ClockCalibration; /*!< Enable or disable the clock calibration. + This parameter can be a value of @ref FDCAN_clock_calibration. */ + + uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration + is bypassed. + This parameter can be a value of @ref FDCAN_clock_divider */ + + uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The + actual configured number of periods is MinOscClkPeriods x 32. + This parameter must be a number between 0x00 and 0xFF */ + + uint32_t CalFieldLength; /*!< Specifies the calibration field length. + This parameter can be a value of @ref FDCAN_calibration_field_length */ + + uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time. + This parameter must be a number between 4 and 25 */ + + uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter. + If set to zero the counter is disabled. + This parameter must be a number between 0x0000 and 0xFFFF */ + +} FDCAN_ClkCalUnitTypeDef; + +/** + * @brief FDCAN filter structure definition + */ +typedef struct +{ + uint32_t IdType; /*!< Specifies the identifier type. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. + This parameter must be a number between: + - 0 and 127, if IdType is FDCAN_STANDARD_ID + - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterType; /*!< Specifies the filter type. + This parameter can be a value of @ref FDCAN_filter_type. + The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted + only when IdType is FDCAN_EXTENDED_ID. + This parameter is ignored if FilterConfig is set to + FDCAN_FILTER_TO_RXBUFFER */ + + uint32_t FilterConfig; /*!< Specifies the filter configuration. + This parameter can be a value of @ref FDCAN_filter_config */ + + uint32_t FilterID1; /*!< Specifies the filter identification 1. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t FilterID2; /*!< Specifies the filter identification 2. + This parameter is ignored if FilterConfig is set to + FDCAN_FILTER_TO_RXBUFFER. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the + matching message will be stored. + This parameter must be a number between 0 and 63. + This parameter is ignored if FilterConfig is different + from FDCAN_FILTER_TO_RXBUFFER */ + + uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for + calibration messages. + This parameter is ignored if FilterConfig is different + from FDCAN_FILTER_TO_RXBUFFER. + This parameter can be: + - 0 : ordinary message + - 1 : calibration message */ + +} FDCAN_FilterTypeDef; + +/** + * @brief FDCAN Tx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the message that will be + transmitted. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without + bit rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or + FD format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. + This parameter can be a value of @ref FDCAN_EFC */ + + uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO + element for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + +} FDCAN_TxHeaderTypeDef; + +/** + * @brief FDCAN Rx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type of the received message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t RxFrameType; /*!< Specifies the the received message frame type. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the received frame length. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + reception. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. + This parameter must be a number between: + - 0 and 127, if IdType is FDCAN_STANDARD_ID + - 0 and 63, if IdType is FDCAN_EXTENDED_ID + When the frame is a Non-Filter matching frame, this parameter + is unused. */ + + uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. + Acceptance of non-matching frames may be enabled via + HAL_FDCAN_ConfigGlobalFilter(). + This parameter takes 0 if the frame matched an Rx filter or + 1 if it did not match any Rx filter */ + +} FDCAN_RxHeaderTypeDef; + +/** + * @brief FDCAN Tx event FIFO structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the transmitted frame. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame + transmission. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element + for identification of Tx message status. + This parameter must be a number between 0 and 0xFF */ + + uint32_t EventType; /*!< Specifies the event type. + This parameter can be a value of @ref FDCAN_event_type */ + +} FDCAN_TxEventFifoTypeDef; + +/** + * @brief FDCAN High Priority Message Status structure definition + */ +typedef struct +{ + uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. + This parameter can be: + - 0 : Standard Filter List + - 1 : Extended Filter List */ + + uint32_t FilterIndex; /*!< Specifies the index of matching filter element. + This parameter can be a number between: + - 0 and 127, if FilterList is 0 (Standard) + - 0 and 63, if FilterList is 1 (Extended) */ + + uint32_t MessageStorage; /*!< Specifies the HP Message Storage. + This parameter can be a value of @ref FDCAN_hp_msg_storage */ + + uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the + message was stored. + This parameter is valid only when MessageStorage is: + FDCAN_HP_STORAGE_RXFIFO0 + or + FDCAN_HP_STORAGE_RXFIFO1 */ + +} FDCAN_HpMsgStatusTypeDef; + +/** + * @brief FDCAN Protocol Status structure definition + */ +typedef struct +{ + uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format + frame with its BRS flag set. + This parameter can be a value of @ref FDCAN_protocol_error_code */ + + uint32_t Activity; /*!< Specifies the FDCAN module communication state. + This parameter can be a value of @ref FDCAN_communication_state */ + + uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. + This parameter can be: + - 0 : The FDCAN is in Error_Active state + - 1 : The FDCAN is in Error_Passive state */ + + uint32_t Warning; /*!< Specifies the FDCAN module warning status. + This parameter can be: + - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96 + - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ + + uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. + This parameter can be: + - 0 : The FDCAN is not in Bus_Off state + - 1 : The FDCAN is in Bus_Off state */ + + uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its ESI flag set + - 1 : Last received CAN FD message had its ESI flag set */ + + uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. + This parameter can be: + - 0 : Last received CAN FD message did not have its BRS flag set + - 1 : Last received CAN FD message had its BRS flag set */ + + uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status. + This parameter can be: + - 0 : no CAN FD message received + - 1 : CAN FD message received */ + + uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. + This parameter can be: + - 0 : No protocol exception event occurred since last read access + - 1 : Protocol exception event occurred */ + + uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. + This parameter can be a number between 0 and 127 */ + +} FDCAN_ProtocolStatusTypeDef; + +/** + * @brief FDCAN Error Counters structure definition + */ +typedef struct +{ + uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. + This parameter can be a number between 0 and 255 */ + + uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. + This parameter can be a number between 0 and 127 */ + + uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. + This parameter can be: + - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 + - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */ + + uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. + This parameter can be a number between 0 and 255. + This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt + or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of + TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ + +} FDCAN_ErrorCountersTypeDef; + +/** + * @brief FDCAN TT Init structure definition + */ +typedef struct +{ + uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode. + This parameter can be a value of @ref FDCAN_operation_mode */ + + uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation. + This parameter can be a value of @ref FDCAN_TT_operation. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL0 */ + + uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master. + This parameter can be a value of @ref FDCAN_TT_time_master */ + + uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR + numerator : TUR = (Numerator +/- SDL) / Denominator. + With : SDL = 2^(SyncDevLimit+5). + This parameter must be a number between 0 and 7 */ + + uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset. + This parameter must be a number between 0 and 127 */ + + uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization. + This parameter can be a value of @ref FDCAN_TT_external_clk_sync. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL1 */ + + uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after + which the application has to serve the application watchdog. + The application watchdog is incremented once each 256 NTUs. + The application watchdog can be disabled by setting AppWdgLimit to 0. + This parameter must be a number between 0 and 255. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL0 */ + + uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering. + This parameter can be a value of @ref FDCAN_TT_global_time_filtering. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL1 */ + + uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration. + This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL1 */ + + uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity. + This parameter can be a value of @ref FDCAN_TT_event_trig_polarity. + This parameter is ignored if OperationMode is set to + FDCAN_TT_COMMUNICATION_LEVEL0 */ + + uint32_t BasicCyclesNbr; /*!< Specifies the number of basic cycles in the system matrix. + This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */ + + uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc. + This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */ + + uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs. + This parameter must be a number between 1 and 16 */ + + uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix. + This is the sum of Tx_Triggers for exclusive, single arbitrating and + merged arbitrating windows. + This parameter must be a number between 0 and 4095 */ + + uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator. + It is advised to set this parameter to the largest applicable value. + This parameter must be a number between 0x10000 and 0x1FFFF */ + + uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator. + This parameter must be a number between 0x0001 and 0x3FFF */ + + uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements. + This parameter must be a number between 0 and 64 */ + + uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger. + This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */ + + uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger. + This parameter can be a value of @ref FDCAN_TT_event_trig_selection */ + +} FDCAN_TT_ConfigTypeDef; + +/** + * @brief FDCAN Trigger structure definition + */ +typedef struct +{ + uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured. + This parameter must be a number between 0 and 63 */ + + uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor. + This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */ + + uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active. + This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. + This parameter must be a number between 0 and RepeatFactor */ + + uint32_t TmEventInt; /*!< Enable or disable the internal time mark event. + If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element + becomes active. + This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */ + + uint32_t TmEventExt; /*!< Enable or disable the external time mark event. + If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when + trigger memory element becomes active. + This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */ + + uint32_t TriggerType; /*!< Specifies the trigger type. + This parameter can be a value of @ref FDCAN_TT_Trigger_Type */ + + uint32_t FilterType; /*!< Specifies the filter identifier type. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid. + This parameter can be a value of @ref FDCAN_Tx_location. + This parameter is taken in consideration only if the trigger is configured for + transmission. */ + + uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid. + This parameter is taken in consideration only if the trigger is configured for + reception. + This parameter must be a number between: + - 0 and 127, if FilterType is FDCAN_STANDARD_ID + - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ + +} FDCAN_TriggerTypeDef; + +/** + * @brief FDCAN TT Operation Status structure definition + */ +typedef struct +{ + uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level. + This parameter can be a value of @ref FDCAN_TT_error_level */ + + uint32_t MasterState; /*!< Specifies the type of the TT master state. + This parameter can be a value of @ref FDCAN_TT_master_state */ + + uint32_t SyncState; /*!< Specifies the type of the TT synchronization state. + This parameter can be a value of @ref FDCAN_TT_sync_state */ + + uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase. + This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. + This parameter can be: + - 0 : Global time not valid + - 1 : Global time in phase with Time Master */ + + uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed. + This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. + This parameter can be: + - 0 : Local clock speed not synchronized to Time Master clock speed + - 1 : Synchronization Deviation = SDL */ + + uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value. + This parameter can be a number between 0 and 0xFF */ + + uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State. + This parameter can be: + - 0 : No global time preset pending + - 1 : Node waits for the global time preset to take effect */ + + uint32_t GapFinished; /*!< Specifies whether a Gap is finished. + This parameter can be: + - 0 : Reset at the end of each reference message + - 1 : Gap finished */ + + uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master. + This parameter can be a number between 0 and 0x7 */ + + uint32_t GapStarted; /*!< Specifies whether a Gap is started. + This parameter can be: + - 0 : No Gap in schedule + - 1 : Gap time after Basic Cycle has started */ + + uint32_t WaitForEvt; /*!< Specifies whether a Gap is announced. + This parameter can be: + - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0 + - 1 : Reference message with Next_is_Gap = 1 received */ + + uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State. + This parameter can be: + - 0 : Application Watchdog served in time + - 1 : Failed to serve Application Watchdog in time */ + + uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State. + This parameter can be: + - 0 : No external clock synchronization pending + - 1 : Node waits for external clock synchronization to take effect */ + + uint32_t PhaseLock; /*!< Specifies the Phase Lock State. + This parameter can be: + - 0 : Phase outside range + - 1 : Phase inside range */ + +} FDCAN_TTOperationStatusTypeDef; + +/** + * @brief FDCAN Message RAM blocks + */ +typedef struct +{ + uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. + This parameter must be a 32-bit word address */ + + uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. + This parameter must be a 32-bit word address */ + + uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address. + This parameter must be a 32-bit word address */ + + uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM. + This parameter must be a 32-bit word address */ + +} FDCAN_MsgRamAddressTypeDef; + +/** + * @brief FDCAN handle structure definition + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +typedef struct __FDCAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +{ + FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ + + TTCAN_TypeDef *ttcan; /*!< TT register base address */ + + FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ + + FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ + + uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index + of latest Tx FIFO/Queue request */ + + __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ + + HAL_LockTypeDef Lock; /*!< FDCAN locking object */ + + __IO uint32_t ErrorCode; /*!< FDCAN Error code */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< FDCAN Clock Calibration callback */ + void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ + void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ + void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ + void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ + void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ + void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ + void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Rx Buffer New Message callback */ + void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ + void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ + void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ + void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ + void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ + void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< FDCAN T Schedule Synchronization callback */ + void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< FDCAN TT Time Mark callback */ + void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback */ + void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< FDCAN TT Global Time callback */ + + void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ + void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +} FDCAN_HandleTypeDef; + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL FDCAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ + HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */ + HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */ + HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */ + HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */ + HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */ + + HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */ + HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */ + +} HAL_FDCAN_CallbackIDTypeDef; + +/** + * @brief HAL FDCAN Callback pointer definition + */ +typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ +typedef void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< pointer to Clock Calibration FDCAN callback function */ +typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ +typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ +typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ +typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ +typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ +typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ +typedef void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< pointer to TT Schedule Synchronization FDCAN callback function */ +typedef void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< pointer to TT Time Mark FDCAN callback function */ +typedef void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function */ +typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< pointer to TT Global Time FDCAN callback function */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants + * @{ + */ + +/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code + * @{ + */ +#define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ +#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ +#define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ +#define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ +#define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ +#define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ +#define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ +#define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ +#define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ +#define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ +#define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ +#define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ +#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */ +#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */ +#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */ +#define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */ +#define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */ +#define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */ +#define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */ +#define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */ +#define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */ + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_format FDCAN Frame Format + * @{ + */ +#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ +#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ +#define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ +/** + * @} + */ + +/** @defgroup FDCAN_operating_mode FDCAN Operating Mode + * @{ + */ +#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ +#define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ +#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ +#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ +/** + * @} + */ + +/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration + * @{ + */ +#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */ +#define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */ +/** + * @} + */ + +/** @defgroup FDCAN_clock_divider FDCAN Clock Divider + * @{ + */ +#define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ +#define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */ +#define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */ +#define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */ +#define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */ +#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */ +#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */ +#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */ +#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */ +#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */ +#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */ +#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */ +#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */ +#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */ +#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */ +#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */ +/** + * @} + */ + +/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length + * @{ + */ +#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */ +#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */ +/** + * @} + */ + +/** @defgroup FDCAN_calibration_state FDCAN Calibration State + * @{ + */ +#define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */ +#define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */ +#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */ +/** + * @} + */ + +/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter + * @{ + */ +#define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */ +#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */ +#define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */ +/** + * @} + */ + +/** @defgroup FDCAN_data_field_size FDCAN Data Field Size + * @{ + */ +#define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */ +#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */ +#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */ +#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */ +#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */ +#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */ +#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */ +/** + * @} + */ + +/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode + * @{ + */ +#define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ +#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ +/** + * @} + */ + +/** @defgroup FDCAN_id_type FDCAN ID Type + * @{ + */ +#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ +#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_type FDCAN Frame Type + * @{ + */ +#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ +#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup FDCAN_data_length_code FDCAN Data Length Code + * @{ + */ +#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ +/** + * @} + */ + +/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator + * @{ + */ +#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ +#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ +/** + * @} + */ + +/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching + * @{ + */ +#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ +#define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ +/** + * @} + */ + +/** @defgroup FDCAN_format FDCAN format + * @{ + */ +#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ +#define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ +/** + * @} + */ + +/** @defgroup FDCAN_EFC FDCAN Event FIFO control + * @{ + */ +#define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ +#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_type FDCAN Filter Type + * @{ + */ +#define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ +#define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ +#define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ +#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ +/** + * @} + */ + +/** @defgroup FDCAN_filter_config FDCAN Filter Configuration + * @{ + */ +#define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ +#define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ +#define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ +#define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ +#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ +#define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_location FDCAN Tx Location + * @{ + */ +#define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ +#define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ +#define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ +#define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */ +#define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */ +#define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */ +#define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */ +#define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */ +#define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */ +#define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */ +#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */ +#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */ +#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */ +#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */ +#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */ +#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */ +#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */ +#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */ +#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */ +#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */ +#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */ +#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */ +#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */ +#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */ +#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */ +#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */ +#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */ +#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */ +#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */ +#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */ +#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */ +#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_location FDCAN Rx Location + * @{ + */ +#define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ +#define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ +#define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */ +#define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */ +#define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */ +#define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */ +#define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */ +#define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */ +#define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */ +#define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */ +#define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */ +#define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */ +#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */ +#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */ +#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */ +#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */ +#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */ +#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */ +#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */ +#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */ +#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */ +#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */ +#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */ +#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */ +#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */ +#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */ +#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */ +#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */ +#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */ +#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */ +#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */ +#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */ +#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */ +#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */ +#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */ +#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */ +#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */ +#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */ +#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */ +#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */ +#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */ +#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */ +#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */ +#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */ +#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */ +#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */ +#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */ +#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */ +#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */ +#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */ +#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */ +#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */ +#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */ +#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */ +#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */ +#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */ +#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */ +#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */ +#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */ +#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */ +#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */ +#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */ +#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */ +#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */ +#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */ +#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */ +/** + * @} + */ + +/** @defgroup FDCAN_event_type FDCAN Event Type + * @{ + */ +#define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ +#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ +/** + * @} + */ + +/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage + * @{ + */ +#define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ +#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ +#define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ +#define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code + * @{ + */ +#define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ +#define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ +#define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ +#define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ +#define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ +#define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ +#define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ +#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ +/** + * @} + */ + +/** @defgroup FDCAN_communication_state FDCAN communication state + * @{ + */ +#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ +#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ +#define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ +#define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ +/** + * @} + */ + +/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark + * @{ + */ +#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */ +#define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */ +#define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode + * @{ + */ +#define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ +#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */ +/** + * @} + */ + +/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames + * @{ + */ +#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ +#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ +#define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ +/** + * @} + */ + +/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames + * @{ + */ +#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ +#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line + * @{ + */ +#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ +#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp FDCAN timestamp + * @{ + */ +#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ +#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ +/** + * @} + */ + +/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler + * @{ + */ +#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ +#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ +#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ +#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ +#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ +#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ +#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ +#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ +#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ +#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ +#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ +#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ +#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ +#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ +#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ +#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ +/** + * @} + */ + +/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation + * @{ + */ +#define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ +#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ +#define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ +#define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload + * @{ + */ +#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */ +#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor + * @{ + */ +#define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */ +#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */ +#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */ +#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */ +#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */ +#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */ +#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type + * @{ + */ +#define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */ +#define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */ +#define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */ +#define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */ +#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */ +#define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */ +#define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */ +#define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */ +#define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */ +#define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */ +#define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal + * @{ + */ +#define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ +#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external + * @{ + */ +#define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ +#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */ +/** + * @} + */ + +/** @defgroup FDCAN_operation_mode FDCAN Operation Mode + * @{ + */ +#define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */ +#define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */ +#define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_operation FDCAN TT Operation + * @{ + */ +#define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */ +#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master + * @{ + */ +#define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */ +#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization + * @{ + */ +#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */ +#define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering + * @{ + */ +#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */ +#define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration + * @{ + */ +#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */ +#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity + * @{ + */ +#define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */ +#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number + * @{ + */ +#define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */ +#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync + * @{ + */ +#define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */ +#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */ +#define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection + * @{ + */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */ +#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection + * @{ + */ +#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */ +#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source + * @{ + */ +#define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */ +#define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */ +#define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */ +#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity + * @{ + */ +#define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */ +#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source + * @{ + */ +#define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */ +#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */ +#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */ +#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level + * @{ + */ +#define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */ +#define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */ +#define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */ +#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_master_state FDCAN TT Master State + * @{ + */ +#define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */ +#define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */ +#define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */ +#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */ +/** + * @} + */ + +/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State + * @{ + */ +#define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */ +#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */ +#define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */ +#define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */ +/** + * @} + */ + +/** @defgroup Interrupt_Masks Interrupt masks + * @{ + */ +#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */ +#define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */ +/** + * @} + */ + +/** @defgroup FDCAN_flags FDCAN Flags + * @{ + */ +#define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ +#define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ +#define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ +#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ +#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */ +#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ +#define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ +#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */ +#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ +#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ +#define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ +#define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */ +#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ +#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ +#define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ +#define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */ +#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ +#define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ +#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ +#define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ +#define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ +#define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ +#define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ +#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ +#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ +#define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ +#define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */ +#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts FDCAN Interrupts + * @{ + */ + +/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts + * @{ + */ +#define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ +#define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ +#define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts + * @{ + */ +#define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ +#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */ +/** + * @} + */ + +/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts + * @{ + */ +#define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ +#define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ +/** + * @} + */ + +/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts + * @{ + */ +#define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */ +#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts + * @{ + */ +#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ +#define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ +#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */ +#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ +#define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ +#define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */ +#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ +/** + * @} + */ + +/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts + * @{ + */ +#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ +#define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ +#define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */ +#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts + * @{ + */ +#define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ +#define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ +#define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ +#define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ +#define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ +#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ +/** + * @} + */ + +/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts + * @{ + */ +#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ +#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ +#define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FDCAN_TTflags FDCAN TT Flags + * @{ + */ +#define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */ +#define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */ +#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */ +#define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */ +#define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */ +#define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */ +#define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */ +#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */ +#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */ +#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */ +#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */ +#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */ +#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */ +#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */ +#define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */ +#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */ +#define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */ +/** + * @} + */ + +/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts + * @{ + */ + +/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts + * @{ + */ +#define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */ +#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */ +#define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */ +#define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */ +/** + * @} + */ + +/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts + * @{ + */ +#define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */ +#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */ +/** + * @} + */ + +/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt + * @{ + */ +#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */ +/** + * @} + */ + +/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts + * @{ + */ +#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */ +#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */ +/** + * @} + */ + +/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts + * @{ + */ +#define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */ +#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */ +#define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */ +#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */ +#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */ +#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */ +/** + * @} + */ + +/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts + * @{ + */ +#define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */ +#define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */ +#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */ +#define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros + * @{ + */ + +/** @brief Reset FDCAN handle state. + * @param __HANDLE__ FDCAN handle. + * @retval None + */ +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ + }while(0) + + +/** + * @brief Disable the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ + }while(0) + +/** + * @brief Check whether the specified FDCAN interrupt is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN interrupt. + * This parameter can be one of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__))) + +/** + * @brief Clear the specified FDCAN interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the interrupts to clear. + * This parameter can be any combination of @arg FDCAN_Interrupts + * @retval None + */ +#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ +do{ \ + ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ + }while(0) + +/** + * @brief Check whether the specified FDCAN flag is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ FDCAN flag. + * This parameter can be one of @arg FDCAN_flags + * @retval FlagStatus + */ +#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__))) + +/** + * @brief Clear the specified FDCAN flags. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ specifies the flags to clear. + * This parameter can be any combination of @arg FDCAN_flags + * @retval None + */ +#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +do{ \ + ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \ + FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \ + }while(0) + +/** @brief Check if the specified FDCAN interrupt source is enabled or disabled. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. + * This parameter can be a value of @arg FDCAN_Interrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__))) + +/** + * @brief Enable the specified FDCAN TT interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN TT interrupt. + * This parameter can be any combination of @arg FDCAN_TTInterrupts + * @retval None + */ +#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FDCAN TT interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN TT interrupt. + * This parameter can be any combination of @arg FDCAN_TTInterrupts + * @retval None + */ +#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified FDCAN TT interrupt is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ FDCAN TT interrupt. + * This parameter can be one of @arg FDCAN_TTInterrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__)) + +/** + * @brief Clear the specified FDCAN TT interrupts. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the TT interrupts to clear. + * This parameter can be any combination of @arg FDCAN_TTInterrupts + * @retval None + */ +#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__)) + +/** + * @brief Check whether the specified FDCAN TT flag is set or not. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ FDCAN TT flag. + * This parameter can be one of @arg FDCAN_TTflags + * @retval FlagStatus + */ +#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__)) + +/** + * @brief Clear the specified FDCAN TT flags. + * @param __HANDLE__ FDCAN handle. + * @param __FLAG__ specifies the TT flags to clear. + * This parameter can be any combination of @arg FDCAN_TTflags + * @retval None + */ +#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__)) + +/** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled. + * @param __HANDLE__ FDCAN handle. + * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check. + * This parameter can be a value of @arg FDCAN_TTInterrupts + * @retval ITStatus + */ +#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FDCAN_Exported_Functions + * @{ + */ + +/** @addtogroup FDCAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group2 + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig); +uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter); +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); +HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark); +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group3 + * @{ + */ +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); +HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); +uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex); +uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); +uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); +uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group4 + * @{ + */ +/* TT Configuration and control functions**************************************/ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig); +HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset); +HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase); +HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); +HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group5 + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine); +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes); +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); +HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs); +HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs); +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group6 + * @{ + */ +/* Callback functions *********************************************************/ +void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); +void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); +void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); +void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); +void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); +void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); +void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); +void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); +void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); +void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group7 + * @{ + */ +/* Peripheral State functions *************************************************/ +uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Types FDCAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Variables FDCAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Constants FDCAN Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ +#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ + ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ + ((FORMAT) == FDCAN_FRAME_FD_BRS )) +#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ + ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ + ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ + ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ + ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) + +#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \ + ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE )) + +#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ + ((CKDIV) == FDCAN_CLOCK_DIV10) || \ + ((CKDIV) == FDCAN_CLOCK_DIV12) || \ + ((CKDIV) == FDCAN_CLOCK_DIV14) || \ + ((CKDIV) == FDCAN_CLOCK_DIV16) || \ + ((CKDIV) == FDCAN_CLOCK_DIV18) || \ + ((CKDIV) == FDCAN_CLOCK_DIV20) || \ + ((CKDIV) == FDCAN_CLOCK_DIV22) || \ + ((CKDIV) == FDCAN_CLOCK_DIV24) || \ + ((CKDIV) == FDCAN_CLOCK_DIV26) || \ + ((CKDIV) == FDCAN_CLOCK_DIV28) || \ + ((CKDIV) == FDCAN_CLOCK_DIV30)) +#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) +#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) +#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) +#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) +#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) +#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) +#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) +#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) +#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) +#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) +#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \ + ((SIZE) == FDCAN_DATA_BYTES_12) || \ + ((SIZE) == FDCAN_DATA_BYTES_16) || \ + ((SIZE) == FDCAN_DATA_BYTES_20) || \ + ((SIZE) == FDCAN_DATA_BYTES_24) || \ + ((SIZE) == FDCAN_DATA_BYTES_32) || \ + ((SIZE) == FDCAN_DATA_BYTES_48) || \ + ((SIZE) == FDCAN_DATA_BYTES_64)) +#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ + ((MODE) == FDCAN_TX_QUEUE_OPERATION)) +#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ + ((ID_TYPE) == FDCAN_EXTENDED_ID)) +#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ + ((CONFIG) == FDCAN_FILTER_REJECT ) || \ + ((CONFIG) == FDCAN_FILTER_HP ) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \ + ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER )) +#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \ + ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \ + ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \ + ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \ + ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \ + ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \ + ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \ + ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \ + ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \ + ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \ + ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \ + ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31)) +#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ + ((FIFO) == FDCAN_RX_FIFO1)) +#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ + ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) +#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK )) +#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ + ((TYPE) == FDCAN_FILTER_DUAL ) || \ + ((TYPE) == FDCAN_FILTER_MASK ) || \ + ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) +#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ + ((TYPE) == FDCAN_REMOTE_FRAME)) +#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ + ((DLC) == FDCAN_DLC_BYTES_1 ) || \ + ((DLC) == FDCAN_DLC_BYTES_2 ) || \ + ((DLC) == FDCAN_DLC_BYTES_3 ) || \ + ((DLC) == FDCAN_DLC_BYTES_4 ) || \ + ((DLC) == FDCAN_DLC_BYTES_5 ) || \ + ((DLC) == FDCAN_DLC_BYTES_6 ) || \ + ((DLC) == FDCAN_DLC_BYTES_7 ) || \ + ((DLC) == FDCAN_DLC_BYTES_8 ) || \ + ((DLC) == FDCAN_DLC_BYTES_12) || \ + ((DLC) == FDCAN_DLC_BYTES_16) || \ + ((DLC) == FDCAN_DLC_BYTES_20) || \ + ((DLC) == FDCAN_DLC_BYTES_24) || \ + ((DLC) == FDCAN_DLC_BYTES_32) || \ + ((DLC) == FDCAN_DLC_BYTES_48) || \ + ((DLC) == FDCAN_DLC_BYTES_64)) +#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ + ((ESI) == FDCAN_ESI_PASSIVE)) +#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ + ((BRS) == FDCAN_BRS_ON )) +#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ + ((FDF) == FDCAN_FD_CAN )) +#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ + ((EFC) == FDCAN_STORE_TX_EVENTS)) +#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U) +#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U) +#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \ + ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \ + ((FIFO) == FDCAN_CFG_RX_FIFO1 )) +#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ + ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ + ((DESTINATION) == FDCAN_REJECT )) +#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ + ((DESTINATION) == FDCAN_REJECT_REMOTE)) +#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ + ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) +#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ + ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) +#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ + ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) +#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ + ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ + ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) +#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \ + ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64)) +#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \ + ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \ + ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER )) +#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \ + ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD)) +#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \ + ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE)) +#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \ + ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \ + ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \ + ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \ + ((TYPE) == FDCAN_TT_END_OF_LIST )) +#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \ + ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT)) +#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \ + ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT)) +#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \ + ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \ + ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 )) +#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \ + ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION)) +#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \ + ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER)) +#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \ + ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE )) +#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \ + ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE )) +#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \ + ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE )) +#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \ + ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING)) +#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \ + ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64)) +#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \ + ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \ + ((SYNC) == FDCAN_TT_SYNC_MATRIX_START )) +#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U)) +#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU)) +#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU)) +#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC))) +#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC))) +#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \ + ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \ + ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \ + ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3)) +#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \ + ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \ + ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \ + ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3)) +#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U)) +#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \ + ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \ + ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \ + ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME)) +#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \ + ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING)) +#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \ + ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \ + ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \ + ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME)) + +#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__) ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Functions FDCAN Private Functions + * @{ + */ + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +#endif /* FDCAN1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FDCAN_H */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h new file mode 100644 index 0000000..a4773b5 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h @@ -0,0 +1,861 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FLASH_H +#define STM32H7xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE_BANK1, + FLASH_PROC_MASSERASE_BANK1, + FLASH_PROC_PROGRAM_BANK1, + FLASH_PROC_SECTERASE_BANK2, + FLASH_PROC_MASSERASE_BANK2, + FLASH_PROC_PROGRAM_BANK2, + FLASH_PROC_ALLBANK_MASSERASE +} FLASH_ProcedureTypeDef; + + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in IT context */ + + __IO uint32_t VoltageForErase; /*!< Internal variable to provide voltage range selected by user in IT context */ + + __IO uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */ + + __IO uint32_t Address; /*!< Internal variable to save address selected for program */ + + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + + __IO uint32_t ErrorCode; /*!< FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ + +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */ +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */ +#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */ +#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE FLASH_FLAG_OPERR /*!< Operation Error */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP FLASH_FLAG_RDPERR /*!< Read Protection Error */ +#define HAL_FLASH_ERROR_RDS FLASH_FLAG_RDSERR /*!< Read Secured Error */ +#define HAL_FLASH_ERROR_SNECC FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error */ +#define HAL_FLASH_ERROR_DBECC FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error */ +#define HAL_FLASH_ERROR_CRCRD FLASH_FLAG_CRCRDERR /*!< CRC Read Error */ + +#define HAL_FLASH_ERROR_WRP_BANK1 FLASH_FLAG_WRPERR_BANK1 /*!< Write Protection Error on Bank 1 */ +#define HAL_FLASH_ERROR_PGS_BANK1 FLASH_FLAG_PGSERR_BANK1 /*!< Program Sequence Error on Bank 1 */ +#define HAL_FLASH_ERROR_STRB_BANK1 FLASH_FLAG_STRBERR_BANK1 /*!< Strobe Error on Bank 1 */ +#define HAL_FLASH_ERROR_INC_BANK1 FLASH_FLAG_INCERR_BANK1 /*!< Inconsistency Error on Bank 1 */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE_BANK1 FLASH_FLAG_OPERR_BANK1 /*!< Operation Error on Bank 1 */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP_BANK1 FLASH_FLAG_RDPERR_BANK1 /*!< Read Protection Error on Bank 1 */ +#define HAL_FLASH_ERROR_RDS_BANK1 FLASH_FLAG_RDSERR_BANK1 /*!< Read Secured Error on Bank 1 */ +#define HAL_FLASH_ERROR_SNECC_BANK1 FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */ +#define HAL_FLASH_ERROR_DBECC_BANK1 FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1 */ +#define HAL_FLASH_ERROR_CRCRD_BANK1 FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1 */ + +#define HAL_FLASH_ERROR_WRP_BANK2 FLASH_FLAG_WRPERR_BANK2 /*!< Write Protection Error on Bank 2 */ +#define HAL_FLASH_ERROR_PGS_BANK2 FLASH_FLAG_PGSERR_BANK2 /*!< Program Sequence Error on Bank 2 */ +#define HAL_FLASH_ERROR_STRB_BANK2 FLASH_FLAG_STRBERR_BANK2 /*!< Strobe Error on Bank 2 */ +#define HAL_FLASH_ERROR_INC_BANK2 FLASH_FLAG_INCERR_BANK2 /*!< Inconsistency Error on Bank 2 */ +#if defined (FLASH_SR_OPERR) +#define HAL_FLASH_ERROR_OPE_BANK2 FLASH_FLAG_OPERR_BANK2 /*!< Operation Error on Bank 2 */ +#endif /* FLASH_SR_OPERR */ +#define HAL_FLASH_ERROR_RDP_BANK2 FLASH_FLAG_RDPERR_BANK2 /*!< Read Protection Error on Bank 2 */ +#define HAL_FLASH_ERROR_RDS_BANK2 FLASH_FLAG_RDSERR_BANK2 /*!< Read Secured Error on Bank 2 */ +#define HAL_FLASH_ERROR_SNECC_BANK2 FLASH_FLAG_SNECCERR_BANK2 /*!< ECC Single Correction Error on Bank 2 */ +#define HAL_FLASH_ERROR_DBECC_BANK2 FLASH_FLAG_DBECCERR_BANK2 /*!< ECC Double Detection Error on Bank 2 */ +#define HAL_FLASH_ERROR_CRCRD_BANK2 FLASH_FLAG_CRCRDERR_BANK2 /*!< CRC Read Error on Bank2 */ + +#define HAL_FLASH_ERROR_OB_CHANGE FLASH_OPTSR_OPTCHANGEERR /*!< Option Byte Change Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word at a specified address */ +#if defined (FLASH_OPTCR_PG_OTP) +#define FLASH_TYPEPROGRAM_OTPWORD 0x02U /*!< Program an OTP word at a specified address */ +#endif /* FLASH_OPTCR_PG_OTP */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< Write Buffer Not Empty flag */ +#define FLASH_FLAG_QW FLASH_SR_QW /*!< Wait Queue on flag */ +#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC Busy flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */ +#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< Strobe Error flag */ +#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */ +#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */ +#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */ +#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */ +#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC End of Calculation flag */ +#define FLASH_FLAG_CRCRDERR FLASH_SR_CRCRDERR /*!< CRC Read Error on bank flag */ + +#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */ +#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Write Buffer Not Empty on Bank 1 flag */ +#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Wait Queue on Bank 1 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC Busy on Bank 1 flag */ +#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */ +#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */ +#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */ +#define FLASH_FLAG_STRBERR_BANK1 FLASH_SR_STRBERR /*!< Strobe Error on Bank 1 flag */ +#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */ +#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */ +#define FLASH_FLAG_SNECCERR_BANK1 FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */ +#define FLASH_FLAG_DBECCERR_BANK1 FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */ +#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC End of Calculation on Bank 1 flag */ +#define FLASH_FLAG_CRCRDERR_BANK1 FLASH_SR_CRCRDERR /*!< CRC Read error on Bank 1 flag */ + +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ + FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ + FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \ + FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCERR_BANK1 | \ + FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \ + FLASH_FLAG_STRBERR_BANK1 | FLASH_FLAG_INCERR_BANK1 | \ + FLASH_FLAG_RDPERR_BANK1 | FLASH_FLAG_RDSERR_BANK1 | \ + FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \ + FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */ +#endif /* FLASH_SR_OPERR */ + +#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \ + FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \ + FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \ + FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */ + +#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */ +#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Write Buffer Not Empty on Bank 2 flag */ +#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Wait Queue on Bank 2 flag */ +#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC Busy on Bank 2 flag */ +#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */ +#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */ +#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */ +#define FLASH_FLAG_STRBERR_BANK2 (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */ +#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */ +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */ +#endif /* FLASH_SR_OPERR */ +#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */ +#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */ +#define FLASH_FLAG_SNECCERR_BANK2 (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */ +#define FLASH_FLAG_DBECCERR_BANK2 (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */ +#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC End of Calculation on Bank 2 flag */ +#define FLASH_FLAG_CRCRDERR_BANK2 (FLASH_SR_CRCRDERR | 0x80000000U) /*!< CRC Read error on Bank 2 flag */ + +#if defined (FLASH_SR_OPERR) +#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ + FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ + FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \ + FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCERR_BANK2 | \ + FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#else +#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \ + FLASH_FLAG_STRBERR_BANK2 | FLASH_FLAG_INCERR_BANK2 | \ + FLASH_FLAG_RDPERR_BANK2 | FLASH_FLAG_RDSERR_BANK2 | \ + FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \ + FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */ +#endif /* FLASH_SR_OPERR */ + +#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \ + FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \ + FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \ + FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Bank 1 Operation Interrupt source */ +#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE /*!< Write Protection Error on Bank 1 Interrupt source */ +#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */ +#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */ +#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ +#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */ +#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */ +#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */ +#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE /*!< Double Detection ECC Error on Bank 1 Interrupt source */ +#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */ +#define FLASH_IT_CRCRDERR_BANK1 FLASH_CR_CRCRDERRIE /*!< CRC Read error on Bank 1 Interrupt source */ + +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ + FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ + FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \ + FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \ + FLASH_IT_SNECCERR_BANK1 | FLASH_IT_DBECCERR_BANK1 | \ + FLASH_IT_CRCEND_BANK1 | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \ + FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \ + FLASH_IT_INCERR_BANK1 | FLASH_IT_RDPERR_BANK1 | \ + FLASH_IT_RDSERR_BANK1 | FLASH_IT_SNECCERR_BANK1 | \ + FLASH_IT_DBECCERR_BANK1 | FLASH_IT_CRCEND_BANK1 | \ + FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ + +#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */ +#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */ +#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */ +#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */ +#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */ +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */ +#endif /* FLASH_CR_OPERRIE */ +#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */ +#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */ +#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */ +#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 Interrupt source */ +#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */ +#define FLASH_IT_CRCRDERR_BANK2 (FLASH_CR_CRCRDERRIE | 0x80000000U) /*!< CRC Read Error on Bank 2 Interrupt source */ + +#if defined (FLASH_CR_OPERRIE) +#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ + FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ + FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2 | \ + FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK2 | \ + FLASH_IT_SNECCERR_BANK2 | FLASH_IT_DBECCERR_BANK2 | \ + FLASH_IT_CRCEND_BANK2 | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#else +#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | \ + FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK2 | \ + FLASH_IT_INCERR_BANK2 | FLASH_IT_RDPERR_BANK2 | \ + FLASH_IT_RDSERR_BANK2 | FLASH_IT_SNECCERR_BANK2 | \ + FLASH_IT_DBECCERR_BANK2 | FLASH_IT_CRCEND_BANK2 | \ + FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */ +#endif /* FLASH_CR_OPERRIE */ +/** + * @} + */ + +#if defined (FLASH_CR_PSIZE) +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE 0x00000000U /*!< Flash program/erase by 8 bits */ +#define FLASH_PSIZE_HALF_WORD FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ +#define FLASH_PSIZE_WORD FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ +#define FLASH_PSIZE_DOUBLE_WORD FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ +/** + * @} + */ +#endif /* FLASH_CR_PSIZE */ + + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U +#define FLASH_KEY2 0xCDEF89ABU +#define FLASH_OPT_KEY1 0x08192A3BU +#define FLASH_OPT_KEY2 0x4C5D6E7FU +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */ +#if (FLASH_SECTOR_TOTAL == 128) +#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */ +#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */ +#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */ +#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */ +#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */ +#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */ +#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */ +#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */ +#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */ +#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */ +#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */ +#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */ +#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */ +#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */ +#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */ +#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */ +#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */ +#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */ +#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */ +#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */ +#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */ +#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */ +#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */ +#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */ +#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */ +#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */ +#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */ +#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */ +#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */ +#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */ +#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */ +#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */ +#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */ +#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */ +#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */ +#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */ +#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */ +#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */ +#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */ +#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */ +#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */ +#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */ +#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */ +#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */ +#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */ +#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */ +#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */ +#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */ +#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */ +#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */ +#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */ +#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */ +#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */ +#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */ +#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */ +#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */ +#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */ +#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */ +#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */ +#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */ +#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */ +#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */ +#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */ +#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */ +#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */ +#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */ +#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */ +#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */ +#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */ +#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */ +#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */ +#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */ +#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */ +#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */ +#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */ +#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */ +#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */ +#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */ +#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */ +#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */ +#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */ +#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */ +#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */ +#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */ +#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */ +#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */ +#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */ +#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */ +#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */ +#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */ +#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */ +#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */ +#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */ +#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */ +#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */ +#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */ +#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */ +#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */ +#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */ +#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */ +#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */ +#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */ +#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */ +#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */ +#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__: FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * In case of Bank 1 This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source + * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source + * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source + * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source + * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source + * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source + * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source + * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source + * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources + * @retval none + */ + +#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__)) + +#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ + __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \ + __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ + + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ : FLASH interrupt + * In case of Bank 1 This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source + * @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source + * @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source + * @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source + * @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source + * @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK1 : CRC Read error on Bank 1 Interrupt source + * @arg FLASH_IT_ALL_BANK1 : All Bank 1 Interrupt sources + * + * In case of Bank 2, this parameter can be any combination of the following values: + * @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source + * @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source + * @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source + * @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source + * @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source + * @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source + * @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source + * @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source + * @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source + * @arg FLASH_IT_CRCRDERR_BANK2 : CRC Read error on Bank 2 Interrupt source + * @arg FLASH_IT_ALL_BANK2 : All Bank 2 Interrupt sources + * @retval none + */ + +#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__)) + +#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \ + __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \ + __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)) +#else +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) +#endif /* DUAL_BANK */ + + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param __FLAG__: specifies the FLASH flag to check. + * In case of Bank 1 This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag + * @arg FLASH_FLAG_WBNE_BANK1 : Write Buffer Not Empty on Bank 1 flag + * @arg FLASH_FLAG_QW_BANK1 : Wait Queue on Bank 1 flag + * @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag + * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag + * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag + * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag + * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag + * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag + * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag + * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag + * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag + * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag + * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag + * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag + * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * + * In case of Bank 2 This parameter can be one of the following values : + * @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag + * @arg FLASH_FLAG_WBNE_BANK2 : Write Buffer Not Empty on Bank 2 flag + * @arg FLASH_FLAG_QW_BANK2 : Wait Queue on Bank 2 flag + * @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag + * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag + * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag + * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag + * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag + * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag + * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag + * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag + * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag + * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag + * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag + * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag + * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__)) + +#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU))) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \ + __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_GET_FLAG(__FLAG__) __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ + + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__: specifies the FLASH flags to clear. + * In case of Bank 1, this parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag + * @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag + * @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag + * @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag + * @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag + * @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag + * @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag + * @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag + * @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag + * @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag + * @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag + * @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags + * @arg FLASH_FLAG_ALL_BANK1 : All Bank 1 flags + * + * In case of Bank 2, this parameter can be any combination of the following values : + * @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag + * @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag + * @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag + * @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag + * @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag + * @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag + * @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag + * @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag + * @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag + * @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag + * @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag + * @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag + * @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags + * @arg FLASH_FLAG_ALL_BANK2 : All Bank 2 flags + * @retval none + */ + +#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__)) + +#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU)) + +#if defined (DUAL_BANK) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \ + __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)) +#else +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) +#endif /* DUAL_BANK */ + +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32h7xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) +#endif /* FLASH_OPTCR_PG_OTP */ + +#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT)) +#if defined (DUAL_BANK) +#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT)) +#endif /* DUAL_BANK */ + +#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG)) +#if defined (DUAL_BANK) +#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG)) +#endif /* DUAL_BANK */ + +#if defined (DUAL_BANK) +#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE)) +#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END)) +#else +#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) <= FLASH_END)) +#endif /* DUAL_BANK */ + +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#else +#if defined (FLASH_OPTCR_PG_OTP) +#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS) (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU)) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \ + IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)) +#else +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS)) +#endif /* FLASH_OPTCR_PG_OTP */ +#endif /* DUAL_BANK */ + +#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U)) + +#if defined (DUAL_BANK) +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2)) +#else +#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) +#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) +#endif /* DUAL_BANK */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank); +HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout); +HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FLASH_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h new file mode 100644 index 0000000..28bb380 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h @@ -0,0 +1,1013 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_FLASH_EX_H +#define STM32H7xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASH_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ + + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ + + uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . + This parameter must be a value of @ref FLASHEx_Banks */ + + uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not + when RDP level decreased from Level 1 to Level 0 or during a mass erase. + This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */ + + uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). + This parameter must be a value between begin and end of a bank */ + + uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). + This parameter must be a value between PCROP Start address and end of a bank */ + + uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 + or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ + + uint32_t BootAddr0; /*!< Boot Address 0. + This parameter must be a value between begin and end of a bank */ + + uint32_t BootAddr1; /*!< Boot Address 1. + This parameter must be a value between begin and end of a bank */ +#if defined(DUAL_CORE) + uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1 + or both. + This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ + + uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0. + This parameter must be a value between begin and end of a bank */ + + uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1. + This parameter must be a value between begin and end of a bank */ +#endif /*DUAL_CORE*/ + + uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not + when RDP level decreased from Level 1 to Level 0 or during a mass erase. + This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ + + uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. + This parameter must be a value between begin address and end address of bank1 */ + + uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. + This parameter must be a value between Secure Area Start address and end address of a bank1 */ + +#if defined (FLASH_OTPBL_LOCKBL) + uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. + This parameter must be a value of @ref FLASHEx_OTP_Blocks */ +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM. + This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost. + This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeCRC; /*!< CRC Selection Type. + This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ + + uint32_t BurstSize; /*!< CRC Burst Size. + This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ + + uint32_t Bank; /*!< Select bank where CRC computation is enabled. + This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ + + uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation + This parameter must be a value of @ref FLASH_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be computed. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t CRCStartAddr; /*!< CRC Start address. + This parameter must be a value between begin address and end address of a bank */ + + uint32_t CRCEndAddr; /*!< CRC End address. + This parameter must be a value between CRC Start address and end address of a bank */ + +} FLASH_CRCInitTypeDef; + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */ +/** + * @} + */ + +#if defined (FLASH_CR_PSIZE) +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */ +#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ +#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ +#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ +/** + * @} + */ +#endif /* FLASH_CR_PSIZE */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ +#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ +#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ +#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ +#if defined (DUAL_CORE) +#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */ +#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */ +#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */ +#else /* Single core */ +#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ +#endif /*DUAL_CORE*/ +#if defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */ +#endif /* FLASH_OTPBL_LOCKBL */ +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (DUAL_CORE) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */ +#elif defined (FLASH_OTPBL_LOCKBL) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */ +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */ +#else +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ + OPTIONBYTE_BOOTADD) /*!< All option byte configuration */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 0xAA00U +#define OB_RDP_LEVEL_1 0x5500U +#define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */ +#define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ +#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ +#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ +#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ +/** + * @} + */ + + + +/** @defgroup FLASHEx_Boot_Address FLASH Boot Address + * @{ + */ +#define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ +#define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ + +/* Unused FLASH Latency defines */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ +/** + * @} + */ + +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 0x01U /*!< Bank 1 */ +#if defined (DUAL_BANK) +#define FLASH_BANK_2 0x02U /*!< Bank 2 */ +#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ +#endif /* DUAL_BANK */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP + * @{ + */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 or during a mass erase */ +#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 128) +#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ +#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ +#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ +#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ +#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ +#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ +#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ +#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ +#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ +#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ +#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ +#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ +#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ +#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ +#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ +#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ +#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ +#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ +#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ +#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ +#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ +#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ +#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ +#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ +#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ +#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ +#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ +#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ +#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ +#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ +#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ +#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ +#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ +#else +#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ +#endif /* FLASH_SECTOR_TOTAL == 128 */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY + * @{ + */ +#define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */ +#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE + * @{ + */ +#define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ +#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7 + * @{ + */ +#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */ +#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */ + +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4 + * @{ + */ +#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */ +#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */ +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW + * @{ + */ +#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */ +#define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW + * @{ + */ +#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/ +#define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/ +/** + * @} + */ +#endif + +/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1 + * @{ + */ +#define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */ +#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1 + * @{ + */ +#define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */ +#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */ +/** + * @} + */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) +/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2 + * @{ + */ +#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */ +#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2 + * @{ + */ +#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */ +#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */ +/** + * @} + */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) +/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK + * @{ + */ +#define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ +#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */ +/** + * @} + */ +#endif /* DUAL_BANK */ + +/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV + * @{ + */ +#define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ +#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ +/** + * @} + */ + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV + * @{ + */ +#define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */ +#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */ +/** + * @} + */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST + * @{ + */ +#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */ +#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED + * @{ + */ +#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */ +#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */ +/** + * @} + */ +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + + /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type + * @{ + */ +#define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */ +#define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/ +#define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/ +#define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */ +#define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ +#define OB_USER_SECURITY 0x0040U /*!< security selection */ +#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ +#if defined (DUAL_BANK) +#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ +#endif /* DUAL_BANK */ +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */ +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ +#if defined (DUAL_CORE) +#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ +#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ +#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ +#endif /*DUAL_CORE*/ +#if defined (FLASH_OPTSR_NRST_STOP_D2) +#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */ +#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */ +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_CORE) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#elif defined (FLASH_OPTSR_VDDMMC_HSLV) +#if defined (DUAL_BANK) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ + OB_USER_VDDMMC_HSLV) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_VDDMMC_HSLV) +#endif /* DUAL_BANK */ +#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) +#else /* Single core */ +#if defined (DUAL_BANK) +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV ) +#endif /* DUAL_BANK */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION + * @{ + */ +#define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ +#define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ +#define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ +/** + * @} + */ + +/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP + * @{ + */ +#define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level + is decreased from Level 1 to Level 0 or during a mass erase */ +#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase) */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type + * @{ + */ +#define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ +#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ +#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */ +/** + * @} + */ + +/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size + * @{ + */ +#define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */ +#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */ +/** + * @} + */ + +/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay + * @{ + */ +#define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */ +#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */ +#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */ +#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ +/** + * @} + */ + +#if defined (FLASH_OTPBL_LOCKBL) +/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks + * @{ + */ +#define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ +#define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ +#define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ +#define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ +#define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ +#define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ +#define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ +#define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ +#define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ +#define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ +#define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ +#define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ +#define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ +#define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ +#define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ +#define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ +#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */ +/** + * @} + */ +#endif /* FLASH_OTPBL_LOCKBL */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Address + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) + +#if defined (FLASH_CR_PSIZE) +/** + * @brief Set the FLASH Program/Erase parallelism. + * @param __PSIZE__ FLASH Program/Erase parallelism + * This parameter can be a value of @ref FLASH_Program_Parallelism + * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) + * @retval none + */ +#if defined (DUAL_BANK) +#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ + MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ + MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) +#else +#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) +#endif /* DUAL_BANK */ + +/** + * @brief Get the FLASH Program/Erase parallelism. + * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2) + * @retval FLASH Program/Erase parallelism + * This return value can be a value of @ref FLASH_Program_Parallelism + */ +#if defined (DUAL_BANK) +#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ + READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ + READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) +#else +#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) +#endif /* DUAL_BANK */ + +#endif /* FLASH_CR_PSIZE */ + +/** + * @brief Set the FLASH Programming Delay. + * @param __DELAY__ FLASH Programming Delay + * This parameter can be a value of @ref FLASHEx_Programming_Delay + * @retval none + */ +#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) + +/** + * @brief Get the FLASH Programming Delay. + * @retval FLASH Programming Delay + * This return value can be a value of @ref FLASHEx_Programming_Delay + */ +#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) + /** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Program operation functions *************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); +#if defined (DUAL_BANK) +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); +#endif /* DUAL_BANK */ + +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ + +/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#if defined (FLASH_CR_PSIZE) +#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) +#endif /* FLASH_CR_PSIZE */ + +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ + (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) + +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ + ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) + +#if (FLASH_SECTOR_TOTAL == 8U) +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#else +#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U) +#endif /* FLASH_SECTOR_TOTAL == 8U */ + +#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ + ((CONFIG) == OB_PCROP_RDP_ERASE)) + +#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ + ((CONFIG) == OB_SECURE_RDP_ERASE)) + +#if defined (DUAL_BANK) +#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) +#endif /* DUAL_BANK */ + +#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) +#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE)) +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + +#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) +#if defined (DUAL_CORE) +#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW)) +#endif /* DUAL_CORE */ +#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) + +#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \ + ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) + +#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) + +#if defined (DUAL_CORE) +#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE)) + +#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE)) +#endif /* DUAL_CORE */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) +#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2)) + +#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2)) +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \ + ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB)) +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE)) +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ + (((TYPE) & ~OB_USER_ALL) == 0U)) + +#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ + ((VALUE) == OB_BOOT_ADD1) || \ + ((VALUE) == OB_BOOT_ADD_BOTH)) + +#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ + ((VALUE) == FLASH_CRC_SECTORS) || \ + ((VALUE) == FLASH_CRC_BANK)) + +#if defined (FLASH_OTPBL_LOCKBL) +#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U)) +#endif /* FLASH_OTPBL_LOCKBL */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_FLASH_EX_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h new file mode 100644 index 0000000..1cd9178 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h @@ -0,0 +1,359 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_GPIO_H +#define STM32H7xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< High speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) + +#if defined(DUAL_CORE) +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__)) +#endif + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32h7xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_GPIO_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h new file mode 100644 index 0000000..7a8edd3 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h @@ -0,0 +1,487 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_GPIO_EX_H +#define STM32H7xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ + +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ +#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */ +#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_D2PWREN ((uint8_t)0x00) /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */ +#if defined(DUAL_CORE) +#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */ +#endif /* DUAL_CORE */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ +#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */ +#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#if defined(SAI4) +#define GPIO_AF1_SAI4 ((uint8_t)0x01) /* SAI4 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* SAI4 */ +#define GPIO_AF1_FMC ((uint8_t)0x01) /* FMC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ + + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ +#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */ +#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */ +#if defined(HRTIM1) +#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(FDCAN3) +#define GPIO_AF2_FDCAN3 ((uint8_t)0x02) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */ +#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */ +#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */ +#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */ +#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF3_OCTOSPIM_P1 ((uint8_t)0x03) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF3_OCTOSPIM_P2 ((uint8_t)0x03) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#if defined(HRTIM1) +#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */ +#endif /* HRTIM1 */ +#define GPIO_AF3_LTDC ((uint8_t)0x03) /* LTDC Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ +#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#if defined(USART10) +#define GPIO_AF4_USART10 ((uint8_t)0x04) /* USART10 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /*USART10*/ +#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF4_DFSDM2 ((uint8_t)0x04) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#if defined(PSSI) +#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#if defined(OCTOSPIM) +#define GPIO_AF4_OCTOSPIM_P1 ((uint8_t)0x04) /* OCTOSPI Manager Port 1 Alternate Function mapping : available on STM32H72xxx/STM32H73xxx */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ +#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */ +#if defined(FDCAN3) +#define GPIO_AF5_FDCAN3 ((uint8_t)0x05) /* FDCAN3 Alternate Function mapping */ +#endif /*FDCAN3*/ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ +#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */ +#if defined(I2C5) +#define GPIO_AF6_I2C5 ((uint8_t)0x06) /* I2C5 Alternate Function mapping */ +#endif /* I2C5*/ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */ +#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(SAI3) +#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */ +#endif /* SAI3 */ +#if defined(OCTOSPIM) +#define GPIO_AF6_OCTOSPIM_P1 ((uint8_t)0x06) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */ +#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ +#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */ +#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */ +#if defined(SAI2) +#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */ +#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */ +#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ +#if defined(SAI4) +#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ +#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ +#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */ +#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */ +#if defined(QUADSPI) +#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if defined(OCTOSPIM) +#define GPIO_AF9_OCTOSPIM_P1 ((uint8_t)0x09) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#define GPIO_AF9_OCTOSPIM_P2 ((uint8_t)0x09) /* OCTOSPI Manager Port 2 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 10 selection + */ +#if defined(SAI2) +#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ +#endif /*SAI2*/ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */ +#if defined(USB2_OTG_FS) +#define GPIO_AF10_OTG2_FS ((uint8_t)0x0A) /* OTG2_FS Alternate Function mapping */ +#endif /*USB2_OTG_FS*/ +#define GPIO_AF10_COMP1 ((uint8_t)0x0A) /* COMP1 Alternate Function mapping */ +#define GPIO_AF10_COMP2 ((uint8_t)0x0A) /* COMP2 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#define GPIO_AF10_CRS_SYNC ((uint8_t)0x0A) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */ +#if defined(QUADSPI) +#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QUADSPI Alternate Function mapping */ +#endif /* QUADSPI */ +#if defined(SAI4) +#define GPIO_AF10_SAI4 ((uint8_t)0x0A) /* SAI4 Alternate Function mapping */ +#endif /* SAI4 */ +#if !defined(USB2_OTG_FS) +#define GPIO_AF10_OTG1_FS ((uint8_t)0x0A) /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /* !USB2_OTG_FS */ +#define GPIO_AF10_OTG1_HS ((uint8_t)0x0A) /* OTG1_HS Alternate Function mapping */ +#if defined(OCTOSPIM) +#define GPIO_AF10_OCTOSPIM_P1 ((uint8_t)0x0A) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ +#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */ +#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */ +#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */ +#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */ +#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */ +#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */ +#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */ +#if defined(DFSDM2_BASE) +#define GPIO_AF11_DFSDM2 ((uint8_t)0x0B) /* DFSDM2 Alternate Function mapping */ +#endif /* DFSDM2_BASE */ +#if defined(USART10) +#define GPIO_AF11_USART10 ((uint8_t)0x0B) /* USART10 Alternate Function mapping */ +#endif /* USART10 */ +#if defined(UART9) +#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ +#endif /* UART9 */ +#if defined(ETH) +#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */ +#endif /* ETH */ +#if defined(LTDC) +#define GPIO_AF11_LTDC ((uint8_t)0x0B) /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx and STM32H72xxx/STM32H73xxx */ +#endif /*LTDC*/ +#if defined(OCTOSPIM) +#define GPIO_AF11_OCTOSPIM_P1 ((uint8_t)0x0B) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_MDIOS ((uint8_t)0x0C) /* MDIOS Alternate Function mapping */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ +#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */ +#define GPIO_AF12_TIM8 ((uint8_t)0x0C) /* TIM8 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF12_LTDC ((uint8_t)0x0C) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(USB2_OTG_FS) +#define GPIO_AF12_OTG1_FS ((uint8_t)0x0C) /* OTG1_FS Alternate Function mapping */ +#endif /* USB2_OTG_FS */ +#if defined(OCTOSPIM) +#define GPIO_AF12_OCTOSPIM_P1 ((uint8_t)0x0C) /* OCTOSPI Manager Port 1 Alternate Function mapping */ +#endif /* OCTOSPIM */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */ +#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */ +#if defined(LTDC) +#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */ +#endif /*LTDC*/ +#if defined(DSI) +#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ +#endif /* DSI */ +#if defined(PSSI) +#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */ +#endif /* PSSI */ +#define GPIO_AF13_TIM1 ((uint8_t)0x0D) /* TIM1 Alternate Function mapping */ +#if defined(TIM23) +#define GPIO_AF13_TIM23 ((uint8_t)0x0D) /* TIM23 Alternate Function mapping */ +#endif /*TIM23*/ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */ +#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */ +#if defined(TIM24) +#define GPIO_AF14_TIM24 ((uint8_t)0x0E) /* TIM24 Alternate Function mapping */ +#endif /*TIM24*/ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @brief GPIO pin available on the platform + */ +/* Defines the available pins per GPIOs */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_All +#define GPIOE_PIN_AVAILABLE GPIO_PIN_All +#define GPIOF_PIN_AVAILABLE GPIO_PIN_All +#define GPIOG_PIN_AVAILABLE GPIO_PIN_All +#if defined(GPIOI) +#define GPIOI_PIN_AVAILABLE GPIO_PIN_All +#endif /*GPIOI*/ +#if defined(GPIOI) +#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All +#else +#define GPIOJ_PIN_AVAILABLE (GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 ) +#endif /* GPIOI */ +#define GPIOH_PIN_AVAILABLE GPIO_PIN_All +#if defined(GPIOI) +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) +#else +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 ) +#endif /* GPIOI */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined(GPIOI) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ + ((__GPIOx__) == (GPIOH))? 7UL :\ + ((__GPIOx__) == (GPIOI))? 8UL :\ + ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\ + ((__GPIOx__) == (GPIOB))? 1UL :\ + ((__GPIOx__) == (GPIOC))? 2UL :\ + ((__GPIOx__) == (GPIOD))? 3UL :\ + ((__GPIOx__) == (GPIOE))? 4UL :\ + ((__GPIOx__) == (GPIOF))? 5UL :\ + ((__GPIOx__) == (GPIOG))? 6UL :\ + ((__GPIOx__) == (GPIOH))? 7UL :\ + ((__GPIOx__) == (GPIOJ))? 9UL : 10UL) +#endif /* GPIOI */ + +/** + * @} + */ + +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_GPIO_EX_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h new file mode 100644 index 0000000..7c853ca --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h @@ -0,0 +1,319 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hcd.h + * @author MCD Application Team + * @brief Header file of HCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_HCD_H +#define STM32H7xx_HAL_HCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_usb.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HCD HCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Types HCD Exported Types + * @{ + */ + +/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition + * @{ + */ +typedef enum +{ + HAL_HCD_STATE_RESET = 0x00, + HAL_HCD_STATE_READY = 0x01, + HAL_HCD_STATE_ERROR = 0x02, + HAL_HCD_STATE_BUSY = 0x03, + HAL_HCD_STATE_TIMEOUT = 0x04 +} HCD_StateTypeDef; + +typedef USB_OTG_GlobalTypeDef HCD_TypeDef; +typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; +typedef USB_OTG_HCTypeDef HCD_HCTypeDef; +typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; +typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; +/** + * @} + */ + +/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +typedef struct __HCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +{ + HCD_TypeDef *Instance; /*!< Register base address */ + HCD_InitTypeDef Init; /*!< HCD required parameters */ + HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ + HAL_LockTypeDef Lock; /*!< HCD peripheral status */ + __IO HCD_StateTypeDef State; /*!< HCD communication state */ + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ + void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ + void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ + void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ + void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ + void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ + + void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ + void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +} HCD_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Constants HCD Exported Constants + * @{ + */ + +/** @defgroup HCD_Speed HCD Speed + * @{ + */ +#define HCD_SPEED_HIGH USBH_HS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ + +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ +#define HCD_DEVICE_SPEED_HIGH 0U +#define HCD_DEVICE_SPEED_FULL 1U +#define HCD_DEVICE_SPEED_LOW 2U +/** + * @} + */ + +/** @defgroup HCD_PHY_Module HCD PHY Module + * @{ + */ +#define HCD_PHY_ULPI 1U +#define HCD_PHY_EMBEDDED 2U +/** + * @} + */ + +/** @defgroup HCD_Error_Code_definition HCD Error Code definition + * @brief HCD Error Code definition + * @{ + */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HCD_Exported_Macros HCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) +#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); + +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); +void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); +void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition + * @brief HAL USB OTG HCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ + HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ + HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ + HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ + HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ + + HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ + HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ + +} HAL_HCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition + * @brief HAL USB OTG HCD Callback pointer definition + * @{ + */ + +typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ +typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, + uint8_t epnum, + HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ +/** + * @} + */ + +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); + +/* Non-Blocking mode: Interrupt */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, + HCD_URBStateTypeDef urb_state); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd); +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HCD_Private_Macros HCD Private Macros + * @{ + */ +/** + * @} + */ +/* Private functions prototypes ----------------------------------------------*/ + +/** + * @} + */ +/** + * @} + */ +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_HCD_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h new file mode 100644 index 0000000..45f6e07 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_HSEM_H +#define STM32H7xx_HAL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HSEM + * @{ + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** + * @brief SemID to mask helper Macro. + * @param __SEMID__: semaphore ID from 0 to 31 + * @retval Semaphore Mask. + */ +#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) + +/** + * @brief Enables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1IER |= (__SEM_MASK__)) : \ + (HSEM->C2IER |= (__SEM_MASK__))) +#else +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) +#endif /* DUAL_CORE */ +/** + * @brief Disables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1IER &= ~(__SEM_MASK__)) : \ + (HSEM->C2IER &= ~(__SEM_MASK__))) +#else +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) +#endif /* DUAL_CORE */ + +/** + * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where an interrupt occurred. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + ((__SEM_MASK__) & HSEM->C1MISR) : \ + ((__SEM_MASK__) & HSEM->C2MISR1)) +#else +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) +#endif /* DUAL_CORE */ + +/** + * @brief Get the semaphores release status flags. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where Release flags rise. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (__SEM_MASK__) & HSEM->C1ISR : \ + (__SEM_MASK__) & HSEM->C2ISR) +#else +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) +#endif /* DUAL_CORE */ + +/** + * @brief Clears the HSEM Interrupt flags. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined(DUAL_CORE) +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ + (HSEM->C1ICR |= (__SEM_MASK__)) : \ + (HSEM->C2ICR |= (__SEM_MASK__))) +#else +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * @{ + */ + +/* HSEM semaphore take (lock) using 2-Step method ****************************/ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID); +/* HSEM semaphore fast take (lock) using 1-Step method ***********************/ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID); +/* HSEM Release **************************************************************/ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID); +/* HSEM Release All************************************************************/ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID); +/* HSEM Check semaphore state Taken or not **********************************/ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); + +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * @{ + */ +/* HSEM Set Clear Key *********************************************************/ +void HAL_HSEM_SetClearKey(uint32_t Key); +/* HSEM Get Clear Key *********************************************************/ +uint32_t HAL_HSEM_GetClearKey(void); +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group3 + * @brief HSEM Notification functions + * @{ + */ +/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/ +void HAL_HSEM_ActivateNotification(uint32_t SemMask); +/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask); +/* HSEM Free Callback (When a semaphore is released) *******************************/ +void HAL_HSEM_FreeCallback(uint32_t SemMask); +/* HSEM IRQ Handler **********************************************************/ +void HAL_HSEM_IRQHandler(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HSEM_Private_Macros HSEM Private Macros + * @{ + */ + +#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX ) + +#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX ) + +#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX ) + +#if defined(DUAL_CORE) +#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \ + ((__COREID__) == HSEM_CPU2_COREID)) +#else +#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID) +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_HSEM_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h new file mode 100644 index 0000000..f706250 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h @@ -0,0 +1,839 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_I2C_H +#define STM32H7xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32h7xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START)) & \ + (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_I2C_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h new file mode 100644 index 0000000..e701b8b --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h @@ -0,0 +1,175 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_I2C_EX_H +#define STM32H7xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#if defined(SYSCFG_PMCR_I2C5_FMP) +#define I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus on I2C5 pins */ +#else +#define I2C_FASTMODEPLUS_I2C5 (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported */ +#endif /* SYSCFG_PMCR_I2C5_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_I2C_EX_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h new file mode 100644 index 0000000..d2ecdf8 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h @@ -0,0 +1,653 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_jpeg.h + * @author MCD Application Team + * @brief Header file of JPEG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_JPEG_H +#define STM32H7xx_HAL_JPEG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined (JPEG) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup JPEG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup JPEG_Exported_Types JPEG Exported Types + * @{ + */ + +/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition + * @brief JPEG encoding configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK + This parameter can be a value of @ref JPEG_ColorSpace */ + + uint32_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0 + This parameter can be a value of @ref JPEG_ChromaSubsampling */ + + uint32_t ImageHeight; /*!< Image height : number of lines */ + + uint32_t ImageWidth; /*!< Image width : number of pixels per line */ + + uint32_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */ + +} JPEG_ConfTypeDef; +/** + * @} + */ + +/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition + * @brief HAL JPEG State structure definition + * @{ + */ +typedef enum +{ + HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */ + HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */ + HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */ + HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */ + HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */ + HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */ + HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */ +} HAL_JPEG_STATETypeDef; + +/** + * @} + */ + + +/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition + * @brief JPEG handle Structure definition + * @{ + */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +typedef struct __JPEG_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */ +{ + JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */ + + JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */ + + uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */ + + uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */ + + __IO uint32_t JpegInCount; /*!< Internal Counter of input data */ + + __IO uint32_t JpegOutCount; /*!< Internal Counter of output data */ + + uint32_t InDataLength; /*!< Input Buffer Length in Bytes */ + + uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */ + + MDMA_HandleTypeDef *hdmain; /*!< JPEG In MDMA handle parameters */ + + MDMA_HandleTypeDef *hdmaout; /*!< JPEG Out MDMA handle parameters */ + + uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */ + + uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */ + + uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */ + + uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */ + + uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */ + + HAL_LockTypeDef Lock; /*!< JPEG locking object */ + + __IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */ + + __IO uint32_t ErrorCode; /*!< JPEG Error code */ + + __IO uint32_t Context; /*!< JPEG Internal context */ + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, + JPEG_ConfTypeDef *pInfo); /*!< JPEG Info ready callback */ + void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Encode complete callback */ + void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Decode complete callback */ + void (*ErrorCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Error callback */ + void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg, + uint32_t NbDecodedData); /*!< JPEG Get Data callback */ + void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, + uint32_t OutDataLength); /*!< JPEG Data ready callback */ + + void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg); /*!< JPEG Msp Init callback */ + void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef + *hjpeg); /*!< JPEG Msp DeInit callback */ + + +#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */ + + +} JPEG_HandleTypeDef; +/** + * @} + */ + + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +/** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition + * @brief HAL JPEG Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_JPEG_ENCODE_CPLT_CB_ID = 0x01U, /*!< JPEG Encode Complete callback ID */ + HAL_JPEG_DECODE_CPLT_CB_ID = 0x02U, /*!< JPEG Decode Complete callback ID */ + HAL_JPEG_ERROR_CB_ID = 0x03U, /*!< JPEG Error callback ID */ + + HAL_JPEG_MSPINIT_CB_ID = 0x04U, /*!< JPEG MspInit callback ID */ + HAL_JPEG_MSPDEINIT_CB_ID = 0x05U /*!< JPEG MspDeInit callback ID */ + +} HAL_JPEG_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition + * @brief HAL JPEG Callback pointer definition + * @{ + */ +typedef void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg); /*!< pointer to a common JPEG callback function */ +typedef void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, + JPEG_ConfTypeDef *pInfo); /*!< pointer to an Info ready JPEG callback function */ +typedef void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, + uint32_t NbDecodedData); /*!< pointer to a Get data JPEG callback function */ +typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, + uint32_t OutDataLength); /*!< pointer to a Data ready JPEG callback function */ +/** + * @} + */ + +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup JPEG_Exported_Constants JPEG Exported Constants + * @{ + */ + +/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition + * @brief JPEG Error Code definition + * @{ + */ + +#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */ +#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */ +#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ +#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +#define HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size + * @brief JPEG Quantization Table Size + * @{ + */ +#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes */ +/** + * @} + */ + + +/** @defgroup JPEG_ColorSpace JPEG ColorSpace + * @brief JPEG Color Space + * @{ + */ +#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U) +#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0 +#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE + + +/** + * @} + */ + + +/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling + * @brief JPEG Chrominance Sampling + * @{ + */ +#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */ +#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */ +#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */ + +/** + * @} + */ + +/** @defgroup JPEG_ImageQuality JPEG Image Quality + * @brief JPEG Min and Max Image Quality + * @{ + */ +#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */ +#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */ + +/** + * @} + */ + +/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition + * @brief JPEG Interrupt definition + * @{ + */ +#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */ +#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */ +#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */ +#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */ +#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */ +#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */ +/** + * @} + */ + +/** @defgroup JPEG_Flag_definition JPEG Flag definition + * @brief JPEG Flags definition + * @{ + */ +#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */ +#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */ +#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */ +#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */ +#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */ +#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */ +#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/ + +#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/ +/** + * @} + */ + +/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition + * @brief JPEG process pause, resume definition + * @{ + */ +#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/ +#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/ +#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup JPEG_Exported_Macros JPEG Exported Macros + * @{ + */ + +/** @brief Reset JPEG handle state + * @param __HANDLE__ specifies the JPEG handle. + * @retval None + */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET) +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + +/** + * @brief Enable the JPEG peripheral. + * @param __HANDLE__ specifies the JPEG handle. + * @retval None + */ +#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN) + +/** + * @brief Disable the JPEG peripheral. + * @param __HANDLE__ specifies the JPEG handle. + * @retval None + */ +#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN) + + +/** + * @brief Check the specified JPEG status flag. + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to check + * This parameter can be one of the following values: + * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag + * @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written + * @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold + * @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available + * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process + * and than last data has been sent to the output FIFO + * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers + * and the internal registers have been updated + * @arg JPEG_FLAG_COF : JPEG Codec operation on going flag + * + * @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE) + */ + +#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__))) + +/** + * @brief Clear the specified JPEG status flag. + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to clear + * This parameter can be one of the following values: + * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process + * and than last data has been sent to the output FIFO + * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers + * @retval None + */ + +#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF)))) + + +/** + * @brief Enable Interrupt. + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to enable + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @retval No return + */ +#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) ) + +/** + * @brief Disable Interrupt. + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to disable + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits + * located in the same IT enable register (CR register). + * @retval No return + */ +#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL) + + +/** + * @brief Get Interrupt state. + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to check + * This parameter can be one of the following values: + * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt + * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt + * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt + * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt + * @arg JPEG_IT_EOC : End of Conversion Interrupt + * @arg JPEG_IT_HPD : Header Parsing Done Interrupt + * + * @retval returns The new state of __INTERRUPT__ (Enabled or disabled) + */ +#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup JPEG_Exported_Functions + * @{ + */ + +/** @addtogroup JPEG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg); + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, + pJPEG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_InfoReadyCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg); + +HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg); + +HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_DataReadyCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg); + +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group2 + * @{ + */ +/* Encoding/Decoding Configuration functions ********************************/ +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf); +HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); +HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg); +HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, + uint8_t *QTable2, uint8_t *QTable3); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group3 + * @{ + */ +/* JPEG processing functions **************************************/ +HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout); +HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout); +HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); +HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); +void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength); +void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength); +HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group4 + * @{ + */ +/* JPEG Decode/Encode callback functions ********************************************************/ +void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); +void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg); +void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData); +void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group5 + * @{ + */ +/* JPEG IRQ handler management ******************************************************/ +void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** @addtogroup JPEG_Exported_Functions_Group6 + * @{ + */ +/* Peripheral State and Error functions ************************************************/ +HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg); +uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup JPEG_Private_Types JPEG Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup JPEG_Private_Defines JPEG Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Variables JPEG Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Constants JPEG Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup JPEG_Private_Macros JPEG Private Macros + * @{ + */ + +#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \ + ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \ + ((SUBSAMPLING) == JPEG_422_SUBSAMPLING)) + +#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX)) + +#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \ + ((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \ + ((COLORSPACE) == JPEG_CMYK_COLORSPACE)) + +#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \ + ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \ + ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup JPEG_Private_Functions JPEG Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* JPEG */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_JPEG_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h new file mode 100644 index 0000000..0eaa415 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h @@ -0,0 +1,719 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_ltdc.h + * @author MCD Application Team + * @brief Header file of LTDC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_LTDC_H +#define STM32H7xx_HAL_LTDC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined (LTDC) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Types LTDC Exported Types + * @{ + */ +#define MAX_LAYER 2U + +/** + * @brief LTDC color structure definition + */ +typedef struct +{ + uint8_t Blue; /*!< Configures the blue value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Green; /*!< Configures the green value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Red; /*!< Configures the red value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint8_t Reserved; /*!< Reserved 0xFF */ +} LTDC_ColorTypeDef; + +/** + * @brief LTDC Init structure definition + */ +typedef struct +{ + uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. + This parameter can be one value of @ref LTDC_HS_POLARITY */ + + uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. + This parameter can be one value of @ref LTDC_VS_POLARITY */ + + uint32_t DEPolarity; /*!< configures the data enable polarity. + This parameter can be one of value of @ref LTDC_DE_POLARITY */ + + uint32_t PCPolarity; /*!< configures the pixel clock polarity. + This parameter can be one of value of @ref LTDC_PC_POLARITY */ + + uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. + This parameter must be a number between + Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + + uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. + This parameter must be a number between + Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + + uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. + This parameter must be a number between + Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + + uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. + This parameter must be a number between + Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + + uint32_t TotalWidth; /*!< configures the total width. + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + + uint32_t TotalHeigh; /*!< configures the total height. + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ +} LTDC_InitTypeDef; + +/** + * @brief LTDC Layer structure definition + */ +typedef struct +{ + uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ + + uint32_t WindowY0; /*!< Configures the Window vertical Start Position. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x7FF. */ + + uint32_t PixelFormat; /*!< Specifies the pixel format. + This parameter can be one of value of @ref LTDC_Pixelformat */ + + uint32_t Alpha; /*!< Specifies the constant alpha used for blending. + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t Alpha0; /*!< Configures the default alpha value. + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ + + uint32_t BlendingFactor1; /*!< Select the blending factor 1. + This parameter can be one of value of @ref LTDC_BlendingFactor1 */ + + uint32_t BlendingFactor2; /*!< Select the blending factor 2. + This parameter can be one of value of @ref LTDC_BlendingFactor2 */ + + uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ + + uint32_t ImageWidth; /*!< Configures the color frame buffer line length. + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + + uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ + + LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ +} LTDC_LayerCfgTypeDef; + +/** + * @brief HAL LTDC State structures definition + */ +typedef enum +{ + HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ + HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ + HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ + HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ + HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ +} HAL_LTDC_StateTypeDef; + +/** + * @brief LTDC handle Structure definition + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +typedef struct __LTDC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +{ + LTDC_TypeDef *Instance; /*!< LTDC Register base address */ + + LTDC_InitTypeDef Init; /*!< LTDC parameters */ + + LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ + + HAL_LockTypeDef Lock; /*!< LTDC Lock */ + + __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ + + __IO uint32_t ErrorCode; /*!< LTDC Error code */ + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ + void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ + void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ + + void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ + void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + +} LTDC_HandleTypeDef; + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LTDC Callback ID enumeration definition + */ +typedef enum +{ + HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ + HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ + + HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ + HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ + HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ + +} HAL_LTDC_CallbackIDTypeDef; + +/** + * @brief HAL LTDC Callback pointer definition + */ +typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */ + +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Constants LTDC Exported Constants + * @{ + */ + +/** @defgroup LTDC_Error_Code LTDC Error Code + * @{ + */ +#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ +#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ +#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ +#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup LTDC_Layer LTDC Layer + * @{ + */ +#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ +#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ +/** + * @} + */ + +/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY + * @{ + */ +#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ +#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY + * @{ + */ +#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ +#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY + * @{ + */ +#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ +#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ +/** + * @} + */ + +/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY + * @{ + */ +#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ +#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ +/** + * @} + */ + +/** @defgroup LTDC_SYNC LTDC SYNC + * @{ + */ +#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ +#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ +/** + * @} + */ + +/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR + * @{ + */ +#define LTDC_COLOR 0x000000FFU /*!< Color mask */ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 + * @{ + */ +#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 + * @{ + */ +#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ +#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ +/** + * @} + */ + +/** @defgroup LTDC_Pixelformat LTDC Pixel format + * @{ + */ +#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ +#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ +/** + * @} + */ + +/** @defgroup LTDC_Alpha LTDC Alpha + * @{ + */ +#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ +/** + * @} + */ + +/** @defgroup LTDC_LAYER_Config LTDC LAYER Config + * @{ + */ +#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ +#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ + +#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ +#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ +/** + * @} + */ + +/** @defgroup LTDC_Interrupts LTDC Interrupts + * @{ + */ +#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ +#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ +#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ +#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ +/** + * @} + */ + +/** @defgroup LTDC_Flags LTDC Flags + * @{ + */ +#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ +#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ +#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ +#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ +/** + * @} + */ + +/** @defgroup LTDC_Reload_Type LTDC Reload Type + * @{ + */ +#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ +#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LTDC_Exported_Macros LTDC Exported Macros + * @{ + */ + +/** @brief Reset LTDC handle state. + * @param __HANDLE__ LTDC handle + * @retval None + */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) +#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @brief Enable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) + +/** + * @brief Disable the LTDC. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) + +/** + * @brief Enable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + |= (uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Disable the LTDC Layer. + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled. + * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval None. + */ +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + &= ~(uint32_t)LTDC_LxCR_LEN) + +/** + * @brief Reload immediately all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) + +/** + * @brief Reload during vertical blanking period all LTDC Layers. + * @param __HANDLE__ LTDC handle + * @retval None. + */ +#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) + +/* Interrupt & Flag management */ +/** + * @brief Get the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) + +/** + * @brief Clears the LTDC pending flags. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Specify the flag to clear. + * This parameter can be any combination of the following values: + * @arg LTDC_FLAG_LI: Line Interrupt flag + * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag + * @arg LTDC_FLAG_TE: Transfer Error interrupt flag + * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified LTDC interrupts. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval None + */ +#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified LTDC interrupt has occurred or not. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ Specify the LTDC interrupt source to check. + * This parameter can be one of the following values: + * @arg LTDC_IT_LI: Line Interrupt flag + * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag + * @arg LTDC_IT_TE: Transfer Error interrupt flag + * @arg LTDC_IT_RR: Register Reload Interrupt Flag + * @retval The state of INTERRUPT (SET or RESET). + */ +#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) +/** + * @} + */ + +/* Include LTDC HAL Extension module */ +#include "stm32h7xx_hal_ltdc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDC_Exported_Functions + * @{ + */ +/** @addtogroup LTDC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); + +/** + * @} + */ + +/** @addtogroup LTDC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Macros LTDC Private Macros + * @{ + */ +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ + ((uint32_t)((__HANDLE__)->Instance))\ + + 0x84U + (0x80U*(__LAYER__))))) +#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ + || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ + || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ + || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ + || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) +#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) +#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) +#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) +#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) +#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) +#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ + ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) +#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) +#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) +#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) +#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) +#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ + ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_LTDC_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h new file mode 100644 index 0000000..15e9adf --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc_ex.h @@ -0,0 +1,83 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_ltdc_ex.h + * @author MCD Application Team + * @brief Header file of LTDC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_LTDC_EX_H +#define STM32H7xx_HAL_LTDC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined (LTDC) && defined (DSI) + +#include "stm32h7xx_hal_dsi.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup LTDCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LTDCEx_Exported_Functions + * @{ + */ + +/** @addtogroup LTDCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg); +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_LTDC_EX_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h new file mode 100644 index 0000000..a39cc0d --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h @@ -0,0 +1,868 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_mdma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_MDMA_H +#define STM32H7xx_HAL_MDMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup MDMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Types MDMA Exported Types + * @brief MDMA Exported Types + * @{ + */ + +/** + * @brief MDMA Configuration Structure definition + */ +typedef struct +{ + + uint32_t Request; /*!< Specifies the MDMA request. + This parameter can be a value of @ref MDMA_Request_selection*/ + + uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a : + a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer + This parameter can be a value of @ref MDMA_Transfer_TriggerMode */ + + uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx. + This parameter can be a value of @ref MDMA_Priority_level */ + + uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness. + This parameter can be a value of @ref MDMA_Endianness */ + + uint32_t SourceInc; /*!< Specifies if the Source increment mode . + This parameter can be a value of @ref MDMA_Source_increment_mode */ + + uint32_t DestinationInc; /*!< Specifies if the Destination increment mode . + This parameter can be a value of @ref MDMA_Destination_increment_mode */ + + uint32_t SourceDataSize; /*!< Specifies the source data size. + This parameter can be a value of @ref MDMA_Source_data_size */ + + uint32_t DestDataSize; /*!< Specifies the destination data size. + This parameter can be a value of @ref MDMA_Destination_data_size */ + + + uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode. + This parameter can be a value of @ref MDMA_data_Alignment */ + + uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes), + this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/ + + uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref MDMA_Source_burst + @note : the burst may be FIXED/INCR based on SourceInc value , + the BURST must be programmed as to ensure that the burst size will be lower than than + BufferTransferLength */ + + uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref MDMA_Destination_burst + @note : the burst may be FIXED/INCR based on DestinationInc value , + the BURST must be programmed as to ensure that the burst size will be lower than than + BufferTransferLength */ + + int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset + signed value : if > 0 then increment the next block source Address by offset from where the last block ends + if < 0 then decrement the next block source Address by offset from where the last block ends + if == 0, the next block source address starts from where the last block ends + */ + + + int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset + signed value : if > 0 then increment the next block destination Address by offset from where the last block ends + if < 0 then decrement the next block destination Address by offset from where the last block ends + if == 0, the next block destination address starts from where the last block ends + */ + +}MDMA_InitTypeDef; + +/** + * @brief HAL MDMA linked list node structure definition + * @note The Linked list node allows to define a new MDMA configuration + * (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers). + * When CLAR register is configured to a non NULL value , each time a transfer ends, + * a new configuration (linked list node) is automatically loaded from the address given in CLAR register. + */ +typedef struct +{ + __IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */ + __IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */ + __IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */ + __IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */ + __IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */ + __IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */ + __IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */ + __IO uint32_t Reserved; /*!< Reserved register */ + __IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */ + __IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */ + +}MDMA_LinkNodeTypeDef; + +/** + * @brief HAL MDMA linked list node configuration structure definition + * @note used with HAL_MDMA_LinkedList_CreateNode function + */ +typedef struct +{ + MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */ + uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */ + uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */ + uint32_t BlockDataLength; /*!< The data length of a block in bytes */ + uint32_t BlockCount; /*!< The number of blocks to be transferred */ + + uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served. + PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ + + uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served. + PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */ + + +}MDMA_LinkNodeConfTypeDef; + + +/** + * @brief HAL MDMA State structure definition + */ +typedef enum +{ + HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */ + HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */ + HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */ + HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */ + HAL_MDMA_STATE_ABORT = 0x04U, /*!< MDMA Abort state */ + +}HAL_MDMA_StateTypeDef; + +/** + * @brief HAL MDMA Level Complete structure definition + */ +typedef enum +{ + HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */ + HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */ + HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */ + +}HAL_MDMA_LevelCompleteTypeDef; + +/** + * @brief HAL MDMA Callbacks IDs structure definition + */ +typedef enum +{ + HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */ + HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */ + HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */ + HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */ + +}HAL_MDMA_CallbackIDTypeDef; + + +/** + * @brief MDMA handle Structure definition + */ +typedef struct __MDMA_HandleTypeDef +{ + MDMA_Channel_TypeDef *Instance; /*!< Register base address */ + + MDMA_InitTypeDef Init; /*!< MDMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< MDMA locking object */ + + __IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */ + + void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */ + + void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */ + + void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */ + + void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */ + + void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */ + + + MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list + (after the initial node defined by the Init struct) + this parameter is used internally by the MDMA driver + to construct the linked list node + */ + + MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list + this parameter is used internally by the MDMA driver + to construct the linked list node + */ + uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */ + + __IO uint32_t ErrorCode; /*!< MDMA Error code */ + +} MDMA_HandleTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Constants MDMA Exported Constants + * @brief MDMA Exported constants + * @{ + */ + +/** @defgroup MDMA_Error_Codes MDMA Error Codes + * @brief MDMA Error Codes + * @{ + */ +#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */ +#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */ +#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */ +#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */ +#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */ +#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */ +#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ +#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */ +#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */ + +/** + * @} + */ + +/** @defgroup MDMA_Request_selection MDMA Request selection + * @brief MDMA_Request_selection + * @{ + */ + +#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */ +#if defined (LTDC) +#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */ +#endif /* LTDC */ +#if defined (JPEG) +#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */ +#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */ +#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */ +#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */ +#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */ +#endif /* JPEG */ +#if defined (OCTOSPI1) +#define MDMA_REQUEST_OCTOSPI1_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI1_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag */ +#endif /* OCTOSPI1 */ +#if defined (QUADSPI) +#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */ +#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */ +#endif /* QUADSPI */ +#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */ +#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */ + +#if defined (DSI) +#define MDMA_REQUEST_DSI_TEARING_EFFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */ +#define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */ +#endif /* DSI */ + +#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */ + +#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU) /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag */ +#define MDMA_REQUEST_SDMMC1_COMMAND_END ((uint32_t)0x0000001FU) /*!< MDMA HW request is SDMMC1 Command End Flag */ + +#if defined (OCTOSPI2) +#define MDMA_REQUEST_OCTOSPI2_FIFO_TH ((uint32_t)0x00000020U) /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag */ +#define MDMA_REQUEST_OCTOSPI2_TC ((uint32_t)0x00000021U) /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag */ +#endif /* OCTOSPI2 */ + +#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */ + +/** + * @} + */ + +/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode + * @brief MDMA Transfer Trigger Mode + * @{ + */ +#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */ +#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */ +#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ +#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */ + +/** + * @} + */ + +/** @defgroup MDMA_Priority_level MDMA Priority level + * @brief MDMA Priority level + * @{ + */ +#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */ +#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */ +#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */ +#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */ + +/** + * @} + */ + + +/** @defgroup MDMA_Endianness MDMA Endianness + * @brief MDMA Endianness + * @{ + */ +#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */ +#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */ +#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */ +#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode + * @brief MDMA Source increment mode + * @{ + */ +#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ +#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ +#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ +#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode + * @brief MDMA Destination increment mode + * @{ + */ +#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */ +#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits) */ +#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */ +#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits) */ +#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */ +#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits) */ +#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */ +#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits) */ +#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_data_size MDMA Source data size + * @brief MDMA Source data size + * @{ + */ +#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */ +#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */ +#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */ +#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_data_size MDMA Destination data size + * @brief MDMA Destination data size + * @{ + */ +#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */ +#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */ +#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */ +#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */ + +/** + * @} + */ + +/** @defgroup MDMA_data_Alignment MDMA data alignment + * @brief MDMA data alignment + * @{ + */ +#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size + All data are right aligned, in Little Endien mode. */ +#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */ +#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended , + Note : this mode is allowed only if the Source data size is smaller than Destination data size */ +#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */ + +/** + * @} + */ + +/** @defgroup MDMA_Source_burst MDMA Source burst + * @brief MDMA Source burst + * @{ + */ +#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */ +#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */ +#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */ +#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */ +#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */ +#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */ +#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */ + +/** + * @} + */ + +/** @defgroup MDMA_Destination_burst MDMA Destination burst + * @brief MDMA Destination burst + * @{ + */ +#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */ +#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */ +#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */ +#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */ +#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */ +#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */ +#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */ +#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */ + +/** + * @} + */ + +/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions + * @brief MDMA interrupt enable definitions + * @{ + */ +#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */ +#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */ +#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */ +#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */ +#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */ + +/** + * @} + */ + +/** @defgroup MDMA_flag_definitions MDMA flag definitions + * @brief MDMA flag definitions + * @{ + */ +#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */ +#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */ +#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ +#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ +#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ +#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel request Active flag */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup MDMA_Exported_Macros MDMA Exported Macros + * @{ + */ + +/** + * @brief Enable the specified MDMA Channel. + * @param __HANDLE__: MDMA handle + * @retval None + */ +#define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN) + +/** + * @brief Disable the specified MDMA Channel. + * @param __HANDLE__: MDMA handle + * @retval None + */ +#define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN) + +/** + * @brief Get the MDMA Channel pending flags. + * @param __HANDLE__: MDMA handle + * @param __FLAG__: Get the specified flag. + * This parameter can be any combination of the following values: + * @arg MDMA_FLAG_TE : Transfer Error flag. + * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. + * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. + * @arg MDMA_FLAG_BT : Block Transfer complete flag. + * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. + * @arg MDMA_FLAG_CRQA : Channel request Active flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) + +/** + * @brief Clear the MDMA Stream pending flags. + * @param __HANDLE__: MDMA handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg MDMA_FLAG_TE : Transfer Error flag. + * @arg MDMA_FLAG_CTC : Channel Transfer Complete flag. + * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. + * @arg MDMA_FLAG_BT : Block Transfer complete flag. + * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. + * @retval None + */ +#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__)) + +/** + * @brief Enables the specified MDMA Channel interrupts. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval None + */ +#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified MDMA Channel interrupts. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval None + */ +#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified MDMA Channel interrupt is enabled or not. + * @param __HANDLE__: MDMA handle + * @param __INTERRUPT__: specifies the MDMA interrupt source to check. + * @arg MDMA_IT_TE : Transfer Error interrupt mask + * @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask + * @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask + * @arg MDMA_IT_BT : Block Transfer interrupt mask + * @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask + * @retval The state of MDMA_IT (SET or RESET). + */ +#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data in bytes to be transferred on the MDMA Channelx. + * @param __HANDLE__ : MDMA handle + * @param __COUNTER__: Number of data in bytes to be transferred. + * @retval None + */ +#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT)) + +/** + * @brief Returns the number of remaining data in bytes in the current MDMA Channelx transfer. + * @param __HANDLE__ : MDMA handle + * @retval The number of remaining data in bytes in the current MDMA Channelx transfer. + */ +#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MDMA_Exported_Functions MDMA Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData); + +HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)); +HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/* Linked list operation functions ********************************************/ +/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions + * @brief Linked list operation functions + * @{ + */ + +HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); + + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma); +HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma); +void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); +uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MDMA_Private_Types MDMA Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MDMA_Private_Defines MDMA Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Variables MDMA Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Constants MDMA Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MDMA_Private_Macros MDMA Private Macros + * @{ + */ + +#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \ + ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \ + ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \ + ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER )) + + +#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \ + ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \ + ((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \ + ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH)) + +#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \ + ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE)) + + +#if defined (OCTOSPI2) +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC)) +#else +#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END)) +#endif /* OCTOSPI2 */ + +#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \ + ((__INC__) == MDMA_SRC_INC_BYTE ) || \ + ((__INC__) == MDMA_SRC_INC_HALFWORD ) || \ + ((__INC__) == MDMA_SRC_INC_WORD ) || \ + ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \ + ((__INC__) == MDMA_SRC_DEC_BYTE) || \ + ((__INC__) == MDMA_SRC_DEC_HALFWORD) || \ + ((__INC__) == MDMA_SRC_DEC_WORD) || \ + ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD)) + +#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \ + ((__INC__) == MDMA_DEST_INC_BYTE ) || \ + ((__INC__) == MDMA_DEST_INC_HALFWORD ) || \ + ((__INC__) == MDMA_DEST_INC_WORD ) || \ + ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \ + ((__INC__) == MDMA_DEST_DEC_BYTE) || \ + ((__INC__) == MDMA_DEST_DEC_HALFWORD) || \ + ((__INC__) == MDMA_DEST_DEC_WORD) || \ + ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD)) + +#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \ + ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD)) + +#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \ + ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD)) + +#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \ + ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT)) + + +#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \ + ((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \ + ((__BURST__) == MDMA_SOURCE_BURST_128BEATS)) + + +#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \ + ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \ + ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \ + ((__BURST__) == MDMA_DEST_BURST_8BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \ + ((__BURST__) == MDMA_DEST_BURST_128BEATS)) + + #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \ + ((__MODE__) == MDMA_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \ + ((__MODE__) == MDMA_FULL_TRANSFER)) + +#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU)) + +#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U)) + +#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U)) + +#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536)) + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MDMA_Private_Functions MDMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_MDMA_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h new file mode 100644 index 0000000..f1fe87f --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h @@ -0,0 +1,444 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PCD_H +#define STM32H7xx_HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_usb.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 +} PCD_StateTypeDef; + +/* Device LPM suspend state */ +typedef enum +{ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ + + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + + uint32_t battery_charging_active; /*!< Enable or disable Battery charging. + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extended module */ +#include "stm32h7xx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** @defgroup PCD_PHY_Module PCD PHY Module + * @{ + */ +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) + +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ +typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 12) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 11) /*!< USB HS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_PCD_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h new file mode 100644 index 0000000..221e2af --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PCD_EX_H +#define STM32H7xx_HAL_PCD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); + + +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); + +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7xx_HAL_PCD_EX_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h new file mode 100644 index 0000000..91a9054 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h @@ -0,0 +1,809 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PWR_H +#define STM32H7xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This + parameter can be a value of @ref + PWR_PVD_detection_level. + */ + + uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the PVD + event. This parameter can be a value of @ref + PWR_PVD_Mode. + */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector + level 0 selection : 1V95 */ +#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector + level 1 selection : 2V1 */ +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector + level 2 selection : 2V25 */ +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector + level 3 selection : 2V4 */ +#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector + level 4 selection : 2V55 */ +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector + level 5 selection : 2V7 */ +#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector + level 6 selection : 2V85 */ +#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage + (Compare internally to VREF) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (0x01U) +#define PWR_SLEEPENTRY_WFE (0x02U) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI (0x01U) +#define PWR_STOPENTRY_WFE (0x02U) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#if defined(PWR_SRDCR_VOS) +#define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1) +#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) +#else +#define PWR_REGULATOR_VOLTAGE_SCALE0 (0U) +#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) +#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) +#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) +#endif /* PWR_SRDCR_VOS */ +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +/* PWR CPU flag */ +#define PWR_FLAG_STOP (0x01U) +#if defined (PWR_CPUCR_SBF_D2) +#define PWR_FLAG_SB_D1 (0x02U) +#define PWR_FLAG_SB_D2 (0x03U) +#endif /* defined (PWR_CPUCR_SBF_D2) */ +#define PWR_FLAG_SB (0x04U) +#if defined (DUAL_CORE) +#define PWR_FLAG_CPU_HOLD (0x05U) +#define PWR_FLAG_CPU2_HOLD (0x06U) +#define PWR_FLAG2_STOP (0x07U) +#define PWR_FLAG2_SB_D1 (0x08U) +#define PWR_FLAG2_SB_D2 (0x09U) +#define PWR_FLAG2_SB (0x0AU) +#endif /* defined (DUAL_CORE) */ +#define PWR_FLAG_PVDO (0x0BU) +#define PWR_FLAG_AVDO (0x0CU) +#define PWR_FLAG_ACTVOSRDY (0x0DU) +#define PWR_FLAG_ACTVOS (0x0EU) +#define PWR_FLAG_BRR (0x0FU) +#define PWR_FLAG_VOSRDY (0x10U) +#if defined (SMPS) +#define PWR_FLAG_SMPSEXTRDY (0x11U) +#else +#define PWR_FLAG_SCUEN (0x11U) +#endif /* defined (SMPS) */ +#if defined (PWR_CSR1_MMCVDO) +#define PWR_FLAG_MMCVDO (0x12U) +#endif /* defined (PWR_CSR1_MMCVDO) */ +#define PWR_FLAG_USB33RDY (0x13U) +#define PWR_FLAG_TEMPH (0x14U) +#define PWR_FLAG_TEMPL (0x15U) +#define PWR_FLAG_VBATH (0x16U) +#define PWR_FLAG_VBATL (0x17U) + +/* PWR Wake up flag */ +#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 +#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 +#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 +#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 +#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5 +#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6 +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK (0x0FFF3F3FU) +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief Configure the main internal regulator output voltage. + * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a + * trade-off between performance and power consumption + * when the device does not operate at the maximum + * frequency (refer to the datasheet for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * Scale 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * Scale 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * Scale 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0 using + * __HAL_PWR_VOLTAGESCALING_CONFIG(). + * Transition to Voltage Scale 0 is only possible when the system is + * already in Voltage Scale 1. + * Transition from Voltage Scale 0 is only possible to Voltage Scale 1 + * then once in Voltage Scale 1 it is possible to switch to another + * voltage scale. + * After each regulator voltage setting, wait on VOSRDY flag to be set + * using macro __HAL_PWR_GET_FLAG(). + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. + * @retval None. + */ +#if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#else /* 3 power domains devices */ +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Check the voltage scaling to be configured */ \ + if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \ + { \ + /* Configure the Voltage Scaling 1 */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + /* Enable the PWR overdrive */ \ + SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + } \ + else \ + { \ + /* Disable the PWR overdrive */ \ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Delay after setting the syscfg boost setting */ \ + tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ + /* Configure the Voltage Scaling x */ \ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + } \ + UNUSED(tmpreg); \ +} while(0) +#else /* STM32H72xxx and STM32H73xxx lines */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ +do { \ + __IO uint32_t tmpreg = 0x00; \ + /* Configure the Voltage Scaling */ \ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ + /* Delay after setting the voltage scaling */ \ + tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ + UNUSED(tmpreg); \ +} while(0) +#endif /* defined(SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ + +/** @brief Check PWR flags are set or not. + * @param __FLAG__ : Specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD + * is enabled by the HAL_PWR_EnablePVD() + * function. + * The PVD is stopped by STANDBY mode. For this + * reason, this bit is equal to 0 after STANDBY + * or reset until the PVDE bit is set. + * @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD + * is enabled by the HAL_PWREx_EnableAVD() + * function. The AVD is stopped by STANDBY mode. + * For this reason, this bit is equal to 0 + * after STANDBY or reset until the AVDE bit + * is set. + * @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is + * ready. + * @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not + * reset when the device wakes up from STANDBY + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator + * voltage scaling output selection is ready. + * mode or by a system reset or power-on reset. + * @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply + * from regulator is ready. + * @arg PWR_FLAG_TEMPH : This flag indicates that the temperature + * equal or above high threshold level. + * @arg PWR_FLAG_TEMPL : This flag indicates that the temperature + * equal or below low threshold level. + * @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal + * or above high threshold level. + * @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal + * or below low threshold level. + * @arg PWR_FLAG_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG_SB : This flag indicates that the system entered in + * STANDBY mode. + * @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_STOP : This flag indicates that the system entered + * in STOP mode. + * @arg PWR_FLAG2_SB : This flag indicates that the system entered + * in STANDBY mode. + * @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain + * entered in STANDBY mode. + * @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain + * entered in STANDBY mode. + * @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes + * up with hold. + * @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes + * up with hold. + * @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS + * External supply is sready. + * @arg PWR_FLAG_SCUEN : This flag indicates that the supply + * configuration update is enabled. + * @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is + * above or equal to 1.2 V. + * @note The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, + * PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, + * PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags + * are used for all H7 family lines. + * The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, + * PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 + * dual core lines. + * The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 + * family except STM32H7Axxx and STM32H7Bxxx lines. + * The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and + * STM32H7Bxxx lines. + * The PWR_FLAG_SCUEN flag is used for devices that support only LDO + * regulator. + * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO + * and SMPS regulators. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#if defined (DUAL_CORE) /* Dual core lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\ + ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* Single core lines */ +#if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */ +#if defined (SMPS) /* STM32H725 and STM32H735 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ + ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* defined (SMPS) */ +#else /* STM32H7Axxx and STM32H7Bxxx lines */ +#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#else /* STM32H7Axx and STM32H7Bxx lines */ +#define __HAL_PWR_GET_FLAG(__FLAG__) \ +(((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ + ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ + ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ + ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ + ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ + ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ + ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ + ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ + ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ + ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ + ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ + ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) +#endif /* SMPS */ +#endif /* PWR_CPUCR_SBF_D2 */ +#endif /* DUAL_CORE */ + +/** @brief Check PWR wake up flags are set or not. + * @param __FLAG__: specifies the wake up flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval The (__FLAG__) state (TRUE or FALSE). + */ +#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) + +#if defined (DUAL_CORE) +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2. + * This parameter can be one of the following values : + * @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 + * CPU flags. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ +do { \ + SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \ +} while(0) +#else +/** @brief Clear CPU PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with other families. + * @note This macro clear all CPU flags. + * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU + * flags are STOPF, SBF, SBF_D1 and SBF_D2. + * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF. + * @retval None. + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) +#endif /* defined (DUAL_CORE) */ + +/** @brief Clear PWR wake up flags. + * @param __FLAG__ : Specifies the wake up flag to be cleared. + * This parameter can be one of the following values : + * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. + * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. + * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. + * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. + * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. + * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. + * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices + * that support GPIOI port. + * @retval None. + */ +#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) + +/** + * @brief Enable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable the PVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable the PVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable event on PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable event on PVD EXTI D2 Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable event on PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable event on PVD EXTI D2 Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable the PVD Rising Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Rising Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Rising & Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Disable the PVD Rising & Falling Interrupt Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) + +#if defined (DUAL_CORE) +/** + * @brief Checks whether the specified PVD EXTI interrupt flag is set or not. + * @retval EXTI D2 PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Clear the PVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) + +#if defined (DUAL_CORE) +/** + * @brief Clear the PVD EXTI D2 flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32h7xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit (void); +void HAL_PWR_EnableBkUpAccess (void); +void HAL_PWR_DisableBkUpAccess (void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD (void); +void HAL_PWR_DisablePVD (void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode (void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler (void); +void HAL_PWR_PVDCallback (void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit (void); +void HAL_PWR_DisableSleepOnExit (void); +void HAL_PWR_EnableSEVOnPend (void); +void HAL_PWR_DisableSEVOnPend (void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +/* Check PVD level parameter */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\ + ((LEVEL) == PWR_PVDLEVEL_1) ||\ + ((LEVEL) == PWR_PVDLEVEL_2) ||\ + ((LEVEL) == PWR_PVDLEVEL_3) ||\ + ((LEVEL) == PWR_PVDLEVEL_4) ||\ + ((LEVEL) == PWR_PVDLEVEL_5) ||\ + ((LEVEL) == PWR_PVDLEVEL_6) ||\ + ((LEVEL) == PWR_PVDLEVEL_7)) + +/* Check PVD mode parameter */ +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +/* Check low power regulator parameter */ +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +/* Check low power mode entry parameter */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ + ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +/* Check low power mode entry parameter */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ + ((ENTRY) == PWR_STOPENTRY_WFE)) + +/* Check voltage scale level parameter */ +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H7xx_HAL_PWR_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h new file mode 100644 index 0000000..61c7609 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h @@ -0,0 +1,789 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_PWR_EX_H +#define STM32H7xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Types PWREx Exported Types + * @{ + */ +/** + * @brief PWREx AVD configuration structure definition + */ +typedef struct +{ + uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This + parameter can be a value of @ref + PWREx_AVD_detection_level + */ + + uint32_t Mode; /*!< Mode : Specifies the EXTI operating mode for the AVD + event. This parameter can be a value of @ref + PWREx_AVD_Mode. + */ +}PWREx_AVDTypeDef; + +/** + * @brief PWREx Wakeup pin configuration structure definition + */ +typedef struct +{ + uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. + This parameter can be a value of @ref + PWREx_WakeUp_Pins + */ + + uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. + This parameter can be a value of @ref + PWREx_PIN_Polarity + */ + + uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This + parameter can be a value of @ref + PWREx_PIN_Pull + */ +}PWREx_WakeupPinTypeDef; + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief PWR VDDMMC voltage level enum definition + */ +typedef enum +{ + PWR_MMC_VOLTAGE_BELOW_1V2, /*!< VDDMMC is below 1V2 */ + PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */ +} PWREx_MMC_VoltageLevel; +#endif /* defined (PWR_CSR1_MMCVDO) */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins + * @{ + */ +/* High level and No pull (default configuration) */ +#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 + +/* High level and No pull */ +#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 +#if defined (PWR_WKUPEPR_WKUPEN5) +#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 +#if defined (PWR_WKUPEPR_WKUPEN3) +#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 +#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 + +/* Low level and No pull */ +#define PWR_WAKEUP_PIN6_LOW (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) +#if defined (PWR_WKUPEPR_WKUPP5) +#define PWR_WAKEUP_PIN5_LOW (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) +#endif /* defined (PWR_WKUPEPR_WKUPP5) */ +#define PWR_WAKEUP_PIN4_LOW (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) +#if defined (PWR_WKUPEPR_WKUPP3) +#define PWR_WAKEUP_PIN3_LOW (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) +#endif /* defined (PWR_WKUPEPR_WKUPP3) */ +#define PWR_WAKEUP_PIN2_LOW (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) +#define PWR_WAKEUP_PIN1_LOW (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration + * @{ + */ +#define PWR_PIN_POLARITY_HIGH (0x00000000U) +#define PWR_PIN_POLARITY_LOW (0x00000001U) +/** + * @} + */ + +/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration + * @{ + */ +#define PWR_PIN_NO_PULL (0x00000000U) +#define PWR_PIN_PULL_UP (0x00000001U) +#define PWR_PIN_PULL_DOWN (0x00000002U) +/** + * @} + */ + +/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. + * @{ + */ +#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ +#if defined (PWR_WKUPFR_WKUPF5) +#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ +#endif /* defined (PWR_WKUPFR_WKUPF5) */ +#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\ + PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6) +#else +#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\ + PWR_WKUPFR_WKUPF4 | PWR_WKUPFR_WKUPF6) +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +/** + * @} + */ + +#if defined (DUAL_CORE) +/** @defgroup PWREx_Core_Select PWREx Core definition + * @{ + */ +#define PWR_CORE_CPU1 (0x00000000U) +#define PWR_CORE_CPU2 (0x00000001U) +/** + * @} + */ +#endif /* defined (DUAL_CORE) */ + +/** @defgroup PWREx_Domains PWREx Domains definition + * @{ + */ +#define PWR_D1_DOMAIN (0x00000000U) +#if defined (PWR_CPUCR_PDDS_D2) +#define PWR_D2_DOMAIN (0x00000001U) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ +#define PWR_D3_DOMAIN (0x00000002U) +/** + * @} + */ + +/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition + * @{ + */ +#if defined (DUAL_CORE) +#define PWR_D1_DOMAIN_FLAGS (0x00000000U) +#define PWR_D2_DOMAIN_FLAGS (0x00000001U) +#define PWR_ALL_DOMAIN_FLAGS (0x00000002U) +#else +#define PWR_CPU_FLAGS (0x00000000U) +#endif /* defined (DUAL_CORE) */ +/** + * @} + */ + +/** @defgroup PWREx_D3_State PWREx D3 Domain State + * @{ + */ +#define PWR_D3_DOMAIN_STOP (0x00000000U) +#define PWR_D3_DOMAIN_RUN (0x00000800U) + +/** + * @} + */ + +/** @defgroup PWREx_Supply_configuration PWREx Supply configuration + * @{ + */ +#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ +#if defined (SMPS) +#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */ +#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ +#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ +#endif /* defined (SMPS) */ +#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */ + +#if defined (SMPS) +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \ + PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#else +#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) +#endif /* defined (SMPS) */ +/** + * @} + */ + + +/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level + * @{ + */ +#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0 + selection : 1V7 */ +#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1 + selection : 2V1 */ +#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2 + selection : 2V5 */ +#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3 + selection : 2V8 */ +/** + * @} + */ + +/** @defgroup PWREx_AVD_Mode PWREx AVD Mode + * @{ + */ +#define PWR_AVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ +#define PWR_AVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) +#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) +#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds + * @{ + */ +#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) +#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL +#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH +/** + * @} + */ + +/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds + * @{ + */ +#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD (0x00000000U) +#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL +#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH +/** + * @} + */ +/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 + * @{ + */ +#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16 + Connected to the AVD EXTI Line */ +/** + * @} + */ + +#if defined (PWR_CR1_SRDRAMSO) +/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection + * @{ + */ +#define PWR_SRD_AHB_MEMORY_BLOCK PWR_CR1_SRDRAMSO /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode */ +#define PWR_USB_FDCAN_MEMORY_BLOCK PWR_CR1_HSITFSO /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */ +#define PWR_GFXMMU_JPEG_MEMORY_BLOCK PWR_CR1_GFXSO /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode */ +#define PWR_TCM_ECM_MEMORY_BLOCK PWR_CR1_ITCMSO /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM1SO /*!< AHB RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AHB_MEMORY_BLOCK PWR_CR1_AHBRAM2SO /*!< AHB RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM1_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM1SO /*!< AXI RAM1 shut-off in DStop/DStop2 mode */ +#define PWR_RAM2_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM2SO /*!< AXI RAM2 shut-off in DStop/DStop2 mode */ +#define PWR_RAM3_AXI_MEMORY_BLOCK PWR_CR1_AXIRAM3SO /*!< AXI RAM3 shut-off in DStop/DStop2 mode */ +#define PWR_MEMORY_BLOCK_KEEP_ON 0U /*!< Memory content is kept in DStop or DStop2 mode */ +#define PWR_MEMORY_BLOCK_SHUT_OFF 1U /*!< Memory content is lost in DStop or DStop2 mode */ +/** + * @} + */ +#endif /* defined (PWR_CR1_SRDRAMSO) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Macro PWREx Exported Macro + * @{ + */ + +/** + * @brief Enable the AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable the AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable the AVD EXTI Line 16 + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable the AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Enable event on AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Disable event on AVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Disable event on AVD EXTI D2 Line 16. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Enable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Disable the AVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) + +/** + * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do { \ + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ +} while(0); + +/** + * @brief Check whether the specified AVD EXTI interrupt flag is set or not. + * @retval EXTI AVD Line Status. + */ +#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) + +#if defined (DUAL_CORE) +/** + * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not. + * @retval EXTI D2 AVD Line Status. + */ +#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Clear the AVD EXTI flag. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) + +#if defined (DUAL_CORE) +/** + * @brief Clear the AVD EXTI D2 flag. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) +#endif /* defined (DUAL_CORE) */ + +/** + * @brief Generates a Software interrupt on AVD EXTI line. + * @retval None. + */ +#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @{ + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig (void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange (void); +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetStopModeVoltageRange (void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @{ + */ +/* System low power control functions */ +#if defined (PWR_CPUCR_RETDS_CD) +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry); +#endif /* defined (PWR_CPUCR_RETDS_CD) */ +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain); +void HAL_PWREx_ConfigD3Domain (uint32_t D3State); +/* Clear Cortex-Mx pending flag */ +void HAL_PWREx_ClearPendingEvent (void); +#if defined (DUAL_CORE) +/* Clear domain flags */ +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags); +/* Core Hold/Release functions */ +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU); +void HAL_PWREx_ReleaseCore (uint32_t CPU); +#endif /* defined (DUAL_CORE) */ +/* Flash low power control functions */ +void HAL_PWREx_EnableFlashPowerDown (void); +void HAL_PWREx_DisableFlashPowerDown (void); +#if defined (PWR_CR1_SRDRAMSO) +/* Memory shut-off functions */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); +#endif /* defined(PWR_CR1_SRDRAMSO) */ +/* Wakeup Pins control functions */ +void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); +/* Power Wakeup PIN IRQ Handler */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void); +void HAL_PWREx_WKUP1_Callback (void); +void HAL_PWREx_WKUP2_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN3) +void HAL_PWREx_WKUP3_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +void HAL_PWREx_WKUP4_Callback (void); +#if defined (PWR_WKUPEPR_WKUPEN5) +void HAL_PWREx_WKUP5_Callback (void); +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +void HAL_PWREx_WKUP6_Callback (void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions + * @{ + */ +/* Backup regulator control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void); +/* USB regulator control functions */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void); +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void); +void HAL_PWREx_EnableUSBVoltageDetector (void); +void HAL_PWREx_DisableUSBVoltageDetector (void); +/* Battery control functions */ +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue); +void HAL_PWREx_DisableBatteryCharging (void); +#if defined (PWR_CR1_BOOSTE) +/* Analog Booster functions */ +void HAL_PWREx_EnableAnalogBooster (void); +void HAL_PWREx_DisableAnalogBooster (void); +#endif /* PWR_CR1_BOOSTE */ +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @{ + */ +/* Power VBAT/Temperature monitoring functions */ +void HAL_PWREx_EnableMonitoring (void); +void HAL_PWREx_DisableMonitoring (void); +uint32_t HAL_PWREx_GetTemperatureLevel (void); +uint32_t HAL_PWREx_GetVBATLevel (void); +#if defined (PWR_CSR1_MMCVDO) +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); +#endif /* PWR_CSR1_MMCVDO */ +/* Power AVD configuration functions */ +void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_EnableAVD (void); +void HAL_PWREx_DisableAVD (void); +/* Power PVD/AVD IRQ Handler */ +void HAL_PWREx_PVD_AVD_IRQHandler (void); +void HAL_PWREx_AVDCallback (void); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +/* Check PWR regulator configuration parameter */ +#if defined (SMPS) +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\ + ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) + +#else +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) +#endif /* defined (SMPS) */ + +/* Check PWR regulator configuration in STOP mode parameter */ +#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\ + ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) + +/* Check PWR domain parameter */ +#if defined (PWR_CPUCR_PDDS_D2) +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D2_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#else +#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\ + ((DOMAIN) == PWR_D3_DOMAIN)) +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + +/* Check D3/SRD domain state parameter */ +#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\ + ((STATE) == PWR_D3_DOMAIN_RUN)) + +/* Check wake up pin parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ + +/* Check wake up pin polarity parameter */ +#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\ + ((POLARITY) == PWR_PIN_POLARITY_LOW)) + +/* Check wake up pin pull configuration parameter */ +#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\ + ((PULL) == PWR_PIN_PULL_UP) ||\ + ((PULL) == PWR_PIN_PULL_DOWN)) + +/* Check wake up flag parameter */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG3) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG5) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#else +#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\ + ((FLAG) == PWR_WAKEUP_FLAG2) ||\ + ((FLAG) == PWR_WAKEUP_FLAG4) ||\ + ((FLAG) == PWR_WAKEUP_FLAG6) ||\ + ((FLAG) == PWR_WAKEUP_FLAG_ALL)) +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ + +/* Check wake up flag parameter */ +#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\ + ((LEVEL) == PWR_AVDLEVEL_1) ||\ + ((LEVEL) == PWR_AVDLEVEL_2) ||\ + ((LEVEL) == PWR_AVDLEVEL_3)) + +/* Check AVD mode parameter */ +#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_AVD_MODE_NORMAL) ||\ + ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING)) + +/* Check resistor battery parameter */ +#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ + ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) +/* Check D1/CD CPU ID parameter */ +#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) + +#if defined (DUAL_CORE) +/* Check CPU parameter */ +#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) + +/* Check D2 CPU ID parameter */ +#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID) + +/* Check PWR domain flag parameter */ +#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \ + ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \ + ((FLAG) == PWR_ALL_DOMAIN_FLAGS)) +#endif /* defined (DUAL_CORE) */ + +#if defined (PWR_CR1_SRDRAMSO) +/* Check memory block parameter */ +#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK) || \ + ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK)) +#endif /* defined (PWR_CR1_SRDRAMSO) */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7xx_HAL_PWR_EX_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h new file mode 100644 index 0000000..39eb5fa --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h @@ -0,0 +1,744 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_qspi.h + * @author MCD Application Team + * @brief Header file of QSPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_QSPI_H +#define STM32H7xx_HAL_QSPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined(QUADSPI) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup QSPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup QSPI_Exported_Types QSPI Exported Types + * @{ + */ + +/** + * @brief QSPI Init structure definition + */ +typedef struct +{ + uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. + This parameter can be a number between 0 and 255 */ + uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) + This parameter can be a value between 1 and 32 */ + uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to + take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) + This parameter can be a value of @ref QSPI_SampleShifting */ + uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits + required to address the flash memory. The flash capacity can be up to 4GB + (addressed using 32 bits) in indirect mode, but the addressable space in + memory-mapped mode is limited to 256MB + This parameter can be a number between 0 and 31 */ + uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number + of clock cycles which the chip select must remain high between commands. + This parameter can be a value of @ref QSPI_ChipSelectHighTime */ + uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. + This parameter can be a value of @ref QSPI_ClockMode */ + uint32_t FlashID; /* Specifies the Flash which will be used, + This parameter can be a value of @ref QSPI_Flash_Select */ + uint32_t DualFlash; /* Specifies the Dual Flash Mode State + This parameter can be a value of @ref QSPI_DualFlash_Mode */ +}QSPI_InitTypeDef; + +/** + * @brief HAL QSPI State structures definition + */ +typedef enum +{ + HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ + HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ + HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ + HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ + HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ + HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ + HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ + HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ + HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ +}HAL_QSPI_StateTypeDef; + +/** + * @brief QSPI Handle Structure definition + */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +typedef struct __QSPI_HandleTypeDef +#else +typedef struct +#endif +{ + QUADSPI_TypeDef *Instance; /* QSPI registers base address */ + QSPI_InitTypeDef Init; /* QSPI communication parameters */ + uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ + __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ + __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ + uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ + __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ + __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ + MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ + __IO HAL_LockTypeDef Lock; /* Locking object */ + __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ + __IO uint32_t ErrorCode; /* QSPI Error code */ + uint32_t Timeout; /* Timeout for the QSPI memory access */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); + void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); + + void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); + void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); +#endif +}QSPI_HandleTypeDef; + +/** + * @brief QSPI Command structure definition + */ +typedef struct +{ + uint32_t Instruction; /* Specifies the Instruction to be sent + This parameter can be a value (8-bit) between 0x00 and 0xFF */ + uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) + This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ + uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) + This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ + uint32_t AddressSize; /* Specifies the Address Size + This parameter can be a value of @ref QSPI_AddressSize */ + uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size + This parameter can be a value of @ref QSPI_AlternateBytesSize */ + uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. + This parameter can be a number between 0 and 31 */ + uint32_t InstructionMode; /* Specifies the Instruction Mode + This parameter can be a value of @ref QSPI_InstructionMode */ + uint32_t AddressMode; /* Specifies the Address Mode + This parameter can be a value of @ref QSPI_AddressMode */ + uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode + This parameter can be a value of @ref QSPI_AlternateBytesMode */ + uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) + This parameter can be a value of @ref QSPI_DataMode */ + uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) + This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length + until end of memory)*/ + uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase + This parameter can be a value of @ref QSPI_DdrMode */ + uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data + output by one half of system clock in DDR mode. + This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ + uint32_t SIOOMode; /* Specifies the send instruction only once mode + This parameter can be a value of @ref QSPI_SIOOMode */ +}QSPI_CommandTypeDef; + +/** + * @brief QSPI Auto Polling mode configuration structure definition + */ +typedef struct +{ + uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. + This parameter can be any value between 0 and 0xFFFF */ + uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. + This parameter can be any value between 1 and 4 */ + uint32_t MatchMode; /* Specifies the method used for determining a match. + This parameter can be a value of @ref QSPI_MatchMode */ + uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref QSPI_AutomaticStop */ +}QSPI_AutoPollingTypeDef; + +/** + * @brief QSPI Memory Mapped mode configuration structure definition + */ +typedef struct +{ + uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. + This parameter can be any value between 0 and 0xFFFF */ + uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref QSPI_TimeOutActivation */ +}QSPI_MemoryMappedTypeDef; + +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/** + * @brief HAL QSPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ + HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ + HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ + HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ + HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ + HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ + HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ + HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ + + HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ + HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ +}HAL_QSPI_CallbackIDTypeDef; + +/** + * @brief HAL QSPI Callback pointer definition + */ +typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup QSPI_Exported_Constants QSPI Exported Constants + * @{ + */ + +/** @defgroup QSPI_ErrorCode QSPI Error Code + * @{ + */ +#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ +#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ +#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ +#endif +/** + * @} + */ + +/** @defgroup QSPI_SampleShifting QSPI Sample Shifting + * @{ + */ +#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!State = HAL_QSPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) +#endif + +/** @brief Enable the QSPI peripheral. + * @param __HANDLE__ specifies the QSPI Handle. + * @retval None + */ +#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) + +/** @brief Disable the QSPI peripheral. + * @param __HANDLE__ specifies the QSPI Handle. + * @retval None + */ +#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) + +/** @brief Enable the specified QSPI interrupt. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. + * This parameter can be one of the following values: + * @arg QSPI_IT_TO: QSPI Timeout interrupt + * @arg QSPI_IT_SM: QSPI Status match interrupt + * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt + * @arg QSPI_IT_TC: QSPI Transfer complete interrupt + * @arg QSPI_IT_TE: QSPI Transfer error interrupt + * @retval None + */ +#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + + +/** @brief Disable the specified QSPI interrupt. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. + * This parameter can be one of the following values: + * @arg QSPI_IT_TO: QSPI Timeout interrupt + * @arg QSPI_IT_SM: QSPI Status match interrupt + * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt + * @arg QSPI_IT_TC: QSPI Transfer complete interrupt + * @arg QSPI_IT_TE: QSPI Transfer error interrupt + * @retval None + */ +#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Check whether the specified QSPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. + * This parameter can be one of the following values: + * @arg QSPI_IT_TO: QSPI Timeout interrupt + * @arg QSPI_IT_SM: QSPI Status match interrupt + * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt + * @arg QSPI_IT_TC: QSPI Transfer complete interrupt + * @arg QSPI_IT_TE: QSPI Transfer error interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Check whether the selected QSPI flag is set or not. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. + * This parameter can be one of the following values: + * @arg QSPI_FLAG_BUSY: QSPI Busy flag + * @arg QSPI_FLAG_TO: QSPI Timeout flag + * @arg QSPI_FLAG_SM: QSPI Status match flag + * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag + * @arg QSPI_FLAG_TC: QSPI Transfer complete flag + * @arg QSPI_FLAG_TE: QSPI Transfer error flag + * @retval None + */ +#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) + +/** @brief Clears the specified QSPI's flag status. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set + * This parameter can be one of the following values: + * @arg QSPI_FLAG_TO: QSPI Timeout flag + * @arg QSPI_FLAG_SM: QSPI Status match flag + * @arg QSPI_FLAG_TC: QSPI Transfer complete flag + * @arg QSPI_FLAG_TE: QSPI Transfer error flag + * @retval None + */ +#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup QSPI_Exported_Functions + * @{ + */ + +/** @addtogroup QSPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); +HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); +void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); +void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); +/** + * @} + */ + +/** @addtogroup QSPI_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +/* QSPI IRQ handler method */ +void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); + +/* QSPI indirect mode */ +HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); +HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); +HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); +HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); +HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); +HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); + +/* QSPI status flag polling mode */ +HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); + +/* QSPI memory-mapped mode */ +HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); + +/* Callback functions in non-blocking modes ***********************************/ +void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); +void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); +void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); + +/* QSPI indirect mode */ +void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); +void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); +void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); + +/* QSPI status flag polling mode */ +void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); + +/* QSPI memory-mapped mode */ +void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); + +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/* QSPI callback registering/unregistering */ +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); +#endif +/** + * @} + */ + +/** @addtogroup QSPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); +uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); +HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); +HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); +void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); +HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); +uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); +HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup QSPI_Private_Macros QSPI Private Macros + * @{ + */ +#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) + +#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) + +#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ + ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) + +#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) + +#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ + ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) + +#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ + ((CLKMODE) == QSPI_CLOCK_MODE_3)) + +#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ + ((FLASH_ID) == QSPI_FLASH_ID_2)) + +#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ + ((MODE) == QSPI_DUALFLASH_DISABLE)) + +#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) + +#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ + ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) + +#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ + ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) + +#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) + +#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ + ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ + ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ + ((MODE) == QSPI_INSTRUCTION_4_LINES)) + +#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ + ((MODE) == QSPI_ADDRESS_1_LINE) || \ + ((MODE) == QSPI_ADDRESS_2_LINES) || \ + ((MODE) == QSPI_ADDRESS_4_LINES)) + +#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ + ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) + +#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ + ((MODE) == QSPI_DATA_1_LINE) || \ + ((MODE) == QSPI_DATA_2_LINES) || \ + ((MODE) == QSPI_DATA_4_LINES)) + +#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ + ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) + +#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ + ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) + +#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ + ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) + +#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) + +#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) + +#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ + ((MODE) == QSPI_MATCH_MODE_OR)) + +#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ + ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) + +#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ + ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) + +#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) +/** +* @} +*/ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(QUADSPI) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_QSPI_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h new file mode 100644 index 0000000..1626c6d --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -0,0 +1,8266 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_RCC_H +#define STM32H7xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ + + uint32_t PLLP; /*!< PLLP: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + uint32_t PLLRGE; /*!AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* JPEG */ + +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI1 */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPI2 */ +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* OTFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GFXMMU */ +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) + +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN)) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN)) +#endif /* OCTOSPI2 */ +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN)) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN)) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN)) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN)) +#endif /* GFXMMU */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U) +#endif /* JPEG */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U) +#if defined (QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) != 0U) +#endif /* QUADSPI */ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) != 0U) +#endif /* OCTOSPII */ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) != 0U) +#endif /* OCTOSPI2 */ +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U) +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U) +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U) +#endif /* OTOFDEC1 */ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U) +#endif /* OTOFDEC2 */ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U) +#endif /* GFXMMU */ + +#define __HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U) +#endif /* JPEG */ +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U) +#if defined (QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN) == 0U) +#endif /* QUADSPI */ +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U) +#endif +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U) +#endif +#if defined(OCTOSPIM) +#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U) +#endif +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U) +#endif +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U) +#endif +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U) +#endif +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DUAL_CORE*/ + +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_ETH1TX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_ETH1RX_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#endif +#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) +#endif /* USB2_OTG_FS */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U) +#define __HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) != 0U) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) != 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) != 0U) +#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) != 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) != 0U) +#endif +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) != 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U) +#define __HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN) == 0U) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN) == 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN) == 0U) +#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN) == 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN) == 0U) +#endif +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN) == 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U) +#endif /* USB2_OTG_FS */ + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DCMI_CLK_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DCMI && PSSI */ + +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_FMACEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* FMAC */ + +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CORDICEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CORDIC */ + +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#else +#define __HAL_RCC_AHBSRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ + +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#else +#define __HAL_RCC_AHBSRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ + +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* RCC_AHB2ENR_HSEMEN */ + +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* BDMA1 */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN)) +#define __HAL_RCC_DCMI_CLK_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_FMACEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CORDICEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN)) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN)) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN)) +#endif + +/** @brief Get the enable or disable status of the AHB2 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) != 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) != 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) != 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) != 0U) +#endif + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN) == 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN) == 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_FMACEN) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_CORDICEN) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U) +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U) +#endif +#if defined(RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN) == 0U) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN) == 0U) +#endif + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* GPIOI */ + +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_BDMA_CLK_ENABLE() __HAL_RCC_BDMA2_CLK_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif + +#define __HAL_RCC_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN) +#define __HAL_RCC_BDMA_CLK_DISABLE() __HAL_RCC_BDMA2_CLK_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN) +#endif +#define __HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Get the enable or disable status of the AHB4 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) != 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U) +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_ENABLED() __HAL_RCC_BDMA2_IS_CLK_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) != 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) != 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U) +#endif +#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U) + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN) == 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U) + +#if defined(RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_DISABLED() __HAL_RCC_BDMA2_IS_CLK_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN) == 0U) +#endif +#if defined(RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_HSEM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN) == 0U) +#endif +#if defined(RCC_AHB4ENR_SRDSRAMEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) == 0U) +#endif +#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LTDC */ + +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DSI*/ + +#define __HAL_RCC_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Get the enable or disable status of the APB3 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) != 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) != 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U) +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN) == 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_DSIEN) == 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U) + + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C5EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C5 */ + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM23EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM23 */ + +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_TIM24EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C5EN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM23EN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_TIM24EN) +#endif /* TIM24 */ + + +/** @brief Get the enable or disable status of the APB1 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) != 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) != 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U) +#define __HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U) +#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U) +#define __HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U) +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) != 0U) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN) == 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C5EN) == 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U) +#define __HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U) +#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U) +#define __HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U) +#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN) == 0U) +#endif /* TIM24 */ + + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*UART9*/ + +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*USART10*/ + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*SAI2*/ + +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*SAI3*/ + +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) +#endif /*HRTIM*/ + +/** @brief Get the enable or disable status of the APB2 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) != 0U) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) != 0U) +#endif /* SAI3 */ +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) != 0U) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U) +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U) +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN) == 0U) +#endif /*SAI2*/ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN) == 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN) == 0U) +#endif /*HRTIM1*/ + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM5 */ + +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* DAC2 */ + +#define __HAL_RCC_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI4 */ + +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DTS*/ + +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN) +#endif /*DFSDM2*/ + +/** @brief Get the enable or disable status of the APB4 peripheral clock + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) != 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U) +#define __HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) != 0U) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U) +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN) == 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U) +#define __HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN) == 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DTSEN) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN) == 0U) +#endif /*DFSDM2*/ + +#if defined(DUAL_CORE) + +/* Exported macros for RCC_C1 -------------------------------------------------*/ + +/** @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_MDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + + + +#define __HAL_RCC_C1_MDMA_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_C1_DMA2D_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#define __HAL_RCC_C1_FMC_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_C1_QSPI_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE() (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) + + + + +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DMA1_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_C1_DMA2_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_C1_ADC12_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#define __HAL_RCC_C1_ART_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_C1_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DCMI_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE() (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_GPIOA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_C1_GPIOB_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_C1_GPIOC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_C1_GPIOD_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_C1_GPIOE_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_C1_GPIOF_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_C1_GPIOG_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_C1_GPIOH_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#define __HAL_RCC_C1_GPIOI_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_C1_GPIOK_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#define __HAL_RCC_C1_CRC_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_C1_BDMA_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#define __HAL_RCC_C1_ADC3_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#define __HAL_RCC_C1_HSEM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE() (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LTDC_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#define __HAL_RCC_C1_DSI_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#define __HAL_RCC_C1_WWDG1_CLK_DISABLE() (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SWPMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_TIM2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_C1_TIM3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_C1_TIM4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_C1_TIM5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_C1_TIM6_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_C1_TIM7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_C1_TIM12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_C1_TIM13_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_C1_TIM14_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) +#define __HAL_RCC_C1_WWDG2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#define __HAL_RCC_C1_SPI2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_C1_SPI3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_C1_USART2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_C1_USART3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_C1_UART4_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_C1_UART5_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_C1_I2C1_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_C1_I2C2_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_C1_I2C3_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#define __HAL_RCC_C1_CEC_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_C1_DAC12_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_C1_UART7_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_C1_UART8_CLK_DISABLE() (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_C1_CRS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_C1_SWPMI_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_C1_OPAMP_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_C1_MDIOS_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_C1_FDCAN_CLK_DISABLE() (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_TIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_C1_TIM8_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_C1_USART1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_C1_USART6_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#define __HAL_RCC_C1_SPI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_C1_SPI4_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_C1_TIM15_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_C1_TIM16_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_C1_TIM17_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_C1_SPI5_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_C1_SAI1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#define __HAL_RCC_C1_SAI2_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#define __HAL_RCC_C1_SAI3_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE() (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C1_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_C1_LPUART1_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_C1_SPI6_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_C1_I2C4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#define __HAL_RCC_C1_COMP12_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_C1_VREF_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_C1_RTC_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#define __HAL_RCC_C1_SAI4_CLK_DISABLE() (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) + +/* Exported macros for RCC_C2 -------------------------------------------------*/ + +/** @brief Enable or disable the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + + +#define __HAL_RCC_C2_MDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FLASH_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCM1_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCM2_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ITCM_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_D1SRAM1_C2_ALLOCATE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + + + + +#define __HAL_RCC_C2_MDMA_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN)) +#define __HAL_RCC_C2_DMA2D_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN)) +#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN)) +#define __HAL_RCC_C2_FMC_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_C2_QSPI_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN)) +#define __HAL_RCC_FLASH_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN)) +#define __HAL_RCC_DTCM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN)) +#define __HAL_RCC_DTCM2_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN)) +#define __HAL_RCC_ITCM_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN)) +#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE() (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN)) + +/** @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ADC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ART_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_DMA1_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN)) +#define __HAL_RCC_C2_DMA2_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_C2_ADC12_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN)) +#define __HAL_RCC_C2_ART_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN)) + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRYP */ + +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* HASH */ + +#define __HAL_RCC_C2_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DCMI_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE() (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN)) + +/** @brief Enable or disable the AHB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_BDMA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_GPIOA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN) +#define __HAL_RCC_C2_GPIOB_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN) +#define __HAL_RCC_C2_GPIOC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN) +#define __HAL_RCC_C2_GPIOD_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN) +#define __HAL_RCC_C2_GPIOE_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN) +#define __HAL_RCC_C2_GPIOF_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN) +#define __HAL_RCC_C2_GPIOG_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN) +#define __HAL_RCC_C2_GPIOH_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN) +#define __HAL_RCC_C2_GPIOI_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN) +#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN) +#define __HAL_RCC_C2_GPIOK_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN) +#define __HAL_RCC_C2_CRC_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN) +#define __HAL_RCC_C2_BDMA_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN) +#define __HAL_RCC_C2_ADC3_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN) +#define __HAL_RCC_C2_HSEM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN) +#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE() (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN) + + +/** @brief Enable or disable the APB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_WWDG1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LTDC_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN) +#define __HAL_RCC_C2_DSI_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN) +#define __HAL_RCC_C2_WWDG1_CLK_DISABLE() (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN) + +/** @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_WWDG2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DAC12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SWPMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_OPAMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_MDIOS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_C2_TIM2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN) +#define __HAL_RCC_C2_TIM3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN) +#define __HAL_RCC_C2_TIM4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN) +#define __HAL_RCC_C2_TIM5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN) +#define __HAL_RCC_C2_TIM6_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN) +#define __HAL_RCC_C2_TIM7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN) +#define __HAL_RCC_C2_TIM12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN) +#define __HAL_RCC_C2_TIM13_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN) +#define __HAL_RCC_C2_TIM14_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN) +#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN) +#define __HAL_RCC_C2_WWDG2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN) +#define __HAL_RCC_C2_SPI2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN) +#define __HAL_RCC_C2_SPI3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN) +#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN) +#define __HAL_RCC_C2_USART2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN) +#define __HAL_RCC_C2_USART3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN) +#define __HAL_RCC_C2_UART4_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN) +#define __HAL_RCC_C2_UART5_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN) +#define __HAL_RCC_C2_I2C1_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN) +#define __HAL_RCC_C2_I2C2_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN) +#define __HAL_RCC_C2_I2C3_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN) +#define __HAL_RCC_C2_CEC_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN) +#define __HAL_RCC_C2_DAC12_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN) +#define __HAL_RCC_C2_UART7_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN) +#define __HAL_RCC_C2_UART8_CLK_DISABLE() (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN) +#define __HAL_RCC_C2_CRS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN) +#define __HAL_RCC_C2_SWPMI_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN) +#define __HAL_RCC_C2_OPAMP_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN) +#define __HAL_RCC_C2_MDIOS_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN) +#define __HAL_RCC_C2_FDCAN_CLK_DISABLE() (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN) + +/** @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_TIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN) +#define __HAL_RCC_C2_TIM8_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN) +#define __HAL_RCC_C2_USART1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN) +#define __HAL_RCC_C2_USART6_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN) +#define __HAL_RCC_C2_SPI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN) +#define __HAL_RCC_C2_SPI4_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN) +#define __HAL_RCC_C2_TIM15_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN) +#define __HAL_RCC_C2_TIM16_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN) +#define __HAL_RCC_C2_TIM17_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN) +#define __HAL_RCC_C2_SPI5_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN) +#define __HAL_RCC_C2_SAI1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN) +#define __HAL_RCC_C2_SAI2_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN) +#define __HAL_RCC_C2_SAI3_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN) +#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN) +#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE() (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN) + +/** @brief Enable or disable the APB4 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ + +#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_COMP12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_VREF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_C2_SAI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\ + UNUSED(tmpreg); \ + } while(0) + + + +#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN) +#define __HAL_RCC_C2_LPUART1_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN) +#define __HAL_RCC_C2_SPI6_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN) +#define __HAL_RCC_C2_I2C4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN) +#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN) +#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN) +#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN) +#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN) +#define __HAL_RCC_C2_COMP12_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN) +#define __HAL_RCC_C2_VREF_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN) +#define __HAL_RCC_C2_RTC_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN) +#define __HAL_RCC_C2_SAI4_CLK_DISABLE() (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN) + +#endif /*DUAL_CORE*/ + +/** @brief Enable or disable the AHB3 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00015031U) /* Resets MDMA, DMA2D, JPEG, FMC, QSPI and SDMMC1 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x01E95031U) /* Resets MDMA, DMA2D, JPEG, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 and GFXMMU */ +#else +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST)) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECRST_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ +#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST)) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ + +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00) +#define __HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST)) +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST)) +#if defined(JPEG) +#define __HAL_RCC_JPGDECRST_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST)) +#endif /* JPEG */ +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST)) +#endif /*QUADSPI*/ +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST)) +#endif /*OCTOSPI1*/ +#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST)) +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST)) +#endif /*GFXMMU*/ + + + +/** @brief Force or release the AHB1 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x0A00C023U) /* Resets DMA1, DMA2, ADC12, ART, ETHMAC, USB1OTG and USB2OTG */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02000223U) /* Resets DMA1, DMA2, ADC12, CRC and USB1OTG */ +#else +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST)) +#endif /*USB2_OTG_FS*/ + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST)) +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST)) +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST)) +#endif /*DUAL_CORE*/ +#if defined(RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST)) +#endif /*USB2_OTG_FS*/ + +/** @brief Force or release the AHB2 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000271U) /* Resets DCMI, CRYPT, HASH, RNG and SDMMC2 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00000A75U) /* Resets DCMI_PSSI, HSEM, CRYPT, HASH, RNG, SDMMC2 and BDMA1 */ +#else +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_FORCE_RESET() __HAL_RCC_DCMI_PSSI_FORCE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() __HAL_RCC_DCMI_PSSI_RELEASE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST)) +#endif /* HASH */ +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST)) +#if defined(FMAC) +#define __HAL_RCC_FMAC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_FMACRST)) +#endif /*FMAC*/ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CORDICRST)) +#endif /*CORDIC*/ +#if defined(RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST)) +#endif +#if defined(BDMA1) +#define __HAL_RCC_BDMA1_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST)) +#endif /*BDMA1*/ + + +/** @brief Force or release the AHB4 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032807FFU) /* Resets GPIOA..GPIOK, CRC, BDMA, ADC3 and HSEM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x002007FFU) /* Resets GPIOA..GPIOK and BDMA2 */ +#else +#define __HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_FORCE_RESET() __HAL_RCC_BDMA2_FORCE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) +#define __HAL_RCC_HSEM_FORCE_RESET() (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST) +#endif + +#define __HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST) +#if defined(RCC_AHB4RSTR_CRCRST) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST) +#define __HAL_RCC_BDMA_RELEASE_RESET() __HAL_RCC_BDMA2_RELEASE_RESET() /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST) +#endif /*ADC3*/ +#if defined(RCC_AHB4RSTR_HSEMRST) +#define __HAL_RCC_HSEM_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST) +#endif + +/** @brief Force or release the APB3 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000018U) /* Rests LTDC and DSI */ +#else +#define __HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if defined(LTDC) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST) +#endif /*DSI*/ + +#define __HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U) +#if defined(LTDC) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST) +#endif /*DSI*/ + +/** @brief Force or release the APB1 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xE8FFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, CEC, DAC1(2), UART7 and UART8 */ +#else +#define __HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x00000136U) /* Resets CRS, SWP, OPAMP, MDIOS and FDCAN */ +#else +#define __HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST) +#define __HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST) +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST) +#define __HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST) +#define __HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST) +#define __HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST) +#define __HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_FORCE_RESET() (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ + +#define __HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U) +#define __HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U) +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST) +#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST) +#if defined(I2C5) +#define __HAL_RCC_I2C5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C5RST) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST) +#define __HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST) +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST) +#define __HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST) +#define __HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST) +#define __HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST) +#define __HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST) +#if defined(TIM23) +#define __HAL_RCC_TIM23_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM23RST) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_TIM24RST) +#endif /* TIM24 */ + +/** @brief Force or release the APB2 peripheral reset. + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x31D73033U) /* Resets TIM1, TIM8, USART1, USART6, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1..SAI3, DFSDM1 and HRTIM */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x40D730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1, SAI2 and DFSDM1 */ +#else +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST) +#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST) +#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST) +#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST) +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_FORCE_RESET() (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST) +#if defined(UART9) +#define __HAL_RCC_UART9_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST) +#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST) +#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST) +#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST) +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST) +#if defined(SAI2) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST) +#endif /*HRTIM1*/ + +/** @brief Force or release the APB4 peripheral reset. + */ + +#if (STM32H7_DEV_ID == 0x450UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0020DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF and SAI4 */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0C00E6AAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2, LPTIM3, DAC2, COMP12, VREF, DTS and DFSDM2 */ +#else +#define __HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST) +#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST) +#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST) +#define __HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST) +#define __HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST) +#define __HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) +#define __HAL_RCC_SAI4_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_FORCE_RESET() (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ + +#define __HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST) +#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST) +#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST) +#define __HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST) +#endif /*LPTIM5*/ +#if defined(RCC_APB4RSTR_DAC2RST) +#define __HAL_RCC_DAC2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST) +#endif +#define __HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST) +#define __HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST) +#if defined(SAI4) +#define __HAL_RCC_SAI4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST) +#endif /*DFSDM2*/ + +/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + + +#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif +#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) +#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN)) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN)) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN)) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN)) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN)) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN)) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN)) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN)) +#endif +#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) +#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE +#else +#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN)) +#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) != 0U) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) != 0U) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) != 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) != 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) != 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) != 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) != 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) != 0U) +#endif +#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U) +#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U) +#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U) +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U) +#endif + +#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U) +#if defined(JPEG) +#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN) == 0U) +#endif /* JPEG */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U) +#if defined(QUADSPI) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN) == 0U) +#endif /*QUADSPI*/ +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U) +#if defined(OCTOSPI1) +#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN) == 0U) +#endif /*OCTOSPI1*/ +#if defined(OCTOSPI2) +#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN) == 0U) +#endif /*OCTOSPI2*/ +#if defined(OCTOSPIM) +#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U) +#endif /*OCTOSPIM*/ +#if defined(OTFDEC1) +#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) == 0U) +#endif /*OTFDEC1*/ +#if defined(OTFDEC2) +#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) == 0U) +#endif /*OTFDEC2*/ +#if defined(GFXMMU) +#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN) == 0U) +#endif /*GFXMMU*/ +#if defined(CD_AXISRAM2_BASE) +#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN) == 0U) +#endif +#if defined(CD_AXISRAM3_BASE) +#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN) == 0U) +#endif +#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U) +#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U) +#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U) +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U) +#else +#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U) +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN)) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN)) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN)) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) +#endif /* USB2_OTG_FS */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U) +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) != 0U) +#endif /*ETH*/ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) != 0U) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) != 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) != 0U) +#endif /*ETH*/ +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) != 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U) +#endif /* USB2_OTG_FS */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U) +#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U) +#if defined(RCC_AHB1LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == 0U) +#endif +#if defined(ETH) +#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN)) == 0U) +#endif /* ETH */ +#if defined(DUAL_CORE) +#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN)) == 0U) +#endif /*DUAL_CORE*/ +#if defined(ETH) +#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN)) == 0U) +#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN)) == 0U) +#endif /* ETH */ +#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U) +#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U) +#if defined(USB2_OTG_FS) +#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN)) == 0U) +#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U) +#endif /* USB2_OTG_FS */ + + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) +#endif + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN)) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_FMACLPEN)) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CORDICLPEN)) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#else +#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#else +#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN)) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) +#endif + +/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) != 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U) +#endif +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) != 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) != 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U) +#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */ + +#if defined(DCMI) && defined(PSSI) +#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN)) == 0U) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED() /* for API backward compatibility*/ +#else +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U) +#endif /* DCMI && PSSI */ +#if defined(CRYP) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == 0U) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == 0U) +#endif /* HASH */ +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U) +#if defined(RCC_AHB2LPENR_DFSDMDMALPEN) +#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U) +#endif +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U) +#if defined(FMAC) +#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_FMACLPEN)) == 0U) +#endif /* FMAC */ +#if defined(CORDIC) +#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CORDICLPEN)) == 0U) +#endif /* CORDIC */ +#if defined(RCC_AHB2LPENR_D2SRAM1LPEN) +#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM2LPEN) +#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U) +#else +#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */ +#if defined(RCC_AHB2LPENR_D2SRAM3LPEN) +#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U) +#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/ + + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#endif /* BDMA2 */ +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#endif /* ADC3 */ +#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN) +#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN)) +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE +#else +#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) +#endif + + +/** @brief Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) != 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) != 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) != 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) != 0U) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U) +#endif + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U) +#if defined(GPIOI) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN)) == 0U) +#endif /* GPIOI */ +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN)) == 0U) +#endif +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN)) == 0U) +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U) +#endif /*BDMA2*/ +#if defined(ADC3) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN)) == 0U) +#endif /*ADC3*/ +#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U) +#if defined(RCC_AHB4LPENR_SRDSRAMLPEN) +#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U) +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED /* For API backward compatibility*/ +#else +#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U) +#endif + + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + + +/** @brief Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) != 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) != 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U) + +#if defined(LTDC) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN)) == 0U) +#endif /* LTDC */ +#if defined(DSI) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN)) == 0U) +#endif /*DSI*/ +#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U) + + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ + + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) + +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#endif /*DUAL_CORE*/ + +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#if defined(I2C5) +#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C5LPEN) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) +#if defined(TIM23) +#define __HAL_RCC_TIM23_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM23LPEN) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_TIM24LPEN) +#endif /* TIM24 */ + + +/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) != 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) != 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U) +#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U) +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) != 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) != 0U) +#endif /* TIM24 */ + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U) +#if defined(DUAL_CORE) +#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN)) == 0U) +#endif /*DUAL_CORE*/ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U) +#if defined(I2C5) +#define __HAL_RCC_I2C5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C5LPEN)) == 0U) +#endif /* I2C5 */ +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U) +#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U) +#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U) +#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U) +#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U) +#if defined(TIM23) +#define __HAL_RCC_TIM23_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM23LPEN)) == 0U) +#endif /* TIM23 */ +#if defined(TIM24) +#define __HAL_RCC_TIM24_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_TIM24LPEN)) == 0U) +#endif /* TIM24 */ + + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#if defined(UART9) +#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#if defined(SAI2) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) +#endif /*HRTIM1*/ + + +/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U) +#if defined(UART9) +#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != 0U) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) != 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) != 0U) +#endif /*HRTIM1*/ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U) +#if defined(UART9) +#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U) +#endif /*UART9*/ +#if defined(USART10) +#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U) +#endif /*USART10*/ +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U) +#if defined(SAI2) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == 0U) +#endif /* SAI2 */ +#if defined(SAI3) +#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN)) == 0U) +#endif /*SAI3*/ +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U) +#if defined(HRTIM1) +#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN)) == 0U) +#endif /*HRTIM1*/ + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN) +#endif /*DFSDM2*/ + + +/** @brief Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) != 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) != 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) != 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U) +#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) != 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) != 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U) +#endif /*DFSDM2*/ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U) +#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U) +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN)) == 0U) +#endif /*LPTIM4*/ +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN)) == 0U) +#endif /*LPTIM5*/ +#if defined(DAC2) +#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN)) == 0U) +#endif /*DAC2*/ +#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U) +#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U) +#if defined(SAI4) +#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN)) == 0U) +#endif /*SAI4*/ +#if defined(DTS) +#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN)) == 0U) +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U) +#endif /*DFSDM2*/ + + +#if defined(DUAL_CORE) + +/** @brief Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) + + +#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) + + + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) + +#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C1->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) + +#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C1->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE() (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE() (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE() (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE() (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) + + +#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE() (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE() (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) + +#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE() (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) + + +#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE() (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) + +/** @brief Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + + +#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN)) + + +#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN)) +#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN)) +#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN)) +#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN)) +#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN)) +#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN)) +#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN)) +#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN)) +#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN)) + + + +/** @brief ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN)) +#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN)) +#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN)) +#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN)) +#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN)) +#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN)) +#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) + +/** @brief ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE() (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN)) + +#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN)) +#if defined(CRYP) +#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN)) +#endif /* CRYP */ +#if defined(HASH) +#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN)) +#endif /* HASH */ +#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN)) +#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN)) +#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE() (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN)) + +/** @brief ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE() (RCC_C2->AHB4LPENR |= (RCC_AHB4LPENR_D3SRAM1LPEN)) + +#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN) +#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN) +#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN) +#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN) +#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN) +#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN) +#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN) +#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN) +#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN) +#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN) +#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN) +#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN) +#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN) +#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN) +#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN) +#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE() (RCC_C2->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN)) + +/** @brief ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE() (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN) + +#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN) +#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN) +#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE() (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN) + +/** @brief ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE() (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE() (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN) + + +#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN) +#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN) +#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN) +#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN) +#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN) +#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN) +#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN) +#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN) +#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN) +#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN) +#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN) +#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN) +#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN) +#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN) +#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN) +#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN) +#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN) +#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN) +#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN) +#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN) +#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN) +#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN) +#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN) +#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN) +#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE() (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN) +#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN) +#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN) +#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN) +#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN) +#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE() (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN) + +/** @brief ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE() (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN) + +#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN) +#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN) +#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN) +#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN) +#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN) +#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN) +#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN) +#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN) +#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN) +#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN) +#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN) +#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN) +#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN) +#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN) +#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE() (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN) + +/** @brief ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is ENABLEd again. + * @note By default, all peripheral clocks are ENABLEd during SLEEP mode. + */ + +#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE() (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN) + +#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN) +#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN) +#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN) +#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN) +#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN) +#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN) +#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN) +#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN) +#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN) +#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN) +#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN) +#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE() (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN) + +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN + * @note After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP + */ +#else +/** @brief Enable or disable peripheral bus clock when D3 domain is in DRUN + * @note After reset (default config), peripheral clock is disabled when CPU is in CSTOP + */ +#endif /*DUAL_CORE*/ + +#if defined(RCC_D3AMR_BDMAAMEN) +#define __HAL_RCC_BDMA_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN) +#endif +#if defined(RCC_D3AMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) +#define __HAL_RCC_CRC_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN) +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) +#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE() (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(DAC2) +#define __HAL_RCC_DAC2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE() (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN) +#endif + +#if defined(RCC_D3AMR_BDMAAMEN) +#define __HAL_RCC_BDMA_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN) +#endif +#if defined(RCC_D3AMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN) +#endif +#if defined(RCC_D3AMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN) +#endif +#if defined(RCC_D3AMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN) +#endif +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN) +#endif +#if defined(LPTIM4) +#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN) +#endif +#if defined(LPTIM5) +#define __HAL_RCC_LPTIM5_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN) +#endif +#if defined(RCC_D3AMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN) +#endif +#if defined(RCC_D3AMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN) +#endif +#if defined(RCC_D3AMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN) +#endif +#if defined(RCC_D3AMR_CRCAMEN) +#define __HAL_RCC_CRC_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN) +#endif +#if defined(SAI4) +#define __HAL_RCC_SAI4_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN) +#endif +#if defined(ADC3) +#define __HAL_RCC_ADC3_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN) +#endif +#if defined(RCC_D3AMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_DTSAMEN) +#endif +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN) +#endif +#if defined(RCC_D3AMR_SRAM4AMEN) +#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE() (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN) +#endif + +#if defined(BDMA2) +#define __HAL_RCC_BDMA2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN) +#endif +#if defined(RCC_SRDAMR_GPIOAMEN) +#define __HAL_RCC_GPIO_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN) +#endif +#if defined(RCC_SRDAMR_LPUART1AMEN) +#define __HAL_RCC_LPUART1_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN) +#endif +#if defined(RCC_SRDAMR_SPI6AMEN) +#define __HAL_RCC_SPI6_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN) +#endif +#if defined(RCC_SRDAMR_I2C4AMEN) +#define __HAL_RCC_I2C4_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM2AMEN) +#define __HAL_RCC_LPTIM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN) +#endif +#if defined(RCC_SRDAMR_LPTIM3AMEN) +#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN) +#endif +#if defined(RCC_SRDAMR_DAC2AMEN) +#define __HAL_RCC_DAC2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN) +#endif +#if defined(RCC_SRDAMR_COMP12AMEN) +#define __HAL_RCC_COMP12_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN) +#endif +#if defined(RCC_SRDAMR_VREFAMEN) +#define __HAL_RCC_VREF_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN) +#endif +#if defined(RCC_SRDAMR_RTCAMEN) +#define __HAL_RCC_RTC_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN) +#endif +#if defined(RCC_SRDAMR_DTSAMEN) +#define __HAL_RCC_DTS_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN) +#endif +#if defined(DFSDM2_BASE) +#define __HAL_RCC_DFSDM2_CLKAM_DISABLE() (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN) +#endif +#if defined(RCC_SRDAMR_BKPRAMAMEN) +#define __HAL_RCC_BKPRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN) +#endif +#if defined(RCC_SRDAMR_SRDSRAMAMEN) +#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE() (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN) +#endif + + +#if defined(RCC_CKGAENR_AXICKG) +/** @brief Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register). + */ + +#define __HAL_RCC_AXI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_ENABLE() (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG) + + +#define __HAL_RCC_AXI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG) +#define __HAL_RCC_AHB_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG) +#define __HAL_RCC_CPU_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG) +#define __HAL_RCC_SDMMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG) +#define __HAL_RCC_MDMA_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG) +#define __HAL_RCC_DMA2D_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG) +#define __HAL_RCC_LTDC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG) +#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG) +#define __HAL_RCC_AHB12_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG) +#define __HAL_RCC_AHB34_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG) +#define __HAL_RCC_FLIFT_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG) +#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG) +#define __HAL_RCC_FMC_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG) +#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG) +#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG) +#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG) +#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG) +#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG) +#define __HAL_RCC_ECCRAM_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG) +#define __HAL_RCC_EXTI_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG) +#define __HAL_RCC_JTAG_CLKGA_DISABLE() (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG) + +#endif /* RCC_CKGAENR_AXICKG */ + + + + +/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param __STATE__ specifies the new state of the HSI. + * This parameter can be one of the following values: + * @arg RCC_HSI_OFF turn OFF the HSI oscillator + * @arg RCC_HSI_ON turn ON the HSI oscillator + * @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset) + * @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2 + * @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4 + * @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8 + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_CONFIG(__STATE__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__)) + + +/** @brief Macro to get the HSI divider. + * @retval The HSI divider. The returned value can be one + * of the following: + * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) + * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 + * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 + * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 + */ +#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after start-up + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICalibrationValue__: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x7F (3F for Rev Y device). + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + do { \ + if(HAL_GetREVID() <= REV_ID_Y) \ + { \ + if((__HSICalibrationValue__) == RCC_HSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, ((uint32_t)0x20) << HAL_RCC_REV_Y_HSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos); \ + } \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); \ + } \ + } while(0) + +#else +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for some peripherals. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI start-up time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + + +/** + * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). + * @note After enabling the HSI48, the application software should wait on + * HSI48RDY flag to be set indicating that HSI48 clock is stable and can + * be used to clock the USB. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON); + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); + +/** + * @brief Macros to enable or disable the Internal oscillator (CSI). + * @note The CSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after + * start-up from Reset, wakeup from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note CSI can not be stopped if it is used as system clock source. + * In this case, you have to select another source of the system + * clock then stop the CSI. + * @note After enabling the CSI, the application software should wait on + * CSIRDY flag to be set indicating that CSI clock is stable and can + * be used as system clock source. + * @note When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator + * clock cycles. + */ +#define __HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION) +#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION) + +/** @brief Macro Adjusts the Internal oscillator (CSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal CSI RC. + * @param __CSICalibrationValue__: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + if(HAL_GetREVID() <= REV_ID_Y) \ + { \ + if((__CSICalibrationValue__) == RCC_CSICALIBRATION_DEFAULT) \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, ((uint32_t)0x10) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ + else \ + { \ + MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos); \ + } \ + } \ + else \ + { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } \ + } while(0) + +#else +#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__) \ + do { \ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos); \ + } while(0) + +#endif /*RCC_VER_X*/ +/** + * @brief Macros to enable or disable the force of the Low-power Internal oscillator (CSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the CSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the CSI start-up time. + * @note The enable of this function has not effect on the CSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON) +#define __HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON) + + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (__HSE__). + * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), + * the application software should wait on HSERDY flag to be set indicating + * that HSE clock is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + * @arg RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*) + * + * (*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + */ +#if defined(RCC_CR_HSEEXT) +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ + } \ + } while(0) +#else +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) +#endif /* RCC_CR_HSEEXT */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*). + A duty cycle close to 50% is recommended. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @note If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*) + * @param __STATE__: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + * @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*) + * + * (*) Available on some STM32H7 lines only. + */ +#if defined(RCC_BDCR_LSEEXT) +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); \ + } \ + } while(0) +#else + +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) + +#endif /* RCC_BDCR_LSEEXT */ +/** + * @} + */ + +/** @brief Macros to enable or disable the the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \ + } while (0) + +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) + + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) + +/** + * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL is disabled. + * This is mainly used to save Power. + * (The ck_pll_p of the System PLL cannot be stopped if used as System Clock). + * @param __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) + +#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__)) + + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 + * @retval None + */ +#define __HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + +#define __HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) + + +/** + * @brief Macro to configures the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __RCC_PLLSOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . + * + * @param __PLLM1__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLLN1__: specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between 4 and 512 or between 8 and 420(*). + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLLP1__: specifies the division factor for system clock. + * This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed) + * + * @param __PLLQ1__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLLR1__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL1P__, __PLL1Q__ or __PLL1R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * (**): For stm32h72xxx and stm32h73xxx family lines. + */ + + +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \ + do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U))); \ + WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \ + ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \ + } while(0) + + +/** @brief Macro to configure the PLLs clock source. + * @note This function must be used only when all PLLs are disabled. + * @param __PLLSOURCE__: specifies the PLLs entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__)) + + +/** + * @brief Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO + * + * @param __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO + * It should be a value between 0 and 8191 + * @note Warning: The software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 + * 150 to 420 MHz if PLL1VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) + + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__)) + + +/** @brief Macro to select the PLL1 reference frequency range. + * @param __RCC_PLL1VCORange__: specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__)) + + + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_CFGR_SWS_CSI: CSI used as system clock. + * - RCC_CFGR_SWS_HSI: HSI used as system clock. + * - RCC_CFGR_SWS_HSE: HSE used as system clock. + * - RCC_CFGR_SWS_PLL: PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) + + +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC)) + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO1 clock + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCO2 clock + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7))); + +/** + * @} + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note On STM32H7 Rev.B and above devices this can't be updated while LSE is ON. + * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. + * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. + * @retval None + */ +#if defined(RCC_VER_X) +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + do{ \ + if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH))) \ + { \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk); \ + } \ + else \ + { \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); \ + } \ + } while(0) +#else +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)); +#endif /*RCC_VER_X*/ +/** + * @brief Macro to configure the wake up from stop clock. + * @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source + * @retval None + */ +#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__)) + +/** + * @brief Macro to configure the Kernel wake up from stop clock. + * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source + * @retval None + */ +#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: HSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: HSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear the RCC's interrupt pending bits + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: CSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_HSECSS: HSE Clock Security interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_CSIRDY: CSI ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt + * @arg RCC_IT_PLLRDY: main PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_HSECSS: HSE Clock Security interrupt + * @arg RCC_IT_LSECSS: Clock security system interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF) + +#if defined(DUAL_CORE) +#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF) + +#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSIDIV: HSI divider flag + * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready + * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready + * @arg RCC_FLAG_PLLRDY: PLL1 clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_C1RST: CPU reset flag + * @arg RCC_FLAG_C2RST: CPU2 reset flag + * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag + * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag + * @arg RCC_FLAG_BORRST: BOR reset flag + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag + * @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag + * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag + * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset + * @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset + * @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset + * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset + * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag + * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR)))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) + +#else + +/** @brief Check RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSIDIV: HSI divider flag + * @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready + * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_D1CKRDY: Domain1 clock ready (*) + * @arg RCC_FLAG_D2CKRDY: Domain2 clock ready (*) + * @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*) + * @arg RCC_FLAG_CDCKRDY: CPU Domain clock ready (*) + * @arg RCC_FLAG_PLLRDY: PLL1 clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_CPURST: CPU reset flag + * @arg RCC_FLAG_D1RST: D1 domain power switch reset flag (*) + * @arg RCC_FLAG_D2RST: D2 domain power switch reset flag (*) + * @arg RCC_FLAG_CDRST: CD domain power switch reset flag (*) + * @arg RCC_FLAG_BORRST: BOR reset flag + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: System reset from CPU reset flag + * @arg RCC_FLAG_BORRST: D2 domain power switch reset flag + * @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset + * @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset + * @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag + * @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + * + * (*) Available on some STM32H7 lines only. + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ +((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR)))) & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U) +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos) + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32h7xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ + +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms */ +#define CSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms */ +#define PLL_FRAC_TIMEOUT_VALUE (1U) /* PLL Fractional part waiting time before new latch enable : 1 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ +#define RCC_DBP_TIMEOUT_VALUE (100U) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ + (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)) + +#if defined(RCC_CR_HSEEXT) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL)) +#else +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) +#endif /* RCC_CR_HSEEXT */ + +#if defined(RCC_BDCR_LSEEXT) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL)) +#else +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) +#endif /* RCC_BDCR_LSEEXT */ + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ + ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \ + ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8)) + +#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ + ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_NONE) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \ + ((VALUE) == RCC_PLL1VCIRANGE_1) || \ + ((VALUE) == RCC_PLL1VCIRANGE_2) || \ + ((VALUE) == RCC_PLL1VCIRANGE_3)) + +#define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM)) + +#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) + +#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#if !defined(RCC_VER_2_0) +#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#else +#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U)) +#endif /* !RCC_VER_2_0 */ +#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ + ((VALUE) == RCC_PLL1_DIVQ) || \ + ((VALUE) == RCC_PLL1_DIVR)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1) || ((SYSCLK) == RCC_SYSCLK_DIV2) || \ + ((SYSCLK) == RCC_SYSCLK_DIV4) || ((SYSCLK) == RCC_SYSCLK_DIV8) || \ + ((SYSCLK) == RCC_SYSCLK_DIV16) || ((SYSCLK) == RCC_SYSCLK_DIV64) || \ + ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \ + ((SYSCLK) == RCC_SYSCLK_DIV512)) + + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ + ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ + ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ + ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ + ((HCLK) == RCC_HCLK_DIV512)) + +#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \ + ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \ + ((CDPCLK1) == RCC_APB3_DIV16)) + +#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */ + +#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \ + ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \ + ((PCLK1) == RCC_APB1_DIV16)) + +#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \ + ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \ + ((PCLK2) == RCC_APB2_DIV16)) + +#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \ + ((SRDPCLK1) == RCC_APB4_DIV4) || ((SRDPCLK1) == RCC_APB4_DIV8) || \ + ((SRDPCLK1) == RCC_APB4_DIV16)) + +#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/ + +#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63)) + +#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK) || \ + ((SOURCE) == RCC_MCO2SOURCE_CSICLK) || ((SOURCE) == RCC_MCO2SOURCE_LSICLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5) || ((DIV) == RCC_MCODIV_6) || \ + ((DIV) == RCC_MCODIV_7) || ((DIV) == RCC_MCODIV_8) || \ + ((DIV) == RCC_MCODIV_9) || ((DIV) == RCC_MCODIV_10) || \ + ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12) || \ + ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14) || \ + ((DIV) == RCC_MCODIV_15)) + +#if defined(DUAL_CORE) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_C1RST) || ((FLAG) == RCC_FLAG_C2RST) || \ + ((FLAG) == RCC_FLAG_SFTR2ST) || ((FLAG) == RCC_FLAG_WWDG2RST)|| \ + ((FLAG) == RCC_FLAG_IWDG2RST) || ((FLAG) == RCC_FLAG_D1RST) || \ + ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTR1ST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV)) + +#else + +#if defined(RCC_CR_D2CKRDY) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_D1CKRDY) || ((FLAG) == RCC_FLAG_D2CKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_CPURST) || ((FLAG) == RCC_FLAG_D1RST) || \ + ((FLAG) == RCC_FLAG_D2RST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#else +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_CSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_CPUCKRDY) || ((FLAG) == RCC_FLAG_CDCKRDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_PLL2RDY) || \ + ((FLAG) == RCC_FLAG_PLL3RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || \ + ((FLAG) == RCC_FLAG_CDRST) || ((FLAG) == RCC_FLAG_BORRST) || \ + ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ + ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDG1RST)|| \ + ((FLAG) == RCC_FLAG_WWDG1RST) || ((FLAG) == RCC_FLAG_LPWR1RST)|| \ + ((FLAG) == RCC_FLAG_LPWR2RST) || ((FLAG) == RCC_FLAG_HSIDIV )) +#endif /* RCC_CR_D2CKRDY */ + +#endif /*DUAL_CORE*/ + +#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU) +#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU) + +#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \ + ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI)) + +#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \ + ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_RCC_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h new file mode 100644 index 0000000..2fb1fd2 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -0,0 +1,4482 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_RCC_EX_H +#define STM32H7xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief PLL2 Clock structure definition + */ +typedef struct +{ + + uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ + + uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + or between Min_Data = 8 and Max_Data = 420(*) + (*) : For stm32h7a3xx and stm32h7b3xx family lines. */ + + uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed */ + + uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + uint32_t PLL2RGE; /*!CR, RCC_CR_PLL2ON) +#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) + +/** + * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled, + * This is mainly used to save Power. + * @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) + +#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) + +/** + * @brief Macro to configures the PLL2 multiplication and division factors. + * @note This function must be used only when PLL2 is disabled. + * + * @param __PLL2M__ specifies the division factor for PLL2 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock + * This parameter must be a number between 4 and 512 or between 8 and 420(*). + * @note You have to set the PLL2N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL2P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @param __PLL2R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128. + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL2P__, __PLL2Q__ or __PLL2R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + */ + +#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \ + do{ \ + MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \ + WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \ + ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \ + } while(0) + +/** + * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO + * + * @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 + * 150 to 420 MHz if PLL2VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)) + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__)) + + +/** @brief Macro to select the PLL2 reference frequency range. + * @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__)) + +/** @brief Macros to enable or disable the main PLL3. + * @note After enabling PLL3, the application software should wait on + * PLL3RDY flag to be set indicating that PLL3 clock is stable and can + * be used as kernel clock source. + * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) +#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) + +/** + * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) + * @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled, + * This is mainly used to save Power. + * @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted + * This parameter can be one of the following values: + * @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) + +#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__)) + +/** + * @brief Macro to configures the PLL3 multiplication and division factors. + * @note This function must be used only when PLL3 is disabled. + * + * @param __PLL3M__ specifies the division factor for PLL3 VCO input clock + * This parameter must be a number between 1 and 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 16 MHz. + * + * @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLL3N parameter correctly to ensure that the VCO + * output frequency is between 150 and 420 MHz (when in medium VCO range) or + * between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range) + * + * @param __PLL3P__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 2 and 128 (where odd numbers not allowed) + * + * @param __PLL3Q__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @param __PLL3R__ specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * + * @note To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) + * is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible + * value to __PLL3P__, __PLL3Q__ or __PLL3R__ parameters. + * @retval None + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + */ + +#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \ + do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \ + WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \ + ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \ + } while(0) + + + +/** + * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor + * + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO + * + * @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO + * It should be a value between 0 and 8191 + * @note Warning: the software has to set correctly these bits to insure that the VCO + * output frequency is between its valid frequency range, which is: + * 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 + * 150 to 420 MHz if PLL3VCOSEL = 1. + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz + * @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz + * @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__)) + + +/** @brief Macro to select the PLL3 reference frequency range. + * @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*) + * @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz + * + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * + * @retval None + */ +#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__)) +/** + * @brief Macro to Configure the SAI1 clock source. + * @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL + * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 + * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 + * @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC + * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock + * @retval None + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#else +#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SAI1SEL */ + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL + * @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2 + * @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3 + * @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP + * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL))) +#else +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL))) +#endif /* RCC_D2CCIP1R_SAI1SEL */ + +/** + * @brief Macro to Configure the SPDIFRX clock source. + * @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived + * from system PLL, PLL2, PLL3, or internal OSC clock + * This parameter can be one of the following values: + * @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL + * @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2 + * @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3 + * @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#else +#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__)) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ + +/** + * @brief Macro to get the SPDIFRX clock source. + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL))) +#else +#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL))) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ + +#if defined(SAI3) +/** + * @brief Macro to Configure the SAI2/3 clock source. + * @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL + * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 + * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 + * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP + * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__)) + +/** @brief Macro to get the SAI2/3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL + * @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2 + * @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3 + * @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP + * @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock + */ +#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL))) + +/** + * @brief Macro to Configure the SAI2 clock source. + * @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI2_CONFIG __HAL_RCC_SAI23_CONFIG + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock + */ +#define __HAL_RCC_GET_SAI2_SOURCE __HAL_RCC_GET_SAI23_SOURCE + +/** + * @brief Macro to Configure the SAI3 clock source. + * @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL + * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 + * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 + * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP + * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG + +/** @brief Macro to get the SAI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL + * @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2 + * @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3 + * @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP + * @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock + */ +#define __HAL_RCC_GET_SAI3_SOURCE __HAL_RCC_GET_SAI23_SOURCE +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +/** + * @brief Macro to Configure the SAI2A clock source. + * @param __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__)) + +/** @brief Macro to get the SAI2A clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL + * @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2 + * @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3 + * @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock = CLKP + * @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock + * @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +/** + * @brief Macro to Configure the SAI2B clock source. + * @param __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + * @retval None + */ +#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__)) + +/** @brief Macro to get the SAI2B clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL + * @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2 + * @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3 + * @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock = CLKP + * @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock + * @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock + */ +#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL))) +#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */ + + +#if defined(SAI4_Block_A) +/** + * @brief Macro to Configure the SAI4A clock source. + * @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL + * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2 + * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3 + * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP + * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__)) + +/** @brief Macro to get the SAI4A clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock + */ +#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL))) +#endif /* SAI4_Block_A */ + +#if defined(SAI4_Block_B) +/** + * @brief Macro to Configure the SAI4B clock source. + * @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock + * @retval None + */ +#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__)) + +/** @brief Macro to get the SAI4B clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL + * @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2 + * @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3 + * @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP + * @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock + */ +#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL))) +#endif /* SAI4_Block_B */ + +/** @brief macro to configure the I2C1/2/3/5* clock (I2C123CLK). + * + * @param __I2C1235CLKSource__ specifies the I2C1/2/3/5* clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_I2C123_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C1235CLKSource__)) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__)) +/* alias */ +#define __HAL_RCC_I2C123_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* RCC_D2CCIP2R_I2C123SEL */ + +/** @brief macro to get the I2C1/2/3/5* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock + * @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock + * + * (**): Available on stm32h72xxx and stm32h73xxx family lines. + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL))) +#elif defined(RCC_CDCCIP2R_I2C123SEL) +#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL))) +#else /* RCC_D2CCIP2R_I2C1235SEL */ +#define __HAL_RCC_GET_I2C1235_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL))) +/* alias */ +#define __HAL_RCC_GET_I2C123_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* RCC_D2CCIP2R_I2C123SEL */ + +/** @brief macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1CLKSource__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C1_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2CLKSource__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3CLKSource__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock + */ +#if defined(I2C5) +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C1235_CONFIG +#else +#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG +#endif /*I2C5*/ + +/** @brief macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock + */ +#if defined(I2C5) +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#else +#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE +#endif /*I2C5*/ + +/** @brief macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4CLKSource__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock + */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#else +#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__)) +#endif /* RCC_D3CCIPR_I2C4SEL */ + +/** @brief macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock + */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL))) +#else +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL))) +#endif /* RCC_D3CCIPR_I2C4SEL */ + +#if defined(I2C5) +/** @brief macro to configure the I2C5 clock (I2C5CLK). + * + * @param __I2C5CLKSource__ specifies the I2C5 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock + */ +#define __HAL_RCC_I2C5_CONFIG __HAL_RCC_I2C1235_CONFIG +#endif /* I2C5 */ + +#if defined(I2C5) +/** @brief macro to get the I2C5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C5CLKSOURCE_D2PCLK1: D2PCLK5 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_PLL3: PLL3 selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_HSI: HSI selected as I2C5 clock + * @arg RCC_I2C5CLKSOURCE_CSI: CSI selected as I2C5 clock + */ +#define __HAL_RCC_GET_I2C5_SOURCE __HAL_RCC_GET_I2C1235_SOURCE +#endif /* I2C5 */ + +/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK). + * + * @param __USART16910CLKSource__ specifies the USART1/6/9* /10* clock source. + * This parameter can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define __HAL_RCC_USART16_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16910CLKSource__)) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__)) +/* alias */ +#define __HAL_RCC_USART16_CONFIG __HAL_RCC_USART16910_CONFIG +#endif /* RCC_D2CCIP2R_USART16SEL */ + +/** @brief macro to get the USART1/6/9* /10* clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock + * @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock + * + * (*) : Available on some STM32H7 lines only. + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL))) +#elif defined(RCC_CDCCIP2R_USART16910SEL) +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL))) +/* alias*/ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#else /* RCC_D2CCIP2R_USART16910SEL */ +#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL))) +/* alias */ +#define __HAL_RCC_GET_USART16_SOURCE __HAL_RCC_GET_USART16910_SOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ + +/** @brief macro to configure the USART234578 clock (USART234578CLK). + * + * @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock + */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__)) +#else +#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__)) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +/** @brief macro to get the USART2/3/4/5/7/8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock + * @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock + */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL))) +#else +#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL))) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +/** @brief macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1CLKSource__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE __HAL_RCC_GET_USART16_SOURCE + +/** @brief macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2CLKSource__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3CLKSource__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4CLKSource__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5CLKSource__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6CLKSource__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_USART6_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE __HAL_RCC_GET_USART16_SOURCE + +/** @brief macro to configure the UART5 clock (UART7CLK). + * + * @param __UART7CLKSource__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_UART7_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +/** @brief macro to configure the UART8 clock (UART8CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_UART8_CONFIG __HAL_RCC_USART234578_CONFIG + +/** @brief macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE __HAL_RCC_GET_USART234578_SOURCE + +#if defined(UART9) +/** @brief macro to configure the UART9 clock (UART9CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_UART9_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the UART9 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock + * @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock + * @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock + */ +#define __HAL_RCC_GET_UART9_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* UART9 */ + +#if defined(USART10) +/** @brief macro to configure the USART10 clock (USART10CLK). + * + * @param __UART8CLKSource__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_USART10_CONFIG __HAL_RCC_USART16_CONFIG + +/** @brief macro to get the USART10 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock + * @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock + */ +#define __HAL_RCC_GET_USART10_SOURCE __HAL_RCC_GET_USART16_SOURCE +#endif /* USART10 */ + +/** @brief macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1CLKSource__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock + */ +#if defined (RCC_D3CCIPR_LPUART1SEL) +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#else +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__)) +#endif /* RCC_D3CCIPR_LPUART1SEL */ + +/** @brief macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock + * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock + */ +#if defined (RCC_D3CCIPR_LPUART1SEL) +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL))) +#else +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL))) +#endif /* RCC_D3CCIPR_LPUART1SEL */ + +/** @brief macro to configure the LPTIM1 clock source. + * + * @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) +#else +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__)) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ + +/** @brief macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL))) +#else +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL))) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ + +/** @brief macro to configure the LPTIM2 clock source. + * + * @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock + */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) +#else +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ + +/** @brief macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock + * @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock + */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL))) +#else +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL))) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ + +/** @brief macro to configure the LPTIM3/4/5 clock source. + * + * @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source. + * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock + */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__)) +#else +#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__)) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ + +/** @brief macro to get the LPTIM3/4/5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock + * @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock + */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL))) +#else +#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL))) +#endif /* RCC_D3CCIPR_LPTIM345SEL */ + +/** @brief macro to configure the LPTIM3 clock source. + * + * @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source. + * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock + */ +#define __HAL_RCC_LPTIM3_CONFIG __HAL_RCC_LPTIM345_CONFIG + +/** @brief macro to get the LPTIM3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock + * @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock + */ +#define __HAL_RCC_GET_LPTIM3_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE + +#if defined(LPTIM4) +/** @brief macro to configure the LPTIM4 clock source. + * + * @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source. + * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock + */ +#define __HAL_RCC_LPTIM4_CONFIG __HAL_RCC_LPTIM345_CONFIG + + +/** @brief macro to get the LPTIM4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock + * @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock + */ +#define __HAL_RCC_GET_LPTIM4_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM4 */ + +#if defined(LPTIM5) +/** @brief macro to configure the LPTIM5 clock source. + * + * @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source. + * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock + */ +#define __HAL_RCC_LPTIM5_CONFIG __HAL_RCC_LPTIM345_CONFIG + + +/** @brief macro to get the LPTIM5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock + * @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock + */ +#define __HAL_RCC_GET_LPTIM5_SOURCE __HAL_RCC_GET_LPTIM345_SOURCE +#endif /* LPTIM5 */ + +#if defined(QUADSPI) +/** @brief macro to configure the QSPI clock source. + * + * @param __QSPICLKSource__ specifies the QSPI clock source. + * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock + */ +#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__)) + + +/** @brief macro to get the QSPI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock + * @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock + */ +#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL))) +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @brief macro to configure the OSPI clock source. + * + * @param __OSPICLKSource__ specifies the OSPI clock source. + * @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#else +#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__)) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ + +/** @brief macro to get the OSPI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL : PLL1_Q Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_PLL2 : PLL2_R Clock selected as OSPI clock + * @arg RCC_RCC_OSPICLKSOURCE_CLKP CLKP selected as OSPI clock + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL))) +#else +#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL))) +#endif /* RCC_CDCCIPR_OCTOSPISEL */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + + +#if defined(DSI) +/** @brief macro to configure the DSI clock source. + * + * @param __DSICLKSource__ specifies the DSI clock source. + * @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock + * @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock + */ +#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__)) + + +/** @brief macro to get the DSI clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock + * @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock + */ +#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL))) +#endif /*DSI*/ + +/** @brief macro to configure the FMC clock source. + * + * @param __FMCCLKSource__ specifies the FMC clock source. + * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) +#else +#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__)) +#endif /* RCC_D1CCIPR_FMCSEL */ + +/** @brief macro to get the FMC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock + * @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL))) +#else +#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL))) +#endif /* RCC_D1CCIPR_FMCSEL */ + +/** @brief Macro to configure the USB clock (USBCLK). + * @param __USBCLKSource__ specifies the USB clock source. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock + * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#else +#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__)) +#endif /* RCC_D2CCIP2R_USBSEL */ + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock + * @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock + * @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL))) +#else +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL))) +#endif /* RCC_D2CCIP2R_USBSEL */ + +/** @brief Macro to configure the ADC clock + * @param __ADCCLKSource__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#else +#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__)) +#endif /* RCC_D3CCIPR_ADCSEL */ + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock + * @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL))) +#else +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) +#endif /* RCC_D3CCIPR_ADCSEL */ + +/** @brief Macro to configure the SWPMI1 clock + * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock + * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#else +#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) +#endif /* RCC_D2CCIP1R_SWPSEL */ + +/** @brief Macro to get the SWPMI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock + * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL))) +#else +#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) +#endif /* RCC_D2CCIP1R_SWPSEL */ + +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#else +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock + */ +#if defined (RCC_D2CCIP1R_DFSDM1SEL) +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL))) +#else +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL))) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ + +#if defined(DFSDM2_BASE) +/** @brief Macro to configure the DFSDM2 clock + * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) + +/** @brief Macro to get the DFSDM2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) Clock selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ +#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL))) +#endif /* DFSDM2 */ + +/** @brief macro to configure the CEC clock (CECCLK). + * + * @param __CECCLKSource__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#else +#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) +#endif /* RCC_D2CCIP2R_CECSEL */ + +/** @brief macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock + * @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL))) +#else +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL))) +#endif /* RCC_D2CCIP2R_CECSEL */ + +/** @brief Macro to configure the CLKP : Oscillator clock for peripheral + * @param __CLKPSource__ specifies Oscillator clock for peripheral + * This parameter can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#else +#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__)) +#endif /* RCC_D1CCIPR_CKPERSEL */ + +/** @brief Macro to get the Oscillator clock for peripheral source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral + * @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL))) +#else +#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL))) +#endif /* RCC_D1CCIPR_CKPERSEL */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @brief Macro to configure the FDCAN clock + * @param __FDCANCLKSource__ specifies clock source for FDCAN + * This parameter can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#else +#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__)) +#endif /* RCC_D2CCIP1R_FDCANSEL */ + +/** @brief Macro to get the FDCAN clock + * @retval The clock source can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL))) +#else +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL))) +#endif /* RCC_D2CCIP1R_FDCANSEL */ + +#endif /*FDCAN1 || FDCAN2*/ + +/** + * @brief Macro to Configure the SPI1/2/3 clock source. + * @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL + * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 + * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 + * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP + * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#else +#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI123SEL */ + +/** @brief Macro to get the SPI1/2/3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL + * @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2 + * @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3 + * @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP + * @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL))) +#else +#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL))) +#endif /* RCC_D2CCIP1R_SPI123SEL */ + +/** + * @brief Macro to Configure the SPI1 clock source. + * @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL + * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 + * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 + * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP + * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI1_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL + * @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2 + * @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3 + * @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP + * @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock + */ +#define __HAL_RCC_GET_SPI1_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI2 clock source. + * @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL + * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 + * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 + * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP + * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI2_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL + * @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2 + * @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3 + * @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP + * @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock + */ +#define __HAL_RCC_GET_SPI2_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI3 clock source. + * @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived + * from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) + * This parameter can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL + * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 + * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 + * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP + * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock + * @retval None + */ +#define __HAL_RCC_SPI3_CONFIG __HAL_RCC_SPI123_CONFIG + +/** @brief Macro to get the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL + * @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2 + * @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3 + * @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP + * @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock + */ +#define __HAL_RCC_GET_SPI3_SOURCE __HAL_RCC_GET_SPI123_SOURCE + +/** + * @brief Macro to Configure the SPI4/5 clock source. + * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 + * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 + * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 + * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI + * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI + * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE + * @retval None + */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#else +#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\ + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__)) +#endif /* RCC_D2CCIP1R_SPI45SEL */ + +/** @brief Macro to get the SPI4/5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 + * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 + * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 + * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI + * @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI + * @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE +*/ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL))) +#else +#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL))) +#endif /* RCC_D2CCIP1R_SPI45SEL */ + +/** + * @brief Macro to Configure the SPI4 clock source. + * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 + * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 + * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 + * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI + * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI + * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE + * @retval None + */ +#define __HAL_RCC_SPI4_CONFIG __HAL_RCC_SPI45_CONFIG + +/** @brief Macro to get the SPI4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 + * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 + * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 + * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI + * @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI + * @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE +*/ +#define __HAL_RCC_GET_SPI4_SOURCE __HAL_RCC_GET_SPI45_SOURCE + +/** + * @brief Macro to Configure the SPI5 clock source. + * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 + * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 + * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 + * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI + * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI + * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE + * @retval None + */ +#define __HAL_RCC_SPI5_CONFIG __HAL_RCC_SPI45_CONFIG + +/** @brief Macro to get the SPI5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 + * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 + * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 + * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI + * @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI + * @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE +*/ +#define __HAL_RCC_GET_SPI5_SOURCE __HAL_RCC_GET_SPI45_SOURCE + +/** + * @brief Macro to Configure the SPI6 clock source. + * @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived + * from system PCLK, PLL2, PLL3, OSC + * This parameter can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 + * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 + * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 + * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI + * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI + * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*) + * + * @retval None + * + * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines. + * + */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#else +#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__)) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +/** @brief Macro to get the SPI6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1 + * @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2 + * @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3 + * @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI + * @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI + * @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE + * @arg RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN +*/ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL))) +#else +#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL))) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +/** @brief Macro to configure the SDMMC clock + * @param __SDMMCCLKSource__ specifies clock source for SDMMC + * This parameter can be one of the following values: + * @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock + * @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#else +#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \ + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__)) +#endif /* RCC_D1CCIPR_SDMMCSEL */ + +/** @brief Macro to get the SDMMC clock + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL))) +#else +#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL))) +#endif /* RCC_D1CCIPR_SDMMCSEL */ + +/** @brief macro to configure the RNG clock (RNGCLK). + * + * @param __RNGCLKSource__ specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#else +#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \ + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__)) +#endif /* RCC_D2CCIP2R_RNGSEL */ + +/** @brief macro to get the RNG clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL))) +#else +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL))) +#endif /* RCC_D2CCIP2R_RNGSEL */ + +#if defined(HRTIM1) +/** @brief Macro to configure the HRTIM1 prescaler clock source. + * @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock + * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__)) + +/** @brief Macro to get the HRTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock + * @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock + */ +#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL))) +#endif /* HRTIM1 */ + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, + * else it is equal to 2 x Frcc_pclkx_d2 (default after reset) + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to 4 x Frcc_pclkx_d2 + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\ + RCC->CFGR |= (__PRESC__); \ + }while(0) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line. + * @retval None + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4. + * @retval None + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Event Line for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS) + + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS) + +#if defined(DUAL_CORE) +/** + * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4. + * @retval EXTI RCC LSE CSS Line Status. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS) + +/** + * @brief Clear the RCC LSE CSS EXTI flag or not for CM4. + * @retval None. + */ +#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) +#endif /* DUAL_CORE */ +/** + * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line. + * @retval None. + */ +#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after pre-scaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + + +/** + * @} + */ + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); +uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); +uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); +uint32_t HAL_RCCEx_GetD1SysClockFreq(void); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSECSS_IT(void); +void HAL_RCCEx_LSECSS_IRQHandler(void); +void HAL_RCCEx_LSECSS_Callback(void); +#if defined(DUAL_CORE) +void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx); +#endif /*DUAL_CORE*/ +#if defined(RCC_GCR_WW1RSC) +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); +#endif /*RCC_GCR_WW1RSC*/ +/** + * @} + */ + + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ + +#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \ + ((VALUE) == RCC_PLL2_DIVQ) || \ + ((VALUE) == RCC_PLL2_DIVR)) + +#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \ + ((VALUE) == RCC_PLL3_DIVQ) || \ + ((VALUE) == RCC_PLL3_DIVR)) + +#if defined(RCC_D2CCIP2R_USART16SEL) +#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +#else +#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART16CLKSOURCE_HSI)) +/* alias*/ +#define IS_RCC_USART16910CLKSOURCE IS_RCC_USART16CLKSOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ + +#if defined(RCC_D2CCIP2R_USART28SEL) +#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#else +#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART234578CLKSOURCE_HSI)) +#endif /* RCC_D2CCIP2R_USART28SEL */ + +#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART2CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) + +#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_USART3CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) + +#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) + +#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) + +#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART6CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) + +#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) + +#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) + +#if defined(UART9) +#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART9CLKSOURCE_HSI)) +#endif + +#if defined(USART10) +#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART10CLKSOURCE_HSI)) +#endif + +#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) + +#if defined(I2C5) +#define IS_RCC_I2C1235CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1235CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_I2C1235CLKSOURCE_CSI)) + +#define IS_RCC_I2C123CLKSOURCE IS_RCC_I2C1235CLKSOURCE /* For API Backward compatibility */ +#else +#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C123CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C123CLKSOURCE_CSI)) +#endif /*I2C5*/ + +#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C1CLKSOURCE_CSI)) + +#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C2CLKSOURCE_CSI)) + +#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) + +#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_I2C4CLKSOURCE_CSI)) + +#if defined(I2C5) +#define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_I2C5CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_I2C5CLKSOURCE_CSI)) +#endif /*I2C5*/ + +#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \ + ((SOURCE) == RCC_RNGCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_RNGCLKSOURCE_LSE) || \ + ((SOURCE) == RCC_RNGCLKSOURCE_LSI)) + +#if defined(HRTIM1) +#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \ + ((SOURCE) == RCC_HRTIM1CLK_CPUCLK)) +#endif + +#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_USBCLKSOURCE_HSI48)) + +#define IS_RCC_SAI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) + +#if defined(SAI3) +#define IS_RCC_SAI23CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN)) + +#define IS_RCC_SAI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) + + +#define IS_RCC_SAI3CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define IS_RCC_SAI2ACLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF)) +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define IS_RCC_SAI2BCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF)) +#endif + +#define IS_RCC_SPI123CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN)) + +#define IS_RCC_SPI1CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN)) + +#define IS_RCC_SPI2CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN)) + +#define IS_RCC_SPI3CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) + +#define IS_RCC_SPI45CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) + +#define IS_RCC_SPI4CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) + +#define IS_RCC_SPI5CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE)) + +#if defined(RCC_D3CCIPR_SPI6SEL) +#define IS_RCC_SPI6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)) +#else +#define IS_RCC_SPI6CLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN)) +#endif /* RCC_D3CCIPR_SPI6SEL */ + +#if defined(SAI4) +#define IS_RCC_SAI4ACLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN)) + +#define IS_RCC_SAI4BCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \ + ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN)) +#endif /*SAI4*/ + +#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) +#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) || \ + ((VALUE) == RCC_PLL2VCIRANGE_1) || \ + ((VALUE) == RCC_PLL2VCIRANGE_2) || \ + ((VALUE) == RCC_PLL2VCIRANGE_3)) + +#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) || \ + ((VALUE) == RCC_PLL3VCIRANGE_1) || \ + ((VALUE) == RCC_PLL3VCIRANGE_2) || \ + ((VALUE) == RCC_PLL3VCIRANGE_3)) + +#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) || \ + ((VALUE) == RCC_PLL2VCOMEDIUM)) + +#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ + ((VALUE) == RCC_PLL3VCOMEDIUM)) + +#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP)) + +#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP)) + +#if defined(LPTIM4) +#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP)) +#endif /* LPTIM4*/ + +#if defined(LPTIM5) +#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP)) +#endif /*LPTIM5*/ + +#if defined(QUADSPI) +#define IS_RCC_QSPICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP)) +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI1) +#define IS_RCC_OSPICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP)) +#endif /*OCTOSPI1 || OCTOSPI1*/ + +#if defined(DSI) +#define IS_RCC_DSICLK(__SOURCE__) \ + (((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \ + ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2)) +#endif /*DSI*/ + +#define IS_RCC_FMCCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) || \ + ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP)) + +#if defined(FDCAN1) || defined(FDCAN2) +#define IS_RCC_FDCANCLK(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2)) +#endif /*FDCAN1 || FDCAN2*/ + +#define IS_RCC_SDMMC(__SOURCE__) \ + (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2)) + +#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_ADCCLKSOURCE_CLKP)) + +#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS)) + +#if defined(DFSDM2_BASE) +#define IS_RCC_DFSDM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \ + ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS)) +#endif /*DFSDM2*/ + +#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \ + ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_CSI)) + +#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_CSI) || \ + ((SOURCE) == RCC_CLKPSOURCE_HSE)) +#define IS_RCC_TIMPRES(VALUE) \ + (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ + ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined(DUAL_CORE) +#define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \ + ((CORE) == RCC_BOOT_C2)) +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +#define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \ + ((WWDG) == RCC_WWDG2)) +#else +#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1) + +#endif /*DUAL_CORE*/ + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_RCC_EX_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h new file mode 100644 index 0000000..cee1ffd --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h @@ -0,0 +1,236 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_sdram.h + * @author MCD Application Team + * @brief Header file of SDRAM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_SDRAM_H +#define STM32H7xx_HAL_SDRAM_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_fmc.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SDRAM + * @{ + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup SDRAM_Exported_Types SDRAM Exported Types + * @{ + */ + +/** + * @brief HAL SDRAM State structure definition + */ +typedef enum +{ + HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ + HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ + HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ + HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ + HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ + HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ + +} HAL_SDRAM_StateTypeDef; + +/** + * @brief SDRAM handle Structure definition + */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +typedef struct __SDRAM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +{ + FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ + + FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ + + __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ + + HAL_LockTypeDef Lock; /*!< SDRAM locking object */ + + MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */ + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ + void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ + void (* DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma); /*!< SDRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma); /*!< SDRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} SDRAM_HandleTypeDef; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SDRAM Callback ID enumeration definition + */ +typedef enum +{ + HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */ + HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */ + HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ + HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ + HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ +} HAL_SDRAM_CallbackIDTypeDef; + +/** + * @brief HAL SDRAM Callback pointer definition + */ +typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); +typedef void (*pSDRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros + * @{ + */ + +/** @brief Reset SDRAM handle state + * @param __HANDLE__ specifies the SDRAM handle. + * @retval None + */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @addtogroup SDRAM_Exported_Functions_Group1 + * @{ + */ + +/* Initialization/de-initialization functions *********************************/ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); + +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); +void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma); +void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/* SDRAM callback registering/unregistering */ +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group3 + * @{ + */ +/* SDRAM Control functions *****************************************************/ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); + +/** + * @} + */ + +/** @addtogroup SDRAM_Exported_Functions_Group4 + * @{ + */ +/* SDRAM State functions ********************************************************/ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_SDRAM_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h new file mode 100644 index 0000000..6daa529 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h @@ -0,0 +1,2462 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_TIM_H +#define STM32H7xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +#if defined(TIM_BDTR_BKBID) + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + +#endif /* TIM_BDTR_BKBID */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#if defined(TIM_BREAK_INPUT_SUPPORT) +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#endif /* TIM_BREAK_INPUT_SUPPORT */ +#define TIM_DMABASE_TISEL 0x0000001AU +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ +#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ +#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ +#endif /*TIM_BDTR_BKBID */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ +#if defined(TIM_BDTR_BKBID) + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ +#endif /* TIM_BDTR_BKBID */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ +#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ +#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ +#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ +#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ +#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ +#define TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) */ +#define TIM_TS_ITR13 (TIM_SMCR_TS_0 | TIM_SMCR_TS_4) /*!< Internal Trigger 13 (ITR13) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL)) + + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENABLE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ + ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) +#if defined(TIM_BDTR_BKBID) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + +#endif /* TIM_BDTR_BKBID */ + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR4) || \ + ((__SELECTION__) == TIM_TS_ITR5) || \ + ((__SELECTION__) == TIM_TS_ITR6) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_ITR12) || \ + ((__SELECTION__) == TIM_TS_ITR13) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32h7xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_TIM_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h new file mode 100644 index 0000000..ebad016 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_TIM_EX_H +#define STM32H7xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity + Not relevant when analog watchdog output of the DFSDM1 used as break input source */ +} TIMEx_BreakInputConfigTypeDef; + +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM8_ETR_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */ +#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */ +#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */ +#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */ +#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */ +#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ +#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */ + +#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ +#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */ + +#define TIM_TIM5_ETR_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */ +#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */ +#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */ +#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */ +#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */ + +#define TIM_TIM23_ETR_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */ +#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */ +#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */ + +#define TIM_TIM24_ETR_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */ +#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */ +#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */ +#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */ +#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */ +/** + * @} + */ +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1_TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ + +#define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8_TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP2 OUT */ + +#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to GPIO */ +#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ +#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */ + +#define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3_TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ +#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ +#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5_TI1 is connected to GPIO */ +#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to CAN TMP */ +#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to CAN RTP */ + +#define TIM_TIM12_TI1_GPIO 0x00000000U /*!< TIM12 TI1 is connected to GPIO */ +#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 TI1 is connected to SPDIF FS */ + +#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 CH1 */ +#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to TIM4 CH1 */ +#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15_TI1 is connected to RCC LSE */ +#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to RCC CSI */ +#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to RCC MCO2 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM3 CH2 */ +#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM4 CH2 */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 TI1 is connected to RCC LSI */ +#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to RCC LSE */ +#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to WKUP_IT */ + +#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 TI1 is connected to SPDIF FS */ +#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to RCC HSE 1Mhz */ +#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to RCC MCO1 */ + +#define TIM_TIM23_TI4_GPIO 0x00000000U /*!< TIM23_TI4 is connected to GPIO */ +#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23_TI4 is connected to COMP1 OUT */ +#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23_TI4 is connected to COMP2 OUT */ +#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM24_TI1_GPIO 0x00000000U /*!< TIM24_TI1 is connected to GPIO */ +#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24_TI1 is connected to CAN TMP */ +#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24_TI1 is connected to CAN RTP */ +#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24_TI1 is connected to CAN SOC */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\ + ((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\ + ((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\ + ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\ + ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\ + ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\ + ((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\ + ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\ + ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\ + ((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\ + ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\ + ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\ + ((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\ + ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\ + ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\ + ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\ + ((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\ + ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC)) + +#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\ + ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\ + ((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\ + ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\ + ((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\ + ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined(TIM_BREAK_INPUT_SUPPORT) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* TIM_BREAK_INPUT_SUPPORT */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); +#if defined(TIM_BDTR_BKBID) + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +#endif /* TIM_BDTR_BKBID */ +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_TIM_EX_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h new file mode 100644 index 0000000..fd48624 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h @@ -0,0 +1,2450 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_bdma.h + * @author MCD Application Team + * @brief Header file of BDMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_BDMA_H +#define STM32H7xx_LL_BDMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_dmamux.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (BDMA) || defined (BDMA1) || defined (BDMA2) + +/** @defgroup BDMA_LL BDMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup BDMA_LL_Private_Variables BDMA Private Variables + * @{ + */ +/* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */ +static const uint8_t LL_BDMA_CH_OFFSET_TAB[] = +{ + (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE), + (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE), + (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE), + (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE), + (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE), + (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE), + (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE), + (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE) +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup BDMA_LL_Private_Macros BDMA Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref BDMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref BDMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref BDMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref BDMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX2_Request_selection + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref BDMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */ + +} LL_BDMA_InitTypeDef; +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants + * @{ + */ +/** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_BDMA_WriteReg function + * @{ + */ +#define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_BDMA_ReadReg function + * @{ + */ +#define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0 /*!< Channel 1 global flag */ +#define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0 /*!< Channel 1 transfer complete flag */ +#define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0 /*!< Channel 1 half transfer flag */ +#define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0 /*!< Channel 1 transfer error flag */ +#define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions + * @{ + */ +#define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_BDMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define LL_BDMA_CHANNEL_1 0x00000001U /*!< BDMA Channel 1 */ +#define LL_BDMA_CHANNEL_2 0x00000002U /*!< BDMA Channel 2 */ +#define LL_BDMA_CHANNEL_3 0x00000003U /*!< BDMA Channel 3 */ +#define LL_BDMA_CHANNEL_4 0x00000004U /*!< BDMA Channel 4 */ +#define LL_BDMA_CHANNEL_5 0x00000005U /*!< BDMA Channel 5 */ +#define LL_BDMA_CHANNEL_6 0x00000006U /*!< BDMA Channel 6 */ +#define LL_BDMA_CHANNEL_7 0x00000007U /*!< BDMA Channel 7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_BDMA_CHANNEL_ALL 0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_BDMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + * @{ + */ +#define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_BDMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_BDMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_BDMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros + * @{ + */ + +/** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in BDMA register + * @param __INSTANCE__ BDMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in BDMA register + * @param __INSTANCE__ BDMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely + * @{ + */ +/** + * @brief Convert BDMAx_Channely into BDMAx + * @param __CHANNEL_INSTANCE__ BDMAx_Channely + * @retval BDMAx + */ +#if defined (BDMA1) +#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA) +#else +#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA) +#endif /* BDMA1 */ + +/** + * @brief Convert BDMAx_Channely into LL_BDMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ BDMAx_Channely + * @retval LL_BDMA_CHANNEL_y + */ +#if defined (BDMA1) +#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \ +LL_BDMA_CHANNEL_7) +#else +#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \ + LL_BDMA_CHANNEL_7) +#endif /* BDMA1 */ + +/** + * @brief Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely + * @param __BDMA_INSTANCE__ BDMAx + * @param __CHANNEL__ LL_BDMA_CHANNEL_y + * @retval BDMAx_Channely + */ +#if defined (BDMA1) +#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \ + BDMA1_Channel7) +#else +#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \ + (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \ + BDMA_Channel7) +#endif /* BDMA1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions + * @{ + */ + +/** @defgroup BDMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable BDMA channel. + * @rmtoll CCR EN LL_BDMA_EnableChannel + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN); +} + +/** + * @brief Disable BDMA channel. + * @rmtoll CCR EN LL_BDMA_DisableChannel + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN); +} + +/** + * @brief Check if BDMA channel is enabled or disabled. + * @rmtoll CCR EN LL_BDMA_IsEnabledChannel + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters link to BDMA transfer. + * @rmtoll CCR DIR LL_BDMA_ConfigTransfer\n + * CCR MEM2MEM LL_BDMA_ConfigTransfer\n + * CCR CIRC LL_BDMA_ConfigTransfer\n + * CCR PINC LL_BDMA_ConfigTransfer\n + * CCR MINC LL_BDMA_ConfigTransfer\n + * CCR PSIZE LL_BDMA_ConfigTransfer\n + * CCR MSIZE LL_BDMA_ConfigTransfer\n + * CCR PL LL_BDMA_ConfigTransfer + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR + * @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT + * @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT + * @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD + * @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD + * @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_BDMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_BDMA_SetDataTransferDirection + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_BDMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_BDMA_GetDataTransferDirection + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_DIR | BDMA_CCR_MEM2MEM)); +} + +/** + * @brief Set BDMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_BDMA_SetMode + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_BDMA_MODE_NORMAL + * @arg @ref LL_BDMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get BDMA mode circular or normal. + * @rmtoll CCR CIRC LL_BDMA_GetMode + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_MODE_NORMAL + * @arg @ref LL_BDMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_BDMA_SetPeriphIncMode + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_BDMA_PERIPH_INCREMENT + * @arg @ref LL_BDMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_BDMA_GetPeriphIncMode + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_PERIPH_INCREMENT + * @arg @ref LL_BDMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_BDMA_SetMemoryIncMode + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_BDMA_MEMORY_INCREMENT + * @arg @ref LL_BDMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_BDMA_GetMemoryIncMode + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_MEMORY_INCREMENT + * @arg @ref LL_BDMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_BDMA_SetPeriphSize + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_BDMA_PDATAALIGN_BYTE + * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD + * @arg @ref LL_BDMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_BDMA_GetPeriphSize + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_PDATAALIGN_BYTE + * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD + * @arg @ref LL_BDMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_BDMA_SetMemorySize + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_BDMA_MDATAALIGN_BYTE + * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD + * @arg @ref LL_BDMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_BDMA_GetMemorySize + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_MDATAALIGN_BYTE + * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD + * @arg @ref LL_BDMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_BDMA_SetChannelPriorityLevel + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_BDMA_PRIORITY_LOW + * @arg @ref LL_BDMA_PRIORITY_MEDIUM + * @arg @ref LL_BDMA_PRIORITY_HIGH + * @arg @ref LL_BDMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_BDMA_GetChannelPriorityLevel + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_PRIORITY_LOW + * @arg @ref LL_BDMA_PRIORITY_MEDIUM + * @arg @ref LL_BDMA_PRIORITY_HIGH + * @arg @ref LL_BDMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, + BDMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_BDMA_SetDataLength + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR, + BDMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_BDMA_GetDataLength + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR, + BDMA_CNDTR_NDT)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_BDMA_SetCurrentTargetMem + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_BDMA_CURRENTTARGETMEM0 + * @arg @ref LL_BDMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_BDMA_GetCurrentTargetMem + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_BDMA_CURRENTTARGETMEM0 + * @arg @ref LL_BDMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_BDMA_EnableDoubleBufferMode + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_BDMA_DisableDoubleBufferMode + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the BDMA channel is enabled. + * @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr). + * @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n + * CMAR MA LL_BDMA_ConfigAddresses + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + /* Direction Memory to Periph */ + if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress); + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress); + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the BDMA channel is enabled. + * @rmtoll CMAR MA LL_BDMA_SetMemoryAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the BDMA channel is enabled. + * @rmtoll CPAR PA LL_BDMA_SetPeriphAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_BDMA_GetMemoryAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_BDMA_GetPeriphAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the BDMA channel is enabled. + * @rmtoll CPAR PA LL_BDMA_SetM2MSrcAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the BDMA channel is enabled. + * @rmtoll CMAR MA LL_BDMA_SetM2MDstAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_BDMA_GetM2MSrcAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_BDMA_GetM2MDstAddress + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_BDMA_SetMemory1Address + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_BDMA_GetMemory1Address + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR); +} + +/** + * @brief Set BDMA request for BDMA Channels on DMAMUX Channel x. + * @note DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_BDMA_SetPeriphRequest + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) +{ + UNUSED(BDMAx); + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get BDMA request for BDMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_BDMA_GetPeriphRequest + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + UNUSED(BDMAx); + return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @} + */ + + +/** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Get Channel 0 global interrupt flag. + * @rmtoll ISR GIF0 LL_BDMA_IsActiveFlag_GI0 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_BDMA_IsActiveFlag_GI1 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_BDMA_IsActiveFlag_GI2 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_BDMA_IsActiveFlag_GI3 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_BDMA_IsActiveFlag_GI4 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_BDMA_IsActiveFlag_GI5 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_BDMA_IsActiveFlag_GI6 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_BDMA_IsActiveFlag_GI7 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 0 transfer complete flag. + * @rmtoll ISR TCIF0 LL_BDMA_IsActiveFlag_TC0 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL); +} +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_BDMA_IsActiveFlag_TC1 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_BDMA_IsActiveFlag_TC2 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_BDMA_IsActiveFlag_TC3 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_BDMA_IsActiveFlag_TC4 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_BDMA_IsActiveFlag_TC5 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_BDMA_IsActiveFlag_TC6 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_BDMA_IsActiveFlag_TC7 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 0 half transfer flag. + * @rmtoll ISR HTIF0 LL_BDMA_IsActiveFlag_HT0 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_BDMA_IsActiveFlag_HT1 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_BDMA_IsActiveFlag_HT2 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_BDMA_IsActiveFlag_HT3 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_BDMA_IsActiveFlag_HT4 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_BDMA_IsActiveFlag_HT5 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_BDMA_IsActiveFlag_HT6 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_BDMA_IsActiveFlag_HT7 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 0 transfer error flag. + * @rmtoll ISR TEIF0 LL_BDMA_IsActiveFlag_TE0 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_BDMA_IsActiveFlag_TE1 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_BDMA_IsActiveFlag_TE2 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_BDMA_IsActiveFlag_TE3 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_BDMA_IsActiveFlag_TE4 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_BDMA_IsActiveFlag_TE5 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_BDMA_IsActiveFlag_TE6 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_BDMA_IsActiveFlag_TE7 + * @param BDMAx BDMA Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) +{ + return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Channel 0 global interrupt flag. + * @note Do not Clear Channel 0 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0, + LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5); +} + +/** + * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6); +} + +/** + * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7); +} + +/** + * @brief Clear Channel 0 transfer complete flag. + * @rmtoll IFCR CTCIF0 LL_BDMA_ClearFlag_TC0 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_BDMA_ClearFlag_TC1 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_BDMA_ClearFlag_TC2 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_BDMA_ClearFlag_TC3 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_BDMA_ClearFlag_TC4 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_BDMA_ClearFlag_TC5 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5); +} + +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_BDMA_ClearFlag_TC6 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6); +} + +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_BDMA_ClearFlag_TC7 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7); +} + +/** + * @brief Clear Channel 0 half transfer flag. + * @rmtoll IFCR CHTIF0 LL_BDMA_ClearFlag_HT0 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_BDMA_ClearFlag_HT1 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_BDMA_ClearFlag_HT2 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_BDMA_ClearFlag_HT3 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_BDMA_ClearFlag_HT4 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_BDMA_ClearFlag_HT5 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5); +} + +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_BDMA_ClearFlag_HT6 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6); +} + +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_BDMA_ClearFlag_HT7 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7); +} + +/** + * @brief Clear Channel 0 transfer error flag. + * @rmtoll IFCR CTEIF0 LL_BDMA_ClearFlag_TE0 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_BDMA_ClearFlag_TE1 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_BDMA_ClearFlag_TE2 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_BDMA_ClearFlag_TE3 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_BDMA_ClearFlag_TE4 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_BDMA_ClearFlag_TE5 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5); +} + +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_BDMA_ClearFlag_TE6 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6); +} + +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_BDMA_ClearFlag_TE7 + * @param BDMAx BDMA Instance + * @retval None + */ +__STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx) +{ + WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7); +} + +/** + * @} + */ + +/** @defgroup BDMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_BDMA_EnableIT_TC + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_BDMA_EnableIT_HT + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_BDMA_EnableIT_TE + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_BDMA_DisableIT_TC + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_BDMA_DisableIT_HT + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_BDMA_DisableIT_TE + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_BDMA_IsEnabledIT_TC + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_BDMA_IsEnabledIT_HT + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_BDMA_IsEnabledIT_TE + * @param BDMAx BDMA Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + uint32_t bdma_base_addr = (uint32_t)BDMAx; + + return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct); +uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel); +void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* BDMA || BDMA1 || BDMA2 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_BDMA_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h new file mode 100644 index 0000000..4f15c6e --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h @@ -0,0 +1,6914 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_BUS_H +#define STM32H7xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_MDMA RCC_AHB3ENR_MDMAEN +#define LL_AHB3_GRP1_PERIPH_DMA2D RCC_AHB3ENR_DMA2DEN + +#if defined(JPEG) +#define LL_AHB3_GRP1_PERIPH_JPGDEC RCC_AHB3ENR_JPGDECEN +#endif /* JPEG */ + +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#if defined(QUADSPI) +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) +#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN +#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN +#endif /*(OCTOSPI1) || (OCTOSPI2)*/ +#if defined(OCTOSPIM) +#define LL_AHB3_GRP1_PERIPH_OCTOSPIM RCC_AHB3ENR_IOMNGREN +#endif /* OCTOSPIM */ +#if defined(OTFDEC1) || defined(OTFDEC2) +#define LL_AHB3_GRP1_PERIPH_OTFDEC1 RCC_AHB3ENR_OTFDEC1EN +#define LL_AHB3_GRP1_PERIPH_OTFDEC2 RCC_AHB3ENR_OTFDEC2EN +#endif /* (OTFDEC1) || (OTFDEC2) */ +#if defined(GFXMMU) +#define LL_AHB3_GRP1_PERIPH_GFXMMU RCC_AHB3ENR_GFXMMUEN +#endif /* GFXMMU */ +#define LL_AHB3_GRP1_PERIPH_SDMMC1 RCC_AHB3ENR_SDMMC1EN +#define LL_AHB3_GRP1_PERIPH_FLASH RCC_AHB3LPENR_FLASHLPEN +#define LL_AHB3_GRP1_PERIPH_DTCM1 RCC_AHB3LPENR_DTCM1LPEN +#define LL_AHB3_GRP1_PERIPH_DTCM2 RCC_AHB3LPENR_DTCM2LPEN +#define LL_AHB3_GRP1_PERIPH_ITCM RCC_AHB3LPENR_ITCMLPEN +#if defined(RCC_AHB3LPENR_AXISRAMLPEN) +#define LL_AHB3_GRP1_PERIPH_AXISRAM RCC_AHB3LPENR_AXISRAMLPEN +#else +#define LL_AHB3_GRP1_PERIPH_AXISRAM1 RCC_AHB3LPENR_AXISRAM1LPEN +#define LL_AHB3_GRP1_PERIPH_AXISRAM LL_AHB3_GRP1_PERIPH_AXISRAM1 /* for backward compatibility*/ +#endif /* RCC_AHB3LPENR_AXISRAMLPEN */ +#if defined(CD_AXISRAM2_BASE) +#define LL_AHB3_GRP1_PERIPH_AXISRAM2 RCC_AHB3LPENR_AXISRAM2LPEN +#endif /* CD_AXISRAM2_BASE */ +#if defined(CD_AXISRAM3_BASE) +#define LL_AHB3_GRP1_PERIPH_AXISRAM3 RCC_AHB3LPENR_AXISRAM3LPEN +#endif /* CD_AXISRAM3_BASE */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#define LL_AHB1_GRP1_PERIPH_ADC12 RCC_AHB1ENR_ADC12EN +#if defined(DUAL_CORE) +#define LL_AHB1_GRP1_PERIPH_ART RCC_AHB1ENR_ARTEN +#endif /* DUAL_CORE */ +#if defined(RCC_AHB1ENR_CRCEN) +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#endif /* RCC_AHB1ENR_CRCEN */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETH1MAC RCC_AHB1ENR_ETH1MACEN +#define LL_AHB1_GRP1_PERIPH_ETH1TX RCC_AHB1ENR_ETH1TXEN +#define LL_AHB1_GRP1_PERIPH_ETH1RX RCC_AHB1ENR_ETH1RXEN +#endif /* ETH */ +#define LL_AHB1_GRP1_PERIPH_USB1OTGHS RCC_AHB1ENR_USB1OTGHSEN +#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI RCC_AHB1ENR_USB1OTGHSULPIEN +#if defined(USB2_OTG_FS) +#define LL_AHB1_GRP1_PERIPH_USB2OTGHS RCC_AHB1ENR_USB2OTGHSEN +#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI RCC_AHB1ENR_USB2OTGHSULPIEN +#endif /* USB2_OTG_FS */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN) +#define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN +#endif /* HSEM && RCC_AHB2ENR_HSEMEN */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR_SDMMC2EN +#if defined(FMAC) +#define LL_AHB2_GRP1_PERIPH_FMAC RCC_AHB2ENR_FMACEN +#endif /* FMAC */ +#if defined(CORDIC) +#define LL_AHB2_GRP1_PERIPH_CORDIC RCC_AHB2ENR_CORDICEN +#endif /* CORDIC */ +#if defined(BDMA1) +#define LL_AHB2_GRP1_PERIPH_BDMA1 RCC_AHB2ENR_BDMA1EN +#endif /* BDMA1 */ +#if defined(RCC_AHB2ENR_D2SRAM1EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM1 RCC_AHB2ENR_D2SRAM1EN +#else +#define LL_AHB2_GRP1_PERIPH_AHBSRAM1 RCC_AHB2ENR_AHBSRAM1EN +#define LL_AHB2_GRP1_PERIPH_D2SRAM1 LL_AHB2_GRP1_PERIPH_AHBSRAM1 /* for backward compatibility*/ +#endif /* RCC_AHB2ENR_D2SRAM1EN */ +#if defined(RCC_AHB2ENR_D2SRAM2EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM2 RCC_AHB2ENR_D2SRAM2EN +#else +#define LL_AHB2_GRP1_PERIPH_AHBSRAM2 RCC_AHB2ENR_AHBSRAM2EN +#define LL_AHB2_GRP1_PERIPH_D2SRAM2 LL_AHB2_GRP1_PERIPH_AHBSRAM2 /* for backward compatibility*/ +#endif /* RCC_AHB2ENR_D2SRAM2EN */ +#if defined(RCC_AHB2ENR_D2SRAM3EN) +#define LL_AHB2_GRP1_PERIPH_D2SRAM3 RCC_AHB2ENR_D2SRAM3EN +#endif /* RCC_AHB2ENR_D2SRAM3EN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#define LL_AHB4_GRP1_PERIPH_GPIOA RCC_AHB4ENR_GPIOAEN +#define LL_AHB4_GRP1_PERIPH_GPIOB RCC_AHB4ENR_GPIOBEN +#define LL_AHB4_GRP1_PERIPH_GPIOC RCC_AHB4ENR_GPIOCEN +#define LL_AHB4_GRP1_PERIPH_GPIOD RCC_AHB4ENR_GPIODEN +#define LL_AHB4_GRP1_PERIPH_GPIOE RCC_AHB4ENR_GPIOEEN +#define LL_AHB4_GRP1_PERIPH_GPIOF RCC_AHB4ENR_GPIOFEN +#define LL_AHB4_GRP1_PERIPH_GPIOG RCC_AHB4ENR_GPIOGEN +#define LL_AHB4_GRP1_PERIPH_GPIOH RCC_AHB4ENR_GPIOHEN +#if defined(GPIOI) +#define LL_AHB4_GRP1_PERIPH_GPIOI RCC_AHB4ENR_GPIOIEN +#endif /* GPIOI */ +#define LL_AHB4_GRP1_PERIPH_GPIOJ RCC_AHB4ENR_GPIOJEN +#define LL_AHB4_GRP1_PERIPH_GPIOK RCC_AHB4ENR_GPIOKEN +#if defined(RCC_AHB4ENR_CRCEN) +#define LL_AHB4_GRP1_PERIPH_CRC RCC_AHB4ENR_CRCEN +#endif /* RCC_AHB4ENR_CRCEN */ +#if defined(BDMA2) +#define LL_AHB4_GRP1_PERIPH_BDMA2 RCC_AHB4ENR_BDMA2EN +#define LL_AHB4_GRP1_PERIPH_BDMA LL_AHB4_GRP1_PERIPH_BDMA2 /* for backward compatibility*/ +#else +#define LL_AHB4_GRP1_PERIPH_BDMA RCC_AHB4ENR_BDMAEN +#endif /* BDMA2 */ +#if defined(ADC3) +#define LL_AHB4_GRP1_PERIPH_ADC3 RCC_AHB4ENR_ADC3EN +#endif /* ADC3 */ +#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN) +#define LL_AHB4_GRP1_PERIPH_HSEM RCC_AHB4ENR_HSEMEN +#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/ +#define LL_AHB4_GRP1_PERIPH_BKPRAM RCC_AHB4ENR_BKPRAMEN +#if defined(RCC_AHB4LPENR_SRAM4LPEN) +#define LL_AHB4_GRP1_PERIPH_SRAM4 RCC_AHB4LPENR_SRAM4LPEN +#define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRAM4 +#else +#define LL_AHB4_GRP1_PERIPH_SRDSRAM RCC_AHB4ENR_SRDSRAMEN +#define LL_AHB4_GRP1_PERIPH_SRAM4 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ +#define LL_AHB4_GRP1_PERIPH_D3SRAM1 LL_AHB4_GRP1_PERIPH_SRDSRAM /* for backward compatibility*/ +#endif /* RCC_AHB4ENR_D3SRAM1EN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH + * @{ + */ +#if defined(LTDC) +#define LL_APB3_GRP1_PERIPH_LTDC RCC_APB3ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB3_GRP1_PERIPH_DSI RCC_APB3ENR_DSIEN +#endif /* DSI */ +#define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN +#if defined(RCC_APB3ENR_WWDGEN) +#define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/ +#endif /* RCC_APB3ENR_WWDGEN */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1LENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1LENR_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1LENR_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1LENR_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1LENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1LENR_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1LENR_TIM12EN +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1LENR_TIM13EN +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1LENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1LENR_LPTIM1EN +#if defined(DUAL_CORE) +#define LL_APB1_GRP1_PERIPH_WWDG2 RCC_APB1LENR_WWDG2EN +#endif /*DUAL_CORE*/ +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1LENR_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1LENR_SPI3EN +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1LENR_SPDIFRXEN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1LENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1LENR_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1LENR_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1LENR_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1LENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1LENR_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1LENR_I2C3EN +#if defined(I2C5) +#define LL_APB1_GRP1_PERIPH_I2C5 RCC_APB1LENR_I2C5EN +#endif /* I2C5 */ +#if defined(RCC_APB1LENR_CECEN) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1LENR_CECEN +#else +#define LL_APB1_GRP1_PERIPH_HDMICEC RCC_APB1LENR_HDMICECEN +#define LL_APB1_GRP1_PERIPH_CEC LL_APB1_GRP1_PERIPH_HDMICEC /* for backward compatibility*/ +#endif /* RCC_APB1LENR_CECEN */ +#define LL_APB1_GRP1_PERIPH_DAC12 RCC_APB1LENR_DAC12EN +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1LENR_UART7EN +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1LENR_UART8EN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_CRS RCC_APB1HENR_CRSEN +#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1HENR_SWPMIEN +#define LL_APB1_GRP2_PERIPH_OPAMP RCC_APB1HENR_OPAMPEN +#define LL_APB1_GRP2_PERIPH_MDIOS RCC_APB1HENR_MDIOSEN +#define LL_APB1_GRP2_PERIPH_FDCAN RCC_APB1HENR_FDCANEN +#if defined(TIM23) +#define LL_APB1_GRP2_PERIPH_TIM23 RCC_APB1HENR_TIM23EN +#endif /* TIM23 */ +#if defined(TIM24) +#define LL_APB1_GRP2_PERIPH_TIM24 RCC_APB1HENR_TIM24EN +#endif /* TIM24 */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#if defined(UART9) +#define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN +#endif /* UART9 */ +#if defined(USART10) +#define LL_APB2_GRP1_PERIPH_USART10 RCC_APB2ENR_USART10EN +#endif /* USART10 */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#if defined(SAI2) +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#endif /* SAI2 */ +#if defined(SAI3) +#define LL_APB2_GRP1_PERIPH_SAI3 RCC_APB2ENR_SAI3EN +#endif /* SAI3 */ +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#if defined(HRTIM1) +#define LL_APB2_GRP1_PERIPH_HRTIM RCC_APB2ENR_HRTIMEN +#endif /* HRTIM1 */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH APB4 GRP1 PERIPH + * @{ + */ +#define LL_APB4_GRP1_PERIPH_SYSCFG RCC_APB4ENR_SYSCFGEN +#define LL_APB4_GRP1_PERIPH_LPUART1 RCC_APB4ENR_LPUART1EN +#define LL_APB4_GRP1_PERIPH_SPI6 RCC_APB4ENR_SPI6EN +#define LL_APB4_GRP1_PERIPH_I2C4 RCC_APB4ENR_I2C4EN +#define LL_APB4_GRP1_PERIPH_LPTIM2 RCC_APB4ENR_LPTIM2EN +#define LL_APB4_GRP1_PERIPH_LPTIM3 RCC_APB4ENR_LPTIM3EN +#if defined(LPTIM4) +#define LL_APB4_GRP1_PERIPH_LPTIM4 RCC_APB4ENR_LPTIM4EN +#endif /* LPTIM4 */ +#if defined(LPTIM5) +#define LL_APB4_GRP1_PERIPH_LPTIM5 RCC_APB4ENR_LPTIM5EN +#endif /* LPTIM5 */ +#if defined(DAC2) +#define LL_APB4_GRP1_PERIPH_DAC2 RCC_APB4ENR_DAC2EN +#endif /* DAC2 */ +#define LL_APB4_GRP1_PERIPH_COMP12 RCC_APB4ENR_COMP12EN +#define LL_APB4_GRP1_PERIPH_VREF RCC_APB4ENR_VREFEN +#define LL_APB4_GRP1_PERIPH_RTCAPB RCC_APB4ENR_RTCAPBEN +#if defined(SAI4) +#define LL_APB4_GRP1_PERIPH_SAI4 RCC_APB4ENR_SAI4EN +#endif /* SAI4 */ +#if defined(DTS) +#define LL_APB4_GRP1_PERIPH_DTS RCC_APB4ENR_DTSEN +#endif /*DTS*/ +#if defined(DFSDM2_BASE) +#define LL_APB4_GRP1_PERIPH_DFSDM2 RCC_APB4ENR_DFSDM2EN +#endif /* DFSDM2_BASE */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_CLKAM_PERIPH CLKAM PERIPH + * @{ + */ +#if defined(RCC_D3AMR_BDMAAMEN) +#define LL_CLKAM_PERIPH_BDMA RCC_D3AMR_BDMAAMEN +#else +#define LL_CLKAM_PERIPH_BDMA2 RCC_SRDAMR_BDMA2AMEN +#define LL_CLKAM_PERIPH_BDMA LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/ +#endif /* RCC_D3AMR_BDMAAMEN */ +#if defined(RCC_SRDAMR_GPIOAMEN) +#define LL_CLKAM_PERIPH_GPIO RCC_SRDAMR_GPIOAMEN +#endif /* RCC_SRDAMR_GPIOAMEN */ +#if defined(RCC_D3AMR_LPUART1AMEN) +#define LL_CLKAM_PERIPH_LPUART1 RCC_D3AMR_LPUART1AMEN +#else +#define LL_CLKAM_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN +#endif /* RCC_D3AMR_LPUART1AMEN */ +#if defined(RCC_D3AMR_SPI6AMEN) +#define LL_CLKAM_PERIPH_SPI6 RCC_D3AMR_SPI6AMEN +#else +#define LL_CLKAM_PERIPH_SPI6 RCC_SRDAMR_SPI6AMEN +#endif /* RCC_D3AMR_SPI6AMEN */ +#if defined(RCC_D3AMR_I2C4AMEN) +#define LL_CLKAM_PERIPH_I2C4 RCC_D3AMR_I2C4AMEN +#else +#define LL_CLKAM_PERIPH_I2C4 RCC_SRDAMR_I2C4AMEN +#endif /* RCC_D3AMR_I2C4AMEN */ +#if defined(RCC_D3AMR_LPTIM2AMEN) +#define LL_CLKAM_PERIPH_LPTIM2 RCC_D3AMR_LPTIM2AMEN +#else +#define LL_CLKAM_PERIPH_LPTIM2 RCC_SRDAMR_LPTIM2AMEN +#endif /* RCC_D3AMR_LPTIM2AMEN */ +#if defined(RCC_D3AMR_LPTIM3AMEN) +#define LL_CLKAM_PERIPH_LPTIM3 RCC_D3AMR_LPTIM3AMEN +#else +#define LL_CLKAM_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN +#endif /* RCC_D3AMR_LPTIM3AMEN */ +#if defined(RCC_D3AMR_LPTIM4AMEN) +#define LL_CLKAM_PERIPH_LPTIM4 RCC_D3AMR_LPTIM4AMEN +#endif /* RCC_D3AMR_LPTIM4AMEN */ +#if defined(RCC_D3AMR_LPTIM5AMEN) +#define LL_CLKAM_PERIPH_LPTIM5 RCC_D3AMR_LPTIM5AMEN +#endif /* RCC_D3AMR_LPTIM5AMEN */ +#if defined(DAC2) +#define LL_CLKAM_PERIPH_DAC2 RCC_SRDAMR_DAC2AMEN +#endif /* DAC2 */ +#if defined(RCC_D3AMR_COMP12AMEN) +#define LL_CLKAM_PERIPH_COMP12 RCC_D3AMR_COMP12AMEN +#else +#define LL_CLKAM_PERIPH_COMP12 RCC_SRDAMR_COMP12AMEN +#endif /* RCC_D3AMR_COMP12AMEN */ +#if defined(RCC_D3AMR_VREFAMEN) +#define LL_CLKAM_PERIPH_VREF RCC_D3AMR_VREFAMEN +#else +#define LL_CLKAM_PERIPH_VREF RCC_SRDAMR_VREFAMEN +#endif /* RCC_D3AMR_VREFAMEN */ +#if defined(RCC_D3AMR_RTCAMEN) +#define LL_CLKAM_PERIPH_RTC RCC_D3AMR_RTCAMEN +#else +#define LL_CLKAM_PERIPH_RTC RCC_SRDAMR_RTCAMEN +#endif /* RCC_D3AMR_RTCAMEN */ +#if defined(RCC_D3AMR_CRCAMEN) +#define LL_CLKAM_PERIPH_CRC RCC_D3AMR_CRCAMEN +#endif /* RCC_D3AMR_CRCAMEN */ +#if defined(SAI4) +#define LL_CLKAM_PERIPH_SAI4 RCC_D3AMR_SAI4AMEN +#endif /* SAI4 */ +#if defined(ADC3) +#define LL_CLKAM_PERIPH_ADC3 RCC_D3AMR_ADC3AMEN +#endif /* ADC3 */ +#if defined(RCC_SRDAMR_DTSAMEN) +#define LL_CLKAM_PERIPH_DTS RCC_SRDAMR_DTSAMEN +#endif /* RCC_SRDAMR_DTSAMEN */ +#if defined(RCC_D3AMR_DTSAMEN) +#define LL_CLKAM_PERIPH_DTS RCC_D3AMR_DTSAMEN +#endif /* RCC_D3AMR_DTSAMEN */ +#if defined(DFSDM2_BASE) +#define LL_CLKAM_PERIPH_DFSDM2 RCC_SRDAMR_DFSDM2AMEN +#endif /* DFSDM2_BASE */ +#if defined(RCC_D3AMR_BKPRAMAMEN) +#define LL_CLKAM_PERIPH_BKPRAM RCC_D3AMR_BKPRAMAMEN +#else +#define LL_CLKAM_PERIPH_BKPRAM RCC_SRDAMR_BKPRAMAMEN +#endif /* RCC_D3AMR_BKPRAMAMEN */ +#if defined(RCC_D3AMR_SRAM4AMEN) +#define LL_CLKAM_PERIPH_SRAM4 RCC_D3AMR_SRAM4AMEN +#else +#define LL_CLKAM_PERIPH_SRDSRAM RCC_SRDAMR_SRDSRAMAMEN +#define LL_CLKAM_PERIPH_SRAM4 LL_CLKAM_PERIPH_SRDSRAM +#endif /* RCC_D3AMR_SRAM4AMEN */ +/** + * @} + */ + +#if defined(RCC_CKGAENR_AXICKG) +/** @defgroup BUS_LL_EC_CKGA_PERIPH CKGA (AXI Clocks Gating) PERIPH + * @{ + */ +#define LL_CKGA_PERIPH_AXI RCC_CKGAENR_AXICKG +#define LL_CKGA_PERIPH_AHB RCC_CKGAENR_AHBCKG +#define LL_CKGA_PERIPH_CPU RCC_CKGAENR_CPUCKG +#define LL_CKGA_PERIPH_SDMMC RCC_CKGAENR_SDMMCCKG +#define LL_CKGA_PERIPH_MDMA RCC_CKGAENR_MDMACKG +#define LL_CKGA_PERIPH_DMA2D RCC_CKGAENR_DMA2DCKG +#define LL_CKGA_PERIPH_LTDC RCC_CKGAENR_LTDCCKG +#define LL_CKGA_PERIPH_GFXMMUM RCC_CKGAENR_GFXMMUMCKG +#define LL_CKGA_PERIPH_AHB12 RCC_CKGAENR_AHB12CKG +#define LL_CKGA_PERIPH_AHB34 RCC_CKGAENR_AHB34CKG +#define LL_CKGA_PERIPH_FLIFT RCC_CKGAENR_FLIFTCKG +#define LL_CKGA_PERIPH_OCTOSPI2 RCC_CKGAENR_OCTOSPI2CKG +#define LL_CKGA_PERIPH_FMC RCC_CKGAENR_FMCCKG +#define LL_CKGA_PERIPH_OCTOSPI1 RCC_CKGAENR_OCTOSPI1CKG +#define LL_CKGA_PERIPH_AXIRAM1 RCC_CKGAENR_AXIRAM1CKG +#define LL_CKGA_PERIPH_AXIRAM2 RCC_CKGAENR_AXIRAM2CKG +#define LL_CKGA_PERIPH_AXIRAM3 RCC_CKGAENR_AXIRAM3CKG +#define LL_CKGA_PERIPH_GFXMMUS RCC_CKGAENR_GFXMMUSCKG +#define LL_CKGA_PERIPH_ECCRAM RCC_CKGAENR_ECCRAMCKG +#define LL_CKGA_PERIPH_EXTI RCC_CKGAENR_EXTICKG +#define LL_CKGA_PERIPH_JTAG RCC_CKGAENR_JTAGCKG +/** + * @} + */ +#endif /* RCC_CKGAENR_AXICKG */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR DTCM2EN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR ITCMEN LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR AXISRAMEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ForceReset\n (*) + * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR MDMARST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR DMA2DRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR JPGDECRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR IOMNGRRST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OTFDEC1RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR OTFDEC2RST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR GFXMMURST LL_AHB3_GRP1_ReleaseReset\n (*) + * AHB3RSTR SDMMC1RST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR OSPI1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ARTEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1MACEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1TXEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1RXEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_AHB1_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ARTRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ForceReset\n (*) + * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ADC12RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ARTRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR ETH1MACRST LL_AHB1_GRP1_ReleaseReset\n (*) + * AHB1RSTR USB1OTGHSRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR USB2OTGHSRST LL_AHB1_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ARTLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ARTLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_AHB1_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR BDMA1EN LL_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR FMACEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CORDICEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM1EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM2EN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM3EN LL_AHB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset\n (*) + * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset\n (*) + * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR FMACLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CORDICLPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR BDMA1LPEN LL_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR D2SRAM1LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_AHB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_FMAC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CORDIC (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR GPIOJEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BDMAEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR HSEMEN LL_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BKPRAMEN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4ENR, Periphs); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR BDMARST LL_AHB4_GRP1_ForceReset\n + * AHB4RSTR ADC3RST LL_AHB4_GRP1_ForceReset\n (*) + * AHB4RSTR HSEMRST LL_AHB4_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll AHB4RSTR GPIOARST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOBRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOCRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIODRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOERST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOFRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOGRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOHRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOIRST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR GPIOJRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR GPIOKRST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR CRCRST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR BDMARST LL_AHB4_GRP1_ReleaseReset\n + * AHB4RSTR ADC3RST LL_AHB4_GRP1_ReleaseReset\n (*) + * AHB4RSTR HSEMRST LL_AHB4_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Enable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR GPIOJLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_EnableClock\n (*) + * APB3ENR DSIEN LL_APB3_GRP1_EnableClock\n (*) + * APB3ENR WWDG1EN LL_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR DSIEN LL_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR WWDG1EN LL_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_APB3_GRP1_DisableClock\n + * APB3ENR DSIEN LL_APB3_GRP1_DisableClock\n + * APB3ENR WWDG1EN LL_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3ENR, Periphs); +} + +/** + * @brief Force APB3 peripherals reset. + * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ForceReset\n (*) + * APB3RSTR DSIRST LL_APB3_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Release APB3 peripherals reset. + * @rmtoll APB3RSTR LTDCRST LL_APB3_GRP1_ReleaseReset\n + * APB3RSTR DSIRST LL_APB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3RSTR, Periphs); +} + +/** + * @brief Enable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR DSILPEN LL_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR DSILPEN LL_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_EnableClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_EnableClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_APB1_GRP1_DisableClock\n (*) + * APB1LENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1LENR I2C5EN LL_APB1_GRP1_DisableClock\n (*) + * APB1LENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR I2C5RST LL_APB1_GRP5_ForceReset\n (*) + * APB1LRSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR DAC12RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1LRSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR I2C5RST LL_APB1_GRP1_ReleaseReset\n (*) + * APB1LRSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR DAC12RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1LRSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LRSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C5LPEN LL_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR CECLPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C5LPEN LL_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR CECLPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LLPENR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR SWPMIRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR OPAMPRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR MDIOSRST LL_APB1_GRP2_ForceReset\n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1HRSTR CRSRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR SWPMIRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR OPAMPRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR MDIOSRST LL_APB1_GRP2_ReleaseReset\n + * APB1HRSTR FDCANRST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HRSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_EnableClock\n (*) + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR USART10EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_APB2_GRP1_DisableClock\n (*) + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_APB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2ENR UART9RST LL_APB2_GRP1_ForceReset\n (*) + * APB2ENR USART10RST LL_APB2_GRP1_ForceReset\n (*) + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI3RST LL_APB2_GRP1_ForceReset\n (*) + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR HRTIMRST LL_APB2_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2ENR UART9RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2ENR USART10RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI3RST LL_APB2_GRP1_ReleaseReset\n (*) + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR HRTIMRST LL_APB2_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2ENR UART9LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2ENR USART10LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_APB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2ENR UART9LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2ENR USART10LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_APB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_EnableClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR LPTIM5EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DAC2EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR COMP12EN LL_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DTSEN LL_APB4_GRP1_DisableClock\n (*) + * APB4ENR DFSDM2EN LL_APB4_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4ENR, Periphs); +} + +/** + * @brief Force APB4 peripherals reset. + * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR I2C4RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DAC2EN LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR COMP12RST LL_APB4_GRP1_ForceReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ForceReset\n + * APB4RSTR SAI4RST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DTSRST LL_APB4_GRP1_ForceReset\n (*) + * APB4RSTR DFSDM2RST LL_APB4_GRP1_ForceReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Release APB4 peripherals reset. + * @rmtoll APB4RSTR SYSCFGRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPUART1RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR SPI6RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR I2C4RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM2RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM3RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR LPTIM4RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR LPTIM5RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR DAC2RST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR COMP12RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR VREFRST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR SAI4RST LL_APB4_GRP1_ReleaseReset\n + * APB4RSTR DTSRST LL_APB4_GRP1_ReleaseReset\n (*) + * APB4RSTR DFSDM2RST LL_APB4_GRP1_ReleaseReset (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4RSTR, Periphs); +} + +/** + * @brief Enable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DAC2LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR COMP12LPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DTSLPEN LL_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DAC2LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR COMP12LPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DTSLPEN LL_APB4_GRP1_DisableClockSleep\n (*) + * APB4LPENR DFSDM2LPEN LL_APB4_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DAC2 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_CLKAM CLKAM + * @{ + */ + +/** + * @brief Enable peripherals clock for CLKAM Mode. + * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPUART1 LL_CLKAM_Enable\n + * D3AMR / SRDAMR SPI6 LL_CLKAM_Enable\n + * D3AMR / SRDAMR I2C4 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Enable\n + * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DAC2 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR COMP12 LL_CLKAM_Enable\n + * D3AMR / SRDAMR VREF LL_CLKAM_Enable\n + * D3AMR / SRDAMR RTC LL_CLKAM_Enable\n + * D3AMR / SRDAMR CRC LL_CLKAM_Enable\n + * D3AMR / SRDAMR SAI4 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR ADC3 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DTS LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Enable\n (*) + * D3AMR / SRDAMR BKPRAM LL_CLKAM_Enable\n + * D3AMR / SRDAMR SRAM4 LL_CLKAM_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CLKAM_PERIPH_BDMA + * @arg @ref LL_CLKAM_PERIPH_GPIO (*) + * @arg @ref LL_CLKAM_PERIPH_LPUART1 + * @arg @ref LL_CLKAM_PERIPH_SPI6 + * @arg @ref LL_CLKAM_PERIPH_I2C4 + * @arg @ref LL_CLKAM_PERIPH_LPTIM2 + * @arg @ref LL_CLKAM_PERIPH_LPTIM3 + * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) + * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) + * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) + * @arg @ref LL_CLKAM_PERIPH_COMP12 + * @arg @ref LL_CLKAM_PERIPH_VREF + * @arg @ref LL_CLKAM_PERIPH_RTC + * @arg @ref LL_CLKAM_PERIPH_CRC (*) + * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) + * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) + * @arg @ref LL_CLKAM_PERIPH_DTS (*) + * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) + * @arg @ref LL_CLKAM_PERIPH_BKPRAM + * @arg @ref LL_CLKAM_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + +#if defined(RCC_D3AMR_BDMAAMEN) + SET_BIT(RCC->D3AMR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->D3AMR, Periphs); +#else + SET_BIT(RCC->SRDAMR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->SRDAMR, Periphs); +#endif /* RCC_D3AMR_BDMAAMEN */ + (void)tmpreg; +} + +/** + * @brief Disable peripherals clock for CLKAM Mode. + * @rmtoll D3AMR / SRDAMR BDMA LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPUART1 LL_CLKAM_Disable\n + * D3AMR / SRDAMR SPI6 LL_CLKAM_Disable\n + * D3AMR / SRDAMR I2C4 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM2 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM3 LL_CLKAM_Disable\n + * D3AMR / SRDAMR LPTIM4 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR LPTIM5 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DAC2 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR COMP12 LL_CLKAM_Disable\n + * D3AMR / SRDAMR VREF LL_CLKAM_Disable\n + * D3AMR / SRDAMR RTC LL_CLKAM_Disable\n + * D3AMR / SRDAMR CRC LL_CLKAM_Disable\n + * D3AMR / SRDAMR SAI4 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR ADC3 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DTS LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR DFSDM2 LL_CLKAM_Disable\n (*) + * D3AMR / SRDAMR BKPRAM LL_CLKAM_Disable\n + * D3AMR / SRDAMR SRAM4 LL_CLKAM_Disable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CLKAM_PERIPH_BDMA + * @arg @ref LL_CLKAM_PERIPH_GPIO (*) + * @arg @ref LL_CLKAM_PERIPH_LPUART1 + * @arg @ref LL_CLKAM_PERIPH_SPI6 + * @arg @ref LL_CLKAM_PERIPH_I2C4 + * @arg @ref LL_CLKAM_PERIPH_LPTIM2 + * @arg @ref LL_CLKAM_PERIPH_LPTIM3 + * @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*) + * @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*) + * @arg @ref LL_CLKAM_PERIPH_DAC2 (*) + * @arg @ref LL_CLKAM_PERIPH_COMP12 + * @arg @ref LL_CLKAM_PERIPH_VREF + * @arg @ref LL_CLKAM_PERIPH_RTC + * @arg @ref LL_CLKAM_PERIPH_CRC (*) + * @arg @ref LL_CLKAM_PERIPH_SAI4 (*) + * @arg @ref LL_CLKAM_PERIPH_ADC3 (*) + * @arg @ref LL_CLKAM_PERIPH_DTS (*) + * @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*) + * @arg @ref LL_CLKAM_PERIPH_BKPRAM + * @arg @ref LL_CLKAM_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs) +{ +#if defined(RCC_D3AMR_BDMAAMEN) + CLEAR_BIT(RCC->D3AMR, Periphs); +#else + CLEAR_BIT(RCC->SRDAMR, Periphs); +#endif /* RCC_D3AMR_BDMAAMEN */ +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_CKGA CKGA + * @{ + */ + +#if defined(RCC_CKGAENR_AXICKG) + + +/** + * @brief Enable clock gating for AXI bus peripherals. + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * @retval None +*/ +__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->CKGAENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->CKGAENR, Periphs); + (void)tmpreg; +} + +#endif /* RCC_CKGAENR_AXICKG */ + +#if defined(RCC_CKGAENR_AXICKG) + +/** + * @brief Disable clock gating for AXI bus peripherals. + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG + * @retval None +*/ +__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) +{ + CLEAR_BIT(RCC->CKGAENR, Periphs); +} + +#endif /* RCC_CKGAENR_AXICKG */ + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @addtogroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable C1 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_C1_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI1EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OSPI2EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB3ENR, Periphs); +} + +/** + * @brief Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_EnableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OSPI2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR IOMNGRLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR OTFDEC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR GFXMMULPEN LL_C1_AHB3_GRP1_DisableClockSleep\n (*) + * AHB3LPENR SDMMC1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C1_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C1_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable C1 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_EnableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_IsEnabledClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ARTEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1MACEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1TXEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR ETH1RXEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB1OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_C1_AHB1_GRP1_DisableClock\n (*) + * AHB1ENR USB2OTGHSULPIEN LL_C1_AHB1_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB1ENR, Periphs); +} + +/** + * @brief Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_EnableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR CRCLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ARTLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1MACLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1TXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR ETH1RXLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB1OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C1_AHB1_GRP1_DisableClockSleep\n (*) + * AHB1LPENR USB2OTGHSULPILPEN LL_C1_AHB1_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable C1 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_EnableClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_EnableClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_IsEnabledClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR CRYPEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR HASHEN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR RNGEN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR BDMA1EN LL_C1_AHB2_GRP1_DisableClock\n (*) + * AHB2ENR D2SRAM1EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM2EN LL_C1_AHB2_GRP1_DisableClock\n + * AHB2ENR D2SRAM3EN LL_C1_AHB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB2ENR, Periphs); +} + +/** + * @brief Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n (*) + * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR HASHLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR RNGLPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR BDAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n (*) + * AHB2LPENR D2SRAM1LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C1_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C1_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable C1 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_EnableClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_IsEnabledClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOJEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BDMAEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR HSEMEN LL_C1_AHB4_GRP1_DisableClock\n (*) + * AHB4ENR BKPRAMEN LL_C1_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_C1_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB4ENR, Periphs); +} + +/** + * @brief Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_EnableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BDMALPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C1_AHB4_GRP1_DisableClockSleep\n (*) + * AHB4LPENR BKPRAMLPEN LL_C1_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C1_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable C1 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_EnableClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_EnableClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_IsEnabledClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C1_APB3_GRP1_DisableClock\n (*) + * APB3ENR DSIEN LL_C1_APB3_GRP1_DisableClock\n (*) + * APB3ENR WWDG1EN LL_C1_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB3ENR, Periphs); +} + +/** + * @brief Enable C1 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR DSILPEN LL_C1_APB3_GRP1_EnableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR DSILPEN LL_C1_APB3_GRP1_DisableClockSleep\n (*) + * APB3LPENR WWDG1LPEN LL_C1_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable C1 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_EnableClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_IsEnabledClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_C1_APB1_GRP1_DisableClock\n (*) + * APB1LENR SPI2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR CECEN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_C1_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_C1_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1LENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n (*) + * APB1LLPENR SPI2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CECLPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_C1_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_C1_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_C1_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_C1_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1HENR, Periphs); +} + +/** + * @brief Enable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C1_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C1_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable C1 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_EnableClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_IsEnabledClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR SPI1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_C1_APB2_GRP1_DisableClock\n (*) + * APB2ENR DFSDM1EN LL_C1_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_C1_APB2_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB2ENR, Periphs); +} + +/** + * @brief Enable C1 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2ENR UART9EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2ENR USART10EN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_EnableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR UART9LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR USART10LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR USART6LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_C1_APB2_GRP1_DisableClockSleep\n (*) + * APB2LPENR DFSDM1LPEN LL_C1_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C1_APB2_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable C1 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DAC2EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_EnableClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_EnableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C1 APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_IsEnabledClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_IsEnabledClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C1 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR LPTIM5EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR COMP12EN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_C1_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR DTSEN LL_C1_APB4_GRP1_DisableClock\n (*) + * APB4ENR DFSDM2EN LL_C1_APB4_GRP1_DisableClock (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB4ENR, Periphs); +} + +/** + * @brief Enable C1 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4ENR DTSLPEN LL_C1_APB4_GRP1_EnableClockSleep\n (*) + * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_EnableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C1->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C1 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR COMP12LPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C1_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) + * APB4ENR DTSLPEN LL_C1_APB4_GRP1_DisableClockSleep\n (*) + * APB4ENR DFSDM2LPEN LL_C1_APB4_GRP1_DisableClockSleep (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DTS (*) + * @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C1->APB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable C2 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_EnableClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB3 peripherals clock. + * @rmtoll AHB3ENR MDMAEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DMA2DEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR JPGDECEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR FMCEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR SDMMC1EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR FLASHEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DTCM1EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR DTCM2EN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR ITCMEN LL_C2_AHB3_GRP1_DisableClock\n + * AHB3ENR AXISRAMEN LL_C2_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB3ENR, Periphs); +} + +/** + * @brief Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_EnableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB3LPENR MDMALPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DMA2DLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR JPGDECLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FMCLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR QSPILPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR SDMMC1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR FLASHLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM1LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR DTCM2LPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR ITCMLPEN LL_C2_AHB3_GRP1_DisableClockSleep\n + * AHB3LPENR AXISRAMLPEN LL_C2_AHB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D + * @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_AHB3_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 + * @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 + * @arg @ref LL_AHB3_GRP1_PERIPH_ITCM + * @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable C2 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_EnableClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB1 peripherals clock. + * @rmtoll AHB1ENR DMA1EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ADC12EN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ARTEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1MACEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1TXEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR ETH1RXEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB1OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSEN LL_C2_AHB1_GRP1_DisableClock\n + * AHB1ENR USB2OTGHSULPIEN LL_C2_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB1ENR, Periphs); +} + +/** + * @brief Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_EnableClockSleep\n + * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB1LPENR DMA1LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR DMA2LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ADC12LPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ARTLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1MACLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1TXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR ETH1RXLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB1OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSLPEN LL_C2_AHB1_GRP1_DisableClockSleep\n + * AHB1LPENR USB2OTGHSULPILPEN LL_C2_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_ADC12 + * @arg @ref LL_AHB1_GRP1_PERIPH_ART (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable C2 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_EnableClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_C2_AHB2_GRP1_DisableClock\n + * AHB2ENR SDMMC2EN LL_C2_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB2ENR, Periphs); +} + +/** + * @brief Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_EnableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB2LPENR DCMILPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR CRYPLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR HASHLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR RNGLPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR SDMMC2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM1LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM2LPEN LL_C2_AHB2_GRP1_DisableClockSleep\n + * AHB2LPENR D2SRAM3LPEN LL_C2_AHB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2 + * @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ + +/** + * @brief Enable C2 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_EnableClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 AHB4 peripherals clock. + * @rmtoll AHB4ENR GPIOAEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOBEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOCEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIODEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOEEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOFEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOGEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOHEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOIEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOJEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR GPIOKEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR CRCEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR BDMAEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC3EN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR HSEMEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR BKPRAMEN LL_C2_AHB4_GRP1_DisableClock\n + * AHB4ENR SRAM4EN LL_C2_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB4ENR, Periphs); +} + +/** + * @brief Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_EnableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->AHB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHB4LPENR GPIOALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOBLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIODLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOELPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOFLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOGLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOHLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOILPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOJLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR GPIOKLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR CRCLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR BDMALPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR ADC3LPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR BKPRAMLPEN LL_C2_AHB4_GRP1_DisableClockSleep\n + * AHB4LPENR SRAM4LPEN LL_C2_AHB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ + * @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK + * @arg @ref LL_AHB4_GRP1_PERIPH_CRC (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BDMA + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM + * @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4 + * @retval None +*/ +__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB3 APB3 + * @{ + */ + +/** + * @brief Enable C2 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_EnableClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_EnableClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB3 peripheral clock is enabled or not + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_IsEnabledClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_IsEnabledClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB3 peripherals clock. + * @rmtoll APB3ENR LTDCEN LL_C2_APB3_GRP1_DisableClock\n + * APB3ENR DSIEN LL_C2_APB3_GRP1_DisableClock\n + * APB3ENR WWDG1EN LL_C2_APB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB3ENR, Periphs); +} + +/** + * @brief Enable C2 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_EnableClockSleep\n + * APB3LPENR DSILPEN LL_C2_APB3_GRP1_EnableClockSleep\n + * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB3 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB3LPENR LTDCLPEN LL_C2_APB3_GRP1_DisableClockSleep\n + * APB3LPENR DSILPEN LL_C2_APB3_GRP1_DisableClockSleep\n + * APB3LPENR WWDG1LPEN LL_C2_APB3_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB3_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB3_GRP1_PERIPH_WWDG1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable C2 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_EnableClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1LENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB1 peripheral clock is enabled or not + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_IsEnabledClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB1 peripherals clock. + * @rmtoll APB1LENR TIM2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM4EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM5EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM6EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM7EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM12EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM13EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR TIM14EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR LPTIM1EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR WWDG2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPI2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPI3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR SPDIFRXEN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR USART2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR USART3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART4EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART5EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C1EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C2EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR I2C3EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR CECEN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR DAC12EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART7EN LL_C2_APB1_GRP1_DisableClock\n + * APB1LENR UART8EN LL_C2_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1LENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_EnableClockSleep\n + * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1LLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1LLPENR TIM2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM6LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM13LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR TIM14LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR LPTIM1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR WWDG2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPI3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR SPDIFRXLPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR USART3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART4LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART5LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C1LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C2LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR I2C3LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR CECLPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR DAC12LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART7LPEN LL_C2_APB1_GRP1_DisableClockSleep\n + * APB1LLPENR UART8LPEN LL_C2_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_CEC + * @arg @ref LL_APB1_GRP1_PERIPH_DAC12 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_EnableClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1HENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB1 peripheral clock is enabled or not + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_IsEnabledClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB1 peripherals clock. + * @rmtoll APB1HENR CRSEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR SWPMIEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR OPAMPEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR MDIOSEN LL_C2_APB1_GRP2_DisableClock\n + * APB1HENR FDCANEN LL_C2_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1HENR, Periphs); +} + +/** + * @brief Enable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_EnableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB1HLPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1HLPENR CRSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR SWPMILPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR OPAMPLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR MDIOSLPEN LL_C2_APB1_GRP2_DisableClockSleep\n + * APB1HLPENR FDCANLPEN LL_C2_APB1_GRP2_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_CRS + * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 + * @arg @ref LL_APB1_GRP2_PERIPH_OPAMP + * @arg @ref LL_APB1_GRP2_PERIPH_MDIOS + * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN + * @arg @ref LL_APB1_GRP2_PERIPH_TIM23 (*) + * @arg @ref LL_APB1_GRP2_PERIPH_TIM24 (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable C2 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_EnableClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_IsEnabledClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR SAI3EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_C2_APB2_GRP1_DisableClock\n + * APB2ENR HRTIMEN LL_C2_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB2ENR, Periphs); +} + +/** + * @brief Enable C2 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_EnableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2LPENR TIM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM8LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR USART6LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI4LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM15LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM16LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR TIM17LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SPI5LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI2LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR SAI3LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR DFSDM1LPEN LL_C2_APB2_GRP1_DisableClockSleep\n + * APB2LPENR HRTIMLPEN LL_C2_APB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 + * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @addtogroup BUS_LL_EF_APB4 APB4 + * @{ + */ + +/** + * @brief Enable C2 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_EnableClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if C2 APB4 peripheral clock is enabled or not + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_IsEnabledClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval uint32_t +*/ +__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U); +} + +/** + * @brief Disable C2 APB4 peripherals clock. + * @rmtoll APB4ENR SYSCFGEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPUART1EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR SPI6EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR I2C4EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM2EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM3EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM4EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR LPTIM5EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR COMP12EN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR VREFEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR RTCAPBEN LL_C2_APB4_GRP1_DisableClock\n + * APB4ENR SAI4EN LL_C2_APB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB4ENR, Periphs); +} + +/** + * @brief Enable C2 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_EnableClockSleep\n + * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC_C2->APB4LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable C2 APB4 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB4LPENR SYSCFGLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPUART1LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SPI6LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR I2C4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM2LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM3LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM4LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR LPTIM5LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR COMP12LPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR VREFLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR RTCAPBLPEN LL_C2_APB4_GRP1_DisableClockSleep\n + * APB4LPENR SAI4LPEN LL_C2_APB4_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB4_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB4_GRP1_PERIPH_SPI6 + * @arg @ref LL_APB4_GRP1_PERIPH_I2C4 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3 + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*) + * @arg @ref LL_APB4_GRP1_PERIPH_COMP12 + * @arg @ref LL_APB4_GRP1_PERIPH_VREF + * @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB + * @arg @ref LL_APB4_GRP1_PERIPH_SAI4 (*) + * + * (*) value not defined in all devices + * @retval None +*/ +__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC_C2->APB4LPENR, Periphs); +} + +/** + * @} + */ + +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_BUS_H */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h new file mode 100644 index 0000000..2b63e8f --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h @@ -0,0 +1,669 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_CORTEX_H +#define STM32H7xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01UL /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02UL /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03UL /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04UL /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */ +#if !defined(CORE_CM4) +#define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */ +#define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */ +#define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */ +#define LL_MPU_REGION_NUMBER11 0x0BUL /*!< REGION Number 11 */ +#define LL_MPU_REGION_NUMBER12 0x0CUL /*!< REGION Number 12 */ +#define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */ +#define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */ +#define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */ +#endif /* !defined(CORE_CM4) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ + +/* Legacy Define */ +#define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source); +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK)); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @arg @ref LL_MPU_REGION_NUMBER8 + * @arg @ref LL_MPU_REGION_NUMBER9 + * @arg @ref LL_MPU_REGION_NUMBER10 + * @arg @ref LL_MPU_REGION_NUMBER11 + * @arg @ref LL_MPU_REGION_NUMBER12 + * @arg @ref LL_MPU_REGION_NUMBER13 + * @arg @ref LL_MPU_REGION_NUMBER14 + * @arg @ref LL_MPU_REGION_NUMBER15 + * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_CORTEX_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crc.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crc.h new file mode 100644 index 0000000..7c5aa20 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crc.h @@ -0,0 +1,461 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_crc.h + * @author MCD Application Team + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_CRC_H +#define STM32H7xx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length + * @{ + */ +#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse + * @{ + */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ +#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ +#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse + * @{ + */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value + * @brief Normal representation of this polynomial value is + * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . + * @{ + */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @brief Configure size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize + * @param CRCx CRC Instance + * @param PolySize This parameter can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize) +{ + MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize); +} + +/** + * @brief Return size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); +} + +/** + * @brief Configure the reversal of the bit order of the input data + * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode); +} + +/** + * @brief Return type of reversal for input data bit order + * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); +} + +/** + * @brief Configure the reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode); +} + +/** + * @brief Return type of reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); +} + +/** + * @brief Initialize the Programmable initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to write the correct value + * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter. + * @rmtoll INIT INIT LL_CRC_SetInitialData + * @param CRCx CRC Instance + * @param InitCrc Value to be programmed in Programmable initial CRC value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) +{ + WRITE_REG(CRCx->INIT, InitCrc); +} + +/** + * @brief Return current Initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to read the correct value + * @rmtoll INIT INIT LL_CRC_GetInitialData + * @param CRCx CRC Instance + * @retval Value programmed in Programmable initial CRC value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->INIT)); +} + +/** + * @brief Initialize the Programmable polynomial value + * (coefficients of the polynomial to be used for CRC calculation). + * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter. + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_SetPolynomialCoef + * @param CRCx CRC Instance + * @param PolynomCoef Value to be programmed in Programmable Polynomial value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef) +{ + WRITE_REG(CRCx->POL, PolynomCoef); +} + +/** + * @brief Return current Programmable polynomial value + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_GetPolynomialCoef + * @param CRCx CRC Instance + * @retval Value programmed in Programmable Polynomial value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->POL)); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Write given 16-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData16 + * @param CRCx CRC Instance + * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) +{ + __IO uint16_t *pReg; + + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = InData; +} + +/** + * @brief Write given 8-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData8 + * @param CRCx CRC Instance + * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) +{ + *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData; +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return current CRC calculation result. 16 bits value is returned. + * @note This function is expected to be used in a 16 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData16 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). + */ +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) +{ + return (uint16_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 8 bits value is returned. + * @note This function is expected to be used in a 8 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData8 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) +{ + return (uint8_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 7 bits value is returned. + * @note This function is expected to be used in a 7 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData7 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) +{ + return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_CRC_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h new file mode 100644 index 0000000..86ce847 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_crs.h @@ -0,0 +1,780 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_CRS_H +#define STM32H7xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 64, which corresponds to the middle of the trimming interval. + * The trimming step is specified in the product datasheet. + * A higher TRIM value corresponds to a higher output frequency. + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 127 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_CRS_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h new file mode 100644 index 0000000..100a2c5 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -0,0 +1,3287 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_DMA_H +#define STM32H7xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_dmamux.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ +static const uint8_t LL_DMA_STR_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) +}; + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Macros DMA LL Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0). + */ +#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Stream + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX1_Request_selection + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_LL_FIFOMODE + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream + + This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_PBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_STREAM STREAM + * @{ + */ +#define LL_DMA_STREAM_0 0x00000000U +#define LL_DMA_STREAM_1 0x00000001U +#define LL_DMA_STREAM_2 0x00000002U +#define LL_DMA_STREAM_3 0x00000003U +#define LL_DMA_STREAM_4 0x00000004U +#define LL_DMA_STREAM_5 0x00000005U +#define LL_DMA_STREAM_6 0x00000006U +#define LL_DMA_STREAM_7 0x00000007U +#define LL_DMA_STREAM_ALL 0xFFFF0000U +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE MODE + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ +#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + * @{ + */ +#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH PERIPH + * @{ + */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY MEMORY + * @{ + */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + * @{ + */ +#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ +#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY PRIORITY + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + + +/** @defgroup DMA_LL_EC_MBURST MBURST + * @{ + */ +#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ +#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ +#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ +#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PBURST PBURST + * @{ + */ +#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ +#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ +#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ +#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + * @{ + */ +#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ +#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + * @{ + */ +#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ +#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ +#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ +#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ +#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ +#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + * @{ + */ +#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + * @{ + */ +/** + * @brief Convert DMAx_Streamy into DMAx + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval LL_DMA_STREAM_y + */ +#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + LL_DMA_STREAM_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + * @param __DMA_INSTANCE__ DMAx + * @param __STREAM__ LL_DMA_STREAM_y + * @retval DMAx_Streamy + */ +#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ + DMA2_Stream7) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA stream. + * @rmtoll CR EN LL_DMA_EnableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); +} + +/** + * @brief Disable DMA stream. + * @rmtoll CR EN LL_DMA_DisableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); +} + +/** + * @brief Check if DMA stream is enabled or disabled. + * @rmtoll CR EN LL_DMA_IsEnabledStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters linked to DMA transfer. + * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + * CR CIRC LL_DMA_ConfigTransfer\n + * CR PINC LL_DMA_ConfigTransfer\n + * CR MINC LL_DMA_ConfigTransfer\n + * CR PSIZE LL_DMA_ConfigTransfer\n + * CR MSIZE LL_DMA_ConfigTransfer\n + * CR PL LL_DMA_ConfigTransfer\n + * CR PFCTRL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + *@retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, + DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR)); +} + +/** + * @brief Set DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_SetMode\n + * CR PFCTRL LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); +} + +/** + * @brief Get DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_GetMode\n + * CR PFCTRL LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size); +} + +/** + * @brief Get Memory size. + * @rmtoll CR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE)); +} + +/** + * @brief Set Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param OffsetSize This parameter can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize); +} + +/** + * @brief Get Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + */ +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS)); +} + +/** + * @brief Set Stream priority level. + * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority); +} + +/** + * @brief Get Stream priority level. + * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); +} + +/** + * @brief Enable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + +/** + * @brief Disable DMA stream bufferable transfer. + * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); +} + +/** + * @brief Set Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_SetDataLength + * @note This action has no effect if + * stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param NbData Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_GetDataLength + * @note Once the stream is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT)); +} +/** + * @brief Set DMA request for DMA Streams on DMAMUX Channel x. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request) +{ + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. + * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mburst This parameter can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst); +} + +/** + * @brief Get Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST)); +} + +/** + * @brief Set Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Pburst This parameter can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst); +} + +/** + * @brief Get Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Get FIFO status. + * @rmtoll FCR FS LL_DMA_GetFIFOStatus + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOSTATUS_0_25 + * @arg @ref LL_DMA_FIFOSTATUS_25_50 + * @arg @ref LL_DMA_FIFOSTATUS_50_75 + * @arg @ref LL_DMA_FIFOSTATUS_75_100 + * @arg @ref LL_DMA_FIFOSTATUS_EMPTY + * @arg @ref LL_DMA_FIFOSTATUS_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS)); +} + +/** + * @brief Disable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Enable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Select FIFO threshold. + * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold); +} + +/** + * @brief Get FIFO threshold. + * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH)); +} + +/** + * @brief Configure the FIFO . + * @rmtoll FCR FTH LL_DMA_ConfigFifo\n + * FCR DMDIS LL_DMA_ConfigFifo + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param FifoMode This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOMODE_ENABLE + * @arg @ref LL_DMA_FIFOMODE_DISABLE + * @param FifoThreshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA stream is enabled. + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * PAR PA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DstAddress Between 0 to 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @rmtoll PAR PA LL_DMA_SetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param PeriphAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress); +} + +/** + * @brief Get the Memory address. + * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); +} + +/** + * @brief Get the Peripheral address. + * @rmtoll PAR PA LL_DMA_GetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_SetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_GetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Stream 0 half transfer flag. + * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 half transfer flag. + * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 half transfer flag. + * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 half transfer flag. + * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 half transfer flag. + * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 half transfer flag. + * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 half transfer flag. + * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 half transfer flag. + * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 transfer complete flag. + * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 transfer complete flag. + * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 transfer complete flag. + * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 transfer complete flag. + * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 transfer complete flag. + * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 transfer complete flag. + * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 transfer complete flag. + * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 transfer complete flag. + * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 transfer error flag. + * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 transfer error flag. + * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 transfer error flag. + * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 transfer error flag. + * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 transfer error flag. + * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 transfer error flag. + * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 transfer error flag. + * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 transfer error flag. + * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 direct mode error flag. + * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 direct mode error flag. + * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 direct mode error flag. + * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 direct mode error flag. + * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 direct mode error flag. + * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 direct mode error flag. + * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 direct mode error flag. + * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 direct mode error flag. + * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 0 FIFO error flag. + * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 1 FIFO error flag. + * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 2 FIFO error flag. + * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 3 FIFO error flag. + * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 4 FIFO error flag. + * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 5 FIFO error flag. + * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 6 FIFO error flag. + * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Stream 7 FIFO error flag. + * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Stream 0 half transfer flag. + * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0); +} + +/** + * @brief Clear Stream 1 half transfer flag. + * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1); +} + +/** + * @brief Clear Stream 2 half transfer flag. + * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2); +} + +/** + * @brief Clear Stream 3 half transfer flag. + * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3); +} + +/** + * @brief Clear Stream 4 half transfer flag. + * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4); +} + +/** + * @brief Clear Stream 5 half transfer flag. + * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5); +} + +/** + * @brief Clear Stream 6 half transfer flag. + * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6); +} + +/** + * @brief Clear Stream 7 half transfer flag. + * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7); +} + +/** + * @brief Clear Stream 0 transfer complete flag. + * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0); +} + +/** + * @brief Clear Stream 1 transfer complete flag. + * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1); +} + +/** + * @brief Clear Stream 2 transfer complete flag. + * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2); +} + +/** + * @brief Clear Stream 3 transfer complete flag. + * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3); +} + +/** + * @brief Clear Stream 4 transfer complete flag. + * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4); +} + +/** + * @brief Clear Stream 5 transfer complete flag. + * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5); +} + +/** + * @brief Clear Stream 6 transfer complete flag. + * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6); +} + +/** + * @brief Clear Stream 7 transfer complete flag. + * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7); +} + +/** + * @brief Clear Stream 0 transfer error flag. + * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0); +} + +/** + * @brief Clear Stream 1 transfer error flag. + * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1); +} + +/** + * @brief Clear Stream 2 transfer error flag. + * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2); +} + +/** + * @brief Clear Stream 3 transfer error flag. + * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3); +} + +/** + * @brief Clear Stream 4 transfer error flag. + * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4); +} + +/** + * @brief Clear Stream 5 transfer error flag. + * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5); +} + +/** + * @brief Clear Stream 6 transfer error flag. + * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6); +} + +/** + * @brief Clear Stream 7 transfer error flag. + * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7); +} + +/** + * @brief Clear Stream 0 direct mode error flag. + * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0); +} + +/** + * @brief Clear Stream 1 direct mode error flag. + * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1); +} + +/** + * @brief Clear Stream 2 direct mode error flag. + * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2); +} + +/** + * @brief Clear Stream 3 direct mode error flag. + * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3); +} + +/** + * @brief Clear Stream 4 direct mode error flag. + * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4); +} + +/** + * @brief Clear Stream 5 direct mode error flag. + * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5); +} + +/** + * @brief Clear Stream 6 direct mode error flag. + * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6); +} + +/** + * @brief Clear Stream 7 direct mode error flag. + * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7); +} + +/** + * @brief Clear Stream 0 FIFO error flag. + * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0); +} + +/** + * @brief Clear Stream 1 FIFO error flag. + * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1); +} + +/** + * @brief Clear Stream 2 FIFO error flag. + * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2); +} + +/** + * @brief Clear Stream 3 FIFO error flag. + * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3); +} + +/** + * @brief Clear Stream 4 FIFO error flag. + * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4); +} + +/** + * @brief Clear Stream 5 FIFO error flag. + * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5); +} + +/** + * @brief Clear Stream 6 FIFO error flag. + * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6); +} + +/** + * @brief Clear Stream 7 FIFO error flag. + * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Enable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_EnableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Enable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_EnableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Disable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_DisableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Disable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_DisableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Check if Half transfer interrupt is enabled. + * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error nterrup is enabled. + * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer complete interrupt is enabled. + * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL); +} + +/** + * @brief Check if Direct mode error interrupt is enabled. + * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if FIFO error interrupt is enabled. + * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + + return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_DMA_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h new file mode 100644 index 0000000..daea475 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma2d.h @@ -0,0 +1,2231 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dma2d.h + * @author MCD Application Team + * @brief Header file of DMA2D LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_DMA2D_H +#define STM32H7xx_LL_DMA2D_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMA2D) + +/** @defgroup DMA2D_LL DMA2D + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures + * @{ + */ + +/** + * @brief LL DMA2D Init Structure Definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the DMA2D transfer mode. + - This parameter can be one value of @ref DMA2D_LL_EC_MODE. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetMode(). */ + + uint32_t ColorMode; /*!< Specifies the color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + + uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputGreen; /*!< Specifies the Green value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputRed; /*!< Specifies the Red value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter is not considered if RGB888 or RGB565 color mode is selected. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputMemoryAddress; /*!< Specifies the memory address. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ + + uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ + + uint32_t LineOffsetMode; /*!< Specifies the output line offset mode. + - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ + + uint32_t LineOffset; /*!< Specifies the output line offset value. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetLineOffset(). */ + + uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ + + uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ + + uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ + + uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. + - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ + +} LL_DMA2D_InitTypeDef; + +/** + * @brief LL DMA2D Layer Configuration Structure Definition + */ +typedef struct +{ + uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, + - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */ + + uint32_t LineOffset; /*!< Specifies the foreground or background line offset value. + - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer, + - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */ + + uint32_t ColorMode; /*!< Specifies the foreground or background color mode. + - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */ + + uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode. + - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */ + + uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */ + + uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */ + + uint32_t Alpha; /*!< Specifies the foreground or background Alpha value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */ + + uint32_t Blue; /*!< Specifies the foreground or background Blue color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */ + + uint32_t Green; /*!< Specifies the foreground or background Green color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */ + + uint32_t Red; /*!< Specifies the foreground or background Red color value. + - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer, + - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ + + uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, + - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */ + + uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode. + - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */ + + uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode. + This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP . + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, + - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ + + uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode + This parameter is applicable for foreground layer only. + This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING + + This parameter can be modified afterwards using unitary functions + - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */ + +} LL_DMA2D_LayerCfgTypeDef; + +/** + * @brief LL DMA2D Output Color Structure Definition + */ +typedef struct +{ + uint32_t ColorMode; /*!< Specifies the color format of the output image. + - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. + + This parameter can be modified afterwards using + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + + uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputGreen; /*!< Specifies the Green value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputRed; /*!< Specifies the Red value of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + + uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter is not considered if RGB888 or RGB565 color mode is selected. + + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + function @ref LL_DMA2D_ConfigOutputColor(). */ + +} LL_DMA2D_ColorTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants + * @{ + */ + +/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA2D_ReadReg function + * @{ + */ +#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ +#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ +#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ +#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ +#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ +#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions + * @{ + */ +#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ +#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ +#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ +#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ +#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ +#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_MODE Mode + * @{ + */ +#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ +#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ +#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ +#define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */ +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */ +#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode + * @{ + */ +#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */ +#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */ +#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */ +#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode + * @{ + */ +#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */ +#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */ +#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */ +#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */ +#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */ +#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */ +#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */ +#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ +#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ +#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ +#define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode + * @{ + */ +#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ +#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by + programmed alpha value */ +#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by + programmed alpha value with, + original alpha channel value */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode + * @{ + */ +#define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */ +#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap + * @{ + */ +#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */ +#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion + * @{ + */ +#define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */ +#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */ +/** + * @} + */ + + +/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode + * @{ + */ +#define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */ +#define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode + * @{ + */ +#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ +#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */ +/** + * @} + */ + +/** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling + * @{ + */ +#define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ +#define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */ +#define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros + * @{ + */ + +/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in DMA2D register. + * @param __INSTANCE__ DMA2D Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA2D register. + * @param __INSTANCE__ DMA2D Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions + * @{ + */ + +/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions + * @{ + */ + +/** + * @brief Start a DMA2D transfer. + * @rmtoll CR START LL_DMA2D_Start + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_START); +} + +/** + * @brief Indicate if a DMA2D transfer is ongoing. + * @rmtoll CR START LL_DMA2D_IsTransferOngoing + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); +} + +/** + * @brief Suspend DMA2D transfer. + * @note This API can be used to suspend automatic foreground or background CLUT loading. + * @rmtoll CR SUSP LL_DMA2D_Suspend + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); +} + +/** + * @brief Resume DMA2D transfer. + * @note This API can be used to resume automatic foreground or background CLUT loading. + * @rmtoll CR SUSP LL_DMA2D_Resume + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START); +} + +/** + * @brief Indicate if DMA2D transfer is suspended. + * @note This API can be used to indicate whether or not automatic foreground or + * background CLUT loading is suspended. + * @rmtoll CR SUSP LL_DMA2D_IsSuspended + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Abort DMA2D transfer. + * @note This API can be used to abort automatic foreground or background CLUT loading. + * @rmtoll CR ABORT LL_DMA2D_Abort + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); +} + +/** + * @brief Indicate if DMA2D transfer is aborted. + * @note This API can be used to indicate whether or not automatic foreground or + * background CLUT loading is aborted. + * @rmtoll CR ABORT LL_DMA2D_IsAborted + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); +} + +/** + * @brief Set DMA2D mode. + * @rmtoll CR MODE LL_DMA2D_SetMode + * @param DMA2Dx DMA2D Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_MODE_M2M + * @arg @ref LL_DMA2D_MODE_M2M_PFC + * @arg @ref LL_DMA2D_MODE_M2M_BLEND + * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); +} + +/** + * @brief Return DMA2D mode + * @rmtoll CR MODE LL_DMA2D_GetMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_MODE_M2M + * @arg @ref LL_DMA2D_MODE_M2M_PFC + * @arg @ref LL_DMA2D_MODE_M2M_BLEND + * @arg @ref LL_DMA2D_MODE_R2M + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG + * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); +} + +/** + * @brief Set DMA2D output color mode. + * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D output color mode. + * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); +} + +/** + * @brief Set DMA2D output Red Blue swap mode. + * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D output Red Blue swap mode. + * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); +} + +/** + * @brief Set DMA2D output alpha inversion mode. + * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D output alpha inversion mode. + * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); +} + + +/** + * @brief Set DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @param OutputSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode) +{ + MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode); +} + +/** + * @brief Return DMA2D output swap mode. + * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR + * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); +} + +/** + * @brief Set DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @param LineOffsetMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode) +{ + MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode); +} + +/** + * @brief Return DMA2D line offset mode. + * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS + * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); +} + +/** + * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll OOR LO LL_DMA2D_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll OOR LO LL_DMA2D_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); +} + +/** + * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). + * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines + * @param DMA2Dx DMA2D Instance + * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines) +{ + MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); +} + +/** + * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) + * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines + * @param DMA2Dx DMA2D Instance + * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); +} + +/** + * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). + * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines + * @param DMA2Dx DMA2D Instance + * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines) +{ + MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines); +} + +/** + * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). + * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines + * @param DMA2Dx DMA2D Instance + * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); +} + +/** + * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr + * @param DMA2Dx DMA2D Instance + * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress); +} + +/** + * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); +} + +/** + * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits). + * @note Output color format depends on output color mode, ARGB8888, RGB888, + * RGB565, ARGB1555 or ARGB4444. + * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting + * with respect to color mode is not done by the user code. + * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n + * OCOLR GREEN LL_DMA2D_SetOutputColor\n + * OCOLR RED LL_DMA2D_SetOutputColor\n + * OCOLR ALPHA LL_DMA2D_SetOutputColor + * @param DMA2Dx DMA2D Instance + * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) +{ + MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ + OutputColor); +} + +/** + * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits). + * @note Alpha channel and red, green, blue color values must be retrieved from the returned + * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) + * as set by @ref LL_DMA2D_SetOutputColorMode. + * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n + * OCOLR GREEN LL_DMA2D_GetOutputColor\n + * OCOLR RED LL_DMA2D_GetOutputColor\n + * OCOLR ALPHA LL_DMA2D_GetOutputColor + * @param DMA2Dx DMA2D Instance + * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ + (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); +} + +/** + * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). + * @rmtoll LWR LW LL_DMA2D_SetLineWatermark + * @param DMA2Dx DMA2D Instance + * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark) +{ + MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark); +} + +/** + * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). + * @rmtoll LWR LW LL_DMA2D_GetLineWatermark + * @param DMA2Dx DMA2D Instance + * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); +} + +/** + * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits). + * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime + * @param DMA2Dx DMA2D Instance + * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime) +{ + MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos)); +} + +/** + * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits). + * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime + * @param DMA2Dx DMA2D Instance + * @retval Dead time value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); +} + +/** + * @brief Enable DMA2D dead time functionality. + * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); +} + +/** + * @brief Disable DMA2D dead time functionality. + * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); +} + +/** + * @brief Indicate if DMA2D dead time functionality is enabled. + * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); +} + +/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions + * @{ + */ + +/** + * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr + * @param DMA2Dx DMA2D Instance + * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress); +} + +/** + * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); +} + +/** + * @brief Enable DMA2D foreground CLUT loading. + * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START); +} + +/** + * @brief Indicate if DMA2D foreground CLUT loading is enabled. + * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); +} + +/** + * @brief Set DMA2D foreground color mode. + * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D foreground color mode. + * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); +} + +/** + * @brief Set DMA2D foreground alpha mode. + * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode + * @param DMA2Dx DMA2D Instance + * @param AphaMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode); +} + +/** + * @brief Return DMA2D foreground alpha mode. + * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); +} + +/** + * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha + * @param DMA2Dx DMA2D Instance + * @param Alpha Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos)); +} + +/** + * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha + * @param DMA2Dx DMA2D Instance + * @retval Alpha value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); +} + +/** + * @brief Set DMA2D foreground Red Blue swap mode. + * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D foreground Red Blue swap mode. + * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); +} + +/** + * @brief Set DMA2D foreground alpha inversion mode. + * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D foreground alpha inversion mode. + * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); +} + +/** + * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); +} + +/** + * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \ + ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue)); +} + +/** + * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos)); +} + +/** + * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor + * @param DMA2Dx DMA2D Instance + * @retval Red color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); +} + +/** + * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor + * @param DMA2Dx DMA2D Instance + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos)); +} + +/** + * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor + * @param DMA2Dx DMA2D Instance + * @retval Green color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); +} + +/** + * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor + * @param DMA2Dx DMA2D Instance + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue); +} + +/** + * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor + * @param DMA2Dx DMA2D Instance + * @retval Blue color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); +} + +/** + * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress); +} + +/** + * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); +} + +/** + * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize + * @param DMA2Dx DMA2D Instance + * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos)); +} + +/** + * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize + * @param DMA2Dx DMA2D Instance + * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); +} + +/** + * @brief Set DMA2D foreground CLUT color mode. + * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @param CLUTColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode); +} + +/** + * @brief Return DMA2D foreground CLUT color mode. + * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); +} + +/** + * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). + * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling + * @param DMA2Dx DMA2D Instance + * @param ChromaSubSampling This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CSS_444 + * @arg @ref LL_DMA2D_CSS_422 + * @arg @ref LL_DMA2D_CSS_420 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling) +{ + MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling); +} + +/** + * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). + * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CSS_444 + * @arg @ref LL_DMA2D_CSS_422 + * @arg @ref LL_DMA2D_CSS_420 + */ +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); +} +/** + * @} + */ + +/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions + * @{ + */ + +/** + * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr + * @param DMA2Dx DMA2D Instance + * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress); +} + +/** + * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); +} + +/** + * @brief Enable DMA2D background CLUT loading. + * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START); +} + +/** + * @brief Indicate if DMA2D background CLUT loading is enabled. + * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); +} + +/** + * @brief Set DMA2D background color mode. + * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode + * @param DMA2Dx DMA2D Instance + * @param ColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode); +} + +/** + * @brief Return DMA2D background color mode. + * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 + * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 + * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 + * @arg @ref LL_DMA2D_INPUT_MODE_L8 + * @arg @ref LL_DMA2D_INPUT_MODE_AL44 + * @arg @ref LL_DMA2D_INPUT_MODE_AL88 + * @arg @ref LL_DMA2D_INPUT_MODE_L4 + * @arg @ref LL_DMA2D_INPUT_MODE_A8 + * @arg @ref LL_DMA2D_INPUT_MODE_A4 + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); +} + +/** + * @brief Set DMA2D background alpha mode. + * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode + * @param DMA2Dx DMA2D Instance + * @param AphaMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode); +} + +/** + * @brief Return DMA2D background alpha mode. + * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF + * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE + * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); +} + +/** + * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha + * @param DMA2Dx DMA2D Instance + * @param Alpha Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos)); +} + +/** + * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha + * @param DMA2Dx DMA2D Instance + * @retval Alpha value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); +} + +/** + * @brief Set DMA2D background Red Blue swap mode. + * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @param RBSwapMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode); +} + +/** + * @brief Return DMA2D background Red Blue swap mode. + * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_RB_MODE_REGULAR + * @arg @ref LL_DMA2D_RB_MODE_SWAP + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); +} + +/** + * @brief Set DMA2D background alpha inversion mode. + * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @param AlphaInversionMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode); +} + +/** + * @brief Return DMA2D background alpha inversion mode. + * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_ALPHA_REGULAR + * @arg @ref LL_DMA2D_ALPHA_INVERTED + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); +} + +/** + * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset + * @param DMA2Dx DMA2D Instance + * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) +{ + MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset); +} + +/** + * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). + * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset + * @param DMA2Dx DMA2D Instance + * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); +} + +/** + * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \ + ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue)); +} + +/** + * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor + * @param DMA2Dx DMA2D Instance + * @param Red Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos)); +} + +/** + * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor + * @param DMA2Dx DMA2D Instance + * @retval Red color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); +} + +/** + * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor + * @param DMA2Dx DMA2D Instance + * @param Green Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos)); +} + +/** + * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor + * @param DMA2Dx DMA2D Instance + * @retval Green color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); +} + +/** + * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor + * @param DMA2Dx DMA2D Instance + * @param Blue Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) +{ + MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue); +} + +/** + * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). + * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor + * @param DMA2Dx DMA2D Instance + * @retval Blue color value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); +} + +/** + * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) +{ + LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress); +} + +/** + * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). + * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr + * @param DMA2Dx DMA2D Instance + * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); +} + +/** + * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize + * @param DMA2Dx DMA2D Instance + * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos)); +} + +/** + * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). + * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize + * @param DMA2Dx DMA2D Instance + * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); +} + +/** + * @brief Set DMA2D background CLUT color mode. + * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @param CLUTColorMode This parameter can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) +{ + MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode); +} + +/** + * @brief Return DMA2D background CLUT color mode. + * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode + * @param DMA2Dx DMA2D Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 + * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 + */ +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +{ + return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management + * @{ + */ + +/** + * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not + * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not + * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not + * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not + * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not + * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not + * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear DMA2D Configuration Error Interrupt Flag + * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); +} + +/** + * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag + * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); +} + +/** + * @brief Clear DMA2D CLUT Access Error Interrupt Flag + * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); +} + +/** + * @brief Clear DMA2D Transfer Watermark Interrupt Flag + * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); +} + +/** + * @brief Clear DMA2D Transfer Complete Interrupt Flag + * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); +} + +/** + * @brief Clear DMA2D Transfer Error Interrupt Flag + * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx) +{ + WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); +} + +/** + * @} + */ + +/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management + * @{ + */ + +/** + * @brief Enable Configuration Error Interrupt + * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); +} + +/** + * @brief Enable CLUT Transfer Complete Interrupt + * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); +} + +/** + * @brief Enable CLUT Access Error Interrupt + * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); +} + +/** + * @brief Enable Transfer Watermark Interrupt + * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); +} + +/** + * @brief Enable Transfer Complete Interrupt + * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); +} + +/** + * @brief Enable Transfer Error Interrupt + * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); +} + +/** + * @brief Disable Configuration Error Interrupt + * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); +} + +/** + * @brief Disable CLUT Transfer Complete Interrupt + * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); +} + +/** + * @brief Disable CLUT Access Error Interrupt + * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); +} + +/** + * @brief Disable Transfer Watermark Interrupt + * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); +} + +/** + * @brief Disable Transfer Complete Interrupt + * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); +} + +/** + * @brief Disable Transfer Error Interrupt + * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE + * @param DMA2Dx DMA2D Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); +} + +/** + * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled. + * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. + * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. + * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. + * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. + * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled. + * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE + * @param DMA2Dx DMA2D Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +{ + return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); +} + + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions + * @{ + */ + +ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); +void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); +void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); +void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); +void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); +uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (DMA2D) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_DMA2D_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h new file mode 100644 index 0000000..bf4cffa --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h @@ -0,0 +1,2436 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_DMAMUX_H +#define STM32H7xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) || defined (DMAMUX2) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004U + +/* Define used to get DMAMUX RequestGenerator offset */ +#define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE) +/* Define used to get DMAMUX Channel Status offset */ +#define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE) +/* Define used to get DMAMUX RequestGenerator status offset */ +#define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ +#define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */ +#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */ +#define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */ +#define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX1_Request_selection DMAMUX1 Request selection + * @brief DMAMUX1 Request selection + * @{ + */ +/* DMAMUX1 requests */ +#define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */ +#define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ +#define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ +#define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ +#define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ +#define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */ +#define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */ +#define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */ +#define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */ +#define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */ +#define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */ +#define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */ +#define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */ +#define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */ +#define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */ +#define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */ +#define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */ +#define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */ +#define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */ +#define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */ +#define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */ +#define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */ +#define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */ +#define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */ +#define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */ +#define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */ +#define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */ +#define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */ +#define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */ +#define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */ +#define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */ +#define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */ +#define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */ +#define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */ +#define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */ +#define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */ +#define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */ +#define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */ +#define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */ +#define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */ +#define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */ +#define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */ +#define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */ +#define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */ +#define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */ +#define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */ +#define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */ +#define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */ +#define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */ +#define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */ +#define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */ +#define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */ +#define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */ +#define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */ +#define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */ +#define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */ +#define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */ +#define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */ +#define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */ +#define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */ +#define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */ +#define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */ +#define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */ +#define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */ +#define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */ +#define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */ +#define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */ +#define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */ +#define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */ +#define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */ +#define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */ +#define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */ +#define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */ +#define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */ +#if defined (PSSI) +#define LL_DMAMUX1_REQ_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */ +#define LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */ +#else +#define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */ +#endif /* PSSI */ +#define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */ +#define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */ +#define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */ +#define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */ +#define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */ +#define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */ +#define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */ +#define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */ +#define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */ +#define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */ +#define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */ +#define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */ +#define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */ +#if defined(SAI2) +#define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */ +#define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */ +#endif /* SAI2 */ +#define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */ +#define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */ +#define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request */ +#define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */ +#if defined (HRTIM1) +#define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6 */ +#endif /* HRTIM1 */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM1 Filter2 request */ +#define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM1 Filter3 request */ +#define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */ +#define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */ +#define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */ +#define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */ +#define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */ +#define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */ +#define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */ +#define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */ +#if defined (SAI3) +#define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */ +#define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */ +#endif /* SAI3 */ +#if defined (ADC3) +#define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */ +#endif /* ADC3 */ +#if defined (UART9) +#define LL_DMAMUX1_REQ_UART9_RX 116U /*!< DMAMUX1 UART9 RX request */ +#define LL_DMAMUX1_REQ_UART9_TX 117U /*!< DMAMUX1 UART9 TX request */ +#endif /* UART9 */ +#if defined (USART10) +#define LL_DMAMUX1_REQ_USART10_RX 118U /*!< DMAMUX1 USART10 RX request */ +#define LL_DMAMUX1_REQ_USART10_TX 119U /*!< DMAMUX1 USART10 TX request */ +#endif /* USART10 */ +#if defined(FMAC) +#define LL_DMAMUX1_REQ_FMAC_READ 120U /*!< DMAMUX1 FMAC Read request */ +#define LL_DMAMUX1_REQ_FMAC_WRITE 121U /*!< DMAMUX1 FMAC Write request */ +#endif /* FMAC */ +#if defined(CORDIC) +#define LL_DMAMUX1_REQ_CORDIC_READ 122U /*!< DMAMUX1 CORDIC Read request */ +#define LL_DMAMUX1_REQ_CORDIC_WRITE 123U /*!< DMAMUX1 CORDIC Write request */ +#endif /* CORDIC */ +#if defined(I2C5) +#define LL_DMAMUX1_REQ_I2C5_RX 124U /*!< DMAMUX1 I2C5 RX request */ +#define LL_DMAMUX1_REQ_I2C5_TX 125U /*!< DMAMUX1 I2C5 TX request */ +#endif /* I2C5 */ +#if defined(TIM23) +#define LL_DMAMUX1_REQ_TIM23_CH1 126U /*!< DMAMUX1 TIM23 CH1 request */ +#define LL_DMAMUX1_REQ_TIM23_CH2 127U /*!< DMAMUX1 TIM23 CH2 request */ +#define LL_DMAMUX1_REQ_TIM23_CH3 128U /*!< DMAMUX1 TIM23 CH3 request */ +#define LL_DMAMUX1_REQ_TIM23_CH4 129U /*!< DMAMUX1 TIM23 CH4 request */ +#define LL_DMAMUX1_REQ_TIM23_UP 130U /*!< DMAMUX1 TIM23 UP request */ +#define LL_DMAMUX1_REQ_TIM23_TRIG 131U /*!< DMAMUX1 TIM23 TRIG request */ +#endif /* TIM23 */ +#if defined(TIM24) +#define LL_DMAMUX1_REQ_TIM24_CH1 132U /*!< DMAMUX1 TIM24 CH1 request */ +#define LL_DMAMUX1_REQ_TIM24_CH2 133U /*!< DMAMUX1 TIM24 CH2 request */ +#define LL_DMAMUX1_REQ_TIM24_CH3 134U /*!< DMAMUX1 TIM24 CH3 request */ +#define LL_DMAMUX1_REQ_TIM24_CH4 135U /*!< DMAMUX1 TIM24 CH4 request */ +#define LL_DMAMUX1_REQ_TIM24_UP 136U /*!< DMAMUX1 TIM24 UP request */ +#define LL_DMAMUX1_REQ_TIM24_TRIG 137U /*!< DMAMUX1 TIM24 TRIG request */ +#endif /* TIM24 */ +/** + * @} + */ + +/** @defgroup DMAMUX2_Request_selection DMAMUX2 Request selection + * @brief DMAMUX2 Request selection + * @{ + */ +/* DMAMUX2 requests */ +#define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */ +#define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */ +#define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */ +#define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */ +#define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */ +#define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */ +#define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */ +#define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */ +#define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */ +#define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */ +#define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */ +#define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */ +#define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */ +#define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */ +#define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */ +#if defined (SAI4) +#define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */ +#define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */ +#endif /* SAI4 */ +#if defined (ADC3) +#define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */ +#endif /* ADC3 */ +#if defined (DAC2) +#define LL_DMAMUX2_REQ_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */ +#endif /* DAC2 */ +#if defined (DFSDM2_Channel0) +#define LL_DMAMUX2_REQ_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 Filter0 request */ +#endif /* DFSDM2_Channel0 */ +/** + * @} + */ + + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */ +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */ +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */ +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */ +#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */ +#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */ +#define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */ + +#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */ +#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */ +#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */ +#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */ +#define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */ +#define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */ +#define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */ +#define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */ +#define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */ +#define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */ +#define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */ +#define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */ + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +#define LL_DMAMUX_REQ_GEN_4 0x00000004U +#define LL_DMAMUX_REQ_GEN_5 0x00000005U +#define LL_DMAMUX_REQ_GEN_6 0x00000006U +#define LL_DMAMUX_REQ_GEN_7 0x00000007U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */ +#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */ +#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */ +#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */ +#define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */ +#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */ + +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */ +#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */ +#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */ +#if defined (LPTIM4) +#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */ +#endif /* LPTIM4 */ +#if defined (LPTIM5) +#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */ +#endif /* LPTIM5 */ +#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */ +#define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */ +#define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */ +#define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */ +#define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */ +#define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */ +#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */ +#define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */ +#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */ +#if defined (ADC3) +#define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */ +#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */ +#endif /* ADC3 */ +#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */ +#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. + * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7. + * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7. + * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_MEM2MEM + * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX1_REQ_ADC1 + * @arg @ref LL_DMAMUX1_REQ_ADC2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM1_UP + * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM1_COM + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM2_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM3_UP + * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM4_UP + * @arg @ref LL_DMAMUX1_REQ_I2C1_RX + * @arg @ref LL_DMAMUX1_REQ_I2C1_TX + * @arg @ref LL_DMAMUX1_REQ_I2C2_RX + * @arg @ref LL_DMAMUX1_REQ_I2C2_TX + * @arg @ref LL_DMAMUX1_REQ_SPI1_RX + * @arg @ref LL_DMAMUX1_REQ_SPI1_TX + * @arg @ref LL_DMAMUX1_REQ_SPI2_RX + * @arg @ref LL_DMAMUX1_REQ_SPI2_TX + * @arg @ref LL_DMAMUX1_REQ_USART1_RX + * @arg @ref LL_DMAMUX1_REQ_USART1_TX + * @arg @ref LL_DMAMUX1_REQ_USART2_RX + * @arg @ref LL_DMAMUX1_REQ_USART2_TX + * @arg @ref LL_DMAMUX1_REQ_USART3_RX + * @arg @ref LL_DMAMUX1_REQ_USART3_TX + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM8_UP + * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM8_COM + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 + * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 + * @arg @ref LL_DMAMUX1_REQ_TIM5_UP + * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG + * @arg @ref LL_DMAMUX1_REQ_SPI3_RX + * @arg @ref LL_DMAMUX1_REQ_SPI3_TX + * @arg @ref LL_DMAMUX1_REQ_UART4_RX + * @arg @ref LL_DMAMUX1_REQ_UART4_TX + * @arg @ref LL_DMAMUX1_REQ_UART5_RX + * @arg @ref LL_DMAMUX1_REQ_UART5_TX + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX1_REQ_TIM6_UP + * @arg @ref LL_DMAMUX1_REQ_TIM7_UP + * @arg @ref LL_DMAMUX1_REQ_USART6_RX + * @arg @ref LL_DMAMUX1_REQ_USART6_TX + * @arg @ref LL_DMAMUX1_REQ_I2C3_RX + * @arg @ref LL_DMAMUX1_REQ_I2C3_TX + * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) + * @arg @ref LL_DMAMUX1_REQ_CRYP_IN + * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT + * @arg @ref LL_DMAMUX1_REQ_HASH_IN + * @arg @ref LL_DMAMUX1_REQ_UART7_RX + * @arg @ref LL_DMAMUX1_REQ_UART7_TX + * @arg @ref LL_DMAMUX1_REQ_UART8_RX + * @arg @ref LL_DMAMUX1_REQ_UART8_TX + * @arg @ref LL_DMAMUX1_REQ_SPI4_RX + * @arg @ref LL_DMAMUX1_REQ_SPI4_TX + * @arg @ref LL_DMAMUX1_REQ_SPI5_RX + * @arg @ref LL_DMAMUX1_REQ_SPI5_TX + * @arg @ref LL_DMAMUX1_REQ_SAI1_A + * @arg @ref LL_DMAMUX1_REQ_SAI1_B + * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) + * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX + * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT + * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS + * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) + * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 + * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 + * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM15_UP + * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG + * @arg @ref LL_DMAMUX1_REQ_TIM15_COM + * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM16_UP + * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX1_REQ_TIM17_UP + * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) + * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) + * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) + * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) + * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) + * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) + * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) + * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) + * @arg @ref LL_DMAMUX2_REQ_MEM2MEM + * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 + * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 + * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX2_REQ_SPI6_RX + * @arg @ref LL_DMAMUX2_REQ_SPI6_TX + * @arg @ref LL_DMAMUX2_REQ_I2C4_RX + * @arg @ref LL_DMAMUX2_REQ_I2C4_TX + * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) + * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) + * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) + * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) + * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) + * + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0 + * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT + * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP + * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0 + * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2 + * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT + * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*) + * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT + * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + * @note (*) Availability depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT + * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX1_SYNC_EXTI0 + * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT + * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP + * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT + * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP + * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP + * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT + * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP + * @arg @ref LL_DMAMUX2_SYNC_EXTI0 + * @arg @ref LL_DMAMUX2_SYNC_EXTI2 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 12. + * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 13. + * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 14. + * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 15. + * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 4 Trigger Event Overrun Flag. + * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 5 Trigger Event Overrun Flag. + * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 6 Trigger Event Overrun Flag. + * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 7 Trigger Event Overrun Flag. + * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 12. + * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 13. + * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 14. + * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 15. + * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15); +} + +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @brief Clear Request Generator 4 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4); +} + +/** + * @brief Clear Request Generator 5 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5); +} + +/** + * @brief Clear Request Generator 6 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6); +} + +/** + * @brief Clear Request Generator 7 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 + * @arg @ref LL_DMAMUX_CHANNEL_6 + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @arg @ref LL_DMAMUX_CHANNEL_12 + * @arg @ref LL_DMAMUX_CHANNEL_13 + * @arg @ref LL_DMAMUX_CHANNEL_14 + * @arg @ref LL_DMAMUX_CHANNEL_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE)); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @arg @ref LL_DMAMUX_REQ_GEN_4 + * @arg @ref LL_DMAMUX_REQ_GEN_5 + * @arg @ref LL_DMAMUX_REQ_GEN_6 + * @arg @ref LL_DMAMUX_REQ_GEN_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; + + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 || DMAMUX2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_DMAMUX_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h new file mode 100644 index 0000000..885f22d --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_exti.h @@ -0,0 +1,3285 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_LL_EXTI_H +#define __STM32H7xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + uint32_t Line_64_95; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */ +#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */ +#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */ +#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */ +#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */ +#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */ +#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */ +#if defined(USB2_OTG_FS) +#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */ +#endif /* USB2_OTG_FS */ +#if defined(DSI) +#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */ +#endif /* DSI */ +#define LL_EXTI_LINE_47 EXTI_IMR2_IM47 /*!< Extended line 47 */ +#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */ +#define LL_EXTI_LINE_49 EXTI_IMR2_IM49 /*!< Extended line 49 */ +#define LL_EXTI_LINE_50 EXTI_IMR2_IM50 /*!< Extended line 50 */ +#define LL_EXTI_LINE_51 EXTI_IMR2_IM51 /*!< Extended line 51 */ +#define LL_EXTI_LINE_52 EXTI_IMR2_IM52 /*!< Extended line 52 */ +#define LL_EXTI_LINE_53 EXTI_IMR2_IM53 /*!< Extended line 53 */ +#define LL_EXTI_LINE_54 EXTI_IMR2_IM54 /*!< Extended line 54 */ +#define LL_EXTI_LINE_55 EXTI_IMR2_IM55 /*!< Extended line 55 */ +#define LL_EXTI_LINE_56 EXTI_IMR2_IM56 /*!< Extended line 56 */ +#if defined(EXTI_IMR2_IM57) +#define LL_EXTI_LINE_57 EXTI_IMR2_IM57 /*!< Extended line 57 */ +#endif /*EXTI_IMR2_IM57*/ +#define LL_EXTI_LINE_58 EXTI_IMR2_IM58 /*!< Extended line 58 */ +#if defined(EXTI_IMR2_IM59) +#define LL_EXTI_LINE_59 EXTI_IMR2_IM59 /*!< Extended line 59 */ +#endif /*EXTI_IMR2_IM59*/ +#define LL_EXTI_LINE_60 EXTI_IMR2_IM60 /*!< Extended line 60 */ +#define LL_EXTI_LINE_61 EXTI_IMR2_IM61 /*!< Extended line 61 */ +#define LL_EXTI_LINE_62 EXTI_IMR2_IM62 /*!< Extended line 62 */ +#define LL_EXTI_LINE_63 EXTI_IMR2_IM63 /*!< Extended line 63 */ +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ + +#define LL_EXTI_LINE_64 EXTI_IMR3_IM64 /*!< Extended line 64 */ +#define LL_EXTI_LINE_65 EXTI_IMR3_IM65 /*!< Extended line 65 */ +#define LL_EXTI_LINE_66 EXTI_IMR3_IM66 /*!< Extended line 66 */ +#define LL_EXTI_LINE_67 EXTI_IMR3_IM67 /*!< Extended line 67 */ +#define LL_EXTI_LINE_68 EXTI_IMR3_IM68 /*!< Extended line 68 */ +#define LL_EXTI_LINE_69 EXTI_IMR3_IM69 /*!< Extended line 69 */ +#define LL_EXTI_LINE_70 EXTI_IMR3_IM70 /*!< Extended line 70 */ +#define LL_EXTI_LINE_71 EXTI_IMR3_IM71 /*!< Extended line 71 */ +#define LL_EXTI_LINE_72 EXTI_IMR3_IM72 /*!< Extended line 72 */ +#define LL_EXTI_LINE_73 EXTI_IMR3_IM73 /*!< Extended line 73 */ +#define LL_EXTI_LINE_74 EXTI_IMR3_IM74 /*!< Extended line 74 */ +#if defined(ADC3) +#define LL_EXTI_LINE_75 EXTI_IMR3_IM75 /*!< Extended line 75 */ +#endif /* ADC3 */ +#if defined(SAI4) +#define LL_EXTI_LINE_76 EXTI_IMR3_IM76 /*!< Extended line 76 */ +#endif /* SAI4 */ +#if defined(DUAL_CORE) +#define LL_EXTI_LINE_77 EXTI_IMR3_IM77 /*!< Extended line 77 */ +#define LL_EXTI_LINE_78 EXTI_IMR3_IM78 /*!< Extended line 78 */ +#define LL_EXTI_LINE_79 EXTI_IMR3_IM79 /*!< Extended line 79 */ +#define LL_EXTI_LINE_80 EXTI_IMR3_IM80 /*!< Extended line 80 */ +#define LL_EXTI_LINE_82 EXTI_IMR3_IM82 /*!< Extended line 82 */ +#define LL_EXTI_LINE_84 EXTI_IMR3_IM84 /*!< Extended line 84 */ +#endif /* DUAL_CORE */ +#define LL_EXTI_LINE_85 EXTI_IMR3_IM85 /*!< Extended line 85 */ +#if defined(ETH) +#define LL_EXTI_LINE_86 EXTI_IMR3_IM86 /*!< Extended line 86 */ +#endif /* ETH */ +#define LL_EXTI_LINE_87 EXTI_IMR3_IM87 /*!< Extended line 87 */ +#if defined(DTS) +#define LL_EXTI_LINE_88 EXTI_IMR3_IM88 /*!< Extended line 88 */ +#endif /* DTS */ +#if defined(EXTI_IMR3_IM89) +#define LL_EXTI_LINE_89 EXTI_IMR3_IM89 /*!< Extended line 89 */ +#endif /* EXTI_IMR3_IM89 */ +#if defined(EXTI_IMR3_IM90) +#define LL_EXTI_LINE_90 EXTI_IMR3_IM90 /*!< Extended line 90 */ +#endif /* EXTI_IMR3_IM90 */ +#if defined(I2C5) +#define LL_EXTI_LINE_91 EXTI_IMR3_IM91 /*!< Extended line 91 */ +#endif /* I2C5 */ +#define LL_EXTI_LINE_ALL_64_95 EXTI_IMR3_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x01U) /*!< Cortex-M7 Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x02U) /*!< Cortex-M7 Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U) /*!< Cortex-M7 Interrupt & Event Mode */ + +#if defined(DUAL_CORE) +#define LL_EXTI_MODE_C1_IT LL_EXTI_MODE_IT /*!< Cortex-M7 Interrupt Mode */ +#define LL_EXTI_MODE_C1_EVENT LL_EXTI_MODE_EVENT /*!< Cortex-M7 Event Mode */ +#define LL_EXTI_MODE_C1_IT_EVENT LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */ + +#define LL_EXTI_MODE_C2_IT ((uint8_t)0x10U) /*!< Cortex-M4 Interrupt Mode */ +#define LL_EXTI_MODE_C2_EVENT ((uint8_t)0x20U) /*!< Cortex-M4 Event Mode */ +#define LL_EXTI_MODE_C2_IT_EVENT ((uint8_t)0x30U) /*!< Cortex-M4 Interrupt & Event Mode */ +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source + * @{ + */ +#define LL_EXTI_D3_PEND_CLR_DMACH6 ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */ +#define LL_EXTI_D3_PEND_CLR_DMACH7 ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */ +#if defined (LPTIM4) +#define LL_EXTI_D3_PEND_CLR_LPTIM4 ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */ +#else +#define LL_EXTI_D3_PEND_CLR_LPTIM2 ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */ +#endif /*LPTIM4*/ +#if defined (LPTIM5) +#define LL_EXTI_D3_PEND_CLR_LPTIM5 ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */ +#else +#define LL_EXTI_D3_PEND_CLR_LPTIM3 ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */ +#endif /*LPTIM5*/ +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) + +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @rmtoll IMR3 IMx LL_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR1, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR2, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_EnableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2IMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR1, ExtiLine); +} + + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR2, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_DisableIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2IMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95 + * @rmtoll C2IMR3 IMx LL_C2_EXTI_IsEnabledIT_64_95 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#endif /* DUAL_CORE */ + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR3, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 (*) + * @arg @ref LL_EXTI_LINE_46 (*) + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 (*) + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 (*) + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * + * (*) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 + * @rmtoll EMR3 EMx LL_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 (*) + * @arg @ref LL_EXTI_LINE_76 (*) + * @arg @ref LL_EXTI_LINE_77 (**) + * @arg @ref LL_EXTI_LINE_78 (**) + * @arg @ref LL_EXTI_LINE_79 (**) + * @arg @ref LL_EXTI_LINE_80 (**) + * @arg @ref LL_EXTI_LINE_82 (**) + * @arg @ref LL_EXTI_LINE_84 (**) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (*) + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_88 (*) + * @arg @ref LL_EXTI_LINE_89 (*) + * @arg @ref LL_EXTI_LINE_90 (*) + * @arg @ref LL_EXTI_LINE_91 (*) + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * + * (*) value not defined in all devices. + * (**) value only defined in dual core devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +#if defined(DUAL_CORE) + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR1, ExtiLine); +} + + +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_EnableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->C2EMR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR1, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR2, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_DisableEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->C2EMR3, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2 + * @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2 + * @rmtoll C2EMR2 EMx LL_C2_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_37 + * @arg @ref LL_EXTI_LINE_38 + * @arg @ref LL_EXTI_LINE_39 + * @arg @ref LL_EXTI_LINE_40 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_42 + * @arg @ref LL_EXTI_LINE_43 + * @arg @ref LL_EXTI_LINE_44 + * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_47 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @arg @ref LL_EXTI_LINE_54 + * @arg @ref LL_EXTI_LINE_55 + * @arg @ref LL_EXTI_LINE_56 + * @arg @ref LL_EXTI_LINE_57 + * @arg @ref LL_EXTI_LINE_58 + * @arg @ref LL_EXTI_LINE_59 + * @arg @ref LL_EXTI_LINE_60 + * @arg @ref LL_EXTI_LINE_61 + * @arg @ref LL_EXTI_LINE_62 + * @arg @ref LL_EXTI_LINE_63 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2 + * @rmtoll C2EMR3 EMx LL_C2_EXTI_IsEnabledEvent_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_64 + * @arg @ref LL_EXTI_LINE_65 + * @arg @ref LL_EXTI_LINE_66 + * @arg @ref LL_EXTI_LINE_67 + * @arg @ref LL_EXTI_LINE_68 + * @arg @ref LL_EXTI_LINE_69 + * @arg @ref LL_EXTI_LINE_70 + * @arg @ref LL_EXTI_LINE_71 + * @arg @ref LL_EXTI_LINE_72 + * @arg @ref LL_EXTI_LINE_73 + * @arg @ref LL_EXTI_LINE_74 + * @arg @ref LL_EXTI_LINE_75 + * @arg @ref LL_EXTI_LINE_76 + * @arg @ref LL_EXTI_LINE_77 + * @arg @ref LL_EXTI_LINE_78 + * @arg @ref LL_EXTI_LINE_79 + * @arg @ref LL_EXTI_LINE_80 + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_87 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set.Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_EnableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR3, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR3 RTx LL_EXTI_DisableRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR3, ExtiLine); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll RTSR3 RTx LL_EXTI_IsEnabledRisingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR3 FTx LL_EXTI_EnableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR3, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR3 FTx LL_EXTI_DisableFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR3, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 64 to 95 + * @rmtoll FTSR3 FTx LL_EXTI_IsEnabledFallingTrig_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR1 + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR2 + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} + +/** + * @brief Generate a software Interrupt Event for Lines in range 64 to 95 + * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2 + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR3 + * register (by writing a 1 into the bit) + * @rmtoll SWIER3 SWIx LL_EXTI_GenerateSWI_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER3, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_IsActiveFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_ReadFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine)); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 64 to 95 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR3 PIFx LL_EXTI_ClearFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 (*) + * @arg @ref LL_EXTI_LINE_84 (*) + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 (**) + * + * (*) value only defined in dual core devices. + * (**) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR3, ExtiLine); +} + +#if defined(DUAL_CORE) + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_IsActiveFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_IsActiveFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @arg @ref LL_EXTI_LINE_ALL_64_95 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_ReadFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_ReadFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine)); +} +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR1 PIFx LL_C2_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR1, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 32 to 63 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR2 PIFx LL_C2_EXTI_ClearFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_51 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR2, ExtiLine); +} + +/** + * @brief Clear ExtLine Flags for Lines in range 64 to 95 for cpu2 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll C2PR3 PIFx LL_C2_EXTI_ClearFlag_64_95 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_82 + * @arg @ref LL_EXTI_LINE_84 + * @arg @ref LL_EXTI_LINE_85 + * @arg @ref LL_EXTI_LINE_86 + * @retval None + */ +__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->C2PR3, ExtiLine); +} + +#endif /* DUAL_CORE */ + +/** + * @brief Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_EnablePendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->D3PMR1, ExtiLine); +} + +/** + * @brief Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_EnablePendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->D3PMR2, ExtiLine); +} + +/** + * @brief Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_DisablePendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->D3PMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_DisablePendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->D3PMR2, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31 + * @rmtoll D3PMR1 MRx LL_D3_EXTI_IsEnabledPendMask_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63 + * @rmtoll D3PMR2 MRx LL_D3_EXTI_IsEnabledPendMask_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15 + * @rmtoll D3PCR1L PCSx LL_D3_EXTI_SetPendClearSel_0_15 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc)); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31 + * @rmtoll D3PCR1H PCSx LL_D3_EXTI_SetPendClearSel_16_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc)); +} + + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47 + * @rmtoll D3PCR2L PCSx LL_D3_EXTI_SetPendClearSel_32_47 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc)); +} + +/** + * @brief Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63 + * @rmtoll D3PCR2H PCSx LL_D3_EXTI_SetPendClearSel_48_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @param ClrSrc This parameter can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc) +{ + MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15 + * @rmtoll D3PCR1L PCSx LL_D3_EXTI_GetPendClearSel_0_15 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31 + * @rmtoll D3PCR1H PCSx LL_D3_EXTI_GetPendClearSel_16_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_25 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos))); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47 + * @rmtoll D3PCR2L PCSx LL_D3_EXTI_GetPendClearSel_32_47 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_41 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine)); +} + +/** + * @brief Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63 + * @rmtoll D3PCR2H PCSx LL_D3_EXTI_GetPendClearSel_48_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_48 + * @arg @ref LL_EXTI_LINE_49 + * @arg @ref LL_EXTI_LINE_50 + * @arg @ref LL_EXTI_LINE_51 + * @arg @ref LL_EXTI_LINE_52 + * @arg @ref LL_EXTI_LINE_53 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6 + * @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7 + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM2 (*) + * @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM3 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos))); +} + + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{, + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_EXTI_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h new file mode 100644 index 0000000..5e8a401 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmc.h @@ -0,0 +1,1162 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_fmc.h + * @author MCD Application Team + * @brief Header file of FMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_FMC_H +#define STM32H7xx_LL_FMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FMC_LL + * @{ + */ + +/** @addtogroup FMC_LL_Private_Macros + * @{ + */ + +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) + + +#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) +#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) +#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) +#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FMC_NAND_ECC_ENABLE)) + +#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) + + +#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) +#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) +#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ + ((__BANK__) == FMC_SDRAM_BANK2)) +#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) +#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) +#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) +#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) + + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types + * @{ + */ + +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef + +#define FMC_NORSRAM_DEVICE FMC_Bank1_R +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R +#define FMC_NAND_DEVICE FMC_Bank3_R +#define FMC_SDRAM_DEVICE FMC_Bank5_6_R + +/** + * @brief FMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Write_FIFO */ + + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FMC_Page_Size */ +} FMC_NORSRAM_InitTypeDef; + +/** + * @brief FMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; + +/** + * @brief FMC NAND Configuration Structure definition + */ +typedef struct +{ + uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. + This parameter can be a value of @ref FMC_NAND_Bank */ + + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FMC_NAND_Data_Width */ + + uint32_t EccComputation; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FMC_ECC */ + + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FMC_ECC_Page_Size */ + + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +} FMC_NAND_InitTypeDef; + +/** + * @brief FMC NAND Timing parameters structure definition + */ +typedef struct +{ + uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ + + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + data bus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FMC_NAND_PCC_TimingTypeDef; + + +/** + * @brief FMC SDRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. + This parameter can be a value of @ref FMC_SDRAM_Bank */ + + uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ + + uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ + + uint32_t MemoryDataWidth; /*!< Defines the memory device width. + This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ + + uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. + This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ + + uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. + This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ + + uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. + This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ + + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow + to disable the clock before changing frequency. + This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ + + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read + commands during the CAS latency and stores data in the Read FIFO. + This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ + + uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. + This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ +} FMC_SDRAM_InitTypeDef; + +/** + * @brief FMC SDRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write + command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ +} FMC_SDRAM_TimingTypeDef; + +/** + * @brief SDRAM command parameters structure definition + */ +typedef struct +{ + uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. + This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ + + uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. + This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ + + uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. + This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ + + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ +} FMC_SDRAM_CommandTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants + * @{ + */ + +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank + * @{ + */ +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing + * @{ + */ +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type FMC Memory Type + * @{ + */ +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width + * @{ + */ +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access + * @{ + */ +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode + * @{ + */ +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity + * @{ + */ +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing FMC Wait Timing + * @{ + */ +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation FMC Write Operation + * @{ + */ +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal FMC Wait Signal + * @{ + */ +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode FMC Extended Mode + * @{ + */ +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait + * @{ + */ +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) +/** + * @} + */ + +/** @defgroup FMC_Page_Size FMC Page Size + * @{ + */ +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ + | FMC_BCRx_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 +/** + * @} + */ + +/** @defgroup FMC_Write_Burst FMC Write Burst + * @{ + */ +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock FMC Continuous Clock + * @{ + */ +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) +/** + * @} + */ + +#if defined(FMC_BCR1_WFDIS) +/** @defgroup FMC_Write_FIFO FMC Write FIFO + * @{ + */ +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ +/** + * @} + */ + +/** @defgroup FMC_Access_Mode FMC Access Mode + * @{ + */ +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller + * @{ + */ +/** @defgroup FMC_NAND_Bank FMC NAND Bank + * @{ + */ +#define FMC_NAND_BANK3 (0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_feature FMC Wait feature + * @{ + */ +#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type + * @{ + */ +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width + * @{ + */ +#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) +/** + * @} + */ + +/** @defgroup FMC_ECC FMC ECC + * @{ + */ +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size + * @{ + */ +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller + * @{ + */ +/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank + * @{ + */ +#define FMC_SDRAM_BANK1 (0x00000000U) +#define FMC_SDRAM_BANK2 (0x00000001U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number + * @{ + */ +#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number + * @{ + */ +#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width + * @{ + */ +#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number + * @{ + */ +#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency + * @{ + */ +#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection + * @{ + */ +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period + * @{ + */ +#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst + * @{ + */ +#define FMC_SDRAM_RBURST_DISABLE (0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE (0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay + * @{ + */ +#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode + * @{ + */ +#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) +#define FMC_SDRAM_CMD_PALL (0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target + * @{ + */ +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status + * @{ + */ +#define FMC_SDRAM_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 +#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition + * @{ + */ +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) +#define FMC_IT_REFRESH_ERROR (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition + * @{ + */ +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) +#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE +#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY +#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros + * @{ + */ +/** + * @brief Enable the FMC Peripheral. + * @retval None + */ +#define __FMC_ENABLE() (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN) + +/** + * @brief Disable the FMC Peripheral. + * @retval None + */ +#define __FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN) +/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCRx_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCRx_MBKEN) + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros + * @brief macros to handle NAND device enable/disable + * @{ + */ + +/** + * @brief Enable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @retval None + */ +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) + +/** + * @brief Disable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @retval None + */ +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) + +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt + * @brief macros to handle NAND interrupts + * @{ + */ + +/** + * @brief Enable the NAND device interrupt. + * @param __INSTANCE__ FMC_NAND instance + * @param __INTERRUPT__ FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) + +/** + * @brief Disable the NAND device interrupt. + * @param __INSTANCE__ FMC_NAND Instance + * @param __INTERRUPT__ FMC_NAND interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FMC_IT_LEVEL: Interrupt level. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @retval None + */ +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the NAND device. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the NAND device. + * @param __INSTANCE__ FMC_NAND Instance + * @param __FLAG__ FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval None + */ +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) + +/** + * @} + */ + + +/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt + * @brief macros to handle SDRAM interrupts + * @{ + */ + +/** + * @brief Enable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) + +/** + * @brief Disable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. + * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR + * @retval None + */ +#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM NOR SRAM + * @{ + */ +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ + +/** @defgroup FMC_LL_NAND NAND + * @{ + */ +/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions + * @{ + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); +/** + * @} + */ +/** + * @} + */ + + +/** @defgroup FMC_LL_SDRAM SDRAM + * @{ + */ +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions + * @{ + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber); +uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_FMC_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h new file mode 100644 index 0000000..b51f9d3 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h @@ -0,0 +1,984 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_GPIO_H +#define STM32H7xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask << 16U); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_GPIO_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h new file mode 100644 index 0000000..cff88b5 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h @@ -0,0 +1,902 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_HSEM_H +#define STM32H7xx_LL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(HSEM) + +/** @defgroup HSEM_LL HSEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants + * @{ + */ + +/** @defgroup HSEM_LL_EC_COREID COREID Defines + * @{ + */ +#define LL_HSEM_COREID_NONE 0U +#define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1 +#if defined(DUAL_CORE) +#define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2 +#endif /* DUAL_CORE */ +#define LL_HSEM_COREID HSEM_CR_COREID_CURRENT +/** + * @} + */ + + +/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_HSEM_ReadReg function + * @{ + */ + +#define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0 +#define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1 +#define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2 +#define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3 +#define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4 +#define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5 +#define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6 +#define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7 +#define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8 +#define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9 +#define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10 +#define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11 +#define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12 +#define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13 +#define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14 +#define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15 +#if (HSEM_SEMID_MAX == 15) +#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU +#else /* HSEM_SEMID_MAX == 31 */ +#define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16 +#define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17 +#define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18 +#define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19 +#define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20 +#define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21 +#define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22 +#define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23 +#define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24 +#define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25 +#define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26 +#define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27 +#define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28 +#define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29 +#define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30 +#define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31 +#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +#endif /* HSEM_SEMID_MAX == 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_LL_EF_Data_Management Data_Management + * @{ + */ + + +/** + * @brief Return 1 if the semaphore is locked, else return 0. + * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Get core id. + * @rmtoll R COREID LL_HSEM_GetCoreId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HSEM_COREID_NONE + * @arg @ref LL_HSEM_COREID_CPU1 + * @arg @ref LL_HSEM_COREID_CPU2 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); +} + +/** + * @brief Get process id. + * @rmtoll R PROCID LL_HSEM_GetProcessId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Process number. Value between Min_Data=0 and Max_Data=255 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); +} + +/** + * @brief Get the lock by writing in R register. + * @note The R register has to be read to determined if the lock is taken. + * @rmtoll R LOCK LL_HSEM_SetLock + * @rmtoll R COREID LL_HSEM_SetLock + * @rmtoll R PROCID LL_HSEM_SetLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); +} + +/** + * @brief Get the lock with 2-step lock. + * @rmtoll R LOCK LL_HSEM_2StepLock + * @rmtoll R COREID LL_HSEM_2StepLock + * @rmtoll R PROCID LL_HSEM_2StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @retval 1 lock fail, 0 lock successful or already locked by same process and core + */ +__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process)); + return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL); +} + +/** + * @brief Get the lock with 1-step lock. + * @rmtoll RLR LOCK LL_HSEM_1StepLock + * @rmtoll RLR COREID LL_HSEM_1StepLock + * @rmtoll RLR PROCID LL_HSEM_1StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval 1 lock fail, 0 lock successful or already locked by same core + */ +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); +} + +/** + * @brief Release the lock of the semaphore. + * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0. + * @rmtoll R LOCK LL_HSEM_ReleaseLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process number. Value between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process) +{ + WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process)); +} + +/** + * @brief Get the lock status of the semaphore. + * @rmtoll R LOCK LL_HSEM_GetStatus + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval 0 semaphore is free, 1 semaphore is locked */ +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); +} + +/** + * @brief Set the key. + * @rmtoll KEYR KEY LL_HSEM_SetKey + * @param HSEMx HSEM Instance. + * @param key Key value. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) +{ + WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Get the key. + * @rmtoll KEYR KEY LL_HSEM_GetKey + * @param HSEMx HSEM Instance. + * @retval key to unlock all semaphore from the same core + */ +__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) +{ + return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Release all semaphore with the same core id. + * @rmtoll CR KEY LL_HSEM_ResetAllLock + * @rmtoll CR SEC LL_HSEM_ResetAllLock + * @rmtoll CR PRIV LL_HSEM_ResetAllLock + * @param HSEMx HSEM Instance. + * @param key Key value. + * @param core This parameter can be one of the following values: + * @arg @ref LL_HSEM_COREID_CPU1 + * @arg @ref LL_HSEM_COREID_CPU2 + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core) +{ + WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core); +} + +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable interrupt. + * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + SET_BIT(HSEMx->C1IER, SemaphoreMask); +} + +/** + * @brief Disable interrupt. + * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + CLEAR_BIT(HSEMx->C1IER, SemaphoreMask); +} + +/** + * @brief Check if interrupt is enabled. + * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable interrupt. + * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + SET_BIT(HSEMx->C2IER, SemaphoreMask); +} + +/** + * @brief Disable interrupt. + * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + CLEAR_BIT(HSEMx->C2IER, SemaphoreMask); +} + +/** + * @brief Check if interrupt is enabled. + * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Clear interrupt status. + * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + WRITE_REG(HSEMx->C1ICR, SemaphoreMask); +} + +/** + * @brief Get interrupt status from ISR register. + * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +/** + * @brief Get interrupt status from MISR register. + * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Clear interrupt status. + * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + WRITE_REG(HSEMx->C2ICR, SemaphoreMask); +} + +/** + * @brief Get interrupt status from ISR register. + * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} + +/** + * @brief Get interrupt status from MISR register. + * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ + return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(HSEM) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_HSEM_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h new file mode 100644 index 0000000..d34acc2 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_iwdg.h @@ -0,0 +1,338 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_iwdg.h + * @author MCD Application Team + * @brief Header file of IWDG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_IWDG_H +#define STM32H7xx_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(IWDG1) || defined(IWDG2) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_IWDG_ReadReg function + * @{ + */ +#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ +#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ +#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */ +/** + * @} + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions + * @{ + */ +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note Except if the hardware watchdog option is selected + * @rmtoll KR KEY LL_IWDG_Enable + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * @rmtoll KR KEY LL_IWDG_ReloadCounter + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_EnableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_DisableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_SetPrescaler + * @param IWDGx IWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) +{ + WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_GetPrescaler + * @param IWDGx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_SetReloadCounter + * @param IWDGx IWDG Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) +{ + WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_GetReloadCounter + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->RLR)); +} + +/** + * @brief Specify high limit of the window value to be compared to the down-counter. + * @rmtoll WINR WIN LL_IWDG_SetWindow + * @param IWDGx IWDG Instance + * @param Window Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) +{ + WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); +} + +/** + * @brief Get the high limit of the window value specified. + * @rmtoll WINR WIN LL_IWDG_GetWindow + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->WINR)); +} + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not + * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Reload Value Update is set or not + * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Window Value Update is set or not + * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not + * @rmtoll SR PVU LL_IWDG_IsReady\n + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady + * @param IWDGx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG1 || IWDG2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_IWDG_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h new file mode 100644 index 0000000..fe66bec --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h @@ -0,0 +1,2643 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_lpuart.h + * @author MCD Application Team + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_LPUART_H +#define STM32H7xx_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256 +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in Baud Rate related macros and corresponding register setting computation */ +#define LPUART_LPUARTDIV_FREQ_MUL 256U +#define LPUART_BRR_MASK 0x000FFFFFU +#define LPUART_BRR_MIN_VALUE 0x00000300U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LL LPUART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ + +} LL_LPUART_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_LPUART_WriteReg function + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPUART_ReadReg function + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to Peripheral Clock and + * expected Baud Rate (20-bit value of LPUARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud Rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART Enable + * @rmtoll CR1 UE LL_LPUART_Enable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART Disable + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + * @rmtoll CR1 UE LL_LPUART_Disable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled + * @rmtoll CR1 UE LL_LPUART_IsEnabled + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief LPUART enabled in STOP Mode + * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in STOP Mode + * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in STOP Mode + * (able to wake up MCU from Stop mode or not) + * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + * CR1 TE LL_LPUART_SetTransferDirection + * @param LPUARTx LPUART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + * CR1 TE LL_LPUART_GetTransferDirection + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled) + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_LPUART_SetParity\n + * CR1 PCE LL_LPUART_SetParity + * @param LPUARTx LPUART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_LPUART_GetParity\n + * CR1 PCE LL_LPUART_GetParity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param LPUARTx LPUART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_SetDataWidth + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_GetDataWidth + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + * @param LPUARTx LPUART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + * CR1 PCE LL_LPUART_ConfigCharacter\n + * CR1 M LL_LPUART_ConfigCharacter\n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + * @param LPUARTx LPUART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param LPUARTx LPUART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set Address of the LPUART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param LPUARTx LPUART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the LPUART node. + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + * @param LPUARTx LPUART Instance + * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_SetWKUPType + * @param LPUARTx LPUART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_GetWKUPType + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure LPUART BRR register for achieving expected Baud Rate value. + * + * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock and expected Baud Rate values + * @note Peripheral clock and Baud Rate values provided as function parameters should be valid + * (Baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * a care should be taken when generating high baud rates using high PeriphClk + * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. + * @rmtoll BRR BRR LL_LPUART_SetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) +{ + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } +} + +/** + * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_LPUART_GetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + + lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; + + if (lpuartdiv >= LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : c + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_EnableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_DisableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the LPUART Parity Error Flag is set or not + * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Framing Error Flag is set or not + * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt Flag is set or not + * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Flag is set or not + * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Busy Flag is set or not + * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Flag is set or not + * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from stop mode Flag is set or not + * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Interrupt is enabled or disabled. + * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer + * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr + * @param LPUARTx LPUART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData8 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) +{ + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData9 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) +{ + return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData8 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData9 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) +{ + LPUARTx->TDR = Value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_LPUART_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h new file mode 100644 index 0000000..be137a4 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_pwr.h @@ -0,0 +1,2301 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_PWR_H +#define STM32H7xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_LL_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +/* Wake-Up Pins PWR register offsets */ +#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL +#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU +/** + * @} + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */ +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */ +#endif /* DUAL_CORE */ +#define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */ +#if defined (PWR_WKUPCR_WKUPC5) +#define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */ +#endif /* defined (PWR_WKUPCR_WKUPC5) */ +#define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */ +#if defined (PWR_WKUPCR_WKUPC3) +#define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */ +#endif /* defined (PWR_WKUPCR_WKUPC3) */ +#define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */ +#define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */ +#define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */ +#define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */ +#define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */ +#if defined (PWR_CSR1_MMCVDO) +#define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */ +#endif /* PWR_CSR1_MMCVDO */ + +#define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */ +#define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */ +#define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */ +#define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */ +#define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */ + +#define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */ +#define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */ + +#if defined (PWR_CPUCR_SBF_D2) +#define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ +#endif /* PWR_CPUCR_SBF_D2 */ +#if defined (PWR_CPUCR_SBF_D1) +#define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ +#endif /* PWR_CPUCR_SBF_D1 */ +#define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */ +#define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */ +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */ +#endif /* DUAL_CORE */ + +#if defined (DUAL_CORE) +#define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ +#define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ +#define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */ +#define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */ +#define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */ +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */ +#else +#define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ +#if defined (PWR_WKUPFR_WKUPF5) +#define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ +#endif /* defined (PWR_WKUPFR_WKUPF5) */ +#define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ +#if defined (PWR_WKUPFR_WKUPF3) +#define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ +#endif /* defined (PWR_WKUPFR_WKUPF3) */ +#define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ +#define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Power mode + * @{ + */ +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */ +#else +#define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */ +#define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */ +#else +#define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */ +#define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */ +#define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */ +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +#define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */ +#define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */ +#define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling + * @{ + */ +#if defined (PWR_CPUCR_PDDS_D2) +#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */ +#if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */ +#endif /* defined (SYSCFG_PWRCR_ODEN) */ +#else +#define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */ +#define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ +#endif /* PWR_CPUCR_PDDS_D2 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */ +#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector + * @{ + */ +#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */ +#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ +#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */ +#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */ +#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */ +#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector + * @{ + */ +#define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */ +#define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */ +#define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */ +#define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */ + +/** + * @} + */ + +/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor + * @{ + */ +#define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */ +#define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */ +#if defined (PWR_WKUPEPR_WKUPEN3) +#define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */ +#endif /* defined (PWR_WKUPEPR_WKUPEN3) */ +#define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */ +#if defined (PWR_WKUPEPR_WKUPEN5) +#define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */ +#endif /* defined (PWR_WKUPEPR_WKUPEN5) */ +#define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration + * @{ + */ +#define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */ +#define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */ +#define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration + * @{ + */ +#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ +#if defined (SMPS) +#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */ +#define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ +#define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ +#define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ +#endif /* SMPS */ +#define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + + /** + * @brief Set the voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); +} + +/** + * @brief Get the voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR1 PVDEN LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR1 PVDEN LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR1 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR1 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); +} + +#if defined (PWR_CR1_BOOSTE) +/** + * @brief Enable the Analog Voltage Booster (VDDA) + * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the Analog Voltage Booster (VDDA) + * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_BOOSTE */ + +#if defined (PWR_CR1_AVD_READY) +/** + * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready + * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVD_READY); +} + +/** + * @brief Disable the Analog Voltage Ready (VDDA) + * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY); +} + +/** + * @brief Check if the Analog Voltage Booster (VDDA) is enabled + * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AVD_READY */ + +/** + * @brief Set the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); +} + +/** + * @brief Get the internal Regulator output voltage in STOP mode + * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 + * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 + */ +__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS)); +} + +/** + * @brief Enable Analog Power Voltage Detector + * @rmtoll CR1 AVDEN LL_PWR_EnableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable Analog Power Voltage Detector + * @rmtoll CR1 AVDEN LL_PWR_DisableAVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Check if Analog Power Voltage Detector is enabled + * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll CR1 ALS LL_PWR_SetAVDLevel + * @param AVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); +} + +/** + * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector + * @rmtoll CR1 ALS LL_PWR_GetAVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_AVDLEVEL_0 + * @arg @ref LL_PWR_AVDLEVEL_1 + * @arg @ref LL_PWR_AVDLEVEL_2 + * @arg @ref LL_PWR_AVDLEVEL_3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS)); +} + +#if defined (PWR_CR1_AXIRAM1SO) +/** + * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); +} + +/** + * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); +} + +/** + * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM1SO */ + +#if defined (PWR_CR1_AXIRAM2SO) +/** + * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); +} + +/** + * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); +} + +/** + * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM2SO */ + +#if defined (PWR_CR1_AXIRAM3SO) +/** + * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); +} + +/** + * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); +} + +/** + * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AXIRAM3SO */ + +#if defined (PWR_CR1_AHBRAM1SO) +/** + * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); +} + +/** + * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); +} + +/** + * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AHBRAM1SO */ + +#if defined (PWR_CR1_AHBRAM2SO) +/** + * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); +} + +/** + * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode + * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); +} + +/** + * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_AHBRAM2SO */ + +#if defined (PWR_CR1_ITCMSO) +/** + * @brief Enable the ITCM shut-off in DStop/DStop2 mode + * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ITCMSO); +} + +/** + * @brief Disable the ITCM shut-off in DStop/DStop2 mode + * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO); +} + +/** + * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_ITCMSO */ + +#if defined (PWR_CR1_HSITFSO) +/** + * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode + * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_HSITFSO); +} + +/** + * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode + * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO); +} + +/** + * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_HSITFSO */ + +#if defined (PWR_CR1_SRDRAMSO) +/** + * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode + * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); +} + +/** + * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode + * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); +} + +/** + * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled + * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL); +} +#endif /* PWR_CR1_SRDRAMSO */ + +/** + * @brief Enable Backup Regulator + * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator + * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and + * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup + * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, + * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that + * the data written into the RAM will be maintained in the Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_BREN); +} + +/** + * @brief Disable Backup Regulator + * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_BREN); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL); +} + +/** + * @brief Enable VBAT and Temperature monitoring + * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMonitoring(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Disable VBAT and Temperature monitoring + * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMonitoring(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Check if the VBAT and Temperature monitoring is enabled + * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL); +} + +#if defined (SMPS) +/** + * @brief Configure the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply + * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply + * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); +} +#else +/** + * @brief Configure the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply + * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply + * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply + * @param SupplySource This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) +{ + /* Set the power supply configuration */ + MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); +} +#endif /* defined (SMPS) */ + +#if defined (SMPS) +/** + * @brief Get the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_GetSupply + * @rmtoll CR3 LDOEN LL_PWR_GetSupply + * @rmtoll CR3 SMPSEN LL_PWR_GetSupply + * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply + * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT + * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); +} +#else +/** + * @brief Get the PWR supply + * @rmtoll CR3 BYPASS LL_PWR_GetSupply + * @rmtoll CR3 LDOEN LL_PWR_GetSupply + * @rmtoll CR3 SCUEN LL_PWR_GetSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetSupply(void) +{ + /* Get the power supply configuration */ + return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); +} +#endif /* defined (SMPS) */ + +/** + * @brief Enable battery charging + * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Disable battery charging + * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Check if battery charging is enabled + * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL); +} + +/** + * @brief Set the Battery charge resistor impedance + * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor + * @param Resistor This parameter can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor); +} + +/** + * @brief Get the Battery charge resistor impedance + * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K + * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K + */ +__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) +{ + return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS)); +} + +/** + * @brief Enable the USB regulator + * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBReg(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_USBREGEN); +} + +/** + * @brief Disable the USB regulator + * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBReg(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN); +} + +/** + * @brief Check if the USB regulator is enabled + * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the USB voltage detector + * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Disable the USB voltage detector + * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Check if the USB voltage detector is enabled + * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL); +} + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D1STOP + * @arg @ref LL_PWR_CPU_MODE_D1STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); +} +#else +/** + * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_CDSTOP + * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D1STOP + * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D1STOP + * @arg @ref LL_PWR_CPU_MODE_D1STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); +} +#else +/** + * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_CDSTOP + * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D1STOP + * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1)); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D2STOP + * @arg @ref LL_PWR_CPU_MODE_D2STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D2STOP + * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D2STOP + * @arg @ref LL_PWR_CPU_MODE_D2STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D2STOP + * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2)); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D3STOP + * @arg @ref LL_PWR_CPU_MODE_D3STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); +} +#else +/** + * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_SRDSTOP + * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D3STOP + * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_D3STOP + * @arg @ref LL_PWR_CPU_MODE_D3STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3)); +} +#else +/** + * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep + * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU_MODE_SRDSTOP + * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD)); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep + * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_CPU2_MODE_D3STOP + * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3)); +} +#endif /* DUAL_CORE */ + +#if defined (DUAL_CORE) +/** + * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode + * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_HoldCPU1(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); +} + +/** + * @brief Release the CPU1 and allocated peripherals + * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ReleaseCPU1(void) +{ + CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); +} + +/** + * @brief Ckeck if the CPU1 and allocated peripherals are held + * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL); +} + +/** + * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode + * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_HoldCPU2(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); +} + +/** + * @brief Release the CPU2 and allocated peripherals + * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ReleaseCPU2(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); +} + +/** + * @brief Ckeck if the CPU2 and allocated peripherals are held + * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief D3 domain remains in Run mode regardless of CPU subsystem modes + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); +} +#else +/** + * @brief SRD domain remains in Run mode regardless of CPU subsystem modes + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief D3 domain follows CPU subsystem modes + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); +} +#else +/** + * @brief SRD domain follows CPU subsystem modes + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief D3 domain follows CPU2 subsystem modes + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void) +{ + CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_PDDS_D2) +/** + * @brief Check if D3 is kept in Run mode when CPU enters low power mode + * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL); +} +#else +/** + * @brief Check if SRD is kept in Run mode when CPU enters low power mode + * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_PDDS_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode + * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 + * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1. + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ +#if defined (PWR_CPUCR_PDDS_D2) + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); +#else + MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling + * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking + * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit. + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ +#if defined (PWR_CPUCR_PDDS_D2) + return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS)); +#else + return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS)); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n + * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n + * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n + * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n + * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL); +} + +/** + * @brief Set the Wake-Up pin Pull None + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Up + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Set the Wake-Up pin Pull Down + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n + * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WKUPEPR, \ + (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ + (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); +} + +/** + * @brief Get the Wake-Up pin pull + * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n + * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 (*) + * @arg @ref LL_PWR_WAKEUP_PIN6 + * + * (*) value not defined in all devices. + * + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL + * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP + * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) +{ + uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); + + return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the voltage level is ready for current actual used VOS + * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether VDDA voltage is below the selected AVD threshold + * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); +} + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief Indicate whether VDDMMC voltage is below 1V2 + * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void) +{ + return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL); +} +#endif /* PWR_CSR1_MMCVDO */ + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below low threshold + * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the VBAT level is above or below high threshold + * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below low threshold + * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the CPU temperature level is above or below high threshold + * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL); +} + +#if defined (SMPS) +/** + * @brief Indicate whether the SMPS external supply is ready or not + * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL); +} +#endif /* SMPS */ + +/** + * @brief Indicate whether the USB supply is ready or not + * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get HOLD2 Flag + * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL); +} + +/** + * @brief Get HOLD1 Flag + * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get CPU System Stop Flag + * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 System Stop Flag + * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Get CPU System Standby Flag + * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 System Standby Flag + * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_SBF_D1) +/** + * @brief Get CPU D1 Domain Standby Flag + * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_SBF_D1 */ + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 D1 Domain Standby Flag + * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +#if defined (PWR_CPUCR_SBF_D2) +/** + * @brief Get CPU D2 Domain Standby Flag + * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void) +{ + return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL); +} +#endif /* PWR_CPUCR_SBF_D2 */ + +#if defined (DUAL_CORE) +/** + * @brief Get CPU2 D2 Domain Standby Flag + * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void) +{ + return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range + * or if its output voltage is still changing to the required voltage level + * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ +#if defined (PWR_CPUCR_PDDS_D2) + return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL); +#else + return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL); +#endif /* PWR_CPUCR_PDDS_D2 */ +} + +/** + * @brief Get Wake-up Flag 6 + * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL); +} + +#if defined (PWR_WKUPFR_WKUPF5) +/** + * @brief Get Wake-up Flag 5 + * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL); +} +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); +} + +#if defined (PWR_WKUPFR_WKUPF3) +/** + * @brief Get Wake-up Flag 3 + * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); +} +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); +} + +/** + * @brief Clear CPU STANDBY, STOP and HOLD flags + * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void) +{ + SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); +} + +#if defined (DUAL_CORE) +/** + * @brief Clear CPU2 STANDBY, STOP and HOLD flags + * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void) +{ + SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); +} +#endif /* DUAL_CORE */ + +/** + * @brief Clear Wake-up Flag 6 + * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6); +} + +#if defined (PWR_WKUPCR_WKUPC5) +/** + * @brief Clear Wake-up Flag 5 + * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5); +} +#endif /* defined (PWR_WKUPCR_WKUPC5) */ + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); +} + +#if defined (PWR_WKUPCR_WKUPC3) +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); +} +#endif /* defined (PWR_WKUPCR_WKUPC3) */ + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); +} + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_PWR_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h new file mode 100644 index 0000000..bd700dc --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h @@ -0,0 +1,6404 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_RCC_H +#define STM32H7xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ +extern const uint8_t LL_RCC_PrescTable[16]; + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif + +/* 32 24 16 8 0 + -------------------------------------------------------- + | Mask | ClkSource | Bit | Register | + | | Config | Position | Offset | + --------------------------------------------------------*/ + +#if defined(RCC_VER_2_0) +/* Clock source register offset Vs CDCCIPR register */ +#define CDCCIP 0x0UL +#define CDCCIP1 0x4UL +#define CDCCIP2 0x8UL +#define SRDCCIP 0xCUL +#else +/* Clock source register offset Vs D1CCIPR register */ +#define D1CCIP 0x0UL +#define D2CCIP1 0x4UL +#define D2CCIP2 0x8UL +#define D3CCIP 0xCUL +#endif /* RCC_VER_2_0 */ + +#define LL_RCC_REG_SHIFT 0U +#define LL_RCC_POS_SHIFT 8U +#define LL_RCC_CONFIG_SHIFT 16U +#define LL_RCC_MASK_SHIFT 24U + +#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) + +#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) + +#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) + +#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ + (( __POS__ ) << LL_RCC_POS_SHIFT) | \ + (( __REG__ ) << LL_RCC_REG_SHIFT) | \ + (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t CPUCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK1_Frequency; + uint32_t PCLK2_Frequency; + uint32_t PCLK3_Frequency; + uint32_t PCLK4_Frequency; +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @brief PLL Clocks Frequency Structure + */ +typedef struct +{ + uint32_t PLL_P_Frequency; + uint32_t PLL_Q_Frequency; + uint32_t PLL_R_Frequency; +} LL_PLL_ClocksTypeDef; + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#if defined(RCC_VER_X) || defined(RCC_VER_3_0) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#else +#define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* RCC_VER_X || RCC_VER_3_0 */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */ +#endif /* CSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider + * @{ + */ +#define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1 +#define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2 +#define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4 +#define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U) +#define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0) +#define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1) +#define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI +#define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE +#define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1 +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source + * @{ + */ +#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) +#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source + * @{ + */ +#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U) +#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler + * @{ + */ +#if defined(RCC_D1CFGR_D1CPRE_DIV1) +#define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1 +#define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2 +#define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4 +#define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8 +#define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16 +#define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64 +#define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128 +#define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256 +#define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512 +#else +#define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1 +#define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2 +#define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4 +#define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8 +#define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16 +#define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64 +#define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128 +#define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256 +#define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512 +#endif /* RCC_D1CFGR_D1CPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler + * @{ + */ +#if defined(RCC_D1CFGR_HPRE_DIV1) +#define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1 +#define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2 +#define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4 +#define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8 +#define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16 +#define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64 +#define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128 +#define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256 +#define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512 +#else +#define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1 +#define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2 +#define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4 +#define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8 +#define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16 +#define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64 +#define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128 +#define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256 +#define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512 +#endif /* RCC_D1CFGR_HPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#if defined(RCC_D2CFGR_D2PPRE1_DIV1) +#define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1 +#define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2 +#define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4 +#define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8 +#define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16 +#else +#define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1 +#define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2 +#define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4 +#define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8 +#define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16 +#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2) + * @{ + */ +#if defined(RCC_D2CFGR_D2PPRE2_DIV1) +#define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1 +#define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2 +#define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4 +#define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8 +#define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16 +#else +#define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1 +#define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2 +#define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4 +#define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8 +#define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16 +#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3) + * @{ + */ +#if defined(RCC_D1CFGR_D1PPRE_DIV1) +#define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1 +#define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2 +#define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4 +#define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8 +#define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16 +#else +#define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1 +#define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2 +#define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4 +#define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8 +#define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16 +#endif /* RCC_D1CFGR_D1PPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4) + * @{ + */ +#if defined(RCC_D3CFGR_D3PPRE_DIV1) +#define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1 +#define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2 +#define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4 +#define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8 +#define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16 +#else +#define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1 +#define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2 +#define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4 +#define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8 +#define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16 +#endif /* RCC_D3CFGR_D3PPRE_DIV1 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U) +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0) +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1) +#define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) +#define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2) +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U) +#define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0) +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1) +#define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) +#define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2) +#define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0) +#define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1) +#define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3) +#define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE) +#define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0) +#define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1) +#define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2) +#define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3) +#define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE) + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U) +#define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5) +#define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4) +#define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) +#define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) +#define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) +#define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) +#define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_USART16SEL) +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0) +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1) +#define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1) +#define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2) +#define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2) +/* Aliases */ +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_RCC_USART16_CLKSOURCE_PCLK2 +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_RCC_USART16_CLKSOURCE_PLL2Q +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_RCC_USART16_CLKSOURCE_PLL3Q +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_RCC_USART16_CLKSOURCE_HSI +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_RCC_USART16_CLKSOURCE_CSI +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_RCC_USART16_CLKSOURCE_LSE + +#elif defined(RCC_D2CCIP2R_USART16910SEL) +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0) +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2) +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2) +/* Aliases */ +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q +#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI +#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI +#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE + +#else +#define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) +#define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0) +#define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1) +#define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2) +#define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2) +/* Aliases */ +#define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2 +#define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q +#define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q +#define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI +#define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI +#define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE +#endif /* RCC_D2CCIP2R_USART16SEL */ +#if defined(RCC_D2CCIP2R_USART28SEL) +#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) +#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2) +#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2) +#else +#define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) +#define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0) +#define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1) +#define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2) +#define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2) +#endif /* RCC_D2CCIP2R_USART28SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#if defined(RCC_D3CCIPR_LPUART1SEL) +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2) +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2) +#else +#define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0) +#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1) +#define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2) +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2) +#endif /* RCC_D3CCIPR_LPUART1SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#if defined (RCC_D2CCIP2R_I2C123SEL) +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0) +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1) +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1) +/* Aliases */ +#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_RCC_I2C123_CLKSOURCE_PCLK1 +#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_RCC_I2C123_CLKSOURCE_PLL3R +#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_RCC_I2C123_CLKSOURCE_HSI +#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_RCC_I2C123_CLKSOURCE_CSI + +#elif defined (RCC_D2CCIP2R_I2C1235SEL) +#define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) +#define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0) +#define LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1) +#define LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1) +/* Aliases */ +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1 +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI + +#else +#define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) +#define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0) +#define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1) +#define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1) +#endif /* RCC_D2CCIP2R_I2C123SEL */ +#if defined (RCC_D3CCIPR_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) +#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1) +#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1) +#else +#define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) +#define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0) +#define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1) +#define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1) +#endif /* RCC_D3CCIPR_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2) +#else +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0) +#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1) +#define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2) +#define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2) +#endif /* RCC_D2CCIP2R_LPTIM1SEL */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2) +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2) +#else +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0) +#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1) +#define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2) +#define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2) +#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2) +#else +#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0) +#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1) +#define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2) +#define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2) +/* aliases*/ +#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4 +#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P +#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R +#define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE +#define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI +#define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP +#endif /* RCC_D3CCIPR_LPTIM345SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2) +#else +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) +#define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0) +#define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1) +#define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2) +#endif +#if defined(SAI3) +#define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) +#define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0) +#define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1) +#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1) +#define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2) +#endif /* SAI3 */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) +#define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0) +#define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1) +#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1) +#define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2) +#define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2) +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) +#define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0) +#define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1) +#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1) +#define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2) +#define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2) +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI4_Block_A) +#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) +#define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0) +#define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1) +#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1) +#define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2) +#if defined(RCC_VER_3_0) +#define LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0) +#endif /* RCC_VER_3_0 */ +#endif /* SAI4_Block_A */ +#if defined(SAI4_Block_B) +#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) +#define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0) +#define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1) +#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1) +#define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2) +#if defined(RCC_VER_3_0) +#define LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0) +#endif /* RCC_VER_3_0 */ +#endif /* SAI4_Block_B */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL) +#else +#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL) +#endif /* RCC_D1CCIPR_SDMMCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_RNGSEL) +#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) +#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0) +#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1) +#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0) +#else +#define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U) +#define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0) +#define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1) +#define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0) +#endif /* RCC_D2CCIP2R_RNGSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_USBSEL) +#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) +#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0) +#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1) +#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0) +#else +#define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U) +#define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0) +#define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1) +#define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0) +#endif /* RCC_D2CCIP2R_USBSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#if defined(RCC_D2CCIP2R_CECSEL) +#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) +#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0) +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1) +#else +#define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U) +#define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0) +#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1) +#endif +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY (0x00000000U) +#define LL_RCC_DSI_CLKSOURCE_PLL2Q (RCC_D1CCIPR_DSISEL) +/** + * @} + */ +#endif /* DSI */ + +/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL) +#else +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U) +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL) +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +/** + * @} + */ + +#if defined(DFSDM2_BASE) +/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 clock source selection + * @{ + */ +#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U) +#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL) +/** + * @} + */ +#endif /* DFSDM2_BASE */ + +/** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0) +#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1) +#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1) +#else +#define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0) +#define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1) +#define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1) +#endif /* RCC_D1CCIPR_FMCSEL */ +/** + * @} + */ + +#if defined(QUADSPI) +/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection + * @{ + */ +#define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0) +#define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1) +#define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1) +/** + * @} + */ +#endif /* QUADSPI */ + + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_OCTOSPISEL) +#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0) +#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1) +#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1) +#else +#define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U) +#define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0) +#define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1) +#define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1) +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +/** + * @} + */ +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + + +/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection + * @{ + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) +#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1) +#else +#define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U) +#define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0) +#define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1) +#endif /* RCC_D1CCIPR_CKPERSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) +#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0) +#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2) +#else +#define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) +#define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0) +#define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1) +#define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2) +#endif /* RCC_D2CCIP1R_SPI123SEL */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) +#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2) +#else +#define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) +#define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0) +#define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1) +#define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2) +#define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2) +#endif /* (RCC_D2CCIP1R_SPI45SEL */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2) +#else +#define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) +#define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0) +#define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1) +#define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2) +#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2) +#endif /* RCC_D3CCIPR_SPI6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0) +#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1) +#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1) +#else +#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U) +#define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0) +#define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1) +#define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1) +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +/** + * @} + */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0) +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1) +#else +#define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U) +#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0) +#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1) +#endif /* RCC_D2CCIP1R_FDCANSEL */ +/** + * @} + */ +#endif /*FDCAN1 || FDCAN2*/ + +/** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection + * @{ + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) +#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL) +#else +#define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U) +#define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL) +#endif /* RCC_D2CCIP1R_SWPSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) +#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0) +#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1) +#else +#define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U) +#define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0) +#define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1) +#endif /* RCC_D3CCIPR_ADCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source + * @{ + */ +#if defined (RCC_D2CCIP2R_USART16SEL) +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U) +#elif defined (RCC_D2CCIP2R_USART16910SEL) +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U) +/* alias*/ +#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE +#else +#define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U) +/* alias*/ +#define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE +#endif /* RCC_D2CCIP2R_USART16SEL */ +#if defined (RCC_D2CCIP2R_USART28SEL) +#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U) +#else +#define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP2R_USART28SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source + * @{ + */ +#if defined(RCC_D3CCIPR_LPUART1SEL) +#define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL +#else +#define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL +#endif /* RCC_D3CCIPR_LPUART1SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source + * @{ + */ +#if defined(RCC_D2CCIP2R_I2C123SEL) +#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE +#elif defined(RCC_D2CCIP2R_I2C1235SEL) +#define LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE +#else +#define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U) +/* alias */ +#define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE +#endif /* RCC_D2CCIP2R_I2C123SEL */ +#if defined(RCC_D3CCIPR_I2C4SEL) +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U) +#else +#define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_I2C4SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source + * @{ + */ +#if defined(RCC_D2CCIP2R_LPTIM1SEL) +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP2R_LPTIM1SEL) */ +#if defined(RCC_D3CCIPR_LPTIM2SEL) +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_LPTIM2SEL */ +#if defined(RCC_D3CCIPR_LPTIM345SEL) +#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U) +#else +#define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U) +#define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */ +#endif /* RCC_D3CCIPR_LPTIM345SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SAI1SEL) +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SAI1SEL */ +#if defined(RCC_D2CCIP1R_SAI23SEL) +#define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SAI23SEL */ +#if defined(RCC_CDCCIP1R_SAI2ASEL) +#define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U) +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) +#define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U) +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(RCC_D3CCIPR_SAI4ASEL) +#define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SAI4ASEL */ +#if defined(RCC_D3CCIPR_SAI4BSEL) +#define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SAI4BSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_SDMMCSEL) +#define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL +#else +#define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL +#endif /* RCC_D1CCIPR_SDMMCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#if (RCC_D2CCIP2R_RNGSEL) +#define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL +#else +#define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL +#endif /* RCC_D2CCIP2R_RNGSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#if (RCC_D2CCIP2R_USBSEL) +#define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL +#else +#define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL +#endif /* RCC_D2CCIP2R_USBSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#if (RCC_D2CCIP2R_CECSEL) +#define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL +#else +#define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL +#endif /* RCC_D2CCIP2R_CECSEL */ +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL +/** + * @} + */ +#endif /* DSI */ + +/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) +#define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL +#else +#define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +/** + * @} + */ + +#if defined(DFSDM2_BASE) +/** @defgroup RCC_LL_EC_DFSDM2 Peripheral DFSDM2 get clock source + * @{ + */ +#define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL +/** + * @} + */ +#endif /* DFSDM2_BASE */ + + + +/** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_FMCSEL) +#define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL +#else +#define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL +#endif +/** + * @} + */ + +#if defined(QUADSPI) +/** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source + * @{ + */ +#define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL +/** + * @} + */ +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source + * @{ + */ +#if defined(RCC_CDCCIPR_OCTOSPISEL) +#define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL +#else +#define LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL +#endif /* RCC_CDCCIPR_OCTOSPISEL */ +/** + * @} + */ +#endif /* OCTOSPI1 || OCTOSPI2 */ + +/** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source + * @{ + */ +#if defined(RCC_D1CCIPR_CKPERSEL) +#define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL +#else +#define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL +#endif /* RCC_D1CCIPR_CKPERSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SPI123SEL) +#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SPI123SEL */ +#if defined(RCC_D2CCIP1R_SPI45SEL) +#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U) +#endif /* RCC_D2CCIP1R_SPI45SEL */ +#if defined(RCC_D3CCIPR_SPI6SEL) +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U) +#else +#define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U) +#endif /* RCC_D3CCIPR_SPI6SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SPDIFSEL) +#define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL +#else +#define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +/** + * @} + */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_FDCANSEL) +#define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL +#else +#define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL +#endif +/** + * @} + */ +#endif /*FDCAN1 || FDCAN2*/ + +/** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source + * @{ + */ +#if defined(RCC_D2CCIP1R_SWPSEL) +#define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL +#else +#define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL +#endif /* RCC_D2CCIP1R_SWPSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#if defined(RCC_D3CCIPR_ADCSEL) +#define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL +#else +#define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL +#endif /* RCC_D3CCIPR_ADCSEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U) +#define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0) +#define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1) +#define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U) +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE) +/** + * @} + */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection + * @{ + */ +#define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */ +#define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */ +/** + * @} + */ +#endif /* HRTIM1 */ + +/** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI +#define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE +#define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range + * @{ + */ +#define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U) +#define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001) +#define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002) +#define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003) +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range + * @{ + */ +#define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */ +#define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */ +/** + * (*) : For stm32h7a3xx and stm32h7b3xx family lines. + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the SYSCLK frequency + * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P) + * @param __SYSPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval SYSCLK clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_D1CPRE) +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_D1CPRE */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency. + * @param __HPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_HPRE) +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_HPRE */ + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D2CFGR_D2PPRE1) +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)) +#endif /* RCC_D2CFGR_D2PPRE1 */ + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#if defined(RCC_D2CFGR_D2PPRE2) +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)) +#endif /* RCC_D2CFGR_D2PPRE2 */ + +/** + * @brief Helper macro to calculate the PCLK3 frequency (APB3) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB3PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D1CFGR_D1PPRE) +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU)) +#endif /* RCC_D1CFGR_D1PPRE */ + +/** + * @brief Helper macro to calculate the PCLK4 frequency (ABP4) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB4PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#if defined(RCC_D3CFGR_D3PPRE) +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU)) +#else +#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU)) +#endif /* RCC_D3CFGR_D3PPRE */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless + * a reset occurs or system enter in standby mode. + * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSHSEON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +#if defined(RCC_CR_HSEEXT) +/** + * @brief Select the Analog HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +} + +/** + * @brief Select the Digital HSE external clock type in Bypass mode + * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEEXT); +} +#endif /* RCC_CR_HSEEXT */ + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI new divider applied and ready + * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV1 + * @arg @ref LL_RCC_HSI_DIV2 + * @arg @ref LL_RCC_HSI_DIV4 + * @arg @ref LL_RCC_HSI_DIV8 + * @retval None. + */ +__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider); +} + +/** + * @brief Get HSI divider + * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider + * @retval can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV1 + * @arg @ref LL_RCC_HSI_DIV2 + * @arg @ref LL_RCC_HSI_DIV4 + * @arg @ref LL_RCC_HSI_DIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} + +/** + * @brief Enable HSI oscillator in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI oscillator in Stop mode + * @rmtoll CR HSION LL_RCC_HSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration + * @retval A value between 0 and 4095 (0xFFF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value, + * should trim the HSI to 64 MHz +/- 1 % + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value can be a value between 0 and 127 (63 for Cut1.x) + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U); + } + else + { + /* STM32H7 Rev.V */ + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); + } +#else + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval A value between 0 and 127 (63 for Cut1.x) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_CSI CSI + * @{ + */ + +/** + * @brief Enable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Disable CSI oscillator + * @rmtoll CR CSION LL_RCC_CSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSION); +} + +/** + * @brief Check if CSI clock is ready + * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Disable CSI oscillator in Stop mode + * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON); +} + +/** + * @brief Get CSI Calibration value + * @note When CSITRIM is written, CSICAL is updated with the sum of + * CSITRIM and the factory trim value + * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration + * @retval A value between 0 and 255 (0xFF) + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Set CSI Calibration trimming + * @note user-programmable trimming value that is added to the CSICAL + * @note Default value is 16, which, when added to the CSICAL value, + * should trim the CSI to 4 MHz +/- 1 % + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming + * @param Value can be a value between 0 and 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U); + } + else + { + /* STM32H7 Rev.V */ + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); + } +#else + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @brief Get CSI Calibration trimming + * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming + * @retval A value between 0 and 31 + */ +__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void) +{ +#if defined(RCC_VER_X) + if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U) + { + /* STM32H7 Rev.Y */ + return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U); + } + else + { + /* STM32H7 Rev.V */ + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + } +#else + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +#endif /* RCC_VER_X */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 oscillator + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 clock is ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of + * HSI48TRIM and the factory trim value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval A value between 0 and 1023 (0x3FF) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} +/** + * @} + */ + +#if defined(RCC_CR_D1CKRDY) + +/** @defgroup RCC_LL_EF_D1CLK D1CKREADY + * @{ + */ + +/** + * @brief Check if D1 clock is ready + * @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ +#else + +/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY + * @{ + */ + +/** + * @brief Check if CPU clock is ready + * @rmtoll CR CPUCKRDY LL_RCC_CPUCK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL); +} +/* alias */ +#define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady +/** + * @} + */ +#endif /* RCC_CR_D1CKRDY */ + +#if defined(RCC_CR_D2CKRDY) + +/** @defgroup RCC_LL_EF_D2CLK D2CKREADY + * @{ + */ + +/** + * @brief Check if D2 clock is ready + * @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL); +} +/** + * @} + */ +#else + +/** @defgroup RCC_LL_EF_CDCLK CDCKREADY + * @{ + */ + +/** + * @brief Check if CD clock is ready + * @rmtoll CR CDCKRDY LL_RCC_CDCK_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL); +} +#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady +/** + * @} + */ +#endif /* RCC_CR_D2CKRDY */ + +/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET + * @{ + */ +#if defined(RCC_GCR_WW1RSC) + +/** + * @brief Enable system wide reset for Window Watch Dog 1 + * @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset + * @retval None. + */ +__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_WW1RSC); +} + +/** + * @brief Check if Window Watch Dog 1 reset is system wide + * @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL); +} +#endif /* RCC_GCR_WW1RSC */ + +#if defined(DUAL_CORE) +/** + * @brief Enable system wide reset for Window Watch Dog 2 + * @rmtoll GCR WW1RSC LL_RCC_WWDG2_EnableSystemReset + * @retval None. + */ +__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_WW2RSC); +} + +/** + * @brief Check if Window Watch Dog 2 reset is system wide + * @rmtoll GCR WW2RSC LL_RCC_WWDG2_IsSystemReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup RCC_LL_EF_BOOT_CPU CPU + * @{ + */ + +/** + * @brief Force CM4 boot (if hold by option byte BCM4 = 0) + * @rmtoll GCR BOOT_C2 LL_RCC_ForceCM4Boot + * @retval None. + */ +__STATIC_INLINE void LL_RCC_ForceCM4Boot(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2); +} + +/** + * @brief Check if CM4 boot is forced + * @rmtoll GCR BOOT_C2 LL_RCC_IsCM4BootForced + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL); +} + +/** + * @brief Force CM7 boot (if hold by option byte BCM7 = 0) + * @rmtoll GCR BOOT_C1 LL_RCC_ForceCM7Boot + * @retval None. + */ +__STATIC_INLINE void LL_RCC_ForceCM7Boot(void) +{ + SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1); +} + +/** + * @brief Check if CM7 boot is forced + * @rmtoll GCR BOOT_C1 LL_RCC_IsCM7BootForced + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void) +{ + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /*DUAL_CORE*/ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable the Clock Security System on LSE. + * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless + * a clock failure is detected. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE failure is detected by Clock Security System + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +#if defined(RCC_BDCR_LSEEXT) +/** + * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} + +/** + * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset). + * @note The external clock must be enabled with the LSEON bit, to be used by the device. + * The LSEEXT bit can be written only if the LSE oscillator is disabled. + * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT); +} +#endif /* RCC_BDCR_LSEEXT */ + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Configure the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source); +} + +/** + * @brief Get the system wakeup clock source + * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +} + +/** + * @brief Configure the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source); +} + +/** + * @brief Get the kernel wakeup clock source + * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI + * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK)); +} + +/** + * @brief Set System prescaler + * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_D1CPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler); +#endif /* RCC_D1CFGR_D1CPRE */ +} + +/** + * @brief Set AHB prescaler + * @rmtoll D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_HPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler); +#endif /* RCC_D1CFGR_HPRE */ +} + +/** + * @brief Set APB1 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D2CFGR_D2PPRE1) + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler); +#endif /* RCC_D2CFGR_D2PPRE1 */ +} + +/** + * @brief Set APB2 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D2CFGR_D2PPRE2) + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler); +#endif /* RCC_D2CFGR_D2PPRE2 */ +} + +/** + * @brief Set APB3 prescaler + * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D1CFGR_D1PPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler); +#endif /* RCC_D1CFGR_D1PPRE */ +} + +/** + * @brief Set APB4 prescaler + * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler) +{ +#if defined(RCC_D3CFGR_D3PPRE) + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler); +#else + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler); +#endif /* RCC_D3CFGR_D3PPRE */ +} + +/** + * @brief Get System prescaler + * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void) +{ +#if defined(RCC_D1CFGR_D1CPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE)); +#endif /* RCC_D1CFGR_D1CPRE */ +} + +/** + * @brief Get AHB prescaler + * @rmtoll D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_AHB_DIV_1 + * @arg @ref LL_RCC_AHB_DIV_2 + * @arg @ref LL_RCC_AHB_DIV_4 + * @arg @ref LL_RCC_AHB_DIV_8 + * @arg @ref LL_RCC_AHB_DIV_16 + * @arg @ref LL_RCC_AHB_DIV_64 + * @arg @ref LL_RCC_AHB_DIV_128 + * @arg @ref LL_RCC_AHB_DIV_256 + * @arg @ref LL_RCC_AHB_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ +#if defined(RCC_D1CFGR_HPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE)); +#endif /* RCC_D1CFGR_HPRE */ +} + +/** + * @brief Get APB1 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ +#if defined(RCC_D2CFGR_D2PPRE1) + return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1)); +#endif /* RCC_D2CFGR_D2PPRE1 */ +} + +/** + * @brief Get APB2 prescaler + * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ +#if defined(RCC_D2CFGR_D2PPRE2) + return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2)); +#endif /* RCC_D2CFGR_D2PPRE2 */ +} + +/** + * @brief Get APB3 prescaler + * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB3_DIV_1 + * @arg @ref LL_RCC_APB3_DIV_2 + * @arg @ref LL_RCC_APB3_DIV_4 + * @arg @ref LL_RCC_APB3_DIV_8 + * @arg @ref LL_RCC_APB3_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) +{ +#if defined(RCC_D1CFGR_D1PPRE) + return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE)); +#else + return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE)); +#endif /* RCC_D1CFGR_D1PPRE */ +} + +/** + * @brief Get APB4 prescaler + * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB4_DIV_1 + * @arg @ref LL_RCC_APB4_DIV_2 + * @arg @ref LL_RCC_APB4_DIV_4 + * @arg @ref LL_RCC_APB4_DIV_8 + * @arg @ref LL_RCC_APB4_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void) +{ +#if defined(RCC_D3CFGR_D3PPRE) + return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE)); +#endif /* RCC_D3CFGR_D3PPRE */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK + * @arg @ref LL_RCC_MCO2SOURCE_CSI + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO1_DIV_6 + * @arg @ref LL_RCC_MCO1_DIV_7 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_9 + * @arg @ref LL_RCC_MCO1_DIV_10 + * @arg @ref LL_RCC_MCO1_DIV_11 + * @arg @ref LL_RCC_MCO1_DIV_12 + * @arg @ref LL_RCC_MCO1_DIV_13 + * @arg @ref LL_RCC_MCO1_DIV_14 + * @arg @ref LL_RCC_MCO1_DIV_15 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_6 + * @arg @ref LL_RCC_MCO2_DIV_7 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_9 + * @arg @ref LL_RCC_MCO2_DIV_10 + * @arg @ref LL_RCC_MCO2_DIV_11 + * @arg @ref LL_RCC_MCO2_DIV_12 + * @arg @ref LL_RCC_MCO2_DIV_13 + * @arg @ref LL_RCC_MCO2_DIV_14 + * @arg @ref LL_RCC_MCO2_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure periph clock source + * @rmtoll D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource\n + * D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource\n + * D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource)); +#else + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource)); +#endif /* */ + MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); +} + +/** + * @brief Configure USARTx clock source + * @rmtoll D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n + * D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D3CCIPR_LPUART1SEL) + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource); +#else + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource); +#endif /* RCC_D3CCIPR_LPUART1SEL */ +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n + * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource + * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n + * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource + * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n + * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SDMMCx clock source + * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_SDMMCSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource); +#endif /* RCC_D1CCIPR_SDMMCSEL */ +} + +/** + * @brief Configure RNGx clock source + * @rmtoll D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_RNGSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource); +#endif /* RCC_D2CCIP2R_RNGSEL */ +} + +/** + * @brief Configure USBx clock source + * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_USBSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource); +#endif /* RCC_D2CCIP2R_USBSEL */ +} + +/** + * @brief Configure CECx clock source + * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP2R_CECSEL) + MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource); +#endif /* RCC_D2CCIP2R_CECSEL */ +} + +#if defined(DSI) +/** + * @brief Configure DSIx clock source + * @rmtoll D1CCIPR DSISEL LL_RCC_SetDSIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource); +} +#endif /* DSI */ + +/** + * @brief Configure DFSDMx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_DFSDM1SEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource); +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +} + +#if defined(DFSDM2_BASE) +/** + * @brief Configure DFSDMx Kernel clock source + * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource); +} +#endif /* DFSDM2_BASE */ + +/** + * @brief Configure FMCx Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource); +#endif /* RCC_D1CCIPR_FMCSEL */ +} + +#if defined(QUADSPI) +/** + * @brief Configure QSPIx Kernel clock source + * @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource) +{ + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource); +} +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** + * @brief Configure OSPIx Kernel clock source + * @rmtoll D1CCIPR OPISEL LL_RCC_SetOSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_OCTOSPISEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource); +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +} +#endif /* OCTOSPI1 || OCTOSPI2 */ + +/** + * @brief Configure CLKP Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D1CCIPR_CKPERSEL) + MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource); +#endif /* RCC_D1CCIPR_CKPERSEL */ +} + +/** + * @brief Configure SPIx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n + * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n + * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource) +{ + LL_RCC_SetClockSource(ClkSource); +} + +/** + * @brief Configure SPDIFx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_SPDIFSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource); +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +} + +/** + * @brief Configure FDCANx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_FDCANSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource); +#endif /* RCC_D2CCIP1R_FDCANSEL */ +} + +/** + * @brief Configure SWPx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D2CCIP1R_SWPSEL) + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource); +#else + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource); +#endif /* RCC_D2CCIP1R_SWPSEL */ +} + +/** + * @brief Configure ADCx Kernel clock source + * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ClkSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource) +{ +#if defined(RCC_D3CCIPR_ADCSEL) + MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource); +#else + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource); +#endif /* RCC_D3CCIPR_ADCSEL */ +} + +/** + * @brief Get periph clock source + * @rmtoll D1CCIPR / CDCCIPR * LL_RCC_GetClockSource\n + * D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource\n + * D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource\n + * D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @arg @ref LL_RCC_I2C123_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI23_CLKSOURCE + * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI45_CLKSOURCE (*) + * @arg @ref LL_RCC_SPI6_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) +{ +#if defined(RCC_D1CCIPR_FMCSEL) + const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph))); +#else + const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph))); +#endif /* RCC_D1CCIPR_FMCSEL */ + return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT)); +} + +/** + * @brief Get USARTx clock source + * @rmtoll D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n + * D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI + * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPUART clock source + * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D3CCIPR_LPUART1SEL) + return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)); +#endif /* RCC_D3CCIPR_LPUART1SEL */ +} + +/** + * @brief Get I2Cx clock source + * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n + * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get LPTIM clock source + * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SAIx clock source + * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n + * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource + * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n + * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SDMMC clock source + * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_SDMMCSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)); +#endif /* RCC_D1CCIPR_SDMMCSEL */ +} + +/** + * @brief Get RNG clock source + * @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_RNGSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)); +#endif /* RCC_D2CCIP2R_RNGSEL */ +} + +/** + * @brief Get USB clock source + * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_USBSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)); +#endif /* RCC_D2CCIP2R_USBSEL */ +} + +/** + * @brief Get CEC clock source + * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI + * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP2R_CECSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)); +#endif /* RCC_D2CCIP2R_CECSEL */ +} + +#if defined(DSI) +/** + * @brief Get DSI clock source + * @rmtoll D1CCIPR DSISEL LL_RCC_GetDSIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)); +} +#endif /* DSI */ + +/** + * @brief Get DFSDM Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_DFSDM1SEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)); +#endif /* RCC_D2CCIP1R_DFSDM1SEL */ +} + +#if defined(DFSDM2_BASE) +/** + * @brief Get DFSDM2 Kernel clock source + * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)); +} +#endif /* DFSDM2_BASE */ + +/** + * @brief Get FMC Kernel clock source + * @rmtoll D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_FMCSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)); +#endif /* RCC_D1CCIPR_FMCSEL */ +} + +#if defined(QUADSPI) +/** + * @brief Get QSPI Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph) +{ + UNUSED(Periph); + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)); +} +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** + * @brief Get OSPI Kernel clock source + * @rmtoll CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_OCTOSPISEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)); +#endif /* RCC_D1CCIPR_OCTOSPISEL */ +} +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + +/** + * @brief Get CLKP Kernel clock source + * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI + * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D1CCIPR_CKPERSEL) + return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)); +#endif /* RCC_D1CCIPR_CKPERSEL */ +} + +/** + * @brief Get SPIx Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n + * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n + * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE + * @arg @ref LL_RCC_SPI45_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN + * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4 + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI + * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE + * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*) + * + * (*) value not defined in all stm32h7xx lines. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph) +{ + return LL_RCC_GetClockSource(Periph); +} + +/** + * @brief Get SPDIF Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_SPDIFSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)); +#endif /* RCC_D2CCIP1R_SPDIFSEL */ +} + +/** + * @brief Get FDCAN Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_FDCANSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)); +#endif /* RCC_D2CCIP1R_FDCANSEL */ +} + +/** + * @brief Get SWP Kernel clock source + * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined(RCC_D2CCIP1R_SWPSEL) + return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)); +#else + return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)); +#endif /* RCC_D2CCIP1R_SWPSEL */ +} + +/** + * @brief Get ADC Kernel clock source + * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource + * @param Periph This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph) +{ + UNUSED(Periph); +#if defined (RCC_D3CCIPR_ADCSEL) + return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)); +#else + return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)); +#endif /* RCC_D3CCIPR_ADCSEL */ +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ +#if defined(RCC_BDCR_BDRST) + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +#else + CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST); +#endif /* RCC_BDCR_BDRST */ +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @arg @ref LL_RCC_RTC_HSE_DIV_32 + * @arg @ref LL_RCC_RTC_HSE_DIV_33 + * @arg @ref LL_RCC_RTC_HSE_DIV_34 + * @arg @ref LL_RCC_RTC_HSE_DIV_35 + * @arg @ref LL_RCC_RTC_HSE_DIV_36 + * @arg @ref LL_RCC_RTC_HSE_DIV_37 + * @arg @ref LL_RCC_RTC_HSE_DIV_38 + * @arg @ref LL_RCC_RTC_HSE_DIV_39 + * @arg @ref LL_RCC_RTC_HSE_DIV_40 + * @arg @ref LL_RCC_RTC_HSE_DIV_41 + * @arg @ref LL_RCC_RTC_HSE_DIV_42 + * @arg @ref LL_RCC_RTC_HSE_DIV_43 + * @arg @ref LL_RCC_RTC_HSE_DIV_44 + * @arg @ref LL_RCC_RTC_HSE_DIV_45 + * @arg @ref LL_RCC_RTC_HSE_DIV_46 + * @arg @ref LL_RCC_RTC_HSE_DIV_47 + * @arg @ref LL_RCC_RTC_HSE_DIV_48 + * @arg @ref LL_RCC_RTC_HSE_DIV_49 + * @arg @ref LL_RCC_RTC_HSE_DIV_50 + * @arg @ref LL_RCC_RTC_HSE_DIV_51 + * @arg @ref LL_RCC_RTC_HSE_DIV_52 + * @arg @ref LL_RCC_RTC_HSE_DIV_53 + * @arg @ref LL_RCC_RTC_HSE_DIV_54 + * @arg @ref LL_RCC_RTC_HSE_DIV_55 + * @arg @ref LL_RCC_RTC_HSE_DIV_56 + * @arg @ref LL_RCC_RTC_HSE_DIV_57 + * @arg @ref LL_RCC_RTC_HSE_DIV_58 + * @arg @ref LL_RCC_RTC_HSE_DIV_59 + * @arg @ref LL_RCC_RTC_HSE_DIV_60 + * @arg @ref LL_RCC_RTC_HSE_DIV_61 + * @arg @ref LL_RCC_RTC_HSE_DIV_62 + * @arg @ref LL_RCC_RTC_HSE_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE)); +} + +/** + * @} + */ + +#if defined(HRTIM1) +/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM + * @{ + */ + +/** + * @brief Set High Resolution Timers Clock Source + * @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler); +} +#endif /* HRTIM1 */ + +#if defined(HRTIM1) +/** + * @brief Get High Resolution Timers Clock Source + * @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM + * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU + */ +__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)); +} +/** + * @} + */ +#endif /* HRTIM1 */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Set the oscillator used as PLL clock source. + * @note PLLSRC can be written only when All PLLs are disabled. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource + * @param PLLSource parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_CSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_NONE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC)); +} + +/** + * @brief Enable PLL1 + * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Check if PLL1 Ready + * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); +} + +/** + * @brief Enable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); +} + +/** + * @brief Enable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); +} + +/** + * @brief Enable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Check if PLL1 P is enabled + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 Q is enabled + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 R is enabled + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 FRACN is enabled + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL1P + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); +} + +/** + * @brief Disable PLL1Q + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); +} + +/** + * @brief Disable PLL1R + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); +} + +/** + * @brief Disable PLL1 FRACN + * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); +} + +/** + * @brief Set PLL1 VCO OutputRange + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos); +} + +/** + * @brief Set PLL1 VCO Input Range + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos); +} + +/** + * @brief Get PLL1 N Coefficient + * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 M Coefficient + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Get PLL1 P Coefficient + * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP + * @retval A value between 2 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 Q Coefficient + * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 R Coefficient + * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL); +} + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); +} + +/** + * @brief Set PLL1 N Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos); +} + +/** + * @brief Set PLL1 M Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos); +} + +/** + * @brief Set PLL1 P Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP + * @param P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines. + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos); +} + +/** + * @brief Set PLL1 Q Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos); +} + +/** + * @brief Set PLL1 R Coefficient + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos); +} + +/** + * @brief Set PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos); +} + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @note Cannot be disabled if the PLL2 clock is used as the system clock + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); +} + +/** + * @brief Enable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); +} + +/** + * @brief Enable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); +} + +/** + * @brief Enable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Check if PLL2 P is enabled + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 Q is enabled + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 R is enabled + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 FRACN is enabled + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL2P + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN); +} + +/** + * @brief Disable PLL2Q + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN); +} + +/** + * @brief Disable PLL2R + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN); +} + +/** + * @brief Disable PLL2 FRACN + * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN); +} + +/** + * @brief Set PLL2 VCO OutputRange + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos); +} + +/** + * @brief Set PLL2 VCO Input Range + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos); +} + +/** + * @brief Get PLL2 N Coefficient + * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 M Coefficient + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Get PLL2 P Coefficient + * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 Q Coefficient + * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 R Coefficient + * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL); +} + +/** + * @brief Get PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos); +} + +/** + * @brief Set PLL2 N Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos); +} + +/** + * @brief Set PLL2 M Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos); +} + +/** + * @brief Set PLL2 P Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos); +} + +/** + * @brief Set PLL2 Q Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos); +} + +/** + * @brief Set PLL2 R Coefficient + * @note This API shall be called only when PLL2 is disabled. + * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos); +} + +/** + * @brief Set PLL2 FRACN Coefficient + * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos); +} + +/** + * @brief Enable PLL3 + * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLL3 + * @note Cannot be disabled if the PLL3 clock is used as the system clock + * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLL3 Ready + * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); +} + +/** + * @brief Enable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); +} + +/** + * @brief Enable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); +} + +/** + * @brief Enable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Check if PLL3 P is enabled + * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 Q is enabled + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 R is enabled + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 FRACN is enabled + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL3P + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3P_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); +} + +/** + * @brief Disable PLL3Q + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); +} + +/** + * @brief Disable PLL3R + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3R_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); +} + +/** + * @brief Disable PLL3 FRACN + * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); +} + +/** + * @brief Set PLL3 VCO OutputRange + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange + * @param VCORange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLVCORANGE_WIDE + * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos); +} + +/** + * @brief Set PLL3 VCO Input Range + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_1_2 + * @arg @ref LL_RCC_PLLINPUTRANGE_2_4 + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos); +} + +/** + * @brief Get PLL3 N Coefficient + * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN + * @retval A value between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 M Coefficient + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM + * @retval A value between 0 and 63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Get PLL3 P Coefficient + * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 Q Coefficient + * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 R Coefficient + * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR + * @retval A value between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL); +} + +/** + * @brief Get PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos); +} + +/** + * @brief Set PLL3 N Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN + * @param N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos); +} + +/** + * @brief Set PLL3 M Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM + * @param M parameter can be a value between 0 and 63 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M) +{ + MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos); +} + +/** + * @brief Set PLL3 P Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP + * @param P parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos); +} + +/** + * @brief Set PLL3 Q Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ + * @param Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos); +} + +/** + * @brief Set PLL3 R Coefficient + * @note This API shall be called only when PLL3 is disabled. + * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR + * @param R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R) +{ + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos); +} + +/** + * @brief Set PLL3 FRACN Coefficient + * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos); +} + + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear CSI ready interrupt flag + * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC); +} + +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); +} + +/** + * @brief Clear PLL3 ready interrupt flag + * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Clear HSE Clock security system interrupt flag + * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSI ready interrupt occurred or not + * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL3 ready interrupt occurred or not + * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE Clock security system interrupt occurred or not + * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n + * RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL); +#endif /*DUAL_CORE*/ +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n + * RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL); +#endif /*DUAL_CORE*/ +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +#if defined(RCC_RSR_D1RSTF) +/** + * @brief Check if RCC flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_D1RSTF */ + +#if defined(RCC_RSR_CDRSTF) +/** + * @brief Check if RCC flag CD reset is set or not. + * @rmtoll RSR CDRSTF LL_RCC_IsActiveFlag_CDRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_CDRSTF */ + +#if defined(RCC_RSR_D2RSTF) +/** + * @brief Check if RCC flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} +#endif /* RCC_RSR_D2RSTF */ + +#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) +/** + * @brief Check if RCC flag CPU reset is set or not. + * @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n + * RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**) + * + * (*) Only available for single core devices + * (**) Only available for Dual core devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void) +{ +#if defined(DUAL_CORE) + return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +#else + return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL); +#endif/*DUAL_CORE*/ +} +#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */ + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Set RMVF bit to clear all reset flags. + * @rmtoll RSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); +} + +#if defined(DUAL_CORE) +/** + * @brief Check if RCC_C1 flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWR1RSTF LL_C1_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_C1_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_C1_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_C1_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_C1_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_C1_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Software reset is set or not. + * @rmtoll RSR SFT1RSTF LL_C1_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_C1_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_C1_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_C1_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_C1_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_C1_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_C1_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag CPU reset is set or not. + * @rmtoll RSR C1RSTF LL_C1_RCC_IsActiveFlag_CPURST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C1 flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_C1_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll RSR RMVF LL_C1_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF); +} + +/** + * @brief Check if RCC_C2 flag Low Power D1 reset is set or not. + * @rmtoll RSR LPWR1RSTF LL_C2_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Low Power D2 reset is set or not. + * @rmtoll RSR LPWR2RSTF LL_C2_RCC_IsActiveFlag_LPWR2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Window Watchdog 1 reset is set or not. + * @rmtoll RSR WWDG1RSTF LL_C2_RCC_IsActiveFlag_WWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Window Watchdog 2 reset is set or not. + * @rmtoll RSR WWDG2RSTF LL_C2_RCC_IsActiveFlag_WWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Independent Watchdog 1 reset is set or not. + * @rmtoll RSR IWDG1RSTF LL_C2_RCC_IsActiveFlag_IWDG1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Independent Watchdog 2 reset is set or not. + * @rmtoll RSR IWDG2RSTF LL_C2_RCC_IsActiveFlag_IWDG2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Software reset is set or not. + * @rmtoll RSR SFT1RSTF LL_C2_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Software reset is set or not. + * @rmtoll RSR SFT2RSTF LL_C2_RCC_IsActiveFlag_SFT2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag POR/PDR reset is set or not. + * @rmtoll RSR PORRSTF LL_C2_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag Pin reset is set or not. + * @rmtoll RSR PINRSTF LL_C2_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag BOR reset is set or not. + * @rmtoll RSR BORRSTF LL_C2_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag D1 reset is set or not. + * @rmtoll RSR D1RSTF LL_C2_RCC_IsActiveFlag_D1RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag D2 reset is set or not. + * @rmtoll RSR D2RSTF LL_C2_RCC_IsActiveFlag_D2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag CPU reset is set or not. + * @rmtoll RSR C1RSTF LL_C2_RCC_IsActiveFlag_CPURST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC_C2 flag CPU2 reset is set or not. + * @rmtoll RSR C2RSTF LL_C2_RCC_IsActiveFlag_CPU2RST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void) +{ + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll RSR RMVF LL_C2_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF); +} +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Enable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Enable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable CSI ready interrupt + * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE); +} + +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); +} + +/** + * @brief Disable PLL3 ready interrupt + * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); +} + +/** + * @brief Disable LSECSS interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if CSI ready interrupt source is enabled or disabled. + * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL3 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +void LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR); + +void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks); +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); + +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +#if defined(DFSDM2_BASE) +uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource); +#endif /* DFSDM2_BASE */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource); +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource); +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource); +#if defined(QUADSPI) +uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) +uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource); +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + + +/** + * @} + */ +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_RCC_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h new file mode 100644 index 0000000..f1f673a --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h @@ -0,0 +1,5215 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_rtc.h + * @author MCD Application Team + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_RTC_H +#define STM32H7xx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_LL_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_LL_INIT_MASK 0xFFFFFFFFU +#define RTC_LL_RSF_MASK 0xFFFFFF5FU + +/* Write protection defines */ +#define RTC_WRITE_PROTECTION_DISABLE 0xFFU +#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU +#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U + +/* Defines used to combine date & time */ +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hours Format. + This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetHourFormat(). */ + + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetSynchPrescaler(). */ +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */ + + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected. + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */ +} LL_RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_LL_EC_WEEKDAY + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */ + + uint8_t Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_LL_EC_MONTH + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */ + + uint8_t Day; /*!< Specifies the RTC Date Day. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 + + This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */ +} LL_RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A + or @ref LL_RTC_ALMB_SetMask() for ALARM B + */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. + This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() + for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B + */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. + If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay() + for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. + + If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY. + + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay() + for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. + */ +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + * @{ + */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + * @{ + */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RTC_ReadReg function + * @{ + */ +#if defined(TAMP) +#define LL_RTC_SCR_ITSF RTC_SCR_CITSF +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF +#define LL_RTC_SCR_TSF RTC_SCR_CTSF +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF +#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF + +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF +#else +#define LL_RTC_ISR_ITSF RTC_ISR_ITSF +#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF +#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F +#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F +#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F +#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF +#define LL_RTC_ISR_TSF RTC_ISR_TSF +#define LL_RTC_ISR_WUTF RTC_ISR_WUTF +#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF +#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF +#define LL_RTC_ISR_INITF RTC_ISR_INITF +#define LL_RTC_ISR_RSF RTC_ISR_RSF +#define LL_RTC_ISR_INITS RTC_ISR_INITS +#define LL_RTC_ISR_SHPF RTC_ISR_SHPF +#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF +#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF +#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF +#endif /* TAMP */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions + * @{ + */ +#define LL_RTC_CR_TSIE RTC_CR_TSIE +#define LL_RTC_CR_WUTIE RTC_CR_WUTIE +#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE +#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +#if !defined(TAMP) +#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE +#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE +#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE +#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE +#endif /* !TAMP */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY + * @{ + */ +#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_MONTH MONTH + * @{ + */ +#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT + * @{ + */ +#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + * @{ + */ +#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ +#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ +#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE + * @{ + */ +#if defined(TAMP) +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */ +#else +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ +#endif /* TAMP */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + * @{ + */ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ +#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + * @{ + */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + * @{ + */ +#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + * @{ + */ +#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ +#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + * @{ + */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + * @{ + */ +#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/ +#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + * @{ + */ +#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + * @{ + */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + * @{ + */ +#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ +/** + * @} + */ + +#if defined(TAMP) +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +/** + * @} + */ +#else +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ +#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ +#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ +#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ +#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +/** + * @} + */ +#endif /* TAMP */ + +#if defined(TAMP) +/** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION + * @{ + */ +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos) + +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos) + +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos) +/** + * @} + */ +#endif /* TAMP */ + +/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + * @{ + */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#define LL_RTC_BKP_DR0 0x00000000U +#define LL_RTC_BKP_DR1 0x00000001U +#define LL_RTC_BKP_DR2 0x00000002U +#define LL_RTC_BKP_DR3 0x00000003U +#define LL_RTC_BKP_DR4 0x00000004U +#define LL_RTC_BKP_DR5 0x00000005U +#define LL_RTC_BKP_DR6 0x00000006U +#define LL_RTC_BKP_DR7 0x00000007U +#define LL_RTC_BKP_DR8 0x00000008U +#define LL_RTC_BKP_DR9 0x00000009U +#define LL_RTC_BKP_DR10 0x0000000AU +#define LL_RTC_BKP_DR11 0x0000000BU +#define LL_RTC_BKP_DR12 0x0000000CU +#define LL_RTC_BKP_DR13 0x0000000DU +#define LL_RTC_BKP_DR14 0x0000000EU +#define LL_RTC_BKP_DR15 0x0000000FU +#define LL_RTC_BKP_DR16 0x00000010U +#define LL_RTC_BKP_DR17 0x00000011U +#define LL_RTC_BKP_DR18 0x00000012U +#define LL_RTC_BKP_DR19 0x00000013U +#define LL_RTC_BKP_DR20 0x00000014U +#define LL_RTC_BKP_DR21 0x00000015U +#define LL_RTC_BKP_DR22 0x00000016U +#define LL_RTC_BKP_DR23 0x00000017U +#define LL_RTC_BKP_DR24 0x00000018U +#define LL_RTC_BKP_DR25 0x00000019U +#define LL_RTC_BKP_DR26 0x0000001AU +#define LL_RTC_BKP_DR27 0x0000001BU +#define LL_RTC_BKP_DR28 0x0000001CU +#define LL_RTC_BKP_DR29 0x0000001DU +#define LL_RTC_BKP_DR30 0x0000001EU +#define LL_RTC_BKP_DR31 0x0000001FU +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + * @{ + */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + * @{ + */ +#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F))) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Date Date helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve weekday. + * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Year in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Year in BCD format (0x00 . . . 0x99) + */ +#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Month in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Day in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Day in BCD format (0x01 . . . 0x31) + */ +#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Time Time helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve hour in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve minute in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve second in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Seconds in format (0x00. . .0x59) + */ +#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat + * @param RTCx RTC Instance + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) +{ + MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); +} + +/** + * @brief Get Hours format (24 hour/day or AM/PM hour format) + * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + */ +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); +} + +/** + * @brief Select the flag to be routed to RTC_ALARM output + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent + * @param RTCx RTC Instance + * @param AlarmOutput This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) +{ + MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); +} + +/** + * @brief Get the flag to be routed to RTC_ALARM output + * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); +} + +#if defined(TAMP) +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); +} +#else +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @note Used only when RTC_ALARM is mapped on PC13 + * @rmtoll OR ALARMOUTTYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @note used only when RTC_ALARM is mapped on PC13 + * @rmtoll OR ALARMOUTTYPE LL_RTC_GetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); +} +#endif /* TAMP */ + +#if defined(TAMP) +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT); +} + +#else +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll ISR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + WRITE_REG(RTCx->ISR, RTC_LL_INIT_MASK); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll ISR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); +} +#endif /* TAMP */ + +/** + * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity + * @param RTCx RTC Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) +{ + MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); +} + +/** + * @brief Get Output polarity + * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); +} + +/** + * @brief Enable Bypass the shadow registers + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Disable Bypass the shadow registers + * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Check if Shadow registers bypass is enabled or not. + * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); +} + +/** + * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Set Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @param RTCx RTC Instance + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Get Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); +} + +#if defined(TAMP) +/** + * @brief Enable tamper output. + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output. + * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL); +} + +/** + * @brief Enable RTC_OUT2 output + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. + * @note RTC_OUT2 isn't available ins VBAT mode. + * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output + * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL); +} +#else +/** + * @brief Enable RTC_OUT remap + * @rmtoll OR OUT_RMP LL_RTC_EnableOutRemap + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->OR, RTC_OR_OUT_RMP); +} + +/** + * @brief Disable RTC_OUT remap + * @rmtoll OR OUT_RMP LL_RTC_DisableOutRemap + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP); +} +#endif /* TAMP */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time format (AM/24-hour or PM notation) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); +} + +/** + * @brief Get time format (AM or PM notation) + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); +} + +/** + * @brief Set Hours in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format + * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour + * RTC_TR HU LL_RTC_TIME_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); +} + +/** + * @brief Get Hours in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to + * Binary format + * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour + * RTC_TR HU LL_RTC_TIME_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); +} + +/** + * @brief Set Minutes in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute + * RTC_TR MNU LL_RTC_TIME_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); +} + +/** + * @brief Get Minutes in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD + * to Binary format + * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute + * RTC_TR MNU LL_RTC_TIME_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); +} + +/** + * @brief Set Seconds in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond + * RTC_TR SU LL_RTC_TIME_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); +} + +/** + * @brief Get Seconds in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD + * to Binary format + * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond + * RTC_TR SU LL_RTC_TIME_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); +} + +/** + * @brief Set time (hour, minute and second) in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note TimeFormat and Hours should follow the same format + * @rmtoll RTC_TR PM LL_RTC_TIME_Config + * RTC_TR HT LL_RTC_TIME_Config + * RTC_TR HU LL_RTC_TIME_Config + * RTC_TR MNT LL_RTC_TIME_Config + * RTC_TR MNU LL_RTC_TIME_Config + * RTC_TR ST LL_RTC_TIME_Config + * RTC_TR SU LL_RTC_TIME_Config + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); +} + +/** + * @brief Get time (hour, minute and second) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TR HT LL_RTC_TIME_Get + * RTC_TR HU LL_RTC_TIME_Get + * RTC_TR MNT LL_RTC_TIME_Get + * RTC_TR MNU LL_RTC_TIME_Get + * RTC_TR ST LL_RTC_TIME_Get + * RTC_TR SU LL_RTC_TIME_Get + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); +} + +/** + * @brief Memorize whether the daylight saving time change has been performed + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Disable memorization whether the daylight saving time change has been performed. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Check if RTC Day Light Saving stored operation has been enabled or not + * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); +} + +/** + * @brief Subtract 1 hour (winter time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SUB1H); +} + +/** + * @brief Add 1 hour (summer time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ADD1H); +} + +/** + * @brief Get Sub second value in the synchronous prescaler counter. + * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through + * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar + * SubSeconds value in second fraction ratio with time unit following + * generic formula: + * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS. + * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond + * @param RTCx RTC Instance + * @retval Sub second value (number between 0 and 65535) + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); +} + +/** + * @brief Synchronize to a remote clock with a high degree of precision. + * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @param RTCx RTC Instance + * @param ShiftSecond This parameter can be one of the following values: + * @arg @ref LL_RTC_SHIFT_SECOND_DELAY + * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE + * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction) +{ + WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Date Date + * @{ + */ + +/** + * @brief Set Year in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format + * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear + * RTC_DR YU LL_RTC_DATE_SetYear + * @param RTCx RTC Instance + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); +} + +/** + * @brief Get Year in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format + * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear + * RTC_DR YU LL_RTC_DATE_GetYear + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x99 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); +} + +/** + * @brief Set Week day + * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); +} + +/** + * @brief Get Week day + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); +} + +/** + * @brief Set Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format + * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth + * RTC_DR MU LL_RTC_DATE_SetMonth + * @param RTCx RTC Instance + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); +} + +/** + * @brief Get Month in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth + * RTC_DR MU LL_RTC_DATE_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); +} + +/** + * @brief Set Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay + * RTC_DR DU LL_RTC_DATE_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); +} + +/** + * @brief Get Day in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay + * RTC_DR DU LL_RTC_DATE_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); +} + +/** + * @brief Set date (WeekDay, Day, Month and Year) in BCD format + * @rmtoll RTC_DR WDU LL_RTC_DATE_Config + * RTC_DR MT LL_RTC_DATE_Config + * RTC_DR MU LL_RTC_DATE_Config + * RTC_DR DT LL_RTC_DATE_Config + * RTC_DR DU LL_RTC_DATE_Config + * RTC_DR YT LL_RTC_DATE_Config + * RTC_DR YU LL_RTC_DATE_Config + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) +{ + uint32_t temp; + + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + + MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); +} + +/** + * @brief Get date (WeekDay, Day, Month and Year) in BCD format + * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_DR WDU LL_RTC_DATE_Get + * RTC_DR MT LL_RTC_DATE_Get + * RTC_DR MU LL_RTC_DATE_Get + * RTC_DR DT LL_RTC_DATE_Get + * RTC_DR DU LL_RTC_DATE_Get + * RTC_DR YT LL_RTC_DATE_Get + * RTC_DR YU LL_RTC_DATE_Get + * @param RTCx RTC Instance + * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMA ALARMA + * @{ + */ + +/** + * @brief Enable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Disable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Specify the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); +} + +/** + * @brief Get the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); +} + +/** + * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Set ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); +} + +/** + * @brief Get ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Get ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set Alarm A time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +} + +/** + * @brief Get Alarm A time format (AM or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); +} + +/** + * @brief Set ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); +} + +/** + * @brief Get ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); +} + +/** + * @brief Set ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); +} + +/** + * @brief Get ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); +} + +/** + * @brief Set ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); +} + +/** + * @brief Get ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); +} + +/** + * @brief Set Alarm A Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask Value between Min_Data=0x00 and Max_Data=0xF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); +} + +/** + * @brief Get Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMB ALARMB + * @{ + */ + +/** + * @brief Enable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Disable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Specify the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); +} + +/** + * @brief Get the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); +} + +/** + * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Set ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); +} + +/** + * @brief Get ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Get ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +} + +/** + * @brief Get ALARM B time format (AM or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); +} + +/** + * @brief Set ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); +} + +/** + * @brief Get ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); +} + +/** + * @brief Set ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute + * @param RTCx RTC Instance + * @param Minutes between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); +} + +/** + * @brief Get ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); +} + +/** + * @brief Set ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); +} + +/** + * @brief Get ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); +} + +/** + * @brief Set Alarm B Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask Value between Min_Data=0x00 and Max_Data=0xF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); +} + +/** + * @brief Get Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Timestamp Timestamp + * @{ + */ + +/** + * @brief Enable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Disable internal event timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ITSE); +} + +/** + * @brief Enable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Disable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Set Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge + * @param RTCx RTC Instance + * @param Edge This parameter can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); +} + +/** + * @brief Get Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); +} + +/** + * @brief Get Timestamp AM/PM notation (AM or 24-hour format) + * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TS_TIME_FORMAT_AM + * @arg @ref LL_RTC_TS_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); +} + +/** + * @brief Get Timestamp Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour + * RTC_TSTR HU LL_RTC_TS_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); +} + +/** + * @brief Get Timestamp Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute + * RTC_TSTR MNU LL_RTC_TS_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); +} + +/** + * @brief Get Timestamp Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond + * RTC_TSTR SU LL_RTC_TS_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime + * RTC_TSTR HU LL_RTC_TS_GetTime + * RTC_TSTR MNT LL_RTC_TS_GetTime + * RTC_TSTR MNU LL_RTC_TS_GetTime + * RTC_TSTR ST LL_RTC_TS_GetTime + * RTC_TSTR SU LL_RTC_TS_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, + RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp Week day + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); +} + +/** + * @brief Get Timestamp Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth + * RTC_TSDR MU LL_RTC_TS_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); +} + +/** + * @brief Get Timestamp Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay + * RTC_TSDR DU LL_RTC_TS_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate + * RTC_TSDR MT LL_RTC_TS_GetDate + * RTC_TSDR MU LL_RTC_TS_GetDate + * RTC_TSDR DT LL_RTC_TS_GetDate + * RTC_TSDR DU LL_RTC_TS_GetDate + * @param RTCx RTC Instance + * @retval Combination of Weekday, Day and Month + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get time-stamp sub second value + * @rmtoll RTC_TSSSR SS LL_RTC_TS_GetSubSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper_Timestamp Time-stamp on Tamper + * @{ + */ + +#if !defined(TAMP) +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); +} +#else +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ + +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); +} +#endif /* !TAMP */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +#if !defined(TAMP) +/** + * @brief Enable RTC_TAMPx input detection + * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable + * TAMPCR TAMP2E LL_RTC_TAMPER_Enable + * TAMPCR TAMP3E LL_RTC_TAMPER_Enable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + SET_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Clear RTC_TAMPx input detection + * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable + * TAMPCR TAMP2E LL_RTC_TAMPER_Disable + * TAMPCR TAMP3E LL_RTC_TAMPER_Disable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + CLEAR_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask + * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask + * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + SET_BIT(RTCx->TAMPCR, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask + * TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask + * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + CLEAR_BIT(RTCx->TAMPCR, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP + * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP + * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + CLEAR_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP + * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP + * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + SET_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param RTCx RTC Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) +{ + MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param RTCx RTC Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) +{ + MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param RTCx RTC Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) +{ + MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel + * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel + * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + SET_BIT(RTCx->TAMPCR, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel + * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel + * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +{ + CLEAR_BIT(RTCx->TAMPCR, Tamper); +} +#endif /* !TAMP */ + +#if defined(TAMP) +/** + * @brief Enable TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Enable + * TAMP_CR1 TAMP3E LL_RTC_TAMPER_Enable + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR1, Tamper); +} + +/** + * @brief Clear TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable + * TAMP_CR1 TAMP2E LL_RTC_TAMPER_Disable + * TAMP_CR1 TAMP3E LL_RTC_TAMPER_Disable + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_2 + * @arg @ref LL_RTC_TAMPER_3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR1, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask + * TAMP_CR2 TAMP2MF LL_RTC_TAMPER_EnableMask + * TAMP_CR2 TAMP3MF LL_RTC_TAMPER_EnableMask + * @param TAMPx TAMP Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask) +{ + SET_BIT(TAMPx->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask + * TAMP_CR2 TAMP2MF LL_RTC_TAMPER_DisableMask + * TAMP_CR2 TAMP3MF LL_RTC_TAMPER_DisableMask + * @param TAMPx TAMP Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 + * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask) +{ + CLEAR_BIT(TAMPx->CR2, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP + * TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP + * TAMP_CR2 TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP + * TAMP_CR2 TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 + * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel + * TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + SET_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel + * TAMP_CR2 TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel + * @param TAMPx TAMP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper) +{ + CLEAR_BIT(TAMPx->CR2, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable (Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param TAMPx TAMP Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param TAMPx TAMP Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param TAMPx TAMP Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq) +{ + MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param TAMPx TAMP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx) +{ + return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} +#endif /* TAMP */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Check if Wakeup timer is enabled or not + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); +} + +/** + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param RTCx RTC Instance + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get Wakeup clock + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get Wakeup auto-reload value + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +/** + * @} + */ + + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +#if !defined(TAMP) +/** + * @brief Writes a data in a specified RTC Backup data register. + * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + tmp = (uint32_t)(&(RTCx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +{ + uint32_t tmp; + + tmp = (uint32_t)(&(RTCx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} +#else +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister + * @param TAMPx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + tmp = (uint32_t)(&(TAMPx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister + * @param TAMPx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 + * @arg @ref LL_RTC_BKP_DR12 + * @arg @ref LL_RTC_BKP_DR13 + * @arg @ref LL_RTC_BKP_DR14 + * @arg @ref LL_RTC_BKP_DR15 + * @arg @ref LL_RTC_BKP_DR16 + * @arg @ref LL_RTC_BKP_DR17 + * @arg @ref LL_RTC_BKP_DR18 + * @arg @ref LL_RTC_BKP_DR19 + * @arg @ref LL_RTC_BKP_DR20 + * @arg @ref LL_RTC_BKP_DR21 + * @arg @ref LL_RTC_BKP_DR22 + * @arg @ref LL_RTC_BKP_DR23 + * @arg @ref LL_RTC_BKP_DR24 + * @arg @ref LL_RTC_BKP_DR25 + * @arg @ref LL_RTC_BKP_DR26 + * @arg @ref LL_RTC_BKP_DR27 + * @arg @ref LL_RTC_BKP_DR28 + * @arg @ref LL_RTC_BKP_DR29 + * @arg @ref LL_RTC_BKP_DR30 + * @arg @ref LL_RTC_BKP_DR31 + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) +{ + uint32_t tmp; + + tmp = (uint32_t)(&(TAMPx->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} +#endif /* !TAMP */ + +/** + * @} + */ + + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +/** + * @} + */ + + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +#if !defined(TAMP) +/** + * @brief Get Internal Time-stamp flag + * @rmtoll RTC_ISR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); +} + +/** + * @brief Get RTC_TAMP3 detection flag + * @rmtoll ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL); +} + +/** + * @brief Get RTC_TAMP2 detection flag + * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); +} + +/** + * @brief Get RTC_TAMP1 detection flag + * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm B flag + * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm A flag + * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll ISR ITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear RTC_TAMP3 detection flag + * @rmtoll ISR TAMP3F LL_RTC_ClearFlag_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear RTC_TAMP2 detection flag + * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear RTC_TAMP1 detection flag + * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll ISR TSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Get Initialization flag + * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll ISR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll ISR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm B write flag + * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm A write flag + * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); +} +#endif /* !TAMP */ + +#if defined(TAMP) +/** + * @brief Get Internal Time-stamp flag + * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm B flag + * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm A flag + * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL); +} + +/** + * @brief Clear Internal Time-stamp flag + * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CITSF); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Get Recalibration pending Flag + * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL); +} + +/** + * @brief Get Initialization flag + * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm B write flag + * @rmtoll RTC_ICSR ALRBWF LL_RTC_IsActiveFlag_ALRBW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm A write flag + * @rmtoll RTC_ICSR ALRAWF LL_RTC_IsActiveFlag_ALRAW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm A masked flag. + * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL); +} + +/** + * @brief Get Alarm B masked flag. + * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL); +} + +/** + * @brief Get Wakeup timer masked flag. + * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL); +} + +/** + * @brief Get Time-stamp masked flag. + * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL); +} + +/** + * @brief Get Time-stamp overflow masked flag. + * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL); +} + +/** + * @brief Get Internal Time-stamp masked flag. + * @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL); +} + +/** + * @brief Get tamper 1 detection flag. + * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL); +} + +/** + * @brief Get tamper 2 detection flag. + * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL); +} + +/** + * @brief Get tamper 3 detection flag. + * @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL); +} + +/** + * @brief Get tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL); +} + +/** + * @brief Get tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL); +} + +/** + * @brief Get tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL); +} + +/** + * @brief Clear tamper 1 detection flag. + * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F); +} + +/** + * @brief Clear tamper 2 detection flag. + * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F); +} + +/** + * @brief Clear tamper 3 detection flag. + * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F); +} +#endif /* TAMP */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +#if !defined(TAMP) +/** + * @brief Enable Tamper 3 interrupt + * @rmtoll TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); +} + +/** + * @brief Disable Tamper 3 interrupt + * @rmtoll TAMPCR TAMP3IE LL_RTC_DisableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); +} + +/** + * @brief Enable Tamper 2 interrupt + * @rmtoll TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); +} + +/** + * @brief Disable Tamper 2 interrupt + * @rmtoll TAMPCR TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); +} + +/** + * @brief Enable Tamper 1 interrupt + * @rmtoll TAMPCR TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); +} + +/** + * @brief Disable Tamper 1 interrupt + * @rmtoll TAMPCR TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); +} + +/** + * @brief Enable all Tamper Interrupt + * @rmtoll TAMPCR TAMPIE LL_RTC_EnableIT_TAMP + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE); +} + +/** + * @brief Disable all Tamper Interrupt + * @rmtoll TAMPCR TAMPIE LL_RTC_DisableIT_TAMP + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE); +} +#endif /* !TAMP */ + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); +} + +#if !defined(TAMP) +/** + * @brief Check if Tamper 3 interrupt is enabled or not + * @rmtoll TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tamper 2 interrupt is enabled or not + * @rmtoll TAMPCR TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL); + +} + +/** + * @brief Check if Tamper 1 interrupt is enabled or not + * @rmtoll TAMPCR TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL); +} + +/** + * @brief Check if all the TAMPER interrupts are enabled or not + * @rmtoll TAMPCR TAMPIE LL_RTC_IsEnabledIT_TAMP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL); +} +#endif /* !TAMP */ + +#if defined(TAMP) +/** + * @brief Enable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Disable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Enable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Disable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Enable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(TAMP_TypeDef *TAMPx) +{ + SET_BIT(TAMPx->IER, TAMP_IER_TAMP3IE); +} + +/** + * @brief Disable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3 + * @param TAMPx TAMP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx) +{ + CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE); +} + +/** + * @brief Check if tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL); +} + +/** + * @brief Check if tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL); +} + +/** + * @brief Check if tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3 + * @param TAMPx TAMP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx) +{ + return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper + * @{ + */ +/** + * @brief Enable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_EnableActiveMode + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_EnableActiveMode + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_EnableActiveMode + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper) +{ + SET_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Disable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_DisableActiveMode + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_DisableActiveMode + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_DisableActiveMode + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper) +{ + CLEAR_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Enable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_EnableFilter + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Disable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_DisableFilter + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Set Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod + * @param ActiveOutputChangePeriod This parameter can be a value from 0 to 7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos)); +} + +/** + * @brief Get Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod + * @retval Output change period. This parameter can be a value from 0 to 7. + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos); +} + +/** + * @brief Set Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler + * @param ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock. + This parameter can be a value of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler); +} + +/** + * @brief Get Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler + * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL)); +} + +/** + * @brief Enable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_EnableOutputSharing + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Disable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_DisableOutputSharing + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Set Active tamper output selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection + * @param OutputSelection Specifies all the output selection of the Active Tamper. + This parameter is a combinasation of the following values: + * One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection) +{ + MODIFY_REG(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3), \ + OutputSelection); +} + +/** + * @brief Get Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR2 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler + * @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void) +{ + return (READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3))); +} + +/** + * @brief Write active tamper seed. + * @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed + * @param Seed + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed) +{ + WRITE_REG(TAMP->ATSEEDR, Seed); +} + +/** + * @brief Get active tamper initialization status flag. + * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get active tamper seed running status flag. + * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U); +} +#endif /* TAMP */ + +/** + * @} + */ + + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct); +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct); +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_RTC_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h new file mode 100644 index 0000000..cb623a0 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h @@ -0,0 +1,3781 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_SPI_H +#define STM32H7xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure + the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions + @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXP (SPI_SR_RXP) +#define LL_SPI_SR_TXP (SPI_SR_TXP) +#define LL_SPI_SR_DXP (SPI_SR_DXP) +#define LL_SPI_SR_EOT (SPI_SR_EOT) +#define LL_SPI_SR_TXTF (SPI_SR_TXTF) +#define LL_SPI_SR_UDR (SPI_SR_UDR) +#define LL_SPI_SR_CRCE (SPI_SR_CRCE) +#define LL_SPI_SR_MODF (SPI_SR_MODF) +#define LL_SPI_SR_OVR (SPI_SR_OVR) +#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE) +#define LL_SPI_SR_TSERF (SPI_SR_TSERF) +#define LL_SPI_SR_SUSP (SPI_SR_SUSP) +#define LL_SPI_SR_TXC (SPI_SR_TXC) +#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE) +#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE) +#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE) +#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE) +#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE) +#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE) +#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE) +#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE) +#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE) +#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE) +#define LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER) +#define LL_SPI_MODE_SLAVE (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_LEVEL SS Level + * @{ + */ +#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI) +#define LL_SPI_SS_LEVEL_LOW (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness + * @{ + */ +#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3) +#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\ + | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness + * @{ + */ +#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3) +#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\ + | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All + * @{ + */ +#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All + * @{ + */ +#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register + * @{ + */ +#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL) +#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0) +#define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data + * @{ + */ +#define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL) +#define LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0) +#define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL) +#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE (0x00000000UL) +#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW (0x00000000UL) +#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity + * @{ + */ +#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL) +#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL) +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2) +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST) +#define LL_SPI_MSB_FIRST (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX (0x00000000UL) +#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0) +#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Data Width + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4) +#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold + * @{ + */ +#define LL_SPI_FIFO_TH_01DATA (0x00000000UL) +#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3) +#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\ + | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC CRC + * @{ + */ +#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4) +#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM) +#define LL_SPI_NSS_HARD_INPUT (0x00000000UL) +#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel + * @{ + */ +#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ +#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Swap the MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Restore default function for MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Check if MOSI and MISO pin are swapped + * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Disable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Check if GPIO control is active + * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI Mode to Master or Slave + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 MASTER LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); +} + +/** + * @brief Get SPI Mode (Master or Slave) + * @rmtoll CFG2 MASTER LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); +} + +/** + * @brief Configure the Idleness applied by master between active edge of SS and first send data + * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness + * @param SPIx SPI Instance + * @param MasterSSIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); +} + +/** + * @brief Get the configured Idleness applied by master + * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); +} + +/** + * @brief Configure the idleness applied by master between data frame + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @param MasterInterDataIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness); +} + +/** + * @brief Get the configured inter data idleness + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI)); +} + +/** + * @brief Set transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize + * @param SPIx SPI Instance + * @param Count 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count); +} + +/** + * @brief Get transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE)); +} + +/** + * @brief Set reload transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSER LL_SPI_SetReloadSize + * @param SPIx SPI Instance + * @param Count 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos); +} + +/** + * @brief Get reload transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSER LL_SPI_GetReloadSize + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos); +} + +/** + * @brief Lock the AF configuration of associated IOs + * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs. + * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. + * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK); +} + +/** + * @brief Check if the AF configuration is locked. + * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Set Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern + * @param SPIx SPI Instance + * @param TXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll); +} + +/** + * @brief Get Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI)); +} + +/** + * @brief Set Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern + * @param SPIx SPI Instance + * @param RXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll); +} + +/** + * @brief Get Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI)); +} + +/** + * @brief Set internal SS input level ignoring what comes from PIN. + * @note This configuration has effect only with config LL_SPI_NSS_SOFT + * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel + * @param SPIx SPI Instance + * @param SSLevel This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel); +} + +/** + * @brief Get internal SS input level + * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + */ +__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI)); +} + +/** + * @brief Enable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Disable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Check if Enable CRC computation on 33/17 bits is enabled + * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL); +} + +/** + * @brief Suspend an ongoing transfer for Master configuration + * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSUSP); +} + +/** + * @brief Start effective transfer on wire for Master configuration + * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSTART); +} + +/** + * @brief Check if there is an unfinished master transfer + * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); +} + +/** + * @brief Enable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Disable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Check if Master Rx auto suspend is activated + * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL); +} + +/** + * @brief Set Underrun behavior + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration + * @param SPIx SPI Instance + * @param UDRConfig This parameter can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); +} + +/** + * @brief Get Underrun behavior + * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); +} + +/** + * @brief Set Underrun Detection method + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 UDRDET LL_SPI_SetUDRDetection + * @param SPIx SPI Instance + * @param UDRDetection This parameter can be one of the following values: + * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME + * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME + * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection); +} + +/** + * @brief Get Underrun Detection method + * @rmtoll CFG1 UDRDET LL_SPI_GetUDRDetection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME + * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME + * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET)); +} + +/** + * @brief Set Serial protocol used + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 SP LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard); +} + +/** + * @brief Get Serial protocol used + * @rmtoll CFG2 SP LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP)); +} + +/** + * @brief Set Clock phase + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase); +} + +/** + * @brief Get Clock phase + * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA)); +} + +/** + * @brief Set Clock polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity); +} + +/** + * @brief Get Clock polarity + * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL)); +} + +/** + * @brief Set NSS polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity + * @param SPIx SPI Instance + * @param NSSPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity); +} + +/** + * @brief Get NSS polarity + * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); +} + +/** + * @brief Set Baudrate Prescaler + * @note This configuration can not be changed when SPI is enabled. + * SPI BaudRate = fPCLK/Pescaler. + * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param Baudrate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate); +} + +/** + * @brief Get Baudrate Prescaler + * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR)); +} + +/** + * @brief Set Transfer Bit Order + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder); +} + +/** + * @brief Get Transfer Bit Order + * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST)); +} + +/** + * @brief Set Transfer Mode + * @note This configuration can not be changed when SPI is enabled except for half duplex direction + * using LL_SPI_SetHalfDuplexDirection. + * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n + * CFG2 COMM LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR); + MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM); +} + +/** + * @brief Get Transfer Mode + * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n + * CFG2 COMM LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +{ + uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR); + uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM); + return (Hddir | Comm); +} + +/** + * @brief Set direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection + * @param SPIx SPI Instance + * @param HalfDuplexDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR); +} + +/** + * @brief Get direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM); +} + +/** + * @brief Set Frame Data Size + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); +} + +/** + * @brief Get Frame Data Size + * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event + * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + */ +__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); +} + +/** + * @brief Enable CRC + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Disable CRC + * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE)); +} + +/** + * @brief Set NSS Mode + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n + * CFG2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS); +} + +/** + * @brief Set NSS Mode + * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n + * CFG2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE)); +} + +/** + * @brief Enable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Disable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Check if NSS pulse is enabled + * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if there is enough data in FIFO to read a full packet + * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there is enough space in FIFO to hold a full packet + * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet + * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL); +} + +/** + * @brief Check that end of transfer event occurred + * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); +} + +/** + * @brief Check that all required data has been filled in the fifo according to transfer size + * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL); +} + +/** + * @brief Get Underrun error flag + * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL); +} + +/** + * @brief Get Mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get Overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get TI Frame format error flag + * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the additional number of data has been reloaded + * @rmtoll SR TSERF LL_SPI_IsActiveFlag_TSER + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL); +} + +/** + * @brief Check if a suspend operation is done + * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Check if last TxFIFO or CRC frame transmission is completed + * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL); +} + +/** + * @brief Check if at least one 32-bit data is available in RxFIFO + * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL); +} + +/** + * @brief Get number of data framed remaining in current TSIZE + * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos); +} + +/** + * @brief Get RxFIFO packing Level + * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_0PACKET + * @arg @ref LL_SPI_RX_FIFO_1PACKET + * @arg @ref LL_SPI_RX_FIFO_2PACKET + * @arg @ref LL_SPI_RX_FIFO_3PACKET + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL)); +} + +/** + * @brief Clear End Of Transfer flag + * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC); +} + +/** + * @brief Clear TXTF flag + * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC); +} + +/** + * @brief Clear Underrun error flag + * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC); +} + +/** + * @brief Clear Overrun error flag + * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC); +} + +/** + * @brief Clear CRC error flag + * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC); +} + +/** + * @brief Clear Mode fault error flag + * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC); +} + +/** + * @brief Clear Frame format error flag + * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC); +} + +/** + * @brief Clear TSER flag + * @rmtoll IFCR TSERFC LL_SPI_ClearFlag_TSER + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC); +} + +/** + * @brief Clear SUSP flag + * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Enable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Enable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Enable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Enable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Enable Underrun IT + * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Enable Overrun IT + * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Enable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Enable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Enable MODF IT + * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Enable TSER reload IT + * @rmtoll IER TSERFIE LL_SPI_EnableIT_TSER + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TSERFIE); +} + +/** + * @brief Disable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Disable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Disable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Disable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Disable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Disable Underrun IT + * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Disable Overrun IT + * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Disable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Disable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Disable MODF IT + * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Disable TSER reload IT + * @rmtoll IER TSERFIE LL_SPI_DisableIT_TSER + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE); +} + +/** + * @brief Check if Rx Packet available IT is enabled + * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx Packet space available IT is enabled + * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Duplex Packet available IT is enabled + * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if End Of Transfer IT is enabled + * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TXTF IT is enabled + * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Underrun IT is enabled + * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Overrun IT is enabled + * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if CRC Error IT is enabled + * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled + * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if MODF IT is enabled + * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TSER reload IT is enabled + * @rmtoll IER TSERFIE LL_SPI_IsEnabledIT_TSER + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); +} +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->TXDR); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->RXDR); +} +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval 0..0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (*((__IO uint8_t *)&SPIx->RXDR)); +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ +#if defined (__GNUC__) + __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); + return (*spirxdr); +#else + return (*((__IO uint16_t *)&SPIx->RXDR)); +#endif /* __GNUC__ */ +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData32 + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) +{ + return (*((__IO uint32_t *)&SPIx->RXDR)); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData 0..0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + *((__IO uint8_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); + *spitxdr = TxData; +#else + *((__IO uint16_t *)&SPIx->TXDR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData32 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) +{ + *((__IO uint32_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Set polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPOLY, CRCPoly); +} + +/** + * @brief Get polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPOLY)); +} + +/** + * @brief Set the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern + * @param SPIx SPI Instance + * @param Pattern 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern) +{ + WRITE_REG(SPIx->UDRDR, Pattern); +} + +/** + * @brief Get the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->UDRDR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRC)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRC)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ +/** + * @} + */ + +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions + @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas + to calculate Prescaler Linear, Parity and unitary functions + @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() + to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B (0x00000000UL) +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) +#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT) +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length + * @{ + */ +#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL) +#define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW (0x00000000UL) +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2S Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS (0x00000000UL) +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX (0x00000000UL) +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) +#define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2) +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0) +#define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level + * @{ + */ +#define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA) +#define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA) +#define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA) +#define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA) +#define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA) +#define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA) +#define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA) +#define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST) +#define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST) +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL) +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE) +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000UL /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000UL /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000UL /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100UL /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000UL /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050UL /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000UL /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025UL /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000UL /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 0UL /*!< Audio Freq not specified. Register I2SDIV = 0 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set I2S Data frame format + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat\n + * I2SCFGR DATFMT LL_I2S_SetDataFormat + * @param SPIx SPI Handle + * @param DataLength This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength); +} + +/** + * @brief Get I2S Data frame format + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat\n + * I2SCFGR DATFMT LL_I2S_GetDataFormat + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT)); +} + +/** + * @brief Set I2S Channel Length Type + * @note This feature is useful with SLAVE only + * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType + * @param SPIx SPI Handle + * @param ChannelLengthType This parameter can be one of the following values: + * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH + * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType); +} + +/** + * @brief Get I2S Channel Length Type + * @note This feature is useful with SLAVE only + * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH + * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH + */ +__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH)); +} + +/** + * @brief Invert the default polarity of WS signal + * @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV); +} + +/** + * @brief Use the default polarity of WS signal + * @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV); +} + +/** + * @brief Check if polarity of WS signal is inverted + * @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion + * @param SPIx SPI Handle + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL); +} + +/** + * @brief Set 2S Clock Polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Handle + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity); +} + +/** + * @brief Get 2S Clock Polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Handle + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S config + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Handle + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard); +} + +/** + * @brief Get I2S config + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Handle + * @retval Return value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * CR1 SPE LL_I2S_Enable + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable I2S peripheral and disable I2S mode + * @rmtoll CR1 SPE LL_I2S_Disable\n + * I2SCFGR I2SMOD LL_I2S_Disable + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); +} + +/** + * @brief Swap the SDO and SDI pin + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIOSwap(SPIx); +} + +/** + * @brief Restore default function for SDO and SDI pin + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIOSwap(SPIx); +} + +/** + * @brief Check if SDO and SDI pin are swapped + * @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIOSwap(SPIx); +} + +/** + * @brief Enable GPIO control + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableGPIOControl(SPIx); +} + +/** + * @brief Disable GPIO control + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableGPIOControl(SPIx); +} + +/** + * @brief Check if GPIO control is active + * @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledGPIOControl(SPIx); +} + +/** + * @brief Lock the AF configuration of associated IOs + * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs. + * The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. + * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIOLock(SPIx); +} + +/** + * @brief Check if the the SPI_CFG2 register is locked + * @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIOLock(SPIx); +} + +/** + * @brief Set Transfer Bit Order + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_I2S_LSB_FIRST + * @arg @ref LL_I2S_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + LL_SPI_SetTransferBitOrder(SPIx, BitOrder); +} +/** + * @brief Get Transfer Bit Order + * @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_LSB_FIRST + * @arg @ref LL_I2S_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx) +{ + return LL_SPI_GetTransferBitOrder(SPIx); +} + +/** + * @brief Start effective transfer on wire + * @rmtoll CR1 CSTART LL_I2S_StartTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx) +{ + LL_SPI_StartMasterTransfer(SPIx); +} + +/** + * @brief Check if there is an unfinished transfer + * @rmtoll CR1 CSTART LL_I2S_IsTransferActive + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveMasterTransfer(SPIx); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event + * @note This configuration can not be changed when I2S is enabled. + * @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_I2S_FIFO_TH_01DATA + * @arg @ref LL_I2S_FIFO_TH_02DATA + * @arg @ref LL_I2S_FIFO_TH_03DATA + * @arg @ref LL_I2S_FIFO_TH_04DATA + * @arg @ref LL_I2S_FIFO_TH_05DATA + * @arg @ref LL_I2S_FIFO_TH_06DATA + * @arg @ref LL_I2S_FIFO_TH_07DATA + * @arg @ref LL_I2S_FIFO_TH_08DATA + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + LL_SPI_SetFIFOThreshold(SPIx, Threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event + * @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_FIFO_TH_01DATA + * @arg @ref LL_I2S_FIFO_TH_02DATA + * @arg @ref LL_I2S_FIFO_TH_03DATA + * @arg @ref LL_I2S_FIFO_TH_04DATA + * @arg @ref LL_I2S_FIFO_TH_05DATA + * @arg @ref LL_I2S_FIFO_TH_06DATA + * @arg @ref LL_I2S_FIFO_TH_07DATA + * @arg @ref LL_I2S_FIFO_TH_08DATA + */ +__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx) +{ + return LL_SPI_GetFIFOThreshold(SPIx); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF + * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos)); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos); +} + +/** + * @brief Enable the Master Clock Output (Pin MCK) + * @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE); +} + +/** + * @brief Disable the Master Clock Output (Pin MCK) + * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Handle + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE); +} + +/** + * @brief Check if the master clock output (Pin MCK) is enabled + * @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL); +} + +/** + * @} + */ + + +/** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if there enough data in FIFO to read a full packet + * @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXP(SPIx); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet + * @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXP(SPIx); +} + +/** + * @brief Get Underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_UDR(SPIx); +} + +/** + * @brief Get Overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get TI Frame format error flag + * @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Clear Underrun error flag + * @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_UDR(SPIx); +} + +/** + * @brief Clear Overrun error flag + * @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear Frame format error flag + * @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Rx Packet available IT + * @rmtoll IER RXPIE LL_I2S_EnableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXP(SPIx); +} + +/** + * @brief Enable Tx Packet space available IT + * @rmtoll IER TXPIE LL_I2S_EnableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXP(SPIx); +} + +/** + * @brief Enable Underrun IT + * @rmtoll IER UDRIE LL_I2S_EnableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_UDR(SPIx); +} + +/** + * @brief Enable Overrun IT + * @rmtoll IER OVRIE LL_I2S_EnableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_OVR(SPIx); +} + +/** + * @brief Enable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_FRE(SPIx); +} + +/** + * @brief Disable Rx Packet available IT + * @rmtoll IER RXPIE LL_I2S_DisableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXP(SPIx); +} + +/** + * @brief Disable Tx Packet space available IT + * @rmtoll IER TXPIE LL_I2S_DisableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXP(SPIx); +} + +/** + * @brief Disable Underrun IT + * @rmtoll IER UDRIE LL_I2S_DisableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_UDR(SPIx); +} + +/** + * @brief Disable Overrun IT + * @rmtoll IER OVRIE LL_I2S_DisableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_OVR(SPIx); +} + +/** + * @brief Disable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_FRE(SPIx); +} + +/** + * @brief Check if Rx Packet available IT is enabled + * @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXP(SPIx); +} + +/** + * @brief Check if Tx Packet space available IT is enabled + * @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXP(SPIx); +} + +/** + * @brief Check if Underrun IT is enabled + * @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_UDR(SPIx); +} + +/** + * @brief Check if Overrun IT is enabled + * @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_OVR(SPIx); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled + * @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_I2S_ReceiveData32 + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData32(SPIx); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_I2S_TransmitData32 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) +{ + LL_SPI_TransmitData32(SPIx, TxData); +} + + +/** + * @} + */ + + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_SPI_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h new file mode 100644 index 0000000..aa5149a --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h @@ -0,0 +1,2442 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_LL_SYSTEM_H +#define __STM32H7xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ +/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status + * @{ + */ +#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT 0x10000U +#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT 0x20000U +#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT 0x40000U +#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT 0x80000U +#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT 0x100000U +#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT 0x200000U +#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT 0x400000U +#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT 0x800000U +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status + * @{ + */ +#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT 0x10000U +#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT 0x20000U +#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT 0x40000U +#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT 0x80000U +#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT 0x100000U +#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT 0x200000U +#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT 0x400000U +#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT 0x800000U +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ +#if defined(I2C5) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 SYSCFG_PMCR_I2C5_FMP /*!< Enable Fast Mode Plus for I2C5 */ +#endif /*I2C5*/ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control +* @{ +*/ +#if defined(SYSCFG_PMCR_BOOSTEN) +#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN SYSCFG_PMCR_BOOSTEN /*!< I/O analog switch voltage booster enable */ +#endif /*SYSCFG_PMCR_BOOSTEN*/ +#define LL_SYSCFG_ANALOG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< PA0 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< PA1 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< PC2 Switch Open */ +#define LL_SYSCFG_ANALOG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< PC3 Switch Open */ +/** + * @} + */ + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection +* @{ +*/ +#define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */ +#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */ +/** + * @} + */ +#endif /* SYSCFG_PMCR_EPIS_SEL */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ +#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ +#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ +#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ +#endif /*GPIOI*/ +#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ +#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 ((0x000FUL << 16U) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 ((0x00F0UL << 16U) | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 ((0x0F00UL << 16U) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 ((0xF000UL << 16U) | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 ((0x000FUL << 16U) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 ((0x00F0UL << 16U) | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 ((0x0F00UL << 16U) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 ((0xF000UL << 16U) | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 ((0x000FUL << 16U) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 ((0x00F0UL << 16U) | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 ((0x0F00UL << 16U) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 ((0xF000UL << 16U) | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 ((0x000FUL << 16U) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 ((0x00F0UL << 16U) | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 ((0x0F00UL << 16U) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 ((0xF000UL << 16U) | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC SYSCFG_CFGR_ITCML /*!< Enables and locks the ITCM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC SYSCFG_CFGR_DTCML /*!< Enables and locks the DTCM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC SYSCFG_CFGR_SRAM1L /*!< Enables and locks the SRAM1 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC SYSCFG_CFGR_SRAM2L /*!< Enables and locks the SRAM2 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#if defined(SYSCFG_CFGR_SRAM3L) +#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC SYSCFG_CFGR_SRAM3L /*!< Enables and locks the SRAM3 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ +#endif /*SYSCFG_CFGR_SRAM3L*/ + +#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC SYSCFG_CFGR_SRAM4L /*!< Enables and locks the SRAM4 double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC SYSCFG_CFGR_BKRAML /*!< Enables and locks the BKRAM double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP SYSCFG_CFGR_CM7L /*!< Enables and locks the Cortex-M7 LOCKUP signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC SYSCFG_CFGR_FLASHL /*!< Enables and locks the FLASH double ECC error signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ + +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR_PVDL /*!< Enables and locks the PVD connection + with TIM1/8/15/16/17 and HRTIM Break Input + and also the PVDE and PLS bits of the Power Control Interface */ +#if defined(DUAL_CORE) +#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP SYSCFG_CFGR_CM4L /*!< Enables and locks the Cortex-M4 LOCKUP signal + with Break Input of TIM1/8/15/16/17 and HRTIM */ +#endif /* DUAL_CORE */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_CELL_CODE 0U +#define LL_SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS +/** + * @} + */ + +/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes + * @{ + */ +#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE 0U +#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE SYSCFG_UR11_IWDG1M +/** + * @} + */ + +#if defined (DUAL_CORE) +/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes + * @{ + */ +#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE 0U +#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE SYSCFG_UR12_IWDG2M +/** + * @} + */ +#endif /* DUAL_CORE */ + +/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration + * @{ + */ +#define LL_SYSCFG_DTCM_RAM_SIZE_2KB 0U +#define LL_SYSCFG_DTCM_RAM_SIZE_4KB 1U +#define LL_SYSCFG_DTCM_RAM_SIZE_8KB 2U +#define LL_SYSCFG_DTCM_RAM_SIZE_16KB 3U +/** + * @} + */ +#ifdef SYSCFG_UR17_TCM_AXI_CFG +/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package + * @{ + */ +#define LL_SYSCFG_ITCM_AXI_64KB_320KB 0U +#define LL_SYSCFG_ITCM_AXI_128KB_256KB 1U +#define LL_SYSCFG_ITCM_AXI_192KB_192KB 2U +#define LL_SYSCFG_ITCM_AXI_256KB_128KB 3U +/** + * @} + */ +#endif /* #ifdef SYSCFG_UR17_TCM_AXI_CFG */ +#if defined(SYSCFG_PKGR_PKG) +/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package + * @{ + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define LL_SYSCFG_LQFP100_PACKAGE 0U +#define LL_SYSCFG_TQFP144_PACKAGE 2U +#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE 5U +#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE 8U +#elif (STM32H7_DEV_ID == 0x483UL) +#define LL_SYSCFG_VFQFPN68_INDUS_PACKAGE 0U +#define LL_SYSCFG_TFBGA100_LQFP100_PACKAGE 1U +#define LL_SYSCFG_LQFP100_INDUS_PACKAGE 2U +#define LL_SYSCFG_TFBGA100_INDUS_PACKAGE 3U +#define LL_SYSCFG_WLCSP115_INDUS_PACKAGE 4U +#define LL_SYSCFG_LQFP144_PACKAGE 5U +#define LL_SYSCFG_UFBGA144_PACKAGE 6U +#define LL_SYSCFG_LQFP144_INDUS_PACKAGE 7U +#define LL_SYSCFG_UFBGA169_INDUS_PACKAGE 8U +#define LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE 9U +#define LL_SYSCFG_LQFP176_INDUS_PACKAGE 10U +#endif /* STM32H7_DEV_ID == 0x450UL */ +/** + * @} + */ +#endif /* SYSCFG_PKGR_PKG */ + +/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level + * @{ + */ +#define LL_SYSCFG_BOR_OFF_RESET_LEVEL 0x00000000U +#define LL_SYSCFG_BOR_LOW_RESET_LEVEL SYSCFG_UR2_BORH_0 +#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL SYSCFG_UR2_BORH_1 +#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL SYSCFG_UR2_BORH + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2 /*!< TIM2 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3 /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4 /*!< TIM4 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5 /*!< TIM5 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6 /*!< TIM6 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7 /*!< TIM7 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12 /*!< TIM12 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13 /*!< TIM13 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14 /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1 /*!< LPTIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1 /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2 /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3 /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#if defined(I2C5) +#define LL_DBGMCU_APB1_GRP1_I2C5_STOP DBGMCU_APB1LFZ1_DBG_I2C5 /*!< I2C5 SMBUS timeout mode stopped when Core is halted */ +#endif /*I2C5*/ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) +#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN /*!< FDCAN is frozen while the core is in debug mode */ +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ +#if defined(TIM23) +#define LL_DBGMCU_APB1_GRP2_TIM23_STOP DBGMCU_APB1HFZ1_DBG_TIM23 /*!< TIM23 is frozen while the core is in debug mode */ +#endif /*TIM23*/ +#if defined(TIM24) +#define LL_DBGMCU_APB1_GRP2_TIM24_STOP DBGMCU_APB1HFZ1_DBG_TIM24 /*!< TIM24 is frozen while the core is in debug mode */ +#endif /*TIM24*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1 /*!< TIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8 /*!< TIM8 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15 /*!< TIM15 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16 /*!< TIM16 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17 /*!< TIM17 counter stopped when core is halted */ +#if defined(HRTIM1) +#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP DBGMCU_APB2FZ1_DBG_HRTIM /*!< HRTIM counter stopped when core is halted */ +#endif /*HRTIM1*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP DBGMCU_APB3FZ1_DBG_WWDG1 /*!< WWDG1 is frozen while the core is in debug mode */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4 /*!< I2C4 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2 /*!< LPTIM2 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3 /*!< LPTIM3 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4 /*!< LPTIM4 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5 /*!< LPTIM5 is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC /*!< RTC is frozen while the core is in debug mode */ +#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP DBGMCU_APB4FZ1_DBG_IWDG1 /*!< IWDG1 is frozen while the core is in debug mode */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** + * @brief Select Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SYSCFG_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ETH_MII + * @arg @ref LL_SYSCFG_ETH_RMII + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll PMCR EPIS_SEL LL_SYSCFG_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ETH_MII + * @arg @ref LL_SYSCFG_ETH_RMII + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL)); +} + +#endif /* SYSCFG_PMCR_EPIS_SEL */ +/** + * @brief Open an Analog Switch + * @rmtoll PMCR PA0SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PA1SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PC2SO LL_SYSCFG_OpenAnalogSwitch + * @rmtoll PMCR PC3SO LL_SYSCFG_OpenAnalogSwitch + * @param AnalogSwitch This parameter can be one of the following values: + * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch) +{ + SET_BIT(SYSCFG->PMCR, AnalogSwitch); +} + +/** + * @brief Close an Analog Switch + * @rmtoll PMCR PA0SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PA1SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PC2SO LL_SYSCFG_CloseAnalogSwitch + * @rmtoll PMCR PC3SO LL_SYSCFG_CloseAnalogSwitch + * @param AnalogSwitch This parameter can be one of the following values: + * @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PA1: PA1 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch + * @arg LL_SYSCFG_ANALOG_SWITCH_PC3: PC3 analog switch + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch) +{ + CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch); +} +#ifdef SYSCFG_PMCR_BOOSTEN +/** + * @brief Enable the Analog booster to reduce the total harmonic distortion + * of the analog switch when the supply voltage is lower than 2.7 V + * @rmtoll PMCR BOOSTEN LL_SYSCFG_EnableAnalogBooster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) +{ + SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} + +/** + * @brief Disable the Analog booster + * @rmtoll PMCR BOOSTEN LL_SYSCFG_DisableAnalogBooster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} +#endif /*SYSCFG_PMCR_BOOSTEN*/ +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->PMCR, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMCR I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_PMCR I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI (*) + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U)); +} + +/** + * @brief Set connections to TIM1/8/15/16/17 and HRTIM Break inputs + * @note this feature is available on STM32H7 rev.B and above + * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR ITCML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR DTCML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM1L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM2L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM3L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR SRAM4L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR BKRAML LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR CM7L LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR FLASHL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR PVDL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR_CM4L LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) + * @retval None + * (*) value not defined in all devices + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L, Break); +#elif defined(SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM3L | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL, Break); +#elif defined(SYSCFG_CFGR_AXISRAML) + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL,\ + Break); +#else + MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML |\ + SYSCFG_CFGR_CM7L | SYSCFG_CFGR_FLASHL | \ + SYSCFG_CFGR_PVDL, Break); +#endif /* DUAL_CORE */ +} + +/** + * @brief Get connections to TIM1/8/15/16/17 and HRTIM Break inputs + * @note this feature is available on STM32H7 rev.B and above + * @rmtoll SYSCFG_CFGR AXISRAML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR ITCML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR DTCML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM1L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM2L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM3L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR SRAM4L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR BKRAML LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR CM7L LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR FLASHL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR PVDL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR_CM4L LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC (*) + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only) + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ +#if defined(DUAL_CORE) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL | SYSCFG_CFGR_CM4L)); +#elif defined (SYSCFG_CFGR_AXISRAML) && defined(SYSCFG_CFGR_SRAM3L) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#elif defined (SYSCFG_CFGR_AXISRAML) + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | \ + SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \ + SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#else + return (uint32_t)(READ_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML | SYSCFG_CFGR_DTCML | SYSCFG_CFGR_CM7L | \ + SYSCFG_CFGR_FLASHL | SYSCFG_CFGR_PVDL )); +#endif /* DUAL_CORE */ +} + +/** + * @brief Enable the Compensation Cell + * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + +/** + * @brief Disable the Compensation Cell + * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + +/** + * @brief Check if the Compensation Cell is enabled + * @rmtoll CCCSR EN LL_SYSCFG_IsEnabledCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag + * @rmtoll CCCSR READY LL_SYSCFG_IsActiveFlag_CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV1 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV2 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); +} + +/** + * @brief Enable the I/O speed optimization when the product voltage is low. + * @rmtoll CCCSR HSLV3 LL_SYSCFG_EnableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV1 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1); +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV2 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2); +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @rmtoll CCCSR HSLV3 LL_SYSCFG_DisableIOSpeedOptimize + * @note This bit is active only if IO_HSLV user option bit is set. It must be used only if the + * product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V + * might be destructive. + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL); +#else + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL); +#endif /*SYSCFG_CCCSR_HSLV*/ +} + +#if defined(SYSCFG_CCCSR_HSLV1) +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV1 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL); +} + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV2 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL); +} + +/** + * @brief Check if the I/O speed optimization is enabled + * @rmtoll CCCSR HSLV3 LL_SYSCFG_IsEnabledIOSpeedOptimization + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL); +} +#endif /*SYSCFG_CCCSR_HSLV1*/ + +/** + * @brief Set the code selection for the I/O Compensation cell + * @rmtoll CCCSR CS LL_SYSCFG_SetCellCompensationCode + * @param CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} + +/** + * @brief Get the code selected for the I/O Compensation cell + * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS)); +} + +#ifdef SYSCFG_CCCSR_CS_MMC + +/** + * @brief Get the code selected for the I/O Compensation cell on the VDDMMC power rail + * @rmtoll CCCSR CS LL_SYSCFG_GetCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC)); +} +#endif /*SYSCFG_CCCSR_CS_MMC*/ + +/** + * @brief Get I/O compensation cell value for PMOS transistors + * @rmtoll CCVR PCV LL_SYSCFG_GetPMOSCompensationValue + * @retval Returned value is the I/O compensation cell value for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV)); +} + +/** + * @brief Get I/O compensation cell value for NMOS transistors + * @rmtoll CCVR NCV LL_SYSCFG_GetNMOSCompensationValue + * @retval Returned value is the I/O compensation cell value for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV)); +} + +/** + * @brief Set I/O compensation cell code for PMOS transistors + * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode); +} + +/** + * @brief Get I/O compensation cell code for PMOS transistors + * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC)); +} + +#ifdef SYSCFG_CCCR_PCC_MMC + +/** + * @brief Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail + * @rmtoll CCCR PCC LL_SYSCFG_SetPMOSCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode); +} + +/** + * @brief Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail + * @rmtoll CCCR PCC LL_SYSCFG_GetPMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for PMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC)); +} +#endif /* SYSCFG_CCCR_PCC_MMC */ + +/** + * @brief Set I/O compensation cell code for NMOS transistors + * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode); +} + +/** + * @brief Get I/O compensation cell code for NMOS transistors + * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC)); +} + +#ifdef SYSCFG_CCCR_NCC_MMC + +/** + * @brief Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail. + * @rmtoll CCCR NCC LL_SYSCFG_SetNMOSCompensationCode + * @param NMOSCode: NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode); +} + +/** + * @brief Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail. + * @rmtoll CCCR NCC LL_SYSCFG_GetNMOSCompensationCode + * @retval Returned value is the I/O compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC)); +} +#endif /*SYSCFG_CCCR_NCC_MMC*/ + +#ifdef SYSCFG_PKGR_PKG +/** + * @brief Get the device package + * @rmtoll PKGR PKG LL_SYSCFG_GetPackage + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_LQFP100_PACKAGE (*) + * @arg @ref LL_SYSCFG_TQFP144_PACKAGE (*) + * @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE (*) + * @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE (*) + * @arg @ref LL_SYSCFG_VFQFPN68_INDUS_PACKAGE (*) + * @arg @ref LL_SYSCFG_TFBGA100_LQFP100_PACKAGE (*) + * @arg @ref LL_SYSCFG_LQFP100_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_TFBGA100_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_WLCSP115_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP144_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA144_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP144_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA169_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE (**) + * @arg @ref LL_SYSCFG_LQFP176_INDUS_PACKAGE (**) + * + * (*) : For stm32h74xxx and stm32h75xxx family lines. + * (**): For stm32h72xxx and stm32h73xxx family lines. + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG)); +} +#endif /*SYSCFG_PKGR_PKG*/ + +#ifdef SYSCFG_UR0_RDP +/** + * @brief Get the Flash memory protection level + * @rmtoll UR0 RDP LL_SYSCFG_GetFLashProtectionLevel + * @retval Returned value can be one of the following values: + * 0xAA : RDP level 0 + * 0xCC : RDP level 2 + * Any other value : RDP level 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP)); +} +#ifdef SYSCFG_UR0_BKS +/** + * @brief Indicate if the Flash memory bank addresses are inverted or not + * @rmtoll UR0 BKS LL_SYSCFG_IsFLashBankAddressesSwaped + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void) +{ + return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR0_BKS*/ + +/** + * @brief Get the BOR Threshold Reset Level + * @rmtoll UR2 BORH LL_SYSCFG_GetBrownoutResetLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL + * @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH)); +} +/** + * @brief BootCM7 address 0 configuration + * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_SetCM7BootAddress0 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress) +{ + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos)); +#else + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos)); +#endif /*DUAL_CORE*/ + +} + +/** + * @brief Get BootCM7 address 0 + * @rmtoll UR2 BOOT_ADD0 LL_SYSCFG_GetCM7BootAddress0 + * @retval Returned the CM7 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void) +{ + /* Get CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos); +#else + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos); +#endif /*DUAL_CORE*/ +} + +/** + * @brief BootCM7 address 1 configuration + * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_SetCM7BootAddress1 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress) +{ + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress); +#else + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress); +#endif /*DUAL_CORE*/ +} + +/** + * @brief Get BootCM7 address 1 + * @rmtoll UR3 BOOT_ADD1 LL_SYSCFG_GetCM7BootAddress1 + * @retval Returned the CM7 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void) +{ + /* Get CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1)); +#else + return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1)); +#endif /* DUAL_CORE */ +} + +#if defined(DUAL_CORE) +/** + * @brief BootCM4 address 0 configuration + * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_SetCM4BootAddress0 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress) +{ + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos)); +} + +/** + * @brief Get BootCM4 address 0 + * @rmtoll UR3 BCM4_ADD0 LL_SYSCFG_GetCM4BootAddress0 + * @retval Returned the CM4 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void) +{ + /* Get CM4 BOOT ADD0 */ + return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos); +} + +/** + * @brief BootCM4 address 1 configuration + * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_SetCM4BootAddress1 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress) +{ + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress); +} + +/** + * @brief Get BootCM4 address 1 + * @rmtoll UR4 BCM4_ADD1 LL_SYSCFG_GetCM4BootAddress1 + * @retval Returned the CM4 Boot Address0 + */ +__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void) +{ + /* Get CM4 BOOT ADD0 */ + return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1)); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Indicates if the flash protected area (Bank 1) is erased by a mass erase + * @rmtoll UR4 MEPAD_BANK1 LL_SYSCFG_IsFlashB1ProtectedAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the flash secured area (Bank 1) is erased by a mass erase + * @rmtoll UR5 MESAD_BANK1 LL_SYSCFG_IsFlashB1SecuredAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 0 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector0WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 1 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector1WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 2 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector2WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 3 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector3WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 4 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector4WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 5 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector5WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 6 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector6WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 7 of the Flash memory bank 1 is write protected + * @rmtoll UR5 WRPN_BANK1 LL_SYSCFG_IsFlashB1Sector7WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Get the protected area start address for Flash bank 1 + * @rmtoll UR6 PABEG_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress + * @retval Returned the protected area start address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1)); +} + +/** + * @brief Get the protected area end address for Flash bank 1 + * @rmtoll UR6 PAEND_BANK1 LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress + * @retval Returned the protected area end address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1)); +} + +/** + * @brief Get the secured area start address for Flash bank 1 + * @rmtoll UR7 SABEG_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaStartAddress + * @retval Returned the secured area start address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1)); +} + +/** + * @brief Get the secured area end address for Flash bank 1 + * @rmtoll UR7 SAEND_BANK1 LL_SYSCFG_GetFlashB1SecuredAreaEndAddress + * @retval Returned the secured area end address for Flash bank 1 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1)); +} + +#ifdef SYSCFG_UR8_MEPAD_BANK2 +/** + * @brief Indicates if the flash protected area (Bank 2) is erased by a mass erase + * @rmtoll UR8 MEPAD_BANK2 LL_SYSCFG_IsFlashB2ProtectedAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the flash secured area (Bank 2) is erased by a mass erase + * @rmtoll UR8 MESAD_BANK2 LL_SYSCFG_IsFlashB2SecuredAreaErasable + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void) +{ + return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR8_MEPAD_BANK2*/ + +#ifdef SYSCFG_UR9_WRPN_BANK2 +/** + * @brief Indicates if the sector 0 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector0WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 1 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector1WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 2 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector2WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 3 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector3WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 4 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector4WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 5 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector5WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 6 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector6WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the sector 7 of the Flash memory bank 2 is write protected + * @rmtoll UR9 WRPN_BANK2 LL_SYSCFG_IsFlashB2Sector7WriteProtected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void) +{ + return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL); +} + +/** + * @brief Get the protected area start address for Flash bank 2 + * @rmtoll UR9 PABEG_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress + * @retval Returned the protected area start address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2)); +} +#endif /*SYSCFG_UR9_WRPN_BANK2*/ + +#ifdef SYSCFG_UR10_PAEND_BANK2 +/** + * @brief Get the protected area end address for Flash bank 2 + * @rmtoll UR10 PAEND_BANK2 LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress + * @retval Returned the protected area end address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2)); +} + +/** + * @brief Get the secured area start address for Flash bank 2 + * @rmtoll UR10 SABEG_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaStartAddress + * @retval Returned the secured area start address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2)); +} +#endif /*SYSCFG_UR10_PAEND_BANK2*/ + +#ifdef SYSCFG_UR11_SAEND_BANK2 +/** + * @brief Get the secured area end address for Flash bank 2 + * @rmtoll UR11 SAEND_BANK2 LL_SYSCFG_GetFlashB2SecuredAreaEndAddress + * @retval Returned the secured area end address for Flash bank 2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2)); +} +#endif /*SYSCFG_UR11_SAEND_BANK2*/ + +/** + * @brief Get the Independent Watchdog 1 control mode (Software or Hardware) + * @rmtoll UR11 IWDG1M LL_SYSCFG_GetIWDG1ControlMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE + * @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M)); +} + +#if defined (DUAL_CORE) +/** + * @brief Get the Independent Watchdog 2 control mode (Software or Hardware) + * @rmtoll UR12 IWDG2M LL_SYSCFG_GetIWDG2ControlMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE + * @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M)); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicates the Secure mode status + * @rmtoll UR12 SECURE LL_SYSCFG_IsSecureModeEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void) +{ + return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL); +} + +/** + * @brief Indicates if a reset is generated when D1 domain enters DStandby mode + * @rmtoll UR13 D1SBRST LL_SYSCFG_IsD1StandbyGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Get the secured DTCM RAM size + * @rmtoll UR13 SDRS LL_SYSCFG_GetSecuredDTCMSize + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB + * @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS)); +} + +/** + * @brief Indicates if a reset is generated when D1 domain enters DStop mode + * @rmtoll UR14 D1STPRST LL_SYSCFG_IsD1StopGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL); +} + +#if defined (DUAL_CORE) +/** + * @brief Indicates if a reset is generated when D2 domain enters DStandby mode + * @rmtoll UR14 D2SBRST LL_SYSCFG_IsD2StandbyGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if a reset is generated when D2 domain enters DStop mode + * @rmtoll UR15 D2STPRST LL_SYSCFG_IsD2StopGenerateReset + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void) +{ + return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL); +} +#endif /* DUAL_CORE */ + +/** + * @brief Indicates if the independent watchdog is frozen in Standby mode + * @rmtoll UR15 FZIWDGSTB LL_SYSCFG_IsIWDGFrozenInStandbyMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void) +{ + return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the independent watchdog is frozen in Stop mode + * @rmtoll UR16 FZIWDGSTP LL_SYSCFG_IsIWDGFrozenInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void) +{ + return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the device private key is programmed + * @rmtoll UR16 PKP LL_SYSCFG_IsPrivateKeyProgrammed + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void) +{ + return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL); +} + +/** + * @brief Indicates if the Product is working on the full voltage range or not + * @rmtoll UR17 IOHSLV LL_SYSCFG_IsActiveFlag_IOHSLV + * @note When the IOHSLV option bit is set the Product is working below 2.7 V. + * When the IOHSLV option bit is reset the Product is working on the + * full voltage range. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void) +{ + return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL); +} + +#ifdef SYSCFG_UR17_TCM_AXI_CFG +/** + * @brief Get the size of ITCM-RAM and AXI-SRAM + * @rmtoll UR17 TCM_AXI_CFG LL_SYSCFG_Get_ITCM_AXI_RAM_Size + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ITCM_AXI_64KB_320KB + * @arg @ref LL_SYSCFG_ITCM_AXI_128KB_256KB + * @arg @ref LL_SYSCFG_ITCM_AXI_192KB_192KB + * @arg @ref LL_SYSCFG_ITCM_AXI_256KB_128KB + */ +__STATIC_INLINE uint32_t LL_SYSCFG_Get_ITCM_AXI_RAM_Size(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->UR17, SYSCFG_UR17_TCM_AXI_CFG)); +} +#endif /*SYSCFG_UR17_TCM_AXI_CFG*/ + +#ifdef SYSCFG_UR18_CPU_FREQ_BOOST +/** + * @brief Indicates if the CPU maximum frequency boost is enabled + * @rmtoll UR18 CPU_FREQ_BOOST LL_SYSCFG_IsCpuFreqBoostEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsCpuFreqBoostEnabled(void) +{ + return ((READ_BIT(SYSCFG->UR18, SYSCFG_UR18_CPU_FREQ_BOOST) == SYSCFG_UR18_CPU_FREQ_BOOST) ? 1UL : 0UL); +} +#endif /*SYSCFG_UR18_CPU_FREQ_BOOST*/ + +#endif /*SYSCFG_UR0_RDP*/ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable D1 Domain/CDomain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Enable D1 Domain/CDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Enable D1 Domain/CDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_EnableD1DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +/** + * @brief Disable D1 Domain/CDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D1/DBGSLEEP_CD LL_DBGMCU_DisableD1DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +#if defined (DUAL_CORE) +/** + * @brief Enable D2 Domain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_EnableD2DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Disable D2 Domain debug during SLEEP mode + * @rmtoll DBGMCU_CR DBGSLEEP_D2 LL_DBGMCU_DisableD2DebugInSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Enable D2 Domain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_EnableD2DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Disable D2 Domain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D2 LL_DBGMCU_DisableD2DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Enable D2 Domain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_EnableD2DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} + +/** + * @brief Disable D2 Domain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D2 LL_DBGMCU_DisableD2DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} +#endif /* DUAL_CORE */ + + +#if defined(DBGMCU_CR_DBG_STOPD3) +/** + * @brief Enable D3 Domain/SRDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} + +/** + * @brief Disable D3 Domain/SRDomain debug during STOP mode + * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_DisableD3DebugInStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} +#endif /*DBGMCU_CR_DBG_STOPD3*/ + +#if defined(DBGMCU_CR_DBG_STANDBYD3) +/** + * @brief Enable D3 Domain/SRDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} + +/** + * @brief Disable D3 Domain/SRDomain debug during STANDBY mode + * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_DisableD3DebugInStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ + +/** + * @brief Enable the trace port clock + * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_EnableTracePortClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); +} + +/** + * @brief Disable the trace port clock + * @rmtoll DBGMCU_CR TRACECKEN LL_DBGMCU_DisableTracePortClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN); +} + +/** + * @brief Enable the Domain1/CDomain debug clock enable + * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_EnableD1DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); +} + +/** + * @brief Disable the Domain1/CDomain debug clock enable + * @rmtoll DBGMCU_CR CKD1EN/CKCDEN LL_DBGMCU_DisableD1DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN); +} + +/** + * @brief Enable the Domain3/SRDomain debug clock enable + * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_EnableD3DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); +} + +/** + * @brief Disable the Domain3/SRDomain debug clock enable + * @rmtoll DBGMCU_CR CKD3EN/CKSRDEN LL_DBGMCU_DisableD3DebugClock + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN); +} + +#define LL_DBGMCU_TRGIO_INPUT_DIRECTION 0U +#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION DBGMCU_CR_DBG_TRGOEN +/** + * @brief Set the direction of the bi-directional trigger pin TRGIO + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_SetExternalTriggerPinDirection\n + * @param PinDirection This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION + * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection); +} + +/** + * @brief Get the direction of the bi-directional trigger pin TRGIO + * @rmtoll DBGMCU_CR TRGOEN LL_DBGMCU_GetExternalTriggerPinDirection\n + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION + * @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN)); +} + +/** + * @brief Freeze APB1 group1 peripherals + * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n (*) + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1LFZ1 TIM2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM4 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM6 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM7 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM12 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM13 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 TIM14 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 LPTIM1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C1 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C2 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C3 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1LFZ1 I2C5 LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C5_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs); +} + +#ifdef DBGMCU_APB1HFZ1_DBG_FDCAN +/** + * @brief Freeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 FDCAN LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} +#endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ + +#if defined(TIM23) || defined(TIM24) +/** + * @brief Freeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1HFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 group2 peripherals + * @rmtoll DBGMCU_APB1HFZ1 TIM23 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + DBGMCU_APB1HFZ1 TIM24 LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM23_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM24_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs); +} +#endif /* TIM23 || TIM24 */ + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph + * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ1 TIM1 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM8 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM15 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM16 LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2FZ1 TIM17 LL_DBGMCU_APB2_GRP1_FreezePeriph + * DBGMCU_APB2FZ1 HRTIM LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ1, Periphs); +} + +/** + * @brief Freeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB3FZ1, Periphs); +} + +/** + * @brief Unfreeze APB3 peripherals + * @rmtoll DBGMCU_APB3FZ1 WWDG1 LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB3FZ1, Periphs); +} + +/** + * @brief Freeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB4FZ1, Periphs); +} + +/** + * @brief Unfreeze APB4 peripherals + * @rmtoll DBGMCU_APB4FZ1 I2C4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM2 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM3 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM4 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 LPTIM5 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 RTC LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @rmtoll DBGMCU_APB4FZ1 WDGLSD1 LL_DBGMCU_APB4_GRP1_FreezePeriph\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP (*) + * @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB4FZ1, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EF_ART ART + * @{ + */ + +/** + * @brief Enable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Enable + * @retval None + */ +__STATIC_INLINE void LL_ART_Enable(void) +{ + SET_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Disable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Disable + * @retval None + */ +__STATIC_INLINE void LL_ART_Disable(void) +{ + CLEAR_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Check if the Cortex-M4 ART cache is enabled + * @rmtoll ART_CTR EN LL_ART_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ART_IsEnabled(void) +{ + return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL); +} + +/** + * @brief Set the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress + * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache. + * @retval None + */ +__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress) +{ + MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL)); +} + +/** + * @brief Get the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress + * @retval the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache + */ +__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void) +{ + return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U); +} +#endif /* DUAL_CORE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_SYSTEM_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h new file mode 100644 index 0000000..f68a4e0 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h @@ -0,0 +1,5209 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32H7xx_LL_TIM_H +#define __STM32H7xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x3CU, /* 7: TIMx_CH5 */ + 0x3CU /* 8: TIMx_CH6 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: OC5M, OC5FE, OC5PE */ + 8U /* 8: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U /* 8: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 16U, /* 7: CC5P */ + 20U /* 8: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 8U, /* 7: OIS5 */ + 10U /* 8: OIS6 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +#if defined(TIM_BREAK_INPUT_SUPPORT) +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + +/* Generic bit definitions for TIMx_AF1 register */ +#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ +#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + +#if defined(TIM_BDTR_BKBID) + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + +#endif /*TIM_BDTR_BKBID */ + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + +#if defined(TIM_BDTR_BKBID) + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + +#endif /*TIM_BDTR_BKBID */ + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_ITR4 + * @arg @ref LL_TIM_TS_ITR5 + * @arg @ref LL_TIM_TS_ITR6 + * @arg @ref LL_TIM_TS_ITR7 + * @arg @ref LL_TIM_TS_ITR8 (*) + * @arg @ref LL_TIM_TS_ITR9 (*) + * @arg @ref LL_TIM_TS_ITR10 (*) + * @arg @ref LL_TIM_TS_ITR11 (*) + * @arg @ref LL_TIM_TS_ITR12 (*) + * @arg @ref LL_TIM_TS_ITR13 (*) + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * + * (*) Value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @brief Select the external trigger (ETR) input source. + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports ETR source selection. + * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource + * @param TIMx Timer instance + * @param ETRSource This parameter can be one of the following values: + * For TIM1, the parameter is one of the following values: + * @arg LL_TIM_TIM1_ETRSOURCE_GPIO: TIM1_ETR is connected to GPIO + * @arg LL_TIM_TIM1_ETRSOURCE_COMP1: TIM1_ETR is connected to COMP1 output + * @arg LL_TIM_TIM1_ETRSOURCE_COMP2: TIM1_ETR is connected to COMP2 output + * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 + * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 + * @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 + * + * For TIM2, the parameter is one of the following values: + * @arg LL_TIM_TIM2_ETRSOURCE_GPIO: TIM2_ETR is connected to GPIO + * @arg LL_TIM_TIM2_ETRSOURCE_COMP1: TIM2_ETR is connected to COMP1 output + * @arg LL_TIM_TIM2_ETRSOURCE_COMP2: TIM2_ETR is connected to COMP2 output + * @arg LL_TIM_TIM2_ETRSOURCE_LSE: TIM2_ETR is connected to LSE + * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A + * @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B + * + * For TIM3, the parameter is one of the following values: + * @arg LL_TIM_TIM3_ETRSOURCE_GPIO: TIM3_ETR is connected to GPIO + * @arg LL_TIM_TIM3_ETRSOURCE_COMP1: TIM3_ETR is connected to COMP1 output + * + * For TIM5, the parameter is one of the following values: + * @arg LL_TIM_TIM5_ETRSOURCE_GPIO: TIM5_ETR is connected to GPIO + * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * + * For TIM8, the parameter is one of the following values: + * @arg LL_TIM_TIM8_ETRSOURCE_GPIO: TIM8_ETR is connected to GPIO + * @arg LL_TIM_TIM8_ETRSOURCE_COMP1: TIM8_ETR is connected to COMP1 output + * @arg LL_TIM_TIM8_ETRSOURCE_COMP2: TIM8_ETR is connected to COMP2 output + * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 + * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 + * @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 + * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 + * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 + * @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 + * + * For TIM23, the parameter is one of the following values: (*) + * @arg LL_TIM_TIM23_ETRSOURCE_GPIO TIM23_ETR is connected to GPIO + * @arg LL_TIM_TIM23_ETRSOURCE_COMP1 TIM23_ETR is connected to COMP1 output + * @arg LL_TIM_TIM23_ETRSOURCE_COMP2 TIM23_ETR is connected to COMP2 output + * + * For TIM24, the parameter is one of the following values: (*) + * @arg LL_TIM_TIM24_ETRSOURCE_GPIO TIM24_ETR is connected to GPIO + * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A + * @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B + * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A + * @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B + * + * (*) Value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) +{ + MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +#if defined(TIM_BDTR_BKBID) +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK\n + * BDTR BKBID LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param BreakAFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); +} + +#else +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, + uint32_t BreakFilter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); +} + +#endif /* TIM_BDTR_BKBID */ +#if defined(TIM_BDTR_BKBID) +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Re-arm the break input (when it operates in bidirectional mode). + * @note The Break input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +#endif /*TIM_BDTR_BKBID */ +/** + * @brief Enable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Disable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +#if defined(TIM_BDTR_BKBID) +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2\n + * BDTR BK2BID LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param Break2AFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); +} + +#else +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); +} + +#endif /*TIM_BDTR_BKBID */ +#if defined(TIM_BDTR_BKBID) +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Re-arm the break 2 input (when it operates in bidirectional mode). + * @note The Break 2 input is automatically armed as soon as MOE bit is set. + * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +#endif /*TIM_BDTR_BKBID */ +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +#if defined(TIM_BREAK_INPUT_SUPPORT) +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n + * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n + * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n + * AF1 BKDF1BK0E LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n + * AF2 BK2DF1BK1E LL_TIM_EnableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + SET_BIT(*pReg, Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n + * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n + * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n + * AF1 BKDF1BK0E LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n + * AF2 BK2DF1BK1E LL_TIM_DisableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); +} +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL + * + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * TIM1: one of the following values: + * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO + * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output + * + * TIM2: one of the following values: + * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO + * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output + * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output + * @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output + * + * TIM3: one of the following values: + * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO + * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output + * @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output + * + * TIM5: one of the following values: + * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO + * @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP: TIM5 TI1 is connected to CAN TMP + * @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP: TIM5 TI1 is connected to CAN RTP + * + * TIM8: one of the following values: + * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO + * @arg LL_TIM_TIM8_TI1_RMP_COMP2: TIM8 TI1 is connected to COMP2 output + * + * TIM12: one of the following values: (*) + * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO + * @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS + * + * TIM15: one of the following values: + * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO + * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2 CH1 + * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3 CH1 + * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4 CH1 + * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE + * @arg LL_TIM_TIM15_TI1_RMP_CSI: TIM15 TI1 is connected to CSI + * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2 + * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI2 is connected to GPIO + * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI2 is connected to TIM2 CH2 + * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI2 is connected to TIM3 CH2 + * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI2 is connected to TIM4 CH2 + * + * TIM16: one of the following values: + * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO + * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI + * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE + * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC wakeup interrupt + * + * TIM17: one of the following values: + * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO + * @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*) + * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz + * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1 + * + * TIM23: one of the following values: (*) + * @arg LL_TIM_TIM23_TI4_RMP_GPIO TIM23_TI4 is connected to GPIO + * @arg LL_TIM_TIM23_TI4_RMP_COMP1 TIM23_TI4 is connected to COMP1 output + * @arg LL_TIM_TIM23_TI4_RMP_COMP2 TIM23_TI4 is connected to COMP2 output + * @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output + * + * TIM24: one of the following values: (*) + * @arg LL_TIM_TIM24_TI1_RMP_GPIO TIM24_TI1 is connected to GPIO + * @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM24_TI1 is connected to CAN_TMP + * @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM24_TI1 is connected to CAN_RTP + * @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC TIM24_TI1 is connected to CAN_SOC + * + * (*) Value not defined in all devices. \n + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32H7xx_LL_TIM_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h new file mode 100644 index 0000000..8494c35 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h @@ -0,0 +1,4400 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_USART_H +#define STM32H7xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_SetWKUPType + * @param USARTx USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_GetWKUPType + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_USART_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h new file mode 100644 index 0000000..59599bf --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h @@ -0,0 +1,558 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_usb.h + * @author MCD Application Team + * @brief Header file of USB Low Layer HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_USB_H +#define STM32H7xx_LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief USB Mode definition + */ + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_ACK, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_HCStateTypeDef; + + +/** + * @brief USB Instance Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + + uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + + uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + +} USB_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +} USB_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + + uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t XferSize; /*!< OTG Channel transfer size. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ + + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; + +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type + * @{ + */ +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + + +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup); +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32H7xx_LL_USB_H */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h new file mode 100644 index 0000000..635ea59 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_utils.h @@ -0,0 +1,401 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_LL_UTILS_H +#define STM32H7xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx.h" +#include "stm32h7xx_ll_system.h" +#include "stm32h7xx_ll_bus.h" + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetM(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetN(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 128 + odd division factors are not allowed + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetP(). */ + + uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO. + This parameter can be a value between 0 and 8191 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetFRACN(). */ + + uint32_t VCO_Input; /*!< PLL clock Input range. + This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOInputRange(). */ + + uint32_t VCO_Output; /*!< PLL clock Output range. + This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_SetVCOOutputRange(). */ + +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output. + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetSysPrescaler(). */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_AHB_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB3CLKDivider; /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB3_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB3Prescaler(). */ + + uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB4_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB4Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE /*!< TQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL /*!< LQFP64 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL /*!< TFBGA100 or LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL /*!< LQFP100 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL /*!< TFBGA100 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL /*!< WLCSP132 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */ +#elif (STM32H7_DEV_ID == 0x483UL) +#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE /*!< VFQFPN68 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE /*!< TFBGA100 or LQFP100 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE /*!< LQFP100 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE /*!< TFBGA100 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE /*!< WLCSP115 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE /*!< LQFP144 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE /*!< UFBGA144 Legacy package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE /*!< LQFP144 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE /*!< UFBGA169 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE /*!< UFBGA176+25 Industrial package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE /*!< LQFP176 Industrial package type */ +#endif /* STM32H7_DEV_ID == 0x450UL */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP144 + * @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS (*) + * + * (*) Packages available on some STM32H7 lines only. + * @note For some SM32H7 lines, enabling the SYSCFG clock is mandatory. + the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ +#if defined(SYSCFG_PKGR_PKG) + + return LL_SYSCFG_GetPackage(); +#else + return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS))); + +#endif /* SYSCFG_PKGR_PKG */ +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t CPU_Frequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t CPU_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, + uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_LL_UTILS_H */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt b/FW/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt new file mode 100644 index 0000000..3edc4d1 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c new file mode 100644 index 0000000..cd71d08 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -0,0 +1,1311 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** + * @brief STM32H7xx HAL Driver version number V1.11.1 + */ +#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ +#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ +#define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */ +#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ +#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ + |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32H7xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + +uint32_t common_system_clock; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure Cortex-M4 Instruction cache through ART accelerator */ + __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */ + __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ + __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB4_FORCE_RESET(); + __HAL_RCC_AHB4_RELEASE_RESET(); + + __HAL_RCC_APB3_FORCE_RESET(); + __HAL_RCC_APB3_RELEASE_RESET(); + + __HAL_RCC_APB1L_FORCE_RESET(); + __HAL_RCC_APB1L_RELEASE_RESET(); + + __HAL_RCC_APB1H_FORCE_RESET(); + __HAL_RCC_APB1H_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB4_FORCE_RESET(); + __HAL_RCC_APB4_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * the SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if((uint32_t)uwTickFreq == 0UL) + { + return HAL_ERROR; + } + + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup HAL_Group2 + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in Systick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32H7xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V. + * This requires VDDA equal to or higher than 2.8 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V. + * This requires VDDA equal to or higher than 2.4 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V. + * This requires VDDA equal to or higher than 2.1 V. + * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V. + * This requires VDDA equal to or higher than 1.8 V. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode specifies the high impedance mode + * This parameter can be one of the following values: + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. + * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) + { + if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} + +#if defined(SYSCFG_PMCR_EPIS_SEL) +/** + * @brief Ethernet PHY Interface Selection either MII or RMII + * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface + * This parameter can be one of the following values: + * @arg SYSCFG_ETH_MII : Select the Media Independent Interface + * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface + * @retval None + */ +void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface)); + + MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface)); +} +#endif /* SYSCFG_PMCR_EPIS_SEL */ + +/** + * @brief Analog Switch control for dual analog pads. + * @param SYSCFG_AnalogSwitch: Selects the analog pad + * This parameter can be one or a combination of the following values: + * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch + * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch + * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch + * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch + * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C) + * This parameter can be one or a combination of the following values: + * @arg SYSCFG_SWITCH_PA0_OPEN + * @arg SYSCFG_SWITCH_PA0_CLOSE + * @arg SYSCFG_SWITCH_PA1_OPEN + * @arg SYSCFG_SWITCH_PA1_CLOSE + * @arg SYSCFG_SWITCH_PC2_OPEN + * @arg SYSCFG_SWITCH_PC2_CLOSE + * @arg SYSCFG_SWITCH_PC3_OPEN + * @arg SYSCFG_SWITCH_PC3_CLOSE + * @retval None + */ + +void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch)); + assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState)); + + MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState)); +} + +#if defined(SYSCFG_PMCR_BOOSTEN) +/** + * @brief Enables the booster to reduce the total harmonic distortion of the analog + * switch when the supply voltage is lower than 2.7 V. + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +void HAL_SYSCFG_EnableBOOST(void) +{ + SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} + +/** + * @brief Disables the booster + * @note Activating the booster allows to guaranty the analog switch AC performance + * when the supply voltage is below 2.7 V: in this case, the analog switch + * performance is the same on the full voltage range + * @retval None + */ +void HAL_SYSCFG_DisableBOOST(void) +{ + CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ; +} +#endif /* SYSCFG_PMCR_BOOSTEN */ + +#if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) +/** + * @brief BootCM7 address 0 configuration + * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + * This parameter can be one of the following values: + * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1 + * @retval None + */ +void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + { + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos)); +#else + MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos)); +#endif /*DUAL_CORE*/ + } + else + { + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16)); +#else + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16)); +#endif /*DUAL_CORE*/ + } +} +#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */ + +#if defined(DUAL_CORE) +/** + * @brief BootCM4 address 0 configuration + * @param BootRegister :Specifies the Boot Address register (Address0 or Address1) + * This parameter can be one of the following values: + * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0 + * @arg SYSCFG_BOOT_ADDR1: Select the boot address1 + * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1 + * @retval None + */ +void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister)); + assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress)); + + if ( BootRegister == SYSCFG_BOOT_ADDR0 ) + { + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos)); + } + + else + { + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16)); + } +} + +/** + * @brief Enables the Cortex-M7 boot + * @retval None + */ +void HAL_SYSCFG_EnableCM7BOOT(void) +{ + SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7); +} + +/** + * @brief Disables the Cortex-M7 boot + * @note Disabling the boot will gate the CPU clock + * @retval None + */ +void HAL_SYSCFG_DisableCM7BOOT(void) +{ + CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ; +} + +/** + * @brief Enables the Cortex-M4 boot + * @retval None + */ +void HAL_SYSCFG_EnableCM4BOOT(void) +{ + SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); +} + +/** + * @brief Disables the Cortex-M4 boot + * @note Disabling the boot will gate the CPU clock + * @retval None + */ +void HAL_SYSCFG_DisableCM4BOOT(void) +{ + CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4); +} +#endif /*DUAL_CORE*/ +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN); +} + + +/** + * @brief To Enable optimize the I/O speed when the product voltage is low. + * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + * higher than 2.5 V might be destructive. + * @retval None + */ +void HAL_SYSCFG_EnableIOSpeedOptimize(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +/** + * @brief To Disable optimize the I/O speed when the product voltage is low. + * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be + * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is + * higher than 2.5 V might be destructive. + * @retval None + */ +void HAL_SYSCFG_DisableIOSpeedOptimize(void) +{ +#if defined(SYSCFG_CCCSR_HSLV) + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV); +#else + CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3)); +#endif /* SYSCFG_CCCSR_HSLV */ +} + +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell + * This parameter can be one of the following values: + * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode)); + MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode)); +} + +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_PMOSCode: PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @param SYSCFG_NMOSCode: NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); +} + +#if defined(SYSCFG_CCCR_NCC_MMC) +/** + * @brief Code selection for the I/O Compensation cell + * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code + * This code is applied to the I/O compensation cell when the CS bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode ) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode)); + assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode)); + MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) ); +} +#endif /* SYSCFG_CCCR_NCC_MMC */ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout0 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16] + * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16] + */ +void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0); +} +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ + +#if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) +/** @brief SYSCFG ADC2 internal input alternate connection macros + * @param Adc2AltRout1 This parameter can be a value of : + * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17] + * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17] + */ +void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1)); + + MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1); +} +#endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ + +/** + * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1); +} + + +/** + * @brief Enable the Debug Module during Domain1/CDomain STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1); +} + +/** + * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +/** + * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable the Debug Module during Domain1 SLEEP mode + * @retval None + */ +void HAL_EnableDomain2DBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Disable the Debug Module during Domain2 SLEEP mode + * @retval None + */ +void HAL_DisableDomain2DBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2); +} + +/** + * @brief Enable the Debug Module during Domain2 STOP mode + * @retval None + */ +void HAL_EnableDomain2DBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Disable the Debug Module during Domain2 STOP mode + * @retval None + */ +void HAL_DisableDomain2DBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2); +} + +/** + * @brief Enable the Debug Module during Domain2 STANDBY mode + * @retval None + */ +void HAL_EnableDomain2DBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} + +/** + * @brief Disable the Debug Module during Domain2 STANDBY mode + * @retval None + */ +void HAL_DisableDomain2DBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2); +} +#endif /*DUAL_CORE*/ + +#if defined(DBGMCU_CR_DBG_STOPD3) +/** + * @brief Enable the Debug Module during Domain3/SRDomain STOP mode + * @retval None + */ +void HAL_EnableDomain3DBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} + +/** + * @brief Disable the Debug Module during Domain3/SRDomain STOP mode + * @retval None + */ +void HAL_DisableDomain3DBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); +} +#endif /*DBGMCU_CR_DBG_STOPD3*/ + +#if defined(DBGMCU_CR_DBG_STANDBYD3) +/** + * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode + * @retval None + */ +void HAL_EnableDomain3DBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} + +/** + * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode + * @retval None + */ +void HAL_DisableDomain3DBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); +} +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ + +/** + * @brief Set the FMC Memory Mapping Swapping config. + * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be + FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 + * @retval HAL state + */ +void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig) +{ + /* Check the parameter */ + assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig)); + MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig); +} + +/** + * @brief Get FMC Bank mapping mode. + * @retval The FMC Bank mapping mode. This parameter can be + FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2 +*/ +uint32_t HAL_GetFMCMemorySwappingConfig(void) +{ + return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP); +} + +/** + * @brief Configure the EXTI input event line edge + * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21), + * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86. + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Edge: Specifies EXTI line Edge used. + * This parameter can be one of the following values : + * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection + * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection + * @retval None + */ +void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ) +{ + /* Check the parameter */ + assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge)); + + /* Clear Rising Falling edge configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + + if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE) + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE) + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } +} + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86. + * @retval None + */ +void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line)); + + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); +} + + +/** + * @brief Clears the EXTI's line pending flags for Domain D1 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @retval None + */ +void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + +} + +#if defined(DUAL_CORE) +/** + * @brief Clears the EXTI's line pending flags for Domain D2 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @retval None + */ +void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_D2_LINE(EXTI_Line)); + WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); +} + +#endif /*DUAL_CORE*/ +/** + * @brief Configure the EXTI input event line for Domain D1 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. + * This parameter can be one or a combination of the following values : + * @arg EXTI_MODE_IT : Interrupt Mode selected + * @arg EXTI_MODE_EVT : Event Mode selected + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + + * @retval None + */ +void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +{ + /* Check the parameter */ + assert_param(IS_EXTI_D1_LINE(EXTI_Line)); + assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); + + if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } + + if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + else + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } +} + +#if defined(DUAL_CORE) +/** + * @brief Configure the EXTI input event line for Domain D2 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved + * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event. + * This parameter can be one or a combination of the following values : + * @arg EXTI_MODE_IT : Interrupt Mode selected + * @arg EXTI_MODE_EVT : Event Mode selected + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + + * @retval None + */ +void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd ) +{ + /* Check the parameter */ + assert_param(IS_EXTI_D2_LINE(EXTI_Line)); + assert_param(IS_EXTI_MODE_LINE(EXTI_Mode)); + + if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } + + if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT) + { + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + else + { + SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + } +} +#endif /*DUAL_CORE*/ + +/** + * @brief Configure the EXTI input event line for Domain D3 + * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values, + * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34, + * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53) + * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line. + * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event. + * This parameter can be one of the following values : + * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source + * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source + * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source + * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source + * @retval None + */ +void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc ) +{ + __IO uint32_t *pRegv; + + /* Check the parameter */ + assert_param(IS_EXTI_D3_LINE(EXTI_Line)); + assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc)); + + if( EXTI_LineCmd == 0UL) + { + /* Clear EXTI line configuration */ + CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) ); + } + else + { + SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL))); + } + + if(((EXTI_Line>>4)%2UL) == 0UL) + { + pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL)); + } + else + { + pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL)); + } + MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL))); + +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c new file mode 100644 index 0000000..05730c1 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined + inside the stm32h7xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enables the MPU + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != 0UL) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00; + MPU->RASR = 0x00; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval status - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h)) + * @retval status - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if defined(DUAL_CORE) + +/** + * @brief Returns the current CPU ID. + * @retval CPU identifier + */ +uint32_t HAL_GetCurrentCPUID(void) +{ + if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U) + { + return CM7_CPUID; + } + else + { + return CM4_CPUID; + } +} + +#else + +/** +* @brief Returns the current CPU ID. +* @retval CPU identifier +*/ +uint32_t HAL_GetCurrentCPUID(void) +{ + return CM7_CPUID; +} + +#endif /*DUAL_CORE*/ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c new file mode 100644 index 0000000..6690bc8 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c @@ -0,0 +1,516 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_crc.c + * @author MCD Application Team + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) + (++) specify input data format + (++) specify input or output data inversion mode if any + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CRC_Private_Functions CRC Private Functions + * @{ + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been + * picked up by user */ + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) + { + /* initialize peripheral with default generating polynomial */ + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); + } + else + { + /* initialize CRC peripheral with generating polynomial defined by user */ + if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* check whether or not non-default CRC initial value has been + * picked up by user */ + assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); + if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) + { + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + } + else + { + WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); + } + + + /* set input data inversion mode */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + + /* set output data inversion mode */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + + /* makes sure the input data format (bytes, halfwords or words stream) + * is properly specified by user */ + assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if (hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_REG(hcrc->Instance->IDR); + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + using combination of the previous CRC value and the new one. + + [..] or + + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter Data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter 32-bit input data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + /* Specific 8-bit input data handling */ + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRC handle state. + * @param hcrc CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) +{ + /* Return CRC handle state */ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Enter 8-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + uint16_t data; + __IO uint16_t *pReg; + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if ((BufferLength % 4U) == 1U) + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + } + if ((BufferLength % 4U) == 2U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + } + if ((BufferLength % 4U) == 3U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + } + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @brief Enter 16-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + __IO uint16_t *pReg; + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; + } + if ((BufferLength % 2U) != 0U) + { + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = pBuffer[2U * i]; + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @} + */ + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c new file mode 100644 index 0000000..c814b28 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c @@ -0,0 +1,230 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_crc_ex.c + * @author MCD Application Team + * @brief Extended CRC HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the CRC peripheral. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim +================================================================================ + ##### How to use this driver ##### +================================================================================ + [..] + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() + (+) Configure Input or Output data inversion + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup CRCEx CRCEx + * @brief CRC Extended HAL module driver + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions + * @{ + */ + +/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Extended configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the generating polynomial + (+) Configure the input data inversion + (+) Configure the output data inversion + +@endverbatim + * @{ + */ + + +/** + * @brief Initialize the CRC polynomial if different from default one. + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). + * This parameter is written in normal representation, e.g. + * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength CRC polynomial length. + * This parameter can be one of the following values: + * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) + * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) + * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ + + /* Check the parameters */ + assert_param(IS_CRC_POL_LENGTH(PolyLength)); + + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) + { + status = HAL_ERROR; + } + else + { + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } + } + if (status == HAL_OK) + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); + + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + } + /* Return function status */ + return status; +} + +/** + * @brief Set the Reverse Input data mode. + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) + * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set input data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the Reverse Output data mode. + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) + * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set output data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + + +/** + * @} + */ + + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c new file mode 100644 index 0000000..dada223 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -0,0 +1,2062 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/** @addtogroup DMA_Private_Types + * @{ + */ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +typedef struct +{ + __IO uint32_t ISR; /*!< BDMA interrupt status register */ + __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */ +} BDMA_Base_Registers; +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */ + +#define BDMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ +#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction */ + +/* DMA to BDMA conversion */ +#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \ + ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \ + BDMA_PERIPH_TO_MEMORY) + +#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U) +#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U) + +#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U) +#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U) + +#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U) + +#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U) + +#if defined(UART9) +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX ))) +#else +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX ))) + +#endif +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + The HAL_DMA_DeInit function allows to deinitialize the DMA stream. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t registerValue; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Get the CR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + registerValue |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be + lock when transferring data to/from USART/UART */ +#if (STM32H7_DEV_ID == 0x450UL) + if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) + { +#endif /* STM32H7_DEV_ID == 0x450UL */ + if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + { + registerValue |= DMA_SxCR_TRBUFF; + } +#if (STM32H7_DEV_ID == 0x450UL) + } +#endif /* STM32H7_DEV_ID == 0x450UL */ + + /* Write to DMA Stream CR register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; + + /* Get the FCR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + registerValue |= hdma->Init.FIFOMode; + + /* the FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + registerValue |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 */ + if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* Check the request parameter */ + assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Get the CR register value */ + registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ + registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ + BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ + BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ + BDMA_CCR_CT)); + + /* Prepare the DMA Channel configuration */ + registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | + DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + DMA_TO_BDMA_MODE(hdma->Init.Mode) | + DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); + + /* Write to DMA Channel CR register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; + + /* calculation of the channel index */ + hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Initialize parameters for DMAMUX request generator : + if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 + */ + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Reset DMA Streamx control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; + + /* Get DMA steam Base Address */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Reset DMA Channel control register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U; + + /* Reset DMA Channel memory 0 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U; + + /* Reset DMA Channel memory 1 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U; + + /* Get DMA steam Base Address */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + /* Return error status */ + return HAL_ERROR; + } + +#if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */ + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ +#endif /* BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->DMAmuxChannel != 0U) + { + /* Resett he DMAMUX channel that corresponds to the DMA stream */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + } + + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Register and Unregister DMA callbacks + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Enable Half Transfer IT if corresponding Callback is set */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + } + } + else /* BDMA channel */ + { + /* Enable Common interrupts */ + MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /*Enable Half Transfer IT if corresponding Callback is set */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check if DMAMUX Synchronization is enabled */ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + const __IO uint32_t *enableRegister; + + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Disable DMA All Interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while(((*enableRegister) & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel: Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t cpltlevel_mask; + uint32_t tickstart = HAL_GetTick(); + + /* IT status register */ + __IO uint32_t *isr_reg; + /* IT clear flag register */ + __IO uint32_t *ifcr_reg; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Polling mode not supported in circular mode and double buffering mode */ + if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + else /* BDMA channel */ + { + /* Polling mode not supported in circular mode */ + if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + + while(((*isr_reg) & cpltlevel_mask) == 0U) + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + else /* BDMA channel */ + { + if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* if timeout then abort the current transfer */ + /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */ + (void) HAL_DMA_Abort(hdma); + /* + Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check for DMAMUX Request generator (if used) overrun status */ + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + } + } + + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU)); + } + + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/ + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU)); + } + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr_dma, tmpisr_bdma; + uint32_t ccr_reg; + __IO uint32_t count = 0U; + uint32_t timeout = SystemCoreClock / 9600U; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr_dma = regs_dma->ISR; + tmpisr_bdma = regs_bdma->ISR; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) + { + /* Disable the transfer error interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) + { + /* Clear the FIFO error flag */ + regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) + { + /* Clear the direct mode error flag */ + regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Multi_Buffering mode enabled */ + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Clear the transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the transfer complete interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); + + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Change the DMA state to error if DMA disable fails */ + hdma->State = HAL_DMA_STATE_ERROR; + } + else + { + /* Change the DMA state to Ready if DMA disable success */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); + + /* Half Transfer Complete Interrupt management ******************************/ + if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) + { + /* Clear the half transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 1 */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 0 */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) + { + /* Clear the transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for Memory 1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for Memory 0 */ + hdma->XferCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Transfer Error Interrupt management **************************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback: pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval None + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Clear DBM bit */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Configure DMA Channel data length */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); + } + } + else /* BDMA instance(s) */ + { + /* return pointer to ISR and IFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Memory Data size equal to Byte */ + if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + break; + + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + return status; +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number; + uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); + + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } + else + { + /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ + (stream_baseaddress >= ((uint32_t)DMA2_Stream0))) + { + stream_number += 8U; + } + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; + } + else + { + /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + } + + hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c new file mode 100644 index 0000000..a134b4e --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c @@ -0,0 +1,712 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler . + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + -@- Multi (Double) buffer mode is possible with DMA and BDMA instances. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + (+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable the Double buffer mode */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + + /* Clear all flags */ + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA instance(s) */ + { + /* Enable the Double buffer mode */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + + /* Clear all flags */ + *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */ + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable the Double buffer mode */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U)); + + /* Clear all flags */ + *ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA instance(s) */ + { + /* Enable the Double buffer mode */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC); + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress; + + /* Calculate the interrupt clear flag register (IFCR) base address */ + ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U)); + + /* Clear all flags */ + *ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + } + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + /*Enable Half Transfer IT if corresponding Callback is set*/ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + } + } + else /* BDMA instance(s) */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + /*Enable Half Transfer IT if corresponding Callback is set*/ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check if DMAMUX Synchronization is enabled*/ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address: The new address + * @param memory: the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + if(memory == MEMORY0) + { + /* change the memory0 address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address; + } + else + { + /* change the memory1 address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address; + } + } + else /* BDMA instance(s) */ + { + if(memory == MEMORY0) + { + /* change the memory0 address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address; + } + else + { + /* change the memory1 address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address; + } + } + + return HAL_OK; +} + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + uint32_t syncSignalID = 0; + uint32_t syncPolarity = 0; + + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + if(pSyncConfig->SyncEnable == ENABLE) + { + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + } + else + { + assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + } + syncSignalID = pSyncConfig->SyncSignalID; + syncPolarity = pSyncConfig->SyncPolarity; + } + + /*Check if the DMA state is ready */ + if(hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Disable the synchronization and event generation before applying a new config */ + CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE)); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG( hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID) , \ + (syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \ + ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); + + /* Process Locked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + HAL_StatusTypeDef status; + HAL_DMA_StateTypeDef temp_state = hdma->State; + + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + } + else + { + assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + } + + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if(hdma->DMAmuxRequestGen == 0U) + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* error status */ + status = HAL_ERROR; + } + else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) + { + /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters */ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ + pRequestGeneratorConfig->Polarity; + /* Process Locked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA stream (instance). + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block */ + if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U)) + { + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if(hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Configure DMA Stream data length */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + } + } + else /* BDMA instance(s) */ + { + /* Configure DMA Stream data length */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + + /* Configure DMA Stream source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + } + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c new file mode 100644 index 0000000..c9090f7 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c @@ -0,0 +1,859 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt (CORE1 or CORE2 in case of dual core line ) + (++) Event (CORE1 or CORE2 in case of dual core line ) + (++) a combination of the previous + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + (+) PendClearSource used to set the D3 Smart Run Domain autoamtic pend clear source. + It is applicable for line with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain). + Value can be one of the following: + (++) EXTI_D3_PENDCLR_SRC_NONE : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 0 + (+++) On a configurable Line : the D3 domain wakeup signal is + automatically cleared after after the Delay + Rising Edge detect + (+++) On a direct Line : the D3 domain wakeup signal is + cleared after the direct event input signal is cleared + + (++) EXTI_D3_PENDCLR_SRC_DMACH6 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b00 : + DMA ch6 event selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_DMACH7 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b01 : + DMA ch7 event selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_LPTIM4 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b10 : + LPTIM4 out selected as D3 domain pendclear source + + (++) EXTI_D3_PENDCLR_SRC_LPTIM5 : no pend clear source is selected : + In this case corresponding bit of D2PMRx register is set to 1 + and corresponding bits(2) of D3PCRxL/H is set to b11 : + LPTIM5 out selected as D3 domain pendclear source + + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + (++) For Exti lines with wkaeup target is Any (CPU1 , CPU2 and D3 smart run domain), + choose gpio D3 PendClearSource using PendClearSource + member from EXTI_PendClear_Source structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04U /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08U /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + +#if defined (DUAL_CORE) + /* Configure interrupt mode for Core2 : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* The event mode cannot be configured if the line does not support it */ + assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT)); + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; +#endif /* DUAL_CORE */ + + /* Configure the D3 PendClear source in case of Wakeup target is Any */ + if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + assert_param(IS_EXTI_D3_PENDCLR_SRC(pExtiConfig->PendClearSource)); + + /*Calc the PMR register address for the given line */ + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + if(pExtiConfig->PendClearSource == EXTI_D3_PENDCLR_SRC_NONE) + { + /* Clear D3PMRx register for the given line */ + regval &= ~maskline; + /* Store D3PMRx register value */ + *regaddr = regval; + } + else + { + /* Set D3PMRx register to 1 for the given line */ + regval |= maskline; + /* Store D3PMRx register value */ + *regaddr = regval; + + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + regval = (*regaddr & (~(pcrlinepos * pcrlinepos * 3UL))) | (pcrlinepos * pcrlinepos * (pExtiConfig->PendClearSource - 1UL)); + *regaddr = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + pExtiConfig->Mode = EXTI_MODE_NONE; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } +#if defined (DUAL_CORE) + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT; + } +#endif /*DUAL_CORE*/ + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00U; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + /* Get default Pend Clear Source */ + pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE; + + /* 3] Get D3 Pend Clear source */ + if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + if(((*regaddr) & linepos) != 0UL) + { + /* if wakeup target is any and PMR set, the read pend clear source from D3PCRxL/H */ + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos)); + } + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t pcrlinepos; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + +#if defined (DUAL_CORE) + /* 1] Clear CM4 interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear CM4 event mode */ + regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; +#endif /* DUAL_CORE */ + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03UL))); + SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* 4] Clear D3 Config lines */ + if ((hexti->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = (*regaddr & ~maskline); + + if(linepos < 16UL) + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1L + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << linepos; + } + else + { + regaddr = (__IO uint32_t *)(&EXTI->D3PCR1H + (EXTI_CONFIG_OFFSET * offset)); + pcrlinepos = 1UL << (linepos - 16UL); + } + + /*Clear D3 PendClear source */ + *regaddr &= (~(pcrlinepos * pcrlinepos * 3UL)); + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4*/ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* Get pending bit */ + regval = (*regaddr & maskline); + + if (regval != 0x00U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4 */ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + +#if defined(DUAL_CORE) + if (HAL_GetCurrentCPUID() == CM7_CPUID) + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); + } + else /* Cortex-M4 */ + { + /* Get pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset)); + } +#else + regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset)); +#endif /* DUAL_CORE */ + + /* Clear Pending bit */ + *regaddr = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c new file mode 100644 index 0000000..950ea15 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c @@ -0,0 +1,6204 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_fdcan.c + * @author MCD Application Team + * @brief FDCAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Flexible DataRate Controller Area Network + * (FDCAN) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Configuration and Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the FDCAN peripheral using HAL_FDCAN_Init function. + + (#) If needed , configure the reception filters and optional features using + the following configuration functions: + (++) HAL_FDCAN_ConfigClockCalibration + (++) HAL_FDCAN_ConfigFilter + (++) HAL_FDCAN_ConfigGlobalFilter + (++) HAL_FDCAN_ConfigExtendedIdMask + (++) HAL_FDCAN_ConfigRxFifoOverwrite + (++) HAL_FDCAN_ConfigFifoWatermark + (++) HAL_FDCAN_ConfigRamWatchdog + (++) HAL_FDCAN_ConfigTimestampCounter + (++) HAL_FDCAN_EnableTimestampCounter + (++) HAL_FDCAN_DisableTimestampCounter + (++) HAL_FDCAN_ConfigTimeoutCounter + (++) HAL_FDCAN_EnableTimeoutCounter + (++) HAL_FDCAN_DisableTimeoutCounter + (++) HAL_FDCAN_ConfigTxDelayCompensation + (++) HAL_FDCAN_EnableTxDelayCompensation + (++) HAL_FDCAN_DisableTxDelayCompensation + (++) HAL_FDCAN_EnableISOMode + (++) HAL_FDCAN_DisableISOMode + (++) HAL_FDCAN_EnableEdgeFiltering + (++) HAL_FDCAN_DisableEdgeFiltering + (++) HAL_FDCAN_TT_ConfigOperation + (++) HAL_FDCAN_TT_ConfigReferenceMessage + (++) HAL_FDCAN_TT_ConfigTrigger + + (#) Start the FDCAN module using HAL_FDCAN_Start function. At this level + the node is active on the bus: it can send and receive messages. + + (#) The following Tx control functions can only be called when the FDCAN + module is started: + (++) HAL_FDCAN_AddMessageToTxFifoQ + (++) HAL_FDCAN_EnableTxBufferRequest + (++) HAL_FDCAN_AbortTxRequest + + (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to + get Tx buffer location used to place the Tx request thanks to + HAL_FDCAN_GetLatestTxFifoQRequestBuffer API. + It is then possible to abort later on the corresponding Tx Request using + HAL_FDCAN_AbortTxRequest API. + + (#) When a message is received into the FDCAN message RAM, it can be + retrieved using the HAL_FDCAN_GetRxMessage function. + + (#) Calling the HAL_FDCAN_Stop function stops the FDCAN module by entering + it to initialization mode and re-enabling access to configuration + registers through the configuration functions listed here above. + + (#) All other control functions can be called any time after initialization + phase, no matter if the FDCAN module is started or stopped. + + *** Polling mode operation *** + ============================== + + [..] + (#) Reception and transmission states can be monitored via the following + functions: + (++) HAL_FDCAN_IsRxBufferMessageAvailable + (++) HAL_FDCAN_IsTxBufferMessagePending + (++) HAL_FDCAN_GetRxFifoFillLevel + (++) HAL_FDCAN_GetTxFifoFreeLevel + + *** Interrupt mode operation *** + ================================ + [..] + (#) There are two interrupt lines: line 0 and 1. + By default, all interrupts are assigned to line 0. Interrupt lines + can be configured using HAL_FDCAN_ConfigInterruptLines function. + + (#) Notifications are activated using HAL_FDCAN_ActivateNotification + function. Then, the process can be controlled through one of the + available user callbacks: HAL_FDCAN_xxxCallback. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback() + to register an interrupt callback. + + Function HAL_FDCAN_RegisterCallback() allows to register following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) RxBufferNewMessageCallback : Rx Buffer New Message Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback, + TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback, + TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks : + respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(), + HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(), + HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(), + HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_TT_RegisterScheduleSyncCallback(), + HAL_FDCAN_TT_RegisterTimeMarkCallback(), HAL_FDCAN_TT_RegisterStopWatchCallback() and + HAL_FDCAN_TT_RegisterGlobalTimeCallback(). + + Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) RxBufferNewMessageCallback : Rx Buffer New Message Callback. + (+) HighPriorityMessageCallback : High Priority Message Callback. + (+) TimestampWraparoundCallback : Timestamp Wraparound Callback. + (+) TimeoutOccurredCallback : Timeout Occurred Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : FDCAN MspInit. + (+) MspDeInitCallback : FDCAN MspDeInit. + + For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, + RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback, + TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated + register callbacks : respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(), + HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(), + HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(), + HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(), + HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), HAL_FDCAN_TT_UnRegisterTimeMarkCallback(), + HAL_FDCAN_TT_UnRegisterStopWatchCallback() and HAL_FDCAN_TT_UnRegisterGlobalTimeCallback(). + + By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + examples HAL_FDCAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit() + or HAL_FDCAN_Init() function. + + When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +#if defined(FDCAN1) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FDCAN FDCAN + * @brief FDCAN HAL module driver + * @{ + */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FDCAN_Private_Constants + * @{ + */ +#define FDCAN_TIMEOUT_VALUE 10U +#define FDCAN_TIMEOUT_COUNT 50U + +#define FDCAN_TX_EVENT_FIFO_MASK (FDCAN_IR_TEFL | FDCAN_IR_TEFF | FDCAN_IR_TEFW | FDCAN_IR_TEFN) +#define FDCAN_RX_FIFO0_MASK (FDCAN_IR_RF0L | FDCAN_IR_RF0F | FDCAN_IR_RF0W | FDCAN_IR_RF0N) +#define FDCAN_RX_FIFO1_MASK (FDCAN_IR_RF1L | FDCAN_IR_RF1F | FDCAN_IR_RF1W | FDCAN_IR_RF1N) +#define FDCAN_ERROR_MASK (FDCAN_IR_ELO | FDCAN_IR_WDI | FDCAN_IR_PEA | FDCAN_IR_PED | FDCAN_IR_ARA) +#define FDCAN_ERROR_STATUS_MASK (FDCAN_IR_EP | FDCAN_IR_EW | FDCAN_IR_BO) +#define FDCAN_TT_SCHEDULE_SYNC_MASK (FDCAN_TTIR_SBC | FDCAN_TTIR_SMC | FDCAN_TTIR_CSM | FDCAN_TTIR_SOG) +#define FDCAN_TT_TIME_MARK_MASK (FDCAN_TTIR_RTMI | FDCAN_TTIR_TTMI) +#define FDCAN_TT_GLOBAL_TIME_MASK (FDCAN_TTIR_GTW | FDCAN_TTIR_GTD) +#define FDCAN_TT_DISTURBING_ERROR_MASK (FDCAN_TTIR_GTE | FDCAN_TTIR_TXU | FDCAN_TTIR_TXO | \ + FDCAN_TTIR_SE1 | FDCAN_TTIR_SE2 | FDCAN_TTIR_ELC) +#define FDCAN_TT_FATAL_ERROR_MASK (FDCAN_TTIR_IWT | FDCAN_TTIR_WT | FDCAN_TTIR_AW | FDCAN_TTIR_CER) + +#define FDCAN_ELEMENT_MASK_STDID ((uint32_t)0x1FFC0000U) /* Standard Identifier */ +#define FDCAN_ELEMENT_MASK_EXTID ((uint32_t)0x1FFFFFFFU) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_RTR ((uint32_t)0x20000000U) /* Remote Transmission Request */ +#define FDCAN_ELEMENT_MASK_XTD ((uint32_t)0x40000000U) /* Extended Identifier */ +#define FDCAN_ELEMENT_MASK_ESI ((uint32_t)0x80000000U) /* Error State Indicator */ +#define FDCAN_ELEMENT_MASK_TS ((uint32_t)0x0000FFFFU) /* Timestamp */ +#define FDCAN_ELEMENT_MASK_DLC ((uint32_t)0x000F0000U) /* Data Length Code */ +#define FDCAN_ELEMENT_MASK_BRS ((uint32_t)0x00100000U) /* Bit Rate Switch */ +#define FDCAN_ELEMENT_MASK_FDF ((uint32_t)0x00200000U) /* FD Format */ +#define FDCAN_ELEMENT_MASK_EFC ((uint32_t)0x00800000U) /* Event FIFO Control */ +#define FDCAN_ELEMENT_MASK_MM ((uint32_t)0xFF000000U) /* Message Marker */ +#define FDCAN_ELEMENT_MASK_FIDX ((uint32_t)0x7F000000U) /* Filter Index */ +#define FDCAN_ELEMENT_MASK_ANMF ((uint32_t)0x80000000U) /* Accepted Non-matching Frame */ +#define FDCAN_ELEMENT_MASK_ET ((uint32_t)0x00C00000U) /* Event type */ + +#define FDCAN_MESSAGE_RAM_SIZE 0x2800U +#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FDCAN_Private_Functions_Prototypes + * @{ + */ +static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan); +static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FDCAN_Exported_Functions FDCAN Exported Functions + * @{ + */ + +/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the FDCAN. + (+) De-initialize the FDCAN. + (+) Enter FDCAN peripheral in power down mode. + (+) Exit power down mode. + (+) Register callbacks. + (+) Unregister callbacks. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FDCAN peripheral according to the specified + * parameters in the FDCAN_InitTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + HAL_StatusTypeDef status; + const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7}; + + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check FDCAN instance */ + if (hfdcan->Instance == FDCAN1) + { + hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U); + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_FRAME_FORMAT(hfdcan->Init.FrameFormat)); + assert_param(IS_FDCAN_MODE(hfdcan->Init.Mode)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.TransmitPause)); + assert_param(IS_FUNCTIONAL_STATE(hfdcan->Init.ProtocolException)); + assert_param(IS_FDCAN_NOMINAL_PRESCALER(hfdcan->Init.NominalPrescaler)); + assert_param(IS_FDCAN_NOMINAL_SJW(hfdcan->Init.NominalSyncJumpWidth)); + assert_param(IS_FDCAN_NOMINAL_TSEG1(hfdcan->Init.NominalTimeSeg1)); + assert_param(IS_FDCAN_NOMINAL_TSEG2(hfdcan->Init.NominalTimeSeg2)); + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + assert_param(IS_FDCAN_DATA_PRESCALER(hfdcan->Init.DataPrescaler)); + assert_param(IS_FDCAN_DATA_SJW(hfdcan->Init.DataSyncJumpWidth)); + assert_param(IS_FDCAN_DATA_TSEG1(hfdcan->Init.DataTimeSeg1)); + assert_param(IS_FDCAN_DATA_TSEG2(hfdcan->Init.DataTimeSeg2)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.StdFiltersNbr, 128U)); + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.ExtFiltersNbr, 64U)); + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo0ElmtsNbr, 64U)); + if (hfdcan->Init.RxFifo0ElmtsNbr > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo0ElmtSize)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxFifo1ElmtsNbr, 64U)); + if (hfdcan->Init.RxFifo1ElmtsNbr > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxFifo1ElmtSize)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.RxBuffersNbr, 64U)); + if (hfdcan->Init.RxBuffersNbr > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.RxBufferSize)); + } + assert_param(IS_FDCAN_MAX_VALUE(hfdcan->Init.TxEventsNbr, 32U)); + assert_param(IS_FDCAN_MAX_VALUE((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr), 32U)); + if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U) + { + assert_param(IS_FDCAN_TX_FIFO_QUEUE_MODE(hfdcan->Init.TxFifoQueueMode)); + } + if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U) + { + assert_param(IS_FDCAN_DATA_SIZE(hfdcan->Init.TxElmtSize)); + } + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Reset callbacks to legacy functions */ + hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback */ + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */ + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */ + hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback; /* Legacy weak RxBufferNewMessageCallback */ + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */ + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */ + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak TimeoutOccurredCallback */ + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */ + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback */ + hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback */ + hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback */ + hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback */ + + if (hfdcan->MspInitCallback == NULL) + { + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hfdcan->MspInitCallback(hfdcan); + } +#else + if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hfdcan->Lock = HAL_UNLOCKED; + + /* Init the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspInit(hfdcan); + } +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode acknowledge */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Set the no automatic retransmission */ + if (hfdcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR); + } + + /* Set the transmit pause feature */ + if (hfdcan->Init.TransmitPause == ENABLE) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + else + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP); + } + + /* Set the Protocol Exception Handling */ + if (hfdcan->Init.ProtocolException == ENABLE) + { + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + else + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD); + } + + /* Set FDCAN Frame Format */ + MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat); + + /* Reset FDCAN Operation Mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM)); + CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + /* Set FDCAN Operating Mode: + | Normal | Restricted | Bus | Internal | External + | | Operation | Monitoring | LoopBack | LoopBack + CCCR.TEST | 0 | 0 | 0 | 1 | 1 + CCCR.MON | 0 | 0 | 1 | 1 | 0 + TEST.LBCK | 0 | 0 | 0 | 1 | 1 + CCCR.ASM | 0 | 1 | 0 | 0 | 0 + */ + if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION) + { + /* Enable Restricted Operation mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + } + else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL) + { + if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING) + { + /* Enable write access to TEST register */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST); + + /* Enable LoopBack mode */ + SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK); + + if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK) + { + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Enable bus monitoring mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON); + } + } + else + { + /* Nothing to do: normal mode */ + } + + /* Set the nominal bit timing register */ + hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos)); + + /* If FD operation with BRS is selected, set the data bit timing register */ + if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS) + { + hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \ + (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \ + (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos)); + } + + if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U) + { + /* Select between Tx FIFO and Tx Queue operation modes */ + SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode); + } + + /* Configure Tx element size */ + if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U) + { + MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]); + } + + /* Configure Rx FIFO 0 element size */ + if (hfdcan->Init.RxFifo0ElmtsNbr > 0U) + { + MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos)); + } + + /* Configure Rx FIFO 1 element size */ + if (hfdcan->Init.RxFifo1ElmtsNbr > 0U) + { + MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos)); + } + + /* Configure Rx buffer element size */ + if (hfdcan->Init.RxBuffersNbr > 0U) + { + MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos)); + } + + /* By default operation mode is set to Event-driven communication. + If Time-triggered communication is needed, user should call the + HAL_FDCAN_TT_ConfigOperation function just after the HAL_FDCAN_Init */ + if (hfdcan->Instance == FDCAN1) + { + CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM); + } + + /* Initialize the Latest Tx FIFO/Queue request buffer index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Initialize the error code */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Initialize the FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Calculate each RAM block address */ + status = FDCAN_CalcultateRamBlockAddresses(hfdcan); + + /* Return function status */ + return status; +} + +/** + * @brief Deinitializes the FDCAN peripheral registers to their default reset values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Check FDCAN handle */ + if (hfdcan == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(hfdcan->Instance)); + + /* Stop the FDCAN module: return value is voluntary ignored */ + (void)HAL_FDCAN_Stop(hfdcan); + + /* Disable Interrupt lines */ + CLEAR_BIT(hfdcan->Instance->ILE, (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1)); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + if (hfdcan->MspDeInitCallback == NULL) + { + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hfdcan->MspDeInitCallback(hfdcan); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_FDCAN_MspDeInit(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the FDCAN MSP. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Enter FDCAN peripheral in sleep mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Request clock stop */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN is ready for power down */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == 0U) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Exit power down mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t tickstart; + + /* Reset clock stop request */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Enter normal operation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Return function status */ + return HAL_OK; +} + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a FDCAN CallBack. + * To be used instead of the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = pCallback; + break; + + case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID : + hfdcan->RxBufferNewMessageCallback = pCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = pCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = pCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = pCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = pCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = pCallback; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a FDCAN CallBack. + * FDCAN callback is redirected to the weak predefined callback + * @param hfdcan pointer to a FDCAN_HandleTypeDef structure that contains + * the configuration information for FDCAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_FDCAN_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty callback ID + * @arg @ref HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID Rx buffer new message callback ID + * @arg @ref HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID High priority message callback ID + * @arg @ref HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID Timestamp wraparound callback ID + * @arg @ref HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID Timeout occurred callback ID + * @arg @ref HAL_FDCAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_FDCAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_FDCAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_FDCAN_TX_FIFO_EMPTY_CB_ID : + hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; + break; + + case HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID : + hfdcan->RxBufferNewMessageCallback = HAL_FDCAN_RxBufferNewMessageCallback; + break; + + case HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID : + hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; + break; + + case HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID : + hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; + break; + + case HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID : + hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; + break; + + case HAL_FDCAN_ERROR_CALLBACK_CB_ID : + hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; + break; + + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hfdcan->State == HAL_FDCAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_FDCAN_MSPINIT_CB_ID : + hfdcan->MspInitCallback = HAL_FDCAN_MspInit; + break; + + case HAL_FDCAN_MSPDEINIT_CB_ID : + hfdcan->MspDeInitCallback = HAL_FDCAN_MspDeInit; + break; + + default : + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Clock Calibration FDCAN Callback + * To be used instead of the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Clock Calibration Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ClockCalibrationCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Clock Calibration FDCAN Callback + * Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ClockCalibrationCallback = HAL_FDCAN_ClockCalibrationCallback; /* Legacy weak ClockCalibrationCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Event Fifo FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Event Fifo Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Event Fifo FDCAN Callback + * Tx Event Fifo FDCAN Callback is redirected to the weak HAL_FDCAN_TxEventFifoCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 0 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 0 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 0 FDCAN Callback + * Rx Fifo 0 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo0Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Rx Fifo 1 FDCAN Callback + * To be used instead of the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Rx Fifo 1 Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Rx Fifo 1 FDCAN Callback + * Rx Fifo 1 FDCAN Callback is redirected to the weak HAL_FDCAN_RxFifo1Callback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Complete FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Complete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Complete FDCAN Callback + * Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Tx Buffer Abort FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Tx Buffer Abort Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Tx Buffer Abort FDCAN Callback + * Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Error Status FDCAN Callback + * To be used instead of the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the Error Status Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Error Status FDCAN Callback + * Error Status FDCAN Callback is redirected to the weak HAL_FDCAN_ErrorStatusCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Schedule Synchronization FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Schedule Synchronization Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_ScheduleSyncCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Schedule Synchronization FDCAN Callback + * TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_ScheduleSyncCallback = HAL_FDCAN_TT_ScheduleSyncCallback; /* Legacy weak TT_ScheduleSyncCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Time Mark FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Time Mark Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_TimeMarkCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Time Mark FDCAN Callback + * TT Time Mark Callback is redirected to the weak HAL_FDCAN_TT_TimeMarkCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_TimeMarkCallback = HAL_FDCAN_TT_TimeMarkCallback; /* Legacy weak TT_TimeMarkCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Stop Watch FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Stop Watch Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_StopWatchCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Stop Watch FDCAN Callback + * TT Stop Watch Callback is redirected to the weak HAL_FDCAN_TT_StopWatchCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_StopWatchCallback = HAL_FDCAN_TT_StopWatchCallback; /* Legacy weak TT_StopWatchCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register TT Global Time FDCAN Callback + * To be used instead of the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback + * @param hfdcan FDCAN handle + * @param pCallback pointer to the TT Global Time Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_GlobalTimeCallback = pCallback; + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the TT Global Time FDCAN Callback + * TT Global Time Callback is redirected to the weak HAL_FDCAN_TT_GlobalTimeCallback() predefined callback + * @param hfdcan FDCAN handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + hfdcan->TT_GlobalTimeCallback = HAL_FDCAN_TT_GlobalTimeCallback; /* Legacy weak TT_GlobalTimeCallback */ + } + else + { + /* Update the error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions + * @brief FDCAN Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigClockCalibration : Configure the FDCAN clock calibration unit + (+) HAL_FDCAN_GetClockCalibrationState : Get the clock calibration state + (+) HAL_FDCAN_ResetClockCalibrationState : Reset the clock calibration state + (+) HAL_FDCAN_GetClockCalibrationCounter : Get the clock calibration counters values + (+) HAL_FDCAN_ConfigFilter : Configure the FDCAN reception filters + (+) HAL_FDCAN_ConfigGlobalFilter : Configure the FDCAN global filter + (+) HAL_FDCAN_ConfigExtendedIdMask : Configure the extended ID mask + (+) HAL_FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode + (+) HAL_FDCAN_ConfigFifoWatermark : Configure the FIFO watermark + (+) HAL_FDCAN_ConfigRamWatchdog : Configure the RAM watchdog + (+) HAL_FDCAN_ConfigTimestampCounter : Configure the timestamp counter + (+) HAL_FDCAN_EnableTimestampCounter : Enable the timestamp counter + (+) HAL_FDCAN_DisableTimestampCounter : Disable the timestamp counter + (+) HAL_FDCAN_GetTimestampCounter : Get the timestamp counter value + (+) HAL_FDCAN_ResetTimestampCounter : Reset the timestamp counter to zero + (+) HAL_FDCAN_ConfigTimeoutCounter : Configure the timeout counter + (+) HAL_FDCAN_EnableTimeoutCounter : Enable the timeout counter + (+) HAL_FDCAN_DisableTimeoutCounter : Disable the timeout counter + (+) HAL_FDCAN_GetTimeoutCounter : Get the timeout counter value + (+) HAL_FDCAN_ResetTimeoutCounter : Reset the timeout counter to its start value + (+) HAL_FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation + (+) HAL_FDCAN_EnableTxDelayCompensation : Enable the transmitter delay compensation + (+) HAL_FDCAN_DisableTxDelayCompensation : Disable the transmitter delay compensation + (+) HAL_FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode + (+) HAL_FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode + (+) HAL_FDCAN_EnableEdgeFiltering : Enable edge filtering during bus integration + (+) HAL_FDCAN_DisableEdgeFiltering : Disable edge filtering during bus integration + +@endverbatim + * @{ + */ + +/** + * @brief Configure the FDCAN clock calibration unit according to the specified + * parameters in the FDCAN_ClkCalUnitTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sCcuConfig pointer to an FDCAN_ClkCalUnitTypeDef structure that + * contains the clock calibration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration)); + if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE) + { + assert_param(IS_FDCAN_CKDIV(sCcuConfig->ClockDivider)); + } + else + { + assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->MinOscClkPeriods, 0xFFU)); + assert_param(IS_FDCAN_CALIBRATION_FIELD_LENGTH(sCcuConfig->CalFieldLength)); + assert_param(IS_FDCAN_MIN_VALUE(sCcuConfig->TimeQuantaPerBitTime, 4U)); + assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->TimeQuantaPerBitTime, 0x25U)); + assert_param(IS_FDCAN_MAX_VALUE(sCcuConfig->WatchdogStartValue, 0xFFFFU)); + } + + /* FDCAN1 should be initialized in order to use clock calibration */ + if (hfdcan->Instance != FDCAN1) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + if (sCcuConfig->ClockCalibration == FDCAN_CLOCK_CALIBRATION_DISABLE) + { + /* Bypass clock calibration */ + SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC); + + /* Configure clock divider */ + MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider); + } + else /* sCcuConfig->ClockCalibration == ENABLE */ + { + /* Clock calibration unit generates time quanta clock */ + CLEAR_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC); + + /* Configure clock calibration unit */ + MODIFY_REG(FDCAN_CCU->CCFG, + (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM), + ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos))); + + /* Configure the start value of the calibration watchdog counter */ + MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the clock calibration state. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state) + */ +uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_CALS); +} + +/** + * @brief Reset the clock calibration state. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan) +{ + /* FDCAN1 should be initialized in order to use clock calibration */ + if (hfdcan->Instance != FDCAN1) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Calibration software reset */ + SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_SWR); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the clock calibration counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Counter clock calibration counter. + * This parameter can be a value of @arg FDCAN_calibration_counter. + * @retval Value clock calibration counter value + */ +uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* Check function parameters */ + assert_param(IS_FDCAN_CALIBRATION_COUNTER(Counter)); + + if (Counter == FDCAN_CALIB_TIME_QUANTA_COUNTER) + { + return ((FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_TQC) >> FDCANCCU_CSTAT_TQC_Pos); + } + else if (Counter == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) + { + return (FDCAN_CCU->CSTAT & FDCANCCU_CSTAT_OCPC); + } + else /* Counter == FDCAN_CALIB_WATCHDOG_COUNTER */ + { + return ((FDCAN_CCU->CWD & FDCANCCU_CWD_WDV) >> FDCANCCU_CWD_WDV_Pos); + } +} + +/** + * @brief Configure the FDCAN reception filter according to the specified + * parameters in the FDCAN_FilterTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that + * contains the filter configuration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig) +{ + uint32_t FilterElementW1; + uint32_t FilterElementW2; + uint32_t *FilterAddress; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(sFilterConfig->IdType)); + assert_param(IS_FDCAN_FILTER_CFG(sFilterConfig->FilterConfig)); + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->RxBufferIndex, 63U)); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->IsCalibrationMsg, 1U)); + } + + if (sFilterConfig->IdType == FDCAN_STANDARD_ID) + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); + if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER) + { + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); + assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); + } + + /* Build filter element */ + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + FilterElementW1 = ((FDCAN_FILTER_TO_RXBUFFER << 27U) | + (sFilterConfig->FilterID1 << 16U) | + (sFilterConfig->IsCalibrationMsg << 8U) | + sFilterConfig->RxBufferIndex); + } + else + { + FilterElementW1 = ((sFilterConfig->FilterType << 30U) | + (sFilterConfig->FilterConfig << 27U) | + (sFilterConfig->FilterID1 << 16U) | + sFilterConfig->FilterID2); + } + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.StandardFilterSA + (sFilterConfig->FilterIndex * 4U)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + } + else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ + { + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); + if (sFilterConfig->FilterConfig != FDCAN_FILTER_TO_RXBUFFER) + { + assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); + assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); + } + + /* Build first word of filter element */ + FilterElementW1 = ((sFilterConfig->FilterConfig << 29U) | sFilterConfig->FilterID1); + + /* Build second word of filter element */ + if (sFilterConfig->FilterConfig == FDCAN_FILTER_TO_RXBUFFER) + { + FilterElementW2 = sFilterConfig->RxBufferIndex; + } + else + { + FilterElementW2 = ((sFilterConfig->FilterType << 30U) | sFilterConfig->FilterID2); + } + + /* Calculate filter address */ + FilterAddress = (uint32_t *)(hfdcan->msgRam.ExtendedFilterSA + (sFilterConfig->FilterIndex * 4U * 2U)); + + /* Write filter element to the message RAM */ + *FilterAddress = FilterElementW1; + FilterAddress++; + *FilterAddress = FilterElementW2; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FDCAN global filter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param NonMatchingStd Defines how received messages with 11-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param NonMatchingExt Defines how received messages with 29-bit IDs that + * do not match any element of the filter list are treated. + * This parameter can be a value of @arg FDCAN_Non_Matching_Frames. + * @param RejectRemoteStd Filter or reject all the remote 11-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @param RejectRemoteExt Filter or reject all the remote 29-bit IDs frames. + * This parameter can be a value of @arg FDCAN_Reject_Remote_Frames. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, + uint32_t NonMatchingStd, + uint32_t NonMatchingExt, + uint32_t RejectRemoteStd, + uint32_t RejectRemoteExt) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingStd)); + assert_param(IS_FDCAN_NON_MATCHING(NonMatchingExt)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteStd)); + assert_param(IS_FDCAN_REJECT_REMOTE(RejectRemoteExt)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure global filter */ + hfdcan->Instance->GFC = ((NonMatchingStd << FDCAN_GFC_ANFS_Pos) | + (NonMatchingExt << FDCAN_GFC_ANFE_Pos) | + (RejectRemoteStd << FDCAN_GFC_RRFS_Pos) | + (RejectRemoteExt << FDCAN_GFC_RRFE_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the extended ID mask. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Mask Extended ID Mask. + * This parameter must be a number between 0 and 0x1FFFFFFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(Mask, 0x1FFFFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the extended ID mask */ + hfdcan->Instance->XIDAM = Mask; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the Rx FIFO operation mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @param OperationMode operation mode. + * This parameter can be a value of @arg FDCAN_Rx_FIFO_operation_mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + assert_param(IS_FDCAN_RX_FIFO_MODE(OperationMode)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + if (RxFifo == FDCAN_RX_FIFO0) + { + /* Select FIFO 0 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode); + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + /* Select FIFO 1 Operation Mode */ + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FIFO watermark. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param FIFO select the FIFO to be configured. + * This parameter can be a value of @arg FDCAN_FIFO_watermark. + * @param Watermark level for FIFO watermark interrupt. + * This parameter must be a number between: + * - 0 and 32, if FIFO is FDCAN_CFG_TX_EVENT_FIFO + * - 0 and 64, if FIFO is FDCAN_CFG_RX_FIFO0 or FDCAN_CFG_RX_FIFO1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_FIFO_WATERMARK(FIFO)); + if (FIFO == FDCAN_CFG_TX_EVENT_FIFO) + { + assert_param(IS_FDCAN_MAX_VALUE(Watermark, 32U)); + } + else /* (FIFO == FDCAN_CFG_RX_FIFO0) || (FIFO == FDCAN_CFG_RX_FIFO1) */ + { + assert_param(IS_FDCAN_MAX_VALUE(Watermark, 64U)); + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Set the level for FIFO watermark interrupt */ + if (FIFO == FDCAN_CFG_TX_EVENT_FIFO) + { + MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFWM, (Watermark << FDCAN_TXEFC_EFWM_Pos)); + } + else if (FIFO == FDCAN_CFG_RX_FIFO0) + { + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0WM, (Watermark << FDCAN_RXF0C_F0WM_Pos)); + } + else /* FIFO == FDCAN_CFG_RX_FIFO1 */ + { + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1WM, (Watermark << FDCAN_RXF1C_F1WM_Pos)); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the RAM watchdog. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param CounterStartValue Start value of the Message RAM Watchdog Counter, + * This parameter must be a number between 0x00 and 0xFF, + * with the reset value of 0x00 the counter is disabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(CounterStartValue, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure the RAM watchdog counter start value */ + MODIFY_REG(hfdcan->Instance->RWD, FDCAN_RWD_WDC, CounterStartValue); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampPrescaler Timestamp Counter Prescaler. + * This parameter can be a value of @arg FDCAN_Timestamp_Prescaler. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP_PRESCALER(TimestampPrescaler)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure prescaler */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TCP, TimestampPrescaler); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimestampOperation Timestamp counter operation. + * This parameter can be a value of @arg FDCAN_Timestamp. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMESTAMP(TimestampOperation)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timestamp counter */ + MODIFY_REG(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS, TimestampOperation); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timestamp counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timestamp counter */ + CLEAR_BIT(hfdcan->Instance->TSCC, FDCAN_TSCC_TSS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timestamp counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Value Timestamp counter value + */ +uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TSCV); +} + +/** + * @brief Reset the timestamp counter to zero. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TSCC & FDCAN_TSCC_TSS) != FDCAN_TIMESTAMP_EXTERNAL) + { + /* Reset timestamp counter. + Actually any write operation to TSCV clears the counter */ + CLEAR_REG(hfdcan->Instance->TSCV); + } + else + { + /* Update error code. + Unable to reset external counter */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimeoutOperation Timeout counter operation. + * This parameter can be a value of @arg FDCAN_Timeout_Operation. + * @param TimeoutPeriod Start value of the timeout down-counter. + * This parameter must be a number between 0x0000 and 0xFFFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation)); + assert_param(IS_FDCAN_MAX_VALUE(TimeoutPeriod, 0xFFFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Select timeout operation and configure period */ + MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos))); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable timeout counter */ + SET_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the timeout counter. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable timeout counter */ + CLEAR_BIT(hfdcan->Instance->TOCC, FDCAN_TOCC_ETOC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Get the timeout counter value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Value Timeout counter value + */ +uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + return (uint16_t)(hfdcan->Instance->TOCV); +} + +/** + * @brief Reset the timeout counter to its start value. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan) +{ + if ((hfdcan->Instance->TOCC & FDCAN_TOCC_TOS) == FDCAN_TIMEOUT_CONTINUOUS) + { + /* Reset timeout counter to start value */ + CLEAR_REG(hfdcan->Instance->TOCV); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Unable to reset counter: controlled only by FIFO empty state */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TdcOffset Transmitter Delay Compensation Offset. + * This parameter must be a number between 0x00 and 0x7F. + * @param TdcFilter Transmitter Delay Compensation Filter Window Length. + * This parameter must be a number between 0x00 and 0x7F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU)); + assert_param(IS_FDCAN_MAX_VALUE(TdcFilter, 0x7FU)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure TDC offset and filter window */ + hfdcan->Instance->TDCR = ((TdcFilter << FDCAN_TDCR_TDCF_Pos) | (TdcOffset << FDCAN_TDCR_TDCO_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable transmitter delay compensation */ + SET_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable the transmitter delay compensation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable transmitter delay compensation */ + CLEAR_BIT(hfdcan->Instance->DBTP, FDCAN_DBTP_TDC); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable ISO 11898-1 protocol mode. + * CAN FD frame format is according to ISO 11898-1 standard. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable Non ISO protocol mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable ISO 11898-1 protocol mode. + * CAN FD frame format is according to Bosch CAN FD specification V1.0. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable Non ISO protocol mode */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_NISO); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Enable edge filtering during bus integration. + * Two consecutive dominant tq are required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Enable edge filtering */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Disable edge filtering during bus integration. + * One dominant tq is required to detect an edge for hard synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Disable edge filtering */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_EFBI); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_Start : Start the FDCAN module + (+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers + (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request + (+) HAL_FDCAN_AddMessageToTxBuffer : Add a message to a dedicated Tx buffer + (+) HAL_FDCAN_EnableTxBufferRequest : Enable transmission request + (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request + (+) HAL_FDCAN_AbortTxRequest : Abort transmission request + (+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM + (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM + (+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status + (+) HAL_FDCAN_GetProtocolStatus : Get protocol status + (+) HAL_FDCAN_GetErrorCounters : Get error counter values + (+) HAL_FDCAN_IsRxBufferMessageAvailable : Check if a new message is received in the selected Rx buffer + (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending on the selected Tx buffer + (+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level + (+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level + (+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode + (+) HAL_FDCAN_ExitRestrictedOperationMode : Exit Restricted Operation Mode + +@endverbatim + * @{ + */ + +/** + * @brief Start the FDCAN module. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan) +{ + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_BUSY; + + /* Request leave initialisation */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Reset the FDCAN ErrorCode */ + hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the FDCAN module and enable access to configuration registers. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Request initialisation */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT); + + /* Wait until the INIT bit into CCCR register is set */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Reset counter */ + Counter = 0U; + + /* Exit from Sleep mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR); + + /* Wait until FDCAN exits sleep mode */ + while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable configuration change */ + SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE); + + /* Reset Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = 0U; + + /* Change FDCAN peripheral state */ + hfdcan->State = HAL_FDCAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData) +{ + uint32_t PutIndex; + + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType)); + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType)); + assert_param(IS_FDCAN_DLC(pTxHeader->DataLength)); + assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator)); + assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch)); + assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat)); + assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl)); + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU)); + + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx FIFO/Queue has an allocated area into the RAM */ + if ((hfdcan->Instance->TXBC & FDCAN_TXBC_TFQS) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Tx FIFO/Queue is not full */ + if ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQF) != 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_FULL; + + return HAL_ERROR; + } + else + { + /* Retrieve the Tx FIFO PutIndex */ + PutIndex = ((hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFQPI) >> FDCAN_TXFQS_TFQPI_Pos); + + /* Add the message to the Tx FIFO/Queue */ + FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, PutIndex); + + /* Activate the corresponding transmission request */ + hfdcan->Instance->TXBAR = ((uint32_t)1 << PutIndex); + + /* Store the Latest Tx FIFO/Queue Request Buffer Index */ + hfdcan->LatestTxFifoQRequest = ((uint32_t)1 << PutIndex); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Add a message to a dedicated Tx buffer + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @param BufferIndex index of the buffer to be configured. + * This parameter can be a value of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_ID_TYPE(pTxHeader->IdType)); + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x7FFU)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_FRAME_TYPE(pTxHeader->TxFrameType)); + assert_param(IS_FDCAN_DLC(pTxHeader->DataLength)); + assert_param(IS_FDCAN_ESI(pTxHeader->ErrorStateIndicator)); + assert_param(IS_FDCAN_BRS(pTxHeader->BitRateSwitch)); + assert_param(IS_FDCAN_FDF(pTxHeader->FDFormat)); + assert_param(IS_FDCAN_EFC(pTxHeader->TxEventFifoControl)); + assert_param(IS_FDCAN_MAX_VALUE(pTxHeader->MessageMarker, 0xFFU)); + assert_param(IS_FDCAN_TX_LOCATION(BufferIndex)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the selected buffer has an allocated area into the RAM */ + if (POSITION_VAL(BufferIndex) >= ((hfdcan->Instance->TXBC & FDCAN_TXBC_NDTB) >> FDCAN_TXBC_NDTB_Pos)) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that there is no transmission request pending for the selected buffer */ + if ((hfdcan->Instance->TXBRP & BufferIndex) != 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + else + { + /* Add the message to the Tx buffer */ + FDCAN_CopyMessageToRAM(hfdcan, pTxHeader, pTxData, POSITION_VAL(BufferIndex)); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable transmission request. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndex buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) +{ + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Add transmission request */ + hfdcan->Instance->TXBAR = BufferIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get Tx buffer index of latest Tx FIFO/Queue request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Tx buffer index of last Tx FIFO/Queue request + * - Any value of @arg FDCAN_Tx_location if Tx request has been submitted. + * - 0 if no Tx FIFO/Queue request have been submitted. + */ +uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan) +{ + /* Return Last Tx FIFO/Queue Request Buffer */ + return hfdcan->LatestTxFifoQRequest; +} + +/** + * @brief Abort transmission request + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndex buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex) +{ + if (hfdcan->State == HAL_FDCAN_STATE_BUSY) + { + /* Add cancellation request */ + hfdcan->Instance->TXBCR = BufferIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxLocation Location of the received message to be read. + * This parameter can be a value of @arg FDCAN_Rx_location. + * @param pRxHeader pointer to a FDCAN_RxHeaderTypeDef structure. + * @param pRxData pointer to a buffer where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData) +{ + uint32_t *RxAddress; + uint8_t *pData; + uint32_t ByteCounter; + uint32_t GetIndex = 0; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if (state == HAL_FDCAN_STATE_BUSY) + { + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 has an allocated area into the RAM */ + if ((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0S) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Rx FIFO 0 is not empty */ + if ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 0 is full & overwrite mode is on*/ + if(((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) + { + if(((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 0 element index*/ + GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + + /* Calculate Rx FIFO 0 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * hfdcan->Init.RxFifo0ElmtSize * 4U)); + } + } + else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 has an allocated area into the RAM */ + if ((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1S) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Rx FIFO 0 is not empty */ + if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + else + { + /* Check that the Rx FIFO 1 is full & overwrite mode is on*/ + if(((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) + { + if(((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) + { + /* When overwrite status is on discard first message in FIFO */ + GetIndex = 1U; + } + } + + /* Calculate Rx FIFO 1 element index*/ + GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + + /* Calculate Rx FIFO 1 element address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * hfdcan->Init.RxFifo1ElmtSize * 4U)); + } + } + else /* Rx element is assigned to a dedicated Rx buffer */ + { + /* Check that the selected buffer has an allocated area into the RAM */ + if (RxLocation >= hfdcan->Init.RxBuffersNbr) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + else + { + /* Calculate Rx buffer address */ + RxAddress = (uint32_t *)(hfdcan->msgRam.RxBufferSA + (RxLocation * hfdcan->Init.RxBufferSize * 4U)); + } + } + + /* Retrieve IdType */ + pRxHeader->IdType = *RxAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18); + } + else /* Extended ID element */ + { + pRxHeader->Identifier = (*RxAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve RxFrameType */ + pRxHeader->RxFrameType = (*RxAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pRxHeader->ErrorStateIndicator = (*RxAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment RxAddress pointer to second word of Rx FIFO element */ + RxAddress++; + + /* Retrieve RxTimestamp */ + pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC); + + /* Retrieve BitRateSwitch */ + pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve FilterIndex */ + pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24); + + /* Retrieve NonMatchingFrame */ + pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31); + + /* Increment RxAddress pointer to payload of Rx FIFO element */ + RxAddress++; + + /* Retrieve Rx payload */ + pData = (uint8_t *)RxAddress; + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++) + { + pRxData[ByteCounter] = pData[ByteCounter]; + } + + if (RxLocation == FDCAN_RX_FIFO0) /* Rx element is assigned to the Rx FIFO 0 */ + { + /* Acknowledge the Rx FIFO 0 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF0A = GetIndex; + } + else if (RxLocation == FDCAN_RX_FIFO1) /* Rx element is assigned to the Rx FIFO 1 */ + { + /* Acknowledge the Rx FIFO 1 that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->RXF1A = GetIndex; + } + else /* Rx element is assigned to a dedicated Rx buffer */ + { + /* Clear the New Data flag of the current Rx buffer */ + if (RxLocation < FDCAN_RX_BUFFER32) + { + hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation); + } + else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */ + { + hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU)); + } + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxEvent pointer to a FDCAN_TxEventFifoTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent) +{ + uint32_t *TxEventAddress; + uint32_t GetIndex; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_MIN_VALUE(hfdcan->Init.TxEventsNbr, 1U)); + + if (state == HAL_FDCAN_STATE_BUSY) + { + /* Check that the Tx Event FIFO has an allocated area into the RAM */ + if ((hfdcan->Instance->TXEFC & FDCAN_TXEFC_EFS) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + + /* Check that the Tx event FIFO is not empty */ + if ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFFL) == 0U) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_FIFO_EMPTY; + + return HAL_ERROR; + } + + /* Calculate Tx event FIFO element address */ + GetIndex = ((hfdcan->Instance->TXEFS & FDCAN_TXEFS_EFGI) >> FDCAN_TXEFS_EFGI_Pos); + TxEventAddress = (uint32_t *)(hfdcan->msgRam.TxEventFIFOSA + (GetIndex * 2U * 4U)); + + /* Retrieve IdType */ + pTxEvent->IdType = *TxEventAddress & FDCAN_ELEMENT_MASK_XTD; + + /* Retrieve Identifier */ + if (pTxEvent->IdType == FDCAN_STANDARD_ID) /* Standard ID element */ + { + pTxEvent->Identifier = ((*TxEventAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U); + } + else /* Extended ID element */ + { + pTxEvent->Identifier = (*TxEventAddress & FDCAN_ELEMENT_MASK_EXTID); + } + + /* Retrieve TxFrameType */ + pTxEvent->TxFrameType = (*TxEventAddress & FDCAN_ELEMENT_MASK_RTR); + + /* Retrieve ErrorStateIndicator */ + pTxEvent->ErrorStateIndicator = (*TxEventAddress & FDCAN_ELEMENT_MASK_ESI); + + /* Increment TxEventAddress pointer to second word of Tx Event FIFO element */ + TxEventAddress++; + + /* Retrieve TxTimestamp */ + pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS); + + /* Retrieve DataLength */ + pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC); + + /* Retrieve BitRateSwitch */ + pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS); + + /* Retrieve FDFormat */ + pTxEvent->FDFormat = (*TxEventAddress & FDCAN_ELEMENT_MASK_FDF); + + /* Retrieve EventType */ + pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET); + + /* Retrieve MessageMarker */ + pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24); + + /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */ + hfdcan->Instance->TXEFA = GetIndex; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Get high priority message status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus) +{ + HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos); + HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos); + HpMsgStatus->MessageStorage = (hfdcan->Instance->HPMS & FDCAN_HPMS_MSI); + HpMsgStatus->MessageIndex = (hfdcan->Instance->HPMS & FDCAN_HPMS_BIDX); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get protocol status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus) +{ + uint32_t StatusReg; + + /* Read the protocol status register */ + StatusReg = READ_REG(hfdcan->Instance->PSR); + + /* Fill the protocol status structure */ + ProtocolStatus->LastErrorCode = (StatusReg & FDCAN_PSR_LEC); + ProtocolStatus->DataLastErrorCode = ((StatusReg & FDCAN_PSR_DLEC) >> FDCAN_PSR_DLEC_Pos); + ProtocolStatus->Activity = (StatusReg & FDCAN_PSR_ACT); + ProtocolStatus->ErrorPassive = ((StatusReg & FDCAN_PSR_EP) >> FDCAN_PSR_EP_Pos); + ProtocolStatus->Warning = ((StatusReg & FDCAN_PSR_EW) >> FDCAN_PSR_EW_Pos); + ProtocolStatus->BusOff = ((StatusReg & FDCAN_PSR_BO) >> FDCAN_PSR_BO_Pos); + ProtocolStatus->RxESIflag = ((StatusReg & FDCAN_PSR_RESI) >> FDCAN_PSR_RESI_Pos); + ProtocolStatus->RxBRSflag = ((StatusReg & FDCAN_PSR_RBRS) >> FDCAN_PSR_RBRS_Pos); + ProtocolStatus->RxFDFflag = ((StatusReg & FDCAN_PSR_REDL) >> FDCAN_PSR_REDL_Pos); + ProtocolStatus->ProtocolException = ((StatusReg & FDCAN_PSR_PXE) >> FDCAN_PSR_PXE_Pos); + ProtocolStatus->TDCvalue = ((StatusReg & FDCAN_PSR_TDCV) >> FDCAN_PSR_TDCV_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get error counter values. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters) +{ + uint32_t CountersReg; + + /* Read the error counters register */ + CountersReg = READ_REG(hfdcan->Instance->ECR); + + /* Fill the error counters structure */ + ErrorCounters->TxErrorCnt = ((CountersReg & FDCAN_ECR_TEC) >> FDCAN_ECR_TEC_Pos); + ErrorCounters->RxErrorCnt = ((CountersReg & FDCAN_ECR_REC) >> FDCAN_ECR_REC_Pos); + ErrorCounters->RxErrorPassive = ((CountersReg & FDCAN_ECR_RP) >> FDCAN_ECR_RP_Pos); + ErrorCounters->ErrorLogging = ((CountersReg & FDCAN_ECR_CEL) >> FDCAN_ECR_CEL_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Check if a new message is received in the selected Rx buffer. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxBufferIndex Rx buffer index. + * This parameter must be a number between 0 and 63. + * @retval Status + * - 0 : No new message on RxBufferIndex. + * - 1 : New message received on RxBufferIndex. + */ +uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_MAX_VALUE(RxBufferIndex, 63U)); + uint32_t NewData1 = hfdcan->Instance->NDAT1; + uint32_t NewData2 = hfdcan->Instance->NDAT2; + + /* Check new message reception on the selected buffer */ + if (((RxBufferIndex < 32U) && ((NewData1 & (uint32_t)((uint32_t)1 << RxBufferIndex)) == 0U)) || + ((RxBufferIndex >= 32U) && ((NewData2 & (uint32_t)((uint32_t)1 << (RxBufferIndex & 0x1FU))) == 0U))) + { + return 0; + } + + /* Clear the New Data flag of the current Rx buffer */ + if (RxBufferIndex < 32U) + { + hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxBufferIndex); + } + else /* 32 <= RxBufferIndex <= 63 */ + { + hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxBufferIndex & 0x1FU)); + } + + return 1; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx buffer. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxBufferIndex Tx buffer index. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval Status + * - 0 : No pending transmission request on TxBufferIndex. + * - 1 : Pending transmission request on TxBufferIndex. + */ +uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) +{ + /* Check pending transmission request on the selected buffer */ + if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) + { + return 0; + } + return 1; +} + +/** + * @brief Return Rx FIFO fill level. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg FDCAN_RX_FIFO0: Rx FIFO 0 + * @arg FDCAN_RX_FIFO1: Rx FIFO 1 + * @retval Level Rx FIFO fill level. + */ +uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo) +{ + uint32_t FillLevel; + + /* Check function parameters */ + assert_param(IS_FDCAN_RX_FIFO(RxFifo)); + + if (RxFifo == FDCAN_RX_FIFO0) + { + FillLevel = hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0FL; + } + else /* RxFifo == FDCAN_RX_FIFO1 */ + { + FillLevel = hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL; + } + + /* Return Rx FIFO fill level */ + return FillLevel; +} + +/** + * @brief Return Tx FIFO free level: number of consecutive free Tx FIFO + * elements starting from Tx FIFO GetIndex. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Level Tx FIFO free level. + */ +uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t FreeLevel; + + FreeLevel = hfdcan->Instance->TXFQS & FDCAN_TXFQS_TFFL; + + /* Return Tx FIFO free level */ + return FreeLevel; +} + +/** + * @brief Check if the FDCAN peripheral entered Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval Status + * - 0 : Normal FDCAN operation. + * - 1 : Restricted Operation Mode active. + */ +uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t OperationMode; + + /* Get Operation Mode */ + OperationMode = ((hfdcan->Instance->CCCR & FDCAN_CCCR_ASM) >> FDCAN_CCCR_ASM_Pos); + + return OperationMode; +} + +/** + * @brief Exit Restricted Operation Mode. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Exit Restricted Operation mode */ + CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions + * @brief TT Configuration and control functions + * +@verbatim + ============================================================================== + ##### TT Configuration and control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_TT_ConfigOperation : Initialize TT operation parameters + (+) HAL_FDCAN_TT_ConfigReferenceMessage : Configure the reference message + (+) HAL_FDCAN_TT_ConfigTrigger : Configure the FDCAN trigger + (+) HAL_FDCAN_TT_SetGlobalTime : Schedule global time adjustment + (+) HAL_FDCAN_TT_SetClockSynchronization : Schedule TUR numerator update + (+) HAL_FDCAN_TT_ConfigStopWatch : Configure stop watch source and polarity + (+) HAL_FDCAN_TT_ConfigRegisterTimeMark : Configure register time mark pulse generation + (+) HAL_FDCAN_TT_EnableRegisterTimeMarkPulse : Enable register time mark pulse generation + (+) HAL_FDCAN_TT_DisableRegisterTimeMarkPulse : Disable register time mark pulse generation + (+) HAL_FDCAN_TT_EnableTriggerTimeMarkPulse : Enable trigger time mark pulse generation + (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse : Disable trigger time mark pulse generation + (+) HAL_FDCAN_TT_EnableHardwareGapControl : Enable gap control by input pin fdcan1_evt + (+) HAL_FDCAN_TT_DisableHardwareGapControl : Disable gap control by input pin fdcan1_evt + (+) HAL_FDCAN_TT_EnableTimeMarkGapControl : Enable gap control (finish only) by register time mark interrupt + (+) HAL_FDCAN_TT_DisableTimeMarkGapControl : Disable gap control by register time mark interrupt + (+) HAL_FDCAN_TT_SetNextIsGap : Transmit next reference message with Next_is_Gap = "1" + (+) HAL_FDCAN_TT_SetEndOfGap : Finish a Gap by requesting start of reference message + (+) HAL_FDCAN_TT_ConfigExternalSyncPhase : Configure target phase used for external synchronization + (+) HAL_FDCAN_TT_EnableExternalSynchronization : Synchronize the phase of the FDCAN schedule to an external schedule + (+) HAL_FDCAN_TT_DisableExternalSynchronization : Disable external schedule synchronization + (+) HAL_FDCAN_TT_GetOperationStatus : Get TT operation status + +@endverbatim + * @{ + */ + +/** + * @brief Initialize TT operation parameters. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams) +{ + uint32_t tickstart; + uint32_t RAMcounter; + uint32_t StartAddress; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_TUR_NUMERATOR(pTTParams->TURNumerator)); + assert_param(IS_FDCAN_TT_TUR_DENOMINATOR(pTTParams->TURDenominator)); + assert_param(IS_FDCAN_TT_TIME_MASTER(pTTParams->TimeMaster)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->SyncDevLimit, 7U)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->InitRefTrigOffset, 127U)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->TriggerMemoryNbr, 64U)); + assert_param(IS_FDCAN_TT_CYCLE_START_SYNC(pTTParams->CycleStartSync)); + assert_param(IS_FDCAN_TT_STOP_WATCH_TRIGGER(pTTParams->StopWatchTrigSel)); + assert_param(IS_FDCAN_TT_EVENT_TRIGGER(pTTParams->EventTrigSel)); + if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER) + { + assert_param(IS_FDCAN_TT_BASIC_CYCLES_NUMBER(pTTParams->BasicCyclesNbr)); + } + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + assert_param(IS_FDCAN_TT_OPERATION(pTTParams->GapEnable)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->AppWdgLimit, 255U)); + assert_param(IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(pTTParams->EvtTrigPolarity)); + assert_param(IS_FDCAN_TT_TX_ENABLE_WINDOW(pTTParams->TxEnableWindow)); + assert_param(IS_FDCAN_MAX_VALUE(pTTParams->ExpTxTrigNbr, 4095U)); + } + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1) + { + assert_param(IS_FDCAN_TT_TUR_LEVEL_0_2(pTTParams->TURNumerator, pTTParams->TURDenominator)); + assert_param(IS_FDCAN_TT_EXTERNAL_CLK_SYNC(pTTParams->ExternalClkSync)); + assert_param(IS_FDCAN_TT_GLOBAL_TIME_FILTERING(pTTParams->GlobalTimeFilter)); + assert_param(IS_FDCAN_TT_AUTO_CLK_CALIBRATION(pTTParams->ClockCalibration)); + } + else + { + assert_param(IS_FDCAN_TT_TUR_LEVEL_1(pTTParams->TURNumerator, pTTParams->TURDenominator)); + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Stop local time in order to enable write access to the other bits of TURCF register */ + CLEAR_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the ELT bit into TURCF register is reset */ + while ((hfdcan->ttcan->TURCF & FDCAN_TURCF_ELT) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Configure TUR (Time Unit Ratio) */ + MODIFY_REG(hfdcan->ttcan->TURCF, + (FDCAN_TURCF_NCL | FDCAN_TURCF_DC), + (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos))); + + /* Enable local time */ + SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT); + + /* Configure TT operation */ + MODIFY_REG(hfdcan->ttcan->TTOCF, + (FDCAN_TTOCF_OM | FDCAN_TTOCF_TM | FDCAN_TTOCF_LDSDL | FDCAN_TTOCF_IRTO), + (pTTParams->OperationMode | \ + pTTParams->TimeMaster | \ + (pTTParams->SyncDevLimit << FDCAN_TTOCF_LDSDL_Pos) | \ + (pTTParams->InitRefTrigOffset << FDCAN_TTOCF_IRTO_Pos))); + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + MODIFY_REG(hfdcan->ttcan->TTOCF, + (FDCAN_TTOCF_GEN | FDCAN_TTOCF_AWL | FDCAN_TTOCF_EVTP), + (pTTParams->GapEnable | \ + (pTTParams->AppWdgLimit << FDCAN_TTOCF_AWL_Pos) | \ + pTTParams->EvtTrigPolarity)); + } + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL1) + { + MODIFY_REG(hfdcan->ttcan->TTOCF, + (FDCAN_TTOCF_EECS | FDCAN_TTOCF_EGTF | FDCAN_TTOCF_ECC), + (pTTParams->ExternalClkSync | \ + pTTParams->GlobalTimeFilter | \ + pTTParams->ClockCalibration)); + } + + /* Configure system matrix limits */ + MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CSS, pTTParams->CycleStartSync); + if (pTTParams->OperationMode != FDCAN_TT_COMMUNICATION_LEVEL0) + { + MODIFY_REG(hfdcan->ttcan->TTMLM, + (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT), + (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos))); + } + if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER) + { + MODIFY_REG(hfdcan->ttcan->TTMLM, FDCAN_TTMLM_CCM, pTTParams->BasicCyclesNbr); + } + + /* Configure input triggers: Stop watch and Event */ + MODIFY_REG(hfdcan->ttcan->TTTS, + (FDCAN_TTTS_SWTSEL | FDCAN_TTTS_EVTSEL), + (pTTParams->StopWatchTrigSel | pTTParams->EventTrigSel)); + + /* Configure trigger memory start address */ + StartAddress = (hfdcan->msgRam.EndAddress - SRAMCAN_BASE) / 4U; + MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TMSA, (StartAddress << FDCAN_TTTMC_TMSA_Pos)); + + /* Trigger memory elements number */ + MODIFY_REG(hfdcan->ttcan->TTTMC, FDCAN_TTTMC_TME, (pTTParams->TriggerMemoryNbr << FDCAN_TTTMC_TME_Pos)); + + /* Recalculate End Address */ + hfdcan->msgRam.TTMemorySA = hfdcan->msgRam.EndAddress; + hfdcan->msgRam.EndAddress = hfdcan->msgRam.TTMemorySA + (pTTParams->TriggerMemoryNbr * 2U * 4U); + + if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */ + { + /* Update error code. + Message RAM overflow */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + return HAL_ERROR; + } + else + { + /* Flush the allocated Message RAM area */ + for (RAMcounter = hfdcan->msgRam.TTMemorySA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) + { + *(uint32_t *)(RAMcounter) = 0x00000000; + } + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param IdType Identifier Type. + * This parameter can be a value of @arg FDCAN_id_type. + * @param Identifier Reference Identifier. + * This parameter must be a number between: + * - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + * - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + * @param Payload Enable or disable the additional payload. + * This parameter can be a value of @arg FDCAN_TT_Reference_Message_Payload. + * This parameter is ignored in case of time slaves. + * If this parameter is set to FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD, the + * following elements are taken from Tx Buffer 0: + * - MessageMarker + * - TxEventFifoControl + * - DataLength + * - Data Bytes (payload): + * - bytes 2-8, for Level 1 + * - bytes 5-8, for Level 0 and Level 2 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_ID_TYPE(IdType)); + if (IdType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x7FFU)); + } + else /* IdType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(Identifier, 0x1FFFFFFFU)); + } + assert_param(IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(Payload)); + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Configure reference message identifier type, identifier and payload */ + if (IdType == FDCAN_EXTENDED_ID) + { + MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier)); + } + else /* IdType == FDCAN_STANDARD_ID */ + { + MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18))); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Configure the FDCAN trigger according to the specified + * parameters in the FDCAN_TriggerTypeDef structure. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param sTriggerConfig pointer to an FDCAN_TriggerTypeDef structure that + * contains the trigger configuration information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig) +{ + uint32_t CycleCode; + uint32_t MessageNumber; + uint32_t TriggerElementW1; + uint32_t TriggerElementW2; + uint32_t *TriggerAddress; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TriggerIndex, 63U)); + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->TimeMark, 0xFFFFU)); + assert_param(IS_FDCAN_TT_REPEAT_FACTOR(sTriggerConfig->RepeatFactor)); + if (sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE) + { + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->StartCycle, (sTriggerConfig->RepeatFactor - 1U))); + } + assert_param(IS_FDCAN_TT_TM_EVENT_INTERNAL(sTriggerConfig->TmEventInt)); + assert_param(IS_FDCAN_TT_TM_EVENT_EXTERNAL(sTriggerConfig->TmEventExt)); + assert_param(IS_FDCAN_TT_TRIGGER_TYPE(sTriggerConfig->TriggerType)); + assert_param(IS_FDCAN_ID_TYPE(sTriggerConfig->FilterType)); + if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED)) + { + assert_param(IS_FDCAN_TX_LOCATION(sTriggerConfig->TxBufferIndex)); + } + if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER) + { + if (sTriggerConfig->FilterType == FDCAN_STANDARD_ID) + { + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 63U)); + } + else /* sTriggerConfig->FilterType == FDCAN_EXTENDED_ID */ + { + assert_param(IS_FDCAN_MAX_VALUE(sTriggerConfig->FilterIndex, 127U)); + } + } + + if (hfdcan->State == HAL_FDCAN_STATE_READY) + { + /* Calculate cycle code */ + if (sTriggerConfig->RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE) + { + CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE; + } + else /* sTriggerConfig->RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */ + { + CycleCode = sTriggerConfig->RepeatFactor + sTriggerConfig->StartCycle; + } + + /* Build first word of trigger element */ + TriggerElementW1 = ((sTriggerConfig->TimeMark << 16) | \ + (CycleCode << 8) | \ + sTriggerConfig->TmEventInt | \ + sTriggerConfig->TmEventExt | \ + sTriggerConfig->TriggerType); + + /* Select message number depending on trigger type (transmission or reception) */ + if (sTriggerConfig->TriggerType == FDCAN_TT_RX_TRIGGER) + { + MessageNumber = sTriggerConfig->FilterIndex; + } + else if ((sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_SINGLE) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_CONTINUOUS) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_ARBITRATION) || + (sTriggerConfig->TriggerType == FDCAN_TT_TX_TRIGGER_MERGED)) + { + MessageNumber = POSITION_VAL(sTriggerConfig->TxBufferIndex); + } + else + { + MessageNumber = 0U; + } + + /* Build second word of trigger element */ + TriggerElementW2 = ((sTriggerConfig->FilterType >> 7) | (MessageNumber << 16)); + + /* Calculate trigger address */ + TriggerAddress = (uint32_t *)(hfdcan->msgRam.TTMemorySA + (sTriggerConfig->TriggerIndex * 4U * 2U)); + + /* Write trigger element to the message RAM */ + *TriggerAddress = TriggerElementW1; + TriggerAddress++; + *TriggerAddress = TriggerElementW2; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Schedule global time adjustment for the next reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimePreset time preset value. + * This parameter must be a number between: + * - 0x0000 and 0x7FFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark + TimePreset + * or + * - 0x8001 and 0xFFFF, Next_Master_Ref_Mark = Current_Master_Ref_Mark - (0x10000 - TimePreset) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_TIME_PRESET(TimePreset)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the external clock synchronization is enabled */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Check that no global time preset is pending */ + if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WGTD) == FDCAN_TTOST_WGTD) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + + /* Configure time preset */ + MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_TP, (TimePreset << FDCAN_TTGTP_TP_Pos)); + + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Schedule time preset to take effect by the next reference message */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_SGT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Schedule TUR numerator update for the next reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param NewTURNumerator new value of the TUR numerator. + * This parameter must be a number between 0x10000 and 0x1FFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_TUR_NUMERATOR(NewTURNumerator)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the external clock synchronization is enabled */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_EECS) != FDCAN_TTOCF_EECS) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Check that no external clock synchronization is pending */ + if ((hfdcan->ttcan->TTOST & FDCAN_TTOST_WECS) == FDCAN_TTOST_WECS) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + + /* Configure new TUR numerator */ + MODIFY_REG(hfdcan->ttcan->TURCF, FDCAN_TURCF_NCL, (NewTURNumerator - 0x10000U)); + + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Schedule TUR numerator update by the next reference message */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ECS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure stop watch source and polarity. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param Source stop watch source. + * This parameter can be a value of @arg FDCAN_TT_stop_watch_source. + * @param Polarity stop watch polarity. + * This parameter can be a value of @arg FDCAN_TT_stop_watch_polarity. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_STOP_WATCH_SOURCE(Source)); + assert_param(IS_FDCAN_TT_STOP_WATCH_POLARITY(Polarity)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Select stop watch source and polarity */ + MODIFY_REG(hfdcan->ttcan->TTOCN, (FDCAN_TTOCN_SWS | FDCAN_TTOCN_SWP), (Source | Polarity)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure register time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TimeMarkSource time mark source. + * This parameter can be a value of @arg FDCAN_TT_time_mark_source. + * @param TimeMarkValue time mark value (reference). + * This parameter must be a number between 0 and 0xFFFF. + * @param RepeatFactor repeat factor of the cycle for which the time mark is valid. + * This parameter can be a value of @arg FDCAN_TT_Repeat_Factor. + * @param StartCycle index of the first cycle in which the time mark becomes valid. + * This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. + * This parameter must be a number between 0 and RepeatFactor. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, + uint32_t TimeMarkSource, uint32_t TimeMarkValue, + uint32_t RepeatFactor, uint32_t StartCycle) +{ + uint32_t Counter = 0U; + uint32_t CycleCode; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(TimeMarkSource)); + assert_param(IS_FDCAN_MAX_VALUE(TimeMarkValue, 0xFFFFU)); + assert_param(IS_FDCAN_TT_REPEAT_FACTOR(RepeatFactor)); + if (RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE) + { + assert_param(IS_FDCAN_MAX_VALUE(StartCycle, (RepeatFactor - 1U))); + } + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable the time mark compare function */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC); + + if (TimeMarkSource != FDCAN_TT_REG_TIMEMARK_DIABLED) + { + /* Calculate cycle code */ + if (RepeatFactor == FDCAN_TT_REPEAT_EVERY_CYCLE) + { + CycleCode = FDCAN_TT_REPEAT_EVERY_CYCLE; + } + else /* RepeatFactor != FDCAN_TT_REPEAT_EVERY_CYCLE */ + { + CycleCode = RepeatFactor + StartCycle; + } + + Counter = 0U; + + /* Wait until the LCKM bit into TTTMK register is reset */ + while ((hfdcan->ttcan->TTTMK & FDCAN_TTTMK_LCKM) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Configure time mark value and cycle code */ + hfdcan->ttcan->TTTMK = ((TimeMarkValue << FDCAN_TTTMK_TM_Pos) | (CycleCode << FDCAN_TTTMK_TICC_Pos)); + + Counter = 0U; + + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Update the register time mark compare source */ + MODIFY_REG(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMC, TimeMarkSource); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable register time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable Register Time Mark Interrupt output on fdcan1_rtp */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable register time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable Register Time Mark Interrupt output on fdcan1_rtp */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_RTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable trigger time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable Trigger Time Mark Interrupt output on fdcan1_tmp */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable trigger time mark pulse generation. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable Trigger Time Mark Interrupt output on fdcan1_rtp */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TTIE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable gap control by input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable gap control by pin fdcan1_evt */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable gap control by input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable gap control by pin fdcan1_evt */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_GCS); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable gap control (finish only) by register time mark interrupt. + * The next register time mark interrupt (TTIR.RTMI = "1") will finish + * the Gap and start the reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable gap control by register time mark interrupt */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable gap control by register time mark interrupt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable gap control by register time mark interrupt */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_TMG); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Transmit next reference message with Next_is_Gap = "1". + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the node is configured for external event-synchronized TT operation */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Set Next is Gap */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_NIG); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Finish a Gap by requesting start of reference message. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that the node is configured for external event-synchronized TT operation */ + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_GEN) != FDCAN_TTOCF_GEN) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != FDCAN_TT_COMMUNICATION_LEVEL0) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Set Finish Gap */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_FGP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code. + Feature not supported for TT Level 0 */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Configure target phase used for external synchronization by event + * trigger input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TargetPhase defines target value of cycle time when a rising edge + * of fdcan1_evt is expected. + * This parameter must be a number between 0 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_MAX_VALUE(TargetPhase, 0xFFFFU)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Check that no external schedule synchronization is pending */ + if ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_ESCN) == FDCAN_TTOCN_ESCN) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PENDING; + + return HAL_ERROR; + } + + /* Configure cycle time target phase */ + MODIFY_REG(hfdcan->ttcan->TTGTP, FDCAN_TTGTP_CTP, (TargetPhase << FDCAN_TTGTP_CTP_Pos)); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Synchronize the phase of the FDCAN schedule to an external schedule + * using event trigger input pin fdcan1_evt. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Enable external synchronization */ + SET_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable external schedule synchronization. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t Counter = 0U; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Wait until the LCKC bit into TTOCN register is reset */ + while ((hfdcan->ttcan->TTOCN & FDCAN_TTOCN_LCKC) != 0U) + { + /* Check for the Timeout */ + if (Counter > FDCAN_TIMEOUT_COUNT) + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + + /* Increment counter */ + Counter++; + } + + /* Disable external synchronization */ + CLEAR_BIT(hfdcan->ttcan->TTOCN, FDCAN_TTOCN_ESCN); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Get TT operation status. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus) +{ + uint32_t TTStatusReg; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + + /* Read the TT operation status register */ + TTStatusReg = READ_REG(hfdcan->ttcan->TTOST); + + /* Fill the TT operation status structure */ + TTOpStatus->ErrorLevel = (TTStatusReg & FDCAN_TTOST_EL); + TTOpStatus->MasterState = (TTStatusReg & FDCAN_TTOST_MS); + TTOpStatus->SyncState = (TTStatusReg & FDCAN_TTOST_SYS); + TTOpStatus->GTimeQuality = ((TTStatusReg & FDCAN_TTOST_QGTP) >> FDCAN_TTOST_QGTP_Pos); + TTOpStatus->ClockQuality = ((TTStatusReg & FDCAN_TTOST_QCS) >> FDCAN_TTOST_QCS_Pos); + TTOpStatus->RefTrigOffset = ((TTStatusReg & FDCAN_TTOST_RTO) >> FDCAN_TTOST_RTO_Pos); + TTOpStatus->GTimeDiscPending = ((TTStatusReg & FDCAN_TTOST_WGTD) >> FDCAN_TTOST_WGTD_Pos); + TTOpStatus->GapFinished = ((TTStatusReg & FDCAN_TTOST_GFI) >> FDCAN_TTOST_GFI_Pos); + TTOpStatus->MasterPriority = ((TTStatusReg & FDCAN_TTOST_TMP) >> FDCAN_TTOST_TMP_Pos); + TTOpStatus->GapStarted = ((TTStatusReg & FDCAN_TTOST_GSI) >> FDCAN_TTOST_GSI_Pos); + TTOpStatus->WaitForEvt = ((TTStatusReg & FDCAN_TTOST_WFE) >> FDCAN_TTOST_WFE_Pos); + TTOpStatus->AppWdgEvt = ((TTStatusReg & FDCAN_TTOST_AWE) >> FDCAN_TTOST_AWE_Pos); + TTOpStatus->ECSPending = ((TTStatusReg & FDCAN_TTOST_WECS) >> FDCAN_TTOST_WECS_Pos); + TTOpStatus->PhaseLock = ((TTStatusReg & FDCAN_TTOST_SPL) >> FDCAN_TTOST_SPL_Pos); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_FDCAN_ConfigInterruptLines : Assign interrupts to either Interrupt line 0 or 1 + (+) HAL_FDCAN_TT_ConfigInterruptLines : Assign TT interrupts to either Interrupt line 0 or 1 + (+) HAL_FDCAN_ActivateNotification : Enable interrupts + (+) HAL_FDCAN_DeactivateNotification : Disable interrupts + (+) HAL_FDCAN_TT_ActivateNotification : Enable TT interrupts + (+) HAL_FDCAN_TT_DeactivateNotification : Disable TT interrupts + (+) HAL_FDCAN_IRQHandler : Handles FDCAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Assign interrupts to either Interrupt line 0 or 1. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ITList indicates which interrupts will be assigned to the selected interrupt line. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @param InterruptLine Interrupt line. + * This parameter can be a value of @arg FDCAN_Interrupt_Line. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(ITList)); + assert_param(IS_FDCAN_IT_LINE(InterruptLine)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Assign list of interrupts to the selected line */ + if (InterruptLine == FDCAN_INTERRUPT_LINE0) + { + CLEAR_BIT(hfdcan->Instance->ILS, ITList); + } + else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */ + { + SET_BIT(hfdcan->Instance->ILS, ITList); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Assign TT interrupts to either Interrupt line 0 or 1. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTITList indicates which interrupts will be assigned to the selected interrupt line. + * This parameter can be any combination of @arg FDCAN_TTInterrupts. + * @param InterruptLine Interrupt line. + * This parameter can be a value of @arg FDCAN_Interrupt_Line. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_IT(TTITList)); + assert_param(IS_FDCAN_IT_LINE(InterruptLine)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Assign list of interrupts to the selected line */ + if (InterruptLine == FDCAN_INTERRUPT_LINE0) + { + CLEAR_BIT(hfdcan->ttcan->TTILS, TTITList); + } + else /* InterruptLine == FDCAN_INTERRUPT_LINE1 */ + { + SET_BIT(hfdcan->ttcan->TTILS, TTITList); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @param BufferIndexes Tx Buffer Indexes. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * This parameter is ignored if ActiveITs does not include one of the following: + * - FDCAN_IT_TX_COMPLETE + * - FDCAN_IT_TX_ABORT_COMPLETE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(ActiveITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Enable Interrupt lines */ + if ((ActiveITs & hfdcan->Instance->ILS) == 0U) + { + /* Enable Interrupt line 0 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + else if ((ActiveITs & hfdcan->Instance->ILS) == ActiveITs) + { + /* Enable Interrupt line 1 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + else + { + /* Enable Interrupt lines 0 and 1 */ + hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1); + } + + if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, + but interrupt will only occur if TC is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes); + } + + if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, + but interrupt will only occur if TCF is enabled in IE register */ + SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes); + } + + /* Enable the selected interrupts */ + __HAL_FDCAN_ENABLE_IT(hfdcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg FDCAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs) +{ + uint32_t ITLineSelection; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_IT(InactiveITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Disable the selected interrupts */ + __HAL_FDCAN_DISABLE_IT(hfdcan, InactiveITs); + + if ((InactiveITs & FDCAN_IT_TX_COMPLETE) != 0U) + { + /* Disable Tx Buffer Transmission Interrupts */ + CLEAR_REG(hfdcan->Instance->TXBTIE); + } + + if ((InactiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) + { + /* Disable Tx Buffer Cancellation Finished Interrupt */ + CLEAR_REG(hfdcan->Instance->TXBCIE); + } + + ITLineSelection = hfdcan->Instance->ILS; + + if ((hfdcan->Instance->IE | ITLineSelection) == ITLineSelection) + { + /* Disable Interrupt line 0 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + + if ((hfdcan->Instance->IE & ITLineSelection) == 0U) + { + /* Disable Interrupt line 1 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Enable TT interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ActiveTTITs indicates which TT interrupts will be enabled. + * This parameter can be any combination of @arg FDCAN_TTInterrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs) +{ + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_IT(ActiveTTITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Enable Interrupt lines */ + if ((ActiveTTITs & hfdcan->ttcan->TTILS) == 0U) + { + /* Enable Interrupt line 0 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + else if ((ActiveTTITs & hfdcan->ttcan->TTILS) == ActiveTTITs) + { + /* Enable Interrupt line 1 */ + SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + else + { + /* Enable Interrupt lines 0 and 1 */ + hfdcan->Instance->ILE = (FDCAN_INTERRUPT_LINE0 | FDCAN_INTERRUPT_LINE1); + } + + /* Enable the selected TT interrupts */ + __HAL_FDCAN_TT_ENABLE_IT(hfdcan, ActiveTTITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable TT interrupts. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param InactiveTTITs indicates which TT interrupts will be disabled. + * This parameter can be any combination of @arg FDCAN_TTInterrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs) +{ + uint32_t ITLineSelection; + HAL_FDCAN_StateTypeDef state = hfdcan->State; + + /* Check function parameters */ + assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance)); + assert_param(IS_FDCAN_TT_IT(InactiveTTITs)); + + if ((state == HAL_FDCAN_STATE_READY) || (state == HAL_FDCAN_STATE_BUSY)) + { + /* Disable the selected TT interrupts */ + __HAL_FDCAN_TT_DISABLE_IT(hfdcan, InactiveTTITs); + + ITLineSelection = hfdcan->ttcan->TTILS; + + if ((hfdcan->ttcan->TTIE | ITLineSelection) == ITLineSelection) + { + /* Disable Interrupt line 0 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0); + } + + if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U) + { + /* Disable Interrupt line 1 */ + CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles FDCAN interrupt request. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t ClkCalibrationITs; + uint32_t TxEventFifoITs; + uint32_t RxFifo0ITs; + uint32_t RxFifo1ITs; + uint32_t Errors; + uint32_t ErrorStatusITs; + uint32_t TransmittedBuffers; + uint32_t AbortedBuffers; + uint32_t TTSchedSyncITs; + uint32_t TTTimeMarkITs; + uint32_t TTGlobTimeITs; + uint32_t TTDistErrors; + uint32_t TTFatalErrors; + uint32_t SWTime; + uint32_t SWCycleCount; + uint32_t itsourceIE; + uint32_t itsourceTTIE; + uint32_t itflagIR; + uint32_t itflagTTIR; + + ClkCalibrationITs = (FDCAN_CCU->IR << 30); + ClkCalibrationITs &= (FDCAN_CCU->IE << 30); + TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK; + TxEventFifoITs &= hfdcan->Instance->IE; + RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK; + RxFifo0ITs &= hfdcan->Instance->IE; + RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK; + RxFifo1ITs &= hfdcan->Instance->IE; + Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK; + Errors &= hfdcan->Instance->IE; + ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK; + ErrorStatusITs &= hfdcan->Instance->IE; + itsourceIE = hfdcan->Instance->IE; + itflagIR = hfdcan->Instance->IR; + + /* High Priority Message interrupt management *******************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET) + { + /* Clear the High Priority Message flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->HighPriorityMessageCallback(hfdcan); +#else + /* High Priority Message Callback */ + HAL_FDCAN_HighPriorityMessageCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Abort interrupt management **********************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET) + { + /* List of aborted monitored buffers */ + AbortedBuffers = hfdcan->Instance->TXBCF; + AbortedBuffers &= hfdcan->Instance->TXBCIE; + + /* Clear the Transmission Cancellation flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferAbortCallback(hfdcan, AbortedBuffers); +#else + /* Transmission Cancellation Callback */ + HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Clock calibration unit interrupts management *****************************/ + if (ClkCalibrationITs != 0U) + { + /* Clear the Clock Calibration flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ClockCalibrationCallback(hfdcan, ClkCalibrationITs); +#else + /* Clock Calibration Callback */ + HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Tx event FIFO interrupts management **************************************/ + if (TxEventFifoITs != 0U) + { + /* Clear the Tx Event FIFO flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxEventFifoCallback(hfdcan, TxEventFifoITs); +#else + /* Tx Event FIFO Callback */ + HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 0 interrupts management ******************************************/ + if (RxFifo0ITs != 0U) + { + /* Clear the Rx FIFO 0 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo0Callback(hfdcan, RxFifo0ITs); +#else + /* Rx FIFO 0 Callback */ + HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Rx FIFO 1 interrupts management ******************************************/ + if (RxFifo1ITs != 0U) + { + /* Clear the Rx FIFO 1 flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxFifo1Callback(hfdcan, RxFifo1ITs); +#else + /* Rx FIFO 1 Callback */ + HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Tx FIFO empty interrupt management ***************************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET) + { + /* Clear the Tx FIFO empty flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxFifoEmptyCallback(hfdcan); +#else + /* Tx FIFO empty Callback */ + HAL_FDCAN_TxFifoEmptyCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Transmission Complete interrupt management *******************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET) + { + /* List of transmitted monitored buffers */ + TransmittedBuffers = hfdcan->Instance->TXBTO; + TransmittedBuffers &= hfdcan->Instance->TXBTIE; + + /* Clear the Transmission Complete flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#else + /* Transmission Complete Callback */ + HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Rx Buffer New Message interrupt management *******************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET) + { + /* Clear the Rx Buffer New Message flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->RxBufferNewMessageCallback(hfdcan); +#else + /* Rx Buffer New Message Callback */ + HAL_FDCAN_RxBufferNewMessageCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timestamp Wraparound interrupt management ********************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET) + { + /* Clear the Timestamp Wraparound flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimestampWraparoundCallback(hfdcan); +#else + /* Timestamp Wraparound Callback */ + HAL_FDCAN_TimestampWraparoundCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Timeout Occurred interrupt management ************************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET) + { + /* Clear the Timeout Occurred flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TimeoutOccurredCallback(hfdcan); +#else + /* Timeout Occurred Callback */ + HAL_FDCAN_TimeoutOccurredCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* Message RAM access failure interrupt management **************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET) + { + /* Clear the Message RAM access failure flag */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE); + + /* Update error code */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS; + } + } + + /* Error Status interrupts management ***************************************/ + if (ErrorStatusITs != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs); +#else + /* Error Status Callback */ + HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* Error interrupts management **********************************************/ + if (Errors != 0U) + { + /* Clear the Error flags */ + __HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors); + + /* Update error code */ + hfdcan->ErrorCode |= Errors; + } + + if (hfdcan->Instance == FDCAN1) + { + if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U) + { + TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK; + TTSchedSyncITs &= hfdcan->ttcan->TTIE; + TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK; + TTTimeMarkITs &= hfdcan->ttcan->TTIE; + TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK; + TTGlobTimeITs &= hfdcan->ttcan->TTIE; + TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK; + TTDistErrors &= hfdcan->ttcan->TTIE; + TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK; + TTFatalErrors &= hfdcan->ttcan->TTIE; + itsourceTTIE = hfdcan->ttcan->TTIE; + itflagTTIR = hfdcan->ttcan->TTIR; + + /* TT Schedule Synchronization interrupts management **********************/ + if (TTSchedSyncITs != 0U) + { + /* Clear the TT Schedule Synchronization flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); +#else + /* TT Schedule Synchronization Callback */ + HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* TT Time Mark interrupts management *************************************/ + if (TTTimeMarkITs != 0U) + { + /* Clear the TT Time Mark flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); +#else + /* TT Time Mark Callback */ + HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* TT Stop Watch interrupt management *************************************/ + if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET) + { + if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET) + { + /* Retrieve Stop watch Time and Cycle count */ + SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos); + SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos); + + /* Clear the TT Stop Watch flag */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); +#else + /* TT Stop Watch Callback */ + HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + } + + /* TT Global Time interrupts management ***********************************/ + if (TTGlobTimeITs != 0U) + { + /* Clear the TT Global Time flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs); + +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); +#else + /* TT Global Time Callback */ + HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } + + /* TT Disturbing Error interrupts management ******************************/ + if (TTDistErrors != 0U) + { + /* Clear the TT Disturbing Error flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors); + + /* Update error code */ + hfdcan->ErrorCode |= TTDistErrors; + } + + /* TT Fatal Error interrupts management ***********************************/ + if (TTFatalErrors != 0U) + { + /* Clear the TT Fatal Error flags */ + __HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors); + + /* Update error code */ + hfdcan->ErrorCode |= TTFatalErrors; + } + } + } + + if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE) + { +#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hfdcan->ErrorCallback(hfdcan); +#else + /* Error Callback */ + HAL_FDCAN_ErrorCallback(hfdcan); +#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group6 Callback functions + * @brief FDCAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_FDCAN_ClockCalibrationCallback + (+) HAL_FDCAN_TxEventFifoCallback + (+) HAL_FDCAN_RxFifo0Callback + (+) HAL_FDCAN_RxFifo1Callback + (+) HAL_FDCAN_TxFifoEmptyCallback + (+) HAL_FDCAN_TxBufferCompleteCallback + (+) HAL_FDCAN_TxBufferAbortCallback + (+) HAL_FDCAN_RxBufferNewMessageCallback + (+) HAL_FDCAN_HighPriorityMessageCallback + (+) HAL_FDCAN_TimestampWraparoundCallback + (+) HAL_FDCAN_TimeoutOccurredCallback + (+) HAL_FDCAN_ErrorCallback + (+) HAL_FDCAN_ErrorStatusCallback + (+) HAL_FDCAN_TT_ScheduleSyncCallback + (+) HAL_FDCAN_TT_TimeMarkCallback + (+) HAL_FDCAN_TT_StopWatchCallback + (+) HAL_FDCAN_TT_GlobalTimeCallback + +@endverbatim + * @{ + */ + +/** + * @brief Clock Calibration callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ClkCalibrationITs indicates which Clock Calibration interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Clock_Calibration_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(ClkCalibrationITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Event callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TxEventFifoITs indicates which Tx Event FIFO interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Tx_Event_Fifo_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TxEventFifoITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 0 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo0ITs indicates which Rx FIFO 0 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo0_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo0ITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo0Callback could be implemented in the user file + */ +} + +/** + * @brief Rx FIFO 1 callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param RxFifo1ITs indicates which Rx FIFO 1 interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Rx_Fifo1_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(RxFifo1ITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxFifo1Callback could be implemented in the user file + */ +} + +/** + * @brief Tx FIFO Empty callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Complete callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the transmitted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Transmission Cancellation callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param BufferIndexes Indexes of the aborted buffers. + * This parameter can be any combination of @arg FDCAN_Tx_location. + * @retval None + */ +__weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(BufferIndexes); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Buffer New Message callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file + */ +} + +/** + * @brief Timestamp Wraparound callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout Occurred callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file + */ +} + +/** + * @brief High Priority Message callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval None + */ +__weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Error status callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param ErrorStatusITs indicates which Error Status interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_Error_Status_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(ErrorStatusITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file + */ +} + +/** + * @brief TT Schedule Synchronization callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTSchedSyncITs indicates which TT Schedule Synchronization interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_TTScheduleSynchronization_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TTSchedSyncITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file + */ +} + +/** + * @brief TT Time Mark callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTTimeMarkITs indicates which TT Schedule Synchronization interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_TTTimeMark_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TTTimeMarkITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file + */ +} + +/** + * @brief TT Stop Watch callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param SWTime Time Value captured at the Stop Watch Trigger pin (fdcan1_swt) falling/rising + * edge (as configured via HAL_FDCAN_TTConfigStopWatch). + * This parameter is a number between 0 and 0xFFFF. + * @param SWCycleCount Cycle count value captured together with SWTime. + * This parameter is a number between 0 and 0x3F. + * @retval None + */ +__weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(SWTime); + UNUSED(SWCycleCount); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file + */ +} + +/** + * @brief TT Global Time callback. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param TTGlobTimeITs indicates which TT Global Time interrupts are signaled. + * This parameter can be any combination of @arg FDCAN_TTGlobalTime_Interrupts. + * @retval None + */ +__weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hfdcan); + UNUSED(TTGlobTimeITs); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions + * @brief FDCAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_FDCAN_GetState() : Return the FDCAN state. + (+) HAL_FDCAN_GetError() : Return the FDCAN error code if any. + +@endverbatim + * @{ + */ +/** + * @brief Return the FDCAN state + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL state + */ +HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN state */ + return hfdcan->State; +} + +/** + * @brief Return the FDCAN error code + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval FDCAN Error Code + */ +uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan) +{ + /* Return FDCAN error code */ + return hfdcan->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup FDCAN_Private_Functions + * @{ + */ + +/** + * @brief Calculate each RAM block start address and size + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval HAL status + */ +static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan) +{ + uint32_t RAMcounter; + uint32_t StartAddress; + + StartAddress = hfdcan->Init.MessageRAMOffset; + + /* Standard filter list start address */ + MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos)); + + /* Standard filter elements number */ + MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos)); + + /* Extended filter list start address */ + StartAddress += hfdcan->Init.StdFiltersNbr; + MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos)); + + /* Extended filter elements number */ + MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos)); + + /* Rx FIFO 0 start address */ + StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U); + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos)); + + /* Rx FIFO 0 elements number */ + MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos)); + + /* Rx FIFO 1 start address */ + StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize); + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos)); + + /* Rx FIFO 1 elements number */ + MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos)); + + /* Rx buffer list start address */ + StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize); + MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos)); + + /* Tx event FIFO start address */ + StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize); + MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos)); + + /* Tx event FIFO elements number */ + MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos)); + + /* Tx buffer list start address */ + StartAddress += (hfdcan->Init.TxEventsNbr * 2U); + MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos)); + + /* Dedicated Tx buffers number */ + MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos)); + + /* Tx FIFO/queue elements number */ + MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos)); + + hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U); + hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U); + hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U); + hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U); + hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U); + hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U); + hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U); + hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U); + + hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U); + + if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */ + { + /* Update error code. + Message RAM overflow */ + hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM; + + /* Change FDCAN state */ + hfdcan->State = HAL_FDCAN_STATE_ERROR; + + return HAL_ERROR; + } + else + { + /* Flush the allocated Message RAM area */ + for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U) + { + *(uint32_t *)(RAMcounter) = 0x00000000; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Copy Tx message to the message RAM. + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure. + * @param pTxData pointer to a buffer containing the payload of the Tx frame. + * @param BufferIndex index of the buffer to be configured. + * @retval HAL status + */ +static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex) +{ + uint32_t TxElementW1; + uint32_t TxElementW2; + uint32_t *TxAddress; + uint32_t ByteCounter; + + /* Build first word of Tx header element */ + if (pTxHeader->IdType == FDCAN_STANDARD_ID) + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_STANDARD_ID | + pTxHeader->TxFrameType | + (pTxHeader->Identifier << 18)); + } + else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */ + { + TxElementW1 = (pTxHeader->ErrorStateIndicator | + FDCAN_EXTENDED_ID | + pTxHeader->TxFrameType | + pTxHeader->Identifier); + } + + /* Build second word of Tx header element */ + TxElementW2 = ((pTxHeader->MessageMarker << 24) | + pTxHeader->TxEventFifoControl | + pTxHeader->FDFormat | + pTxHeader->BitRateSwitch | + pTxHeader->DataLength); + + /* Calculate Tx element address */ + TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U)); + + /* Write Tx element header to the message RAM */ + *TxAddress = TxElementW1; + TxAddress++; + *TxAddress = TxElementW2; + TxAddress++; + + /* Write Tx payload to the message RAM */ + for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U) + { + *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) | + ((uint32_t)pTxData[ByteCounter + 2U] << 16) | + ((uint32_t)pTxData[ByteCounter + 1U] << 8) | + (uint32_t)pTxData[ByteCounter]); + TxAddress++; + } +} + +/** + * @} + */ +#endif /* HAL_FDCAN_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* FDCAN1 */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c new file mode 100644 index 0000000..a3fe346 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c @@ -0,0 +1,1201 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AXI I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) Error code correction (ECC) : Data in flash are 266-bits word + (10 bits added per flash word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32H7xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: 256-bit word only + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_FLASH_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + [..] + (@) For any Flash memory program operation (erase or program), the CPU clock frequency + (HCLK) must be at least 1MHz. + (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + a Flash memory operation. + (@) The application can simultaneously request a read and a write operation through each AXI + interface. + As the Flash memory is divided into two independent banks, the embedded Flash + memory interface can drive different operations at the same time on each bank. For + example a read, write or erase operation can be executed on bank 1 while another read, + write or erase operation is executed on bank 2. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +FLASH_ProcessTypeDef pFlash; +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Functions FLASH Exported functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program a flash word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *dest_addr = (__IO uint32_t *)FlashAddress; + __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + uint32_t bank; + uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else + if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ + { + bank = FLASH_BANK_1; + } +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + { + bank = FLASH_BANK_2; + } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + + if(status == HAL_OK) + { +#if defined (DUAL_BANK) + if(bank == FLASH_BANK_1) + { +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + } + else + { + /* Set PG bit */ + SET_BIT(FLASH->CR2, FLASH_CR_PG); + } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } +#endif /* DUAL_BANK */ + + __ISB(); + __DSB(); + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } + + __ISB(); + __DSB(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + +#if defined (DUAL_BANK) +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + if(bank == FLASH_BANK_1) + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + } + else + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR2, FLASH_CR_PG); + } + } +#else /* Single Bank */ +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* If the program operation is completed, disable the OTP_PG */ + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* If the program operation is completed, disable the PG */ + CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); + } +#endif /* DUAL_BANK */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program a flash word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param FlashAddress specifies the address to be programmed. + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *dest_addr = (__IO uint32_t*)FlashAddress; + __IO uint32_t *src_addr = (__IO uint32_t*)DataAddress; + uint32_t bank; + uint8_t row_index = FLASH_NB_32BITWORD_IN_FLASHWORD; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(FlashAddress)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + +#if defined (FLASH_OPTCR_PG_OTP) + if((IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) || (IS_FLASH_PROGRAM_ADDRESS_OTP(FlashAddress))) +#else + if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress)) +#endif /* FLASH_OPTCR_PG_OTP */ + { + bank = FLASH_BANK_1; + } +#if defined (DUAL_BANK) + else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress)) + { + bank = FLASH_BANK_2; + } +#endif /* DUAL_BANK */ + else + { + return HAL_ERROR; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, bank); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + pFlash.Address = FlashAddress; + +#if defined (DUAL_BANK) + if(bank == FLASH_BANK_1) + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2; + + /* Set PG bit */ + SET_BIT(FLASH->CR2, FLASH_CR_PG); + + /* Enable End of Operation and Error interrupts for Bank2 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ + } +#else /* Single Bank */ + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1; + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Set OTP_PG bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_PG_OTP); + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Set PG bit */ + SET_BIT(FLASH->CR1, FLASH_CR_PG); + } + + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ +#endif /* DUAL_BANK */ + + __ISB(); + __DSB(); + +#if defined (FLASH_OPTCR_PG_OTP) + if (TypeProgram == FLASH_TYPEPROGRAM_OTPWORD) + { + /* Program an OTP word (16 bits) */ + *(__IO uint16_t *)FlashAddress = *(__IO uint16_t*)DataAddress; + } + else +#endif /* FLASH_OPTCR_PG_OTP */ + { + /* Program the flash word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + row_index--; + } while (row_index != 0U); + } + + __ISB(); + __DSB(); + } + + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t temp; + uint32_t errorflag; + FLASH_ProcedureTypeDef procedure; + + /* Check FLASH Bank1 End of Operation flag */ + if(__HAL_FLASH_GET_FLAG_BANK1(FLASH_SR_EOP) != RESET) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1) + { + /* Nb of sector to erased can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if(pFlash.NbSectorsToErase != 0U) + { + /* Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear bank 1 End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + + /* Increment sector number */ + pFlash.Sector++; + temp = pFlash.Sector; + FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called */ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } + else + { + procedure = pFlash.ProcedureOnGoing; + + if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /* MassErase ended. Return the selected bank */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(FLASH_BANK_1); + } + else if(procedure == FLASH_PROC_PROGRAM_BANK1) + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else + { + /* Nothing to do */ + } + + if((procedure != FLASH_PROC_SECTERASE_BANK2) && \ + (procedure != FLASH_PROC_MASSERASE_BANK2) && \ + (procedure != FLASH_PROC_PROGRAM_BANK2)) + { + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } + } + +#if defined (DUAL_BANK) + /* Check FLASH Bank2 End of Operation flag */ + if(__HAL_FLASH_GET_FLAG_BANK2(FLASH_SR_EOP) != RESET) + { + if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK2) + { + /*Nb of sector to erased can be decreased*/ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase*/ + if(pFlash.NbSectorsToErase != 0U) + { + /*Indicate user which sector has been erased*/ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear bank 2 End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + + /*Increment sector number*/ + pFlash.Sector++; + temp = pFlash.Sector; + FLASH_Erase_Sector(temp, FLASH_BANK_2, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called */ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = 0xFFFFFFFFU; + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Sector); + + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } + else + { + procedure = pFlash.ProcedureOnGoing; + + if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /*MassErase ended. Return the selected bank*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(FLASH_BANK_2); + } + else if(procedure == FLASH_PROC_PROGRAM_BANK2) + { + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + } + else + { + /* Nothing to do */ + } + + if((procedure != FLASH_PROC_SECTERASE_BANK1) && \ + (procedure != FLASH_PROC_MASSERASE_BANK1) && \ + (procedure != FLASH_PROC_PROGRAM_BANK1)) + { + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } + } +#endif /* DUAL_BANK */ + + /* Check FLASH Bank1 operation error flags */ +#if defined (FLASH_SR_OPERR) + errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ + FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); +#else + errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ + FLASH_FLAG_INCERR_BANK1); +#endif /* FLASH_SR_OPERR */ + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= errorflag; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag); + + procedure = pFlash.ProcedureOnGoing; + + if(procedure == FLASH_PROC_SECTERASE_BANK1) + { + /* Return the faulty sector */ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if((procedure == FLASH_PROC_MASSERASE_BANK1) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /* Return the faulty bank */ + temp = FLASH_BANK_1; + } + else + { + /* Return the faulty address */ + temp = pFlash.Address; + } + + /* Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + } + +#if defined (DUAL_BANK) + /* Check FLASH Bank2 operation error flags */ +#if defined (FLASH_SR_OPERR) + errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ + FLASH_FLAG_INCERR_BANK2 | FLASH_FLAG_OPERR_BANK2) & 0x7FFFFFFFU); +#else + errorflag = FLASH->SR2 & ((FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | FLASH_FLAG_STRBERR_BANK2 | \ + FLASH_FLAG_INCERR_BANK2) & 0x7FFFFFFFU); +#endif /* FLASH_SR_OPERR */ + + if(errorflag != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= (errorflag | 0x80000000U); + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag); + + procedure = pFlash.ProcedureOnGoing; + + if(procedure== FLASH_PROC_SECTERASE_BANK2) + { + /*return the faulty sector*/ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + } + else if((procedure == FLASH_PROC_MASSERASE_BANK2) || (procedure == FLASH_PROC_ALLBANK_MASSERASE)) + { + /*return the faulty bank*/ + temp = FLASH_BANK_2; + } + else + { + /*return the faulty address*/ + temp = pFlash.Address; + } + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + } +#endif /* DUAL_BANK */ + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { +#if defined (FLASH_CR_OPERRIE) + /* Disable Bank1 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); + +#if defined (DUAL_BANK) + /* Disable Bank2 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#endif /* DUAL_BANK */ +#else + /* Disable Bank1 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); + +#if defined (DUAL_BANK) + /* Disable Bank2 Operation and Error source interrupt */ + __HAL_FLASH_DISABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* DUAL_BANK */ +#endif /* FLASH_CR_OPERRIE */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector which has been erased + * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: Bank number which has been requested to erase + * Sectors Erase: Sector number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank1 Registers access */ + WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash Bank2 is unlocked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Locks the FLASH control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank1 Control Register access */ + SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + + /* Verify Flash Bank1 is locked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) == 0U) + { + return HAL_ERROR; + } + +#if defined (DUAL_BANK) + /* Set the LOCK Bit to lock the FLASH Bank2 Control Register access */ + SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + + /* Verify Flash Bank2 is locked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) == 0U) + { + return HAL_ERROR; + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if(READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPT_KEY2); + + /* Verify that the Option Bytes are unlocked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK); + + /* Verify that the Option Bytes are locked */ + if (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTLOCK) == 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Launch the option bytes loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + HAL_StatusTypeDef status; + + /* Wait for CRC computation to be completed */ + if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } +#if defined (DUAL_BANK) + else if (FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } +#endif /* DUAL_BANK */ + else + { + status = HAL_OK; + } + + if (status == HAL_OK) + { + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->OPTCR, FLASH_OPTCR_OPTSTART); + + /* Wait for OB change operation to be completed */ + status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval HAL_FLASH_ERRORCode The returned value can be: + * @arg HAL_FLASH_ERROR_NONE : No error set + * + * @arg HAL_FLASH_ERROR_WRP_BANK1 : Write Protection Error on Bank 1 + * @arg HAL_FLASH_ERROR_PGS_BANK1 : Program Sequence Error on Bank 1 + * @arg HAL_FLASH_ERROR_STRB_BANK1 : Strobe Error on Bank 1 + * @arg HAL_FLASH_ERROR_INC_BANK1 : Inconsistency Error on Bank 1 + * @arg HAL_FLASH_ERROR_OPE_BANK1 : Operation Error on Bank 1 + * @arg HAL_FLASH_ERROR_RDP_BANK1 : Read Protection Error on Bank 1 + * @arg HAL_FLASH_ERROR_RDS_BANK1 : Read Secured Error on Bank 1 + * @arg HAL_FLASH_ERROR_SNECC_BANK1: ECC Single Correction Error on Bank 1 + * @arg HAL_FLASH_ERROR_DBECC_BANK1: ECC Double Detection Error on Bank 1 + * @arg HAL_FLASH_ERROR_CRCRD_BANK1: CRC Read Error on Bank 1 + * + * @arg HAL_FLASH_ERROR_WRP_BANK2 : Write Protection Error on Bank 2 + * @arg HAL_FLASH_ERROR_PGS_BANK2 : Program Sequence Error on Bank 2 + * @arg HAL_FLASH_ERROR_STRB_BANK2 : Strobe Error on Bank 2 + * @arg HAL_FLASH_ERROR_INC_BANK2 : Inconsistency Error on Bank 2 + * @arg HAL_FLASH_ERROR_OPE_BANK2 : Operation Error on Bank 2 + * @arg HAL_FLASH_ERROR_RDP_BANK2 : Read Protection Error on Bank 2 + * @arg HAL_FLASH_ERROR_RDS_BANK2 : Read Secured Error on Bank 2 + * @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2 + * @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2 + * @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2 +*/ + +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) +{ + /* Wait for the FLASH operation to complete by polling on QW flag to be reset. + Even if the FLASH operation fails, the QW flag will be reset and an error + flag will be set */ + + uint32_t bsyflag = FLASH_FLAG_QW_BANK1; + uint32_t errorflag = 0; + uint32_t tickstart = HAL_GetTick(); + + assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + +#if defined (DUAL_BANK) + + if (Bank == FLASH_BANK_2) + { + /* Select bsyflag depending on Bank */ + bsyflag = FLASH_FLAG_QW_BANK2; + } +#endif /* DUAL_BANK */ + + while(__HAL_FLASH_GET_FLAG(bsyflag)) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Get Error Flags */ + if (Bank == FLASH_BANK_1) + { + errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1; + } +#if defined (DUAL_BANK) + else + { + errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U; + } +#endif /* DUAL_BANK */ + + /* In case of error reported in Flash SR1 or SR2 register */ + if((errorflag & 0x7FFFFFFFU) != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= errorflag; + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(errorflag); + + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if(Bank == FLASH_BANK_1) + { + if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_EOP_BANK1)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); + } + } +#if defined (DUAL_BANK) + else + { + if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_EOP_BANK2)) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_EOP_BANK2); + } + } +#endif /* DUAL_BANK */ + + return HAL_OK; +} + +/** + * @brief Wait for a FLASH Option Bytes change operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout) +{ + /* Get timeout */ + uint32_t tickstart = HAL_GetTick(); + + /* Wait for the FLASH Option Bytes change operation to complete by polling on OPT_BUSY flag to be reset */ + while(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPT_BUSY) != 0U) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check option byte change error */ + if(READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_OPTCHANGEERR) != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_OB_CHANGE; + + /* Clear the OB error flag */ + FLASH->OPTCCR |= FLASH_OPTCCR_CLR_OPTCHANGEERR; + + return HAL_ERROR; + } + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @brief Wait for a FLASH CRC computation to complete. + * @param Timeout maximum flash operation timeout + * @param Bank flash FLASH_BANK_1 or FLASH_BANK_2 + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank) +{ + uint32_t bsyflag; + uint32_t tickstart = HAL_GetTick(); + + assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank)); + + /* Select bsyflag depending on Bank */ + if(Bank == FLASH_BANK_1) + { + bsyflag = FLASH_FLAG_CRC_BUSY_BANK1; + } + else + { + bsyflag = FLASH_FLAG_CRC_BUSY_BANK2; + } + + /* Wait for the FLASH CRC computation to complete by polling on CRC_BUSY flag to be reset */ + while(__HAL_FLASH_GET_FLAG(bsyflag)) + { + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH CRC read error flag */ + if(Bank == FLASH_BANK_1) + { + if (__HAL_FLASH_GET_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1)) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK1; + + /* Clear FLASH CRC read error pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCRDERR_BANK1); + + return HAL_ERROR; + } + } +#if defined (DUAL_BANK) + else + { + if (__HAL_FLASH_GET_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2)) + { + /* Save the error code */ + pFlash.ErrorCode |= HAL_FLASH_ERROR_CRCRD_BANK2; + + /* Clear FLASH CRC read error pending bit */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCRDERR_BANK2); + + return HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + /* If there is no error flag set */ + return HAL_OK; +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c new file mode 100644 index 0000000..fd4acec --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c @@ -0,0 +1,1860 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32H7xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) PCROP protection for all banks + (+) Global readout protection (RDP) + (+) Write protection + (+) Secure access only protection + (+) Bank / register swapping (when Dual-Bank) + (+) Cyclic Redundancy Check (CRC) + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32H7xx devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Sector erase, bank erase and dual-bank mass erase + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to: + (++) Set/Reset the write protection per bank + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + (++) PCROP protection configuration and control per bank + (++) Secure area configuration and control per bank + (++) Core Boot address configuration + (++) TCM / AXI shared RAM configuration + (++) CPU Frequency Boost configuration + + (#) FLASH Memory Lock and unlock per Bank: HAL_FLASHEx_Lock_Bank1(), HAL_FLASHEx_Unlock_Bank1(), + HAL_FLASHEx_Lock_Bank2() and HAL_FLASHEx_Unlock_Bank2() functions + + (#) FLASH CRC computation function: Use HAL_FLASHEx_ComputeCRC() to: + (++) Enable CRC feature + (++) Program the desired burst size + (++) Define the user Flash Area on which the CRC has be computed + (++) Perform the CRC computation + (++) Disable CRC feature + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks); +static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks); +static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Bank); +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank); +static void FLASH_OB_RDPConfig(uint32_t RDPLevel); +static uint32_t FLASH_OB_GetRDP(void); +static void FLASH_OB_PCROPConfig(uint32_t PCROConfigRDP, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks); +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr,uint32_t *PCROPEndAddr, uint32_t Bank); +static void FLASH_OB_BOR_LevelConfig(uint32_t Level); +static uint32_t FLASH_OB_GetBOR(void); +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); +static uint32_t FLASH_OB_GetUser(void); +static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); +static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); +static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks); +static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank); +static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank); +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank); + +#if defined (DUAL_CORE) +static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1); +static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1); +#endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block); +static uint32_t FLASH_OB_OTP_GetLock(void); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig); +static uint32_t FLASH_OB_SharedRAM_GetConfig(void); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost); +static uint32_t FLASH_OB_CPUFreq_GetBoost(void); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that contains the configuration + * information on faulty sector in case of error (0xFFFFFFFF means that all + * the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed on Bank1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + if(status == HAL_OK) + { + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + + /* Wait for last operation to be completed on Bank 1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + /* if the erase operation is completed, disable the Bank1 BER Bit */ + FLASH->CR1 &= (~FLASH_CR_BER); + } +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + /* if the erase operation is completed, disable the Bank2 BER Bit */ + FLASH->CR2 &= (~FLASH_CR_BER); + } +#endif /* DUAL_BANK */ + } + else + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + /* Erase by sector by sector to be done*/ + for(sector_index = pEraseInit->Sector; sector_index < (pEraseInit->NbSectors + pEraseInit->Sector); sector_index++) + { + FLASH_Erase_Sector(sector_index, pEraseInit->Banks, pEraseInit->VoltageRange); + + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR1 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + } +#if defined (DUAL_BANK) + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR2 &= (~(FLASH_CR_SER | FLASH_CR_SNB)); + } +#endif /* DUAL_BANK */ + + if(status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector */ + *SectorError = sector_index; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_BANK(pEraseInit->Banks)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed on Bank 1 */ + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } + } + +#if defined (DUAL_BANK) + /* Wait for last operation to be completed on Bank 2 */ + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* DUAL_BANK */ + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + if((pEraseInit->Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Enable End of Operation and Error interrupts for Bank 1 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1); +#else + __HAL_FLASH_ENABLE_IT_BANK1(FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | FLASH_IT_PGSERR_BANK1 | \ + FLASH_IT_STRBERR_BANK1 | FLASH_IT_INCERR_BANK1); +#endif /* FLASH_CR_OPERRIE */ + } +#if defined (DUAL_BANK) + if((pEraseInit->Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Enable End of Operation and Error interrupts for Bank 2 */ +#if defined (FLASH_CR_OPERRIE) + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); +#else + __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ + FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2); +#endif /* FLASH_CR_OPERRIE */ + } +#endif /* DUAL_BANK */ + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + if(pEraseInit->Banks == FLASH_BANK_1) + { + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK1; + } +#if defined (DUAL_BANK) + else if(pEraseInit->Banks == FLASH_BANK_2) + { + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE_BANK2; + } +#endif /* DUAL_BANK */ + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_ALLBANK_MASSERASE; + } + + FLASH_MassErase(pEraseInit->VoltageRange, pEraseInit->Banks); + } + else + { + /* Erase by sector to be done */ +#if defined (DUAL_BANK) + if(pEraseInit->Banks == FLASH_BANK_1) + { + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; + } + else + { + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK2; + } +#else + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE_BANK1; +#endif /* DUAL_BANK */ + + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = pEraseInit->VoltageRange; + + /* Erase first sector and wait for IT */ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->Banks, pEraseInit->VoltageRange); + } + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1) != HAL_OK) + { + status = HAL_ERROR; + } +#if defined (DUAL_BANK) + else if(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2) != HAL_OK) + { + status = HAL_ERROR; + } +#endif /* DUAL_BANK */ + else + { + status = HAL_OK; + } + + if(status == HAL_OK) + { + /*Write protection configuration*/ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + + if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + FLASH_OB_EnableWRP(pOBInit->WRPSector,pOBInit->Banks); + } + else + { + /*Disable of Write protection on the selected Sector*/ + FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks); + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) + { + /* Configure the Read protection level */ + FLASH_OB_RDPConfig(pOBInit->RDPLevel); + } + + /* User Configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Configure the user option bytes */ + FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); + } + + /* PCROP Configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U) + { + assert_param(IS_FLASH_BANK(pOBInit->Banks)); + + /*Configure the Proprietary code readout protection */ + FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr, pOBInit->Banks); + } + + /* BOR Level configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + +#if defined(DUAL_CORE) + /* CM7 Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD) + { + FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + } + + /* CM4 Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD) + { + FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1); + } +#else /* Single Core*/ + /* Boot Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD) + { + FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); + } +#endif /*DUAL_CORE*/ + + /* Secure area configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA) + { + FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks); + } + +#if defined(FLASH_OTPBL_LOCKBL) + /* OTP Block Lock configuration */ + if((pOBInit->OptionType & OPTIONBYTE_OTP_LOCK) == OPTIONBYTE_OTP_LOCK) + { + FLASH_OB_OTP_LockConfig(pOBInit->OTPBlockLock); + } +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined(FLASH_OPTSR2_TCM_AXI_SHARED) + /* TCM / AXI Shared RAM configuration */ + if((pOBInit->OptionType & OPTIONBYTE_SHARED_RAM) == OPTIONBYTE_SHARED_RAM) + { + FLASH_OB_SharedRAM_Config(pOBInit->SharedRamConfig); + } +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined(FLASH_OPTSR2_CPUFREQ_BOOST) + /* CPU Frequency Boost configuration */ + if((pOBInit->OptionType & OPTIONBYTE_FREQ_BOOST) == OPTIONBYTE_FREQ_BOOST) + { + FLASH_OB_CPUFreq_BoostConfig(pOBInit->FreqBoostState); + } +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * @note The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2, + * as this parameter is use to get the given Bank WRP, PCROP and secured area configuration. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = (OPTIONBYTE_USER | OPTIONBYTE_RDP | OPTIONBYTE_BOR); + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + +#if defined (DUAL_BANK) + if ((pOBInit->Banks == FLASH_BANK_1) || (pOBInit->Banks == FLASH_BANK_2)) +#else + if (pOBInit->Banks == FLASH_BANK_1) +#endif /* DUAL_BANK */ + { + pOBInit->OptionType |= (OPTIONBYTE_WRP | OPTIONBYTE_PCROP | OPTIONBYTE_SECURE_AREA); + + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(&(pOBInit->WRPState), &(pOBInit->WRPSector), pOBInit->Banks); + + /* Get the Proprietary code readout protection */ + FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr), pOBInit->Banks); + + /*Get Bank Secure area*/ + FLASH_OB_GetSecureArea(&(pOBInit->SecureAreaConfig), &(pOBInit->SecureAreaStartAddr), &(pOBInit->SecureAreaEndAddr), pOBInit->Banks); + } + + /*Get Boot Address*/ + FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1)); +#if defined(DUAL_CORE) + pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD; + + /*Get CM4 Boot Address*/ + FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1)); +#else + pOBInit->OptionType |= OPTIONBYTE_BOOTADD; +#endif /*DUAL_CORE*/ + +#if defined (FLASH_OTPBL_LOCKBL) + pOBInit->OptionType |= OPTIONBYTE_OTP_LOCK; + + /* Get OTP Block Lock */ + pOBInit->OTPBlockLock = FLASH_OB_OTP_GetLock(); +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) + pOBInit->OptionType |= OPTIONBYTE_SHARED_RAM; + + /* Get TCM / AXI Shared RAM */ + pOBInit->SharedRamConfig = FLASH_OB_SharedRAM_GetConfig(); +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) + pOBInit->OptionType |= OPTIONBYTE_FREQ_BOOST; + + /* Get CPU Frequency Boost */ + pOBInit->FreqBoostState = FLASH_OB_CPUFreq_GetBoost(); +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ +} + +/** + * @brief Unlock the FLASH Bank1 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void) +{ + if(READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank1 Registers access */ + WRITE_REG(FLASH->KEYR1, FLASH_KEY1); + WRITE_REG(FLASH->KEYR1, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR1, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH Bank1 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank1 Registers access */ + SET_BIT(FLASH->CR1, FLASH_CR_LOCK); + return HAL_OK; +} + +#if defined (DUAL_BANK) +/** + * @brief Unlock the FLASH Bank2 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void) +{ + if(READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + /* Authorize the FLASH Bank2 Registers access */ + WRITE_REG(FLASH->KEYR2, FLASH_KEY1); + WRITE_REG(FLASH->KEYR2, FLASH_KEY2); + + /* Verify Flash Bank1 is unlocked */ + if (READ_BIT(FLASH->CR2, FLASH_CR_LOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Locks the FLASH Bank2 control registers access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void) +{ + /* Set the LOCK Bit to lock the FLASH Bank2 Registers access */ + SET_BIT(FLASH->CR2, FLASH_CR_LOCK); + return HAL_OK; +} +#endif /* DUAL_BANK */ + +/* + * @brief Perform a CRC computation on the specified FLASH memory area + * @param pCRCInit pointer to an FLASH_CRCInitTypeDef structure that + * contains the configuration information for the CRC computation. + * @note CRC computation uses CRC-32 (Ethernet) polynomial 0x4C11DB7 + * @note The application should avoid running a CRC on PCROP or secure-only + * user Flash memory area since it may alter the expected CRC value. + * A special error flag (CRC read error: CRCRDERR) can be used to + * detect such a case. + * @retval HAL Status +*/ +HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result) +{ + HAL_StatusTypeDef status; + uint32_t sector_index; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK_EXCLUSIVE(pCRCInit->Bank)); + assert_param(IS_FLASH_TYPECRC(pCRCInit->TypeCRC)); + + /* Wait for OB change operation to be completed */ + status = FLASH_OB_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (pCRCInit->Bank == FLASH_BANK_1) + { + /* Enable CRC feature */ + FLASH->CR1 |= FLASH_CR_CRC_EN; + + /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + FLASH->CCR1 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + + /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */ + FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + + if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + { + /* Clear sectors list */ + FLASH->CRCCR1 |= FLASH_CRCCR_CLEAN_SECT; + + /* Select CRC sectors */ + for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++) + { + FLASH_CRC_AddSector(sector_index, FLASH_BANK_1); + } + } + else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + { + /* Enable Bank 1 CRC select bit */ + FLASH->CRCCR1 |= FLASH_CRCCR_ALL_BANK; + } + else + { + /* Select CRC start and end addresses */ + FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_1); + } + + /* Start the CRC calculation */ + FLASH->CRCCR1 |= FLASH_CRCCR_START_CRC; + + /* Wait on CRC busy flag */ + status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_1); + + /* Return CRC result */ + (*CRC_Result) = FLASH->CRCDATA; + + /* Disable CRC feature */ + FLASH->CR1 &= (~FLASH_CR_CRC_EN); + + /* Clear CRC flags */ + __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_CRCEND_BANK1 | FLASH_FLAG_CRCRDERR_BANK1); + } +#if defined (DUAL_BANK) + else + { + /* Enable CRC feature */ + FLASH->CR2 |= FLASH_CR_CRC_EN; + + /* Clear CRC flags in Status Register: CRC end of calculation and CRC read error */ + FLASH->CCR2 |= (FLASH_CCR_CLR_CRCEND | FLASH_CCR_CLR_CRCRDERR); + + /* Clear current CRC result, program burst size and define memory area on which CRC has to be computed */ + FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_CRC | pCRCInit->BurstSize | pCRCInit->TypeCRC; + + if (pCRCInit->TypeCRC == FLASH_CRC_SECTORS) + { + /* Clear sectors list */ + FLASH->CRCCR2 |= FLASH_CRCCR_CLEAN_SECT; + + /* Add CRC sectors */ + for(sector_index = pCRCInit->Sector; sector_index < (pCRCInit->NbSectors + pCRCInit->Sector); sector_index++) + { + FLASH_CRC_AddSector(sector_index, FLASH_BANK_2); + } + } + else if (pCRCInit->TypeCRC == FLASH_CRC_BANK) + { + /* Enable Bank 2 CRC select bit */ + FLASH->CRCCR2 |= FLASH_CRCCR_ALL_BANK; + } + else + { + /* Select CRC start and end addresses */ + FLASH_CRC_SelectAddress(pCRCInit->CRCStartAddr, pCRCInit->CRCEndAddr, FLASH_BANK_2); + } + + /* Start the CRC calculation */ + FLASH->CRCCR2 |= FLASH_CRCCR_START_CRC; + + /* Wait on CRC busy flag */ + status = FLASH_CRC_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE, FLASH_BANK_2); + + /* Return CRC result */ + (*CRC_Result) = FLASH->CRCDATA; + + /* Disable CRC feature */ + FLASH->CR2 &= (~FLASH_CR_CRC_EN); + + /* Clear CRC flags */ + __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_CRCEND_BANK2 | FLASH_FLAG_CRCRDERR_BANK2); + } +#endif /* DUAL_BANK */ + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory + * @param VoltageRange The device program/erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + * + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint32_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ +#if defined (FLASH_CR_PSIZE) + assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ + assert_param(IS_FLASH_BANK(Banks)); + +#if defined (DUAL_BANK) + /* Flash Mass Erase */ + if((Banks & FLASH_BANK_BOTH) == FLASH_BANK_BOTH) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange for Bank1 and Bank2 */ + FLASH->CR1 &= (~FLASH_CR_PSIZE); + FLASH->CR2 &= (~FLASH_CR_PSIZE); + + /* Set voltage range */ + FLASH->CR1 |= VoltageRange; + FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Set Mass Erase Bit */ + FLASH->OPTCR |= FLASH_OPTCR_MER; + } + else +#endif /* DUAL_BANK */ + { + /* Proceed to erase Flash Bank */ + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank1 */ + FLASH->CR1 &= (~FLASH_CR_PSIZE); + FLASH->CR1 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Erase Bank1 */ + FLASH->CR1 |= (FLASH_CR_BER | FLASH_CR_START); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { +#if defined (FLASH_CR_PSIZE) + /* Set Program/erase VoltageRange for Bank2 */ + FLASH->CR2 &= (~FLASH_CR_PSIZE); + FLASH->CR2 |= VoltageRange; +#endif /* FLASH_CR_PSIZE */ + + /* Erase Bank2 */ + FLASH->CR2 |= (FLASH_CR_BER | FLASH_CR_START); + } +#endif /* DUAL_BANK */ + } +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * This parameter can be a value of @ref FLASH_Sectors + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * @param VoltageRange The device program/erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1 : Flash program/erase by 8 bits + * @arg FLASH_VOLTAGE_RANGE_2 : Flash program/erase by 16 bits + * @arg FLASH_VOLTAGE_RANGE_3 : Flash program/erase by 32 bits + * @arg FLASH_VOLTAGE_RANGE_4 : Flash program/erase by 64 bits + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange) +{ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); +#if defined (FLASH_CR_PSIZE) + assert_param(IS_VOLTAGERANGE(VoltageRange)); +#else + UNUSED(VoltageRange); +#endif /* FLASH_CR_PSIZE */ + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank1 */ + FLASH->CR1 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + + FLASH->CR1 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank1 */ + FLASH->CR1 &= ~(FLASH_CR_SNB); + + FLASH->CR1 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { +#if defined (FLASH_CR_PSIZE) + /* Reset Program/erase VoltageRange and Sector Number for Bank2 */ + FLASH->CR2 &= ~(FLASH_CR_PSIZE | FLASH_CR_SNB); + + FLASH->CR2 |= (FLASH_CR_SER | VoltageRange | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#else + /* Reset Sector Number for Bank2 */ + FLASH->CR2 &= ~(FLASH_CR_SNB); + + FLASH->CR2 |= (FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos) | FLASH_CR_START); +#endif /* FLASH_CR_PSIZE */ + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Enable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: enable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: enable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: enable WRP on both bank1 and bank2 specified sectors + * + * @retval HAL FLASH State + */ +static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Enable Write Protection for bank 1 */ + FLASH->WPSN_PRG1 &= (~(WRPSector & FLASH_WPSN_WRPSN)); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Enable Write Protection for bank 2 */ + FLASH->WPSN_PRG2 &= (~(WRPSector & FLASH_WPSN_WRPSN)); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * @param WRPSector specifies the sector(s) to disable write protection. + * This parameter can be one of the following values: + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL + * + * @param Banks the specific bank to apply WRP sectors + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: disable WRP on specified bank1 sectors + * @arg FLASH_BANK_2: disable WRP on specified bank2 sectors + * @arg FLASH_BANK_BOTH: disable WRP on both bank1 and bank2 specified sectors + * + * @retval HAL FLASH State + */ +static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + assert_param(IS_FLASH_BANK(Banks)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Disable Write Protection for bank 1 */ + FLASH->WPSN_PRG1 |= (WRPSector & FLASH_WPSN_WRPSN); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Disable Write Protection for bank 2 */ + FLASH->WPSN_PRG2 |= (WRPSector & FLASH_WPSN_WRPSN); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get the write protection of the given bank 1 or bank 2 sectors + * @param WRPState gives the write protection state on the given bank. + * This parameter can be one of the following values: + * @arg WRPState: OB_WRPSTATE_DISABLE or OB_WRPSTATE_ENABLE + + * @param WRPSector gives the write protected sector(s) on the given bank . + * This parameter can be one of the following values: + * @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL + * + * @param Bank the specific bank to apply WRP sectors + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: Get bank1 WRP sectors + * @arg FLASH_BANK_2: Get bank2 WRP sectors + * @arg FLASH_BANK_BOTH: note allowed in this functions + * + * @retval HAL FLASH State + */ +static void FLASH_OB_GetWRP(uint32_t *WRPState, uint32_t *WRPSector, uint32_t Bank) +{ + uint32_t regvalue = 0U; + + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->WPSN_CUR1; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->WPSN_CUR2; + } +#endif /* DUAL_BANK */ + + (*WRPSector) = (~regvalue) & FLASH_WPSN_WRPSN; + + if(*WRPSector == 0U) + { + (*WRPState) = OB_WRPSTATE_DISABLE; + } + else + { + (*WRPState) = OB_WRPSTATE_ENABLE; + } +} + +/** + * @brief Set the read protection level. + * + * @note To configure the RDP level, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the RDP level, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * to go back to level 1 or 0 !!! + * + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @retval HAL status + */ +static void FLASH_OB_RDPConfig(uint32_t RDPLevel) +{ + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_RDP, RDPLevel); +} + +/** + * @brief Get the read protection level. + * @retval RDPLevel specifies the read protection level. + * This return value can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdp_level; + } +} + +#if defined(DUAL_CORE) +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param UserType The FLASH User Option Bytes to be modified : + * a combination of @ref FLASHEx_OB_USER_Type + * + * @param UserConfig The FLASH User Option Bytes values: + * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), + * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + * + * @retval HAL status + */ +#else +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the HAL_FLASH_OB_Unlock() function. + * + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param UserType The FLASH User Option Bytes to be modified : + * a combination of @arg FLASHEx_OB_USER_Type + * + * @param UserConfig The FLASH User Option Bytes values: + * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + * + * @retval HAL status + */ +#endif /*DUAL_CORE*/ +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) +{ + uint32_t optr_reg_val = 0; + uint32_t optr_reg_mask = 0; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + + if((UserType & OB_USER_IWDG1_SW) != 0U) + { + /* IWDG_HW option byte should be modified */ + assert_param(IS_OB_IWDG1_SOURCE(UserConfig & FLASH_OPTSR_IWDG1_SW)); + + /* Set value and mask for IWDG_HW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW); + optr_reg_mask |= FLASH_OPTSR_IWDG1_SW; + } +#if defined(DUAL_CORE) + if((UserType & OB_USER_IWDG2_SW) != 0U) + { + /* IWDG2_SW option byte should be modified */ + assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW)); + + /* Set value and mask for IWDG2_SW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW); + optr_reg_mask |= FLASH_OPTSR_IWDG2_SW; + } +#endif /*DUAL_CORE*/ + if((UserType & OB_USER_NRST_STOP_D1) != 0U) + { + /* NRST_STOP option byte should be modified */ + assert_param(IS_OB_STOP_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D1)); + + /* Set value and mask for NRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D1); + optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D1; + } + + if((UserType & OB_USER_NRST_STDBY_D1) != 0U) + { + /* NRST_STDBY option byte should be modified */ + assert_param(IS_OB_STDBY_D1_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D1)); + + /* Set value and mask for NRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D1); + optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D1; + } + + if((UserType & OB_USER_IWDG_STOP) != 0U) + { + /* IWDG_STOP option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTSR_FZ_IWDG_STOP)); + + /* Set value and mask for IWDG_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_STOP); + optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_STOP; + } + + if((UserType & OB_USER_IWDG_STDBY) != 0U) + { + /* IWDG_STDBY option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY)); + + /* Set value and mask for IWDG_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_FZ_IWDG_SDBY); + optr_reg_mask |= FLASH_OPTSR_FZ_IWDG_SDBY; + } + + if((UserType & OB_USER_ST_RAM_SIZE) != 0U) + { + /* ST_RAM_SIZE option byte should be modified */ + assert_param(IS_OB_USER_ST_RAM_SIZE(UserConfig & FLASH_OPTSR_ST_RAM_SIZE)); + + /* Set value and mask for ST_RAM_SIZE option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_ST_RAM_SIZE); + optr_reg_mask |= FLASH_OPTSR_ST_RAM_SIZE; + } + + if((UserType & OB_USER_SECURITY) != 0U) + { + /* SECURITY option byte should be modified */ + assert_param(IS_OB_USER_SECURITY(UserConfig & FLASH_OPTSR_SECURITY)); + + /* Set value and mask for SECURITY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_SECURITY); + optr_reg_mask |= FLASH_OPTSR_SECURITY; + } + +#if defined(DUAL_CORE) + if((UserType & OB_USER_BCM4) != 0U) + { + /* BCM4 option byte should be modified */ + assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4)); + + /* Set value and mask for BCM4 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4); + optr_reg_mask |= FLASH_OPTSR_BCM4; + } + + if((UserType & OB_USER_BCM7) != 0U) + { + /* BCM7 option byte should be modified */ + assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7)); + + /* Set value and mask for BCM7 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7); + optr_reg_mask |= FLASH_OPTSR_BCM7; + } +#endif /* DUAL_CORE */ + +#if defined (FLASH_OPTSR_NRST_STOP_D2) + if((UserType & OB_USER_NRST_STOP_D2) != 0U) + { + /* NRST_STOP option byte should be modified */ + assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2)); + + /* Set value and mask for NRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2); + optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2; + } + + if((UserType & OB_USER_NRST_STDBY_D2) != 0U) + { + /* NRST_STDBY option byte should be modified */ + assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2)); + + /* Set value and mask for NRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2); + optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2; + } +#endif /* FLASH_OPTSR_NRST_STOP_D2 */ + +#if defined (DUAL_BANK) + if((UserType & OB_USER_SWAP_BANK) != 0U) + { + /* SWAP_BANK_OPT option byte should be modified */ + assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTSR_SWAP_BANK_OPT)); + + /* Set value and mask for SWAP_BANK_OPT option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_SWAP_BANK_OPT); + optr_reg_mask |= FLASH_OPTSR_SWAP_BANK_OPT; + } +#endif /* DUAL_BANK */ + + if((UserType & OB_USER_IOHSLV) != 0U) + { + /* IOHSLV_OPT option byte should be modified */ + assert_param(IS_OB_USER_IOHSLV(UserConfig & FLASH_OPTSR_IO_HSLV)); + + /* Set value and mask for IOHSLV_OPT option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_IO_HSLV); + optr_reg_mask |= FLASH_OPTSR_IO_HSLV; + } + +#if defined (FLASH_OPTSR_VDDMMC_HSLV) + if((UserType & OB_USER_VDDMMC_HSLV) != 0U) + { + /* VDDMMC_HSLV option byte should be modified */ + assert_param(IS_OB_USER_VDDMMC_HSLV(UserConfig & FLASH_OPTSR_VDDMMC_HSLV)); + + /* Set value and mask for VDDMMC_HSLV option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTSR_VDDMMC_HSLV); + optr_reg_mask |= FLASH_OPTSR_VDDMMC_HSLV; + } +#endif /* FLASH_OPTSR_VDDMMC_HSLV */ + + /* Configure the option bytes register */ + MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val); +} + +#if defined(DUAL_CORE) +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values + * IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24), + * nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + */ +#else +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values + * IWDG_SW(Bit4), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7), + * FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]), + * SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31). + */ +#endif /*DUAL_CORE*/ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR); + userConfig &= (~(FLASH_OPTSR_BOR_LEV | FLASH_OPTSR_RDP)); + + return userConfig; +} + +/** + * @brief Configure the Proprietary code readout protection of the desired addresses + * + * @note To configure the PCROP options, the option lock bit OPTLOCK must be + * cleared with the call of the HAL_FLASH_OB_Unlock() function. + * @note To validate the PCROP options, the option bytes must be reloaded + * through the call of the HAL_FLASH_OB_Launch() function. + * + * @param PCROPConfig specifies if the PCROP area for the given Bank shall be erased or not + * when RDP level decreased from Level 1 to Level 0, or after a bank erase with protection removal + * This parameter must be a value of @arg FLASHEx_OB_PCROP_RDP enumeration + * + * @param PCROPStartAddr specifies the start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the bank + * + * @param PCROPEndAddr specifies the end address of the Proprietary code readout protection + * This parameter can be an address between PCROPStartAddr and end of the bank + * + * @param Banks the specific bank to apply PCROP protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: PCROP on specified bank1 area + * @arg FLASH_BANK_2: PCROP on specified bank2 area + * @arg FLASH_BANK_BOTH: PCROP on specified bank1 and bank2 area (same config will be applied on both banks) + * + * @retval None + */ +static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_OB_PCROP_RDP(PCROPConfig)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(PCROPEndAddr)); + + /* Configure the Proprietary code readout protection */ + FLASH->PRAR_PRG1 = ((PCROPStartAddr - FLASH_BANK1_BASE) >> 8) | \ + (((PCROPEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ + PCROPConfig; + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(PCROPEndAddr)); + + /* Configure the Proprietary code readout protection */ + FLASH->PRAR_PRG2 = ((PCROPStartAddr - FLASH_BANK2_BASE) >> 8) | \ + (((PCROPEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_PRAR_PROT_AREA_END_Pos) | \ + PCROPConfig; + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get the Proprietary code readout protection configuration on a given Bank + * + * @param PCROPConfig indicates if the PCROP area for the given Bank shall be erased or not + * when RDP level decreased from Level 1 to Level 0 or after a bank erase with protection removal + * + * @param PCROPStartAddr gives the start address of the Proprietary code readout protection of the bank + * + * @param PCROPEndAddr gives the end address of the Proprietary code readout protection of the bank + * + * @param Bank the specific bank to apply PCROP protection + * This parameter can be exclusively one of the following values: + * @arg FLASH_BANK_1: PCROP on specified bank1 area + * @arg FLASH_BANK_2: PCROP on specified bank2 area + * @arg FLASH_BANK_BOTH: is not allowed here + * + * @retval None + */ +static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROPStartAddr, uint32_t *PCROPEndAddr, uint32_t Bank) +{ + uint32_t regvalue = 0; + uint32_t bankBase = 0; + + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->PRAR_CUR1; + bankBase = FLASH_BANK1_BASE; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->PRAR_CUR2; + bankBase = FLASH_BANK2_BASE; + } +#endif /* DUAL_BANK */ + + (*PCROPConfig) = (regvalue & FLASH_PRAR_DMEP); + + (*PCROPStartAddr) = ((regvalue & FLASH_PRAR_PROT_AREA_START) << 8) + bankBase; + (*PCROPEndAddr) = (regvalue & FLASH_PRAR_PROT_AREA_END) >> FLASH_PRAR_PROT_AREA_END_Pos; + (*PCROPEndAddr) = ((*PCROPEndAddr) << 8) + bankBase; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V + * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V + * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V + * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V + * @retval None + */ +static void FLASH_OB_BOR_LevelConfig(uint32_t Level) +{ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Configure BOR_LEV option byte */ + MODIFY_REG(FLASH->OPTSR_PRG, FLASH_OPTSR_BOR_LEV, Level); +} + +/** + * @brief Get the BOR Level. + * @retval The Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL0: Reset level threshold is set to 1.6V + * @arg OB_BOR_LEVEL1: Reset level threshold is set to 2.1V + * @arg OB_BOR_LEVEL2: Reset level threshold is set to 2.4V + * @arg OB_BOR_LEVEL3: Reset level threshold is set to 2.7V + */ +static uint32_t FLASH_OB_GetBOR(void) +{ + return (FLASH->OPTSR_CUR & FLASH_OPTSR_BOR_LEV); +} + +/** + * @brief Set Boot address + * @param BootOption Boot address option byte to be programmed, + * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION + (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) + * + * @param BootAddress0 Specifies the Boot Address 0 + * @param BootAddress1 Specifies the Boot Address 1 + * @retval HAL Status + */ +static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); + + if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress0)); + + /* Configure CM7 BOOT ADD0 */ +#if defined(DUAL_CORE) + MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16)); +#else /* Single Core*/ + MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16)); +#endif /* DUAL_CORE */ + } + + if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress1)); + + /* Configure CM7 BOOT ADD1 */ +#if defined(DUAL_CORE) + MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1); +#else /* Single Core*/ + MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1); +#endif /* DUAL_CORE */ + } +} + +/** + * @brief Get Boot address + * @param BootAddress0 Specifies the Boot Address 0. + * @param BootAddress1 Specifies the Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +{ + uint32_t regvalue; + +#if defined(DUAL_CORE) + regvalue = FLASH->BOOT7_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1); +#else /* Single Core */ + regvalue = FLASH->BOOT_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT_ADD1); +#endif /* DUAL_CORE */ +} + +#if defined(DUAL_CORE) +/** + * @brief Set CM4 Boot address + * @param BootOption Boot address option byte to be programmed, + * This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION + (OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH) + * + * @param BootAddress0 Specifies the CM4 Boot Address 0. + * @param BootAddress1 Specifies the CM4 Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADD_OPTION(BootOption)); + + if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress0)); + + /* Configure CM4 BOOT ADD0 */ + MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16)); + + } + + if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1) + { + /* Check the parameters */ + assert_param(IS_BOOT_ADDRESS(BootAddress1)); + + /* Configure CM4 BOOT ADD1 */ + MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1); + } +} + +/** + * @brief Get CM4 Boot address + * @param BootAddress0 Specifies the CM4 Boot Address 0. + * @param BootAddress1 Specifies the CM4 Boot Address 1. + * @retval HAL Status + */ +static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1) +{ + uint32_t regvalue; + + regvalue = FLASH->BOOT4_CUR; + + (*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16; + (*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1); +} +#endif /*DUAL_CORE*/ + +/** + * @brief Set secure area configuration + * @param SecureAreaConfig specify if the secure area will be deleted or not + * when RDP level decreased from Level 1 to Level 0 or during a mass erase. + * + * @param SecureAreaStartAddr Specifies the secure area start address + * @param SecureAreaEndAddr Specifies the secure area end address + * @param Banks the specific bank to apply Security protection + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Secure area on specified bank1 area + * @arg FLASH_BANK_2: Secure area on specified bank2 area + * @arg FLASH_BANK_BOTH: Secure area on specified bank1 and bank2 area (same config will be applied on both banks) + * @retval None + */ +static void FLASH_OB_SecureAreaConfig(uint32_t SecureAreaConfig, uint32_t SecureAreaStartAddr, uint32_t SecureAreaEndAddr, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_OB_SECURE_RDP(SecureAreaConfig)); + + if((Banks & FLASH_BANK_1) == FLASH_BANK_1) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(SecureAreaEndAddr)); + + /* Configure the secure area */ + FLASH->SCAR_PRG1 = ((SecureAreaStartAddr - FLASH_BANK1_BASE) >> 8) | \ + (((SecureAreaEndAddr - FLASH_BANK1_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ + (SecureAreaConfig & FLASH_SCAR_DMES); + } + +#if defined (DUAL_BANK) + if((Banks & FLASH_BANK_2) == FLASH_BANK_2) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(SecureAreaEndAddr)); + + /* Configure the secure area */ + FLASH->SCAR_PRG2 = ((SecureAreaStartAddr - FLASH_BANK2_BASE) >> 8) | \ + (((SecureAreaEndAddr - FLASH_BANK2_BASE) >> 8) << FLASH_SCAR_SEC_AREA_END_Pos) | \ + (SecureAreaConfig & FLASH_SCAR_DMES); + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Get secure area configuration + * @param SecureAreaConfig indicates if the secure area will be deleted or not + * when RDP level decreased from Level 1 to Level 0 or during a mass erase. + * @param SecureAreaStartAddr gives the secure area start address + * @param SecureAreaEndAddr gives the secure area end address + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureAreaStartAddr, uint32_t *SecureAreaEndAddr, uint32_t Bank) +{ + uint32_t regvalue = 0; + uint32_t bankBase = 0; + + /* Check Bank parameter value */ + if(Bank == FLASH_BANK_1) + { + regvalue = FLASH->SCAR_CUR1; + bankBase = FLASH_BANK1_BASE; + } + +#if defined (DUAL_BANK) + if(Bank == FLASH_BANK_2) + { + regvalue = FLASH->SCAR_CUR2; + bankBase = FLASH_BANK2_BASE; + } +#endif /* DUAL_BANK */ + + /* Get the secure area settings */ + (*SecureAreaConfig) = (regvalue & FLASH_SCAR_DMES); + (*SecureAreaStartAddr) = ((regvalue & FLASH_SCAR_SEC_AREA_START) << 8) + bankBase; + (*SecureAreaEndAddr) = (regvalue & FLASH_SCAR_SEC_AREA_END) >> FLASH_SCAR_SEC_AREA_END_Pos; + (*SecureAreaEndAddr) = ((*SecureAreaEndAddr) << 8) + bankBase; +} + +/** + * @brief Add a CRC sector to the list of sectors on which the CRC will be calculated + * @param Sector Specifies the CRC sector number + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + + if (Bank == FLASH_BANK_1) + { + /* Clear CRC sector */ + FLASH->CRCCR1 &= (~FLASH_CRCCR_CRC_SECT); + + /* Select CRC Sector and activate ADD_SECT bit */ + FLASH->CRCCR1 |= Sector | FLASH_CRCCR_ADD_SECT; + } +#if defined (DUAL_BANK) + else + { + /* Clear CRC sector */ + FLASH->CRCCR2 &= (~FLASH_CRCCR_CRC_SECT); + + /* Select CRC Sector and activate ADD_SECT bit */ + FLASH->CRCCR2 |= Sector | FLASH_CRCCR_ADD_SECT; + } +#endif /* DUAL_BANK */ +} + +/** + * @brief Select CRC start and end memory addresses on which the CRC will be calculated + * @param CRCStartAddr Specifies the CRC start address + * @param CRCEndAddr Specifies the CRC end address + * @param Bank Specifies the Bank + * @retval None + */ +static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank) +{ + if (Bank == FLASH_BANK_1) + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK1(CRCEndAddr)); + + /* Write CRC Start and End addresses */ + FLASH->CRCSADD1 = CRCStartAddr; + FLASH->CRCEADD1 = CRCEndAddr; + } +#if defined (DUAL_BANK) + else + { + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCStartAddr)); + assert_param(IS_FLASH_PROGRAM_ADDRESS_BANK2(CRCEndAddr)); + + /* Write CRC Start and End addresses */ + FLASH->CRCSADD2 = CRCStartAddr; + FLASH->CRCEADD2 = CRCEndAddr; + } +#endif /* DUAL_BANK */ +} +/** + * @} + */ + +#if defined (FLASH_OTPBL_LOCKBL) +/** + * @brief Configure the OTP Block Lock. + * @param OTP_Block specifies the OTP Block to lock. + * This parameter can be a value of @ref FLASHEx_OTP_Blocks + * @retval None + */ +static void FLASH_OB_OTP_LockConfig(uint32_t OTP_Block) +{ + /* Check the parameters */ + assert_param(IS_OTP_BLOCK(OTP_Block)); + + /* Configure the OTP Block lock in the option bytes register */ + FLASH->OTPBL_PRG |= (OTP_Block & FLASH_OTPBL_LOCKBL); +} + +/** + * @brief Get the OTP Block Lock. + * @retval OTP_Block specifies the OTP Block to lock. + * This return value can be a value of @ref FLASHEx_OTP_Blocks + */ +static uint32_t FLASH_OB_OTP_GetLock(void) +{ + return (FLASH->OTPBL_CUR); +} +#endif /* FLASH_OTPBL_LOCKBL */ + +#if defined (FLASH_OPTSR2_TCM_AXI_SHARED) +/** + * @brief Configure the TCM / AXI Shared RAM. + * @param SharedRamConfig specifies the Shared RAM configuration. + * This parameter can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + * @retval None + */ +static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_TCM_AXI_SHARED(SharedRamConfig)); + + /* Configure the TCM / AXI Shared RAM in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_TCM_AXI_SHARED, SharedRamConfig); +} + +/** + * @brief Get the TCM / AXI Shared RAM configuration. + * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration. + * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED + */ +static uint32_t FLASH_OB_SharedRAM_GetConfig(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED); +} +#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ + +#if defined (FLASH_OPTSR2_CPUFREQ_BOOST) +/** + * @brief Configure the CPU Frequency Boost. + * @param FreqBoost specifies the CPU Frequency Boost state. + * This parameter can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + * @retval None + */ +static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost) +{ + /* Check the parameters */ + assert_param(IS_OB_USER_CPUFREQ_BOOST(FreqBoost)); + + /* Configure the CPU Frequency Boost in the option bytes register */ + MODIFY_REG(FLASH->OPTSR2_PRG, FLASH_OPTSR2_CPUFREQ_BOOST, FreqBoost); +} + +/** + * @brief Get the CPU Frequency Boost state. + * @retval FreqBoost returns the CPU Frequency Boost state. + * This return value can be a value of @ref FLASHEx_OB_CPUFREQ_BOOST + */ +static uint32_t FLASH_OB_CPUFreq_GetBoost(void) +{ + return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST); +} +#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c new file mode 100644 index 0000000..3580f78 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c @@ -0,0 +1,555 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#if defined(DUAL_CORE) +#define EXTI_CPU1 (0x01000000U) +#define EXTI_CPU2 (0x02000000U) +#endif /*DUAL_CORE*/ +#define GPIO_NUMBER (16U) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t temp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0x00U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + temp = EXTI_CurrentCPU->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->EMR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI_CurrentCPU->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->IMR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t tmp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position) ; + + if (iocurrent != 0x00U) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FUL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration for Current CPU */ + EXTI_CurrentCPU->IMR1 &= ~(iocurrent); + EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence*/ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ +#if defined(DUAL_CORE) && defined(CORE_CM4) + if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#else + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#endif +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c new file mode 100644 index 0000000..d0fe63a --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c @@ -0,0 +1,1748 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hcd.c + * @author MCD Application Team + * @brief HCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a HCD_HandleTypeDef handle structure, for example: + HCD_HandleTypeDef hhcd; + + (#)Fill parameters of Init structure in HCD handle + + (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: + (##) Enable the HCD/USB Low Level interface clock using the following macros + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure HCD pin-out + (##) Configure HCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the HAL HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HAL_HCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +#ifdef HAL_HCD_MODULE_ENABLED +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @defgroup HCD HCD + * @brief HCD HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx; + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); + + USBx = hhcd->Instance; + + if (hhcd->State == HAL_HCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; + + if (hhcd->MspInitCallback == NULL) + { + hhcd->MspInitCallback = HAL_HCD_MspInit; + } + + /* Init the low level hardware */ + hhcd->MspInitCallback(hhcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_HCD_MspInit(hhcd); +#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ + } + + hhcd->State = HAL_HCD_STATE_BUSY; + + /* Disable DMA mode for FS instance */ + if ((USBx->CID & (0x1U << 8)) == 0U) + { + hhcd->Init.dma_enable = 0U; + } + + /* Disable the Interrupts */ + __HAL_HCD_DISABLE(hhcd); + + /* Init the Core (common init.) */ + (void)USB_CoreInit(hhcd->Instance, hhcd->Init); + + /* Force Host Mode*/ + (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE); + + /* Init Host */ + (void)USB_HostInit(hhcd->Instance, hhcd->Init); + + hhcd->State = HAL_HCD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_HIGH: High speed mode, + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef status; + + __HAL_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].dev_addr = dev_address; + hhcd->hc[ch_num].max_packet = mps; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].ep_type = ep_type; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + hhcd->hc[ch_num].speed = speed; + + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, mps); + + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(hhcd); + (void)USB_HC_Halt(hhcd->Instance, ch_num); + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return HAL_ERROR; + } + + hhcd->State = HAL_HCD_STATE_BUSY; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + if (hhcd->MspDeInitCallback == NULL) + { + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hhcd->MspDeInitCallback(hhcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_HCD_MspDeInit(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_DISABLE(hhcd); + + hhcd->State = HAL_HCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + hhcd->hc[ch_num].ep_is_in = direction; + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if ((token == 1U) && (direction == 0U)) /*send data */ + { + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + hhcd->hc[ch_num].xfer_len = length; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].state = HC_IDLE; + + return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); +} + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + uint32_t interrupt; + + /* Ensure that we are in device mode */ + if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) + { + return; + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); + } + + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle Host Disconnect Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) + { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Flush USB Fifo */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + + /* Handle Host Port Disconnect Interrupt */ +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->DisconnectCallback(hhcd); +#else + HAL_HCD_Disconnect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Host Port Interrupts */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) + { + HCD_Port_IRQHandler(hhcd); + } + + /* Handle Host SOF Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->SOFCallback(hhcd); +#else + HAL_HCD_SOF_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + /* Handle Host channel Interrupt */ + if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) + { + interrupt = USB_HC_ReadInterrupt(hhcd->Instance); + for (i = 0U; i < hhcd->Init.Host_channels; i++) + { + if ((interrupt & (1UL << (i & 0xFU))) != 0U) + { + if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) + { + HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); + } + else + { + HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + } + } + } + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); + } + } +} + + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB HCD Callback + * To be used instead of the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = pCallback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = pCallback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = pCallback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = pCallback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = pCallback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = pCallback; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Unregister an USB HCD Callback + * USB HCD callback is redirected to the weak predefined callback + * @param hhcd USB HCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID + * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID + * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID + * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID + * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID + * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + /* Setup Legacy weak Callbacks */ + if (hhcd->State == HAL_HCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_HCD_SOF_CB_ID : + hhcd->SOFCallback = HAL_HCD_SOF_Callback; + break; + + case HAL_HCD_CONNECT_CB_ID : + hhcd->ConnectCallback = HAL_HCD_Connect_Callback; + break; + + case HAL_HCD_DISCONNECT_CB_ID : + hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; + break; + + case HAL_HCD_PORT_ENABLED_CB_ID : + hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; + break; + + case HAL_HCD_PORT_DISABLED_CB_ID : + hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; + break; + + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hhcd->State == HAL_HCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HCD_MSPINIT_CB_ID : + hhcd->MspInitCallback = HAL_HCD_MspInit; + break; + + case HAL_HCD_MSPDEINIT_CB_ID : + hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; + break; + + default : + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + return status; +} + +/** + * @brief Register USB HCD Host Channel Notify URB Change Callback + * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = pCallback; + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hhcd); + + if (hhcd->State == HAL_HCD_STATE_READY) + { + hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hhcd); + + return status; +} +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + /* Enable port power */ + (void)USB_DriveVbus(hhcd->Instance, 1U); + + /* Enable global interrupt */ + __HAL_HCD_ENABLE(hhcd); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) +{ + __HAL_LOCK(hhcd); + (void)USB_StopHost(hhcd->Instance); + __HAL_UNLOCK(hhcd); + + return HAL_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) +{ + return (USB_ResetPort(hhcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HAL state + */ +HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL + */ +HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetCurrentFrame(hhcd->Instance)); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) +{ + return (USB_GetHostSpeed(hhcd->Instance)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + /* ... */ + } + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + } + + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) + { + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + /* ... */ + } + + if (hhcd->Init.dma_enable == 1U) + { + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else if (hhcd->hc[chnum].state == HC_BBLERR) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + hhcd->hc[chnum].ErrCnt = 0U; + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else + { + /* ... */ + } + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t num_packets; + + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + + if (hhcd->hc[chnum].do_ping == 1U) + { + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + /* transaction completed with NYET state, update do ping state */ + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) + { + hhcd->hc[chnum].state = HC_NYET; + hhcd->hc[chnum].do_ping = 1U; + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + + if (hhcd->hc[chnum].do_ping == 0U) + { + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) + { + hhcd->hc[chnum].do_ping = 1U; + } + } + + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else + { + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) + { + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) + { + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } + } + else + { + return; + } + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#else + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + else + { + /* ... */ + } +} + +/** + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none + */ +static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t pktsts; + uint32_t pktcnt; + uint32_t GrxstspReg; + uint32_t xferSizePktCnt; + uint32_t tmpreg; + uint32_t chnum; + + GrxstspReg = hhcd->Instance->GRXSTSP; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; + + switch (pktsts) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) + { + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) + { + (void)USB_ReadPacket(hhcd->Instance, + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); + + /* manage multiple Xfer */ + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; + + /* get transfer size packet count */ + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_ERROR; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } +} + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USBx_HPRT0; + hprt0_dup = USBx_HPRT0; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) + { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->ConnectCallback(hhcd); +#else + HAL_HCD_Connect_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) + { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) + { + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); + } + else + { + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } + } + else + { + if (hhcd->Init.speed == HCD_SPEED_FULL) + { + USBx_HOST->HFIR = HFIR_60_MHZ; + } + } +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortEnabledCallback(hhcd); +#else + HAL_HCD_PortEnabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + + } + else + { +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->PortDisabledCallback(hhcd); +#else + HAL_HCD_PortDisabled_Callback(hhcd); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) + { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + } + + /* Clear Port Interrupts */ + USBx_HPRT0 = hprt0_dup; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_HCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c new file mode 100644 index 0000000..1d17bac --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c @@ -0,0 +1,447 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_hsem.c + * @author MCD Application Team + * @brief HSEM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the semaphore peripheral: + * + Semaphore Take function (2-Step Procedure) , non blocking + * + Semaphore FastTake function (1-Step Procedure) , non blocking + * + Semaphore Status check + * + Semaphore Clear Key Set and Get + * + Release and release all functions + * + Semaphore notification enabling and disabling and callnack functions + * + IRQ handler management + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters : + (++) the semaphore ID from 0 to 31 + (++) the process ID from 0 to 255 + (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter : + (++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero + (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter : + (++) the semaphore ID from 0_ID to 31 + (++) It returns 1 if the given semaphore is taken otherwise (Free) zero + (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters : + (++) the semaphore ID from 0 to 31 + (++) the process ID from 0 to 255: + (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt + may be generated when enabled (notification activated). If ProcessID or MasterID does not match, + semaphore remains taken (locked) + + (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All + This function takes as parameters : + (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by + HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions + (++) the Master ID: + (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds + to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the + Key or the MasterID doesn't match, semaphores remains taken (locked) + + (#)Semaphores Release all key functions: + (++) HAL_HSEM_SetClearKey() to set semaphore release all Key + (++) HAL_HSEM_GetClearKey() to get release all Key + (#)Semaphores notification functions : + (++) HAL_HSEM_ActivateNotification to activate a notification callback on + a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released + the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released + semaphores (bitfield). + + (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield). + (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask + Used by the notification functions + *** HSEM HAL driver macros list *** + ============================================= + [..] Below the list of most used macros in HSEM HAL driver. + + (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask. + [..] Example of use : + [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25). + [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example. + (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not. + (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags. + (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup HSEM HSEM + * @brief HSEM HAL module driver + * @{ + */ + +#ifdef HAL_HSEM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(DUAL_CORE) +/** @defgroup HSEM_Private_Constants HSEM Private Constants + * @{ + */ + +#ifndef HSEM_R_MASTERID +#define HSEM_R_MASTERID HSEM_R_COREID +#endif + +#ifndef HSEM_RLR_MASTERID +#define HSEM_RLR_MASTERID HSEM_RLR_COREID +#endif + +#ifndef HSEM_CR_MASTERID +#define HSEM_CR_MASTERID HSEM_CR_COREID +#endif + +/** + * @} + */ +#endif /* DUAL_CORE */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * +@verbatim + ============================================================================== + ##### HSEM Take and Release functions ##### + ============================================================================== +[..] This section provides functions allowing to: + (+) Take a semaphore with 2 Step method + (+) Fast Take a semaphore with 1 Step method + (+) Check semaphore state Taken or not + (+) Release a semaphore + (+) Release all semaphore at once + +@endverbatim + * @{ + */ + + +/** + * @brief Take a semaphore in 2 Step mode. + * @param SemID: semaphore ID from 0 to 31 + * @param ProcessID: Process ID from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + +#if USE_MULTI_CORE_SHARED_CODE != 0U + /* First step write R register with MasterID, processID and take bit=1*/ + HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK); + + /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */ + if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK)) + { + /*take success when MasterID and ProcessID match and take bit set*/ + return HAL_OK; + } +#else + /* First step write R register with MasterID, processID and take bit=1*/ + HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK); + + /* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */ + if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK)) + { + /*take success when MasterID and ProcessID match and take bit set*/ + return HAL_OK; + } +#endif + + /* Semaphore take fails*/ + return HAL_ERROR; +} + +/** + * @brief Fast Take a semaphore with 1 Step mode. + * @param SemID: semaphore ID from 0 to 31 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + +#if USE_MULTI_CORE_SHARED_CODE != 0U + /* Read the RLR register to take the semaphore */ + if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK)) + { + /*take success when MasterID match and take bit set*/ + return HAL_OK; + } +#else + /* Read the RLR register to take the semaphore */ + if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK)) + { + /*take success when MasterID match and take bit set*/ + return HAL_OK; + } +#endif + + /* Semaphore take fails */ + return HAL_ERROR; +} +/** + * @brief Check semaphore state Taken or not. + * @param SemID: semaphore ID + * @retval HAL HSEM state + */ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID) +{ + return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL); +} + + +/** + * @brief Release a semaphore. + * @param SemID: semaphore ID from 0 to 31 + * @param ProcessID: Process ID from 0 to 255 + * @retval None + */ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + + /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */ +#if USE_MULTI_CORE_SHARED_CODE != 0U + HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID)); +#else + HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT); +#endif + +} + +/** + * @brief Release All semaphore used by a given Master . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @param CoreID: CoreID of the CPU that is using semaphores to be released + * @retval None + */ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID) +{ + assert_param(IS_HSEM_KEY(Key)); + assert_param(IS_HSEM_COREID(CoreID)); + + HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos)); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * +@verbatim + ============================================================================== + ##### HSEM Set and Get Key functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Set semaphore Key + (+) Get semaphore Key +@endverbatim + + * @{ + */ + +/** + * @brief Set semaphore Key . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @retval None + */ +void HAL_HSEM_SetClearKey(uint32_t Key) +{ + assert_param(IS_HSEM_KEY(Key)); + + MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos)); + +} + +/** + * @brief Get semaphore Key . + * @retval Semaphore Key , value from 0 to 0xFFFF + */ +uint32_t HAL_HSEM_GetClearKey(void) +{ + return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management + * @brief HSEM Notification functions. + * +@verbatim + ============================================================================== + ##### HSEM IRQ handler management and Notification functions ##### + ============================================================================== +[..] This section provides HSEM IRQ handler and Notification function. + +@endverbatim + * @{ + */ + +/** + * @brief Activate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_ActivateNotification(uint32_t SemMask) +{ +#if USE_MULTI_CORE_SHARED_CODE != 0U + /*enable the semaphore mask interrupts */ + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /*Use interrupt line 0 for CPU1 Master */ + HSEM->C1IER |= SemMask; + } + else /* HSEM_CPU2_COREID */ + { + /*Use interrupt line 1 for CPU2 Master*/ + HSEM->C2IER |= SemMask; + } +#else + HSEM_COMMON->IER |= SemMask; +#endif +} + +/** + * @brief Deactivate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask) +{ +#if USE_MULTI_CORE_SHARED_CODE != 0U + /*enable the semaphore mask interrupts */ + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /*Use interrupt line 0 for CPU1 Master */ + HSEM->C1IER &= ~SemMask; + } + else /* HSEM_CPU2_COREID */ + { + /*Use interrupt line 1 for CPU2 Master*/ + HSEM->C2IER &= ~SemMask; + } +#else + HSEM_COMMON->IER &= ~SemMask; +#endif +} + +/** + * @brief This function handles HSEM interrupt request + * @retval None + */ +void HAL_HSEM_IRQHandler(void) +{ + uint32_t statusreg; +#if USE_MULTI_CORE_SHARED_CODE != 0U + if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID) + { + /* Get the list of masked freed semaphores*/ + statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/ + + /*Disable Interrupts*/ + HSEM->C1IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM->C1ICR = ((uint32_t)statusreg); + } + else /* HSEM_CPU2_COREID */ + { + /* Get the list of masked freed semaphores*/ + statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/ + + /*Disable Interrupts*/ + HSEM->C2IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM->C2ICR = ((uint32_t)statusreg); + } +#else + /* Get the list of masked freed semaphores*/ + statusreg = HSEM_COMMON->MISR; + + /*Disable Interrupts*/ + HSEM_COMMON->IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM_COMMON->ICR = ((uint32_t)statusreg); + +#endif + /* Call FreeCallback */ + HAL_HSEM_FreeCallback(statusreg); +} + +/** + * @brief Semaphore Released Callback. + * @param SemMask: Mask of Released semaphores + * @retval None + */ +__weak void HAL_HSEM_FreeCallback(uint32_t SemMask) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(SemMask); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HSEM_FreeCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_HSEM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c new file mode 100644 index 0000000..c9ad0e7 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -0,0 +1,7268 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive stream or channel depends on Instance + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream or channel depends on Instance + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream or channel depends on Instance + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + hi2c->Instance->CR2 = (I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (I2C_Trials == Trials) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream or channel depends on Instance */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream or channel depends on Instance */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t treatdmaerror = 0U; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + if (hi2c->hdmatx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmaerror = 1U; + } + } + + if (hi2c->hdmarx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmaerror = 1U; + } + } + + /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */ + if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } +} + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + return HAL_OK; + } + else + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ + (hi2c->XferISR == I2C_Slave_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK, and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c new file mode 100644 index 0000000..d9b8e46 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32H7xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @note For all I2C5 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C5 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus); +} +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c new file mode 100644 index 0000000..d833271 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_jpeg.c @@ -0,0 +1,4199 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_jpeg.c + * @author MCD Application Team + * @brief JPEG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the JPEG encoder/decoder peripheral: + * + Initialization and de-initialization functions + * + JPEG processing functions encoding and decoding + * + JPEG decoding Getting Info and encoding configuration setting + * + JPEG enable/disable header parsing functions (for decoding) + * + JPEG Input/Output Buffer configuration. + * + JPEG callback functions + * + JPEG Abort/Pause/Resume functions + * + JPEG custom quantization tables setting functions + * + IRQ handler management + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required. + Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral. + + (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set + the encoding parameters (mandatory before calling the encoding function). + the application can change the encoding parameter ImageQuality from + 1 to 100 to obtain a more or less quality (visual quality vs the original row image), + and inversely more or less jpg file size. + + (#) Note that for decoding operation the JPEG peripheral output data are organized in + YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification + ISO/IEC 10918-1 standard. + It is up to the application to transform these YCbCr blocks to RGB data that can be display. + + Respectively, for Encoding operation the JPEG peripheral input should be organized + in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr + MCU blocks transformation before feeding the JPEG peripheral with data. + + (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively + a JPEG encoding/decoding operation in polling method (blocking). + + (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively + a JPEG encoding/decoding operation with Interrupt method (not blocking). + + (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively + a JPEG encoding/decoding operation with DMA method (not blocking). + + (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation + is a JPEG decoding to provide the application with JPEG image parameters. + This callback is asserted when the JPEG peripheral successfully parse the + JPEG header. + + (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding + operations to inform the application that the input buffer has been + consumed by the peripheral and to ask for a new data chunk if the operation + (encoding/decoding) has not been complete yet. + + (++) This CallBack should be implemented in the application side. It should + call the function HAL_JPEG_ConfigInputBuffer if new input data are available, + or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT + to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the + application to provide a new input data chunk. + Once the application succeed getting new data and if the input has been paused, + the application can call the function HAL_JPEG_ConfigInputBuffer to set the new + input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume. + If the application has ended feeding the HAL JPEG with input data (no more input data), the application + Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback) + with the parameter InDataLength set to zero. + + (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows + to the application to provide the input data (for encoding or decoding) by chunks. + If the new input data chunk is not available (because data should be read from an input file + for example) the application can pause the JPEG input (using function HAL_JPEG_Pause) + Once the new input data chunk is available ( read from a file for example), the application + can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk + then resume the JPEG HAL input by calling function HAL_JPEG_Resume. + + (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume. + any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available. + However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called + (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended + Transferring the previous chunk buffer to the JPEG peripheral. + + (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver + has filled the given output buffer with the given size. + + (++) This CallBack should be implemented in the application side. It should + call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver + with the new output buffer location and size to be used to store next data chunk. + if the application is not ready to provide the output chunk location then it can + call the function HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_OUTPUT + to inform the JPEG HAL driver that it shall pause output data. Once the application + is ready to receive the new data chunk (output buffer location free or available) it should call + the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver + with the new output chunk buffer location and size, then call HAL_JPEG_Resume + to inform the HAL that it shall resume outputting data in the given output buffer. + + (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows + the application to receive data from the JPEG peripheral by chunks. when a chunk + is received, the application can pause the HAL JPEG output data to be able to process + these received data (YCbCr to RGB conversion in case of decoding or data storage in case + of encoding). + + (++) The application can call functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume. + any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use. + However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called + (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended + Transferring the previous chunk buffer from the JPEG peripheral to the application. + + (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has + ended the current JPEG encoding operation, and all output data has been transmitted + to the application. + + (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has + ended the current JPEG decoding operation. and all output data has been transmitted + to the application. + + (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during + the current operation. the application can call the function HAL_JPEG_GetError() + to retrieve the error codes. + + (#) By default the HAL JPEG driver uses the default quantization tables + as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding. + User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables + Note that for decoding the quantization tables are automatically extracted from + the JPEG header. + + (#) To control JPEG state you can use the following function: HAL_JPEG_GetState() + + *** JPEG HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in JPEG HAL driver. + + (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state. + (+) __HAL_JPEG_ENABLE : Enable the JPEG peripheral. + (+) __HAL_JPEG_DISABLE : Disable the JPEG peripheral. + (+) __HAL_JPEG_GET_FLAG : Check the specified JPEG status flag. + (+) __HAL_JPEG_CLEAR_FLAG : Clear the specified JPEG status flag. + (+) __HAL_JPEG_ENABLE_IT : Enable the specified JPEG Interrupt. + (+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt. + (+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled). + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_JPEG_RegisterCallback() or HAL_JPEG_RegisterXXXCallback() + to register an interrupt callback. + + Function HAL_JPEG_RegisterCallback() allows to register following callbacks: + (+) EncodeCpltCallback : callback for end of encoding operation. + (+) DecodeCpltCallback : callback for end of decoding operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : JPEG MspInit. + (+) MspDeInitCallback : JPEG MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + For specific callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated + register callbacks : respectively HAL_JPEG_RegisterInfoReadyCallback(), + HAL_JPEG_RegisterGetDataCallback() and HAL_JPEG_RegisterDataReadyCallback(). + + Use function HAL_JPEG_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_JPEG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) EncodeCpltCallback : callback for end of encoding operation. + (+) DecodeCpltCallback : callback for end of decoding operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : JPEG MspInit. + (+) MspDeInitCallback : JPEG MspDeInit. + + For callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated + unregister callbacks : respectively HAL_JPEG_UnRegisterInfoReadyCallback(), + HAL_JPEG_UnRegisterGetDataCallback() and HAL_JPEG_UnRegisterDataReadyCallback(). + + By default, after the HAL_JPEG_Init() and when the state is HAL_JPEG_STATE_RESET + all callbacks are set to the corresponding weak functions : + examples HAL_JPEG_DecodeCpltCallback() , HAL_JPEG_GetDataCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_JPEG_Init()/ HAL_JPEG_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_JPEG_Init() / HAL_JPEG_DeInit() + keep and use the user MspInit/MspDeInit functions (registered beforehand) + + Callbacks can be registered/unregistered in HAL_JPEG_STATE_READY state only. + Exception done MspInit/MspDeInit callbacks that can be registered/unregistered + in HAL_JPEG_STATE_READY or HAL_JPEG_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_JPEG_RegisterCallback() before calling HAL_JPEG_DeInit() + or HAL_JPEG_Init() function. + + When The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +#ifdef HAL_JPEG_MODULE_ENABLED + +#if defined (JPEG) + +/** @defgroup JPEG JPEG + * @brief JPEG HAL module driver. + * @{ + */ + +/* Private define ------------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Constants + * @{ + */ +#define JPEG_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */ +#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162) /* Huffman AC table size : 162 codes*/ +#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12) /* Huffman AC table size : 12 codes*/ + +#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/ + +#define JPEG_FIFO_TH_SIZE ((uint32_t)8U) /* JPEG Input/Output HW FIFO Threshold in words*/ + +#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/ + +#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/ +#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/ +#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003) /* JPEG context : operation Mask */ + +#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004) /* JPEG context : Transfer use Polling */ +#define JPEG_CONTEXT_IT ((uint32_t)0x00000008) /* JPEG context : Transfer use Interrupt */ +#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000C) /* JPEG context : Transfer use DMA */ +#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000C) /* JPEG context : Transfer Mask */ + + +#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100) /* JPEG context : encoding config done */ + +#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000) /* JPEG context : Pause Input */ +#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000) /* JPEG context : Pause Output */ + +#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000) /* JPEG context : Use custom quantization tables */ + +#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000) /* JPEG context : ending with DMA in progress */ + +#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000) /* Process is on going */ +#define JPEG_PROCESS_DONE ((uint32_t)0x00000001) /* Process is done (ends) */ +/** + * @} + */ + +/* Private typedef -----------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Types + * @{ + */ + +/* + JPEG Huffman Table Structure definition : + This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification + */ +typedef struct +{ + /* These two fields directly represent the contents of a JPEG DHT marker */ + uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ + + uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ + + +} JPEG_ACHuffTableTypeDef; + +typedef struct +{ + /* These two fields directly represent the contents of a JPEG DHT marker */ + uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ + + uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ + + +} JPEG_DCHuffTableTypeDef; + +typedef struct +{ + uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE]; /*!< Code length */ + + uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ + +} JPEG_AC_HuffCodeTableTypeDef; + +typedef struct +{ + uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE]; /*!< Code length */ + + uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ + +} JPEG_DC_HuffCodeTableTypeDef; +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup JPEG_Private_Variables + * @{ + */ + +static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable = +{ + { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/ + + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ + +}; + +static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable = +{ + { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, /*Bits*/ + + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ +}; + +static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable = +{ + { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/ + + { + 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */ + 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, + 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, + 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, + 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, + 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, + 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, + 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, + 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, + 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, + 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, + 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, + 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, + 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, + 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, + 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, + 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, + 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, + 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa + } +}; + +static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable = +{ + { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/ + + { + 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */ + 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, + 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, + 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0, + 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34, + 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26, + 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38, + 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, + 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, + 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, + 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, + 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, + 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, + 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, + 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, + 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, + 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, + 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, + 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, + 0xf9, 0xfa + } +}; + +static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] = +{ + 0, 1, 8, 16, 9, 2, 3, 10, + 17, 24, 32, 25, 18, 11, 4, 5, + 12, 19, 26, 33, 40, 48, 41, 34, + 27, 20, 13, 6, 7, 14, 21, 28, + 35, 42, 49, 56, 57, 50, 43, 36, + 29, 22, 15, 23, 30, 37, 44, 51, + 58, 59, 52, 45, 38, 31, 39, 46, + 53, 60, 61, 54, 47, 55, 62, 63 +}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup JPEG_Private_Functions_Prototypes + * @{ + */ + +static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK); +static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, + JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable); +static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, + JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable); +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, + const __IO uint32_t *DCTableAddress); +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, + const __IO uint32_t *ACTableAddress); +static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg); +static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg); +static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, + __IO uint32_t *QTableAddress); +static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg); +static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg); +static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg); + +static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg); +static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg); +static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords); +static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords); +static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg); + +static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg); +static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg); +static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma); +static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma); +static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma); +static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions JPEG Exported Functions + * @{ + */ + +/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the JPEG peripheral and creates the associated handle + (+) DeInitialize the JPEG peripheral + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the JPEG according to the specified + * parameters in the JPEG_InitTypeDef and creates the associated handle. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg) +{ + /* These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. */ + static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] = + { + 16, 11, 10, 16, 24, 40, 51, 61, + 12, 12, 14, 19, 26, 58, 60, 55, + 14, 13, 16, 24, 40, 57, 69, 56, + 14, 17, 22, 29, 51, 87, 80, 62, + 18, 22, 37, 56, 68, 109, 103, 77, + 24, 35, 55, 64, 81, 104, 113, 92, + 49, 64, 78, 87, 103, 121, 120, 101, + 72, 92, 95, 98, 112, 100, 103, 99 + }; + static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] = + { + 17, 18, 24, 47, 99, 99, 99, 99, + 18, 21, 26, 66, 99, 99, 99, 99, + 24, 26, 56, 99, 99, 99, 99, 99, + 47, 66, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99, + 99, 99, 99, 99, 99, 99, 99, 99 + }; + + /* Check the JPEG handle allocation */ + if (hjpeg == NULL) + { + return HAL_ERROR; + } + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + if (hjpeg->State == HAL_JPEG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hjpeg->Lock = HAL_UNLOCKED; + + hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */ + hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */ + hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */ + hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */ + hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */ + hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */ + + if (hjpeg->MspInitCallback == NULL) + { + hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hjpeg->MspInitCallback(hjpeg); + } +#else + if (hjpeg->State == HAL_JPEG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hjpeg->Lock = HAL_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK */ + HAL_JPEG_MspInit(hjpeg); + } +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Start the JPEG Core*/ + __HAL_JPEG_ENABLE(hjpeg); + + /* Stop the JPEG encoding/decoding process*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /* init default quantization tables*/ + hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable); + hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable); + hjpeg->QuantTable2 = NULL; + hjpeg->QuantTable3 = NULL; + + /* init the default Huffman tables*/ + if (JPEG_Set_HuffEnc_Mem(hjpeg) != HAL_OK) + { + hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE; + + return HAL_ERROR; + } + + /* Enable header processing*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Reset the JPEG ErrorCode */ + hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; + + /*Clear the context filelds*/ + hjpeg->Context = 0; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the JPEG peripheral. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Check the JPEG handle allocation */ + if (hjpeg == NULL) + { + return HAL_ERROR; + } + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + if (hjpeg->MspDeInitCallback == NULL) + { + hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hjpeg->MspDeInitCallback(hjpeg); + +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_JPEG_MspDeInit(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Reset the JPEG ErrorCode */ + hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_RESET; + + /*Clear the context fields*/ + hjpeg->Context = 0; + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the JPEG MSP. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes JPEG MSP. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User JPEG Callback + * To be used instead of the weak predefined callback + * @param hjpeg JPEG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID + * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID + * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, + pJPEG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_ENCODE_CPLT_CB_ID : + hjpeg->EncodeCpltCallback = pCallback; + break; + + case HAL_JPEG_DECODE_CPLT_CB_ID : + hjpeg->DecodeCpltCallback = pCallback; + break; + + case HAL_JPEG_ERROR_CB_ID : + hjpeg->ErrorCallback = pCallback; + break; + + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = pCallback; + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_JPEG_STATE_RESET == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = pCallback; + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Unregister a JPEG Callback + * JPEG callabck is redirected to the weak predefined callback + * @param hjpeg JPEG handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID + * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID + * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_ENCODE_CPLT_CB_ID : + hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */ + break; + + case HAL_JPEG_DECODE_CPLT_CB_ID : + hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */ + break; + + case HAL_JPEG_ERROR_CB_ID : + hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_JPEG_STATE_RESET == hjpeg->State) + { + switch (CallbackID) + { + case HAL_JPEG_MSPINIT_CB_ID : + hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_JPEG_MSPDEINIT_CB_ID : + hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Register Info Ready JPEG Callback + * To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @param pCallback pointer to the Info Ready Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_InfoReadyCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->InfoReadyCallback = pCallback; + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief UnRegister the Info Ready JPEG Callback + * Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */ + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Register Get Data JPEG Callback + * To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback + * @param hjpeg JPEG handle + * @param pCallback pointer to the Get Data Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->GetDataCallback = pCallback; + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief UnRegister the Get Data JPEG Callback + * Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback + * @param hjpeg JPEG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */ + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief Register Data Ready JPEG Callback + * To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @param pCallback pointer to the Get Data Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg, + pJPEG_DataReadyCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->DataReadyCallback = pCallback; + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +/** + * @brief UnRegister the Data Ready JPEG Callback + * Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback + * @param hjpeg JPEG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (HAL_JPEG_STATE_READY == hjpeg->State) + { + hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */ + } + else + { + /* Update the error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hjpeg); + return status; +} + +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions + * @brief JPEG Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration + (+) HAL_JPEG_GetInfo() : Extract the image configuration from the JPEG header during the decoding + (+) HAL_JPEG_EnableHeaderParsing() : Enable JPEG Header parsing for decoding + (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding + (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding. + +@endverbatim + * @{ + */ + +/** + * @brief Set the JPEG encoding configuration. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pConf pointer to a JPEG_ConfTypeDef structure that contains + * the encoding configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf) +{ + uint32_t error; + uint32_t numberMCU; + uint32_t hfactor; + uint32_t vfactor; + uint32_t hMCU; + uint32_t vMCU; + + /* Check the JPEG handle allocation */ + if ((hjpeg == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace)); + assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling)); + assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality)); + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + hjpeg->State = HAL_JPEG_STATE_BUSY; + + hjpeg->Conf.ColorSpace = pConf->ColorSpace; + hjpeg->Conf.ChromaSubsampling = pConf->ChromaSubsampling; + hjpeg->Conf.ImageHeight = pConf->ImageHeight; + hjpeg->Conf.ImageWidth = pConf->ImageWidth; + hjpeg->Conf.ImageQuality = pConf->ImageQuality; + + /* Reset the Color Space : by default only one quantization table is used*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE; + + /* Set Number of color components*/ + if (hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE) + { + /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/ + hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING; + + JPEG_SetColorGrayScale(hjpeg); + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); + } + else if (hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE) + { + /* + Set the Color Space for YCbCr : 2 quantization tables are used + one for Luminance(Y) and one for both Chrominances (Cb & Cr) + */ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0; + + JPEG_SetColorYCBCR(hjpeg); + + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); + /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/ + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1)); + + if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL) + { + /*Use user customized quantization tables , 1 table per component*/ + /* use 3 quantization tables , one for each component*/ + hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE); + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1; + + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2)); + + /*Use Quantization 1 table for component 1*/ + hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT); + hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; + + /*Use Quantization 2 table for component 2*/ + hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT); + hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; + } + } + else /* ColorSpace == JPEG_CMYK_COLORSPACE */ + { + JPEG_SetColorCMYK(hjpeg); + + /* Set quantization table 0*/ + error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); + /*By default quantization table 0 for All components*/ + + if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL) + { + /*Use user customized quantization tables , 1 table per component*/ + /* use 4 quantization tables , one for each component*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE; + + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1)); + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2)); + error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3)); + + /*Use Quantization 1 table for component 1*/ + hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; + + /*Use Quantization 2 table for component 2*/ + hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; + + /*Use Quantization 3 table for component 3*/ + hjpeg->Instance->CONFR7 |= JPEG_CONFR7_QT; + } + } + + if (error != 0UL) + { + hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_ERROR; + } + /* Set the image size*/ + /* set the number of lines*/ + MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFFUL) << 16)); + /* set the number of pixels per line*/ + MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFFUL) << 16)); + + + if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/ + { + hfactor = 16; + vfactor = 16; + } + else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/ + { + hfactor = 16; + vfactor = 8; + } + else /* Default is 8x8 MCU, 4:4:4*/ + { + hfactor = 8; + vfactor = 8; + } + + hMCU = (hjpeg->Conf.ImageWidth / hfactor); + if ((hjpeg->Conf.ImageWidth % hfactor) != 0UL) + { + hMCU++; /*+1 for horizontal incomplete MCU */ + } + + vMCU = (hjpeg->Conf.ImageHeight / vfactor); + if ((hjpeg->Conf.ImageHeight % vfactor) != 0UL) + { + vMCU++; /*+1 for vertical incomplete MCU */ + } + + numberMCU = (hMCU * vMCU) - 1UL; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/ + /* Set the number of MCU*/ + hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU); + + hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Set the JPEG State to ready */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Return function status */ + return HAL_BUSY; + } + } +} + +/** + * @brief Extract the image configuration from the JPEG header during the decoding + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains + * The JPEG decoded header information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) +{ + uint32_t yblockNb; + uint32_t cBblockNb; + uint32_t cRblockNb; + + /* Check the JPEG handle allocation */ + if ((hjpeg == NULL) || (pInfo == NULL)) + { + return HAL_ERROR; + } + + /*Read the conf parameters */ + if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1) + { + pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE; + } + else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0UL) + { + pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE; + } + else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF) + { + pInfo->ColorSpace = JPEG_CMYK_COLORSPACE; + } + else + { + return HAL_ERROR; + } + + pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000UL) >> 16; + pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000UL) >> 16; + + if ((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE)) + { + yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4; + cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4; + cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4; + + if ((yblockNb == 1UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) + { + pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/ + } + else if ((yblockNb == 0UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + else if ((yblockNb == 3UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) + { + pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING; + } + else /*Default is 4:4:4*/ + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + } + else + { + pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; + } + + pInfo->ImageQuality = JPEG_GetQuality(hjpeg); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable JPEG Header parsing for decoding + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the JPEG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg) +{ + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Enable header processing*/ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; + + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_OK; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @brief Disable JPEG Header parsing for decoding + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the JPEG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg) +{ + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + /* Disable header processing*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR; + + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_OK; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @brief Modify the default Quantization tables used for JPEG encoding. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param QTable0 pointer to uint8_t , define the user quantification table for color component 1. + * If NULL assume no need to update the table and no error return + * @param QTable1 pointer to uint8_t , define the user quantification table for color component 2. + * If NULL assume no need to update the table and no error return. + * @param QTable2 pointer to uint8_t , define the user quantification table for color component 3, + * If NULL assume no need to update the table and no error return. + * @param QTable3 pointer to uint8_t , define the user quantification table for color component 4. + * If NULL assume no need to update the table and no error return. + * + * @retval HAL status + */ + + +HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, + uint8_t *QTable2, uint8_t *QTable3) +{ + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_BUSY; + + hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES; + + hjpeg->QuantTable0 = QTable0; + hjpeg->QuantTable1 = QTable1; + hjpeg->QuantTable2 = QTable2; + hjpeg->QuantTable3 = QTable3; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions + * @brief processing functions. + * +@verbatim + ============================================================================== + ##### JPEG processing functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_JPEG_Encode() : JPEG encoding with polling process + (+) HAL_JPEG_Decode() : JPEG decoding with polling process + (+) HAL_JPEG_Encode_IT() : JPEG encoding with interrupt process + (+) HAL_JPEG_Decode_IT() : JPEG decoding with interrupt process + (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process + (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process + (+) HAL_JPEG_Pause() : Pause the Input/Output processing + (+) HAL_JPEG_Resume() : Resume the JPEG Input/Output processing + (+) HAL_JPEG_ConfigInputBuffer() : Config Encoding/Decoding Input Buffer + (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer + (+) HAL_JPEG_Abort() : Aborts the JPEG Encoding/Decoding + +@endverbatim + * @{ + */ + +/** + * @brief Starts JPEG encoding with polling processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with Polling*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /* In Data length must be multiple of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /* Out Data length must be multiple of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /*JPEG data processing : In/Out FIFO transfer*/ + while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with polling processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + /* Get tick */ + tickstart = HAL_GetTick(); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with Polling*/ + /*Set the Context to Encode with Polling*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /*JPEG data processing : In/Out FIFO transfer*/ + while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_READY; + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG encoding with interrupt processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + else + { + if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with IT*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with interrupt processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with IT*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/ + hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/ + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG encoding with DMA processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, + uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State != HAL_JPEG_STATE_READY) + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + else + { + if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; + + /*Set the Context to Encode with DMA*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataInMCU; + hjpeg->pJpegOutBuffPtr = pDataOut; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /* JPEG encoding process using DMA */ + if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK) + { + /* Update State */ + hjpeg->State = HAL_JPEG_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts JPEG decoding with DMA processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, + uint8_t *pDataOutMCU, uint32_t OutDataLength) +{ + /* Check the parameters */ + assert_param((InDataLength >= 4UL)); + assert_param((OutDataLength >= 4UL)); + + /* Check In/out buffer allocation and size */ + if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hjpeg); + + if (hjpeg->State == HAL_JPEG_STATE_READY) + { + /*Change JPEG state*/ + hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; + + /*Set the Context to Decode with DMA*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); + hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA); + + /*Store In/out buffers pointers and size*/ + hjpeg->pJpegInBuffPtr = pDataIn; + hjpeg->pJpegOutBuffPtr = pDataOutMCU; + hjpeg->InDataLength = InDataLength; + hjpeg->OutDataLength = OutDataLength; + + /*Reset In/out data counter */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Init decoding process*/ + JPEG_Init_Process(hjpeg); + + /* JPEG decoding process using DMA */ + if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK) + { + /* Update State */ + hjpeg->State = HAL_JPEG_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_ERROR; + } + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + return HAL_BUSY; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Pause the JPEG Input/Output processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param XferSelection This parameter can be one of the following values : + * JPEG_PAUSE_RESUME_INPUT : Pause Input processing + * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing + * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) +{ + uint32_t mask = 0; + + assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; + } + + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; + mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; + mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); + } + __HAL_JPEG_DISABLE_IT(hjpeg, mask); + + } + else + { + /* Nothing to do */ + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Resume the JPEG Input/Output processing + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param XferSelection This parameter can be one of the following values : + * JPEG_PAUSE_RESUME_INPUT : Resume Input processing + * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing + * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) +{ + uint32_t mask = 0; + uint32_t xfrSize; + + assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); + + if ((hjpeg->Context & (JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)) == 0UL) + { + /* if nothing paused to resume return error*/ + return HAL_ERROR; + } + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); + /*if the MDMA In is triggred with JPEG In FIFO Threshold flag + then MDMA In buffer size is 32 bytes + + else (MDMA In is triggred with JPEG In FIFO not full flag) + then MDMA In buffer size is 4 bytes + */ + xfrSize = hjpeg->hdmain->Init.BufferTransferLength; + + if (xfrSize == 0UL) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; + return HAL_ERROR; + } + /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % xfrSize); + + + if (hjpeg->InDataLength > 0UL) + { + /* Start DMA FIFO In transfer */ + if (HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, + hjpeg->InDataLength, 1) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; + return HAL_ERROR; + } + } + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); + + if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL) + { + JPEG_DMA_PollResidualData(hjpeg); + } + else + { + /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag + then MDMA out buffer size is 32 bytes + else (MDMA Out is triggred with JPEG Out FIFO not empty flag) + then MDMA buffer size is 4 bytes + */ + xfrSize = hjpeg->hdmaout->Init.BufferTransferLength; + + if (xfrSize == 0UL) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; + return HAL_ERROR; + } + /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/ + hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % xfrSize); + + /* Start DMA FIFO Out transfer */ + if (HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, + hjpeg->OutDataLength, 1) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; + return HAL_ERROR; + } + } + + } + + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); + mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); + } + if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) + { + hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); + mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); + } + __HAL_JPEG_ENABLE_IT(hjpeg, mask); + + } + else + { + /* Nothing to do */ + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Config Encoding/Decoding Input Buffer. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module. + * @param pNewInputBuffer Pointer to the new input data buffer + * @param InDataLength Size in bytes of the new Input data buffer + * @retval HAL status + */ +void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength) +{ + hjpeg->pJpegInBuffPtr = pNewInputBuffer; + hjpeg->InDataLength = InDataLength; +} + +/** + * @brief Config Encoding/Decoding Output Buffer. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module. + * @param pNewOutputBuffer Pointer to the new output data buffer + * @param OutDataLength Size in bytes of the new Output data buffer + * @retval HAL status + */ +void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength) +{ + hjpeg->pJpegOutBuffPtr = pNewOutputBuffer; + hjpeg->OutDataLength = OutDataLength; +} + +/** + * @brief Aborts the JPEG Encoding/Decoding. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tickstart; + uint32_t tmpContext; + tmpContext = hjpeg->Context; + + /*Reset the Context operation and method*/ + hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA); + + if ((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + /* Stop the DMA In/out Xfer*/ + if (HAL_MDMA_Abort(hjpeg->hdmaout) != HAL_OK) + { + if (hjpeg->hdmaout->ErrorCode == HAL_MDMA_ERROR_TIMEOUT) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + } + } + if (HAL_MDMA_Abort(hjpeg->hdmain) != HAL_OK) + { + if (hjpeg->hdmain->ErrorCode == HAL_MDMA_ERROR_TIMEOUT) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + } + } + + } + + /* Stop the JPEG encoding/decoding process*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if the JPEG Codec is effectively disabled */ + while (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != 0UL) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > JPEG_TIMEOUT_VALUE) + { + /* Update error code */ + hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; + + /* Change the DMA state */ + hjpeg->State = HAL_JPEG_STATE_ERROR; + break; + } + } + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /* Reset JpegInCount and JpegOutCount */ + hjpeg->JpegInCount = 0; + hjpeg->JpegOutCount = 0; + + /*Reset the Context Pause*/ + hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT); + + /* Change the DMA state*/ + if (hjpeg->ErrorCode != HAL_JPEG_ERROR_NONE) + { + hjpeg->State = HAL_JPEG_STATE_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + /* Return function status */ + return HAL_ERROR; + } + else + { + hjpeg->State = HAL_JPEG_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + /* Return function status */ + return HAL_OK; + } + +} + + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions + * @brief JPEG process callback functions. + * +@verbatim + ============================================================================== + ##### JPEG Decode and Encode callback functions ##### + ============================================================================== + [..] This section provides callback functions: + (+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback + (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback. + (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback. + (+) HAL_JPEG_ErrorCallback() : JPEG error callback. + (+) HAL_JPEG_GetDataCallback() : Get New Data chunk callback. + (+) HAL_JPEG_DataReadyCallback() : Decoded/Encoded Data ready callback. + +@endverbatim + * @{ + */ + +/** + * @brief Decoding JPEG Info ready callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains + * The JPEG decoded header information + * @retval None + */ +__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(pInfo); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Encoding complete callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_EncodeCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Decoding complete callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_EncodeCpltCallback could be implemented in the user file + */ +} + +/** + * @brief JPEG error callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +__weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Get New Data chunk callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param NbDecodedData Number of consummed data in the previous chunk in bytes + * @retval None + */ +__weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(NbDecodedData); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_GetDataCallback could be implemented in the user file + */ +} + +/** + * @brief Decoded/Encoded Data ready callback. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param pDataOut pointer to the output data buffer + * @param OutDataLength number in bytes of data available in the specified output buffer + * @retval None + */ +__weak void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hjpeg); + UNUSED(pDataOut); + UNUSED(OutDataLength); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_JPEG_DataReadyCallback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management + * @brief JPEG IRQ handler. + * +@verbatim + ============================================================================== + ##### JPEG IRQ handler management ##### + ============================================================================== + [..] This section provides JPEG IRQ handler function. + (+) HAL_JPEG_IRQHandler() : handles JPEG interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief This function handles JPEG interrupt request. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg) +{ + switch (hjpeg->State) + { + case HAL_JPEG_STATE_BUSY_ENCODING: + case HAL_JPEG_STATE_BUSY_DECODING: + /* continue JPEG data encoding/Decoding*/ + /* JPEG data processing : In/Out FIFO transfer*/ + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + (void) JPEG_Process(hjpeg); + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + JPEG_DMA_ContinueProcess(hjpeg); + } + else + { + /* Nothing to do */ + } + break; + + default: + break; + } +} + +/** + * @} + */ + +/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] This section provides JPEG State and Errors function. + (+) HAL_JPEG_GetState() : permits to get in run-time the JPEG state. + (+) HAL_JPEG_GetError() : Returns the JPEG error code if any. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the JPEG state. + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG state + */ +HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg) +{ + return hjpeg->State; +} + +/** + * @brief Return the JPEG error code + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for the specified JPEG. + * @retval JPEG Error Code + */ +uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) +{ + return hjpeg->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @addtogroup JPEG_Private_Functions + * @{ + */ + +/** + * @brief Generates Huffman sizes/Codes Table from Bits/vals Table + * @param Bits pointer to bits table + * @param Huffsize pointer to sizes table + * @param Huffcode pointer to codes table + * @param LastK pointer to last Coeff (table dimension) + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) +{ + uint32_t i; + uint32_t p; + uint32_t l; + uint32_t code; + uint32_t si; + + /* Figure C.1: Generation of table of Huffman code sizes */ + p = 0; + for (l = 0; l < 16UL; l++) + { + i = (uint32_t)Bits[l]; + if ((p + i) > 256UL) + { + /* check for table overflow */ + return HAL_ERROR; + } + while (i != 0UL) + { + Huffsize[p] = (uint8_t) l + 1U; + p++; + i--; + } + } + Huffsize[p] = 0; + *LastK = p; + + /* Figure C.2: Generation of table of Huffman codes */ + code = 0; + si = Huffsize[0]; + p = 0; + while (Huffsize[p] != 0U) + { + while (((uint32_t) Huffsize[p]) == si) + { + Huffcode[p] = code; + p++; + code++; + } + /* code must fit in "size" bits (si), no code is allowed to be all ones*/ + if(si > 31UL) + { + return HAL_ERROR; + } + if (((uint32_t) code) >= (((uint32_t) 1) << si)) + { + return HAL_ERROR; + } + code <<= 1; + si++; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table + * that can programmed to the JPEG encoder registers + * @param AC_BitsValsTable pointer to AC huffman bits/vals table + * @param AC_SizeCodesTable pointer to AC huffman Sizes/Codes table + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, + JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable) +{ + HAL_StatusTypeDef error; + uint8_t huffsize[257]; + uint32_t huffcode[257]; + uint32_t k; + uint32_t l, lsb, msb; + uint32_t lastK; + + error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK); + if (error != HAL_OK) + { + return error; + } + + /* Figure C.3: Ordering procedure for encoding procedure code tables */ + k = 0; + + while (k < lastK) + { + l = AC_BitsValsTable->HuffVal[k]; + if (l == 0UL) + { + l = 160; /*l = 0x00 EOB code*/ + } + else if (l == 0xF0UL) /* l = 0xF0 ZRL code*/ + { + l = 161; + } + else + { + msb = (l & 0xF0UL) >> 4; + lsb = (l & 0x0FUL); + l = (msb * 10UL) + lsb - 1UL; + } + if (l >= JPEG_AC_HUFF_TABLE_SIZE) + { + return HAL_ERROR; /* Huffman Table overflow error*/ + } + else + { + AC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; + AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U; + k++; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table + * that can programmed to the JPEG encoder registers + * @param DC_BitsValsTable pointer to DC huffman bits/vals table + * @param DC_SizeCodesTable pointer to DC huffman Sizes/Codes table + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, + JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable) +{ + HAL_StatusTypeDef error; + + uint32_t k; + uint32_t l; + uint32_t lastK; + uint8_t huffsize[257]; + uint32_t huffcode[257]; + error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK); + if (error != HAL_OK) + { + return error; + } + /* Figure C.3: ordering procedure for encoding procedure code tables */ + k = 0; + + while (k < lastK) + { + l = DC_BitsValsTable->HuffVal[k]; + if (l >= JPEG_DC_HUFF_TABLE_SIZE) + { + return HAL_ERROR; /* Huffman Table overflow error*/ + } + else + { + DC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; + DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U; + k++; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the JPEG register with an DC huffman table at the given DC table address + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableDC pointer to DC huffman table + * @param DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, + const __IO uint32_t *DCTableAddress) +{ + HAL_StatusTypeDef error; + JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable; + uint32_t i; + uint32_t lsb; + uint32_t msb; + __IO uint32_t *address, *addressDef; + + if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0)) + { + address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL)); + } + else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1)) + { + address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL)); + } + else + { + return HAL_ERROR; + } + + if (HuffTableDC != NULL) + { + error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable); + if (error != HAL_OK) + { + return error; + } + addressDef = address; + *addressDef = 0x0FFF0FFF; + addressDef++; + *addressDef = 0x0FFF0FFF; + + i = JPEG_DC_HUFF_TABLE_SIZE; + while (i > 1UL) + { + i--; + address --; + msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & + 0xFFUL); + i--; + lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & + 0xFFUL); + + *address = lsb | (msb << 16); + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the JPEG register with an AC huffman table at the given AC table address + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param HuffTableAC pointer to AC huffman table + * @param ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. + * @retval HAL status + */ +static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, + const __IO uint32_t *ACTableAddress) +{ + HAL_StatusTypeDef error; + JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable; + uint32_t i, lsb, msb; + __IO uint32_t *address, *addressDef; + + if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC0)) + { + address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL)); + } + else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1)) + { + address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL)); + } + else + { + return HAL_ERROR; + } + + if (HuffTableAC != NULL) + { + error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable); + if (error != HAL_OK) + { + return error; + } + /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */ + /* Locations 162:175 of each AC table contain information used internally by the core */ + + addressDef = address; + for (i = 0; i < 3UL; i++) + { + *addressDef = 0x0FFF0FFF; + addressDef++; + } + *addressDef = 0x0FD10FD0; + addressDef++; + *addressDef = 0x0FD30FD2; + addressDef++; + *addressDef = 0x0FD50FD4; + addressDef++; + *addressDef = 0x0FD70FD6; + /* end of Locations 162:175 */ + + + i = JPEG_AC_HUFF_TABLE_SIZE; + while (i > 1UL) + { + i--; + address--; + msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & + 0xFFUL); + i--; + lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & + 0xFFUL); + + *address = lsb | (msb << 16); + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the JPEG encoder register huffman tables to used during + * the encdoing operation + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg) +{ + HAL_StatusTypeDef error; + + JPEG_Set_Huff_DHTMem(hjpeg); + error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable, + (hjpeg->Instance->HUFFENC_AC0)); + if (error != HAL_OK) + { + return error; + } + + error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable, + (hjpeg->Instance->HUFFENC_AC1)); + if (error != HAL_OK) + { + return error; + } + + error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable, + hjpeg->Instance->HUFFENC_DC0); + if (error != HAL_OK) + { + return error; + } + + error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable, + hjpeg->Instance->HUFFENC_DC1); + if (error != HAL_OK) + { + return error; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the JPEG register huffman tables to be included in the JPEG + * file header (used for encoding only) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg) +{ + JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable; + JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable; + JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable; + JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable; + uint32_t value, index; + __IO uint32_t *address; + + /* DC0 Huffman Table : BITS*/ + /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/ + address = (hjpeg->Instance->DHTMEM + 3); + index = 16; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableDC0->Bits[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC0->Bits[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC0->Bits[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC0->Bits[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* DC0 Huffman Table : Val*/ + /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */ + address = (hjpeg->Instance->DHTMEM + 6); + index = 12; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableDC0->HuffVal[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC0->HuffVal[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC0->HuffVal[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC0->HuffVal[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + } + + /* AC0 Huffman Table : BITS*/ + /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/ + address = (hjpeg->Instance->DHTMEM + 10UL); + index = 16; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableAC0->Bits[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC0->Bits[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC0->Bits[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC0->Bits[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* AC0 Huffman Table : Val*/ + /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */ + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */ + address = (hjpeg->Instance->DHTMEM + 51); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFFUL); + *address = value; + + /*continue setting 160 AC0 huffman values */ + address--; /* address = hjpeg->Instance->DHTMEM + 50*/ + index = 160; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableAC0->HuffVal[index - 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC0->HuffVal[index - 2UL] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC0->HuffVal[index - 3UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC0->HuffVal[index - 4UL] & 0xFFUL); + address--; + index -= 4UL; + } + + /* DC1 Huffman Table : BITS*/ + /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 51); + value = *address & 0x0000FFFFU; + value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFFUL) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 55); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFFUL); + *address = value; + + /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/ + address--; + index = 12; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableDC1->Bits[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC1->Bits[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC1->Bits[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC1->Bits[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* DC1 Huffman Table : Val*/ + /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */ + address = (hjpeg->Instance->DHTMEM + 55); + value = *address & 0x0000FFFFUL; + value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFFUL) << + 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */ + address = (hjpeg->Instance->DHTMEM + 58); + value = *address & 0xFFFF0000UL; + value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFFUL); + *address = value; + + /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/ + address--; + index = 8; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableDC1->HuffVal[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableDC1->HuffVal[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableDC1->HuffVal[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + } + + /* AC1 Huffman Table : BITS*/ + /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */ + address = (hjpeg->Instance->DHTMEM + 58); + value = *address & 0x0000FFFFU; + value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFFUL) << 16); + *address = value; + + /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */ + address = (hjpeg->Instance->DHTMEM + 62); + value = *address & 0xFFFF0000U; + value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFFUL); + *address = value; + + /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/ + address--; + index = 12; + while (index > 3UL) + { + + *address = (((uint32_t)HuffTableAC1->Bits[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC1->Bits[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC1->Bits[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC1->Bits[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + + } + /* AC1 Huffman Table : Val*/ + /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */ + /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */ + address = (hjpeg->Instance->DHTMEM + 62); + value = *address & 0x0000FFFFUL; + value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFFUL) << + 16); + *address = value; + + /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */ + address = (hjpeg->Instance->DHTMEM + 102); + index = 160; + while (index > 3UL) + { + *address = (((uint32_t)HuffTableAC1->HuffVal[index + 1UL] & 0xFFUL) << 24) | + (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFFUL) << 16) | + (((uint32_t)HuffTableAC1->HuffVal[index - 1UL] & 0xFFUL) << 8) | + ((uint32_t)HuffTableAC1->HuffVal[index - 2UL] & 0xFFUL); + address--; + index -= 4UL; + } + +} + +/** + * @brief Configure the JPEG registers with a given quantization table + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param QTable pointer to an array of 64 bytes giving the quantization table + * @param QTableAddress destination quantization address in the JPEG peripheral + * it could be QMEM0, QMEM1, QMEM2 or QMEM3 + * @retval 0 if no error, 1 if error + */ +static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, + __IO uint32_t *QTableAddress) +{ + uint32_t i; + uint32_t j; + uint32_t quantRow; + uint32_t quantVal; + uint32_t ScaleFactor; + __IO uint32_t *tableAddress; + + tableAddress = QTableAddress; + + if ((hjpeg->Conf.ImageQuality >= 50UL) && (hjpeg->Conf.ImageQuality <= 100UL)) + { + ScaleFactor = 200UL - (hjpeg->Conf.ImageQuality * 2UL); + } + else if (hjpeg->Conf.ImageQuality > 0UL) + { + ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality); + } + else + { + return 1UL; + } + + /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/ + i = 0; + while (i < (JPEG_QUANT_TABLE_SIZE - 3UL)) + { + quantRow = 0; + for (j = 0; j < 4UL; j++) + { + /* Note that the quantization coefficients must be specified in the table in zigzag order */ + quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i + j]]) * ScaleFactor) + 50UL) / 100UL; + + if (quantVal == 0UL) + { + quantVal = 1UL; + } + else if (quantVal > 255UL) + { + quantVal = 255UL; + } + else + { + /* Nothing to do, keep same value of quantVal */ + } + + quantRow |= ((quantVal & 0xFFUL) << (8UL * j)); + } + + i += 4UL; + *tableAddress = quantRow; + tableAddress ++; + } + + /* Return function status */ + return 0UL; +} + +/** + * @brief Configure the JPEG registers for YCbCr color space + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t ySamplingH; + uint32_t ySamplingV; + uint32_t yblockNb; + + /*Set Number of color components to 3*/ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_NF; + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1; + + /* compute MCU block size and Y, Cb ,Cr sampling factors*/ + if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ + + yblockNb = 0x30; /* 4 blocks of 8x8*/ + } + else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0x10; /* 2 blocks of 8x8*/ + } + else /*JPEG_444_SUBSAMPLING and default*/ + { + ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0; /* 1 block of 8x8*/ + } + + hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); + hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1); + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB)); + + /*Reset CONFR5 register*/ + hjpeg->Instance->CONFR5 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ + hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD); + + /*Reset CONFR6 register*/ + hjpeg->Instance->CONFR6 = 0; + /*Set Horizental and Vertical sampling factor and number of blocks for component 2*/ + /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */ + /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */ + hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD); + +} + +/** + * @brief Configure the JPEG registers for GrayScale color space + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg) +{ + /*Set Number of color components to 1*/ + hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); + + /*in GrayScale use 1 single Quantization table (Table 0)*/ + /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/ + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ; +} + +/** + * @brief Configure the JPEG registers for CMYK color space + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t ySamplingH; + uint32_t ySamplingV; + uint32_t yblockNb; + + /*Set Number of color components to 4*/ + hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS); + + /* compute MCU block size and Y, Cb ,Cr sampling factors*/ + if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ + + yblockNb = 0x30; /* 4 blocks of 8x8*/ + } + else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) + { + ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0x10; /* 2 blocks of 8x8*/ + } + else /*JPEG_444_SUBSAMPLING and default*/ + { + ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ + ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ + + yblockNb = 0; /* 1 block of 8x8*/ + } + + /*Reset CONFR4 register*/ + hjpeg->Instance->CONFR4 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ + hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB)); + + /*Reset CONFR5 register*/ + hjpeg->Instance->CONFR5 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ + hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0); + + /*Reset CONFR6 register*/ + hjpeg->Instance->CONFR6 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/ + hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0); + + /*Reset CONFR7 register*/ + hjpeg->Instance->CONFR7 = 0; + /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/ + hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0); +} + +/** + * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None + */ +static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg) +{ + /*Reset pause*/ + hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)); + + if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + /*Set JPEG Codec to Decoding mode */ + hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE; + } + else /* JPEG_CONTEXT_ENCODE */ + { + /*Set JPEG Codec to Encoding mode */ + hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE; + } + + /*Stop JPEG processing */ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Flush input and output FIFOs*/ + hjpeg->Instance->CR |= JPEG_CR_IFF; + hjpeg->Instance->CR |= JPEG_CR_OFF; + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /*Start Encoding/Decoding*/ + hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START; + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC | JPEG_IT_HPD); + } + else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) + { + /*Enable End Of Conversation, and End Of Header parsing interruptions*/ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); + + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief JPEG encoding/decoding process in case of Polling or Interrupt + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING + */ +static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext; + + /*End of header processing flag */ + if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) + { + /*Call Header parsing complete callback */ + (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); + /* Reset the ImageQuality */ + hjpeg->Conf.ImageQuality = 0; + /* Note : the image quality is only available at the end of the decoding operation */ + /* at the current stage the calculated image quality is not correct so reset it */ + + /*Call Info Ready callback */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf); +#else + HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD); + + /* Clear header processing done flag */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF); + } + } + + /*Input FIFO status handling*/ + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL) + { + /*Input FIFO threshold flag */ + /*JPEG_FIFO_TH_SIZE words can be written in */ + JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE); + } + else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL) + { + /*Input FIFO Not Full flag */ + /*32-bit value can be written in */ + JPEG_ReadInputData(hjpeg, 1); + } + else + { + /* Nothing to do */ + } + } + + + /*Output FIFO flag handling*/ + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL) + { + /*Output FIFO threshold flag */ + /*JPEG_FIFO_TH_SIZE words can be read out */ + JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE); + } + else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) + { + /*Output FIFO Not Empty flag */ + /*32-bit value can be read out */ + JPEG_StoreOutputData(hjpeg, 1); + } + else + { + /* Nothing to do */ + } + } + + /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/ + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF) + { + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) + { + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + } + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + /*Call End of conversion callback */ + if (hjpeg->JpegOutCount > 0UL) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + /*Reset Context Operation*/ + tmpContext = hjpeg->Context; + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DecodeCpltCallback(hjpeg); +#else + HAL_JPEG_DecodeCpltCallback(hjpeg); +#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ + } + else /* JPEG_CONTEXT_ENCODE */ + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->EncodeCpltCallback(hjpeg); +#else + HAL_JPEG_EncodeCpltCallback(hjpeg); +#endif + } + + return JPEG_PROCESS_DONE; + } + + + return JPEG_PROCESS_ONGOING; +} + +/** + * @brief Store some output data from the JPEG peripheral to the output buffer. + * This function is used when the JPEG peripheral has new data to output + * in case of Polling or Interrupt process + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param nbOutputWords Number of output words (of 32 bits) ready from the JPEG peripheral + * @retval None + */ +static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) +{ + uint32_t index; + uint32_t nb_words; + uint32_t nb_bytes; + uint32_t dataword; + + if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL))) + { + for (index = 0; index < nbOutputWords; index++) + { + /*Transfer 32 bits from the JPEG output FIFO*/ + dataword = hjpeg->Instance->DOR; + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24); + hjpeg->JpegOutCount += 4UL; + } + if (hjpeg->OutDataLength == hjpeg->JpegOutCount) + { + /*Output Buffer is full, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ + hjpeg->JpegOutCount = 0; + } + } + else if (hjpeg->OutDataLength > hjpeg->JpegOutCount) + { + nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL; + for (index = 0; index < nb_words; index++) + { + /*Transfer 32 bits from the JPEG output FIFO*/ + dataword = hjpeg->Instance->DOR; + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24); + hjpeg->JpegOutCount += 4UL; + } + if (hjpeg->OutDataLength == hjpeg->JpegOutCount) + { + /*Output Buffer is full, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + hjpeg->JpegOutCount = 0; + } + else + { + nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; + dataword = hjpeg->Instance->DOR; + for (index = 0; index < nb_bytes; index++) + { + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL); + hjpeg->JpegOutCount++; + } + /*Output Buffer is full, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + + nb_bytes = 4UL - nb_bytes; + for (index = nb_bytes; index < 4UL; index++) + { + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL); + hjpeg->JpegOutCount++; + } + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Read some input Data from the input buffer. + * This function is used when the JPEG peripheral needs new data + * in case of Polling or Interrupt process + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @param nbRequestWords Number of input words (of 32 bits) that the JPE peripheral request + * @retval None + */ +static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) +{ + uint32_t nb_bytes = 0; + uint32_t nb_words; + uint32_t index; + uint32_t dataword; + uint32_t input_count; + + if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL)) + { + /* No more Input data : nothing to do*/ + (void) HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT); + } + else if (hjpeg->InDataLength > hjpeg->JpegInCount) + { + nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount; + } + else if (hjpeg->InDataLength == hjpeg->JpegInCount) + { + /*Call HAL_JPEG_GetDataCallback to get new data */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount); +#else + HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); +#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ + + if (hjpeg->InDataLength > 4UL) + { + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); + } + hjpeg->JpegInCount = 0; + nb_bytes = hjpeg->InDataLength; + } + else + { + /* Nothing to do */ + } + if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL)) + { + nb_words = nb_bytes / 4UL; + if (nb_words >= nbRequestWords) + { + for (index = 0; index < nbRequestWords; index++) + { + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); + + hjpeg->JpegInCount += 4UL; + } + } + else /*nb_words < nbRequestWords*/ + { + if (nb_words > 0UL) + { + for (index = 0; index < nb_words; index++) + { + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); + + hjpeg->JpegInCount += 4UL; + } + } + else + { + /* end of file*/ + dataword = 0; + for (index = 0; index < nb_bytes; index++) + { + dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL)); + hjpeg->JpegInCount++; + } + hjpeg->Instance->DIR = dataword; + } + } + } +} + +/** + * @brief Start the JPEG DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING + */ +static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t inXfrSize, outXfrSize; + + /*if the MDMA In is triggred with JPEG In FIFO Threshold flag + then MDMA In buffer size is 32 bytes + else (MDMA In is triggred with JPEG In FIFO not full flag) + then MDMA In buffer size is 4 bytes + */ + inXfrSize = hjpeg->hdmain->Init.BufferTransferLength; + + /*if the MDMA Out is triggred with JPEG Out FIFO Threshold flag + then MDMA out buffer size is 32 bytes + else (MDMA Out is triggred with JPEG Out FIFO not empty flag) + then MDMA buffer size is 4 bytes + */ + outXfrSize = hjpeg->hdmaout->Init.BufferTransferLength; + + if ((hjpeg->InDataLength < inXfrSize) || (hjpeg->OutDataLength < outXfrSize)) + { + return HAL_ERROR; + } + /* Set the JPEG MDMA In transfer complete callback */ + hjpeg->hdmain->XferCpltCallback = JPEG_MDMAInCpltCallback; + /* Set the MDMA In error callback */ + hjpeg->hdmain->XferErrorCallback = JPEG_MDMAErrorCallback; + + /* Set the JPEG MDMA Out transfer complete callback */ + hjpeg->hdmaout->XferCpltCallback = JPEG_MDMAOutCpltCallback; + /* Set the MDMA In error callback */ + hjpeg->hdmaout->XferErrorCallback = JPEG_MDMAErrorCallback; + /* Set the MDMA Out Abort callback */ + hjpeg->hdmaout->XferAbortCallback = JPEG_MDMAOutAbortCallback; + + if ((inXfrSize == 0UL) || (outXfrSize == 0UL)) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + return HAL_ERROR; + } + /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize); + + /*MDMA transfer size (BNDTR) must be a multiple of MDMA buffer size (TLEN)*/ + hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % outXfrSize); + + + /* Start MDMA FIFO Out transfer */ + if (HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, + hjpeg->OutDataLength, 1) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + return HAL_ERROR; + } + /* Start DMA FIFO In transfer */ + if (HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, + hjpeg->InDataLength, 1) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Continue the current JPEG DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING + */ +static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) +{ + /*End of header processing flag rises*/ + if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) + { + /*Call Header parsing complete callback */ + (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); + + /* Reset the ImageQuality */ + hjpeg->Conf.ImageQuality = 0; + /* Note : the image quality is only available at the end of the decoding operation */ + /* at the current stage the calculated image quality is not correct so reset it */ + + /*Call Info Ready callback */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf); +#else + HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD); + + /* Clear header processing done flag */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF); + } + } + + /*End of Conversion handling*/ + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != 0UL) + { + + hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA; + + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Clear all flags */ + __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); + + if (hjpeg->hdmain->State == HAL_MDMA_STATE_BUSY) + { + /* Stop the MDMA In Xfer*/ + (void) HAL_MDMA_Abort_IT(hjpeg->hdmain); + } + + if (hjpeg->hdmaout->State == HAL_MDMA_STATE_BUSY) + { + /* Stop the MDMA out Xfer*/ + (void) HAL_MDMA_Abort_IT(hjpeg->hdmaout); + } + else + { + JPEG_DMA_EndProcess(hjpeg); + } + } + + +} + +/** + * @brief Finalize the current JPEG DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG_PROCESS_DONE + */ +static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext; + hjpeg->JpegOutCount = hjpeg->OutDataLength - (hjpeg->hdmaout->Instance->CBNDTR & MDMA_CBNDTR_BNDT); + + /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ + if (hjpeg->JpegOutCount == hjpeg->OutDataLength) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + /*Check if remaining data in the output FIFO*/ + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) + { + if (hjpeg->JpegOutCount > 0UL) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + tmpContext = hjpeg->Context; + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DecodeCpltCallback(hjpeg); +#else + HAL_JPEG_DecodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + else /* JPEG_CONTEXT_ENCODE */ + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->EncodeCpltCallback(hjpeg); +#else + HAL_JPEG_EncodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + } + else if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + JPEG_DMA_PollResidualData(hjpeg); + } + else + { + /* Nothing to do */ + } + +} + +/** + * @brief Poll residual output data when DMA process (encoding/decoding) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval None. + */ +static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t tmpContext; + uint32_t count; + uint32_t dataOut; + + for (count = JPEG_FIFO_SIZE; count > 0UL; count--) + { + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) + { + dataOut = hjpeg->Instance->DOR; + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataOut & 0x000000FFUL); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataOut & 0x0000FF00UL) >> 8); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataOut & 0x00FF0000UL) >> 16); + hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataOut & 0xFF000000UL) >> 24); + hjpeg->JpegOutCount += 4UL; + + if (hjpeg->JpegOutCount == hjpeg->OutDataLength) + { + /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + } + } + } + + tmpContext = hjpeg->Context; + + if ((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) || ((tmpContext & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)) + { + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + if (hjpeg->JpegOutCount > 0UL) + { + /*Output Buffer is not empty, call DecodedDataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + hjpeg->JpegOutCount = 0; + } + + tmpContext = hjpeg->Context; + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); + + /* Process Unlocked */ + __HAL_UNLOCK(hjpeg); + + /* Change the JPEG state */ + hjpeg->State = HAL_JPEG_STATE_READY; + + /*Call End of Encoding/Decoding callback */ + if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DecodeCpltCallback(hjpeg); +#else + HAL_JPEG_DecodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + else /* JPEG_CONTEXT_ENCODE */ + { +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->EncodeCpltCallback(hjpeg); +#else + HAL_JPEG_EncodeCpltCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief MDMA input transfer complete callback + * @param hmdma pointer to a MDMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_MDMAInCpltCallback(MDMA_HandleTypeDef *hmdma) +{ + uint32_t inXfrSize; + + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent; + + /* Disable The JPEG IT so the MDMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + /* Check if context method is DMA and we are not in ending DMA stage */ + if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) == JPEG_CONTEXT_DMA) + { + + /*if the MDMA In is triggred with JPEG In FIFO Threshold flag + then MDMA In buffer size is 32 bytes + else (MDMA In is triggred with JPEG In FIFO not full flag) + then MDMA In buffer size is 4 bytes + */ + inXfrSize = hjpeg->hdmain->Init.BufferTransferLength; + + hjpeg->JpegInCount = hjpeg->InDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT); + + /*Call HAL_JPEG_GetDataCallback to get new data */ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount); +#else + HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + + if (hjpeg->InDataLength >= inXfrSize) + { + if (inXfrSize == 0UL) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->ErrorCallback(hjpeg); +#else + HAL_JPEG_ErrorCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + return; + } + /*JPEG Input MDMA transfer data number must be multiple of MDMA buffer size + as the destination is a 32 bits register */ + hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % inXfrSize); + + } + else if (hjpeg->InDataLength > 0UL) + { + /* Transfer the remaining Data, must be multiple of source data size (byte) and destination data size (word) */ + if ((hjpeg->InDataLength % 4UL) != 0UL) + { + hjpeg->InDataLength = ((hjpeg->InDataLength / 4UL) + 1UL) * 4UL; + } + } + else + { + /* Nothing to do */ + } + + if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (hjpeg->InDataLength > 0UL)) + { + /* Start MDMA FIFO In transfer */ + if (HAL_MDMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, + hjpeg->InDataLength, 1) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->ErrorCallback(hjpeg); +#else + HAL_JPEG_ErrorCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + return; + } + } + + /* JPEG Conversion still on going : Enable the JPEG IT */ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); + } +} + +/** + * @brief MDMA output transfer complete callback + * @param hmdma pointer to a MDMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_MDMAOutCpltCallback(MDMA_HandleTypeDef *hmdma) +{ + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent; + + + /* Disable The JPEG IT so the MDMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) == + JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */ + { + if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0UL) + { + hjpeg->JpegOutCount = hjpeg->OutDataLength - (hmdma->Instance->CBNDTR & MDMA_CBNDTR_BNDT); + + /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#else + HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + + if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) + { + /* Start MDMA FIFO Out transfer */ + if (HAL_MDMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, + hjpeg->OutDataLength, 1) != HAL_OK) + { + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + hjpeg->State = HAL_JPEG_STATE_ERROR; +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->ErrorCallback(hjpeg); +#else + HAL_JPEG_ErrorCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ + return; + } + } + } + + /* JPEG Conversion still on going : Enable the JPEG IT */ + __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); + } + +} + +/** + * @brief MDMA Transfer error callback + * @param hmdma pointer to a MDMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_MDMAErrorCallback(MDMA_HandleTypeDef *hmdma) +{ + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent; + + /*Stop Encoding/Decoding*/ + hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; + + /* Disable All Interrupts */ + __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); + + hjpeg->State = HAL_JPEG_STATE_READY; + hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; + +#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) + hjpeg->ErrorCallback(hjpeg); +#else + HAL_JPEG_ErrorCallback(hjpeg); +#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ +} + +/** + * @brief MDMA output Abort callback + * @param hmdma pointer to a MDMA_HandleTypeDef structure. + * @retval None + */ +static void JPEG_MDMAOutAbortCallback(MDMA_HandleTypeDef *hmdma) +{ + JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((MDMA_HandleTypeDef *)hmdma)->Parent; + + if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL) + { + JPEG_DMA_EndProcess(hjpeg); + } +} + + +/** + * @brief Calculate the decoded image quality (from 1 to 100) + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains + * the configuration information for JPEG module + * @retval JPEG image quality from 1 to 100. + */ +static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg) +{ + uint32_t quality = 0; + uint32_t quantRow, quantVal, scale, i, j; + __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0; + + i = 0; + while (i < (JPEG_QUANT_TABLE_SIZE - 3UL)) + { + quantRow = *tableAddress; + for (j = 0; j < 4UL; j++) + { + quantVal = (quantRow >> (8UL * j)) & 0xFFUL; + if (quantVal == 1UL) + { + /* if Quantization value = 1 then quality is 100%*/ + quality += 100UL; + } + else + { + /* Note that the quantization coefficients must be specified in the table in zigzag order */ + scale = (quantVal * 100UL) / ((uint32_t) hjpeg->QuantTable0[JPEG_ZIGZAG_ORDER[i + j]]); + + if (scale <= 100UL) + { + quality += (200UL - scale) / 2UL; + } + else + { + quality += 5000UL / scale; + } + } + } + + i += 4UL; + tableAddress ++; + } + + return (quality / 64UL); +} +/** + * @} + */ + +/** + * @} + */ +#endif /* JPEG */ +#endif /* HAL_JPEG_MODULE_ENABLED */ + + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c new file mode 100644 index 0000000..8277402 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c @@ -0,0 +1,2220 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_ltdc.c + * @author MCD Application Team + * @brief LTDC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the LTDC peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LTDC HAL driver can be used as follows: + + (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc; + + (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API: + (##) Enable the LTDC interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the LTDC interrupt priority + (+++) Enable the NVIC LTDC IRQ Channel + + (#) Initialize the required configuration through the following parameters: + the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity, + Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function + + *** Configuration *** + ========================= + [..] + (#) Program the required configuration through the following parameters: + the pixel format, the blending factors, input alpha value, the window size + and the image size using HAL_LTDC_ConfigLayer() function for foreground + or/and background layer. + + (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and + HAL_LTDC_EnableCLUT functions. + + (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). + + (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() + and HAL_LTDC_EnableColorKeying functions. + + (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() + function + + (#) If needed, reconfigure and change the pixel format value, the alpha value + value, the window size, the window position and the layer start address + for foreground or/and background layer using respectively the following + functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), + HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). + + (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. + This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) + then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). + + After calling the _NoReload functions to set different color/format/layer settings, + the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if + an immediate reload is required. + Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if + the reload should be done in the next vertical blanking period, + this option allows to avoid display flicker by applying the new settings during the vertical blanking period. + + + (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() + + *** LTDC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in LTDC HAL driver. + + (+) __HAL_LTDC_ENABLE: Enable the LTDC. + (+) __HAL_LTDC_DISABLE: Disable the LTDC. + (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer. + (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer. + (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration. + (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. + (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. + (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. + (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. + (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. + + [..] + (@) You can refer to the LTDC HAL driver header file for more useful macros + + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use function HAL_LTDC_RegisterCallback() to register a callback. + + [..] + Function HAL_LTDC_RegisterCallback() allows to register following callbacks: + (+) LineEventCallback : LTDC Line Event Callback. + (+) ReloadEventCallback : LTDC Reload Event Callback. + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit. + (+) MspDeInitCallback : LTDC MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) LineEventCallback : LTDC Line Event Callback + (+) ReloadEventCallback : LTDC Reload Event Callback + (+) ErrorCallback : LTDC Error Callback + (+) MspInitCallback : LTDC MspInit + (+) MspDeInitCallback : LTDC MspDeInit. + + [..] + By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit() + only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit() + or HAL_LTDC_Init() function. + + [..] + When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +#ifdef HAL_LTDC_MODULE_ENABLED + +#if defined (LTDC) + +/** @defgroup LTDC LTDC + * @brief LTDC HAL module driver + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Define LTDC Private Define + * @{ + */ +#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LTDC_Exported_Functions LTDC Exported Functions + * @{ + */ + +/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + (+) De-initialize the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tmp; + uint32_t tmp1; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); + assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); + assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); + assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); + assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); + assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); + assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); + assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); + assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); + assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); + assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); + assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + + /* Reset the LTDC callback to the legacy weak callbacks */ + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hltdc->MspInitCallback == NULL) + { + hltdc->MspInitCallback = HAL_LTDC_MspInit; + } + /* Init the low level hardware */ + hltdc->MspInitCallback(hltdc); + } +#else + if (hltdc->State == HAL_LTDC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_LTDC_MspInit(hltdc); + } +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the HS, VS, DE and PC polarity */ + hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); + hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ + hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); + + /* Set Synchronization size */ + hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); + tmp = (hltdc->Init.HorizontalSync << 16U); + hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); + + /* Set Accumulated Back porch */ + hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); + tmp = (hltdc->Init.AccumulatedHBP << 16U); + hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); + + /* Set Accumulated Active Width */ + hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); + tmp = (hltdc->Init.AccumulatedActiveW << 16U); + hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); + + /* Set Total Width */ + hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); + tmp = (hltdc->Init.TotalWidth << 16U); + hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); + + /* Set the background color value */ + tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); + hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); + hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); + + /* Enable the Transfer Error and FIFO underrun interrupts */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); + + /* Enable LTDC by setting LTDCEN bit */ + __HAL_LTDC_ENABLE(hltdc); + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-initialize the LTDC peripheral. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ + +HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) +{ + uint32_t tickstart; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + + /* Disable LTDC Layer 1 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1); + +#if defined(LTDC_Layer2_BASE) + /* Disable LTDC Layer 2 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2); +#endif /* LTDC_Layer2_BASE */ + + /* Reload during vertical blanking period */ + __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for VSYNC Interrupt */ + while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE) + { + break; + } + } + + /* Disable LTDC */ + __HAL_LTDC_DISABLE(hltdc); + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + if (hltdc->MspDeInitCallback == NULL) + { + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; + } + /* DeInit the low level hardware */ + hltdc->MspDeInitCallback(hltdc); +#else + /* DeInit the low level hardware */ + HAL_LTDC_MspDeInit(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + + /* Initialize the error code */ + hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-initialize the LTDC MSP. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LTDC Callback + * To be used instead of the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = pCallback; + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = pCallback; + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = pCallback; + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = pCallback; + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} + +/** + * @brief Unregister an LTDC Callback + * LTDC callback is redirected to the weak predefined callback + * @param hltdc ltdc handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID + * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID + * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hltdc); + + if (hltdc->State == HAL_LTDC_STATE_READY) + { + switch (CallbackID) + { + case HAL_LTDC_LINE_EVENT_CB_ID : + hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ + break; + + case HAL_LTDC_RELOAD_EVENT_CB_ID : + hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ + break; + + case HAL_LTDC_ERROR_CB_ID : + hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hltdc->State == HAL_LTDC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LTDC_MSPINIT_CB_ID : + hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ + break; + + case HAL_LTDC_MSPDEINIT_CB_ID : + hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hltdc); + + return status; +} +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides function allowing to: + (+) Handle LTDC interrupt request + +@endverbatim + * @{ + */ +/** + * @brief Handle LTDC interrupt request. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ +void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) +{ + uint32_t isrflags = READ_REG(hltdc->Instance->ISR); + uint32_t itsources = READ_REG(hltdc->Instance->IER); + + /* Transfer Error Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) + { + /* Disable the transfer Error interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); + + /* Clear the transfer error flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* FIFO underrun Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) + { + /* Disable the FIFO underrun interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); + + /* Clear the FIFO underrun flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); + + /* Update error code */ + hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Transfer error Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + hltdc->ErrorCallback(hltdc); +#else + /* Call legacy error callback*/ + HAL_LTDC_ErrorCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Line Interrupt management ************************************************/ + if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) + { + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Clear the Line interrupt flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Line interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered Line Event callback */ + hltdc->LineEventCallback(hltdc); +#else + /*Call Legacy Line Event callback */ + HAL_LTDC_LineEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } + + /* Register reload Interrupt management ***************************************/ + if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) + { + /* Disable the register reload interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); + + /* Clear the register reload flag */ + __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); + + /* Change LTDC state */ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + /* Reload interrupt Callback */ +#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) + /*Call registered reload Event callback */ + hltdc->ReloadEventCallback(hltdc); +#else + /*Call Legacy Reload Event callback */ + HAL_LTDC_ReloadEventCallback(hltdc); +#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Error LTDC callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Line Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_LineEventCallback could be implemented in the user file + */ +} + +/** + * @brief Reload Event callback. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval None + */ +__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hltdc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LTDC_ReloadEvenCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the LTDC foreground or/and background parameters. + (+) Set the active layer. + (+) Configure the color keying. + (+) Configure the C-LUT. + (+) Enable / Disable the color keying. + (+) Enable / Disable the C-LUT. + (+) Update the layer position. + (+) Update the layer size. + (+) Update pixel format on the fly. + (+) Update transparency on the fly. + (+) Update address on the fly. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the LTDC Layer according to the specified + * parameters in the LTDC_InitTypeDef and create the associated handle. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Load the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pCLUT pointer to the color lookup table address. + * @param CLUTSize the color lookup table size. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t counter; + uint32_t *pcolorlut = pCLUT; + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + for (counter = 0U; (counter < CLUTSize); counter++) + { + if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) + { + tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + else + { + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + } + + pcolorlut++; + + /* Specifies the C-LUT address and RGB value */ + LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; + } + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable Dither by setting DTEN bit */ + LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable Dither. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) +{ + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable Dither by setting DTEN bit */ + LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} +/** + * @brief Reconfigure the frame buffer Address. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Set the Immediate Reload type */ + hltdc->Instance->SRCR = LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous + * call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Set the Reload type as immediate update of LTDC pitch configured above */ + LTDC->SRCR |= LTDC_SRCR_IMR; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Define the position of the line interrupt. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Line Line Interrupt Position. + * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LIPOS(Line)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable the Line interrupt */ + __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); + + /* Set the Line Interrupt position */ + LTDC->LIPCR = (uint32_t)Line; + + /* Enable the Line interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reload LTDC Layers configuration. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param ReloadType This parameter can be one of the following values : + * LTDC_RELOAD_IMMEDIATE : Immediate Reload + * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking + * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) +{ + /* Check the parameters */ + assert_param(IS_LTDC_RELOAD(ReloadType)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable the Reload interrupt */ + __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); + + /* Apply Reload type */ + hltdc->Instance->SRCR = ReloadType; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Configure the LTDC Layer according to the specified without reloading + * parameters in the LTDC_InitTypeDef and create the associated handle. + * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains + * the configuration information for the Layer. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); + assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); + assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); + assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); + assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); + assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); + assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); + assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); + assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); + assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Copy new layer configuration into handle structure */ + hltdc->LayerCfg[LayerIdx] = *pLayerCfg; + + /* Configure the LTDC Layer */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Initialize the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window size without reloading. + * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param XSize LTDC Pixel per line + * @param YSize LTDC Line number + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters (Layers parameters)*/ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(XSize)); + assert_param(IS_LTDC_CFBLNBR(YSize)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal stop */ + pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; + + /* update vertical stop */ + pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; + + /* Reconfigures the color frame buffer pitch in byte */ + pLayerCfg->ImageWidth = XSize; + + /* Reconfigures the frame buffer line number */ + pLayerCfg->ImageHeight = YSize; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Set the LTDC window position without reloading. + * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param X0 LTDC window X offset + * @param Y0 LTDC window Y offset + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + assert_param(IS_LTDC_CFBLL(X0)); + assert_param(IS_LTDC_CFBLNBR(Y0)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* update horizontal start/stop */ + pLayerCfg->WindowX0 = X0; + pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; + + /* update vertical start/stop */ + pLayerCfg->WindowY0 = Y0; + pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the pixel format without reloading. + * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains + * the configuration information for the LTDC. + * @param Pixelformat new pixel format value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the pixel format */ + pLayerCfg->PixelFormat = Pixelformat; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the layer alpha value without reloading. + * Variant of the function HAL_LTDC_SetAlpha without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Alpha new alpha value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_ALPHA(Alpha)); + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Alpha value */ + pLayerCfg->Alpha = Alpha; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Reconfigure the frame buffer Address without reloading. + * Variant of the function HAL_LTDC_SetAddress without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param Address new address value. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) +{ + LTDC_LayerCfgTypeDef *pLayerCfg; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Get layer configuration from handle structure */ + pLayerCfg = &hltdc->LayerCfg[LayerIdx]; + + /* Reconfigure the Address */ + pLayerCfg->FBStartAdress = Address; + + /* Set LTDC parameters */ + LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by + * previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * Variant of the function HAL_LTDC_SetPitch without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. + * @param LayerIdx LTDC layer index concerned by the modification of line pitch. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t pitchUpdate; + uint32_t pixelFormat; + + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* get LayerIdx used pixel format */ + pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; + + if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + pitchUpdate = ((LinePitchInPixels * tmp) << 16U); + + /* Clear previously set standard pitch */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; + + /* Set new line pitch value */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + + +/** + * @brief Configure the color keying without reloading. + * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param RGBValue the color key value + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Configure the default color values */ + LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); + LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color keying without reloading. + * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Enable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color keying without reloading. + * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color keying by setting COLKEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Enable the color lookup table without reloading. + * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @brief Disable the color lookup table without reloading. + * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: + * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_LTDC_LAYER(LayerIdx)); + + /* Process locked */ + __HAL_LOCK(hltdc); + + /* Change LTDC peripheral state */ + hltdc->State = HAL_LTDC_STATE_BUSY; + + /* Disable LTDC color lookup table by setting CLUTEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; + + /* Change the LTDC state*/ + hltdc->State = HAL_LTDC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hltdc); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the LTDC handle state. + (+) Get the LTDC handle error code. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LTDC handle state. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval HAL state + */ +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->State; +} + +/** + * @brief Return the LTDC handle error code. + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @retval LTDC Error Code + */ +uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) +{ + return hltdc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup LTDC_Private_Functions LTDC Private Functions + * @{ + */ + +/** + * @brief Configure the LTDC peripheral + * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param pLayerCfg Pointer LTDC Layer Configuration structure + * @param LayerIdx LTDC Layer index. + * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) + * @retval None + */ +static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +{ + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + + /* Configure the horizontal start and stop position */ + tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + + /* Configure the vertical start and stop position */ + tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); + LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); + + /* Specifies the pixel format */ + LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); + LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); + + /* Configure the default color values */ + tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); + tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); + tmp2 = (pLayerCfg->Alpha0 << 24U); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | + LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); + + /* Specifies the constant alpha value */ + LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); + LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); + + /* Specifies the blending factors */ + LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); + LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); + + /* Configure the color frame buffer start address */ + LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); + LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); + + if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) + { + tmp = 4U; + } + else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) + { + tmp = 3U; + } + else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ + (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) + { + tmp = 2U; + } + else + { + tmp = 1U; + } + + /* Configure the color frame buffer pitch in byte */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 7U)); + /* Configure the frame buffer line number */ + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); + LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); + + /* Enable LTDC_Layer by setting LEN bit */ + LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* LTDC */ + +#endif /* HAL_LTDC_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c new file mode 100644 index 0000000..fec1737 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_ltdc_ex.c + * @author MCD Application Team + * @brief LTDC Extension HAL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) + +#if defined (LTDC) && defined (DSI) + +/** @defgroup LTDCEx LTDCEx + * @brief LTDC HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions + * @{ + */ + +/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the LTDC + +@endverbatim + * @{ + */ + +/** + * @brief Retrieve common parameters from DSI Video mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains + * the DSI video mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarity is inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; + hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */ + + /* Retrieve vertical timing parameters from DSI */ + hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; + hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + + return HAL_OK; +} + +/** + * @brief Retrieve common parameters from DSI Adapted command mode configuration structure + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains + * the configuration information for the LTDC. + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains + * the DSI command mode configuration parameters + * @note The implementation of this function is taking into account the LTDC + * polarities inversion as described in the current LTDC specification + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg) +{ + /* Retrieve signal polarities from DSI */ + + /* The following polarities are inverted: + LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH + LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH + LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ + + /* Note 1 : Code in line w/ Current LTDC specification */ + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; + hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; + + /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ + /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; + hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; + hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */ + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LTDC && DSI */ + +#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c new file mode 100644 index 0000000..089d9fb --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c @@ -0,0 +1,1899 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_mdma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Master Direct Memory Access (MDMA) peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the MDMA Channel + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and MDMA requests. + + (#) + For a given Channel use HAL_MDMA_Init function to program the required configuration through the following parameters: + transfer request , channel priority, data endianness, Source increment, destination increment , + source data size, destination data size, data alignment, source Burst, destination Burst , + buffer Transfer Length, Transfer Trigger Mode (buffer transfer, block transfer, repeated block transfer + or full transfer) source and destination block address offset, mask address and data. + + If using the MDMA in linked list mode then use function HAL_MDMA_LinkedList_CreateNode to fill a transfer node. + Note that parameters given to the function HAL_MDMA_Init corresponds always to the node zero. + Use function HAL_MDMA_LinkedList_AddNode to connect the created node to the linked list at a given position. + User can make a linked list circular using function HAL_MDMA_LinkedList_EnableCircularMode , this function will automatically connect the + last node of the list to the first one in order to make the list circular. + In this case the linked list will loop on node 1 : first node connected after the initial transfer defined by the HAL_MDMA_Init + + -@- The initial transfer itself (node 0 corresponding to the Init). + User can disable the circular mode using function HAL_MDMA_LinkedList_DisableCircularMode, this function will then remove + the connection between last node and first one. + + Function HAL_MDMA_LinkedList_RemoveNode can be used to remove (disconnect) a node from the transfer linked list. + When a linked list is circular (last node connected to first one), if removing node1 (node where the linked list loops), + the linked list remains circular and node 2 becomes the first one. + Note that if the linked list is made circular the transfer will loop infinitely (or until aborted by the user). + + [..] + (+) User can select the transfer trigger mode (parameter TransferTriggerMode) to define the amount of data to be + transfer upon a request : + (++) MDMA_BUFFER_TRANSFER : each request triggers a transfer of BufferTransferLength data + with BufferTransferLength defined within the HAL_MDMA_Init. + (++) MDMA_BLOCK_TRANSFER : each request triggers a transfer of a block + with block size defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + or within the current linked list node parameters. + (++) MDMA_REPEAT_BLOCK_TRANSFER : each request triggers a transfer of a number of blocks + with block size and number of blocks defined within the function HAL_MDMA_Start/HAL_MDMA_Start_IT + or within the current linked list node parameters. + (++) MDMA_FULL_TRANSFER : each request triggers a full transfer + all blocks and all nodes(if a linked list has been created using HAL_MDMA_LinkedList_CreateNode \ HAL_MDMA_LinkedList_AddNode). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_MDMA_Start() to start MDMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_MDMA_PollForTransfer() to poll for the end of current transfer or a transfer level + In this case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_MDMA_Abort() function to abort the current transfer : blocking method this API returns + when the abort ends or timeout (should not be called from an interrupt service routine). + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the MDMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the MDMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_MDMA_Start_IT() to start MDMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the MDMA interrupt is configured. + (+) Use HAL_MDMA_IRQHandler() called under MDMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_MDMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of MDMA handle structure). + + (+) Use HAL_MDMA_Abort_IT() function to abort the current transfer : non-blocking method. This API will finish the execution immediately + then the callback XferAbortCallback (if specified by the user) is asserted once the MDMA channel has effectively aborted. + (could be called from an interrupt service routine). + + (+) Use functions HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback respectevely to register unregister user callbacks + from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferBufferCpltCallback : buffer transfer complete callback. + (++) XferBlockCpltCallback : block transfer complete callback. + (++) XferRepeatBlockCpltCallback : repeated block transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + + [..] + (+) If the transfer Request corresponds to SW request (MDMA_REQUEST_SW) User can use function HAL_MDMA_GenerateSWRequest to + trigger requests manually. Function HAL_MDMA_GenerateSWRequest must be used with the following precautions: + (++) This function returns an error if used while the Transfer has ended or not started. + (++) If used while the current request has not been served yet (current request transfer on going) + this function returns an error and the new request is ignored. + + Generally this function should be used in conjunctions with the MDMA callbacks: + (++) example 1: + (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BUFFER_TRANSFER + (+++) Register a callback for buffer transfer complete (using callback ID set to HAL_MDMA_XFER_BUFFERCPLT_CB_ID) + (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first BufferTransferLength data. + (+++) When the buffer transfer complete callback is asserted first buffer has been transferred and user can ask for a new buffer transfer + request using HAL_MDMA_GenerateSWRequest. + + (++) example 2: + (+++) Configure a transfer with request set to MDMA_REQUEST_SW and trigger mode set to MDMA_BLOCK_TRANSFER + (+++) Register a callback for block transfer complete (using callback ID HAL_MDMA_XFER_BLOCKCPLT_CB_ID) + (+++) After calling HAL_MDMA_Start_IT the MDMA will issue the transfer of a first block of data. + (+++) When the block transfer complete callback is asserted the first block has been transferred and user can ask + for a new block transfer request using HAL_MDMA_GenerateSWRequest. + + [..] Use HAL_MDMA_GetState() function to return the MDMA state and HAL_MDMA_GetError() in case of error detection. + + *** MDMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in MDMA HAL driver. + + (+) __HAL_MDMA_ENABLE: Enable the specified MDMA Channel. + (+) __HAL_MDMA_DISABLE: Disable the specified MDMA Channel. + (+) __HAL_MDMA_GET_FLAG: Get the MDMA Channel pending flags. + (+) __HAL_MDMA_CLEAR_FLAG: Clear the MDMA Channel pending flags. + (+) __HAL_MDMA_ENABLE_IT: Enable the specified MDMA Channel interrupts. + (+) __HAL_MDMA_DISABLE_IT: Disable the specified MDMA Channel interrupts. + (+) __HAL_MDMA_GET_IT_SOURCE: Check whether the specified MDMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the header file of the MDMA HAL driver for more useful macros. + + [..] + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup MDMA MDMA + * @brief MDMA HAL module driver + * @{ + */ + +#ifdef HAL_MDMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup MDMA_Private_Constants + * @{ + */ +#define HAL_TIMEOUT_MDMA_ABORT 5U /* 5 ms */ +#define HAL_MDMA_CHANNEL_SIZE 0x40U /* an MDMA instance channel size is 64 byte */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup MDMA_Private_Functions_Prototypes + * @{ + */ +static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount); +static void MDMA_Init(MDMA_HandleTypeDef *hmdma); + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions MDMA Exported Functions + * @{ + */ + +/** @addtogroup MDMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to : + Initialize and de-initialize the MDMA channel. + Register and Unregister MDMA callbacks + [..] + The HAL_MDMA_Init() function follows the MDMA channel configuration procedures as described in + reference manual. + The HAL_MDMA_DeInit function allows to deinitialize the MDMA channel. + HAL_MDMA_RegisterCallback and HAL_MDMA_UnRegisterCallback functions allows + respectevely to register/unregister an MDMA callback function. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MDMA according to the specified + * parameters in the MDMA_InitTypeDef and create the associated handle. + * @param hmdma: Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDMA_STREAM_ALL_INSTANCE(hmdma->Instance)); + assert_param(IS_MDMA_PRIORITY(hmdma->Init.Priority)); + assert_param(IS_MDMA_ENDIANNESS_MODE(hmdma->Init.Endianness)); + assert_param(IS_MDMA_REQUEST(hmdma->Init.Request)); + assert_param(IS_MDMA_SOURCE_INC(hmdma->Init.SourceInc)); + assert_param(IS_MDMA_DESTINATION_INC(hmdma->Init.DestinationInc)); + assert_param(IS_MDMA_SOURCE_DATASIZE(hmdma->Init.SourceDataSize)); + assert_param(IS_MDMA_DESTINATION_DATASIZE(hmdma->Init.DestDataSize)); + assert_param(IS_MDMA_DATA_ALIGNMENT(hmdma->Init.DataAlignment)); + assert_param(IS_MDMA_SOURCE_BURST(hmdma->Init.SourceBurst)); + assert_param(IS_MDMA_DESTINATION_BURST(hmdma->Init.DestBurst)); + assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(hmdma->Init.BufferTransferLength)); + assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(hmdma->Init.TransferTriggerMode)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.SourceBlockAddressOffset)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(hmdma->Init.DestBlockAddressOffset)); + + + /* Allocate lock resource */ + __HAL_UNLOCK(hmdma); + + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Check if the MDMA channel is effectively disabled */ + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) + { + /* Update error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_TIMEOUT; + + /* Change the MDMA state */ + hmdma->State = HAL_MDMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the MDMA channel registers */ + MDMA_Init(hmdma); + + /* Reset the MDMA first/last linkedlist node addresses and node counter */ + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Initialize the MDMA state */ + hmdma->State = HAL_MDMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the MDMA peripheral + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_DeInit(MDMA_HandleTypeDef *hmdma) +{ + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Disable the selected MDMA Channelx */ + __HAL_MDMA_DISABLE(hmdma); + + /* Reset MDMA Channel control register */ + hmdma->Instance->CCR = 0; + hmdma->Instance->CTCR = 0; + hmdma->Instance->CBNDTR = 0; + hmdma->Instance->CSAR = 0; + hmdma->Instance->CDAR = 0; + hmdma->Instance->CBRUR = 0; + hmdma->Instance->CLAR = 0; + hmdma->Instance->CTBR = 0; + hmdma->Instance->CMAR = 0; + hmdma->Instance->CMDR = 0; + + /* Clear all flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma,(MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC)); + + /* Reset the MDMA first/last linkedlist node addresses and node counter */ + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Initialize the MDMA state */ + hmdma->State = HAL_MDMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return HAL_OK; +} + +/** + * @brief Config the Post request Mask address and Mask data + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param MaskAddress: specifies the address to be updated (written) with MaskData after a request is served. + * @param MaskData: specifies the value to be written to MaskAddress after a request is served. + * MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* if HW request set Post Request MaskAddress and MaskData, */ + if((hmdma->Instance->CTCR & MDMA_CTCR_SWRM) == 0U) + { + /* Set the HW request clear Mask and Data */ + hmdma->Instance->CMAR = MaskAddress; + hmdma->Instance->CMDR = MaskData; + + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + if(MaskAddress == 0U) + { + hmdma->Instance->CTCR &= ~MDMA_CTCR_BWM; + } + else + { + hmdma->Instance->CTCR |= MDMA_CTCR_BWM; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @brief Register callbacks + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CallbackID: User Callback identifier + * @param pCallback: pointer to callbacsk function. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + switch (CallbackID) + { + case HAL_MDMA_XFER_CPLT_CB_ID: + hmdma->XferCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + hmdma->XferBufferCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + hmdma->XferBlockCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + hmdma->XferRepeatBlockCpltCallback = pCallback; + break; + + case HAL_MDMA_XFER_ERROR_CB_ID: + hmdma->XferErrorCallback = pCallback; + break; + + case HAL_MDMA_XFER_ABORT_CB_ID: + hmdma->XferAbortCallback = pCallback; + break; + + default: + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CallbackID: User Callback identifier + * a HAL_MDMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + switch (CallbackID) + { + case HAL_MDMA_XFER_CPLT_CB_ID: + hmdma->XferCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_BUFFERCPLT_CB_ID: + hmdma->XferBufferCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_BLOCKCPLT_CB_ID: + hmdma->XferBlockCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID: + hmdma->XferRepeatBlockCpltCallback = NULL; + break; + + case HAL_MDMA_XFER_ERROR_CB_ID: + hmdma->XferErrorCallback = NULL; + break; + + case HAL_MDMA_XFER_ABORT_CB_ID: + hmdma->XferAbortCallback = NULL; + break; + + case HAL_MDMA_XFER_ALL_CB_ID: + hmdma->XferCpltCallback = NULL; + hmdma->XferBufferCpltCallback = NULL; + hmdma->XferBlockCpltCallback = NULL; + hmdma->XferRepeatBlockCpltCallback = NULL; + hmdma->XferErrorCallback = NULL; + hmdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### Linked list operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Create a linked list node + (+) Add a node to the MDMA linked list + (+) Remove a node from the MDMA linked list + (+) Enable/Disable linked list circular mode +@endverbatim + * @{ + */ + +/** + * @brief Initializes an MDMA Link Node according to the specified + * parameters in the pMDMA_LinkedListNodeConfig . + * @param pNode: Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * registers configurations. + * @param pNodeConfig: Pointer to a MDMA_LinkNodeConfTypeDef structure that contains + * the configuration information for the specified MDMA Linked List Node. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig) +{ + uint32_t addressMask; + uint32_t blockoffset; + + /* Check the MDMA peripheral state */ + if((pNode == NULL) || (pNodeConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_MDMA_PRIORITY(pNodeConfig->Init.Priority)); + assert_param(IS_MDMA_ENDIANNESS_MODE(pNodeConfig->Init.Endianness)); + assert_param(IS_MDMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_MDMA_SOURCE_INC(pNodeConfig->Init.SourceInc)); + assert_param(IS_MDMA_DESTINATION_INC(pNodeConfig->Init.DestinationInc)); + assert_param(IS_MDMA_SOURCE_DATASIZE(pNodeConfig->Init.SourceDataSize)); + assert_param(IS_MDMA_DESTINATION_DATASIZE(pNodeConfig->Init.DestDataSize)); + assert_param(IS_MDMA_DATA_ALIGNMENT(pNodeConfig->Init.DataAlignment)); + assert_param(IS_MDMA_SOURCE_BURST(pNodeConfig->Init.SourceBurst)); + assert_param(IS_MDMA_DESTINATION_BURST(pNodeConfig->Init.DestBurst)); + assert_param(IS_MDMA_BUFFER_TRANSFER_LENGTH(pNodeConfig->Init.BufferTransferLength)); + assert_param(IS_MDMA_TRANSFER_TRIGGER_MODE(pNodeConfig->Init.TransferTriggerMode)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.SourceBlockAddressOffset)); + assert_param(IS_MDMA_BLOCK_ADDR_OFFSET(pNodeConfig->Init.DestBlockAddressOffset)); + + assert_param(IS_MDMA_TRANSFER_LENGTH(pNodeConfig->BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(pNodeConfig->BlockCount)); + + + /* Configure next Link node Address Register to zero */ + pNode->CLAR = 0; + + /* Configure the Link Node registers*/ + pNode->CTBR = 0; + pNode->CMAR = 0; + pNode->CMDR = 0; + pNode->Reserved = 0; + + /* Write new CTCR Register value */ + pNode->CTCR = pNodeConfig->Init.SourceInc | pNodeConfig->Init.DestinationInc | \ + pNodeConfig->Init.SourceDataSize | pNodeConfig->Init.DestDataSize | \ + pNodeConfig->Init.DataAlignment| pNodeConfig->Init.SourceBurst | \ + pNodeConfig->Init.DestBurst | \ + ((pNodeConfig->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + pNodeConfig->Init.TransferTriggerMode; + + /* If SW request set the CTCR register to SW Request Mode*/ + if(pNodeConfig->Init.Request == MDMA_REQUEST_SW) + { + pNode->CTCR |= MDMA_CTCR_SWRM; + } + + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + if((pNodeConfig->Init.Request == MDMA_REQUEST_SW) || (pNodeConfig->PostRequestMaskAddress != 0U)) + { + pNode->CTCR |= MDMA_CTCR_BWM; + } + + /* Set the new CBNDTR Register value */ + pNode->CBNDTR = ((pNodeConfig->BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC; + + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ + if(pNodeConfig->Init.SourceBlockAddressOffset < 0) + { + pNode->CBNDTR |= MDMA_CBNDTR_BRSUM; + /*write new CBRUR Register value : source repeat block offset */ + blockoffset = (uint32_t)(- pNodeConfig->Init.SourceBlockAddressOffset); + pNode->CBRUR = blockoffset & 0x0000FFFFU; + } + else + { + /*write new CBRUR Register value : source repeat block offset */ + pNode->CBRUR = (((uint32_t) pNodeConfig->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + } + + /* if block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ + if(pNodeConfig->Init.DestBlockAddressOffset < 0) + { + pNode->CBNDTR |= MDMA_CBNDTR_BRDUM; + /*write new CBRUR Register value : destination repeat block offset */ + blockoffset = (uint32_t)(- pNodeConfig->Init.DestBlockAddressOffset); + pNode->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + else + { + /*write new CBRUR Register value : destination repeat block offset */ + pNode->CBRUR |= ((((uint32_t)pNodeConfig->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + + /* Configure MDMA Link Node data length */ + pNode->CBNDTR |= pNodeConfig->BlockDataLength; + + /* Configure MDMA Link Node destination address */ + pNode->CDAR = pNodeConfig->DstAddress; + + /* Configure MDMA Link Node Source address */ + pNode->CSAR = pNodeConfig->SrcAddress; + + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ + if(pNodeConfig->Init.Request != MDMA_REQUEST_SW) + { + /* Set the HW request in CTBR register */ + pNode->CTBR = pNodeConfig->Init.Request & MDMA_CTBR_TSEL; + /* Set the HW request clear Mask and Data */ + pNode->CMAR = pNodeConfig->PostRequestMaskAddress; + pNode->CMDR = pNodeConfig->PostRequestMaskData; + } + + addressMask = pNodeConfig->SrcAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHBSbus is used as source (read operation) on channel x */ + pNode->CTBR |= MDMA_CTBR_SBUS; + } + + addressMask = pNodeConfig->DstAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHB bus is used as destination (write operation) on channel x */ + pNode->CTBR |= MDMA_CTBR_DBUS; + } + + return HAL_OK; +} + +/** + * @brief Connect a node to the linked list. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param pNewNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * to be add to the list. + * @param pPrevNode : Pointer to the new node position in the linked list or zero to insert the new node + * at the end of the list + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode) +{ + MDMA_LinkNodeTypeDef *pNode; + uint32_t counter = 0, nodeInserted = 0; + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if((hmdma == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Check if this is the first node (after the Inititlization node) */ + if((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) + { + if(pPrevNode == NULL) + { + /* if this is the first node after the initialization + connect this node to the node 0 by updating + the MDMA channel CLAR register to this node address */ + hmdma->Instance->CLAR = (uint32_t)pNewNode; + /* Set the MDMA handle First linked List node*/ + hmdma->FirstLinkedListNodeAddress = pNewNode; + + /*reset New node link */ + pNewNode->CLAR = 0; + + /* Update the Handle last node address */ + hmdma->LastLinkedListNodeAddress = pNewNode; + + hmdma->LinkedListNodeCounter = 1; + } + else + { + hal_status = HAL_ERROR; + } + } + else if(hmdma->FirstLinkedListNodeAddress != pNewNode) + { + /* Check if the node to insert already exists*/ + pNode = hmdma->FirstLinkedListNodeAddress; + while((counter < hmdma->LinkedListNodeCounter) && (hal_status == HAL_OK)) + { + if(pNode->CLAR == (uint32_t)pNewNode) + { + hal_status = HAL_ERROR; /* error this node already exist in the linked list and it is not first node */ + } + pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + counter++; + } + + if(hal_status == HAL_OK) + { + /* Check if the previous node is the last one in the current list or zero */ + if((pPrevNode == hmdma->LastLinkedListNodeAddress) || (pPrevNode == NULL)) + { + /* insert the new node at the end of the list */ + pNewNode->CLAR = hmdma->LastLinkedListNodeAddress->CLAR; + hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)pNewNode; + /* Update the Handle last node address */ + hmdma->LastLinkedListNodeAddress = pNewNode; + /* Increment the linked list node counter */ + hmdma->LinkedListNodeCounter++; + } + else + { + /*insert the new node after the pPreviousNode node */ + pNode = hmdma->FirstLinkedListNodeAddress; + counter = 0; + while((counter < hmdma->LinkedListNodeCounter) && (nodeInserted == 0U)) + { + counter++; + if(pNode == pPrevNode) + { + /*Insert the new node after the previous one */ + pNewNode->CLAR = pNode->CLAR; + pNode->CLAR = (uint32_t)pNewNode; + /* Increment the linked list node counter */ + hmdma->LinkedListNodeCounter++; + nodeInserted = 1; + } + else + { + pNode = (MDMA_LinkNodeTypeDef *)pNode->CLAR; + } + } + + if(nodeInserted == 0U) + { + hal_status = HAL_ERROR; + } + } + } + } + else + { + hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } +} + +/** + * @brief Disconnect/Remove a node from the transfer linked list. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param pNode : Pointer to a MDMA_LinkNodeTypeDef structure that contains Linked list node + * to be removed from the list. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode) +{ + MDMA_LinkNodeTypeDef *ptmpNode; + uint32_t counter = 0, nodeDeleted = 0; + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if((hmdma == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else if(hmdma->FirstLinkedListNodeAddress == pNode) /* Deleting first node */ + { + /* Delete 1st node */ + if(hmdma->LastLinkedListNodeAddress == pNode) + { + /*if the last node is at the same time the first one (1 single node after the init node 0) + then update the last node too */ + + hmdma->FirstLinkedListNodeAddress = 0; + hmdma->LastLinkedListNodeAddress = 0; + hmdma->LinkedListNodeCounter = 0; + + hmdma->Instance->CLAR = 0; + } + else + { + if((uint32_t)hmdma->FirstLinkedListNodeAddress == hmdma->LastLinkedListNodeAddress->CLAR) + { + /* if last node is looping to first (circular list) one update the last node connection */ + hmdma->LastLinkedListNodeAddress->CLAR = pNode->CLAR; + } + + /* if deleting the first node after the initialization + connect the next node to the node 0 by updating + the MDMA channel CLAR register to this node address */ + hmdma->Instance->CLAR = pNode->CLAR; + hmdma->FirstLinkedListNodeAddress = (MDMA_LinkNodeTypeDef *)hmdma->Instance->CLAR; + /* Update the Handle node counter */ + hmdma->LinkedListNodeCounter--; + } + } + else /* Deleting any other node */ + { + /*Deleted node is not the first one : find it */ + ptmpNode = hmdma->FirstLinkedListNodeAddress; + while((counter < hmdma->LinkedListNodeCounter) && (nodeDeleted == 0U)) + { + counter++; + if(ptmpNode->CLAR == ((uint32_t)pNode)) + { + /* if deleting the last node */ + if(pNode == hmdma->LastLinkedListNodeAddress) + { + /*Update the linked list last node address in the handle*/ + hmdma->LastLinkedListNodeAddress = ptmpNode; + } + /* update the next node link after deleting pMDMA_LinkedListNode */ + ptmpNode->CLAR = pNode->CLAR; + nodeDeleted = 1; + /* Update the Handle node counter */ + hmdma->LinkedListNodeCounter--; + } + else + { + ptmpNode = (MDMA_LinkNodeTypeDef *)ptmpNode->CLAR; + } + } + + if(nodeDeleted == 0U) + { + /* last node reashed without finding the node to delete : return error */ + hal_status = HAL_ERROR; + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } +} + +/** + * @brief Make the linked list circular by connecting the last node to the first. + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else + { + /* to enable circular mode Last Node should be connected to first node */ + hmdma->LastLinkedListNodeAddress->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; + } + + } + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; +} + +/** + * @brief Disable the linked list circular mode by setting the last node connection to null + * @param hmdma : Pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma) +{ + HAL_StatusTypeDef hal_status = HAL_OK; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* If first and last node are null (no nodes in the list) : return error*/ + if(((uint32_t)hmdma->FirstLinkedListNodeAddress == 0U) || ((uint32_t)hmdma->LastLinkedListNodeAddress == 0U) || (hmdma->LinkedListNodeCounter == 0U)) + { + hal_status = HAL_ERROR; + } + else + { + /* to disable circular mode Last Node should be connected to NULL */ + hmdma->LastLinkedListNodeAddress->CLAR = 0; + } + + } + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + + return hal_status; +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start MDMA transfer + (+) Configure the source, destination address and data length and + Start MDMA transfer with interrupt + (+) Abort MDMA transfer + (+) Poll for transfer complete + (+) Generate a SW request (when Request is set to MDMA_REQUEST_SW) + (+) Handle MDMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the MDMA Transfer. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress : The source memory Buffer address + * @param DstAddress : The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount : The number of a blocks to be transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Start(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + /* Check the parameters */ + assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_MDMA_DISABLE(hmdma); + + /* Configure the source, destination address and the data length */ + MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); + + /* Enable the Peripheral */ + __HAL_MDMA_ENABLE(hmdma); + + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* activate If SW request mode*/ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Starts the MDMA Transfer with interrupts enabled. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress : The source memory Buffer address + * @param DstAddress : The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount : The number of a blocks to be transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + /* Check the parameters */ + assert_param(IS_MDMA_TRANSFER_LENGTH(BlockDataLength)); + assert_param(IS_MDMA_BLOCK_COUNT(BlockCount)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmdma); + + if(HAL_MDMA_STATE_READY == hmdma->State) + { + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_BUSY; + + /* Initialize the error code */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_MDMA_DISABLE(hmdma); + + /* Configure the source, destination address and the data length */ + MDMA_SetConfig(hmdma, SrcAddress, DstAddress, BlockDataLength, BlockCount); + + /* Enable Common interrupts i.e Transfer Error IT and Channel Transfer Complete IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC)); + + if(hmdma->XferBlockCpltCallback != NULL) + { + /* if Block transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BT); + } + + if(hmdma->XferRepeatBlockCpltCallback != NULL) + { + /* if Repeated Block transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BRT); + } + + if(hmdma->XferBufferCpltCallback != NULL) + { + /* if buffer transfer complete Callback is set enable the corresponding IT*/ + __HAL_MDMA_ENABLE_IT(hmdma, MDMA_IT_BFTC); + } + + /* Enable the Peripheral */ + __HAL_MDMA_ENABLE(hmdma); + + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* activate If SW request mode*/ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + /* Return error status */ + return HAL_BUSY; + } + + return HAL_OK; +} + +/** + * @brief Aborts the MDMA Transfer. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * + * @note After disabling a MDMA Channel, a check for wait until the MDMA Channel is + * effectively disabled is added. If a Channel is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Channel will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); + + /* Disable the channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Check if the MDMA Channel is effectively disabled */ + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if( (HAL_GetTick() - tickstart ) > HAL_TIMEOUT_MDMA_ABORT) + { + /* Update error code */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the MDMA state */ + hmdma->State = HAL_MDMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Clear all interrupt flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_FLAG_BT | MDMA_FLAG_BRT | MDMA_FLAG_BFTC)); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the MDMA state*/ + hmdma->State = HAL_MDMA_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Aborts the MDMA Transfer in Interrupt mode. + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma) +{ + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + /* No transfer ongoing */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hmdma->State = HAL_MDMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_MDMA_DISABLE(hmdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param CompleteLevel: Specifies the MDMA level complete. + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + uint32_t levelFlag, errorFlag; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_MDMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_MDMA_STATE_BUSY != hmdma->State) + { + /* No transfer ongoing */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + levelFlag = ((CompleteLevel == HAL_MDMA_FULL_TRANSFER) ? MDMA_FLAG_CTC : \ + (CompleteLevel == HAL_MDMA_BUFFER_TRANSFER)? MDMA_FLAG_BFTC : \ + (CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) ? MDMA_FLAG_BT : \ + MDMA_FLAG_BRT); + + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while(__HAL_MDMA_GET_FLAG(hmdma, levelFlag) == 0U) + { + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) + { + /* Get the transfer error source flag */ + errorFlag = hmdma->Instance->CESR; + + if((errorFlag & MDMA_CESR_TED) == 0U) + { + /* Update error code : Read Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; + } + else + { + /* Update error code : Write Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + } + + if((errorFlag & MDMA_CESR_TEMD) != 0U) + { + /* Update error code : Error Mask Data */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; + } + + if((errorFlag & MDMA_CESR_TELD) != 0U) + { + /* Update error code : Error Linked list */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; + } + + if((errorFlag & MDMA_CESR_ASE) != 0U) + { + /* Update error code : Address/Size alignment error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; + } + + if((errorFlag & MDMA_CESR_BSE) != 0U) + { + /* Update error code : Block Size error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; + } + + (void) HAL_MDMA_Abort(hmdma); /* if error then abort the current transfer */ + + /* + Note that the Abort function will + - Clear all transfer flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + + } + + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_TIMEOUT; + + (void) HAL_MDMA_Abort(hmdma); /* if timeout then abort the current transfer */ + + /* + Note that the Abort function will + - Clear all transfer flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + } + } + } + + /* Clear the transfer level flag */ + if(CompleteLevel == HAL_MDMA_BUFFER_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); + + } + else if(CompleteLevel == HAL_MDMA_BLOCK_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT)); + + } + else if(CompleteLevel == HAL_MDMA_REPEAT_BLOCK_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BFTC | MDMA_FLAG_BT | MDMA_FLAG_BRT)); + } + else if(CompleteLevel == HAL_MDMA_FULL_TRANSFER) + { + __HAL_MDMA_CLEAR_FLAG(hmdma, (MDMA_FLAG_BRT | MDMA_FLAG_BT | MDMA_FLAG_BFTC | MDMA_FLAG_CTC)); + + /* Process unlocked */ + __HAL_UNLOCK(hmdma); + + hmdma->State = HAL_MDMA_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Generate an MDMA SW request trigger to activate the request on the given Channel. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma) +{ + uint32_t request_mode; + + /* Check the MDMA peripheral handle */ + if(hmdma == NULL) + { + return HAL_ERROR; + } + + /* Get the softawre request mode */ + request_mode = hmdma->Instance->CTCR & MDMA_CTCR_SWRM; + + if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U) + { + /* if no Transfer on going (MDMA enable bit not set) return error */ + hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U)) + { + /* if an MDMA ongoing request has not yet end or if request mode is not SW request return error */ + hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY; + + return HAL_ERROR; + } + else + { + /* Set the SW request bit to activate the request on the Channel */ + hmdma->Instance->CCR |= MDMA_CCR_SWRQ; + + return HAL_OK; + } +} + +/** + * @brief Handles MDMA interrupt request. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval None + */ +void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma) +{ + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600U; + + uint32_t generalIntFlag, errorFlag; + + /* General Interrupt Flag management ****************************************/ + generalIntFlag = 1UL << ((((uint32_t)hmdma->Instance - (uint32_t)(MDMA_Channel0))/HAL_MDMA_CHANNEL_SIZE) & 0x1FU); + if((MDMA->GISR0 & generalIntFlag) == 0U) + { + return; /* the General interrupt flag for the current channel is down , nothing to do */ + } + + /* Transfer Error Interrupt management ***************************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_TE) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_TE) != 0U) + { + /* Disable the transfer error interrupt */ + __HAL_MDMA_DISABLE_IT(hmdma, MDMA_IT_TE); + + /* Get the transfer error source flag */ + errorFlag = hmdma->Instance->CESR; + + if((errorFlag & MDMA_CESR_TED) == 0U) + { + /* Update error code : Read Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_READ_XFER; + } + else + { + /* Update error code : Write Transfer error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_WRITE_XFER; + } + + if((errorFlag & MDMA_CESR_TEMD) != 0U) + { + /* Update error code : Error Mask Data */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_MASK_DATA; + } + + if((errorFlag & MDMA_CESR_TELD) != 0U) + { + /* Update error code : Error Linked list */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_LINKED_LIST; + } + + if((errorFlag & MDMA_CESR_ASE) != 0U) + { + /* Update error code : Address/Size alignment error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_ALIGNMENT; + } + + if((errorFlag & MDMA_CESR_BSE) != 0U) + { + /* Update error code : Block Size error error */ + hmdma->ErrorCode |= HAL_MDMA_ERROR_BLOCK_SIZE; + } + + /* Clear the transfer error flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE); + } + } + + /* Buffer Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BFTC) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BFTC) != 0U) + { + /* Clear the buffer transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BFTC); + + if(hmdma->XferBufferCpltCallback != NULL) + { + /* Buffer transfer callback */ + hmdma->XferBufferCpltCallback(hmdma); + } + } + } + + /* Block Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BT) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BT) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BT); + + if(hmdma->XferBlockCpltCallback != NULL) + { + /* Block transfer callback */ + hmdma->XferBlockCpltCallback(hmdma); + } + } + } + + /* Repeated Block Transfer Complete Interrupt management ******************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_BRT) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_BRT) != 0U) + { + /* Clear the repeat block transfer complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_BRT); + + if(hmdma->XferRepeatBlockCpltCallback != NULL) + { + /* Repeated Block transfer callback */ + hmdma->XferRepeatBlockCpltCallback(hmdma); + } + } + } + + /* Channel Transfer Complete Interrupt management ***********************************/ + if((__HAL_MDMA_GET_FLAG(hmdma, MDMA_FLAG_CTC) != 0U)) + { + if(__HAL_MDMA_GET_IT_SOURCE(hmdma, MDMA_IT_CTC) != 0U) + { + /* Disable all the transfer interrupts */ + __HAL_MDMA_DISABLE_IT(hmdma, (MDMA_IT_TE | MDMA_IT_CTC | MDMA_IT_BT | MDMA_IT_BRT | MDMA_IT_BFTC)); + + if(HAL_MDMA_STATE_ABORT == hmdma->State) + { + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change the DMA state */ + hmdma->State = HAL_MDMA_STATE_READY; + + if(hmdma->XferAbortCallback != NULL) + { + hmdma->XferAbortCallback(hmdma); + } + return; + } + + /* Clear the Channel Transfer Complete flag */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_CTC); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + /* Change MDMA peripheral state */ + hmdma->State = HAL_MDMA_STATE_READY; + + if(hmdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hmdma->XferCpltCallback(hmdma); + } + } + } + + /* manage error case */ + if(hmdma->ErrorCode != HAL_MDMA_ERROR_NONE) + { + hmdma->State = HAL_MDMA_STATE_ABORT; + + /* Disable the channel */ + __HAL_MDMA_DISABLE(hmdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U); + + /* Process Unlocked */ + __HAL_UNLOCK(hmdma); + + if((hmdma->Instance->CCR & MDMA_CCR_EN) != 0U) + { + /* Change the MDMA state to error if MDMA disable fails */ + hmdma->State = HAL_MDMA_STATE_ERROR; + } + else + { + /* Change the MDMA state to Ready if MDMA disable success */ + hmdma->State = HAL_MDMA_STATE_READY; + } + + + if (hmdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hmdma->XferErrorCallback(hmdma); + } + } +} + +/** + * @} + */ + +/** @addtogroup MDMA_Exported_Functions_Group4 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the MDMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the MDMA state. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval HAL state + */ +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma) +{ + return hmdma->State; +} + +/** + * @brief Return the MDMA error code + * @param hmdma : pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval MDMA Error Code + */ +uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) +{ + return hmdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup MDMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the MDMA Transfer parameter. + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param BlockDataLength : The length of a block transfer in bytes + * @param BlockCount: The number of blocks to be transferred + * @retval HAL status + */ +static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) +{ + uint32_t addressMask; + + /* Configure the MDMA Channel data length */ + MODIFY_REG(hmdma->Instance->CBNDTR ,MDMA_CBNDTR_BNDT, (BlockDataLength & MDMA_CBNDTR_BNDT)); + + /* Configure the MDMA block repeat count */ + MODIFY_REG(hmdma->Instance->CBNDTR , MDMA_CBNDTR_BRC , ((BlockCount - 1U) << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC); + + /* Clear all interrupt flags */ + __HAL_MDMA_CLEAR_FLAG(hmdma, MDMA_FLAG_TE | MDMA_FLAG_CTC | MDMA_CISR_BRTIF | MDMA_CISR_BTIF | MDMA_CISR_TCIF); + + /* Configure MDMA Channel destination address */ + hmdma->Instance->CDAR = DstAddress; + + /* Configure MDMA Channel Source address */ + hmdma->Instance->CSAR = SrcAddress; + + addressMask = SrcAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHBSbus is used as source (read operation) on channel x */ + hmdma->Instance->CTBR |= MDMA_CTBR_SBUS; + } + else + { + /*The AXI bus is used as source (read operation) on channel x */ + hmdma->Instance->CTBR &= (~MDMA_CTBR_SBUS); + } + + addressMask = DstAddress & 0xFF000000U; + if((addressMask == 0x20000000U) || (addressMask == 0x00000000U)) + { + /*The AHB bus is used as destination (write operation) on channel x */ + hmdma->Instance->CTBR |= MDMA_CTBR_DBUS; + } + else + { + /*The AXI bus is used as destination (write operation) on channel x */ + hmdma->Instance->CTBR &= (~MDMA_CTBR_DBUS); + } + + /* Set the linked list register to the first node of the list */ + hmdma->Instance->CLAR = (uint32_t)hmdma->FirstLinkedListNodeAddress; +} + +/** + * @brief Initializes the MDMA handle according to the specified + * parameters in the MDMA_InitTypeDef + * @param hmdma: pointer to a MDMA_HandleTypeDef structure that contains + * the configuration information for the specified MDMA Channel. + * @retval None + */ +static void MDMA_Init(MDMA_HandleTypeDef *hmdma) +{ + uint32_t blockoffset; + + /* Prepare the MDMA Channel configuration */ + hmdma->Instance->CCR = hmdma->Init.Priority | hmdma->Init.Endianness; + + /* Write new CTCR Register value */ + hmdma->Instance->CTCR = hmdma->Init.SourceInc | hmdma->Init.DestinationInc | \ + hmdma->Init.SourceDataSize | hmdma->Init.DestDataSize | \ + hmdma->Init.DataAlignment | hmdma->Init.SourceBurst | \ + hmdma->Init.DestBurst | \ + ((hmdma->Init.BufferTransferLength - 1U) << MDMA_CTCR_TLEN_Pos) | \ + hmdma->Init.TransferTriggerMode; + + /* If SW request set the CTCR register to SW Request Mode */ + if(hmdma->Init.Request == MDMA_REQUEST_SW) + { + /* + -If the request is done by SW : BWM could be set to 1 or 0. + -If the request is done by a peripheral : + If mask address not set (0) => BWM must be set to 0 + If mask address set (different than 0) => BWM could be set to 1 or 0 + */ + hmdma->Instance->CTCR |= (MDMA_CTCR_SWRM | MDMA_CTCR_BWM); + } + + /* Reset CBNDTR Register */ + hmdma->Instance->CBNDTR = 0; + + /* if block source address offset is negative set the Block Repeat Source address Update Mode to decrement */ + if(hmdma->Init.SourceBlockAddressOffset < 0) + { + hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRSUM; + /* Write new CBRUR Register value : source repeat block offset */ + blockoffset = (uint32_t)(- hmdma->Init.SourceBlockAddressOffset); + hmdma->Instance->CBRUR = (blockoffset & 0x0000FFFFU); + } + else + { + /* Write new CBRUR Register value : source repeat block offset */ + hmdma->Instance->CBRUR = (((uint32_t)hmdma->Init.SourceBlockAddressOffset) & 0x0000FFFFU); + } + + /* If block destination address offset is negative set the Block Repeat destination address Update Mode to decrement */ + if(hmdma->Init.DestBlockAddressOffset < 0) + { + hmdma->Instance->CBNDTR |= MDMA_CBNDTR_BRDUM; + /* Write new CBRUR Register value : destination repeat block offset */ + blockoffset = (uint32_t)(- hmdma->Init.DestBlockAddressOffset); + hmdma->Instance->CBRUR |= ((blockoffset & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + else + { + /*write new CBRUR Register value : destination repeat block offset */ + hmdma->Instance->CBRUR |= ((((uint32_t)hmdma->Init.DestBlockAddressOffset) & 0x0000FFFFU) << MDMA_CBRUR_DUV_Pos); + } + + /* if HW request set the HW request and the requet CleraMask and ClearData MaskData, */ + if(hmdma->Init.Request != MDMA_REQUEST_SW) + { + /* Set the HW request in CTRB register */ + hmdma->Instance->CTBR = hmdma->Init.Request & MDMA_CTBR_TSEL; + } + else /* SW request : reset the CTBR register */ + { + hmdma->Instance->CTBR = 0; + } + + /* Write Link Address Register */ + hmdma->Instance->CLAR = 0; +} + +/** + * @} + */ + +#endif /* HAL_MDMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c new file mode 100644 index 0000000..a50cac2 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c @@ -0,0 +1,2346 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + + if (hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; + } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; + + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } + + (void)USB_DevDisconnect(hpcd->Instance); + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_PCD_MspDeInit(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callback is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD BCD Callback + * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD BCD Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD BCD Callback + * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD LPM Callback + * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD LPM Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD LPM Callback + * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + + __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + __HAL_PCD_DISABLE(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + RegVal = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; + + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + + if (hpcd->Init.dma_enable == 1U) + { + hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; + + /* this is ZLP, so prepare EP0 for next setup */ + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) + { + /* prepare to rx more setup packets */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + { + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } + + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { + hpcd->LPM_State = LPM_L1; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + else + { + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, + (uint8_t *)hpcd->Setup); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + /* Handle SOF Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + + /* Handle Incomplete ISO IN Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; + + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; + + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else + HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + } + + /* Handle Disconnection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + { + RegVal = hpcd->Instance->GOTGINT; + + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else + HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + hpcd->Instance->GOTGINT |= RegVal; + } + } +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Enable USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + __HAL_LOCK(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + + if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) && + (hpcd->Init.battery_charging_enable == 1U)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __HAL_LOCK(hpcd); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + + (void)USB_EPSetStall(hpcd->Instance, ep); + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_ActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) +{ + return hpcd->State; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_EPTypeDef *ep; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if (hpcd->Init.dma_enable == 1U) + { + if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + } + else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + ep = &hpcd->OUT_ep[epnum]; + + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + + if (epnum == 0U) + { + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + /* ... */ + } + } + else + { + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) + { + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c new file mode 100644 index 0000000..1d4bfe9 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c @@ -0,0 +1,341 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pcd_ex.c + * @author MCD Application Team + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration + +@endverbatim + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + + +/** + * @brief Handle BatteryCharging Process. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t tickstart = HAL_GetTick(); + + /* Enable DCD : Data Contact Detect */ + USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; + + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); + + /* Check Detect flag */ + if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + /* Primary detection: checks if connected to Standard Downstream Port + (without charging capability) */ + USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + HAL_Delay(50U); + + if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) + { + /* Case of Standard Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* start secondary detection to check connection to Charging Downstream + Port or Dedicated Charging Port */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + HAL_Delay(50U); + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + HAL_Delay(50U); + + if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) + { + /* case Dedicated Charging Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { + /* case Charging Downstream Port */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Battery Charging capability discovery finished */ + (void)HAL_PCDEx_DeActivateBCD(hpcd); + + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Activate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + + /* Power Down USB transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Enable Battery charging */ + USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; + + hpcd->battery_charging_active = 1U; + + return HAL_OK; +} + +/** + * @brief Deactivate BatteryCharging feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); + + /* Disable Battery charging */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + + hpcd->battery_charging_active = 0U; + + return HAL_OK; +} + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief Send LPM message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ +} + +/** + * @brief Send BatteryCharging message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c new file mode 100644 index 0000000..aeb9933 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c @@ -0,0 +1,873 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions. + * + Peripheral Control functions. + * + Interrupt Handling functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + In the H7 family, the number of power domains is different between + device lines. This difference is due to characteristics of each device. + + (#) Domain architecture overview for the different H7 lines: + (+) Dual core lines are STM32H745, STM32H747, STM32H755 and STM32H757. + These devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals and a CPU + (Cortex-M4). The D3 domain contains the system control, I/O logic + and low-power peripherals. + (+) STM32H72x, STM32H73x, STM32H742, STM32H743, STM32H750 and STM32H753 + devices have 3 power domains (D1, D2 and D3). + The domain D1 contains a CPU (Cortex-M7), a Flash memory and some + peripherals. The D2 domain contains peripherals. The D3 domains + contains the system control, I/O logic and low-power peripherals. + (+) STM32H7Axxx and STM32H7Bxxx devices have 2 power domains (CD and SRD). + The core domain (CD) contains a CPU (Cortex-M7), a Flash + memory and peripherals. The SmartRun domain contains the system + control, I/O logic and low-power peripherals. + + (#) Every entity have low power mode as described below : + (#) The CPU low power modes are : + (+) CPU CRUN. + (+) CPU CSLEEP. + (+) CPU CSTOP. + (#) The domain low power modes are : + (+) DRUN. + (+) DSTOP. + (+) DSTANDBY. + (#) The SYSTEM low power modes are : + (+) RUN* : The Run* mode is entered after a POR reset and a wakeup from + Standby. In Run* mode, the performance is limited and the + system supply configuration shall be programmed. The system + enters Run mode only when the ACTVOSRDY bit in PWR control + status register 1 (PWR_CSR1) is set to 1. + (+) RUN. + (+) STOP. + (+) STANDBY. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Power management peripheral is active by default at startup level in + STM32h7xx lines. + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RTC registers, RTC backup + data registers and backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Power Voltage Detector, + then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() functions to start + and stop the PVD detection. + (+) PVD level could be one of the following values : + (++) 1V95 + (++) 2V1 + (++) 2V25 + (++) 2V4 + (++) 2V55 + (++) 2V7 + (++) 2V85 + (++) External voltage level + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High) and to enable and disable it. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the current Core in SLEEP + mode. Wake-up from SLEEP mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in SLEEP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0 + mode for single core devices. For dual core devices, this API will enter + the domain (containing Cortex-Mx that executing this function) in DSTOP + mode. According to the used parameter, user could select the regulator to + be kept actif in low power mode and wake-up event type. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in CSTOP mode with __WFE() entry. + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + STANDBY mode for single core devices. For dual core devices, this API + will enter the domain (containing Cortex-Mx that executing this function) + in DSTANDBY mode. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-Mx re-entring in SLEEP mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-Mx to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + (#) Call HAL_PWR_PVD_IRQHandler() function to handle the PWR PVD interrupt + request. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_VOLTAGESCALING_CONFIG() : Configure the main internal + regulator output voltage. + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#if !defined (DUAL_CORE) +#define PVD_MODE_IT (0x00010000U) +#define PVD_MODE_EVT (0x00020000U) +#endif /* !defined (DUAL_CORE) */ + +#define PVD_RISING_EDGE (0x00000001U) +#define PVD_FALLING_EDGE (0x00000002U) +#define PVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] + This section provides functions allowing to deinitialize power peripheral. + + [..] + After system reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted write + accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit (void) +{ +} + +/** + * @brief Enable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess (void) +{ + /* Enable access to RTC and backup registers */ + SET_BIT (PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None. + */ +void HAL_PWR_DisableBkUpAccess (void) +{ + /* Disable access to RTC and backup registers */ + CLEAR_BIT (PWR->CR1, PWR_CR1_DBP); +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Power Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control Functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power peripheral. + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[7:0] bits in the PWR_CR1 + register). + + (+) A PVDO flag is available to indicate if VDD is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + + (+) The PVD is stopped in STANDBY mode. + + *** Wake-up pin configuration *** + ================================= + [..] + (+) Wake-up pin is used to wake up the system from STANDBY mode. + The pin pull is configurable through the WKUPEPR register to be in + No-pull, Pull-up and Pull-down. + The pin polarity is configurable through the WKUPEPR register to be + active on rising or falling edges. + + (+) There are up to six Wake-up pin in the STM32H7 devices family. + + *** Low Power modes configuration *** + ===================================== + [..] + The device present 3 principles low-power modes features: + (+) SLEEP mode : Cortex-Mx is stopped and all PWR domains are remaining + active (Powered and Clocked). + + (+) STOP mode : Cortex-Mx is stopped, clocks are stopped and the + regulator is running. The Main regulator or the LP + regulator could be selected. + + (+) STANDBY mode : All PWR domains enter DSTANDBY mode and the VCORE + supply regulator is powered off. + + *** SLEEP mode *** + ================== + [..] + (+) Entry: + The SLEEP mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, + SLEEPEntry) function. + + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction. + + -@@- The Regulator parameter is not used for the STM32H7 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from SLEEP mode. + + *** STOP mode *** + ================= + [..] + In system STOP mode, all clocks in the 1.2V domain are stopped, the PLL, + the HSI, and the HSE RC oscillators are disabled. Internal SRAM and + register contents are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption in STOP mode, FLASH can be powered off before + entering the STOP mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the STOP mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The STOP mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, + STOPEntry) function with: + + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON: Main regulator ON. + (+++) PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. + + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction. + + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** STANDBY mode *** + ==================== + [..] + (+) + The system STANDBY mode allows to achieve the lowest power consumption. + It is based on the Cortex-Mx deep SLEEP mode, with the voltage regulator + disabled. The system is consequently powered off. The PLL, the HSI + oscillator and the HSE oscillator are also switched off. SRAM and register + contents are lost except for the RTC registers, RTC backup registers, + backup SRAM and standby circuitry. + + [..] + The voltage regulator is OFF. + + (++) Entry: + (+++) The STANDBY mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), + RTC wakeup, tamper event, time stamp event, external reset in NRST + pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an + RTC Wakeup event, a tamper event or a time-stamp event, without + depending on an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the STOP and STANDBY modes + + (++) To wake up from the STOP mode with an RTC alarm event, it is + necessary to configure the RTC to generate the RTC alarm using the + HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the STOP mode with an RTC Tamper or time stamp event, + it is necessary to configure the RTC to detect the tamper or time + stamp event using the HAL_RTCEx_SetTimeStamp_IT() or + HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the STOP mode with an RTC WakeUp event, it is + necessary to configure the RTC to generate the RTC WakeUp event + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Programmable Voltage Detector(PVD). + * @param sConfigPVD : Pointer to an PWR_PVDTypeDef structure that contains + * the configuration information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. + * @retval None. + */ +void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the PVD configuration parameter */ + if (sConfigPVD == NULL) + { + return; + } + + /* Check the parameters */ + assert_param (IS_PWR_PVD_LEVEL (sConfigPVD->PVDLevel)); + assert_param (IS_PWR_PVD_MODE (sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG (PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + + /* Clear previous config */ +#if !defined (DUAL_CORE) + __HAL_PWR_PVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_PVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE (); + +#if !defined (DUAL_CORE) + /* Interrupt mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT (); + } + + /* Event mode configuration */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT (); + } +#endif /* !defined (DUAL_CORE) */ + + /* Rising edge configuration */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE (); + } + + /* Falling edge configuration */ + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE (); + } +} + +/** + * @brief Enable the Programmable Voltage Detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD (void) +{ + /* Enable the power voltage detector */ + SET_BIT (PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Disable the Programmable Voltage Detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD (void) +{ + /* Disable the power voltage detector */ + CLEAR_BIT (PWR->CR1, PWR_CR1_PVDEN); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity : Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which + * sets the default (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6. + * or one of the following values where the user can explicitly states + * the enabled pin and the chosen polarity: + * @arg PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinPolarity)); + + /* + Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge). + */ + MODIFY_REG (PWR->WKUPEPR, PWR_EWUP_MASK, WakeUpPinPolarity); +} + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx : Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6, + * PWR_WAKEUP_PIN1_HIGH, PWR_WAKEUP_PIN1_LOW, + * PWR_WAKEUP_PIN2_HIGH, PWR_WAKEUP_PIN2_LOW, + * PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, + * PWR_WAKEUP_PIN4_HIGH, PWR_WAKEUP_PIN4_LOW, + * PWR_WAKEUP_PIN5_HIGH, PWR_WAKEUP_PIN5_LOW, + * PWR_WAKEUP_PIN6_HIGH, PWR_WAKEUP_PIN6_LOW. + * @note The PWR_WAKEUP_PIN3_HIGH, PWR_WAKEUP_PIN3_LOW, PWR_WAKEUP_PIN5_HIGH + * and PWR_WAKEUP_PIN5_LOW are available only for devices that includes + * GPIOI port. + * @retval None. + */ +void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPinx)); + + /* Disable the wake up pin selected */ + CLEAR_BIT (PWR->WKUPEPR, (PWR_WKUPEPR_WKUPEN & WakeUpPinx)); +} + +/** + * @brief Enter the current core in SLEEP mode (CSLEEP). + * @param Regulator : Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : SLEEP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : SLEEP mode with low power + * regulator ON. + * @note This parameter is not used for the STM32H7 family and is kept as + * parameter just to maintain compatibility with the lower power + * families. + * @param SLEEPEntry : Specifies if SLEEP mode is entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI : enter SLEEP mode with WFI instruction. + * @arg PWR_SLEEPENTRY_WFE : enter SLEEP mode with WFE instruction. + * @note Ensure to clear pending events before calling this API through + * HAL_PWREx_ClearPendingEvent() when the SLEEP entry is WFE. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select SLEEP mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } +} + +/** + * @brief Enter STOP mode. + * @note For single core devices, this API will enter the system in STOP mode + * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is + * cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTOP mode. If all + * Cortex-Mx domains are in DSTOP and RUN_D3 bit in CPUCR register is + * cleared, all the system will enter in STOP mode. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @note In System STOP mode, all I/O pins keep the same state as in Run mode. + * @note When exiting System STOP mode by issuing an interrupt or a wakeup + * event, the HSI RC oscillator is selected as default system wakeup + * clock. + * @note In System STOP mode, when the voltage regulator operates in low + * power mode, an additional startup delay is incurred when the system + * is waking up. By keeping the internal regulator ON during STOP mode, + * the consumption is higher although the startup time is reduced. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + + /* Select the regulator state in STOP mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when Cortex-M7 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + } + else + { + /* Keep DSTOP mode when Cortex-M4 enters DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + } +#else /* Single core devices */ + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Keep DSTOP mode when Cortex-M7 enter in DEEP-SLEEP */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select STOP mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enter STANDBY mode. + * @note For single core devices, this API will enter the system in STANDBY + * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR + * register is cleared. + * For dual core devices, this API will enter the domain (containing + * Cortex-Mx that executing this function) in DSTANDBY mode. If all + * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register + * is cleared, all the system will enter in STANDBY mode. + * @note The system enters Standby mode only when all domains are in DSTANDBY. + * @note When the System exit STANDBY mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock. + * @note It is recommended to disable all regulators before entring STANDBY + * mode for power consumption saving purpose. + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode (void) +{ + /* Configure the PWR mode for the different Domains */ +#if defined (DUAL_CORE) + /* Check CPU ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D1 | PWR_CPU2CR_PDDS_D3)); + } + else + { + /* Enter DSTANDBY mode when Cortex-M4 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D2 | PWR_CPUCR_PDDS_D3)); + SET_BIT (PWR->CPU2CR, (PWR_CPU2CR_PDDS_D2 | PWR_CPU2CR_PDDS_D3)); + } +#else /* Single core devices */ + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, (PWR_CPUCR_PDDS_D1 | PWR_CPUCR_PDDS_D3)); + +#if defined (PWR_CPUCR_PDDS_D2) + /* Enter DSTANDBY mode when Cortex-M7 enters DEEP-SLEEP */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* PWR_CPUCR_PDDS_D2 */ +#endif /* defined (DUAL_CORE) */ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores(); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); +} + +/** + * @brief Indicate Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit (void) +{ + /* Set SLEEPONEXIT bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable Sleep-On-Exit feature when returning from Handler mode to + * Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit (void) +{ + /* Clear SLEEPONEXIT bit of Cortex-Mx System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEVONPEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-Mx. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend (void) +{ + /* Set SEVONPEND bit of Cortex-Mx System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-Mx. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend (void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group3 Interrupt Handling Functions + * @brief Interrupt Handling functions + * +@verbatim + =============================================================================== + ##### Interrupt Handling Functions ##### + =============================================================================== + [..] + This section provides functions allowing to handle the PVD pending + interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None. + */ +void HAL_PWR_PVD_IRQHandler (void) +{ +#if defined (DUAL_CORE) + /* Check Cortex-Mx ID */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Check PWR EXTI D1 flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* Clear PWR EXTI D1 pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } + } + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) + { + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_PVD_EXTID2_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } + } +#else /* Single core devices */ + /* PVD EXTI line interrupt detected */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* Clear PWR EXTI pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + } +#endif /* defined (DUAL_CORE) */ +} + +/** + * @brief PWR PVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_PVDCallback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback can be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c new file mode 100644 index 0000000..5d51ceb --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c @@ -0,0 +1,2142 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply + with the following different setups according to hardware (support SMPS): + (+) PWR_DIRECT_SMPS_SUPPLY + (+) PWR_SMPS_1V8_SUPPLIES_LDO + (+) PWR_SMPS_2V5_SUPPLIES_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO + (+) PWR_SMPS_1V8_SUPPLIES_EXT + (+) PWR_SMPS_2V5_SUPPLIES_EXT + (+) PWR_LDO_SUPPLY + (+) PWR_EXTERNAL_SOURCE_SUPPLY + + (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup. + + (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main + internal regulator output voltage. The voltage scaling could be one of + the following scales : + (+) PWR_REGULATOR_VOLTAGE_SCALE0 + (+) PWR_REGULATOR_VOLTAGE_SCALE1 + (+) PWR_REGULATOR_VOLTAGE_SCALE2 + (+) PWR_REGULATOR_VOLTAGE_SCALE3 + + (#) Call HAL_PWREx_GetVoltageRange() function to get the current output + voltage applied to the main regulator. + + (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the + main internal regulator output voltage in STOP mode. The voltage scaling + in STOP mode could be one of the following scales : + (+) PWR_REGULATOR_SVOS_SCALE3 + (+) PWR_REGULATOR_SVOS_SCALE4 + (+) PWR_REGULATOR_SVOS_SCALE5 + + (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current + output voltage applied to the main regulator in STOP mode. + + (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode + with core domain in D2STOP mode. This API is used only for STM32H7Axxx + and STM32H7Bxxx devices. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in + DSTOP mode. Call this API with all available power domains to enter the + system in STOP mode. + Please ensure to clear all CPU pending events by calling + HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx + in DEEP-SLEEP mode with __WFE() entry. + + (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the + Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry. + + (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain + in DSTANDBY mode. Call this API with all available power domains to enter + the system in STANDBY mode. + + (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state + (RUN/STOP) when the system enter to low power mode. + + (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the + selected power domain. This API is used only for dual core devices. + + (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold + and release the selected CPU and and their domain peripherals when + exiting STOP mode. These APIs are used only for dual core devices. + + (#) Call HAL_PWREx_EnableFlashPowerDown() and + HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the + Flash Power Down in STOP mode. + + (#) Call HAL_PWREx_EnableMemoryShutOff() and + HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the + memory block shut-off in DStop or DStop2. These APIs are used only for + STM32H7Axxx and STM32H7Bxxx lines. + + (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin() + functions to enable and disable the Wake-up pin functionality for + the selected pin. + + (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag() + functions to manage wake-up flag for the selected pin. + + (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up + pins interrupts. + + (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions + to enable and disable the backup domain regulator. + + (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(), + HAL_PWREx_EnableUSBVoltageDetector() and + HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power + regulation functionalities. + + (#) Call HAL_PWREx_EnableBatteryCharging() and + HAL_PWREx_DisableBatteryCharging() functions to enable and disable the + battery charging feature with the selected resistor. + + (#) Call HAL_PWREx_EnableAnalogBooster() and + HAL_PWREx_DisableAnalogBooster() functions to enable and disable the + AVD boost feature when the VDD supply voltage is below 2V7. + + (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() + functions to enable and disable the VBAT and Temperature monitoring. + When VBAT and Temperature monitoring feature is enables, use + HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get + respectively the Temperature level and VBAT level. + + (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring() + function to get VDDMMC voltage level. This API is used only for + STM32H7Axxx and STM32H7Bxxx lines + + (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured + (event mode and voltage threshold) in order to set up the Analog Voltage + Detector then use HAL_PWREx_EnableAVD() and HAL_PWREx_DisableAVD() + functions to start and stop the AVD detection. + (+) AVD level could be one of the following values : + (++) 1V7 + (++) 2V1 + (++) 2V5 + (++) 2V8 + + (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and + AVD interrupt request. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Constants + * @{ + */ + +/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask + * @{ + */ +#define AVD_MODE_IT (0x00010000U) +#define AVD_MODE_EVT (0x00020000U) +#define AVD_RISING_EDGE (0x00000001U) +#define AVD_FALLING_EDGE (0x00000002U) +#define AVD_RISING_FALLING_EDGE (0x00000003U) +/** + * @} + */ + +/** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value + * @{ + */ +#define PWR_FLAG_SETTING_DELAY (1000U) +/** + * @} + */ + +/** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets + * @{ + */ +/* Wake-Up Pins EXTI register mask */ +#if defined (EXTI_IMR2_IM57) +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\ + EXTI_IMR2_IM59 | EXTI_IMR2_IM60) +#else +#define PWR_EXTI_WAKEUP_PINS_MASK (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\ + EXTI_IMR2_IM58 | EXTI_IMR2_IM60) +#endif /* defined (EXTI_IMR2_IM57) */ + +/* Wake-Up Pins PWR Pin Pull shift offsets */ +#define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U) +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] + (#) When the system is powered on, the POR monitors VDD supply. Once VDD is + above the POR threshold level, the voltage regulator is enabled in the + default supply configuration: + (+) The Voltage converter output level is set at 1V0 in accordance with + the VOS3 level configured in PWR (D3/SRD) domain control register + (PWR_D3CR/PWR_SRDCR). + (+) The system is kept in reset mode as long as VCORE is not ok. + (+) Once VCORE is ok, the system is taken out of reset and the HSI + oscillator is enabled. + (+) Once the oscillator is stable, the system is initialized: Flash memory + and option bytes are loaded and the CPU starts in Run* mode. + (+) The software shall then initialize the system including supply + configuration programming using the HAL_PWREx_ConfigSupply(). + (+) Once the supply configuration has been configured, the + HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR + control status register 1 (PWR_CSR1) to guarantee a valid voltage + levels: + (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the + system is in limited Run* mode, write accesses to the RAMs are not + permitted and VOS shall not be changed. + (++) Once ACTVOSRDY indicates that voltage levels are valid, the system + is in normal Run mode, write accesses to RAMs are allowed and VOS + can be changed. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source to set after a + * system startup. + * This parameter can be one of the following values : + * @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power + * Domains. The LDO is Bypassed. + * @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies + * the LDO. The Vcore Power Domains + * are supplied from the LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output + * supplies external + * circuits and the LDO. + * The Vcore Power Domains + * are supplied from the + * LDO. + * @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies + * external circuits. The LDO is + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power + * Domains. The SMPS regulator is Bypassed. + * @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are + * Bypassed. The Vcore Power + * Domains are supplied from + * external source. + * @note The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all + * H7 lines. + * The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO, + * PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO, + * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and + * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS + * regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param (IS_PWR_SUPPLY (SupplySource)); + + /* Check if supply source was configured */ +#if defined (PWR_FLAG_SCUEN) + if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U) +#else + if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) +#endif /* defined (PWR_FLAG_SCUEN) */ + { + /* Check supply configuration */ + if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource) + { + /* Supply configuration update locked, can't apply a new supply config */ + return HAL_ERROR; + } + else + { + /* Supply configuration update locked, but new supply configuration + matches with old supply configuration : nothing to do + */ + return HAL_OK; + } + } + + /* Set the power supply configuration */ + MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + +#if defined (SMPS) + /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */ + if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || + (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) || + (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT)) + { + /* Get the current tick number */ + tickstart = HAL_GetTick (); + + /* Wait till SMPS external supply ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } +#endif /* defined (SMPS) */ + + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configuration. + */ +uint32_t HAL_PWREx_GetSupplyConfig (void) +{ + return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK); +} + +/** + * @brief Configure the main internal regulator output voltage. + * @param VoltageScaling : Specifies the regulator output voltage to achieve + * a tradeoff between performance and power + * consumption. + * This parameter can be one of the following values : + * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output + * Scale 0 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output + * range 1 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output + * range 2 mode. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output + * range 3 mode. + * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is + * only possible when Vcore is supplied from LDO (Low DropOut). The + * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() + * macro before configuring Voltage Scale 0. + * To enter low power mode , and if current regulator voltage is + * Voltage Scale 0 then first switch to Voltage Scale 1 before entering + * low power mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling)); + + /* Get the voltage scaling */ + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling) + { + /* Old and new voltage scaling configuration match : nothing to do */ + return HAL_OK; + } + +#if defined (PWR_SRDCR_VOS) + /* Set the voltage range */ + MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); +#else +#if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ + if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0) + { + if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN) + { + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + /* Enable the PWR overdrive */ + SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + } + else + { + /* The voltage scale 0 is only possible when LDO regulator is enabled */ + return HAL_ERROR; + } + } + else + { + if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1) + { + if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U) + { + /* Disable the PWR overdrive */ + CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + } + } + + /* Set the voltage range */ + MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); + } +#else /* STM32H72xxx and STM32H73xxx lines */ + /* Set the voltage range */ + MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); +#endif /* defined (SYSCFG_PWRCR_ODEN) */ +#endif /* defined (PWR_SRDCR_VOS) */ + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till voltage level flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage. Reflecting the last + * VOS value applied to the PMU. + * @retval The current applied VOS selection. + */ +uint32_t HAL_PWREx_GetVoltageRange (void) +{ + /* Get the active voltage scaling */ + return (PWR->CSR1 & PWR_CSR1_ACTVOS); +} + +/** + * @brief Configure the main internal regulator output voltage in STOP mode. + * @param VoltageScaling : Specifies the regulator output voltage when the + * system enters Stop mode to achieve a tradeoff between performance + * and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range + * 3 mode. + * @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range + * 4 mode. + * @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range + * 5 mode. + * @note The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage + * regulator in Low-power (LP) mode to further reduce power consumption. + * When preselecting SVOS3, the use of the voltage regulator low-power + * mode (LP) can be selected by LPDS register bit. + * @note The selected SVOS4 and SVOS5 levels add an additional startup delay + * when exiting from system Stop mode. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling)); + + /* Return the stop mode voltage range */ + MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling); + + return HAL_OK; +} + +/** + * @brief Get the main internal regulator output voltage in STOP mode. + * @retval The actual applied VOS selection. + */ +uint32_t HAL_PWREx_GetStopModeVoltageRange (void) +{ + /* Return the stop voltage scaling */ + return (PWR->CR1 & PWR_CR1_SVOS); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @brief Low power control functions + * +@verbatim + =============================================================================== + ##### Low power control functions ##### + =============================================================================== + + *** Domains Low Power modes configuration *** + ============================================= + [..] + This section provides the extended low power mode control APIs. + The system presents 3 principles domains (D1, D2 and D3) that can be + operated in low-power modes (DSTOP or DSTANDBY mode): + + (+) DSTOP mode to enters a domain to STOP mode: + (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU + subsystem is in CSTOP mode and has allocated peripheral in the + domain. + In DSTOP mode the domain bus matrix clock is stopped. + (++) The system enters STOP mode using one of the following scenarios: + (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains + enter DSTOP mode. + (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains + enter DSTOP mode. + (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains + enter DSTOP mode. + (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain + enters DSTOP mode. + (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain + enters DSTOP mode. + (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain + enters DSTOP mode. + (+++) D1, D2 and D3 domains enter DSTOP mode. + (++) When the system enters STOP mode, the clocks are stopped and the + regulator is running in main or low power mode. + (++) D3 domain can be kept in Run mode regardless of the CPU status when + enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function. + + (+) DSTANDBY mode to enters a domain to STANDBY mode: + (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control + register (PWR_CPUCR) for the Dn domain selects Standby mode. + (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter + DSTANDBY mode. Consequently the VCORE supply regulator is powered + off. + + *** DSTOP mode *** + ================== + [..] + In DStop mode the domain bus matrix clock is stopped. + The Flash memory can enter low-power Stop mode when it is enabled through + FLPS in PWR_CR1 register. This allows a trade-off between domain DStop + restart time and low power consumption. + [..] + In DStop mode domain peripherals using the LSI or LSE clock and + peripherals having a kernel clock request are still able to operate. + [..] + Before entering DSTOP mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. + + (+) Entry: + The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator, + STOPEntry, Domain) function with: + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON : Main regulator ON. + (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON. + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction + (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction + (++) Domain: + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode. + + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** DSTANDBY mode *** + ===================== + [..] + In DStandby mode: + (+) The domain bus matrix clock is stopped. + (+) The domain is powered down and the domain RAM and register contents + are lost. + [..] + Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache + function in order to clean the D-Cache and guarantee the data integrity + for the SRAM memories. + + (+) Entry: + The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode + (Domain) function with: + (++) Domain: + (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode. + (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode. + (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode. + + (+) Exit: + WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + wakeup, tamper event, time stamp event, external reset in NRST pin, + IWDG reset. + + *** Keep D3/SRD in RUN mode *** + =============================== + [..] + D3/SRD domain can be kept in Run mode regardless of the CPU status when + entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function + with : + (+) D3State: + (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system + mode. + (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless + of CPU subsystem mode. + + *** FLASH Power Down configuration **** + ======================================= + [..] + By setting the FLPS bit in the PWR_CR1 register using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters + power down mode when the device enters STOP mode. When the Flash memory is + in power down mode, an additional startup delay is incurred when waking up + from STOP mode. + + *** Wakeup Pins configuration **** + =================================== + [..] + Wakeup pins allow the system to exit from Standby mode. The configuration + of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams) + function with: + (+) sPinParams: structure to enable and configure a wakeup pin: + (++) WakeUpPin: Wakeup pin to be enabled. + (++) PinPolarity: Wakeup pin polarity (rising or falling edge). + (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down). + [..] + The wakeup pins are internally connected to the EXTI lines [55-60] to + generate an interrupt if enabled. The EXTI lines configuration is done by + the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c + file. + [..] + When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is + called and the appropriate flag is set in the PWR_WKUPFR register. Then in + the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be + cleared and the appropriate user callback will be called. The user can add + his own code by customization of function pointer HAL_PWREx_WKUPx_Callback. + +@endverbatim + * @{ + */ + +#if defined (PWR_CPUCR_RETDS_CD) +/** + * @brief Enter the system to STOP mode with main domain in DSTOP2. + * @note In STOP mode, the domain bus matrix clock is stalled. + * @note In STOP mode, memories and registers are maintained and peripherals + * in CPU domain are no longer operational. + * @note All clocks in the VCORE domain are stopped, the PLL, the HSI and the + * HSE oscillators are disabled. Only Peripherals that have wakeup + * capability can switch on the HSI to receive a frame, and switch off + * the HSI after receiving the frame if it is not a wakeup frame. In + * this case the HSI clock is propagated only to the peripheral + * requesting it. + * @note When exiting STOP mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock if STOPWUCK bit in + * RCC_CFGR register is set. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @retval None. + */ +void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + + /* Select the regulator state in Stop mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD); + + /* Keep DSTOP mode when SmartRun domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __ISB (); + __DSB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} +#endif /* defined (PWR_CPUCR_RETDS_CD) */ + +/** + * @brief Enter a Domain to DSTOP mode. + * @note This API gives flexibility to manage independently each domain STOP + * mode. For dual core lines, this API should be executed with the + * corresponding Cortex-Mx to enter domain to DSTOP mode. When it is + * executed by all available Cortex-Mx, the system enter to STOP mode. + * For single core lines, calling this API with domain parameter set to + * PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode + * independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the + * CPUCR_RUN_D3 is cleared. + * @note In DStop mode the domain bus matrix clock is stopped. + * @note The system D3/SRD domain enter Stop mode only when the CPU subsystem + * is in CStop mode, the EXTI wakeup sources are inactive and at least + * one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for + * any domain request Stop. + * @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache + * function in order to clean the D-Cache and guarantee the data + * integrity for the SRAM memories. + * @note In System Stop mode, the domain peripherals that use the LSI or LSE + * clock, and the peripherals that have a kernel clock request to + * select HSI or CSI as source, are still able to operate. + * @param Regulator : Specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON : STOP mode with regulator ON. + * @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power + * regulator ON. + * @param STOPEntry : Specifies if STOP mode in entered with WFI or WFE + * intrinsic instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. + * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction. + * @param Domain : Specifies the Domain to enter in DSTOP mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode. + * @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode. + * @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode. + * @retval None. + */ +void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain) +{ + /* Check the parameters */ + assert_param (IS_PWR_REGULATOR (Regulator)); + assert_param (IS_PWR_STOP_ENTRY (STOPEntry)); + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the regulator state in Stop mode */ + MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator); + + /* Select the domain Power Down DeepSleep */ + if (Domain == PWR_D1_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ + + /* Keep DSTOP mode when D1/CD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + } +#if defined (PWR_CPUCR_PDDS_D2) + else if (Domain == PWR_D2_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering stop + mode will not be performed + */ + return; + } + + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Ensure that all instructions are done before entering STOP mode */ + __DSB (); + __ISB (); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI (); + } + else + { + /* Request Wait For Event */ + __WFE (); + } + + /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */ + CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +#else + /* Keep DSTOP mode when D2 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2); +#endif /* defined (DUAL_CORE) */ + } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + else + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + } + else + { + /* Keep DSTOP mode when D3 domain enters Deepsleep */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); + } +#else + /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief Clear pending event. + * @note This API clears the pending event in order to enter a given CPU + * to CSLEEP or CSTOP. It should be called just before APIs performing + * enter low power mode using Wait For Event request. + * @note Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ClearPendingEvent (void) +{ +#if defined (DUAL_CORE) + /* Check the current Core */ + if (HAL_GetCurrentCPUID () == CM7_CPUID) + { + __WFE (); + } + else + { + __SEV (); + __WFE (); + } +#else + __WFE (); +#endif /* defined (DUAL_CORE) */ +} + +/** + * @brief Enter a Domain to DSTANDBY mode. + * @note This API gives flexibility to manage independently each domain + * STANDBY mode. For dual core lines, this API should be executed with + * the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When + * it is executed by all available Cortex-Mx, the system enter STANDBY + * mode. + * For single core lines, calling this API with D1/SRD the selected + * domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0 + * and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1. + * @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for + * the Dn domain select Standby mode. When the system enters Standby + * mode, the voltage regulator is disabled. + * @note When D2 or D3 domain is in DStandby mode and the CPU sets the + * domain PDDS_Dn bit to select Stop mode, the domain remains in + * DStandby mode. The domain will only exit DStandby when the CPU + * allocates a peripheral in the domain. + * @note The system D3/SRD domain enters Standby mode only when the D1 and D2 + * domain are in DStandby. + * @note Before entering DSTANDBY mode it is recommended to call + * SCB_CleanDCache function in order to clean the D-Cache and guarantee + * the data integrity for the SRAM memories. + * @param Domain : Specifies the Domain to enter to STANDBY mode. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode. + * @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode. + * @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode. + * @retval None + */ +void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain) +{ + /* Check the parameters */ + assert_param (IS_PWR_DOMAIN (Domain)); + + /* Select the domain Power Down DeepSleep */ + if (Domain == PWR_D1_DOMAIN) + { +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM7_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } +#endif /* defined (DUAL_CORE) */ + + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1); + +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1); +#endif /*DUAL_CORE*/ + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); + } +#if defined (PWR_CPUCR_PDDS_D2) + else if (Domain == PWR_D2_DOMAIN) + { + /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ + SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2); + +#if defined (DUAL_CORE) + /* Check current core */ + if (HAL_GetCurrentCPUID () != CM4_CPUID) + { + /* + When the domain selected and the cortex-mx don't match, entering + standby mode will not be performed + */ + return; + } + + /* Allow DSTANDBY mode when D2 domain enters Deepsleep */ + SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* This option is used to ensure that store operations are completed */ +#if defined (__CC_ARM) + __force_stores (); +#endif /* defined (__CC_ARM) */ + + /* Request Wait For Interrupt */ + __WFI (); +#endif /* defined (DUAL_CORE) */ + } +#endif /* defined (PWR_CPUCR_PDDS_D2) */ + else + { + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3); + +#if defined (DUAL_CORE) + /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3); +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief Configure the D3/SRD Domain state when the System in low power mode. + * @param D3State : Specifies the D3/SRD state. + * This parameter can be one of the following values : + * @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep + * CPU sub-system low power mode. + * @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode + * regardless of the CPU sub-system low + * power mode. + * @retval None + */ +void HAL_PWREx_ConfigD3Domain (uint32_t D3State) +{ + /* Check the parameter */ + assert_param (IS_D3_STATE (D3State)); + + /* Keep D3/SRD in run mode */ + MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State); +} + +#if defined (DUAL_CORE) +/** + * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a + * given domain. + * @param DomainFlags : Specifies the Domain flags to be cleared. + * This parameter can be one of the following values: + * @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags. + * @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags. + * @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags. + * @retval None. + */ +void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags) +{ + /* Check the parameter */ + assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags)); + + /* D1 CPU flags */ + if (DomainFlags == PWR_D1_DOMAIN_FLAGS) + { + /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + } + /* D2 CPU flags */ + else if (DomainFlags == PWR_D2_DOMAIN_FLAGS) + { + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); + } + else + { + /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF); + /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF); + } +} + +/** + * @brief Hold the CPU and their domain peripherals when exiting STOP mode. + * @param CPU : Specifies the core to be held. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master. + * @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param (IS_PWR_CORE (CPU)); + + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) + { + /* If CPU1 is not held */ + if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1) + { + /* Set HOLD2 bit */ + SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); + } + else + { + status = HAL_ERROR; + } + } + else + { + /* If CPU2 is not held */ + if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2) + { + /* Set HOLD1 bit */ + SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Release the CPU and their domain peripherals after a wake-up from + * STOP mode. + * @param CPU: Specifies the core to be released. + * This parameter can be one of the following values: + * @arg PWR_CORE_CPU1: Release the CPU1 and their domain + * peripherals from holding. + * @arg PWR_CORE_CPU2: Release the CPU2 and their domain + * peripherals from holding. + * @retval None + */ +void HAL_PWREx_ReleaseCore (uint32_t CPU) +{ + /* Check the parameters */ + assert_param (IS_PWR_CORE (CPU)); + + /* Check CPU index */ + if (CPU == PWR_CORE_CPU2) + { + /* Reset HOLD2 bit */ + CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2); + } + else + { + /* Reset HOLD1 bit */ + CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1); + } +} +#endif /* defined (DUAL_CORE) */ + + +/** + * @brief Enable the Flash Power Down in Stop mode. + * @note When Flash Power Down is enabled the Flash memory enters low-power + * mode when D1/SRD domain is in DStop mode. This feature allows to + * obtain the best trade-off between low-power consumption and restart + * time when exiting from DStop mode. + * @retval None. + */ +void HAL_PWREx_EnableFlashPowerDown (void) +{ + /* Enable the Flash Power Down */ + SET_BIT (PWR->CR1, PWR_CR1_FLPS); +} + +/** + * @brief Disable the Flash Power Down in Stop mode. + * @note When Flash Power Down is disabled the Flash memory is kept on + * normal mode when D1/SRD domain is in DStop mode. This feature allows + * to obtain the best trade-off between low-power consumption and + * restart time when exiting from DStop mode. + * @retval None. + */ +void HAL_PWREx_DisableFlashPowerDown (void) +{ + /* Disable the Flash Power Down */ + CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS); +} + +#if defined (PWR_CR1_SRDRAMSO) +/** + * @brief Enable memory block shut-off in DStop or DStop2 modes + * @note In DStop or DStop2 mode, the content of the memory blocks is + * maintained. Further power optimization can be obtained by switching + * off some memory blocks. This optimization implies loss of the memory + * content. The user can select which memory is discarded during STOP + * mode by means of xxSO bits. + * @param MemoryBlock : Specifies the memory block to shut-off during DStop or + * DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. + */ +void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Enable memory block shut-off */ + SET_BIT (PWR->CR1, MemoryBlock); +} + +/** + * @brief Disable memory block shut-off in DStop or DStop2 modes + * @param MemoryBlock : Specifies the memory block to keep content during + * DStop or DStop2 mode. + * This parameter can be one of the following values: + * @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory. + * @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and + * FDCAN memories. + * @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories. + * @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories. + * @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory. + * @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory. + * @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory. + * @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory. + * @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory. + * @retval None. + */ +void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock) +{ + /* Check the parameter */ + assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock)); + + /* Disable memory block shut-off */ + CLEAR_BIT (PWR->CR1, MemoryBlock); +} +#endif /* defined (PWR_CR1_SRDRAMSO) */ + +/** + * @brief Enable the Wake-up PINx functionality. + * @param sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that + * contains the configuration information for the wake-up + * Pin. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx. All combination are allowed: wake up only + * Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and + * Cortex-M4. + * @retval None. + */ +void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams) +{ + uint32_t pinConfig; + uint32_t regMask; + const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1; + + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin)); + assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity)); + assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull)); + + pinConfig = sPinParams->WakeUpPin | \ + (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP1_Pos) & 0x1FU)) | \ + (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) + PWR_WKUPEPR_WKUPPUPD1_Pos) & 0x1FU)); + + regMask = sPinParams->WakeUpPin | \ + (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \ + (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET) & 0x1FU)); + + /* Enable and Specify the Wake-Up pin polarity and the pull configuration + for the event detection (rising or falling edge) */ + MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig); +#ifndef DUAL_CORE + /* Configure the Wakeup Pin EXTI Line */ + MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos)); +#endif /* !DUAL_CORE */ +} + +/** + * @brief Disable the Wake-up PINx functionality. + * @param WakeUpPin : Specifies the Wake-Up pin to be disabled. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 : Disable PA0 wake-up PIN. + * @arg PWR_WAKEUP_PIN2 : Disable PA2 wake-up PIN. + * @arg PWR_WAKEUP_PIN3 : Disable PI8 wake-up PIN. + * @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN. + * @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN. + * @arg PWR_WAKEUP_PIN6 : Disable PC1 wake-up PIN. + * @note The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for + * devices that support GPIOI port. + * @retval None + */ +void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin) +{ + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin)); + + /* Disable the WakeUpPin */ + CLEAR_BIT (PWR->WKUPEPR, WakeUpPin); +} + +/** + * @brief Get the Wake-Up Pin pending flags. + * @param WakeUpFlag : Specifies the Wake-Up PIN flag to be checked. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Get wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Get wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Get wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Get wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Get wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Get wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all + * wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. + * @retval The Wake-Up pin flag. + */ +uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag) +{ + /* Check the parameters */ + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + + /* Return the wake up pin flag */ + return (PWR->WKUPFR & WakeUpFlag); +} + +/** + * @brief Clear the Wake-Up pin pending flag. + * @param WakeUpFlag: Specifies the Wake-Up PIN flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0. + * @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2. + * @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8. + * @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13. + * @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11. + * @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1. + * @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from + * all wake up pins. + * @note The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for + * devices that support GPIOI port. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag) +{ + /* Check the parameter */ + assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag)); + + /* Clear the wake up event received from wake up pin x */ + SET_BIT (PWR->WKUPCR, WakeUpFlag); + + /* Check if the wake up event is well cleared */ + if ((PWR->WKUPFR & WakeUpFlag) != 0U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief This function handles the PWR WAKEUP PIN interrupt request. + * @note This API should be called under the WAKEUP_PIN_IRQHandler(). + * @retval None. + */ +void HAL_PWREx_WAKEUP_PIN_IRQHandler (void) +{ + /* Wakeup pin EXTI line interrupt detected */ + if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U) + { + /* Clear PWR WKUPF1 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1); + + /* PWR WKUP1 interrupt user callback */ + HAL_PWREx_WKUP1_Callback (); + } + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U) + { + /* Clear PWR WKUPF2 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2); + + /* PWR WKUP2 interrupt user callback */ + HAL_PWREx_WKUP2_Callback (); + } +#if defined (PWR_WKUPFR_WKUPF3) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U) + { + /* Clear PWR WKUPF3 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3); + + /* PWR WKUP3 interrupt user callback */ + HAL_PWREx_WKUP3_Callback (); + } +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U) + { + /* Clear PWR WKUPF4 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4); + + /* PWR WKUP4 interrupt user callback */ + HAL_PWREx_WKUP4_Callback (); + } +#if defined (PWR_WKUPFR_WKUPF5) + else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U) + { + /* Clear PWR WKUPF5 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5); + + /* PWR WKUP5 interrupt user callback */ + HAL_PWREx_WKUP5_Callback (); + } +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + else + { + /* Clear PWR WKUPF6 flag */ + __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6); + + /* PWR WKUP6 interrupt user callback */ + HAL_PWREx_WKUP6_Callback (); + } +} + +/** + * @brief PWR WKUP1 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP1_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP1Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP2 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP2_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP2Callback can be implemented in the user file + */ +} + +#if defined (PWR_WKUPFR_WKUPF3) +/** + * @brief PWR WKUP3 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP3_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP3Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF3) */ + +/** + * @brief PWR WKUP4 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP4_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP4Callback can be implemented in the user file + */ +} + +#if defined (PWR_WKUPFR_WKUPF5) +/** + * @brief PWR WKUP5 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP5_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP5Callback can be implemented in the user file + */ +} +#endif /* defined (PWR_WKUPFR_WKUPF5) */ + +/** + * @brief PWR WKUP6 interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_WKUP6_Callback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWREx_WKUP6Callback can be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions + * @brief Peripherals control functions + * +@verbatim + =============================================================================== + ##### Peripherals control functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only + from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its + content is retained even in Standby or VBAT mode when the low power + backup regulator is enabled. It can be considered as an internal + EEPROM when VBAT is always present. You can use the + HAL_PWREx_EnableBkUpReg() function to enable the low power backup + regulator. + (+) When the backup domain is supplied by VDD (analog switch connected to + VDD) the backup SRAM is powered from VDD which replaces the VBAT power + supply to save battery life. + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + (+) The main internal regulator can be configured to have a tradeoff + between performance and power consumption when the device does not + operate at the maximum frequency. This is done through + HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS + bit in PWR_D3CR register. + (+) The main internal regulator can be configured to operate in Low Power + mode when the system enters STOP mode to further reduce power + consumption. + This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS) + function which configure the SVOS bit in PWR_CR1 register. + The selected SVOS4 and SVOS5 levels add an additional startup delay + when exiting from system Stop mode. + -@- Refer to the product datasheets for more details. + + *** USB Regulator configuration *** + =================================== + [..] + (+) The USB transceivers are supplied from a dedicated VDD33USB supply + that can be provided either by the integrated USB regulator, or by an + external USB supply. + (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the + VDD33USB is then provided from the USB regulator. + (+) When the USB regulator is enabled, the VDD33USB supply level detector + shall be enabled through HAL_PWREx_EnableUSBVoltageDetector() + function. + (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg() + function and VDD33USB can be provided from an external supply. In this + case VDD33USB and VDD50USB shall be connected together. + + *** VBAT battery charging *** + ============================= + [..] + (+) When VDD is present, the external battery connected to VBAT can be + charged through an internal resistance. VBAT charging can be performed + either through a 5 KOhm resistor or through a 1.5 KOhm resistor. + (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging + (ResistorValue) function with: + (++) ResistorValue: + (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor. + (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor. + (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging() + function. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void) +{ + uint32_t tickstart; + + /* Enable the Backup regulator */ + SET_BIT (PWR->CR2, PWR_CR2_BREN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till Backup regulator ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Backup Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void) +{ + uint32_t tickstart; + + /* Disable the Backup regulator */ + CLEAR_BIT (PWR->CR2, PWR_CR2_BREN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till Backup regulator ready flag is reset */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void) +{ + uint32_t tickstart; + + /* Enable the USB regulator */ + SET_BIT (PWR->CR3, PWR_CR3_USBREGEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till the USB regulator ready flag is set */ + while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the USB Regulator. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void) +{ + uint32_t tickstart; + + /* Disable the USB regulator */ + CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN); + + /* Get tick */ + tickstart = HAL_GetTick (); + + /* Wait till the USB regulator ready flag is reset */ + while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U) + { + if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Enable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_EnableUSBVoltageDetector (void) +{ + /* Enable the USB voltage detector */ + SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Disable the USB voltage level detector. + * @retval None. + */ +void HAL_PWREx_DisableUSBVoltageDetector (void) +{ + /* Disable the USB voltage detector */ + CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN); +} + +/** + * @brief Enable the Battery charging. + * @note When VDD is present, charge the external battery through an internal + * resistor. + * @param ResistorValue : Specifies the charging resistor. + * This parameter can be one of the following values : + * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. + * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. + * @retval None. + */ +void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue) +{ + /* Check the parameter */ + assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue)); + + /* Specify the charging resistor */ + MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue); + + /* Enable the Battery charging */ + SET_BIT (PWR->CR3, PWR_CR3_VBE); +} + +/** + * @brief Disable the Battery charging. + * @retval None. + */ +void HAL_PWREx_DisableBatteryCharging (void) +{ + /* Disable the Battery charging */ + CLEAR_BIT (PWR->CR3, PWR_CR3_VBE); +} + +#if defined (PWR_CR1_BOOSTE) +/** + * @brief Enable the booster to guarantee the analog switch AC performance when + * the VDD supply voltage is below 2V7. + * @note The VDD supply voltage can be monitored through the PVD and the PLS + * field bits. + * @retval None. + */ +void HAL_PWREx_EnableAnalogBooster (void) +{ + /* Enable the Analog voltage */ + SET_BIT (PWR->CR1, PWR_CR1_AVD_READY); + + /* Enable VDDA booster */ + SET_BIT (PWR->CR1, PWR_CR1_BOOSTE); +} + +/** + * @brief Disable the analog booster. + * @retval None. + */ +void HAL_PWREx_DisableAnalogBooster (void) +{ + /* Disable VDDA booster */ + CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE); + + /* Disable the Analog voltage */ + CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY); +} +#endif /* defined (PWR_CR1_BOOSTE) */ +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions + * @brief Power Monitoring functions + * +@verbatim + =============================================================================== + ##### Power Monitoring functions ##### + =============================================================================== + + *** VBAT and Temperature supervision *** + ======================================== + [..] + (+) The VBAT battery voltage supply can be monitored by comparing it with + two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags + in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or + lower than the threshold. + (+) The temperature can be monitored by comparing it with two threshold + levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR + control register 2 (PWR_CR2), indicate whether the device temperature + is higher or lower than the threshold. + (+) The VBAT and the temperature monitoring is enabled by + HAL_PWREx_EnableMonitoring() function and disabled by + HAL_PWREx_DisableMonitoring() function. + (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can + be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or + PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD. + (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature + level which can be : + PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or + PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD. + + *** AVD configuration *** + ========================= + [..] + (+) The AVD is used to monitor the VDDA power supply by comparing it to a + threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1 + register). + (+) A AVDO flag is available to indicate if VDDA is higher or lower + than the AVD threshold. This event is internally connected to the EXTI + line 16 to generate an interrupt if enabled. + It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro. + (+) The AVD is stopped in System Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_EnableMonitoring (void) +{ + /* Enable the VBAT and Temperature monitoring */ + SET_BIT (PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Disable the VBAT and temperature monitoring. + * @retval HAL status. + */ +void HAL_PWREx_DisableMonitoring (void) +{ + /* Disable the VBAT and Temperature monitoring */ + CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN); +} + +/** + * @brief Indicate whether the junction temperature is between, above or below + * the thresholds. + * @retval Temperature level. + */ +uint32_t HAL_PWREx_GetTemperatureLevel (void) +{ + uint32_t tempLevel, regValue; + + /* Read the temperature flags */ + regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL)); + + /* Check if the temperature is below the threshold */ + if (regValue == PWR_CR2_TEMPL) + { + tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD; + } + /* Check if the temperature is above the threshold */ + else if (regValue == PWR_CR2_TEMPH) + { + tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD; + } + /* The temperature is between the thresholds */ + else + { + tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return tempLevel; +} + +/** + * @brief Indicate whether the Battery voltage level is between, above or below + * the thresholds. + * @retval VBAT level. + */ +uint32_t HAL_PWREx_GetVBATLevel (void) +{ + uint32_t VBATLevel, regValue; + + /* Read the VBAT flags */ + regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL)); + + /* Check if the VBAT is below the threshold */ + if (regValue == PWR_CR2_VBATL) + { + VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD; + } + /* Check if the VBAT is above the threshold */ + else if (regValue == PWR_CR2_VBATH) + { + VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD; + } + /* The VBAT is between the thresholds */ + else + { + VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD; + } + + return VBATLevel; +} + +#if defined (PWR_CSR1_MMCVDO) +/** + * @brief Get the VDDMMC voltage level. + * @retval The VDDMMC voltage level. + */ +PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void) +{ + PWREx_MMC_VoltageLevel mmc_voltage; + + /* Check voltage detector output on VDDMMC value */ + if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U) + { + mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2; + } + else + { + mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2; + } + + return mmc_voltage; +} +#endif /* defined (PWR_CSR1_MMCVDO) */ + +/** + * @brief Configure the event mode and the voltage threshold detected by the + * Analog Voltage Detector (AVD). + * @param sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains + * the configuration information for the AVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @note For dual core devices, please ensure to configure the EXTI lines for + * the different Cortex-Mx through PWR_Exported_Macro provided by this + * driver. All combination are allowed: wake up only Cortex-M7, wake up + * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. + * @retval None. + */ +void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD) +{ + /* Check the parameters */ + assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); + assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode)); + + /* Set the ALS[18:17] bits according to AVDLevel value */ + MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel); + + /* Clear any previous config */ +#if !defined (DUAL_CORE) + __HAL_PWR_AVD_EXTI_DISABLE_EVENT (); + __HAL_PWR_AVD_EXTI_DISABLE_IT (); +#endif /* !defined (DUAL_CORE) */ + + __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE (); + __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE (); + +#if !defined (DUAL_CORE) + /* Configure the interrupt mode */ + if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT) + { + __HAL_PWR_AVD_EXTI_ENABLE_IT (); + } + + /* Configure the event mode */ + if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT) + { + __HAL_PWR_AVD_EXTI_ENABLE_EVENT (); + } +#endif /* !defined (DUAL_CORE) */ + + /* Rising edge configuration */ + if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE (); + } + + /* Falling edge configuration */ + if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE) + { + __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE (); + } +} + +/** + * @brief Enable the Analog Voltage Detector (AVD). + * @retval None. + */ +void HAL_PWREx_EnableAVD (void) +{ + /* Enable the Analog Voltage Detector */ + SET_BIT (PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief Disable the Analog Voltage Detector(AVD). + * @retval None. + */ +void HAL_PWREx_DisableAVD (void) +{ + /* Disable the Analog Voltage Detector */ + CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN); +} + +/** + * @brief This function handles the PWR PVD/AVD interrupt request. + * @note This API should be called under the PVD_AVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_AVD_IRQHandler (void) +{ + /* Check if the Programmable Voltage Detector is enabled (PVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U) + { +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ + { + /* Check PWR D1/CD EXTI flag */ + if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG (); + } + } +#if defined (DUAL_CORE) + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback (); + + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_PVD_EXTID2_CLEAR_FLAG(); + } + } +#endif /* defined (DUAL_CORE) */ + } + + /* Check if the Analog Voltage Detector is enabled (AVD) */ + if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U) + { +#if defined (DUAL_CORE) + if (HAL_GetCurrentCPUID () == CM7_CPUID) +#endif /* defined (DUAL_CORE) */ + { + /* Check PWR EXTI D1/CD flag */ + if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U) + { + /* PWR AVD interrupt user callback */ + HAL_PWREx_AVDCallback (); + + /* Clear PWR EXTI D1/CD pending bit */ + __HAL_PWR_AVD_EXTI_CLEAR_FLAG (); + } + } +#if defined (DUAL_CORE) + else + { + /* Check PWR EXTI D2 flag */ + if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U) + { + /* PWR AVD interrupt user callback */ + HAL_PWREx_AVDCallback (); + + /* Clear PWR EXTI D2 pending bit */ + __HAL_PWR_AVD_EXTID2_CLEAR_FLAG (); + } + } +#endif /* defined (DUAL_CORE) */ + } +} + +/** + * @brief PWR AVD interrupt callback. + * @retval None. + */ +__weak void HAL_PWREx_AVDCallback (void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_AVDCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c new file mode 100644 index 0000000..822b0c9 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_qspi.c @@ -0,0 +1,2666 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_qspi.c + * @author MCD Application Team + * @brief QSPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the QuadSPI interface (QSPI). + * + Initialization and de-initialization functions + * + Indirect functional mode management + * + Memory-mapped functional mode management + * + Auto-polling functional mode management + * + Interrupts and flags management + * + MDMA channel configuration for indirect functional mode + * + Errors management and abort functionality + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + *** Initialization *** + ====================== + [..] + (#) As prerequisite, fill in the HAL_QSPI_MspInit() : + (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). + (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). + (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). + (++) If interrupt mode is used, enable and configure QuadSPI global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (++) If DMA mode is used, enable the clocks for the QuadSPI MDMA + with __HAL_RCC_MDMA_CLK_ENABLE(), configure MDMA with HAL_MDMA_Init(), + link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure + MDMA global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (#) Configure the flash size, the clock prescaler, the fifo threshold, the + clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function. + + *** Indirect functional mode *** + ================================ + [..] + (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() + functions : + (++) Instruction phase : the mode used and if present the instruction opcode. + (++) Address phase : the mode used and if present the size and the address value. + (++) Alternate-bytes phase : the mode used and if present the size and the alternate + bytes values. + (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (++) Data phase : the mode used and if present the number of bytes. + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + if activated. + (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + (#) If no data is required for the command, it is sent directly to the memory : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete. + (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or + HAL_QSPI_Transmit_IT() after the command configuration : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode,HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. + (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or + HAL_QSPI_Receive_IT() after the command configuration : + (++) In polling mode, the output of the function is done when the transfer is complete. + (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. + (++) In DMA mode,HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. + + *** Auto-polling functional mode *** + ==================================== + [..] + (#) Configure the command sequence and the auto-polling functional mode using the + HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions : + (++) Instruction phase : the mode used and if present the instruction opcode. + (++) Address phase : the mode used and if present the size and the address value. + (++) Alternate-bytes phase : the mode used and if present the size and the alternate + bytes values. + (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (++) Data phase : the mode used. + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + if activated. + (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), + the polling interval and the automatic stop activation. + (#) After the configuration : + (++) In polling mode, the output of the function is done when the status match is reached. The + automatic stop is activated to avoid an infinite loop. + (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached. + + *** MDMA functional mode *** + ==================================== + [..] + (#) Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_QSPI_MspInit() function : + (++) MDMA settings for write operation : + (+) The DestinationInc should be MDMA_DEST_INC_DISABLE + (+) The SourceInc must be a value of MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). + (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) + aligned with MDMA_Source_increment_mode . + (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + (++) MDMA settings for read operation : + (+) The SourceInc should be MDMA_SRC_INC_DISABLE + (+) The DestinationInc must be a value of MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). + (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . + (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + aligned with MDMA_Destination_increment_mode. + (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi. + (#)In case of wrong MDMA setting + (++) For write operation : + (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_QSPI_Transmit_DMA(). + (++) For read operation : + (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_QSPI_Receive_DMA(). + + *** Memory-mapped functional mode *** + ===================================== + [..] + (#) Configure the command sequence and the memory-mapped functional mode using the + HAL_QSPI_MemoryMapped() functions : + (++) Instruction phase : the mode used and if present the instruction opcode. + (++) Address phase : the mode used and the size. + (++) Alternate-bytes phase : the mode used and if present the size and the alternate + bytes values. + (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (++) Data phase : the mode used. + (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay + if activated. + (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + (++) The timeout activation and the timeout period. + (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on + the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. + + *** Errors management and abort functionality *** + ================================================= + [..] + (#) HAL_QSPI_GetError() function gives the error raised during the last operation. + (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and + flushes the fifo : + (++) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. + + *** Control functions *** + ========================= + [..] + (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver. + (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. + (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. + (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_QSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : QSPI MspInit. + (+) MspDeInitCallback : QSPI MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : QSPI MspInit. + (+) MspDeInitCallback : QSPI MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit + or HAL_QSPI_Init function. + + When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** Workarounds linked to Silicon Limitation *** + ==================================================== + [..] + (#) Workarounds Implemented inside HAL Driver + (++) Extra data written in the FIFO at the end of a read transfer + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +#if defined(QUADSPI) + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup QSPI QSPI + * @brief QSPI HAL module driver + * @{ + */ +#ifdef HAL_QSPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup QSPI_Private_Constants QSPI Private Constants + * @{ + */ +#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!Instance)); + assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); + assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); + assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); + assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); + assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); + assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); + assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); + + if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) + { + assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); + } + + if(hqspi->State == HAL_QSPI_STATE_RESET) + { + +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */ + hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; + hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; + hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; + hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; + hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; + hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; + hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; + hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; + + if(hqspi->MspInitCallback == NULL) + { + hqspi->MspInitCallback = HAL_QSPI_MspInit; + } + + /* Init the low level hardware */ + hqspi->MspInitCallback(hqspi); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_QSPI_MspInit(hqspi); +#endif + + /* Configure the default timeout for the QSPI memory access */ + HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); + } + + /* Configure QSPI FIFO Threshold */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); + + /* Wait till BUSY flag reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + + if(status == HAL_OK) + { + /* Configure QSPI Clock Prescaler and Sample Shift */ + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), + ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | + hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); + + /* Configure QSPI Flash Size, CS High Time and Clock Mode */ + MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), + ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | + hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); + + /* Enable the QSPI peripheral */ + __HAL_QSPI_ENABLE(hqspi); + + /* Set QSPI error code to none */ + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + /* Initialize the QSPI state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief De-Initialize the QSPI peripheral. + * @param hqspi QSPI handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) +{ + /* Check the QSPI handle allocation */ + if(hqspi == NULL) + { + return HAL_ERROR; + } + + /* Disable the QSPI Peripheral Clock */ + __HAL_QSPI_DISABLE(hqspi); + +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + if(hqspi->MspDeInitCallback == NULL) + { + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + } + + /* DeInit the low level hardware */ + hqspi->MspDeInitCallback(hqspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_QSPI_MspDeInit(hqspi); +#endif + + /* Set QSPI error code to none */ + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + /* Initialize the QSPI state */ + hqspi->State = HAL_QSPI_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the QSPI MSP. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_QSPI_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the QSPI MSP. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_QSPI_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions + * @brief QSPI Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Handle the interrupts. + (+) Handle the command sequence. + (+) Transmit data in blocking, interrupt or DMA mode. + (+) Receive data in blocking, interrupt or DMA mode. + (+) Manage the auto-polling functional mode. + (+) Manage the memory-mapped functional mode. + +@endverbatim + * @{ + */ + +/** + * @brief Handle QSPI interrupt request. + * @param hqspi QSPI handle + * @retval None + */ +void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) +{ + __IO uint32_t *data_reg; + uint32_t flag = READ_REG(hqspi->Instance->SR); + uint32_t itsource = READ_REG(hqspi->Instance->CR); + + /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ + if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) + { + data_reg = &hqspi->Instance->DR; + + if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) + { + /* Transmission process */ + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) + { + if (hqspi->TxXferCount > 0U) + { + /* Fill the FIFO until the threshold is reached */ + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; + hqspi->TxXferCount--; + } + else + { + /* No more data available for the transfer */ + /* Disable the QSPI FIFO Threshold Interrupt */ + __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); + break; + } + } + } + else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) + { + /* Receiving Process */ + while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) + { + if (hqspi->RxXferCount > 0U) + { + /* Read the FIFO until the threshold is reached */ + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; + hqspi->RxXferCount--; + } + else + { + /* All data have been received for the transfer */ + /* Disable the QSPI FIFO Threshold Interrupt */ + __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); + break; + } + } + } + else + { + /* Nothing to do */ + } + + /* FIFO Threshold callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->FifoThresholdCallback(hqspi); +#else + HAL_QSPI_FifoThresholdCallback(hqspi); +#endif + } + + /* QSPI Transfer Complete interrupt occurred -------------------------------*/ + else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) + { + /* Clear interrupt */ + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); + + /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ + __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); + + /* Transfer complete callback */ + if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) + { + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + { + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hqspi->hmdma); + } + + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* TX Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TxCpltCallback(hqspi); +#else + HAL_QSPI_TxCpltCallback(hqspi); +#endif + } + else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) + { + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + { + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hqspi->hmdma); + } + else + { + data_reg = &hqspi->Instance->DR; + while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) + { + if (hqspi->RxXferCount > 0U) + { + /* Read the last data received in the FIFO until it is empty */ + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; + hqspi->RxXferCount--; + } + else + { + /* All data have been received for the transfer */ + break; + } + } + } + + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* RX Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->RxCpltCallback(hqspi); +#else + HAL_QSPI_RxCpltCallback(hqspi); +#endif + } + else if(hqspi->State == HAL_QSPI_STATE_BUSY) + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Command Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->CmdCpltCallback(hqspi); +#else + HAL_QSPI_CmdCpltCallback(hqspi); +#endif + } + else if(hqspi->State == HAL_QSPI_STATE_ABORT) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) + { + /* Abort called by the user */ + + /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else + HAL_QSPI_AbortCpltCallback(hqspi); +#endif + } + else + { + /* Abort due to an error (eg : MDMA error) */ + + /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else + HAL_QSPI_ErrorCallback(hqspi); +#endif + } + } + else + { + /* Nothing to do */ + } + } + + /* QSPI Status Match interrupt occurred ------------------------------------*/ + else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) + { + /* Clear interrupt */ + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); + + /* Check if the automatic poll mode stop is activated */ + if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) + { + /* Disable the QSPI Transfer Error and Status Match Interrupts */ + __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } + + /* Status match callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->StatusMatchCallback(hqspi); +#else + HAL_QSPI_StatusMatchCallback(hqspi); +#endif + } + + /* QSPI Transfer Error interrupt occurred ----------------------------------*/ + else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) + { + /* Clear interrupt */ + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); + + /* Disable all the QSPI Interrupts */ + __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); + + /* Set error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + { + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Disable the MDMA channel */ + hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; + if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + { + /* Set error code to DMA */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else + HAL_QSPI_ErrorCallback(hqspi); +#endif + } + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else + HAL_QSPI_ErrorCallback(hqspi); +#endif + } + } + + /* QSPI Timeout interrupt occurred -----------------------------------------*/ + else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) + { + /* Clear interrupt */ + WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); + + /* Timeout callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->TimeOutCallback(hqspi); +#else + HAL_QSPI_TimeOutCallback(hqspi); +#endif + } + + else + { + /* Nothing to do */ + } +} + +/** + * @brief Set the command configuration. + * @param hqspi QSPI handle + * @param cmd : structure that contains the command configuration information + * @param Timeout Timeout duration + * @note This function is used only in Indirect Read or Write Modes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + { + assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); + } + + assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); + } + + assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); + if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); + } + + assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); + assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + + assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); + assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_BUSY; + + /* Wait till BUSY flag reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Call the configuration function */ + QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + if (cmd->DataMode == QSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + else + { + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** + * @brief Set the command configuration in interrupt mode. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @note This function is used only in Indirect Read or Write Modes + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + { + assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); + } + + assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); + } + + assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); + if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); + } + + assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); + assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + + assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); + assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_BUSY; + + /* Wait till BUSY flag reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + if (cmd->DataMode == QSPI_DATA_NONE) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + } + + /* Call the configuration function */ + QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + if (cmd->DataMode == QSPI_DATA_NONE) + { + /* When there is no data phase, the transfer start as soon as the configuration is done + so activate TC and TE interrupts */ + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI Transfer Error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); + } + else + { + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + + /* Return function status */ + return status; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + __IO uint32_t *data_reg = &hqspi->Instance->DR; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + if(pData != NULL ) + { + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; + + /* Configure counters and size of the handle */ + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->pTxBuffPtr = pData; + + /* Configure QSPI: CCR register with functional as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + while(hqspi->TxXferCount > 0U) + { + /* Wait until FT flag is set to send data */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; + hqspi->pTxBuffPtr++; + hqspi->TxXferCount--; + } + + if (status == HAL_OK) + { + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear Transfer Complete bit */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + } + } + + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + else + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + return status; +} + + +/** + * @brief Receive an amount of data in blocking mode. + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + __IO uint32_t *data_reg = &hqspi->Instance->DR; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + if(pData != NULL ) + { + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; + + /* Configure counters and size of the handle */ + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->pRxBuffPtr = pData; + + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + while(hqspi->RxXferCount > 0U) + { + /* Wait until FT or TC flag is set to read received data */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout); + + if (status != HAL_OK) + { + break; + } + + *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); + hqspi->pRxBuffPtr++; + hqspi->RxXferCount--; + } + + if (status == HAL_OK) + { + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Clear Transfer Complete bit */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + } + } + + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + else + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + } + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with interrupt. + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + if(pData != NULL ) + { + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; + + /* Configure counters and size of the handle */ + hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->pTxBuffPtr = pData; + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + + /* Configure QSPI: CCR register with functional as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); + } + else + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with interrupt. + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + if(pData != NULL ) + { + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; + + /* Configure counters and size of the handle */ + hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; + hqspi->pRxBuffPtr = pData; + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); + + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); + } + else + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + + return status; +} + +/** + * @brief Send an amount of data in non-blocking mode with DMA. + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @note This function is used only in Indirect Write Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Clear the error code */ + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + if(pData != NULL ) + { + /* Configure counters of the handle */ + hqspi->TxXferCount = data_size; + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + + /* Configure size and pointer of the handle */ + hqspi->TxXferSize = hqspi->TxXferCount; + hqspi->pTxBuffPtr = pData; + + /* Configure QSPI: CCR register with functional mode as indirect write */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); + + /* Set the QSPI MDMA transfer complete callback */ + hqspi->hmdma->XferCpltCallback = QSPI_DMATxCplt; + + /* Set the MDMA error callback */ + hqspi->hmdma->XferErrorCallback = QSPI_DMAError; + + /* Clear the MDMA abort callback */ + hqspi->hmdma->XferAbortCallback = NULL; + + /* In Transmit mode , the MDMA destination is the QSPI DR register : Force the MDMA Destination Increment to disable */ + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE); + + /* Update MDMA configuration with the correct SourceInc field for Write operation */ + if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE); + } + else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD); + } + else if (hqspi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD); + } + else + { + /* in case of incorrect source data size */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + status = HAL_ERROR; + } + + /* Enable the QSPI transmit MDMA */ + if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize, 1) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + + return status; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. + * @note This function is used only in Indirect Read Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t addr_reg = READ_REG(hqspi->Instance->AR); + uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Clear the error code */ + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + if(pData != NULL ) + { + /* Configure counters of the handle */ + hqspi->RxXferCount = data_size; + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); + + /* Configure size and pointer of the handle */ + hqspi->RxXferSize = hqspi->RxXferCount; + hqspi->pRxBuffPtr = pData; + + /* Set the QSPI MDMA transfer complete callback */ + hqspi->hmdma->XferCpltCallback = QSPI_DMARxCplt; + + /* Set the MDMA error callback */ + hqspi->hmdma->XferErrorCallback = QSPI_DMAError; + + /* Clear the MDMA abort callback */ + hqspi->hmdma->XferAbortCallback = NULL; + + /* In Receive mode , the MDMA source is the QSPI DR register : Force the MDMA Source Increment to disable */ + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE); + + /* Update MDMA configuration with the correct DestinationInc field for read operation */ + if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE); + } + else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD); + } + else if (hqspi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD) + { + MODIFY_REG(hqspi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD); + } + else + { + /* in case of incorrect destination data size */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + status = HAL_ERROR; + } + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + /* Enable the MDMA */ + if (HAL_MDMA_Start_IT(hqspi->hmdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize, 1) == HAL_OK) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + + /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; + status = HAL_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + + return status; +} + +/** + * @brief Configure the QSPI Automatic Polling Mode in blocking mode. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Timeout duration + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + { + assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); + } + + assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); + } + + assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); + if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); + } + + assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); + assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + + assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); + assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + + assert_param(IS_QSPI_INTERVAL(cfg->Interval)); + assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); + assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; + + /* Wait till BUSY flag reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); + + if (status == HAL_OK) + { + /* Configure QSPI: PSMAR register with the status match value */ + WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); + + /* Configure QSPI: PSMKR register with the status mask value */ + WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); + + /* Configure QSPI: PIR register with the interval value */ + WRITE_REG(hqspi->Instance->PIR, cfg->Interval); + + /* Configure QSPI: CR register with Match mode and Automatic stop enabled + (otherwise there will be an infinite loop in blocking mode) */ + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), + (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); + + /* Call the configuration function */ + cmd->NbData = cfg->StatusBytesSize; + QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + + /* Wait until SM flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); + + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** + * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @note This function is used only in Automatic Polling Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + { + assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); + } + + assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); + } + + assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); + if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); + } + + assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); + assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + + assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); + assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + + assert_param(IS_QSPI_INTERVAL(cfg->Interval)); + assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); + assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); + assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; + + /* Wait till BUSY flag reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + /* Configure QSPI: PSMAR register with the status match value */ + WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); + + /* Configure QSPI: PSMKR register with the status mask value */ + WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); + + /* Configure QSPI: PIR register with the interval value */ + WRITE_REG(hqspi->Instance->PIR, cfg->Interval); + + /* Configure QSPI: CR register with Match mode and Automatic stop mode */ + MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), + (cfg->MatchMode | cfg->AutomaticStop)); + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); + + /* Call the configuration function */ + cmd->NbData = cfg->StatusBytesSize; + QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI Transfer Error and status match Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); + + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + } + else + { + status = HAL_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the Memory Mapped mode. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. + * @note This function is used only in Memory mapped Mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); + if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + { + assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); + } + + assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); + } + + assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); + if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + { + assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); + } + + assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); + assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); + + assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); + assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); + assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); + + assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; + + /* Wait till BUSY flag reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + /* Configure QSPI: CR register with timeout counter enable */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); + + if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) + { + assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); + + /* Configure QSPI: LPTR register with the low-power timeout value */ + WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); + + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); + + /* Enable the QSPI TimeOut Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); + } + + /* Call the configuration function */ + QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); + } + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** + * @brief Transfer Error callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_QSPI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Abort completed callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_QSPI_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Command completed callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_QSPI_CmdCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_QSPI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer completed callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_QSPI_TxCpltCallback could be implemented in the user file + */ +} + + +/** + * @brief FIFO Threshold callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file + */ +} + +/** + * @brief Status Match callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_QSPI_StatusMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Timeout callback. + * @param hqspi QSPI handle + * @retval None + */ +__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hqspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_QSPI_TimeOutCallback could be implemented in the user file + */ +} +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User QSPI Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID + * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID + * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID + * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID + * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID + * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID + * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID + * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID + * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID + * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + switch (CallbackId) + { + case HAL_QSPI_ERROR_CB_ID : + hqspi->ErrorCallback = pCallback; + break; + case HAL_QSPI_ABORT_CB_ID : + hqspi->AbortCpltCallback = pCallback; + break; + case HAL_QSPI_FIFO_THRESHOLD_CB_ID : + hqspi->FifoThresholdCallback = pCallback; + break; + case HAL_QSPI_CMD_CPLT_CB_ID : + hqspi->CmdCpltCallback = pCallback; + break; + case HAL_QSPI_RX_CPLT_CB_ID : + hqspi->RxCpltCallback = pCallback; + break; + case HAL_QSPI_TX_CPLT_CB_ID : + hqspi->TxCpltCallback = pCallback; + break; + case HAL_QSPI_STATUS_MATCH_CB_ID : + hqspi->StatusMatchCallback = pCallback; + break; + case HAL_QSPI_TIMEOUT_CB_ID : + hqspi->TimeOutCallback = pCallback; + break; + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = pCallback; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hqspi->State == HAL_QSPI_STATE_RESET) + { + switch (CallbackId) + { + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = pCallback; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hqspi); + return status; +} + +/** + * @brief Unregister a User QSPI Callback + * QSPI Callback is redirected to the weak (surcharged) predefined callback + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID + * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID + * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID + * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID + * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID + * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID + * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID + * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID + * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID + * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + switch (CallbackId) + { + case HAL_QSPI_ERROR_CB_ID : + hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; + break; + case HAL_QSPI_ABORT_CB_ID : + hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; + break; + case HAL_QSPI_FIFO_THRESHOLD_CB_ID : + hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; + break; + case HAL_QSPI_CMD_CPLT_CB_ID : + hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; + break; + case HAL_QSPI_RX_CPLT_CB_ID : + hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; + break; + case HAL_QSPI_TX_CPLT_CB_ID : + hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; + break; + case HAL_QSPI_STATUS_MATCH_CB_ID : + hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; + break; + case HAL_QSPI_TIMEOUT_CB_ID : + hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; + break; + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = HAL_QSPI_MspInit; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hqspi->State == HAL_QSPI_STATE_RESET) + { + switch (CallbackId) + { + case HAL_QSPI_MSP_INIT_CB_ID : + hqspi->MspInitCallback = HAL_QSPI_MspInit; + break; + case HAL_QSPI_MSP_DEINIT_CB_ID : + hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; + break; + default : + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hqspi); + return status; +} +#endif + +/** + * @} + */ + +/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions + * @brief QSPI control and State functions + * +@verbatim + =============================================================================== + ##### Peripheral Control and State functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to : + (+) Check in run-time the state of the driver. + (+) Check the error code set during last operation. + (+) Abort any operation. + + +@endverbatim + * @{ + */ + +/** + * @brief Return the QSPI handle state. + * @param hqspi QSPI handle + * @retval HAL state + */ +HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) +{ + /* Return QSPI handle state */ + return hqspi->State; +} + +/** +* @brief Return the QSPI error code. +* @param hqspi QSPI handle +* @retval QSPI Error Code +*/ +uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) +{ + return hqspi->ErrorCode; +} + +/** +* @brief Abort the current transmission. +* @param hqspi QSPI handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart = HAL_GetTick(); + + /* Check if the state is in one of the busy states */ + if (((uint32_t)hqspi->State & 0x2U) != 0U) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + { + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Abort MDMA */ + status = HAL_MDMA_Abort(hqspi->hmdma); + if(status != HAL_OK) + { + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + } + } + + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } + + if (status == HAL_OK) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + else + { + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + + return status; +} + +/** +* @brief Abort the current transmission (non-blocking function) +* @param hqspi QSPI handle +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check if the state is in one of the busy states */ + if (((uint32_t)hqspi->State & 0x2U) != 0U) + { + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Update QSPI state */ + hqspi->State = HAL_QSPI_STATE_ABORT; + + /* Disable all interrupts */ + __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); + + if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) + { + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Abort MDMA channel */ + hqspi->hmdma->XferAbortCallback = QSPI_DMAAbortCplt; + if (HAL_MDMA_Abort_IT(hqspi->hmdma) != HAL_OK) + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Abort Complete callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->AbortCpltCallback(hqspi); +#else + HAL_QSPI_AbortCpltCallback(hqspi); +#endif + } + } + else + { + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } + } + } + return status; +} + +/** @brief Set QSPI timeout. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. + * @retval None + */ +void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) +{ + hqspi->Timeout = Timeout; +} + +/** @brief Set QSPI Fifo threshold. + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Synchronize init structure with new FIFO threshold value */ + hqspi->Init.FifoThreshold = Threshold; + + /* Configure QSPI FIFO Threshold */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, + ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** @brief Get QSPI Fifo threshold. + * @param hqspi QSPI handle. + * @retval Fifo threshold (value between 1 and 16) + */ +uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) +{ + return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); +} + +/** @brief Set FlashID. + * @param hqspi QSPI handle. + * @param FlashID Index of the flash memory to be accessed. + * This parameter can be a value of @ref QSPI_Flash_Select. + * @note The FlashID is ignored when dual flash mode is enabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameter */ + assert_param(IS_QSPI_FLASH_ID(FlashID)); + + /* Process locked */ + __HAL_LOCK(hqspi); + + if(hqspi->State == HAL_QSPI_STATE_READY) + { + /* Synchronize init structure with new FlashID value */ + hqspi->Init.FlashID = FlashID; + + /* Configure QSPI FlashID */ + MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); + } + else + { + status = HAL_BUSY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup QSPI_Private_Functions QSPI Private Functions + * @{ + */ + +/** + * @brief DMA QSPI receive process complete callback. + * @param hmdma MDMA handle + * @retval None + */ +static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma) +{ + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); + hqspi->RxXferCount = 0U; + + /* Enable the QSPI transfer complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); +} + +/** + * @brief DMA QSPI transmit process complete callback. + * @param hmdma MDMA handle + * @retval None + */ +static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma) +{ + QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hmdma->Parent); + hqspi->TxXferCount = 0U; + + /* Enable the QSPI transfer complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); +} + +/** + * @brief DMA QSPI communication error callback. + * @param hmdma MDMA handle + * @retval None + */ +static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) +{ + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); + + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ + CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Abort the QSPI */ + (void)HAL_QSPI_Abort_IT(hqspi); + +} + +/** + * @brief MDMA QSPI abort complete callback. + * @param hmdma MDMA handle + * @retval None + */ +static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) +{ + QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hmdma->Parent); + + hqspi->RxXferCount = 0U; + hqspi->TxXferCount = 0U; + + if(hqspi->State == HAL_QSPI_STATE_ABORT) + { + /* MDMA Abort called by QSPI abort */ + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* MDMA Abort called due to a transfer error interrupt */ + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + + /* Error callback */ +#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) + hqspi->ErrorCallback(hqspi); +#else + HAL_QSPI_ErrorCallback(hqspi); +#endif + } +} + +/** + * @brief Wait for a flag state until timeout. + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, + FlagStatus State, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is in expected state */ + while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + hqspi->State = HAL_QSPI_STATE_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the communication registers. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured + * This parameter can be one of the following values: + * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode + * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode + * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode + * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode + * @retval None + */ +static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode) +{ + assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode)); + + if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) + { + /* Configure QSPI: DLR register with the number of data to read or write */ + WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); + } + + if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) + { + if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + { + /* Configure QSPI: ABR register with alternate bytes value */ + WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); + + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + /*---- Command with instruction, address and alternate bytes ----*/ + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | + cmd->Instruction | FunctionalMode)); + + if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) + { + /* Configure QSPI: AR register with address value */ + WRITE_REG(hqspi->Instance->AR, cmd->Address); + } + } + else + { + /*---- Command with instruction and alternate bytes ----*/ + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | + cmd->Instruction | FunctionalMode)); + } + } + else + { + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + /*---- Command with instruction and address ----*/ + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | + cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + + if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) + { + /* Configure QSPI: AR register with address value */ + WRITE_REG(hqspi->Instance->AR, cmd->Address); + } + } + else + { + /*---- Command with only instruction ----*/ + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | + cmd->InstructionMode | cmd->Instruction | FunctionalMode)); + } + } + } + else + { + if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) + { + /* Configure QSPI: ABR register with alternate bytes value */ + WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); + + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + /*---- Command with address and alternate bytes ----*/ + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressSize | cmd->AddressMode | + cmd->InstructionMode | FunctionalMode)); + + if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) + { + /* Configure QSPI: AR register with address value */ + WRITE_REG(hqspi->Instance->AR, cmd->Address); + } + } + else + { + /*---- Command with only alternate bytes ----*/ + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateBytesSize | cmd->AlternateByteMode | + cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + } + } + else + { + if (cmd->AddressMode != QSPI_ADDRESS_NONE) + { + /*---- Command with only address ----*/ + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressSize | + cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); + + if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) + { + /* Configure QSPI: AR register with address value */ + WRITE_REG(hqspi->Instance->AR, cmd->Address); + } + } + else + { + /*---- Command with only data phase ----*/ + if (cmd->DataMode != QSPI_DATA_NONE) + { + /* Configure QSPI: CCR register with all communications parameters */ + WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | + cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | + cmd->AlternateByteMode | cmd->AddressMode | + cmd->InstructionMode | FunctionalMode)); + } + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_QSPI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(QUADSPI) */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c new file mode 100644 index 0000000..8c987ac --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -0,0 +1,1814 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except + internal SRAM, Flash, JTAG and PWR + (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analogue mode , except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses pre-scalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock kernel source(s) for peripherals which clocks are not + derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R + and RCC_D3CCIPR registers + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE,CSI, LSI,HSI48, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB3, AHB1 + AHB2,AHB4,APB3, APB1L, APB1H, APB2, and APB4). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral + clock, or PLL input.But even with frequency calibration, is less accurate than an + external crystal oscillator or ceramic resonator. + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL , The RCC features three independent PLLs (clocked by HSI , HSE or CSI), + featuring three different output clocks and able to work either in integer or Fractional mode. + (++) A main PLL, PLL1, which is generally used to provide clocks to the CPU + and to some peripherals. + (++) Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals. + + + (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M NMI (Non-Mask-able Interrupt) + exception vector. + + (#) MCO1 (micro controller clock output), used to output HSI, LSE, HSE, PLL1(PLL1_Q) + or HSI48 clock (through a configurable pre-scaler) on PA8 pin. + + (#) MCO2 (micro controller clock output), used to output HSE, PLL2(PLL2_P), SYSCLK, + LSI, CSI, or PLL1(PLL1_P) clock (through a configurable pre-scaler) on PC9 pin. + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): CSI,HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System core clock through configurable + pre-scaler and used to clock the CPU, memory and peripherals mapped + on AHB and APB bus of the 3 Domains (D1, D2, D3)* through configurable pre-scalers + and used to clock the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve system clock frequency. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except those + with dual clock domain where kernel source clock could be selected through + RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers. + + (*) : 2 Domains (CD and SRD) for stm32h7a3xx and stm32h7b3xx family lines. +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL1, PLL2 and PLL3 OFF + * - AHB, APB Bus pre-scaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Update the SystemCoreClock and SystemD2Clock global variables */ + SystemCoreClock = HSI_VALUE; + SystemD2Clock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON \ + | RCC_CR_HSI48ON | RCC_CR_CSSHSEON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL2ON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); + + /* Wait till PLL2 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLL3 bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); + + /* Wait till PLL3 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_D1CFGR_HPRE) + /* Reset D1CFGR register */ + CLEAR_REG(RCC->D1CFGR); + + /* Reset D2CFGR register */ + CLEAR_REG(RCC->D2CFGR); + + /* Reset D3CFGR register */ + CLEAR_REG(RCC->D3CFGR); +#else + /* Reset CDCFGR1 register */ + CLEAR_REG(RCC->CDCFGR1); + + /* Reset CDCFGR2 register */ + CLEAR_REG(RCC->CDCFGR2); + + /* Reset SRDCFGR register */ + CLEAR_REG(RCC->SRDCFGR); +#endif + + /* Reset PLLCKSELR register to default value */ + RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5; + + /* Reset PLLCFGR register to default value */ + WRITE_REG(RCC->PLLCFGR, 0x01FF0000U); + + /* Reset PLL1DIVR register to default value */ + WRITE_REG(RCC->PLL1DIVR, 0x01010280U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2DIVR register to default value */ + WRITE_REG(RCC->PLL2DIVR, 0x01010280U); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + + /* Reset PLL3DIVR register to default value */ + WRITE_REG(RCC->PLL3DIVR, 0x01010280U); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); + +#if defined(RCC_CR_HSEEXT) + /* Reset HSEEXT */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +#endif /* RCC_CR_HSEEXT */ + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Reset all RSR flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + { + return HAL_ERROR; + } + + } + + return HAL_OK; +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t temp1_pllckcfg, temp2_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* When the HSI is used as system clock it will not be disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + { + return HAL_ERROR; + } + /* Otherwise, only HSI division and calibration are allowed */ + else + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- CSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + { + /* Check the parameters */ + assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); + assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue)); + + /* When the CSI is used as system clock it will not disabled */ + const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + const uint32_t temp_pllckselr = RCC->PLLCKSELR; + if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) + { + /* When CSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + } + } + else + { + /* Check the CSI State */ + if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) + { + /* Enable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/ + __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (CSI). */ + __HAL_RCC_CSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till CSI is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /*------------------------------ HSI48 Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the HSI48 State */ + if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLRGE_VALUE(RCC_OscInitStruct->PLL.PLLRGE)); + assert_param(IS_RCC_PLLVCO_VALUE(RCC_OscInitStruct->PLL.PLLVCOSEL)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Disable PLLFRACN . */ + __HAL_RCC_PLLFRACN_DISABLE(); + + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + + /* Select PLL1 input reference frequency range: VCI */ + __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; + + /* Select PLL1 output frequency range : VCO */ + __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + + /* Enable PLL1Q Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* Enable PLL1R Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + + /* Enable PLL1FRACN . */ + __HAL_RCC_PLLFRACN_ENABLE(); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp1_pllckcfg = RCC->PLLCKSELR; + temp2_pllckcfg = RCC->PLL1DIVR; + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) + { + return HAL_ERROR; + } + else + { + /* Check if only fractional part needs to be updated */ + temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); + if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + /* Disable PLL1FRACEN */ + __HAL_RCC_PLLFRACN_DISABLE(); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) + { + } + /* Configure PLL1 PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + /* Enable PLL1FRACEN to latch new value. */ + __HAL_RCC_PLLFRACN_ENABLE(); + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency: FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Core Clock Frequency + * and updated by HAL_InitTick() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after start-up delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * D1CPRE[3:0] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + HAL_StatusTypeDef halstatus; + uint32_t tickstart; + uint32_t common_system_clock; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + + } + + /* Increasing the BUS frequency divider */ + /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + { +#if defined (RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#else + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { +#if defined (RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif + } + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { +#if defined(RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif + } + + /*-------------------------- D3PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#endif + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { +#if defined (RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#else + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif + } + + /*------------------------- SYSCLK Configuration -------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); +#if defined(RCC_D1CFGR_D1CPRE) + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); +#else + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); +#endif + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + { + return HAL_ERROR; + } + } + /* CSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + /* Decreasing the BUS frequency divider */ + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { +#if defined(RCC_D1CFGR_HPRE) + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#else + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + { + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } +#endif + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + { +#if defined(RCC_D1CFGR_D1PPRE) + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#else + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } +#endif + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { +#if defined(RCC_D2CFGR_D2PPRE1) + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } +#endif + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { +#if defined (RCC_D2CFGR_D2PPRE2) + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } +#endif + } + + /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + { +#if defined(RCC_D3CFGR_D3PPRE) + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#else + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } +#endif + } + + /* Update the SystemCoreClock global variable */ +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + /* Configure the source of time base considering new system clocks settings*/ + halstatus = HAL_InitTick(uwTickPrio); + + return halstatus; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx: specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLL1QCLK: PLL1Q clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: PLL1P clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_CSICLK: CSI clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_LSICLK: LSI clock selected as MCO2 source + * @param RCC_MCODiv: specifies the MCOx pre-scaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1 up to RCC_MCODIV_15 : divider applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[3:0] bits then Select MCO1 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[3:0] bits then Select MCO2 clock source and pre-scaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 7U))); + } +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M NMI (Non-Mask-able Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSHSEON) ; +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSHSEON); +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(*) + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) CSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSI_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in stm32h7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baud rate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue; + float_t fracn1, pllvco; + uint32_t sysclockfreq; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + sysclockfreq = (uint32_t) HSI_VALUE; + } + + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; + pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; + sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); + } + else + { + sysclockfreq = 0U; + } + break; + + default: + sysclockfreq = CSI_VALUE; + break; + } + + return sysclockfreq; +} + + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return SystemD2Clock; +} + + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ +#if defined (RCC_D2CFGR_D2PPRE1) + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); +#else + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); +#endif +} + + +/** + * @brief Returns the D2 PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +#if defined(RCC_D2CFGR_D2PPRE2) + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); +#else + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); +#endif +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; + + /* Get the HSE configuration -----------------------------------------------*/ +#if defined(RCC_CR_HSEEXT) + if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#else + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } +#endif /* RCC_CR_HSEEXT */ + + /* Get the CSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_CSION) == RCC_CR_CSION) + { + RCC_OscInitStruct->CSIState = RCC_CSI_ON; + } + else + { + RCC_OscInitStruct->CSIState = RCC_CSI_OFF; + } + +#if defined(RCC_VER_X) + if (HAL_GetREVID() <= REV_ID_Y) + { + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos); + } + else + { + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + } +#else + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); +#endif /*RCC_VER_X*/ + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + +#if defined(RCC_VER_X) + if (HAL_GetREVID() <= REV_ID_Y) + { + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos); + } + else + { + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + } +#else + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); +#endif /*RCC_VER_X*/ + + /* Get the LSE configuration -----------------------------------------------*/ +#if defined(RCC_BDCR_LSEEXT) + if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } +#else + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } +#endif /* RCC_BDCR_LSEEXT */ + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the HSI48 configuration ---------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + } + else + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE)); + RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos); + RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos)); +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency: Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + +#if defined(RCC_D1CFGR_D1CPRE) + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE); + + /* Get the D1HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE); + + /* Get the APB3 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE); +#else + /* Get the SYSCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE); + + /* Get the D1HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE); + + /* Get the APB3 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2); + + /* Get the APB4 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE); +#endif + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c new file mode 100644 index 0000000..b771887 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -0,0 +1,3935 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_defines RCCEx Private Defines + * @{ + */ +#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ +#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ + +#define DIVIDER_P_UPDATE 0U +#define DIVIDER_Q_UPDATE 1U +#define DIVIDER_R_UPDATE 2U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123, + * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, + * SAI4A*, SAI4B*, SPI6, RTC). + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * (*) : Available on some STM32H7 lines only. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /*---------------------------- SPDIFRX configuration -------------------------------*/ + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + + switch (PeriphClkInit->SpdifrxClockSelection) + { + case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ + /* Enable PLL1Q Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_HSI: + /* Internal OSC clock is used as source of SPDIFRX clock*/ + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPDIFRX clock*/ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SAI1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + switch (PeriphClkInit->Sai1ClockSelection) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PIN: + /* External clock is used as source of SAI1 clock*/ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(SAI3) + /*---------------------------- SAI2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) + { + switch (PeriphClkInit->Sai23ClockSelection) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PIN: + /* External clock is used as source of SAI2/3 clock*/ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2/3 clock*/ + __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + /*---------------------------- SAI2A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) + { + switch (PeriphClkInit->Sai2AClockSelection) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ + /* Enable SAI2A Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PIN: + /* External clock is used as source of SAI2A clock*/ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2A clock*/ + __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2A*/ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) + + /*---------------------------- SAI2B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) + { + switch (PeriphClkInit->Sai2BClockSelection) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PIN: + /* External clock is used as source of SAI2B clock*/ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2B clock*/ + __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2B*/ + +#if defined(SAI4) + /*---------------------------- SAI4A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) + { + switch (PeriphClkInit->Sai4AClockSelection) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4A clock */ + /* SAI4A clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4A clock*/ + __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + /*---------------------------- SAI4B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) + { + switch (PeriphClkInit->Sai4BClockSelection) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4B clock */ + /* SAI4B clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4B clock*/ + __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI4*/ + +#if defined(QUADSPI) + /*---------------------------- QSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) + { + switch (PeriphClkInit->QspiClockSelection) + { + case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ + /* Enable QSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_QSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_D1HCLK: + /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of QSPI clock*/ + __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /*---------------------------- OCTOSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + switch (PeriphClkInit->OspiClockSelection) + { + case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ + /* Enable OSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_OSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_HCLK: + /* HCLK clock selected as OSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of OSPI clock*/ + __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*OCTOSPI*/ + + /*---------------------------- SPI1/2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) + { + switch (PeriphClkInit->Spi123ClockSelection) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ + /* Enable SPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PIN: + /* External clock is used as source of SPI1/2/3 clock*/ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI1/2/3 clock*/ + __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI4/5 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) + { + switch (PeriphClkInit->Spi45ClockSelection) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for SPI4/5 */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI4/5 clock*/ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI4/5 clock*/ + __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI6 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + { + switch (PeriphClkInit->Spi6ClockSelection) + { + case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI6 clock source configuration done later after clock selection check */ + break; + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI6 clock*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: + /* 2S_CKIN is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#endif + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI6 clock*/ + __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(DSI) + /*---------------------------- DSI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + switch (PeriphClkInit->DsiClockSelection) + { + + case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* DSI clock source configuration done later after clock selection check */ + break; + + case RCC_DSICLKSOURCE_PHY: + /* PHY is used as clock source for DSI*/ + /* DSI clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of DSI clock*/ + __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*DSI*/ + +#if defined(FDCAN1) || defined(FDCAN2) + /*---------------------------- FDCAN configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + switch (PeriphClkInit->FdcanClockSelection) + { + case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ + /* Enable FDCAN Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_HSE: + /* HSE is used as clock source for FDCAN*/ + /* FDCAN clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FDCAN clock*/ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*FDCAN1 || FDCAN2*/ + + /*---------------------------- FMC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + { + switch (PeriphClkInit->FmcClockSelection) + { + case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ + /* Enable FMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* FMC clock source configuration done later after clock selection check */ + break; + + + case RCC_FMCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_HCLK: + /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FMC clock*/ + __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- RTC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg; + } + + /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ + if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*-------------------------- USART1/6 configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) + { + switch (PeriphClkInit->Usart16ClockSelection) + { + case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART1/6 clock */ + __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) + { + switch (PeriphClkInit->Usart234578ClockSelection) + { + case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART2/3/4/5/7/8 clock */ + __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- LPUART1 Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + switch (PeriphClkInit->Lpuart1ClockSelection) + { + case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_LSE: + /* LSE, oscillator is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPUART1 clock */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + switch (PeriphClkInit->Lptim1ClockSelection) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM1 clock*/ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) + { + switch (PeriphClkInit->Lptim2ClockSelection) + { + case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM2CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM2 clock*/ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM345 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) + { + switch (PeriphClkInit->Lptim345ClockSelection) + { + + case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM345CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM3/4/5 clock */ + __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ +#if defined(I2C5) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); + + if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); + + } +#else + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); + + if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); + + } +#endif /* I2C5 */ + + /*------------------------------ I2C4 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + + } + + /*---------------------------- ADC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + switch (PeriphClkInit->AdcClockSelection) + { + + case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ + /* ADC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of ADC clock*/ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ USB Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + + switch (PeriphClkInit->UsbClockSelection) + { + case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ + /* Enable USB Clock output generated form System USB . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ + + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of USB clock */ + /* USB clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USB clock*/ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------------- SDMMC Configuration ------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); + + switch (PeriphClkInit->SdmmcClockSelection) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ + /* Enable SDMMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SDMMC clock*/ + __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(LTDC) + /*-------------------------------------- LTDC Configuration -----------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* LTDC */ + + /*------------------------------ RNG Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + { + + switch (PeriphClkInit->RngClockSelection) + { + case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ + /* Enable RNG Clock output generated form System RNG . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of RNG clock */ + /* RNG clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of RNG clock*/ + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------ SWPMI1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); + + /* Configure the SWPMI1 interface clock source */ + __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); + } +#if defined(HRTIM1) + /*------------------------------ HRTIM1 clock Configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); + + /* Configure the HRTIM1 clock source */ + __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); + } +#endif /*HRTIM1*/ + /*------------------------------ DFSDM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + +#if defined(DFSDM2_BASE) + /*------------------------------ DFSDM2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM2 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } +#endif /* DFSDM2 */ + + /*------------------------------------ TIM configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*------------------------------------ CKPER configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + { + /* Check the parameters */ + assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); + + /* Configure the CKPER clock source */ + __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); + } + + /*------------------------------ CEC Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC interface clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*---------------------------- PLL2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*---------------------------- PLL3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + if (status == HAL_OK) + { + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks : + * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123, + * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC. + * SAI4A*, SAI4B*, SPI6, RTC, TIM). + * @retval None + * + * (*) : Available on some STM32H7 lines only. + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = + RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | + RCC_PERIPHCLK_CKPER; + +#if defined(I2C5) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; +#else + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; +#endif /*I2C5*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B; +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI3) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23; +#endif /* SAI3 */ +#if defined(SAI4) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A; + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; +#endif /* SAI4 */ +#if defined(DFSDM2_BASE) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2; +#endif /* DFSDM2 */ +#if defined(QUADSPI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI; +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; +#endif /* OCTOSPI1 || OCTOSPI2 */ +#if defined(HRTIM1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; +#endif /* HRTIM1 */ +#if defined(LTDC) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; +#endif /* LTDC */ +#if defined(DSI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI; +#endif /* DSI */ + + /* Get the PLL3 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); + PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos); + PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos); + + /* Get the PLL2 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); + PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos); + PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos); + + /* Get the USART1 configuration --------------------------------------------*/ + PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE(); + /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ + PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(I2C5) + /* Get the I2C1/2/3/5 clock source -----------------------------------------*/ + PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#else + /* Get the I2C1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#endif /*I2C5*/ + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ + PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE(); + /* Get the SAI1 clock source -----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#if defined(SAI3) + /* Get the SAI2/3 clock source ---------------------------------------------*/ + PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE(); +#endif /*SAI3*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL_0) + /* Get the SAI2A clock source ---------------------------------------------*/ + PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE(); +#endif /*SAI2A*/ +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + /* Get the SAI2B clock source ---------------------------------------------*/ + PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE(); +#endif /*SAI2B*/ +#if defined(SAI4) + /* Get the SAI4A clock source ----------------------------------------------*/ + PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE(); + /* Get the SAI4B clock source ----------------------------------------------*/ + PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE(); +#endif /*SAI4*/ + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USB clock source ------------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); + /* Get the SDMMC clock source ----------------------------------------------*/ + PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#if defined(HRTIM1) + /* Get the HRTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); +#endif /* HRTIM1 */ + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + /* Get the SWPMI1 clock source ---------------------------------------------*/ + PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); + /* Get the DFSDM1 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); +#if defined(DFSDM2_BASE) + /* Get the DFSDM2 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); +#endif /* DFSDM2 */ + /* Get the SPDIFRX clock source --------------------------------------------*/ + PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + /* Get the SPI1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE(); + /* Get the SPI4/5 clock source ---------------------------------------------*/ + PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE(); + /* Get the SPI6 clock source -----------------------------------------------*/ + PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); + /* Get the FDCAN clock source ----------------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + /* Get the FMC clock source ------------------------------------------------*/ + PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); +#if defined(QUADSPI) + /* Get the QSPI clock source -----------------------------------------------*/ + PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /* Get the OSPI clock source -----------------------------------------------*/ + PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 || OCTOSPI2 */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /*DSI*/ + + /* Get the CKPER clock source ----------------------------------------------*/ + PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk: Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*) + * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock + * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock + * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock + * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock + * @retval Frequency in KHz + * + * (*) : Available on some STM32H7 lines only. + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) +{ + PLL1_ClocksTypeDef pll1_clocks; + PLL2_ClocksTypeDef pll2_clocks; + PLL3_ClocksTypeDef pll3_clocks; + + /* This variable is used to store the clock frequency (value in Hz) */ + uint32_t frequency; + /* This variable is used to store the SAI and CKP clock source */ + uint32_t saiclocksource; + uint32_t ckpclocksource; + uint32_t srcclk; + + if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + + saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + +#if defined(SAI3) + else if (PeriphClk == RCC_PERIPHCLK_SAI23) + { + + saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + + else if (PeriphClk == RCC_PERIPHCLK_SAI2A) + { + saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + + } +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + else if (PeriphClk == RCC_PERIPHCLK_SAI2B) + { + + saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + break; + } + + case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif + +#if defined(SAI4) + else if (PeriphClk == RCC_PERIPHCLK_SAI4A) + { + + saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } + + else if (PeriphClk == RCC_PERIPHCLK_SAI4B) + { + + saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif /*SAI4*/ + else if (PeriphClk == RCC_PERIPHCLK_SPI123) + { + /* Get SPI1/2/3 clock source */ + srcclk = __HAL_RCC_GET_SPI123_SOURCE(); + + switch (srcclk) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI45) + { + /* Get SPI45 clock source */ + srcclk = __HAL_RCC_GET_SPI45_SOURCE(); + switch (srcclk) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + break; + } + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADC) + { + /* Get ADC clock source */ + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + switch (srcclk) + { + case RCC_ADCCLKSOURCE_PLL2: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_ADCCLKSOURCE_PLL3: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_ADCCLKSOURCE_CLKP: + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + /* Get SDMMC clock source */ + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); + + switch (srcclk) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI6) + { + /* Get SPI6 clock source */ + srcclk = __HAL_RCC_GET_SPI6_SOURCE(); + + switch (srcclk) + { + case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ + { + frequency = HAL_RCCEx_GetD3PCLK1Freq(); + break; + } + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#endif /* RCC_SPI6CLKSOURCE_PIN */ + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN) + { + /* Get FDCAN clock source */ + srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); + + switch (srcclk) + { + case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else + { + frequency = 0; + } + + return frequency; +} + + +/** + * @brief Returns the D1PCLK1 frequency + * @note Each time D1PCLK1 changes, this function must be called to update the + * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D1PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) +{ +#if defined(RCC_D1CFGR_D1PPRE) + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); +#endif +} + +/** + * @brief Returns the D3PCLK1 frequency + * @note Each time D3PCLK1 changes, this function must be called to update the + * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D3PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) +{ +#if defined(RCC_D3CFGR_D3PPRE) + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); +#endif +} +/** +* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency + * @note The PLL2 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL2CLK changes, this function must be called to update the + * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL2_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) +{ + uint32_t pllsource, pll2m, pll2fracen, hsivalue; + float_t fracn2, pll2vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N + PLL2xCLK = PLL2_VCO / PLL2x + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); + pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; + fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); + + if (pll2m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + else + { + pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + } + PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; + PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; + PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; + } + else + { + PLL2_Clocks->PLL2_P_Frequency = 0U; + PLL2_Clocks->PLL2_Q_Frequency = 0U; + PLL2_Clocks->PLL2_R_Frequency = 0U; + } +} + +/** +* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency + * @note The PLL3 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL3CLK changes, this function must be called to update the + * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL3_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) +{ + uint32_t pllsource, pll3m, pll3fracen, hsivalue; + float_t fracn3, pll3vco; + + /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N + PLL3xCLK = PLL3_VCO / PLLxR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; + pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; + fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); + + if (pll3m != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + else + { + pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + } + PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; + PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; + PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; + } + else + { + PLL3_Clocks->PLL3_P_Frequency = 0U; + PLL3_Clocks->PLL3_Q_Frequency = 0U; + PLL3_Clocks->PLL3_R_Frequency = 0U; + } + +} + +/** +* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency + * @note The PLL1 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL1CLK changes, this function must be called to update the + * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL1_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) +{ + uint32_t pllsource, pll1m, pll1fracen, hsivalue; + float_t fracn1, pll1vco; + + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); + pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pll1m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + + PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; + PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; + PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; + } + else + { + PLL1_Clocks->PLL1_P_Frequency = 0U; + PLL1_Clocks->PLL1_Q_Frequency = 0U; + PLL1_Clocks->PLL1_R_Frequency = 0U; + } + +} + +/** + * @brief Returns the main System frequency + * @note Each time System clock changes, this function must be called to update the + * right core clock value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCCEx_GetD1SysClockFreq(void) +{ + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return common_system_clock; +} +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions + * @brief Extended Peripheral Control functions + * @{ + */ +/** + * @brief Enables the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disables the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + /* Disable LSE CSS IT if any */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 18 */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); +#else + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +#endif /* DUAL_CORE && CORE_CM4 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock + * @param WakeUpClk: Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the oscillator Kernel clock source for wakeup from Stop + * @param WakeUpClk: Kernel Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection + * @retval None + */ +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable COREx boot independently of CMx_B option byte value + * @param RCC_BootCx: Boot Core to be enabled + * This parameter can be one of the following values: + * @arg RCC_BOOT_C1: CM7 core selection + * @arg RCC_BOOT_C2: CM4 core selection + * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY + * + * @retval None + */ +void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx) +{ + assert_param(IS_RCC_BOOT_CORE(RCC_BootCx)); + SET_BIT(RCC->GCR, RCC_BootCx) ; +} + +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** + * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @arg RCC_WWDG2: WWDG2 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} + +#else +#if defined(RCC_GCR_WW1RSC) +/** + * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} +#endif +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the up-counting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2)) + { + /* Use Rev.Y value of USB2 */ + value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity); + } + else + { + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + } + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the time-out +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg @ref RCC_CRS_TIMEOUT +* @arg @ref RCC_CRS_SYNCOK +* @arg @ref RCC_CRS_SYNCWARN +* @arg @ref RCC_CRS_SYNCERR +* @arg @ref RCC_CRS_SYNCMISS +* @arg @ref RCC_CRS_TRIMOVF +*/ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or time-out detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } + while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCCEx_Private_functions RCCEx Private Functions + * @{ + */ +/** + * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL2 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +{ + + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M)); + assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N)); + assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P)); + assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R)); + assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q)); + assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); + assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); + + /* Check that PLL2 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL2 multiplication and division factors. */ + __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, + pll2->PLL2N, + pll2->PLL2P, + pll2->PLL2Q, + pll2->PLL2R); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; + + /* Select PLL2 output frequency range : VCO */ + __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; + + /* Disable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_DISABLE(); + + /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); + + /* Enable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_ENABLE(); + + /* Enable the PLL2 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); + } + else + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); + } + + /* Enable PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + + +/** + * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL3 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M)); + assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N)); + assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P)); + assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R)); + assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q)); + assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); + assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); + + /* Check that PLL3 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL3. */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the PLL3 multiplication and division factors. */ + __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, + pll3->PLL3N, + pll3->PLL3P, + pll3->PLL3Q, + pll3->PLL3R); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; + + /* Select PLL3 output frequency range : VCO */ + __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; + + /* Disable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_DISABLE(); + + /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); + + /* Enable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_ENABLE(); + + /* Enable the PLL3 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); + } + else + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); + } + + /* Enable PLL3. */ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + + + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c new file mode 100644 index 0000000..ee80dac --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c @@ -0,0 +1,1321 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_sdram.c + * @author MCD Application Team + * @brief SDRAM HAL module driver. + * This file provides a generic firmware to drive SDRAM memories mounted + * as external device. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SDRAM memories. It uses the FMC layer functions to interface + with SDRAM devices. + The following sequence should be followed to configure the FMC to interface + with SDRAM memories: + + (#) Declare a SDRAM_HandleTypeDef handle structure, for example: + SDRAM_HandleTypeDef hsdram + + (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SDRAM device + + (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: + FMC_SDRAM_TimingTypeDef Timing; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() + (##) Control register configuration using the FMC SDRAM interface function + FMC_SDRAM_Init() + (##) Timing register configuration using the FMC SDRAM interface function + FMC_SDRAM_Timing_Init() + (##) Program the SDRAM external device by applying its initialization sequence + according to the device plugged in your hardware. This step is mandatory + for accessing the SDRAM device. + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the SDRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access + (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ + HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or + the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM + device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef + structure. + + (#) You can continuously monitor the SDRAM device HAL state by calling the function + HAL_SDRAM_GetState() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init + and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit + or HAL_SDRAM_Init function. + + When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + +/** @defgroup SDRAM SDRAM + * @brief SDRAM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ +static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma); +static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma); +static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### SDRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Timing Pointer to SDRAM control timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + /* Check the SDRAM handle parameter */ + if (hsdram == NULL) + { + return HAL_ERROR; + } + + if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if (hsdram->MspInitCallback == NULL) + { + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + } + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Init the low level hardware */ + hsdram->MspInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspInit(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Initialize SDRAM control Interface */ + (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + + /* Initialize SDRAM timing Interface */ + (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + + /* Enable FMC Peripheral */ + __FMC_ENABLE(); + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Perform the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) +{ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if (hsdram->MspDeInitCallback == NULL) + { + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + } + + /* DeInit the low level hardware */ + hsdram->MspDeInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspDeInit(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + + /* Configure the SDRAM registers with their reset values */ + (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + + /* Reset the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief SDRAM MSP Init. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SDRAM MSP DeInit. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function handles SDRAM refresh error interrupt request. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) +{ + /* Check SDRAM interrupt Rising edge flag */ + if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) + { + /* SDRAM refresh error interrupt callback */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->RefreshErrorCallback(hsdram); +#else + HAL_SDRAM_RefreshErrorCallback(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + + /* Clear SDRAM refresh error interrupt pending bit */ + __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); + } +} + +/** + * @brief SDRAM Refresh error callback. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hmdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hmdma DMA handle + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SDRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint8_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint8_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 8-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint8_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *(__IO uint8_t *)pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 16-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + pSdramAddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 16-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psdramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *psdramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psdramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 32-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + uint32_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint32_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 32-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + status = HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SDRAM_STATE_READY) + { + hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt; + } + else + { + hsdram->hmdma->XferCpltCallback = SDRAM_DMACpltProt; + } + hsdram->hmdma->XferErrorCallback = SDRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + status = HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt; + hsdram->hmdma->XferErrorCallback = SDRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SDRAM Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} + +/** + * @brief Unregister a User SDRAM Callback + * SDRAM Callback is redirected to the weak (surcharged) predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} + +/** + * @brief Register a User SDRAM Callback for DMA transfers + * To be used instead of the weak (surcharged) predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = pCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Enable write protection */ + (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) +{ + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Disable write protection */ + (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Sends Command to the SDRAM bank. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Command SDRAM command structure + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout) +{ + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + + /* Update the SDRAM controller state state */ + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Programs the SDRAM Memory Refresh rate. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param RefreshRate The SDRAM refresh rate value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param AutoRefreshNumber The SDRAM auto Refresh number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Set the Auto-Refresh number */ + (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Returns the SDRAM memory current mode. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval The SDRAM memory mode. + */ +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) +{ + /* Return the SDRAM memory current mode */ + return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SDRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SDRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SDRAM state. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL state + */ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) +{ + return hsdram->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ +/** + * @brief MDMA SDRAM process complete callback. + * @param hmdma : MDMA handle + * @retval None + */ +static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hmdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hmdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief MDMA SRAM process complete callback. + * @param hmdma : MDMA handle + * @retval None + */ +static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hmdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hmdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief MDMA SDRAM error callback. + * @param hmdma : MDMA handle + * @retval None + */ +static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); + + /* Disable the MDMA channel */ + __HAL_MDMA_DISABLE(hmdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_ERROR; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferErrorCallback(hmdma); +#else + HAL_SDRAM_DMA_XferErrorCallback(hmdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c new file mode 100644 index 0000000..eab578f --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -0,0 +1,7908 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + case TIM_CLOCKSOURCE_ITR4: + case TIM_CLOCKSOURCE_ITR5: + case TIM_CLOCKSOURCE_ITR6: + case TIM_CLOCKSOURCE_ITR7: + case TIM_CLOCKSOURCE_ITR8: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + case TIM_TS_ITR4: + case TIM_TS_ITR5: + case TIM_TS_ITR6: + case TIM_TS_ITR7: + case TIM_TS_ITR8: + case TIM_TS_ITR9: + case TIM_TS_ITR10: + case TIM_TS_ITR11: + case TIM_TS_ITR12: + case TIM_TS_ITR13: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_ITR4: Internal Trigger 4 (*) + * @arg TIM_TS_ITR5: Internal Trigger 5 + * @arg TIM_TS_ITR6: Internal Trigger 6 + * @arg TIM_TS_ITR7: Internal Trigger 7 + * @arg TIM_TS_ITR8: Internal Trigger 8 (*) + * @arg TIM_TS_ITR9: Internal Trigger 9 (*) + * @arg TIM_TS_ITR10: Internal Trigger 10 (*) + * @arg TIM_TS_ITR11: Internal Trigger 11 (*) + * @arg TIM_TS_ITR12: Internal Trigger 12 (*) + * @arg TIM_TS_ITR13: Internal Trigger 13 (*) + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * + * (*) Value not defined in all devices. + * + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c new file mode 100644 index 0000000..ad4cbee --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c @@ -0,0 +1,2947 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#if defined(TIM_BDTR_BKBID) +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +#endif /* TIM_BDTR_BKBID */ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR12: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR13: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR2: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_ITR2: Internal trigger 12 selected (*) + * @arg TIM_TS_ITR3: Internal trigger 13 selected (*) + * @arg TIM_TS_NONE: No trigger is needed + * + * (*) Value not defined in all devices. + * + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || + (InputTrigger == TIM_TS_ITR12) || (InputTrigger == TIM_TS_ITR13)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + +#if defined(TIM_BDTR_BKBID) + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Set BREAK AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + } + +#endif /* TIM_BDTR_BKBID */ + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); +#if defined(TIM_BDTR_BKBID) + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set BREAK2 AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } +#endif /* TIM_BDTR_BKBID */ + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + } + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM1_AF1_BKCMP1E; + bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM1_AF1_BKCMP2E; + bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BK0E; + bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} +#endif /*TIM_BREAK_INPUT_SUPPORT */ + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter is one of the following values: + * @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO + * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output + * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 + * + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output + * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_SAI1_FSA: TIM2_ETR is connected to SAI1 FS_A + * @arg TIM_TIM2_ETR_SAI1_FSB: TIM2_ETR is connected to SAI1 FS_B + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_ETR_GPIO: TIM3_ETR is connected to GPIO + * @arg TIM_TIM3_ETR_COMP1: TIM3_ETR is connected to COMP1 output + * + * For TIM5, the parameter is one of the following values: + * @arg TIM_TIM5_ETR_GPIO: TIM5_ETR is connected to GPIO + * @arg TIM_TIM5_ETR_SAI2_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI2_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * @arg TIM_TIM5_ETR_SAI4_FSA: TIM5_ETR is connected to SAI2 FS_A (*) + * @arg TIM_TIM5_ETR_SAI4_FSB: TIM5_ETR is connected to SAI2 FS_B (*) + * + * For TIM8, the parameter is one of the following values: + * @arg TIM_TIM8_ETR_GPIO: TIM8_ETR is connected to GPIO + * @arg TIM_TIM8_ETR_COMP1: TIM8_ETR is connected to COMP1 output + * @arg TIM_TIM8_ETR_COMP2: TIM8_ETR is connected to COMP2 output + * @arg TIM_TIM8_ETR_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1 + * @arg TIM_TIM8_ETR_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2 + * @arg TIM_TIM8_ETR_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3 + * @arg TIM_TIM8_ETR_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1 + * @arg TIM_TIM8_ETR_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2 + * @arg TIM_TIM8_ETR_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3 + * + * For TIM23, the parameter is one of the following values: (*) + * @arg TIM_TIM23_ETR_GPIO TIM23_ETR is connected to GPIO + * @arg TIM_TIM23_ETR_COMP1 TIM23_ETR is connected to COMP1 output + * @arg TIM_TIM23_ETR_COMP2 TIM23_ETR is connected to COMP2 output + * + * For TIM24, the parameter is one of the following values: (*) + * @arg TIM_TIM24_ETR_GPIO TIM24_ETR is connected to GPIO + * @arg TIM_TIM24_ETR_SAI4_FSA TIM24_ETR is connected to SAI4 FS_A + * @arg TIM_TIM24_ETR_SAI4_FSB TIM24_ETR is connected to SAI4 FS_B + * @arg TIM_TIM24_ETR_SAI1_FSA TIM24_ETR is connected to SAI1 FS_A + * @arg TIM_TIM24_ETR_SAI1_FSB TIM24_ETR is connected to SAI1 FS_B + * + * (*) Value not defined in all devices. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: + * For TIM1, the parameter is one of the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output + * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output + * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output + * @arg TIM_TIM3_TI1_COMP1_COMP2: TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output + * + * For TIM5, the parameter is one of the following values: + * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO + * @arg TIM_TIM5_TI1_CAN_TMP: TIM5 TI1 is connected to CAN TMP + * @arg TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP + * + * For TIM8, the parameter is one of the following values: + * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO + * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output + * + * For TIM12, the parameter can have the following values: (*) + * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO + * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS + * + * For TIM15, the parameter is one of the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1 + * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE + * @arg TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI + * @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2 + * @arg TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2 + * + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt + * + * For TIM17, the parameter can have the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*) + * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz + * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1 + * + * For TIM23, the parameter can have the following values: (*) + * @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO + * @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output + * @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output + * @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output + * + * For TIM24, the parameter can have the following values: (*) + * @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO + * @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP + * @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP + * @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC + * + * (*) Value not defined in all devices. \n + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_3: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); + break; + case TIM_CHANNEL_4: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BDTR_BKBID) + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* TIM_BDTR_BKBID */ + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_bdma.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_bdma.c new file mode 100644 index 0000000..4abaed3 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_bdma.c @@ -0,0 +1,344 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_bdma.c + * @author MCD Application Team + * @brief BDMA LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_bdma.h" +#include "stm32h7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (BDMA) || defined (BDMA1) || defined (BDMA2) + +/** @addtogroup BDMA_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup BDMA_LL_Private_Macros + * @{ + */ +#define IS_LL_BDMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_BDMA_MODE(__VALUE__) (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_BDMA_MODE_CIRCULAR)) + +#define IS_LL_BDMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT)) + +#define IS_LL_BDMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT)) + +#define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD)) + +#define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD)) + +#define IS_LL_BDMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#if defined(ADC3) +#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3) +#else +#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0) +#endif /* ADC3 */ + +#define IS_LL_BDMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_BDMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_BDMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH)) + +#define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == BDMA) && \ + (((CHANNEL) == LL_BDMA_CHANNEL_0) || \ + ((CHANNEL) == LL_BDMA_CHANNEL_1) || \ + ((CHANNEL) == LL_BDMA_CHANNEL_2) || \ + ((CHANNEL) == LL_BDMA_CHANNEL_3) || \ + ((CHANNEL) == LL_BDMA_CHANNEL_4) || \ + ((CHANNEL) == LL_BDMA_CHANNEL_5) || \ + ((CHANNEL) == LL_BDMA_CHANNEL_6) || \ + ((CHANNEL) == LL_BDMA_CHANNEL_7)))) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup BDMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup BDMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @arg @ref LL_BDMA_CHANNEL_ALL + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel) +{ + BDMA_Channel_TypeDef *tmp ; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters */ + assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel) || (Channel == LL_BDMA_CHANNEL_ALL)); + + if (Channel == LL_BDMA_CHANNEL_ALL) + { + if (BDMAx == BDMA) + { + /* Force reset of BDMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + + /* Release reset of BDMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + } + else + { + status = ERROR; + } + } + else + { + tmp = (BDMA_Channel_TypeDef *)(__LL_BDMA_GET_CHANNEL_INSTANCE(BDMAx, Channel)); + + /* Disable the selected DMAx_Channely */ + CLEAR_BIT(tmp->CCR, BDMA_CCR_EN); + + /* Reset DMAx_Channely control register */ + LL_BDMA_WriteReg(tmp, CCR, 0U); + + /* Reset DMAx_Channely remaining bytes register */ + LL_BDMA_WriteReg(tmp, CNDTR, 0U); + + /* Reset DMAx_Channely peripheral address register */ + LL_BDMA_WriteReg(tmp, CPAR, 0U); + + /* Reset DMAx_Channely memory 0 address register */ + LL_BDMA_WriteReg(tmp, CM0AR, 0U); + + /* Reset DMAx_Channely memory 1 address register */ + LL_BDMA_WriteReg(tmp, CM1AR, 0U); + + /* Reset Request register field for BDMAx Channel */ + LL_BDMA_SetPeriphRequest(BDMAx, Channel, LL_DMAMUX2_REQ_MEM2MEM); + + if (Channel == LL_BDMA_CHANNEL_0) + { + /* Reset interrupt pending bits for DMAx Channel0 */ + LL_BDMA_ClearFlag_GI0(BDMAx); + } + else if (Channel == LL_BDMA_CHANNEL_1) + { + /* Reset interrupt pending bits for DMAx Channel1 */ + LL_BDMA_ClearFlag_GI1(BDMAx); + } + else if (Channel == LL_BDMA_CHANNEL_2) + { + /* Reset interrupt pending bits for DMAx Channel2 */ + LL_BDMA_ClearFlag_GI2(BDMAx); + } + else if (Channel == LL_BDMA_CHANNEL_3) + { + /* Reset interrupt pending bits for DMAx Channel3 */ + LL_BDMA_ClearFlag_GI3(BDMAx); + } + else if (Channel == LL_BDMA_CHANNEL_4) + { + /* Reset interrupt pending bits for DMAx Channel4 */ + LL_BDMA_ClearFlag_GI4(BDMAx); + } + else if (Channel == LL_BDMA_CHANNEL_5) + { + /* Reset interrupt pending bits for DMAx Channel5 */ + LL_BDMA_ClearFlag_GI5(BDMAx); + } + + else if (Channel == LL_BDMA_CHANNEL_6) + { + /* Reset interrupt pending bits for DMAx Channel6 */ + LL_BDMA_ClearFlag_GI6(BDMAx); + } + else if (Channel == LL_BDMA_CHANNEL_7) + { + /* Reset interrupt pending bits for DMAx Channel7 */ + LL_BDMA_ClearFlag_GI7(BDMAx); + } + else + { + status = ERROR; + } + } + + return (uint32_t)status; +} + +/** + * @brief Initialize the BDMA registers according to the specified parameters in BDMA_InitStruct. + * @note To convert BDMAx_Channely Instance to BDMAx Instance and Channely, use helper macros : + * @arg @ref __LL_BDMA_GET_INSTANCE + * @arg @ref __LL_BDMA_GET_CHANNEL + * @param BDMAx BDMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_BDMA_CHANNEL_0 + * @arg @ref LL_BDMA_CHANNEL_1 + * @arg @ref LL_BDMA_CHANNEL_2 + * @arg @ref LL_BDMA_CHANNEL_3 + * @arg @ref LL_BDMA_CHANNEL_4 + * @arg @ref LL_BDMA_CHANNEL_5 + * @arg @ref LL_BDMA_CHANNEL_6 + * @arg @ref LL_BDMA_CHANNEL_7 + * @param BDMA_InitStruct pointer to a @ref LL_BDMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters */ + assert_param(IS_LL_BDMA_ALL_CHANNEL_INSTANCE(BDMAx, Channel)); + + /* Check the DMA parameters from BDMA_InitStruct */ + assert_param(IS_LL_BDMA_DIRECTION(BDMA_InitStruct->Direction)); + assert_param(IS_LL_BDMA_MODE(BDMA_InitStruct->Mode)); + assert_param(IS_LL_BDMA_PERIPHINCMODE(BDMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_BDMA_MEMORYINCMODE(BDMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_BDMA_PERIPHDATASIZE(BDMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_BDMA_MEMORYDATASIZE(BDMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData)); + assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest)); + assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority)); + + /*---------------------------- DMAx CCR Configuration ------------------------ + * Configure DMAx_Channely: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits + * - Mode: BDMA_CCR_CIRC bit + * - PeriphOrM2MSrcIncMode: BDMA_CCR_PINC bit + * - MemoryOrM2MDstIncMode: BDMA_CCR_MINC bit + * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits + * - Priority: BDMA_CCR_PL[1:0] bits + */ + LL_BDMA_ConfigTransfer(BDMAx, Channel, BDMA_InitStruct->Direction | \ + BDMA_InitStruct->Mode | \ + BDMA_InitStruct->PeriphOrM2MSrcIncMode | \ + BDMA_InitStruct->MemoryOrM2MDstIncMode | \ + BDMA_InitStruct->PeriphOrM2MSrcDataSize | \ + BDMA_InitStruct->MemoryOrM2MDstDataSize | \ + BDMA_InitStruct->Priority); + + /*-------------------------- DMAx CMAR Configuration ------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: BDMA_CMAR_MA[31:0] bits + */ + LL_BDMA_SetMemoryAddress(BDMAx, Channel, BDMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx CPAR Configuration ------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: BDMA_CPAR_PA[31:0] bits + */ + LL_BDMA_SetPeriphAddress(BDMAx, Channel, BDMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx CNDTR Configuration ----------------------- + * Configure the peripheral base address with parameter : + * - NbData: BDMA_CNDTR_NDT[15:0] bits + */ + LL_BDMA_SetDataLength(BDMAx, Channel, BDMA_InitStruct->NbData); + + /*--------------------------- DMAMUXx CCR Configuration ---------------------- + * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter : + * - PeriphRequest: BDMA_CxCR[7:0] bits + */ + LL_BDMA_SetPeriphRequest(BDMAx, Channel, BDMA_InitStruct->PeriphRequest); + + return (uint32_t)SUCCESS; +} + +/** + * @brief Set each @ref LL_BDMA_InitTypeDef field to default value. + * @param BDMA_InitStruct Pointer to a @ref LL_BDMA_InitTypeDef structure. + * @retval None + */ +void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct) +{ + /* Set BDMA_InitStruct fields to default values */ + BDMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + BDMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + BDMA_InitStruct->Direction = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY; + BDMA_InitStruct->Mode = LL_BDMA_MODE_NORMAL; + BDMA_InitStruct->PeriphOrM2MSrcIncMode = LL_BDMA_PERIPH_NOINCREMENT; + BDMA_InitStruct->MemoryOrM2MDstIncMode = LL_BDMA_MEMORY_NOINCREMENT; + BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE; + BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE; + BDMA_InitStruct->NbData = 0x00000000U; + BDMA_InitStruct->PeriphRequest = LL_DMAMUX2_REQ_MEM2MEM; + BDMA_InitStruct->Priority = LL_BDMA_PRIORITY_LOW; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* BDMA || BDMA1 || BDMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crc.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crc.c new file mode 100644 index 0000000..34f0dd1 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_crc.c @@ -0,0 +1,111 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_crc.c + * @author MCD Application Team + * @brief CRC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_crc.h" +#include "stm32h7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (CRC) + +/** @addtogroup CRC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize CRC registers (Registers restored to their default values). + * @param CRCx CRC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(CRCx)); + + if (CRCx == CRC) + { +#if defined(LL_AHB4_GRP1_PERIPH_CRC) + /* Force CRC reset */ + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_CRC); + + /* Release CRC reset */ + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_CRC); +#else + /* Force CRC reset */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC); + + /* Release CRC reset */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC); +#endif /*LL_AHB4_GRP1_PERIPH_CRC)*/ + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (CRC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c new file mode 100644 index 0000000..b7e32d2 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c @@ -0,0 +1,423 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_dma.c + * @author MCD Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_dma.h" +#include "stm32h7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @addtogroup DMA_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ + ((__VALUE__) == LL_DMA_MODE_PFCTRL)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#if defined(TIM24) +#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_TIM24_TRIG)) +#elif defined(ADC3) +#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_ADC3)) +#else +#define IS_LL_DMA_REQUEST(REQUEST) (((REQUEST) <= LL_DMAMUX1_REQ_USART10_TX)) +#endif /* TIM24 */ + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ + (((STREAM) == LL_DMA_STREAM_0) || \ + ((STREAM) == LL_DMA_STREAM_1) || \ + ((STREAM) == LL_DMA_STREAM_2) || \ + ((STREAM) == LL_DMA_STREAM_3) || \ + ((STREAM) == LL_DMA_STREAM_4) || \ + ((STREAM) == LL_DMA_STREAM_5) || \ + ((STREAM) == LL_DMA_STREAM_6) || \ + ((STREAM) == LL_DMA_STREAM_7) || \ + ((STREAM) == LL_DMA_STREAM_ALL))) || \ + (((INSTANCE) == DMA2) && \ + (((STREAM) == LL_DMA_STREAM_0) || \ + ((STREAM) == LL_DMA_STREAM_1) || \ + ((STREAM) == LL_DMA_STREAM_2) || \ + ((STREAM) == LL_DMA_STREAM_3) || \ + ((STREAM) == LL_DMA_STREAM_4) || \ + ((STREAM) == LL_DMA_STREAM_5) || \ + ((STREAM) == LL_DMA_STREAM_6) || \ + ((STREAM) == LL_DMA_STREAM_7) || \ + ((STREAM) == LL_DMA_STREAM_ALL)))) + +#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == LL_DMA_FIFOMODE_ENABLE)) + +#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ + ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ + ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ + ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) + +#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ + ((BURST) == LL_DMA_MBURST_INC4) || \ + ((BURST) == LL_DMA_MBURST_INC8) || \ + ((BURST) == LL_DMA_MBURST_INC16)) + +#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ + ((BURST) == LL_DMA_PBURST_INC4) || \ + ((BURST) == LL_DMA_PBURST_INC8) || \ + ((BURST) == LL_DMA_PBURST_INC16)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @arg @ref LL_DMA_STREAM_ALL + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) +{ + DMA_Stream_TypeDef *tmp; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Stream parameters */ + assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); + + if (Stream == LL_DMA_STREAM_ALL) + { + if (DMAx == DMA1) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + } + else if (DMAx == DMA2) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + } + else + { + status = ERROR; + } + } + else + { + /* Disable the selected Stream */ + LL_DMA_DisableStream(DMAx, Stream); + + /* Get the DMA Stream Instance */ + tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); + + /* Reset DMAx_Streamy configuration register */ + LL_DMA_WriteReg(tmp, CR, 0U); + + /* Reset DMAx_Streamy remaining bytes register */ + LL_DMA_WriteReg(tmp, NDTR, 0U); + + /* Reset DMAx_Streamy peripheral address register */ + LL_DMA_WriteReg(tmp, PAR, 0U); + + /* Reset DMAx_Streamy memory address register */ + LL_DMA_WriteReg(tmp, M0AR, 0U); + + /* Reset DMAx_Streamy memory address register */ + LL_DMA_WriteReg(tmp, M1AR, 0U); + + /* Reset DMAx_Streamy FIFO control register */ + LL_DMA_WriteReg(tmp, FCR, 0x00000021U); + + /* Reset Channel register field for DMAx Stream */ + LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM); + + if (Stream == LL_DMA_STREAM_0) + { + /* Reset the Stream0 pending flags */ + DMAx->LIFCR = 0x0000003FU; + } + else if (Stream == LL_DMA_STREAM_1) + { + /* Reset the Stream1 pending flags */ + DMAx->LIFCR = 0x00000F40U; + } + else if (Stream == LL_DMA_STREAM_2) + { + /* Reset the Stream2 pending flags */ + DMAx->LIFCR = 0x003F0000U; + } + else if (Stream == LL_DMA_STREAM_3) + { + /* Reset the Stream3 pending flags */ + DMAx->LIFCR = 0x0F400000U; + } + else if (Stream == LL_DMA_STREAM_4) + { + /* Reset the Stream4 pending flags */ + DMAx->HIFCR = 0x0000003FU; + } + else if (Stream == LL_DMA_STREAM_5) + { + /* Reset the Stream5 pending flags */ + DMAx->HIFCR = 0x00000F40U; + } + else if (Stream == LL_DMA_STREAM_6) + { + /* Reset the Stream6 pending flags */ + DMAx->HIFCR = 0x003F0000U; + } + else if (Stream == LL_DMA_STREAM_7) + { + /* Reset the Stream7 pending flags */ + DMAx->HIFCR = 0x0F400000U; + } + else + { + status = ERROR; + } + } + + return (uint32_t)status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_STREAM + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Stream parameters */ + assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); + + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + { + assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); + assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); + assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); + } + + /*---------------------------- DMAx SxCR Configuration ------------------------ + * Configure DMAx_Streamy: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_SxCR_DIR[1:0] bits + * - Mode: DMA_SxCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits + * - Priority: DMA_SxCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority + ); + + if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) + { + /*---------------------------- DMAx SxFCR Configuration ------------------------ + * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : + * - FIFOMode: DMA_SxFCR_DMDIS bit + * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits + */ + LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); + + /*---------------------------- DMAx SxCR Configuration -------------------------- + * Configure DMAx_Streamy: memory burst transfer with parameters : + * - MemBurst: DMA_SxCR_MBURST[1:0] bits + */ + LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst); + + /*---------------------------- DMAx SxCR Configuration -------------------------- + * Configure DMAx_Streamy: peripheral burst transfer with parameters : + * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits + */ + LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst); + } + + /*-------------------------- DMAx SxM0AR Configuration -------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx SxPAR Configuration --------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx SxNDTR Configuration ------------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_SxNDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); + + /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- + * Configure the peripheral base address with parameter : + * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest); + + return (uint32_t)SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = 0x00000000U; + DMA_InitStruct->PeriphRequest = LL_DMAMUX1_REQ_MEM2MEM; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; + DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; + DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; + DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; + DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c new file mode 100644 index 0000000..5e3a198 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_exti.c @@ -0,0 +1,456 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) +#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) +#define IS_LL_EXTI_LINE_64_95(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_EXTI_DeInit(void) +{ + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR1, 0x00000000U); + LL_EXTI_WriteReg(RTSR2, 0x00000000U); + LL_EXTI_WriteReg(RTSR3, 0x00000000U); + + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR1, 0x00000000U); + LL_EXTI_WriteReg(FTSR2, 0x00000000U); + LL_EXTI_WriteReg(FTSR3, 0x00000000U); + + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER1, 0x00000000U); + LL_EXTI_WriteReg(SWIER2, 0x00000000U); + LL_EXTI_WriteReg(SWIER3, 0x00000000U); + + /* D3 Pending register set to default reset values */ + LL_EXTI_WriteReg(D3PMR1, 0x00000000U); + LL_EXTI_WriteReg(D3PMR2, 0x00000000U); + LL_EXTI_WriteReg(D3PMR3, 0x00000000U); + + /* D3 Pending clear selection register low to default reset values */ + LL_EXTI_WriteReg(D3PCR1L, 0x00000000U); + LL_EXTI_WriteReg(D3PCR2L, 0x00000000U); + LL_EXTI_WriteReg(D3PCR3L, 0x00000000U); + + /* D3 Pending clear selection register high to default reset values */ + LL_EXTI_WriteReg(D3PCR1H, 0x00000000U); + LL_EXTI_WriteReg(D3PCR2H, 0x00000000U); + LL_EXTI_WriteReg(D3PCR3H, 0x00000000U); + + /* Interrupt mask register reset */ + LL_EXTI_WriteReg(IMR1, 0x00000000U); + LL_EXTI_WriteReg(IMR2, 0x00000000U); + LL_EXTI_WriteReg(IMR3, 0x00000000U); + + /* Event mask register reset */ + LL_EXTI_WriteReg(EMR1, 0x00000000U); + LL_EXTI_WriteReg(EMR2, 0x00000000U); + LL_EXTI_WriteReg(EMR3, 0x00000000U); + + /* Clear Pending requests */ + LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk); + LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk); + LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk); + +#if defined(DUAL_CORE) + /* Interrupt mask register set to default reset values for Core 2 (Coretx-M4)*/ + LL_EXTI_WriteReg(C2IMR1, 0x00000000U); + LL_EXTI_WriteReg(C2IMR2, 0x00000000U); + LL_EXTI_WriteReg(C2IMR3, 0x00000000U); + + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(C2EMR1, 0x00000000U); + LL_EXTI_WriteReg(C2EMR2, 0x00000000U); + LL_EXTI_WriteReg(C2EMR3, 0x00000000U); + + /* Clear Pending requests */ + LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk); + LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk); + LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk); + +#endif /* DUAL_CORE*/ + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); + assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT) + { + /* Enable IT on provided Lines for Cortex-M7*/ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + } + else + { + /* Disable IT on provided Lines for Cortex-M7*/ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + } + + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT) + { + /* Enable event on provided Lines for Cortex-M7 */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + else + { + /* Disable event on provided Lines for Cortex-M7 */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } +#if defined(DUAL_CORE) + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT) + { + /* Enable IT on provided Lines for Cortex-M4 */ + LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31); + } + else + { + /* Disable IT on provided Lines for Cortex-M4*/ + LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + } + + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT) + { + /* Enable event on provided Lines for Cortex-M4 */ + LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + else + { + /* Disable event on provided Lines for Cortex-M4*/ + LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } +#endif /* DUAL_CORE */ + + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + /* Configure EXTI Lines in range from 32 to 63 */ + if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE) + { + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT) + { + /* Enable IT on provided Lines for Cortex-M7*/ + LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); + } + else + { + /* Disable IT on provided Lines for Cortex-M7*/ + LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); + } + + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT) + { + /* Enable event on provided Lines for Cortex-M7 */ + LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); + } + else + { + /* Disable event on provided Lines for Cortex-M7 */ + LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + } +#if defined(DUAL_CORE) + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT) + { + /* Enable IT on provided Lines for Cortex-M4 */ + LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63); + } + else + { + /* Disable IT on provided Lines for Cortex-M4 */ + LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63); + } + + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT) + { + /* Enable event on provided Lines for Cortex-M4 */ + LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); + } + else + { + /* Disable event on provided Lines for Cortex-M4 */ + LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + } +#endif /* DUAL_CORE */ + + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); + LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); + break; + default: + status = ERROR; + break; + } + } + } + /* Configure EXTI Lines in range from 64 to 95 */ + if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE) + { + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT) + { + /* Enable IT on provided Lines for Cortex-M7*/ + LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95); + } + else + { + /* Disable IT on provided Lines for Cortex-M7*/ + LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); + } + + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT) + { + /* Enable event on provided Lines for Cortex-M7 */ + LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95); + } + else + { + /* Disable event on provided Lines for Cortex-M7 */ + LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); + } + +#if defined(DUAL_CORE) + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT) + { + /* Enable IT on provided Lines for Cortex-M4 */ + LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95); + } + else + { + /* Disable IT on provided Lines for Cortex-M4 */ + LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95); + } + + if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT) + { + /* Enable event on provided Lines for Cortex-M4 */ + LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95); + } + else + { + /* Disable event on provided Lines for Cortex-M4 */ + LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); + } +#endif /* DUAL_CORE */ + + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95); + LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95); + break; + default: + status = ERROR; + break; + } + } + } + } + else /* DISABLE LineCommand */ + { + /* Disable IT on provided Lines for Cortex-M7*/ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); + LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); + + /* Disable event on provided Lines for Cortex-M7 */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); + +#if defined(DUAL_CORE) + /* Disable IT on provided Lines for Cortex-M4*/ + LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); + LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); + + /* Disable event on provided Lines for Cortex-M4 */ + LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); + LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); +#endif /* DUAL_CORE */ + } + + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->Line_64_95 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c new file mode 100644 index 0000000..eb53261 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c @@ -0,0 +1,1091 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_fmc.c + * @author MCD Application Team + * @brief FMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### FMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND memory controller + (+) The Synchronous DRAM (SDRAM) controller + + [..] The FMC functional block makes the interface with synchronous and asynchronous static + memories and SDRAM memories. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FMC performs + only one access at a time to an external device. + The main features of the FMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Interface with synchronous DRAM (SDRAM) memories + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) + +/** @defgroup FMC_LL FMC Low Layer + * @brief FMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FMC registers bit mask --------------------------- */ + +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ + FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ + FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ + FMC_BTRx_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ + FMC_BWTRx_ACCMOD)) + +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ + FMC_PCR_PWID | FMC_PCR_ECCEN | \ + FMC_PCR_TCLR | FMC_PCR_TAR | \ + FMC_PCR_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ + FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ + FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) + + +/* --- SDCR Register ---*/ +/* SDCR register clear mask */ +#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCRx_NC | FMC_SDCRx_NR | \ + FMC_SDCRx_MWID | FMC_SDCRx_NB | \ + FMC_SDCRx_CAS | FMC_SDCRx_WP | \ + FMC_SDCRx_SDCLK | FMC_SDCRx_RBURST | \ + FMC_SDCRx_RPIPE)) + +/* --- SDTR Register ---*/ +/* SDTR register clear mask */ +#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTRx_TMRD | FMC_SDTRx_TXSR | \ + FMC_SDTRx_TRAS | FMC_SDTRx_TRC | \ + FMC_SDTRx_TWR | FMC_SDTRx_TRP | \ + FMC_SDTRx_TRCD)) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions + * @{ + */ + + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() + (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() + (+) FMC NORSRAM bank extended timing configuration using the function + FMC_NORSRAM_Extended_Timing_Init() + (+) FMC NORSRAM bank enable/disable write operation using the functions + FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NORSRAM interface + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMC_NORSRAM device according to the specified + * control parameters in the FMC_NORSRAM_InitTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FMC_MUX(Init->DataAddressMux)); + assert_param(IS_FMC_MEMORY(Init->MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); + assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FMC_NORSRAM_DISABLE(Device, Init->NSBank); + + /* Set NORSRAM device control parameters */ + if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + + btcr_reg |= Init->ContinuousClock; + btcr_reg |= Init->WriteFifo; + btcr_reg |= Init->PageSize; + + mask = (FMC_BCRx_MBKEN | + FMC_BCRx_MUXEN | + FMC_BCRx_MTYP | + FMC_BCRx_MWID | + FMC_BCRx_FACCEN | + FMC_BCRx_BURSTEN | + FMC_BCRx_WAITPOL | + FMC_BCRx_WAITCFG | + FMC_BCRx_WREN | + FMC_BCRx_WAITEN | + FMC_BCRx_EXTMOD | + FMC_BCRx_ASYNCWAIT | + FMC_BCRx_CBURSTRW); + + mask |= FMC_BCR1_CCLKEN; + mask |= FMC_BCR1_WFDIS; + mask |= FMC_BCRx_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + + /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ + if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); + } + + if (Init->NSBank != FMC_NORSRAM_BANK1) + { + /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ + SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); + } + + return HAL_OK; +} + +/** + * @brief DeInitialize the FMC_NORSRAM peripheral + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable the FMC_NORSRAM device */ + __FMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FMC_NORSRAM device */ + /* FMC_NORSRAM_BANK1 */ + if (Bank == FMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DBU; + } + /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2U; + } + + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set FMC_NORSRAM device timing parameters */ + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | + (Timing->AccessMode))); + + /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ + if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + { + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); + } + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @param ExtendedMode FMC Extended Mode + * This parameter can be one of the following values: + * @arg FMC_EXTENDED_MODE_DISABLE + * @arg FMC_EXTENDED_MODE_ENABLE + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) +{ + /* Check the parameters */ + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFFU; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions + * @brief NAND Controller functions + * + @verbatim + ============================================================================== + ##### How to use NAND device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC NAND banks in order + to run the NAND external devices. + + (+) FMC NAND bank reset using the function FMC_NAND_DeInit() + (+) FMC NAND bank control configuration using the function FMC_NAND_Init() + (+) FMC NAND bank common space timing configuration using the function + FMC_NAND_CommonSpace_Timing_Init() + (+) FMC NAND bank attribute space timing configuration using the function + FMC_NAND_AttributeSpace_Timing_Init() + (+) FMC NAND bank enable/disable ECC correction feature using the functions + FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() + (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NAND interface + (+) De-initialize the FMC NAND interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_NAND device according to the specified + * control parameters in the FMC_NAND_HandleTypeDef + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Init->NandBank)); + assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); + assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Common space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Attribute space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos))); + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_NAND device + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable the NAND Bank */ + __FMC_NAND_DISABLE(Device, Bank); + + /* De-initialize the NAND Bank */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR, 0x00000018U); + WRITE_REG(Device->SR, 0x00000040U); + WRITE_REG(Device->PMEM, 0xFCFCFCFCU); + WRITE_REG(Device->PATT, 0xFCFCFCFCU); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Enable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + SET_BIT(Device->PCR, FMC_PCR_ECCEN); + + return HAL_OK; +} + + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FIFO is empty */ + while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; + + return HAL_OK; +} + +/** + * @} + */ + + + +/** @defgroup FMC_LL_SDRAM + * @brief SDRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use SDRAM device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC SDRAM banks in order + to run the SDRAM external devices. + + (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() + (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() + (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() + (+) FMC SDRAM bank enable/disable write operation using the functions + FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() + (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() + +@endverbatim + * @{ + */ + +/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC SDRAM interface + (+) De-initialize the FMC SDRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_SDRAM device according to the specified + * control parameters in the FMC_SDRAM_InitTypeDef + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection | + Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + FMC_SDCRx_SDCLK | + FMC_SDCRx_RBURST | + FMC_SDCRx_RPIPE, + (Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection)); + } + + return HAL_OK; +} + + +/** + * @brief Initializes the FMC_SDRAM device timing according to the specified + * parameters in the FMC_SDRAM_TimingTypeDef + * @param Device Pointer to SDRAM device instance + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | + (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + FMC_SDTRx_TRC | + FMC_SDTRx_TRP, + (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos)); + + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); + } + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_SDRAM peripheral + * @param Device Pointer to SDRAM device instance + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* De-initialize the SDRAM device */ + Device->SDCR[Bank] = 0x000002D0U; + Device->SDTR[Bank] = 0x0FFFFFFFU; + Device->SDCMR = 0x00000000U; + Device->SDRTR = 0x00000000U; + Device->SDSR = 0x00000000U; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_SDRAM write protection. + * @param Device Pointer to SDRAM device instance + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Enable write protection */ + SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_SDRAM write protection. + * @param hsdram FMC_SDRAM handle + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Disable write protection */ + CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Send Command to the FMC SDRAM bank + * @param Device Pointer to SDRAM device instance + * @param Command Pointer to SDRAM command structure + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), + ((Command->CommandMode) | (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); + /* Prevent unused argument(s) compilation warning */ + UNUSED(Timeout); + return HAL_OK; +} + +/** + * @brief Program the SDRAM Memory Refresh rate. + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); + + return HAL_OK; +} + +/** + * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. + * @param Device Pointer to SDRAM device instance + * @param AutoRefreshNumber Specifies the auto Refresh number. + * @retval None + */ +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); + + /* Set the Auto-refresh number in command register */ + MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); + + return HAL_OK; +} + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param Device Pointer to SDRAM device instance + * @param Bank Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @retval The FMC SDRAM bank mode status, could be on of the following values: + * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or + * FMC_SDRAM_POWER_DOWN_MODE. + */ +uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Get the corresponding bank mode */ + if (Bank == FMC_SDRAM_BANK1) + { + tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c new file mode 100644 index 0000000..f48c346 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_gpio.c @@ -0,0 +1,305 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_gpio.h" +#include "stm32h7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @addtogroup GPIO_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 ) ||\ + ((__VALUE__) == LL_GPIO_AF_8 ) ||\ + ((__VALUE__) == LL_GPIO_AF_9 ) ||\ + ((__VALUE__) == LL_GPIO_AF_10 ) ||\ + ((__VALUE__) == LL_GPIO_AF_11 ) ||\ + ((__VALUE__) == LL_GPIO_AF_12 ) ||\ + ((__VALUE__) == LL_GPIO_AF_13 ) ||\ + ((__VALUE__) == LL_GPIO_AF_14 ) ||\ + ((__VALUE__) == LL_GPIO_AF_15 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC); + } +#if defined(GPIOD) + else if (GPIOx == GPIOD) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD); + } +#endif /* GPIOD */ +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE); + } +#endif /* GPIOE */ +#if defined(GPIOF) + else if (GPIOx == GPIOF) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF); + } +#endif /* GPIOF */ +#if defined(GPIOG) + else if (GPIOx == GPIOG) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG); + } +#endif /* GPIOG */ +#if defined(GPIOH) + else if (GPIOx == GPIOH) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH); + } +#endif /* GPIOH */ +#if defined(GPIOI) + else if (GPIOx == GPIOI) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOI); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOI); + } +#endif /* GPIOI */ +#if defined(GPIOJ) + else if (GPIOx == GPIOJ) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOJ); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOJ); + } +#endif /* GPIOJ */ +#if defined(GPIOK) + else if (GPIOx == GPIOK) + { + LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOK); + LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOK); + } +#endif /* GPIOK */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos, currentpin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = POSITION_VAL(GPIO_InitStruct->Pin); + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos); + + if (currentpin != 0x00000000U) + { + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Alternate function configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + } + pinpos++; + } + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c new file mode 100644 index 0000000..739cb1a --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c @@ -0,0 +1,285 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_lpuart.c + * @author MCD Application Team + * @brief LPUART LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_lpuart.h" +#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @addtogroup LPUART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of LPUART registers */ + +#define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + +/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ +/* value : */ +/* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ +/* - LPUART_BRR register value should be >= 0x300 */ +/* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ +/* Baudrate specified by the user should belong to [8, 33000000].*/ +#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U)) + +/* __VALUE__ BRR content must be greater than or equal to 0x300. */ +#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */ +#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) + +#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + +#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + +#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + +#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + +#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LPUART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize LPUART registers (Registers restored to their default values). + * @param LPUARTx LPUART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + + if (LPUARTx == LPUART1) + { + /* Force reset of LPUART peripheral */ + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPUART1); + + /* Release reset of LPUART peripheral */ + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPUART1); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize LPUART registers according to the specified + * parameters in LPUART_InitStruct. + * @note As some bits in LPUART configuration registers can only be written when + * the LPUART is disabled (USART_CR1_UE bit =0), + * LPUART Peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0). + * @param LPUARTx LPUART Instance + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * that contains the configuration information for the specified LPUART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content + * - ERROR: Problem occurred during LPUART Registers initialization + */ +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue)); + assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); + assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); + assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity)); + assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection)); + assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl)); + + /* LPUART needs to be in disabled state, in order to be able to configure some bits in + CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */ + if (LL_LPUART_IsEnabled(LPUARTx) == 0U) + { + /*---------------------------- LPUART CR1 Configuration ----------------------- + * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters: + * - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value + */ + MODIFY_REG(LPUARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection)); + + /*---------------------------- LPUART CR2 Configuration ----------------------- + * Configure LPUARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value. + */ + LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits); + + /*---------------------------- LPUART CR3 Configuration ----------------------- + * Configure LPUARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according + * to LPUART_InitStruct->HardwareFlowControl value. + */ + LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); + + /*---------------------------- LPUART BRR Configuration ----------------------- + * Retrieve Clock frequency used for LPUART Peripheral + */ + periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); + + /* Configure the LPUART Baud Rate : + - prescaler value is required + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (LPUART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_LPUART_SetBaudRate(LPUARTx, + periphclk, + LPUART_InitStruct->PrescalerValue, + LPUART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 0x300 */ + assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR)); + + /* Check BRR is lower than or equal to 0xFFFFF */ + assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR)); + } + + /*---------------------------- LPUART PRESC Configuration ----------------------- + * Configure LPUARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. + */ + LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue); + } + + return (status); +} + +/** + * @brief Set each @ref LL_LPUART_InitTypeDef field to default value. + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + /* Set LPUART_InitStruct fields to default values */ + LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; + LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; + LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; + LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; + LPUART_InitStruct->TransferDirection = LL_LPUART_DIRECTION_TX_RX; + LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c new file mode 100644 index 0000000..e7b85d9 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c @@ -0,0 +1,1793 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @addtogroup RCC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Variables + * @{ + */ +const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART16_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART234578_CLKSOURCE)) + + +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C123_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) + +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPTIM345_CLKSOURCE)) + +#if defined(SAI3) +#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI23_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE)) +#elif defined(SAI4) +#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI4A_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI4B_CLKSOURCE)) +#else +#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI2A_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SAI2B_CLKSOURCE)) +#endif /* SAI3 */ + +#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI123_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI45_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +static uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency); + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL1, PLL2 and PLL3 OFF + * - AHB, APB Bus pre-scaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +void LL_RCC_DeInit(void) +{ + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait for HSI READY bit */ + while (LL_RCC_HSI_IsReady() == 0U) + {} + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \ + | RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Wait for PLL1 READY bit to be reset */ + while (LL_RCC_PLL1_IsReady() != 0U) + {} + + /* Wait for PLL2 READY bit to be reset */ + while (LL_RCC_PLL2_IsReady() != 0U) + {} + + /* Wait for PLL3 READY bit to be reset */ + while (LL_RCC_PLL3_IsReady() != 0U) + {} + +#if defined(RCC_D1CFGR_HPRE) + /* Reset D1CFGR register */ + CLEAR_REG(RCC->D1CFGR); + + /* Reset D2CFGR register */ + CLEAR_REG(RCC->D2CFGR); + + /* Reset D3CFGR register */ + CLEAR_REG(RCC->D3CFGR); +#else + /* Reset CDCFGR1 register */ + CLEAR_REG(RCC->CDCFGR1); + + /* Reset CDCFGR2 register */ + CLEAR_REG(RCC->CDCFGR2); + + /* Reset SRDCFGR register */ + CLEAR_REG(RCC->SRDCFGR); + +#endif /* RCC_D1CFGR_HPRE */ + + /* Reset PLLCKSELR register to default value */ + RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5; + + /* Reset PLLCFGR register to default value */ + LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U); + + /* Reset PLL1DIVR register to default value */ + LL_RCC_WriteReg(PLL1DIVR, 0x01010280U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Reset PLL2DIVR register to default value */ + LL_RCC_WriteReg(PLL2DIVR, 0x01010280U); + + /* Reset PLL2FRACR register */ + CLEAR_REG(RCC->PLL2FRACR); + + /* Reset PLL3DIVR register to default value */ + LL_RCC_WriteReg(PLL3DIVR, 0x01010280U); + + /* Reset PLL3FRACR register */ + CLEAR_REG(RCC->PLL3FRACR); + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts */ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC + | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC + | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC); + + /* Clear reset source flags */ + SET_BIT(RCC->RSR, RCC_RSR_RMVF); + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); + } + +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks. + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is CSI, function returns values based on CSI_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in header file (default value + * 64 MHz) divider by HSIDIV, but the real value may vary depending on + * on the variations in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in header file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note (***) CSI_VALUE is a constant defined in header file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks. + * @note Each time SYSCLK, HCLK, PCLK1, PCLK2, PCLK3 and/or PCLK4 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK3 clock frequency */ + RCC_Clocks->PCLK3_Frequency = RCC_GetPCLK3ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK4 clock frequency */ + RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return PLL1 clocks frequencies + * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval None + */ +void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) +{ + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource; + uint32_t m, n, fracn = 0U; + + /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_PLLSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_NONE: + default: + /* PLL clock disabled */ + break; + } + + PLL_Clocks->PLL_P_Frequency = 0U; + PLL_Clocks->PLL_Q_Frequency = 0U; + PLL_Clocks->PLL_R_Frequency = 0U; + + m = LL_RCC_PLL1_GetM(); + n = LL_RCC_PLL1_GetN(); + if (LL_RCC_PLL1FRACN_IsEnabled() != 0U) + { + fracn = LL_RCC_PLL1_GetFRACN(); + } + + if (m != 0U) + { + if (LL_RCC_PLL1P_IsEnabled() != 0U) + { + PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetP()); + } + + if (LL_RCC_PLL1Q_IsEnabled() != 0U) + { + PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetQ()); + } + + if (LL_RCC_PLL1R_IsEnabled() != 0U) + { + PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL1_GetR()); + } + } +} + +/** + * @brief Return PLL2 clocks frequencies + * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval None + */ +void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) +{ + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource; + uint32_t m, n, fracn = 0U; + + /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_PLLSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_NONE: + default: + /* PLL clock disabled */ + break; + } + + PLL_Clocks->PLL_P_Frequency = 0U; + PLL_Clocks->PLL_Q_Frequency = 0U; + PLL_Clocks->PLL_R_Frequency = 0U; + + m = LL_RCC_PLL2_GetM(); + n = LL_RCC_PLL2_GetN(); + if (LL_RCC_PLL2FRACN_IsEnabled() != 0U) + { + fracn = LL_RCC_PLL2_GetFRACN(); + } + + if (m != 0U) + { + if (LL_RCC_PLL2P_IsEnabled() != 0U) + { + PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetP()); + } + + if (LL_RCC_PLL2Q_IsEnabled() != 0U) + { + PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetQ()); + } + + if (LL_RCC_PLL2R_IsEnabled() != 0U) + { + PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL2_GetR()); + } + } +} + +/** + * @brief Return PLL3 clocks frequencies + * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready + * @retval None + */ +void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) +{ + uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO, pllsource; + uint32_t m, n, fracn = 0U; + + /* PLL_VCO = (HSE_VALUE, CSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN) + SYSCLK = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_PLLSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + pllinputfreq = CSI_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + pllinputfreq = HSE_VALUE; + } + break; + + case LL_RCC_PLLSOURCE_NONE: + default: + /* PLL clock disabled */ + break; + } + + PLL_Clocks->PLL_P_Frequency = 0U; + PLL_Clocks->PLL_Q_Frequency = 0U; + PLL_Clocks->PLL_R_Frequency = 0U; + + m = LL_RCC_PLL3_GetM(); + n = LL_RCC_PLL3_GetN(); + if (LL_RCC_PLL3FRACN_IsEnabled() != 0U) + { + fracn = LL_RCC_PLL3_GetFRACN(); + } + + if ((m != 0U) && (pllinputfreq != 0U)) + { + if (LL_RCC_PLL3P_IsEnabled() != 0U) + { + PLL_Clocks->PLL_P_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetP()); + } + + if (LL_RCC_PLL3Q_IsEnabled() != 0U) + { + PLL_Clocks->PLL_Q_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetQ()); + } + + if (LL_RCC_PLL3R_IsEnabled() != 0U) + { + PLL_Clocks->PLL_R_Frequency = LL_RCC_CalcPLLClockFreq(pllinputfreq, m, n, fracn, LL_RCC_PLL3_GetR()); + } + } +} + +/** + * @brief Helper function to calculate the PLL frequency output + * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP ()); + * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI) + * @param M Between 1 and 63 + * @param N Between 4 and 512 + * @param FRACN Between 0 and 0x1FFF + * @param PQR VCO output divider (P, Q or R) + * Between 1 and 128, except for PLL1P Odd value not allowed + * @retval PLL1 clock frequency (in Hz) + */ +uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR) +{ + float_t freq; + + freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000)); + + freq = freq / (float_t)PQR; + + return (uint32_t)freq; +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART16_CLKSOURCE + * @arg @ref LL_RCC_USART234578_CLKSOURCE + * @retval USART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART16_CLKSOURCE_PCLK2: + usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_USART234578_CLKSOURCE_PCLK1: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_USART16_CLKSOURCE_PLL2Q: + case LL_RCC_USART234578_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + usart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USART16_CLKSOURCE_PLL3Q: + case LL_RCC_USART234578_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + usart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USART16_CLKSOURCE_HSI: + case LL_RCC_USART234578_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_USART16_CLKSOURCE_CSI: + case LL_RCC_USART234578_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + usart_frequency = CSI_VALUE; + } + break; + + case LL_RCC_USART16_CLKSOURCE_LSE: + case LL_RCC_USART234578_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + usart_frequency = LSE_VALUE; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return usart_frequency; +} + +/** + * @brief Return LPUART clock frequency + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval LPUART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) +{ + uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART1_CLKSOURCE_PCLK4: + lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_LPUART1_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + lpuart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + lpuart_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + lpuart_frequency = CSI_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return lpuart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C123_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C123_CLKSOURCE_PCLK1: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_I2C4_CLKSOURCE_PCLK4: + i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_I2C123_CLKSOURCE_PLL3R: + case LL_RCC_I2C4_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + i2c_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_I2C123_CLKSOURCE_HSI: + case LL_RCC_I2C4_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_I2C123_CLKSOURCE_CSI: + case LL_RCC_I2C4_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + i2c_frequency = CSI_VALUE; + } + break; + + default: + /* Nothing to do */ + break; + } + + return i2c_frequency; +} + +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @arg @ref LL_RCC_LPTIM345_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_LPTIM2_CLKSOURCE_PCLK4: + case LL_RCC_LPTIM345_CLKSOURCE_PCLK4: + lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PLL2P: + case LL_RCC_LPTIM2_CLKSOURCE_PLL2P: + case LL_RCC_LPTIM345_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + lptim_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PLL3R: + case LL_RCC_LPTIM2_CLKSOURCE_PLL3R: + case LL_RCC_LPTIM345_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + lptim_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: + case LL_RCC_LPTIM2_CLKSOURCE_LSE: + case LL_RCC_LPTIM345_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSI: + case LL_RCC_LPTIM2_CLKSOURCE_LSI: + case LL_RCC_LPTIM345_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_CLKP: + case LL_RCC_LPTIM2_CLKSOURCE_CLKP: + case LL_RCC_LPTIM345_CLKSOURCE_CLKP: + lptim_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Kernel clock disabled */ + break; + } + + return lptim_frequency; +} + +/** + * @brief Return SAIx clock frequency + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI23_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*) + * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*) + * @retval SAI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + * + * (*) : Available on some STM32H7 lines only. + */ +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) +{ + uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); + + switch (LL_RCC_GetSAIClockSource(SAIxSource)) + { + case LL_RCC_SAI1_CLKSOURCE_PLL1Q: +#if defined(SAI3) + case LL_RCC_SAI23_CLKSOURCE_PLL1Q: +#endif /* SAI3 */ +#if defined(SAI4) + case LL_RCC_SAI4A_CLKSOURCE_PLL1Q: + case LL_RCC_SAI4B_CLKSOURCE_PLL1Q: +#endif /* SAI4 */ +#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL) + case LL_RCC_SAI2A_CLKSOURCE_PLL1Q: + case LL_RCC_SAI2B_CLKSOURCE_PLL1Q: +#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */ + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + sai_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SAI1_CLKSOURCE_PLL2P: +#if defined(SAI3) + case LL_RCC_SAI23_CLKSOURCE_PLL2P: +#endif /* SAI3 */ +#if defined(SAI4) + case LL_RCC_SAI4A_CLKSOURCE_PLL2P: + case LL_RCC_SAI4B_CLKSOURCE_PLL2P: +#endif /* SAI4 */ +#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL) + case LL_RCC_SAI2A_CLKSOURCE_PLL2P: + case LL_RCC_SAI2B_CLKSOURCE_PLL2P: +#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */ + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + sai_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SAI1_CLKSOURCE_PLL3P: +#if defined(SAI3) + case LL_RCC_SAI23_CLKSOURCE_PLL3P: +#endif /* SAI3 */ +#if defined(SAI4) + case LL_RCC_SAI4A_CLKSOURCE_PLL3P: + case LL_RCC_SAI4B_CLKSOURCE_PLL3P: +#endif /* SAI4 */ +#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL) + case LL_RCC_SAI2A_CLKSOURCE_PLL3P: + case LL_RCC_SAI2B_CLKSOURCE_PLL3P: +#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */ + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + sai_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN: +#if defined(SAI3) + case LL_RCC_SAI23_CLKSOURCE_I2S_CKIN: +#endif /* SAI3 */ +#if defined(SAI4) + case LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN: + case LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN: +#endif /* SAI4 */ +#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL) + case LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN: + case LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN: +#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */ + sai_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_SAI1_CLKSOURCE_CLKP: +#if defined(SAI3) + case LL_RCC_SAI23_CLKSOURCE_CLKP: +#endif /* SAI3 */ +#if defined(SAI4) + case LL_RCC_SAI4A_CLKSOURCE_CLKP: + case LL_RCC_SAI4B_CLKSOURCE_CLKP: +#endif /* SAI4 */ +#if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL) + case LL_RCC_SAI2A_CLKSOURCE_CLKP: + case LL_RCC_SAI2B_CLKSOURCE_CLKP: +#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */ + sai_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Kernel clock disabled */ + break; + } + + return sai_frequency; +} + +/** + * @brief Return ADC clock frequency + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval ADC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) +{ + uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetADCClockSource(ADCxSource)) + { + case LL_RCC_ADC_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + adc_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_ADC_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + adc_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_ADC_CLKSOURCE_CLKP: + adc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Kernel clock disabled */ + break; + } + + return adc_frequency; +} + +/** + * @brief Return SDMMC clock frequency + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC_CLKSOURCE + * @retval SDMMC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) +{ + uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) + { + case LL_RCC_SDMMC_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + sdmmc_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SDMMC_CLKSOURCE_PLL2R: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + sdmmc_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + default: + /* Nothing to do */ + break; + } + + return sdmmc_frequency; +} + +/** + * @brief Return RNG clock frequency + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval RNG clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) +{ + uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetRNGClockSource(RNGxSource)) + { + case LL_RCC_RNG_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + rng_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_RNG_CLKSOURCE_HSI48: + if (LL_RCC_HSI48_IsReady() != 0U) + { + rng_frequency = 48000000U; + } + break; + + case LL_RCC_RNG_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + rng_frequency = LSE_VALUE; + } + break; + + case LL_RCC_RNG_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + rng_frequency = LSI_VALUE; + } + break; + + default: + /* Nothing to do */ + break; + } + + return rng_frequency; +} + +/** + * @brief Return CEC clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_LSE: + if (LL_RCC_LSE_IsReady() != 0U) + { + cec_frequency = LSE_VALUE; + } + break; + + case LL_RCC_CEC_CLKSOURCE_LSI: + if (LL_RCC_LSI_IsReady() != 0U) + { + cec_frequency = LSI_VALUE; + } + break; + + case LL_RCC_CEC_CLKSOURCE_CSI_DIV122: + if (LL_RCC_CSI_IsReady() != 0U) + { + cec_frequency = CSI_VALUE / 122U; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return cec_frequency; +} + +/** + * @brief Return USB clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready or Disabled + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { + case LL_RCC_USB_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + usb_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USB_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + usb_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_USB_CLKSOURCE_HSI48: + if (LL_RCC_HSI48_IsReady() != 0U) + { + usb_frequency = HSI48_VALUE; + } + break; + + case LL_RCC_USB_CLKSOURCE_DISABLE: + default: + /* Nothing to do */ + break; + } + + return usb_frequency; +} + +/** + * @brief Return DFSDM clock frequency + * @param DFSDMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval DFSDM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) +{ + uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource)) + { + case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: + dfsdm_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: + dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + default: + /* Nothing to do */ + break; + } + + return dfsdm_frequency; +} + +#if defined(DFSDM2_BASE) +/** + * @brief Return DFSDM clock frequency + * @param DFSDMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM2_CLKSOURCE + * @retval DFSDM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource) +{ + uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + + switch (LL_RCC_GetDFSDM2ClockSource(DFSDMxSource)) + { + + case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: + dfsdm_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_DFSDM2_CLKSOURCE_PCLK4: + dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + default: + /* Nothing to do */ + break; + } + + return dfsdm_frequency; +} +#endif /* DFSDM2_BASE */ + +#if defined(DSI) +/** + * @brief Return DSI clock frequency + * @param DSIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval DSI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used + */ +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) +{ + uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetDSIClockSource(DSIxSource)) + { + case LL_RCC_DSI_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + dsi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_DSI_CLKSOURCE_PHY: + dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + + default: + /* Nothing to do */ + break; + } + + return dsi_frequency; +} +#endif /* DSI */ + +/** + * @brief Return SPDIF clock frequency + * @param SPDIFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPDIF_CLKSOURCE + * @retval SPDIF clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource) +{ + uint32_t spdif_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetSPDIFClockSource(SPDIFxSource)) + { + case LL_RCC_SPDIF_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + spdif_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPDIF_CLKSOURCE_PLL2R: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + spdif_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_SPDIF_CLKSOURCE_PLL3R: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + spdif_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_SPDIF_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + default: + /* Nothing to do */ + break; + } + + return spdif_frequency; +} + +/** + * @brief Return SPIx clock frequency + * @param SPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI123_CLKSOURCE + * @arg @ref LL_RCC_SPI45_CLKSOURCE + * @arg @ref LL_RCC_SPI6_CLKSOURCE + * @retval SPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) +{ + uint32_t spi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Check parameter */ + assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource)); + + switch (LL_RCC_GetSPIClockSource(SPIxSource)) + { + case LL_RCC_SPI123_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPI123_CLKSOURCE_PLL2P: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SPI123_CLKSOURCE_PLL3P: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_P_Frequency; + } + break; + + case LL_RCC_SPI123_CLKSOURCE_I2S_CKIN: +#if defined(LL_RCC_SPI6_CLKSOURCE_I2S_CKIN) + case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN: +#endif /* LL_RCC_SPI6_CLKSOURCE_I2S_CKIN */ + spi_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_SPI123_CLKSOURCE_CLKP: + spi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + case LL_RCC_SPI45_CLKSOURCE_PCLK2: + spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_SPI6_CLKSOURCE_PCLK4: + spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_SPI45_CLKSOURCE_PLL2Q: + case LL_RCC_SPI6_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPI45_CLKSOURCE_PLL3Q: + case LL_RCC_SPI6_CLKSOURCE_PLL3Q: + if (LL_RCC_PLL3_IsReady() != 0U) + { + LL_RCC_GetPLL3ClockFreq(&PLL_Clocks); + spi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_SPI45_CLKSOURCE_HSI: + case LL_RCC_SPI6_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_SPI45_CLKSOURCE_CSI: + case LL_RCC_SPI6_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + spi_frequency = CSI_VALUE; + } + break; + + case LL_RCC_SPI45_CLKSOURCE_HSE: + case LL_RCC_SPI6_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + spi_frequency = HSE_VALUE; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return spi_frequency; +} + +/** + * @brief Return SWP clock frequency + * @param SWPxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SWP_CLKSOURCE + * @retval SWP clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource) +{ + uint32_t swp_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetSWPClockSource(SWPxSource)) + { + case LL_RCC_SWP_CLKSOURCE_PCLK1: + swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); + break; + + case LL_RCC_SWP_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + default: + /* Nothing to do */ + break; + } + + return swp_frequency; +} + +/** + * @brief Return FDCAN clock frequency + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval FDCAN clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) +{ + uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetFDCANClockSource(FDCANxSource)) + { + case LL_RCC_FDCAN_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + fdcan_frequency = HSE_VALUE; + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + fdcan_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_PLL2Q: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + fdcan_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + default: + /* Kernel clock disabled */ + break; + } + + return fdcan_frequency; +} + +/** + * @brief Return FMC clock frequency + * @param FMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FMC_CLKSOURCE + * @retval FMC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource) +{ + uint32_t fmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetFMCClockSource(FMCxSource)) + { + case LL_RCC_FMC_CLKSOURCE_HCLK: + fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); + break; + + case LL_RCC_FMC_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + fmc_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_FMC_CLKSOURCE_PLL2R: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + fmc_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_FMC_CLKSOURCE_CLKP: + fmc_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Nothing to do */ + break; + } + + return fmc_frequency; +} + +#if defined(QUADSPI) +/** + * @brief Return QSPI clock frequency + * @param QSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_QSPI_CLKSOURCE + * @retval QSPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource) +{ + uint32_t qspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetQSPIClockSource(QSPIxSource)) + { + case LL_RCC_QSPI_CLKSOURCE_HCLK: + qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); + break; + + case LL_RCC_QSPI_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + qspi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_QSPI_CLKSOURCE_PLL2R: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + qspi_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_QSPI_CLKSOURCE_CLKP: + qspi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Nothing to do */ + break; + } + + return qspi_frequency; +} +#endif /* QUADSPI */ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) +/** + * @brief Return OSPI clock frequency + * @param OSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI_CLKSOURCE + * @retval OSPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ + +uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource) +{ + uint32_t ospi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + LL_PLL_ClocksTypeDef PLL_Clocks; + + switch (LL_RCC_GetOSPIClockSource(OSPIxSource)) + { + case LL_RCC_OSPI_CLKSOURCE_HCLK: + ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); + break; + + case LL_RCC_OSPI_CLKSOURCE_PLL1Q: + if (LL_RCC_PLL1_IsReady() != 0U) + { + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + ospi_frequency = PLL_Clocks.PLL_Q_Frequency; + } + break; + + case LL_RCC_OSPI_CLKSOURCE_PLL2R: + if (LL_RCC_PLL2_IsReady() != 0U) + { + LL_RCC_GetPLL2ClockFreq(&PLL_Clocks); + ospi_frequency = PLL_Clocks.PLL_R_Frequency; + } + break; + + case LL_RCC_OSPI_CLKSOURCE_CLKP: + ospi_frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE); + break; + + default: + /* Nothing to do */ + break; + } + + return ospi_frequency; +} +#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */ + +/** + * @brief Return CLKP clock frequency + * @param CLKPxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CLKP_CLKSOURCE + * @retval CLKP clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource) +{ + uint32_t clkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_GetCLKPClockSource(CLKPxSource)) + { + case LL_RCC_CLKP_CLKSOURCE_HSI: + if (LL_RCC_HSI_IsReady() != 0U) + { + clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + } + break; + + case LL_RCC_CLKP_CLKSOURCE_CSI: + if (LL_RCC_CSI_IsReady() != 0U) + { + clkp_frequency = CSI_VALUE; + } + break; + + case LL_RCC_CLKP_CLKSOURCE_HSE: + if (LL_RCC_HSE_IsReady() != 0U) + { + clkp_frequency = HSE_VALUE; + } + break; + + default: + /* CLKP clock disabled */ + break; + } + + return clkp_frequency; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +static uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0U; + LL_PLL_ClocksTypeDef PLL_Clocks; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + /* No check on Ready: Won't be selected by hardware if not */ + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: + frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_CSI: + frequency = CSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1: + LL_RCC_GetPLL1ClockFreq(&PLL_Clocks); + frequency = PLL_Clocks.PLL_P_Frequency; + break; + + default: + /* Nothing to do */ + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return PCLK2 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK2 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK2 clock frequency */ + return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); +} + +/** + * @brief Return PCLK3 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK3 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK3 clock frequency */ + return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler()); +} + +/** + * @brief Return PCLK4 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK4 clock frequency (in Hz) + */ +static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK4 clock frequency */ + return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler()); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c new file mode 100644 index 0000000..0e516e7 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c @@ -0,0 +1,876 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_rtc.c + * @author MCD Application Team + * @brief RTC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_rtc.h" +#include "stm32h7xx_ll_cortex.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @addtogroup RTC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Constants + * @{ + */ +/* Default values used for prescaler */ +#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU +#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU + +/* Values used for timeout */ +#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Macros + * @{ + */ + +#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ + || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) + +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) + +#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + +#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \ + || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM)) + +#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) +#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) + +#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) + +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) + +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) + +#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) + +#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL)) + +#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) + + +#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) + +#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) + + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes the RTC registers to their default reset values. + * @note This function does not reset the RTC Clock source and RTC Backup Data + * registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are de-initialized + * - ERROR: RTC registers are not de-initialized + */ +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) +{ + ErrorStatus status = ERROR; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Reset TR, DR and CR registers */ + LL_RTC_WriteReg(RTCx, TR, 0x00000000U); + LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + + /* Reset All CR bits except CR[2:0] */ + LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); + + LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); + LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); + LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); + LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); + LL_RTC_WriteReg(RTCx, CALR, 0x00000000U); + LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); + LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); + +#if defined(TAMP) + /* Reset ICSR register and exit initialization mode */ + LL_RTC_WriteReg(RTCx, ICSR, 0x00000000U); +#else + /* Reset ISR register and exit initialization mode */ + LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); + + /* Reset Tamper and alternate functions configuration register */ + LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U); + + /* Reset Option register */ + LL_RTC_WriteReg(RTCx, OR, 0x00000000U); +#endif /* TAMP */ + + /* Wait till the RTC RSF flag is set */ + status = LL_RTC_WaitForSynchro(RTCx); + } + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + +#if defined(TAMP) + /* DeInitialization of the TAMP */ + LL_RTC_WriteReg(TAMP, CR1, 0xFFFF0000U); + LL_RTC_WriteReg(TAMP, FLTCR, 0x00000000U); + LL_RTC_WriteReg(TAMP, ATCR1, 0x00000000U); + LL_RTC_WriteReg(TAMP, IER, 0x00000000U); + LL_RTC_WriteReg(TAMP, SCR, 0xFFFFFFFFU); +#endif /* TAMP */ + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTCx RTC Instance + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat)); + assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Set Hour Format */ + LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat); + + /* Configure Synchronous and Asynchronous prescaler factor */ + LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler); + LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT; +} + +/** + * @brief Set the RTC current time. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + } + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours, + RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); + } + else + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; + RTC_TimeStruct->Hours = 0U; + RTC_TimeStruct->Minutes = 0U; + RTC_TimeStruct->Seconds = 0U; +} + +/** + * @brief Set the RTC current date. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Day register is configured + * - ERROR: RTC Day register is not configured + */ +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) + { + RTC_DateStruct->Month = (uint8_t)((RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU); + } + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day)); + } + else + { + assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year))); + assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month))); + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); + } + assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year); + } + else + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day), + __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00) + * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Day = 1U; + RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0U; +} + +/** + * @brief Set the RTC Alarm A. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use @ref LL_RTC_ALMA_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMA registers are configured + * - ERROR: ALARMA registers are not configured + */ +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMA_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMA_EnableWeekday(RTCx); + LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set the RTC Alarm B. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (@ref LL_RTC_ALMB_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMB registers are configured + * - ERROR: ALARMB registers are not configured + */ +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMB_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMB_EnableWeekday(RTCx); + LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE; +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Check if the Initialization mode is set */ + if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U) + { + /* Set the Initialization mode */ + LL_RTC_EnableInitMode(RTCx); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) +{ + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + return SUCCESS; +} + +/** + * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Clear RSF flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Wait the registers to be synchronised */ + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + + if (status != ERROR) + { + timeout = RTC_SYNCHRO_TIMEOUT; + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c new file mode 100644 index 0000000..d78aaf0 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c @@ -0,0 +1,750 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_spi.c + * @author MCD Application Team + * @brief SPI LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_spi.h" +#include "stm32h7xx_ll_bus.h" +#include "stm32h7xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) + +/** @addtogroup SPI_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup SPI_LL_Private_Macros + * @{ + */ + +#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \ + ((__VALUE__) == LL_SPI_MODE_SLAVE)) + +#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED)) + +#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS)) + +#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \ + ((__VALUE__) == LL_SPI_PROTOCOL_TI)) + +#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \ + ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + +#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \ + ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + +#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + +#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \ + ((__VALUE__) == LL_SPI_MSB_FIRST)) + +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT)) + +#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_16DATA)) + +#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \ + ((__VALUE__) == LL_SPI_CRC_5BIT) || \ + ((__VALUE__) == LL_SPI_CRC_6BIT) || \ + ((__VALUE__) == LL_SPI_CRC_7BIT) || \ + ((__VALUE__) == LL_SPI_CRC_8BIT) || \ + ((__VALUE__) == LL_SPI_CRC_9BIT) || \ + ((__VALUE__) == LL_SPI_CRC_10BIT) || \ + ((__VALUE__) == LL_SPI_CRC_11BIT) || \ + ((__VALUE__) == LL_SPI_CRC_12BIT) || \ + ((__VALUE__) == LL_SPI_CRC_13BIT) || \ + ((__VALUE__) == LL_SPI_CRC_14BIT) || \ + ((__VALUE__) == LL_SPI_CRC_15BIT) || \ + ((__VALUE__) == LL_SPI_CRC_16BIT) || \ + ((__VALUE__) == LL_SPI_CRC_17BIT) || \ + ((__VALUE__) == LL_SPI_CRC_18BIT) || \ + ((__VALUE__) == LL_SPI_CRC_19BIT) || \ + ((__VALUE__) == LL_SPI_CRC_20BIT) || \ + ((__VALUE__) == LL_SPI_CRC_21BIT) || \ + ((__VALUE__) == LL_SPI_CRC_22BIT) || \ + ((__VALUE__) == LL_SPI_CRC_23BIT) || \ + ((__VALUE__) == LL_SPI_CRC_24BIT) || \ + ((__VALUE__) == LL_SPI_CRC_25BIT) || \ + ((__VALUE__) == LL_SPI_CRC_26BIT) || \ + ((__VALUE__) == LL_SPI_CRC_27BIT) || \ + ((__VALUE__) == LL_SPI_CRC_28BIT) || \ + ((__VALUE__) == LL_SPI_CRC_29BIT) || \ + ((__VALUE__) == LL_SPI_CRC_30BIT) || \ + ((__VALUE__) == LL_SPI_CRC_31BIT) || \ + ((__VALUE__) == LL_SPI_CRC_32BIT)) + +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + +#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET)) + +#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \ + ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + +#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + +#if defined(SPI1) + if (SPIx == SPI1) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI1 */ +#if defined(SPI2) + if (SPIx == SPI2) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI2 */ +#if defined(SPI3) + if (SPIx == SPI3) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI3 */ +#if defined(SPI4) + if (SPIx == SPI4) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI4 */ +#if defined(SPI5) + if (SPIx == SPI5) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI5 */ +#if defined(SPI6) + if (SPIx == SPI6) + { + /* Force reset of SPI clock */ + LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_SPI6); + + /* Release reset of SPI clock */ + LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI6 */ + + return status; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled + * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t tmp_nss; + uint32_t tmp_mode; + uint32_t tmp_nss_polarity; + + /* Check the SPI Instance SPIx*/ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Check the SPI parameters from SPI_InitStruct*/ + assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate)); + assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + + /* Check the SPI instance is not enabled */ + if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) + { + /*---------------------------- SPIx CFG1 Configuration ------------------------ + * Configure SPIx CFG1 with parameters: + * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits + * - CRC Computation Enable : SPI_CFG1_CRCEN bit + * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits + */ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, + SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth); + + tmp_nss = SPI_InitStruct->NSS; + tmp_mode = SPI_InitStruct->Mode; + tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx); + + /* Checks to setup Internal SS signal level and avoid a MODF Error */ + if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \ + (tmp_mode == LL_SPI_MODE_MASTER)) || \ + ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \ + (tmp_mode == LL_SPI_MODE_SLAVE)))) + { + LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); + } + + /*---------------------------- SPIx CFG2 Configuration ------------------------ + * Configure SPIx CFG2 with parameters: + * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits + * - ClockPolarity : SPI_CFG2_CPOL bit + * - ClockPhase : SPI_CFG2_CPHA bit + * - BitOrder : SPI_CFG2_LSBFRST bit + * - Master/Slave Mode : SPI_CFG2_MASTER bit + * - SPI Mode : SPI_CFG2_COMM[1:0] bits + */ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | + SPI_CFG2_CPOL | SPI_CFG2_CPHA | + SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM, + SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity | + SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder | + SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM)); + + /*---------------------------- SPIx CR1 Configuration ------------------------ + * Configure SPIx CR1 with parameter: + * - Half Duplex Direction : SPI_CR1_HDDIR bit + */ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR); + + /*---------------------------- SPIx CRCPOLY Configuration ---------------------- + * Configure SPIx CRCPOLY with parameter: + * - CRCPoly : CRCPOLY[31:0] bits + */ + if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + } + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) +{ + /* Set SPI_InitStruct fields to default values */ + SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct->CRCPoly = 7UL; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/** @addtogroup I2S_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Constants I2S Private Constants + * @{ + */ +/* I2S registers Masks */ +#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_DATFMT | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_MCKOE | \ + SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Macros I2S Private Macros + * @{ + */ + +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_24B) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \ + ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + +#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__) (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH) || \ + ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH)) + +#define IS_LL_I2S_CKPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) || \ + ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) || \ + ((__VALUE__) == LL_I2S_STANDARD_MSB) || \ + ((__VALUE__) == LL_I2S_STANDARD_LSB) || \ + ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) || \ + ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) || \ + ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) || \ + ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_TX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_RX) || \ + ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX)) + +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) || \ + ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) && \ + ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) || \ + ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + +#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) <= 0xFFUL) + +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) || \ + ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) + +#define IS_LL_I2S_FIFO_TH (__VALUE__) (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA) || \ + ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA)) + +#define IS_LL_I2S_BIT_ORDER(__VALUE__) (((__VALUE__) == LL_I2S_LSB_FIRST) || \ + ((__VALUE__) == LL_I2S_MSB_FIRST)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI/I2S registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +{ + return LL_SPI_DeInit(SPIx); +} + +/** + * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. + * @note As some bits in I2S configuration registers can only be written when the SPI is disabled + * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @note I2S (SPI) source clock must be ready before calling this function. Otherwise will results + * in wrong programming. + * @param SPIx SPI Instance + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are Initialized + * - ERROR: SPI registers are not Initialized + */ +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +{ + uint32_t i2sdiv = 0UL; + uint32_t i2sodd = 0UL; + uint32_t packetlength = 1UL; + uint32_t ispcm = 0UL; + uint32_t tmp; + uint32_t sourceclock; + + ErrorStatus status = ERROR; + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + assert_param(IS_LL_I2S_CKPOL(I2S_InitStruct->ClockPolarity)); + + /* Check that SPE bit is set to 0 in order to be sure that SPI/I2S block is disabled. + * In this case, it is useless to check if the I2SMOD bit is set to 0 because + * this bit I2SMOD only serves to select the desired mode. + */ + if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) + { + /*---------------------------- SPIx I2SCFGR Configuration -------------------- + * Configure SPIx I2SCFGR with parameters: + * - Mode : SPI_I2SCFGR_I2SCFG[2:0] bits + * - Standard : SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + * - DataFormat : SPI_I2SCFGR_CHLEN, SPI_I2SCFGR_DATFMT and SPI_I2SCFGR_DATLEN[1:0] bits + * - ClockPolarity : SPI_I2SCFGR_CKPOL bit + * - MCLKOutput : SPI_I2SPR_MCKOE bit + * - I2S mode : SPI_I2SCFGR_I2SMOD bit + */ + + /* Write to SPIx I2SCFGR */ + MODIFY_REG(SPIx->I2SCFGR, + I2S_I2SCFGR_CLEAR_MASK, + I2S_InitStruct->Mode | I2S_InitStruct->Standard | + I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + I2S_InitStruct->MCLKOutput | SPI_I2SCFGR_I2SMOD); + + /*---------------------------- SPIx I2SCFGR Configuration ---------------------- + * Configure SPIx I2SCFGR with parameters: + * - AudioFreq : SPI_I2SCFGR_I2SDIV[7:0] and SPI_I2SCFGR_ODD bits + */ + + /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + * else, default values are used: i2sodd = 0U, i2sdiv = 0U. + */ + if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) + * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + */ + if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + { + /* Packet length is 32 bits */ + packetlength = 2UL; + } + + /* Check if PCM standard is used */ + if ((I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_SHORT) || + (I2S_InitStruct->Standard == LL_I2S_STANDARD_PCM_LONG)) + { + ispcm = 1UL; + } + + /* Get the I2S (SPI) source clock value */ +#if defined (SPI_SPI6I2S_SUPPORT) + if (SPIx == SPI6) + { + sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI6_CLKSOURCE); + } + else + { + sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE); + } +#else + sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE); +#endif /* SPI_SPI6I2S_SUPPORT */ + + /* Compute the Real divider depending on the MCLK output state with a fixed point */ + if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (((sourceclock / (256UL >> ispcm)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL; + } + else + { + /* MCLK output is disabled */ + tmp = (((sourceclock / ((32UL >> ispcm) * packetlength)) * 16UL) / I2S_InitStruct->AudioFreq) + 8UL; + } + + /* Remove the fixed point */ + tmp = tmp / 16UL; + + /* Check the parity of the divider */ + i2sodd = tmp & 0x1UL; + + /* Compute the i2sdiv prescaler */ + i2sdiv = tmp / 2UL; + } + + /* Test if the obtain values are forbidden or out of range */ + if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL)) + { + /* Set the default values */ + i2sdiv = 0UL; + i2sodd = 0UL; + } + + /* Write to SPIx I2SCFGR register the computed value */ + MODIFY_REG(SPIx->I2SCFGR, + SPI_I2SCFGR_ODD | SPI_I2SCFGR_I2SDIV, + (i2sodd << SPI_I2SCFGR_ODD_Pos) | (i2sdiv << SPI_I2SCFGR_I2SDIV_Pos)); + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; +} + +/** + * @brief Set linear and parity prescaler. + * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF + * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) +{ + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + + /* Write to SPIx I2SPR */ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV | SPI_I2SCFGR_ODD, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos) | + (PrescalerParity << SPI_I2SCFGR_ODD_Pos)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c new file mode 100644 index 0000000..2af3936 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c @@ -0,0 +1,1415 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_tim.c + * @author MCD Application Team + * @brief TIM LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_tim.h" +#include "stm32h7xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM23) || defined (TIM24) + +/** @addtogroup TIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup TIM_LL_Private_Macros + * @{ + */ +#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + +#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + +#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + +#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + +#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + +#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + +#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + +#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + +#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + +#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) +#if defined(TIM_BDTR_BKBID) + +#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) +#endif /* TIM_BDTR_BKBID */ + +#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + +#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) +#if defined(TIM_BDTR_BKBID) + +#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) +#endif /*TIM_BDTR_BKBID */ + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_LL_Private_Functions TIM Private Functions + * @{ + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set TIMx registers to their reset values. + * @param TIMx Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: invalid TIMx instance + */ +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + + if (TIMx == TIM1) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + } +#if defined(TIM2) + else if (TIMx == TIM2) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + } +#endif /* TIM2 */ +#if defined(TIM3) + else if (TIMx == TIM3) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + } +#endif /* TIM3 */ +#if defined(TIM4) + else if (TIMx == TIM4) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + } +#endif /* TIM4 */ +#if defined(TIM5) + else if (TIMx == TIM5) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + } +#endif /* TIM5 */ +#if defined(TIM6) + else if (TIMx == TIM6) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + } +#endif /* TIM6 */ +#if defined (TIM7) + else if (TIMx == TIM7) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + } +#endif /* TIM7 */ +#if defined(TIM8) + else if (TIMx == TIM8) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); + } +#endif /* TIM8 */ +#if defined(TIM12) + else if (TIMx == TIM12) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); + } +#endif /* TIM12 */ +#if defined(TIM13) + else if (TIMx == TIM13) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); + } +#endif /* TIM13 */ +#if defined(TIM14) + else if (TIMx == TIM14) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); + } +#endif /* TIM14 */ +#if defined(TIM15) + else if (TIMx == TIM15) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); + } +#endif /* TIM15 */ +#if defined(TIM16) + else if (TIMx == TIM16) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); + } +#endif /* TIM16 */ +#if defined(TIM17) + else if (TIMx == TIM17) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); + } +#endif /* TIM17 */ + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) + * @retval None + */ +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = (uint16_t)0x0000; + TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM_InitStruct->RepetitionCounter = 0x00000000U; +} + +/** + * @brief Configure the TIMx time base unit. + * @param TIMx Timer Instance + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + + tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + } + + /* Write to TIMx CR1 */ + LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + + /* Set the Autoreload value */ + LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + + /* Set the Prescaler value */ + LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + } + + /* Generate an update event to reload the Prescaler + and the repetition counter value (if applicable) immediately */ + LL_TIM_GenerateEvent_UPDATE(TIMx); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx output channel configuration data + * structure to their default values. + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) + * @retval None + */ +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->CompareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; +} + +/** + * @brief Configure the TIMx output channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = OC1Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = OC2Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = OC3Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = OC4Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH5: + result = OC5Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH6: + result = OC6Config(TIMx, TIM_OC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMx input channel configuration data + * structure to their default values. + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) + * @retval None + */ +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the TIMx input channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = IC1Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = IC2Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = IC3Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = IC4Config(TIMx, TIM_IC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Fills each TIM_EncoderInitStruct field with its default value + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) + * @retval None + */ +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + /* Set the default configuration */ + TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMx Timer Instance + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Configure TI1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + + /* Configure TI2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Set encoder mode */ + LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx Hall sensor interface configuration data + * structure to their default values. + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) + * @retval None + */ +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + /* Set the default configuration */ + TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_HallSensorInitStruct->CommutationDelay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @note TIMx slave mode controller is configured in reset mode. + Selected internal trigger is TI1F_ED. + * @note Channel 1 is configured as input, IC1 is mapped on TRC. + * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + * between 2 changes on the inputs. It gives information about motor speed. + * @note Channel 2 is configured in output PWM 2 mode. + * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + * @note OC2REF is selected as trigger output on TRGO. + * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used + * when TIMx operates in Hall sensor interface mode. + * @param TIMx Timer Instance + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + uint32_t tmpcr2; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx SMCR register value */ + tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcr2 |= TIM_CR2_TI1S; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcr2 |= LL_TIM_TRGO_OC2REF; + + /* Configure the slave mode controller */ + tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + tmpsmcr |= LL_TIM_TS_TI1F_ED; + tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + + /* Configure input channel 1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + + /* Configure input channel 2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx SMCR */ + LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + /* Write to TIMx CCR2 */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + + return SUCCESS; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; +#if defined(TIM_BDTR_BKBID) + TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; +#endif /*TIM_BDTR_BKBID */ + TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; +#if defined(TIM_BDTR_BKBID) + TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; +#endif /*TIM_BDTR_BKBID */ + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * can be necessary to configure all of them during the first write access to + * the TIMx_BDTR register. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); +#if defined(TIM_BDTR_BKBID) + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); +#else + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); +#endif /*TIM_BDTR_BKBID */ + + if (IS_TIM_BKIN2_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); + assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); +#if defined(TIM_BDTR_BKBID) + assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode)); +#endif /*TIM_BDTR_BKBID */ + + /* Set the BREAK2 input related BDTR bit-fields */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); +#if defined(TIM_BDTR_BKBID) + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); +#endif /*TIM_BDTR_BKBID */ + } + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_LL_Private_Functions TIM Private Functions + * @brief Private functions + * @{ + */ +/** + * @brief Configure the TIMx output channel 1. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 2. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 3. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 4. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 5. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC5E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); + + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 6. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC6E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 1. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC1P | TIM_CCER_CC1NP), + (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 2. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC2P | TIM_CCER_CC2NP), + ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 3. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 4. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC4P | TIM_CCER_CC4NP), + ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); + + return SUCCESS; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 || TIM23 || TIM24 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c new file mode 100644 index 0000000..d4b8d28 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c @@ -0,0 +1,495 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_usart.c + * @author MCD Application Team + * @brief USART LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_usart.h" +#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10) + +/** @addtogroup USART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Macros + * @{ + */ + +#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + +/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + * divided by the smallest oversampling used on the USART (i.e. 8) */ +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U) + +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + +#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) + +#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + +#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + +#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + +#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + +#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + +#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + +#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) + +#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup USART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize USART registers (Registers restored to their default values). + * @param USARTx USART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are de-initialized + * - ERROR: USART registers are not de-initialized + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + + if (USARTx == USART1) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); + } + else if (USARTx == USART2) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + } + else if (USARTx == USART3) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); + } + else if (USARTx == UART4) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); + } + else if (USARTx == UART5) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); + } + else if (USARTx == USART6) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6); + } + else if (USARTx == UART7) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7); + } + else if (USARTx == UART8) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8); + } +#if defined(UART9) + else if (USARTx == UART9) + { + /* Force reset of UART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9); + + /* Release reset of UART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9); + } +#endif /* UART9 */ +#if defined(USART10) + else if (USARTx == USART10) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10); + } +#endif /* USART10 */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize USART registers according to the specified + * parameters in USART_InitStruct. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. + * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). + * @param USARTx USART Instance + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are initialized according to USART_InitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue)); + assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); + assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR1 Configuration --------------------- + * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: + * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value + * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. + */ + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); + + /*---------------------------- USART CR2 Configuration --------------------- + * Configure USARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + */ + LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + + /*---------------------------- USART CR3 Configuration --------------------- + * Configure USARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. + */ + LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + + /*---------------------------- USART BRR Configuration --------------------- + * Retrieve Clock frequency used for USART Peripheral + */ + if (USARTx == USART1) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE); + } + else if (USARTx == USART2) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == USART3) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == UART4) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == UART5) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == USART6) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE); + } + else if (USARTx == UART7) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } + else if (USARTx == UART8) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); + } +#if defined(UART9) + else if (USARTx == UART9) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE); + } +#endif /* UART9 */ +#if defined(USART10) + else if (USARTx == USART10) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE); + } +#endif /* USART10 */ + else + { + /* Nothing to do, as error code is already assigned to ERROR value */ + } + + /* Configure the USART Baud Rate : + - prescaler value is required + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (USART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->PrescalerValue, + USART_InitStruct->OverSampling, + USART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + } + + /*---------------------------- USART PRESC Configuration ----------------------- + * Configure USARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value. + */ + LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue); + } + /* Endif (=> USART not in Disabled state => return ERROR) */ + + return (status); +} + +/** + * @brief Set each @ref LL_USART_InitTypeDef field to default value. + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) +{ + /* Set USART_InitStruct fields to default values */ + USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; + USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; +} + +/** + * @brief Initialize USART Clock related settings according to the + * specified parameters in the USART_ClockInitStruct. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. + * @param USARTx USART Instance + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * that contains the Clock configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check USART Instance and Clock signal output parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + } + /* Else (USART not in Disabled state => return ERROR */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + /* Set LL_USART_ClockInitStruct fields with default values */ + USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + + diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c new file mode 100644 index 0000000..85d0136 --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c @@ -0,0 +1,2143 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_usb.c + * @author MCD Application Team + * @brief USB Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. + + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + + @endverbatim + + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_LL_USB_DRIVER + * @{ + */ + +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + } + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + if (cfg.battery_charging_enable == 0U) + { + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + else + { + /* Deactivate the USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + } + + if (cfg.dma_enable == 1U) + { + /* make sure to reserve 18 fifo Locations for DMA buffers */ + USBx->GDFIFOCFG &= ~(0xFFFFU << 16); + USBx->GDFIFOCFG |= 0x3EEU << 16; + + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + uint32_t ms = 0U; + + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); + } + else + { + return HAL_ERROR; + } + + if (ms == 50U) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } + else + { + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + /* Device mode configuration */ + USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_FlushTxFifo Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode + */ +uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + pSrc++; + pSrc++; + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pDest = dest; + uint32_t pData; + uint32_t i; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval USB Device OUT EP interrupt status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval USB Device IN EP interrupt status + */ +uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS |= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); + + /* Disable Battery chargin detector */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); + + + if ((USBx->CID & (0x1U << 8)) != 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + + /* Make sure the FIFOs are flushed. */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; + + if ((USBx->CID & (0x1U << 8)) != 0U) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + else + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return ret; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = HFIR_48_MHZ; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = HFIR_6_MHZ; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Core speed + * @param USBx Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_HIGH: High speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; + uint32_t HostCoreSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { + if ((USBx->CID & (0x1U << 8)) != 0U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; + } + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; + + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + __IO uint32_t tmpreg; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; + + if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) + { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + + if ((dma == 0U) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + + } + + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /* dma mode */ + { + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + __IO uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + + if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && + (ChannelEna == 0U)) + { + return HAL_OK; + } + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) + { + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; + + (void)USB_EnableGlobalInt(USBx); + + return ret; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @} + */ diff --git a/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c new file mode 100644 index 0000000..865129e --- /dev/null +++ b/FW/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c @@ -0,0 +1,1072 @@ +/** + ****************************************************************************** + * @file stm32h7xx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_ll_utils.h" +#include "stm32h7xx_ll_rcc.h" +#include "stm32h7xx_ll_pwr.h" + +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32H7xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ +#if (STM32H7_DEV_ID == 0x450UL) +#define UTILS_MAX_FREQUENCY_SCALE1 480000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 300000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE3 200000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ +#elif (STM32H7_DEV_ID == 0x480UL) +#define UTILS_MAX_FREQUENCY_SCALE0 280000000U /*!< Maximum frequency for system clock at power scale0, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE1 225000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 160000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE3 88000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ +#elif (STM32H7_DEV_ID == 0x483UL) +#define UTILS_MAX_FREQUENCY_SCALE0 550000000U /*!< Maximum frequency for system clock at power scale0, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE1 200000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 150000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE3 85000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ +#endif /*STM32H7_DEV_ID == 0x450UL*/ + +/* Defines used for PLL range */ +#define UTILS_PLLVCO_INPUT_MIN1 1000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX1 2000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MIN2 2000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX2 4000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MIN3 4000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX3 8000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MIN4 8000000U /*!< Frequency min for the low range PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX4 16000000U /*!< Frequency max for the wide range PLLVCO input, in Hz */ + +#if (POWER_DOMAINS_NUMBER == 3U) +#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_WIDE_OUTPUT_MIN 192000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_WIDE_OUTPUT_MAX 836000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */ +#else +#define UTILS_PLLVCO_MEDIUM_OUTPUT_MIN 150000000U /*!< Frequency min for the medium range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_WIDE_OUTPUT_MIN 128000000U /*!< Frequency min for the wide range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_MEDIUM_OUTPUT_MAX 420000000U /*!< Frequency max for the medium range PLLVCO output, in Hz */ +#define UTILS_PLLVCO_WIDE_OUTPUT_MAX 560000000U /*!< Frequency max for the wide range PLLVCO output, in Hz */ +#endif /*POWER_DOMAINS_NUMBER == 3U*/ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to HCLK Frequency */ +#if (STM32H7_DEV_ID == 0x480UL) +#define UTILS_SCALE0_LATENCY0_FREQ 44000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */ +#define UTILS_SCALE0_LATENCY1_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */ +#define UTILS_SCALE0_LATENCY2_FREQ 132000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */ +#define UTILS_SCALE0_LATENCY3_FREQ 176000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */ +#define UTILS_SCALE0_LATENCY4_FREQ 220000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */ +#define UTILS_SCALE0_LATENCY5_FREQ 264000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 0 */ +#define UTILS_SCALE0_LATENCY6_FREQ 280000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 0 */ + +#define UTILS_SCALE1_LATENCY0_FREQ 42000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ +#define UTILS_SCALE1_LATENCY1_FREQ 84000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 126000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_FREQ 168000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE1_LATENCY4_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ +#define UTILS_SCALE1_LATENCY5_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ + +#define UTILS_SCALE2_LATENCY0_FREQ 34000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ +#define UTILS_SCALE2_LATENCY1_FREQ 68000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 102000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#define UTILS_SCALE2_LATENCY3_FREQ 136000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ +#define UTILS_SCALE2_LATENCY4_FREQ 160000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ + +#define UTILS_SCALE3_LATENCY0_FREQ 22000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ +#define UTILS_SCALE3_LATENCY1_FREQ 44000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ +#define UTILS_SCALE3_LATENCY2_FREQ 66000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ +#define UTILS_SCALE3_LATENCY3_FREQ 88000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ + +#elif (STM32H7_DEV_ID == 0x450UL) + +#define UTILS_SCALE1_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ +#define UTILS_SCALE1_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 240000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ + +#define UTILS_SCALE2_LATENCY0_FREQ 55000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ +#define UTILS_SCALE2_LATENCY1_FREQ 110000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 165000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ +#define UTILS_SCALE2_LATENCY3_FREQ 220000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ + +#define UTILS_SCALE3_LATENCY0_FREQ 45000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ +#define UTILS_SCALE3_LATENCY1_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ +#define UTILS_SCALE3_LATENCY2_FREQ 135000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ +#define UTILS_SCALE3_LATENCY3_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ +#define UTILS_SCALE3_LATENCY4_FREQ 225000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ + +#elif (STM32H7_DEV_ID == 0x483UL) + +#define UTILS_SCALE0_LATENCY0_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 0 */ +#define UTILS_SCALE0_LATENCY1_FREQ 140000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */ +#define UTILS_SCALE0_LATENCY2_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */ +#define UTILS_SCALE0_LATENCY3_FREQ 275000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */ + +#define UTILS_SCALE1_LATENCY0_FREQ 67000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ +#define UTILS_SCALE1_LATENCY1_FREQ 133000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 200000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ + +#define UTILS_SCALE2_LATENCY0_FREQ 50000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ +#define UTILS_SCALE2_LATENCY1_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE2_LATENCY2_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ + +#define UTILS_SCALE3_LATENCY0_FREQ 35000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ +#define UTILS_SCALE3_LATENCY1_FREQ 70000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ +#define UTILS_SCALE3_LATENCY2_FREQ 85000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ + +#endif /*STM32H7_DEV_ID == 0x480UL*/ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_AHB_DIV(__VALUE__) (((__VALUE__) == LL_RCC_AHB_DIV_1) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_2) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_4) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_8) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_16) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_64) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_128) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_256) \ + || ((__VALUE__) == LL_RCC_AHB_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + +#define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB3_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB3_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB3_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB3_DIV_16)) + +#define IS_LL_UTILS_APB4_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB4_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB4_DIV_16)) + +#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 63U)) + +#if (POWER_DOMAINS_NUMBER == 3U) +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U)) +#else +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 420U)) +#endif /*POWER_DOMAINS_NUMBER == 3U*/ + +#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) + +#define IS_LL_UTILS_FRACN_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU) + +#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__, __RANGE__) ( \ +(((__RANGE__) == LL_RCC_PLLINPUTRANGE_1_2) && (UTILS_PLLVCO_INPUT_MIN1 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX1)) || \ +(((__RANGE__) == LL_RCC_PLLINPUTRANGE_2_4) && (UTILS_PLLVCO_INPUT_MIN2 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX2)) || \ +(((__RANGE__) == LL_RCC_PLLINPUTRANGE_4_8) && (UTILS_PLLVCO_INPUT_MIN3 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX3)) || \ +(((__RANGE__) == LL_RCC_PLLINPUTRANGE_8_16) && (UTILS_PLLVCO_INPUT_MIN4 <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX4))) + +#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__, __RANGE__) ( \ +(((__RANGE__) == LL_RCC_PLLVCORANGE_MEDIUM) && (UTILS_PLLVCO_MEDIUM_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_MEDIUM_OUTPUT_MAX)) || \ +(((__RANGE__) == LL_RCC_PLLVCORANGE_WIDE) && (UTILS_PLLVCO_WIDE_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_WIDE_OUTPUT_MAX))) + +#define IS_LL_UTILS_CHECK_VCO_RANGES(__RANGEIN__, __RANGEOUT__) ( \ +(((__RANGEIN__) == LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_MEDIUM)) || \ +(((__RANGEIN__) != LL_RCC_PLLINPUTRANGE_1_2) && ((__RANGEOUT__) == LL_RCC_PLLVCORANGE_WIDE))) + +#if (STM32H7_DEV_ID == 0x450UL) +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ + (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) +#else +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \ + (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ + (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) +#endif /* STM32H7_DEV_ID == 0x450UL */ + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_IsPLLsReady(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ +#if defined (DUAL_CORE) +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param CPU_Frequency Core frequency in Hz + * @note CPU_Frequency can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq + * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency + * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency. + * @retval None + */ +#else +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param CPU_Frequency Core frequency in Hz + * @note CPU_Frequency can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +#endif /* DUAL_CORE */ +void LL_Init1msTick(uint32_t CPU_Frequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(CPU_Frequency, 1000U); +} + + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + uint32_t count = Delay; + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if(count < LL_MAX_DELAY) + { + count++; + } + + while (count != 0U) + { + if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + count--; + } + } +} + +/** + * @} + */ + +#if (STM32H7_DEV_ID == 0x450UL) +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK is 480 MHz(*) and HCLK is 240 MHz. + (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 120 MHz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + (++) +----------------------------------------------------------------------------+ + (++) | Wait states | HCLK clock frequency (MHz) | + (++) | |-----------------------------------------------------------| + (++) | (Latency) | voltage range 1 | voltage range 2 | voltage range 3 | + (++) | | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V | + (++) |----------------|-------------------|-------------------|-------------------| + (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 55 | 0 < HCLK <= 45 | + (++) |----------------|-------------------|-------------------|-------------------| + (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 55 < HCLK <= 110 | 45 < HCLK <= 90 | + (++) |----------------|-------------------|-------------------|-------------------| + (++) |2WS(3CPU cycle) | 140 < HCLK <= 240 | 110 < HCLK <= 165 | 90 < HCLK <= 135 | + (++) |----------------|-------------------|-------------------|-------------------| + (++) |3WS(4CPU cycle) | -- | 165 < HCLK <= 220 | 135 < HCLK <= 180 | + (++) |----------------|-------------------|-------------------|-------------------| + (++) |4WS(5CPU cycle) | -- | -- | 180 < HCLK <= 225 | + (++) +----------------------------------------------------------------------------+ + + (*) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + @endinternal + * @{ + */ + +#elif (STM32H7_DEV_ID == 0x480UL) +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK is 280 MHz and HCLK is 280 MHz. + (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 140 MHz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + (++) +------------------------------------------------------------------------------------------------+ + (++) | Wait states | HCLK clock frequency (MHz) | + (++) | |-------------------------------------------------------------------------------| + (++) | (Latency) | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 | + (++) | | 1.26V - 1.35V | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |0WS(1CPU cycle) | 0 < HCLK <= 44 | 0 < HCLK <= 42 | 0 < HCLK <= 34 | 0 < HCLK <= 22 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |1WS(2CPU cycle) | 44 < HCLK <= 88 | 42 < HCLK <= 84 | 34 < HCLK <= 68 | 22 < HCLK <= 44 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |2WS(3CPU cycle) | 88 < HCLK <= 132 | 84 < HCLK <= 126 | 68 < HCLK <= 102 | 44 < HCLK <= 66 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |3WS(4CPU cycle) | 132 < HCLK <= 176 | 126 < HCLK <= 168 | 102 < HCLK <= 136 | 66 < HCLK <= 88 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |4WS(5CPU cycle) | 176 < HCLK <= 220 | 168 < HCLK <= 210 | 136 < HCLK <= 160 | -- | + (++) +------------------------------------------------------------------------------------------------+ + (++) |5WS(6CPU cycle) | 220 < HCLK <= 264 | 210 < HCLK <= 225 | -- | -- | + (++) +------------------------------------------------------------------------------------------------+ + (++) |6WS(7CPU cycle) | 264 < HCLK <= 280 | -- | -- | -- | + (++) +------------------------------------------------------------------------------------------------+ + (++) |7WS(8CPU cycle) | -- | -- | -- | -- | + (++) +------------------------------------------------------------------------------------------------+ + + @endinternal + * @{ + */ + +#elif (STM32H7_DEV_ID == 0x483UL) +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK is 550 MHz(*) and HCLK is 275 MHz. + (+) The maximum frequency of the PCLK1, PCLK2, PCLK3 and PCLK4 is 137.5 MHz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + (++) +------------------------------------------------------------------------------------------------+ + (++) | Wait states | HCLK clock frequency (MHz) | + (++) | |-------------------------------------------------------------------------------| + (++) | (Latency) | voltage range 0 | voltage range 1 | voltage range 2 | voltage range 3 | + (++) | | 1.26V - 1.40V | 1.15V - 1.26V | 1.05V - 1.15V | 0.95V - 1.05V | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |0WS(1CPU cycle) | 0 < HCLK <= 70 | 0 < HCLK <= 67 | 0 < HCLK <= 50 | 0 < HCLK <= 35 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |1WS(2CPU cycle) | 70 < HCLK <= 140 | 67 < HCLK <= 133 | 50 < HCLK <= 100 | 35 < HCLK <= 70 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |2WS(3CPU cycle) | 140 < HCLK <= 210 | 133 < HCLK <= 200 | 100 < HCLK <= 150 | 70 < HCLK <= 85 | + (++) |----------------|-------------------|-------------------|-------------------|-------------------| + (++) |3WS(4CPU cycle) | 210 < HCLK <= 275 | -- | -- | -- | + (++) +----------------|-------------------|-------------------|-------------------|-------------------| + + (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + @endinternal + * @{ + */ +#endif /* STM32H7_DEV_ID == 0x450UL */ + +#if defined (DUAL_CORE) +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param CPU_Frequency Core frequency in Hz + * @note CPU_Frequency can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq + * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency + * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency. + * @retval None + */ +#else +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param CPU_Frequency Core frequency in Hz + * @note CPU_Frequency can be calculated thanks to RCC helper macro or function + * @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +#endif /* DUAL_CORE */ +void LL_SetSystemCoreClock(uint32_t CPU_Frequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = CPU_Frequency; +} + +/** + * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) + * - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reach (PLLVCO_output / PLLP) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; +#ifdef USE_FULL_ASSERT + uint32_t vcoinput_freq, vcooutput_freq; +#endif + uint32_t pllfreq, hsi_clk; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); + + hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos)); + + /* Check VCO Input frequency */ +#ifdef USE_FULL_ASSERT + vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM; +#endif + assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input)); + + /* Check VCO Output frequency */ +#ifdef USE_FULL_ASSERT + vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL); +#endif + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output)); + + /* Check VCO Input ranges */ + assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output)); + + /* Check if one of the PLL is enabled */ + if(UTILS_IsPLLsReady() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if(LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL1P_Enable(); + LL_RCC_PLL1FRACN_Enable(); + LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI); + LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input); + LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output); + LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM); + LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN); + LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP) + * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM) + * - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(***) (PLLVCO_output = PLLVCO_input * PLLN) + * - PLLP: ensure that max frequency at 550000000 Hz(*), 480000000 Hz(**) or 280000000 Hz(***) is reached (PLLVCO_output / PLLP) + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + * + * (*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. + * (**) : For stm32h74xxx and stm32h75xxx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. + * (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. + * + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; +#ifdef USE_FULL_ASSERT + uint32_t vcoinput_freq, vcooutput_freq; +#endif + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check VCO Input frequency */ +#ifdef USE_FULL_ASSERT + vcoinput_freq = HSEFrequency / UTILS_PLLInitStruct->PLLM; +#endif + assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input)); + + /* Check VCO output frequency */ +#ifdef USE_FULL_ASSERT + vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U); +#endif + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output)); + + /* Check VCO Input/output ranges compatibility */ + assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output)); + + /* Check if one of the PLL is enabled */ + if(UTILS_IsPLLsReady() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if(LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if(HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL1P_Enable(); + LL_RCC_PLL1FRACN_Enable(); + LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE); + LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input); + LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output); + LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM); + LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN); + LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP); + LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLK_Frequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) +{ + ErrorStatus status = SUCCESS; + uint32_t timeout; + uint32_t getlatency; + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + + + /* Frequency cannot be equal to 0 */ + if (HCLK_Frequency == 0U) + { + status = ERROR; + } + else + { +#if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x483UL) + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0) + { +#if (STM32H7_DEV_ID == 0x480UL) + if((HCLK_Frequency > UTILS_SCALE0_LATENCY5_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY6_FREQ)) + { + /* 264 < HCLK <= 280 => 6WS (7 CPU cycles) */ + latency = LL_FLASH_LATENCY_6; + } + else if((HCLK_Frequency > UTILS_SCALE0_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY5_FREQ)) + { + /* 220 < HCLK <= 264 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if((HCLK_Frequency > UTILS_SCALE0_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY4_FREQ)) + { + /* 176 < HCLK <= 220 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ)) +#elif (STM32H7_DEV_ID == 0x483UL) + if((HCLK_Frequency > UTILS_SCALE0_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY3_FREQ)) +#endif /* STM32H7_DEV_ID == 0x480UL */ + { + /* 132 < HCLK <= 176 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if((HCLK_Frequency > UTILS_SCALE0_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY2_FREQ)) + { + /* 88 < HCLK <= 132 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else if((HCLK_Frequency > UTILS_SCALE0_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE0_LATENCY1_FREQ)) + { + /* 44 < HCLK <= 88 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else if(HCLK_Frequency <= UTILS_SCALE0_LATENCY0_FREQ) + { + /* HCLK <= 44 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ + } + else + { + status = ERROR; + } + } +#if (STM32H7_DEV_ID == 0x480UL) + else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY5_FREQ)) + { + /* 210 < HCLK <= 225 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ)) + { + /* 168 < HCLK <= 210 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ)) + { + /* 126 < HCLK <= 168 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)) +#else + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)) +#endif /* STM32H7_DEV_ID == 0x480UL */ +#else + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)) +#endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x483UL */ + { + /* 140 < HCLK <= 210 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)) + { + /* 70 < HCLK <= 140 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else if(HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ) + { + /* HCLK <= 70 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ + } + else + { + status = ERROR; + } + } + else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) + { +#if (STM32H7_DEV_ID == 0x480UL) || (STM32H7_DEV_ID == 0x450UL) +#if (STM32H7_DEV_ID == 0x480UL) + if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY4_FREQ)) + { + /* 136 < HCLK <= 160 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ)) +#else + if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ)) +#endif /* STM32H7_DEV_ID == 0x480UL */ + { + /* 165 < HCLK <= 220 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ)) +#else + if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ)) +#endif /* STM32H7_DEV_ID == 0x480UL || STM32H7_DEV_ID == 0x450UL */ + { + /* 110 < HCLK <= 165 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else if((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ)) + { + /* 55 < HCLK <= 110 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else if(HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ) + { + /* HCLK <= 55 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ + } + else + { + status = ERROR; + } + } + else /* Scale 3 */ + { +#if (STM32H7_DEV_ID == 0x450UL) || (STM32H7_DEV_ID == 0x480UL) +#if (STM32H7_DEV_ID == 0x450UL) + if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY4_FREQ)) + { + /* 180 < HCLK <= 225 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ)) +#else + if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ)) +#endif /*STM32H7_DEV_ID == 0x450UL*/ + { + /* 135 < HCLK <= 180 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ)) +#else + if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ)) +#endif /* STM32H7_DEV_ID == 0x450UL || STM32H7_DEV_ID == 0x480UL */ + { + /* 90 < HCLK <= 135 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else if((HCLK_Frequency > UTILS_SCALE3_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ)) + { + /* 45 < HCLK <= 90 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else if(HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ) + { + /* HCLK <= 45 => 0WS (1 CPU cycles) : Do nothing keep latency to default LL_FLASH_LATENCY_0 */ + } + else + { + status = ERROR; + } + } + + if(status == SUCCESS) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0U)); + + if(getlatency != latency) + { + status = ERROR; + } + } + } + + return status; +} + + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ + + +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); + assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN)); + + pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP); + + return pllfreq; +} + +/** + * @brief Check that all PLLs are ready therefore configuration can be done + * @retval An ErrorStatus enumeration value: + * - SUCCESS: All PLLs are ready so configuration can be done + * - ERROR: One PLL at least is busy + */ +static ErrorStatus UTILS_IsPLLsReady(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if one of the PLL1 is busy */ + if(LL_RCC_PLL1_IsReady() != 0U) + { + /* PLL1 configuration cannot be done */ + status = ERROR; + } + + /* Check if one of the PLL2 is busy */ + if(LL_RCC_PLL2_IsReady() != 0U) + { + /* PLL2 configuration cannot be done */ + status = ERROR; + } + + /* Check if one of the PLL3 is busy */ + if(LL_RCC_PLL3_IsReady() != 0U) + { + /* PLL3 configuration cannot be done */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t new_hclk_frequency; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider)); + assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider)); + + /* Calculate the new HCLK frequency */ + new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (SystemD2Clock < new_hclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(new_hclk_frequency); + } + + /* Update system clock configuration */ + if(status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL1_Enable(); + while (LL_RCC_PLL1_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Set All APBxPrescaler to the Highest Divider */ + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16); + LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16); + LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16); + LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16); + + /* Set SYS prescaler*/ + LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider); + + /* Set AHB prescaler*/ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + + /* Sysclk activation on the main PLL */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APBn prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider); + LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider); + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (SystemD2Clock > new_hclk_frequency) + { + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(new_hclk_frequency); + } + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (SYSCLK_Frequency >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + + /* Update SystemCoreClock variable */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + LL_SetSystemCoreClock(SystemD2Clock); +#else + LL_SetSystemCoreClock(SYSCLK_Frequency); +#endif /* DUAL_CORE && CORE_CM4 */ + + } + + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/FW/FATFS/App/fatfs.c b/FW/FATFS/App/fatfs.c new file mode 100644 index 0000000..4d25166 --- /dev/null +++ b/FW/FATFS/App/fatfs.c @@ -0,0 +1,58 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file fatfs.c + * @brief Code for fatfs applications + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +#include "fatfs.h" + +uint8_t retUSBH; /* Return value for USBH */ +char USBHPath[4]; /* USBH logical drive path */ +FATFS USBHFatFS; /* File system object for USBH logical drive */ +FIL USBHFile; /* File object for USBH */ + +/* USER CODE BEGIN Variables */ +void MX_FATFS_DeInit(void) +{ + /* 解除所有挂载的卷 */ + f_mount(NULL, "", 1); +} +/* USER CODE END Variables */ + +void MX_FATFS_Init(void) +{ + /*## FatFS: Link the USBH driver ###########################*/ + retUSBH = FATFS_LinkDriver(&USBH_Driver, USBHPath); + + /* USER CODE BEGIN Init */ + /* additional user code for init */ + /* USER CODE END Init */ +} + +/** + * @brief Gets Time from RTC + * @param None + * @retval Time in DWORD + */ +DWORD get_fattime(void) +{ + /* USER CODE BEGIN get_fattime */ + return 0; + /* USER CODE END get_fattime */ +} + +/* USER CODE BEGIN Application */ + +/* USER CODE END Application */ diff --git a/FW/FATFS/App/fatfs.h b/FW/FATFS/App/fatfs.h new file mode 100644 index 0000000..7c08958 --- /dev/null +++ b/FW/FATFS/App/fatfs.h @@ -0,0 +1,47 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file fatfs.h + * @brief Header for fatfs applications + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __fatfs_H +#define __fatfs_H +#ifdef __cplusplus + extern "C" { +#endif + +#include "ff.h" +#include "ff_gen_drv.h" +#include "usbh_diskio.h" /* defines USBH_Driver as external */ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern uint8_t retUSBH; /* Return value for USBH */ +extern char USBHPath[4]; /* USBH logical drive path */ +extern FATFS USBHFatFS; /* File system object for USBH logical drive */ +extern FIL USBHFile; /* File object for USBH */ + +void MX_FATFS_Init(void); + +/* USER CODE BEGIN Prototypes */ +void MX_FATFS_DeInit(void); +/* USER CODE END Prototypes */ +#ifdef __cplusplus +} +#endif +#endif /*__fatfs_H */ diff --git a/FW/FATFS/Target/ffconf.h b/FW/FATFS/Target/ffconf.h new file mode 100644 index 0000000..a6f1201 --- /dev/null +++ b/FW/FATFS/Target/ffconf.h @@ -0,0 +1,271 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * FatFs - Generic FAT file system module R0.12c (C)ChaN, 2017 + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +#ifndef _FFCONF +#define _FFCONF 68300 /* Revision ID */ + +/*-----------------------------------------------------------------------------/ +/ Additional user header to be used +/-----------------------------------------------------------------------------*/ +#include "main.h" +#include "stm32h7xx_hal.h" +#include "usbh_core.h" +#include "usbh_msc.h" +/* Handle for USB Host */ +#define hUSB_Host hUsbHostFS + +/*-----------------------------------------------------------------------------/ +/ Function Configurations +/-----------------------------------------------------------------------------*/ + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + +#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */ +/* This option switches string functions, f_gets(), f_putc(), f_puts() and +/ f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + +#define _USE_FIND 0 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + +#define _USE_MKFS 1 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + +#define _USE_FASTSEEK 1 +/* This option switches fast seek feature. (0:Disable or 1:Enable) */ + +#define _USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + +#define _USE_CHMOD 0 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also _FS_READONLY needs to be 0 to enable this option. */ + +#define _USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + +#define _USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + +/*-----------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/-----------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 1 - ASCII (No extended character. Non-LFN cfg. only) +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +*/ + +#define _USE_LFN 0 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN switches the support of long file name (LFN). +/ +/ 0: Disable support of LFN. _MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added +/ to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and +/ additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255. +/ It should be set 255 to support full featured LFN operations. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree(), must be added to the project. */ + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16) +/ To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1. +/ This option also affects behavior of string I/O functions. */ + +#define _STRF_ENCODE 3 +/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to +/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf(). +/ +/ 0: ANSI/OEM +/ 1: UTF-16LE +/ 2: UTF-16BE +/ 3: UTF-8 +/ +/ This option has no effect when _LFN_UNICODE == 0. */ + +#define _FS_RPATH 0 /* 0 to 2 */ +/* This option configures support of relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/----------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + +/* USER CODE BEGIN Volumes */ +#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */ +#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3" +/* _STR_VOLUME_ID switches string support of volume ID. +/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. _VOLUME_STRS defines the drive ID strings for each +/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for +/ the drive ID strings are: A-Z and 0-9. */ +/* USER CODE END Volumes */ + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Multiple partition */ +/* This option switches support of multi-partition on a physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When multi-partition is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ function will be available. */ +#define _MIN_SS 512 /* 512, 1024, 2048 or 4096 */ +#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */ +/* These options configure the range of sector size to be supported. (512, 1024, +/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured +/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the +/ disk_ioctl() function. */ + +#define _USE_TRIM 0 +/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + +#define _FS_NOFSINFO 0 /* 0,1,2 or 3 */ +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + +/*---------------------------------------------------------------------------/ +/ System Configurations +/----------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the file system object (FATFS) is used for the file data transfer. */ + +#define _FS_EXFAT 0 +/* This option switches support of exFAT file system. (0:Disable or 1:Enable) +/ When enable exFAT, also LFN needs to be enabled. (_USE_LFN >= 1) +/ Note that enabling exFAT discards C89 compatibility. */ + +#define _FS_NORTC 0 +#define _NORTC_MON 6 +#define _NORTC_MDAY 4 +#define _NORTC_YEAR 2015 +/* The option _FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set _FS_NORTC = 1 to disable +/ the timestamp function. All objects modified by FatFs will have a fixed timestamp +/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time. +/ To enable timestamp function (_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to get current time form real-time clock. _NORTC_MON, +/ _NORTC_MDAY and _NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (_FS_READONLY = 1). */ + +#define _FS_LOCK 2 /* 0:Disable or >=1:Enable */ +/* The option _FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when _FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + +#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ +#define _SYNC_t NULL +/* The option _FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The _FS_TIMEOUT defines timeout period in unit of time tick. +/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +/* define the ff_malloc ff_free macros as standard malloc free */ +#if !defined(ff_malloc) && !defined(ff_free) +#include +#define ff_malloc malloc +#define ff_free free +#endif + +#endif /* _FFCONF */ diff --git a/FW/FATFS/Target/usbh_diskio.c b/FW/FATFS/Target/usbh_diskio.c new file mode 100644 index 0000000..09f35ac --- /dev/null +++ b/FW/FATFS/Target/usbh_diskio.c @@ -0,0 +1,267 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbh_diskio.c (based on usbh_diskio_template.c v2.0.2) + * @brief USB Host Disk I/O driver + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* USER CODE BEGIN firstSection */ +/* can be used to modify / undefine following code or add new definitions */ +/* USER CODE END firstSection */ + +/* Includes ------------------------------------------------------------------*/ +#include "ff_gen_drv.h" +#include "usbh_diskio.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#define USB_DEFAULT_BLOCK_SIZE 512 + +/* Private variables ---------------------------------------------------------*/ +extern USBH_HandleTypeDef hUSB_Host; + +/* Private function prototypes -----------------------------------------------*/ +DSTATUS USBH_initialize (BYTE); +DSTATUS USBH_status (BYTE); +DRESULT USBH_read (BYTE, BYTE*, DWORD, UINT); + +#if _USE_WRITE == 1 + DRESULT USBH_write (BYTE, const BYTE*, DWORD, UINT); +#endif /* _USE_WRITE == 1 */ + +#if _USE_IOCTL == 1 + DRESULT USBH_ioctl (BYTE, BYTE, void*); +#endif /* _USE_IOCTL == 1 */ + +const Diskio_drvTypeDef USBH_Driver = +{ + USBH_initialize, + USBH_status, + USBH_read, +#if _USE_WRITE == 1 + USBH_write, +#endif /* _USE_WRITE == 1 */ +#if _USE_IOCTL == 1 + USBH_ioctl, +#endif /* _USE_IOCTL == 1 */ +}; + +/* USER CODE BEGIN beforeFunctionSection */ +/* can be used to modify / undefine following code or add new code */ +/* USER CODE END beforeFunctionSection */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Initializes a Drive + * @param lun : lun id + * @retval DSTATUS: Operation status + */ +DSTATUS USBH_initialize(BYTE lun) +{ + /* CAUTION : USB Host library has to be initialized in the application */ + + return RES_OK; +} + +/** + * @brief Gets Disk Status + * @param lun : lun id + * @retval DSTATUS: Operation status + */ +DSTATUS USBH_status(BYTE lun) +{ + DRESULT res = RES_ERROR; + + if(USBH_MSC_UnitIsReady(&hUSB_Host, lun)) + { + res = RES_OK; + } + else + { + res = RES_ERROR; + } + + return res; +} + +/* USER CODE BEGIN beforeReadSection */ +/* can be used to modify previous code / undefine following code / add new code */ +/* USER CODE END beforeReadSection */ + +/** + * @brief Reads Sector(s) + * @param lun : lun id + * @param *buff: Data buffer to store read data + * @param sector: Sector address (LBA) + * @param count: Number of sectors to read (1..128) + * @retval DRESULT: Operation result + */ +DRESULT USBH_read(BYTE lun, BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + MSC_LUNTypeDef info; + + if(USBH_MSC_Read(&hUSB_Host, lun, sector, buff, count) == USBH_OK) + { + res = RES_OK; + } + else + { + USBH_MSC_GetLUNInfo(&hUSB_Host, lun, &info); + + switch (info.sense.asc) + { + case SCSI_ASC_LOGICAL_UNIT_NOT_READY: + case SCSI_ASC_MEDIUM_NOT_PRESENT: + case SCSI_ASC_NOT_READY_TO_READY_CHANGE: + USBH_ErrLog ("USB Disk is not ready!"); + res = RES_NOTRDY; + break; + + default: + res = RES_ERROR; + break; + } + } + + return res; +} + +/* USER CODE BEGIN beforeWriteSection */ +/* can be used to modify previous code / undefine following code / add new code */ +/* USER CODE END beforeWriteSection */ + +/** + * @brief Writes Sector(s) + * @param lun : lun id + * @param *buff: Data to be written + * @param sector: Sector address (LBA) + * @param count: Number of sectors to write (1..128) + * @retval DRESULT: Operation result + */ +#if _USE_WRITE == 1 +DRESULT USBH_write(BYTE lun, const BYTE *buff, DWORD sector, UINT count) +{ + DRESULT res = RES_ERROR; + MSC_LUNTypeDef info; + + if(USBH_MSC_Write(&hUSB_Host, lun, sector, (BYTE *)buff, count) == USBH_OK) + { + res = RES_OK; + } + else + { + USBH_MSC_GetLUNInfo(&hUSB_Host, lun, &info); + + switch (info.sense.asc) + { + case SCSI_ASC_WRITE_PROTECTED: + USBH_ErrLog("USB Disk is Write protected!"); + res = RES_WRPRT; + break; + + case SCSI_ASC_LOGICAL_UNIT_NOT_READY: + case SCSI_ASC_MEDIUM_NOT_PRESENT: + case SCSI_ASC_NOT_READY_TO_READY_CHANGE: + USBH_ErrLog("USB Disk is not ready!"); + res = RES_NOTRDY; + break; + + default: + res = RES_ERROR; + break; + } + } + + return res; +} +#endif /* _USE_WRITE == 1 */ + +/* USER CODE BEGIN beforeIoctlSection */ +/* can be used to modify previous code / undefine following code / add new code */ +/* USER CODE END beforeIoctlSection */ + +/** + * @brief I/O control operation + * @param lun : lun id + * @param cmd: Control code + * @param *buff: Buffer to send/receive control data + * @retval DRESULT: Operation result + */ +#if _USE_IOCTL == 1 +DRESULT USBH_ioctl(BYTE lun, BYTE cmd, void *buff) +{ + DRESULT res = RES_ERROR; + MSC_LUNTypeDef info; + + switch (cmd) + { + /* Make sure that no pending write process */ + case CTRL_SYNC: + res = RES_OK; + break; + + /* Get number of sectors on the disk (DWORD) */ + case GET_SECTOR_COUNT : + if(USBH_MSC_GetLUNInfo(&hUSB_Host, lun, &info) == USBH_OK) + { + *(DWORD*)buff = info.capacity.block_nbr; + res = RES_OK; + } + else + { + res = RES_ERROR; + } + break; + + /* Get R/W sector size (WORD) */ + case GET_SECTOR_SIZE : + if(USBH_MSC_GetLUNInfo(&hUSB_Host, lun, &info) == USBH_OK) + { + *(DWORD*)buff = info.capacity.block_size; + res = RES_OK; + } + else + { + res = RES_ERROR; + } + break; + + /* Get erase block size in unit of sector (DWORD) */ + case GET_BLOCK_SIZE : + + if(USBH_MSC_GetLUNInfo(&hUSB_Host, lun, &info) == USBH_OK) + { + *(DWORD*)buff = info.capacity.block_size / USB_DEFAULT_BLOCK_SIZE; + res = RES_OK; + } + else + { + res = RES_ERROR; + } + break; + + default: + res = RES_PARERR; + } + + return res; +} +#endif /* _USE_IOCTL == 1 */ + +/* USER CODE BEGIN lastSection */ +/* can be used to modify / undefine previous code or add new code */ +/* USER CODE END lastSection */ diff --git a/FW/FATFS/Target/usbh_diskio.h b/FW/FATFS/Target/usbh_diskio.h new file mode 100644 index 0000000..b76ea8d --- /dev/null +++ b/FW/FATFS/Target/usbh_diskio.h @@ -0,0 +1,40 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usbh_diskio.h (based on usbh_diskio_template.h v2.0.2) + * @brief Header for usbh_diskio.c module + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USBH_DISKIO_H +#define __USBH_DISKIO_H + +/* USER CODE BEGIN firstSection */ +/* can be used to modify / undefine following code or add new definitions */ +/* USER CODE END firstSection */ + +/* Includes ------------------------------------------------------------------*/ +#include "usbh_core.h" +#include "usbh_msc.h" +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +extern const Diskio_drvTypeDef USBH_Driver; + +/* USER CODE BEGIN lastSection */ +/* can be used to modify / undefine previous code or add new definitions */ +/* USER CODE END lastSection */ + +#endif /* __USBH_DISKIO_H */ + diff --git a/MyCode/Gui/AboutUs.cpp b/MyCode/Gui/AboutUs.cpp new file mode 100644 index 0000000..289b0f1 --- /dev/null +++ b/MyCode/Gui/AboutUs.cpp @@ -0,0 +1,120 @@ +#include "AboutUs.h" + +void TAboutUs::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("关于我们", Caption.Text); + Caption.Visible = 1; + + OnActive = 0; + +} + +void TAboutUs::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TAboutUs::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TAboutUs::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + +void TAboutUs::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + ReDrawInf(); +} + +void TAboutUs::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + ReDrawInf(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + + ReDrawInf(); + } +} + +//______________________________________________________________________________________________________________________________ + +void TAboutUs::ReDrawInf() +{ + TextRender_string24(100, 86, clNearBlack, "公司名称: "); + TextRender_string24(100, 116, clNearBlack, "公司地址:"); + + TextRender_string24(100, 146, clNearBlack, "历史:"); + TextRender_string24(100, 176, clNearBlack, "简介:"); + + TextRender_string24(100, 206, clNearBlack, "业务联系:"); + TextRender_string24(100, 246, clNearBlack, "技术服务电话:"); + +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TAboutUs::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + + switch(aKey){ + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + + return aMsg; +} + diff --git a/MyCode/Gui/AboutUs.h b/MyCode/Gui/AboutUs.h new file mode 100644 index 0000000..f250786 --- /dev/null +++ b/MyCode/Gui/AboutUs.h @@ -0,0 +1,52 @@ +#ifndef ABOUTUS_H_ +#define ABOUTUS_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TAboutUs{ + public: + unsigned int OnActive; + public: + TStaticText Caption; + + u32 Color; + + int TabOrder; + TRect Bound; + TRect Content; + public: + TAboutUs(){}; + TAboutUs(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void FullRedraw(int Prm); + void ReDraw(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void LoadData(); + void ReDrawInf(); + + int ExtRequst(unsigned char Prm){return 0;} + +}; + + + +#endif + diff --git a/MyCode/Gui/AddrAssign.cpp b/MyCode/Gui/AddrAssign.cpp new file mode 100644 index 0000000..ca05ede --- /dev/null +++ b/MyCode/Gui/AddrAssign.cpp @@ -0,0 +1,505 @@ +#include "RuntimeData.h" +#include "AddrAssign.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + + +void TAddrAssign::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+510,Top,286, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + RectPanel.Set(60,140,720,320); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("系统调试->指派终端设备地址", Caption.Text); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + CtlIndex = 0; + CtlMacIndex =0; + ByWhat =0; + + OnActive = 0; + IsFastCmd = 0; +} + +void TAddrAssign::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TAddrAssign::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TAddrAssign::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TAddrAssign::DrawCaption2(void) +{ + TMyString::sFromStr("按TAB键切换写入方式", SText.Text); + SText.Show(); +} + +void TAddrAssign::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); +} + +void TAddrAssign::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + aPanel->Show(); + MacShow(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + MacShow(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TAddrAssign::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ + +void TAddrAssign::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<3;i++)aPanel->Edit[i].Selected = 0; + for(i=11; i<14;i++)aPanel->Edit[i].Selected = 0; + for(i=0; i<3;i++)aPanel->Btn[i].Selected = 0; + if(ByWhat){ + switch(CtlMacIndex){ + case 0: + aPanel->Edit[11].Selected = 1; + break; + case 1: + aPanel->Edit[12].Selected = 1; + break; + case 2: + aPanel->Edit[13].Selected = 1; + break; + case 3: + aPanel->Btn[1].Selected = 1; + break; + case 4: + aPanel->Btn[2].Selected = 1; + break; + default: + + break; + } + }else{ + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Edit[2].Selected = 1; + break; + case 3: + aPanel->Btn[0].Selected = 1; + break; + default: + + break; + } + } +} + +void TAddrAssign::MacShow() +{ + int x,y, pst,i; + unsigned int tClr, bClr; + char t; + + x = RectPanel.Left + 309; + y = RectPanel.Top + 76; + if(aPanel->Edit[13].Selected){ + bClr = clDeepBlue; + tClr = clNearWhite; + }else{ + bClr = clNearWhite; + tClr = clNearBlack; + } + TEdit::sDrawSelf(x,y,339,36,bClr); + x = x + 3; + y = y + 6; + for(i=0; i<7; i++){ + t = aPanel->Edit[13].Str.Text[i*3 +0]; + if(t){ + gui_write_EN2412(x, y, tClr, t); + }else{ + gui_write_EN2412(x, y, tClr, 'x'); + } + x +=12; + t = aPanel->Edit[13].Str.Text[i*3 +1]; + if(t){ + gui_write_EN2412(x, y, tClr, t); + }else{ + gui_write_EN2412(x, y, tClr, 'x'); + } + x +=12; + t = aPanel->Edit[13].Str.Text[i*3 +2]; + if(t){ + gui_write_EN2412(x, y, tClr, t); + }else{ + gui_write_EN2412(x, y, tClr, 'x'); + } + x +=12; + if(i<6)gui_write_EN2412(x, y, tClr, '-'); + x +=12; + } + if(aPanel->Edit[13].Selected){ + pst = aPanel->Edit[13].Pst / 3 * 4; + pst += aPanel->Edit[13].Pst % 3; + x = RectPanel.Left + 309 + 3; + x = (pst + 1) * 12 + x; + VertLineRender(x, y, 24, tClr); + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TAddrAssign::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + if(ByWhat){ + //Mac Type + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(CtlMacIndex < 3){ + if(CtlMacIndex == 0){ + aPanel->Edit[11].KeyIn(aKey); + aPanel->Edit[11].ReDraw(); + }else + if(CtlMacIndex == 1){ + aPanel->Edit[12].KeyIn(aKey); + aPanel->Edit[12].ReDraw(); + }else + if(CtlMacIndex == 2){ + aPanel->Edit[13].KeyIn(aKey); + MacShow(); + } + } + if(CtlMacIndex == 4){ + if(aKey == VK_RIGHT){ + CtlMacIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + MacShow(); + } + }else + if(CtlMacIndex == 5){ + if(aKey == VK_LEFT){ + CtlMacIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + MacShow(); + } + } + } + + if(aKey == VK_UP){ + if(CtlMacIndex >0){ + CtlMacIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + MacShow(); + } + }else + if(aKey == VK_DOWN){ + if(CtlMacIndex <4){ + CtlMacIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + MacShow(); + } + }else + if(aKey == VK_TAB){ + if(ByWhat){ + ByWhat =0; + }else{ + ByWhat =1; + } + Check4Selected(); + aPanel->ReDrawItems(); + MacShow(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + SendCmd(); + } + + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + }else{ + //Not Mac Type + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(CtlIndex < 3){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].ReDraw(); + } + } + + if(aKey == VK_UP){ + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + }else + if(aKey == VK_DOWN){ + if(CtlIndex <3){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + }else + if(aKey == VK_TAB){ + if(ByWhat){ + ByWhat =0; + }else{ + ByWhat =1; + } + Check4Selected(); + aPanel->ReDrawItems(); + MacShow(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + SendCmd(); + } + + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + + return aMsg; +} + +void TAddrAssign::PanelCanvasOut() +{ + VertLineRender(RectPanel.Left + 170, RectPanel.Top+6, 140, clSilver); +} + +void TAddrAssign::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[0].Init(11,3,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[1].Init(11,35,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[2].Init(11,67,70,30,x,yt,clNearBlack,clFrmFace); + + aPanel->SText[11].Init(216,3,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[12].Init(216,35,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[13].Init(204,67,70,30,x,yt,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路号", aPanel->SText[0].Text); + TMyString::sFromStr("原地址", aPanel->SText[1].Text); + TMyString::sFromStr("新地址", aPanel->SText[2].Text); + + TMyString::sFromStr("回路号", aPanel->SText[11].Text); + TMyString::sFromStr(" 地址", aPanel->SText[12].Text); + TMyString::sFromStr("MAC 6:0", aPanel->SText[13].Text); + + aPanel->Edit[0].Init(101,3,50,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(101,35,50,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(101,67,50,30,x,yt,clNearBlack,clNearWhite); + + aPanel->Edit[11].Init(310,3,50,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[12].Init(310,35,50,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[13].Init(310,67,50,30,x,yt,clNearBlack,clNearWhite); + + aPanel->Btn[0].Init(32,122,110,30,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[1].Init(310,122,110,30,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[2].Init(430,122,110,30,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[0].Caption.FromStr("更改地址"); + aPanel->Btn[1].Caption.FromStr("读取MAC"); + aPanel->Btn[2].Caption.FromStr("写入地址"); + + + for(i=0; i<3;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + for(i=0; i<3;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(2); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("01"); + aPanel->Edit[i].Pst = 1; + } + for(i=11; i<14;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(5); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + aPanel->Edit[i].Pst = 1; + } + aPanel->Edit[13].Visible = 0; + aPanel->Edit[13].SetMaxLen(21); + aPanel->Edit[13].Str.FromStr("001002003004005006007"); + aPanel->Edit[13].Pst = 20; + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + + MacShow(); +} + +void TAddrAssign::SendCmd() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0, aP1; + + Len =5; + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP0 = cVal; + + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP1 = cVal; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + aIde.BitF.Cmd = cVal; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + Data[0] = 0; + + //InnerCan.CmdSendCustom(aIde, Data, Len); + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + + + + + + diff --git a/MyCode/Gui/AddrAssign.h b/MyCode/Gui/AddrAssign.h new file mode 100644 index 0000000..7d6604a --- /dev/null +++ b/MyCode/Gui/AddrAssign.h @@ -0,0 +1,85 @@ +#ifndef ADDRASSIGN_H_ +#define ADDRASSIGN_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TAddrAssign{ + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + + TRect Content; + TRect RectPanel; + + TMyString Str; + + unsigned int CtlMacIndex; + unsigned int CtlIndex; + unsigned int ByWhat; + union{ + unsigned short sVal[4]; + unsigned char cVal[8]; + }RecData; + unsigned short Scaling[4]; + int IsFastCmd; + unsigned char Data[8]; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TAddrAssign(){}; + TAddrAssign(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + void MacShow(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + + void SendCmd(); + void SendFastCmd(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + + + diff --git a/MyCode/Gui/Allow.cpp b/MyCode/Gui/Allow.cpp new file mode 100644 index 0000000..dd29b3d --- /dev/null +++ b/MyCode/Gui/Allow.cpp @@ -0,0 +1,429 @@ +#include "Allow.h" +#include "Runtime.h" +#include "server.h" + +void TAllow::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + CtlIndex = 1; + IsShow = 0; + IsPermission =0; + Sta = 0; + + CtlNumSta = IsSelf; +} + +void TAllow::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TAllow::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TAllow::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "联动->手/自动控制状态 "); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 90, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "本机"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "控制状态"); + TextRender_string24(Lv.Grid.Left[1] + 104, Lv.Grid.Top[1] +40, clSilver, "按左右键更改值,按确定键执行"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Linkage->Auto "); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 90, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "Local"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Set Auto"); + TextRender_string24(Lv.Grid.Left[1] + 104, Lv.Grid.Top[1] +40, clSilver, "Press Key Left Or Key Right To Change,Key OK To Apply"); + } +} + +void TAllow::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iEdit[0].Init(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +36,60,30,0,0,1,clNearWhite); + IList->Edit[1].Init(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +36,90,30,0,0,1,clNearWhite); + for(int i=0; i<2;i++){ + IList->Edit[i].Enable = 1; + IList->Edit[i].Visible = 1; + IList->Edit[i].SetMaxLen(2); + IList->Edit[i].SetInputMaskEn(); + IList->Edit[i].Str.FromStr("01"); + IList->Edit[i].SetPstTail(); + } + if(MainCtl.fData.Split.NetworkMode == 1){ + IList->Edit[0].Enable = 1; + }else{ + IList->Edit[0].Enable = 0; + } + DrawFixText(); + IList->Edit[1].IsShowCursor = 0; + LoadData(); + ShowAuto(); +} + +void TAllow::Show(void) +{ + IsShow = 1; + RenderBackGround(); + DrawSelf(); +} + +void TAllow::FullRedraw(int Prm) +{ + if(Prm == 0){ + Show(); + DrawSelf(); + DrawCtlNum(); + DrawCtlNumTip(); + ShowAuto(); + ShowSta(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; iEdit[0].Show(); + IList->Edit[1].Show(); + DrawCtlNum(); + DrawCtlNumTip(); + ShowAuto(); + Check4Selected(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +//______________________________________________________________________________________________________________________________ +void TAllow::ClearSelected(void) +{ + switch(CtlIndex){ + case 0: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 1: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + default: + + break; + } +} + +void TAllow::Check4Selected(void) +{ + switch(CtlIndex){ + case 0: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + break; + case 1: + IList->Edit[1].Selected = 1; + IList->Edit[1].Show(); + break; + default: + + break; + } +} + +void TAllow::ShowAuto() +{ + if(LanguageEnCn==0){ + if(aAuto == 0){ + IList->Edit[1].Str.FromStr("手动"); + }else{ + IList->Edit[1].Str.FromStr("自动"); + } + }else{ + if(aAuto == 0){ + IList->Edit[1].Str.FromStr("Manual"); + }else{ + IList->Edit[1].Str.FromStr("Auto"); + } + } + IList->Edit[1].Show(); +} + +void TAllow::PermissionCmdGO() +{ + if(PermissionCmd == 1){ + AllowAuto = aAuto; + AllowManual = aManual; + ProcessUserSetManualState(); + Record.OperateAdd_AllowSet(MainCtl.fData.Split.MyNum, AllowAuto + AllowManual); + LoadData(); + ExRecord.SetStateCodeAutoManual(); + FecBusCRT.SetStateCodeAutoManual(); + DrawCtlNum(); + ShowAuto(); + if( (AllowAuto == aAuto) && (AllowManual == aManual) ){ + ShowSta(1); + }else{ + ShowSta(-1); + } + }else + if(PermissionCmd == 2){ + ProtoC2C.TxMsg.Data.CarryByte = 255; + ProtoC2C.TxMsg.Data.Priority =1; + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd_SetSlaveAllow; + ProtoC2C.TxMsg.Data.Len = 4; + + ProtoC2C.TxMsg.Data.Data[0] = 0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CtlNum; + ProtoC2C.TxMsg.Data.Data[3] = aAuto; + + ProtoC2C.oBufInsert(); + + ShowSta(2); + } +} + +void TAllow::PermissionCmdReturnDraw() +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Show(); + IList->Edit[1].Show(); + Check4Selected(); +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TAllow::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone, PmsRtnMsg; + int iVal; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex == 0){ + IList->Edit[0].KeyIn(aKey); + DrawCtlNumTip(); + IList->Edit[0].Show(); + }else + if(CtlIndex == 1){ + if(aAuto){ + aAuto =0; + aManual =2; + }else{ + aAuto =1; + aManual =0; + } + ShowAuto(); + } + break; + case VK_UP: + if(MainCtl.fData.Split.NetworkMode == 1){ + if(CtlIndex >0){ + ClearSelected(); + CtlIndex --; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(CtlIndex <1){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + if(CtlIndex == 1){ + if(aAuto){ + aAuto =0; + aManual =2; + }else{ + aAuto =1; + aManual =0; + } + ShowAuto(); + } + break; + case VK_EXECUTE: + //Save Data Here + if( (MainCtl.fData.Split.NetworkMode == 1) && (CtlNumSta != IsSelf) ){ + if(CtlNumSta == IsSlave){ + PermissionCmd = 2; + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 16, 400, 140, 2); + } + } + }else{ + PermissionCmd = 1; + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 16, 400, 140, 2); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + if(VK_EXECUTE != aKey){ + ShowSta(0); + } + } + + return aMsg; +} + +void TAllow::InitPanel(void) +{ + LoadData(); + Check4Selected(); + DrawCtlNum(); + ShowAuto(); +} + +void TAllow::LoadData() +{ + aAuto = AllowAuto; + aManual = AllowManual; +} + +void TAllow::DrawCtlNum() +{ + IList->Edit[0].Str.FromUInt2Dg(MainCtl.fData.Split.MyNum); + IList->Edit[0].Show(); +} + +void TAllow::DrawCtlNumTip() +{ + CtlNum = IList->Edit[0].Str.ToInteger(); + if( (CtlNum <1) || (CtlNum >dNETWORK_MACHINE_COUNT) ){ + CtlNumSta = IsNull; + IList->Edit[0].SelectedColor = clRed; + if(LanguageEnCn==0)TextRender_string24(Lv.Grid.Left[0] + 80, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "无效机器号 "); + else TextRender_string24(Lv.Grid.Left[0] + 80, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "Ctrl ID Invalid"); + }else{ + IList->Edit[0].SelectedColor = clBlue; + if(CtlNum == MainCtl.fData.Split.MyNum){ + CtlNumSta = IsSelf; + if(LanguageEnCn==0)TextRender_string24(Lv.Grid.Left[0] + 90, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "本机 "); + else TextRender_string24(Lv.Grid.Left[0] + 90, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "Local "); + }else{ + if( (CtlNum ProtoC2C.CtlMask.EndNum) ){ + unsigned int IsInlist = 0; + for(int i=0; iIsShow){ + // aAuto=ExtAuto; + // if(IsSelfChecking ==0 ) + // ShowAuto(); + //} +} + +void TAllow::ShowSta(int aSta) +{ + Sta = aSta; + ShowSta(); +} + +void TAllow::sRecoverSetDefault() +{ + AllowAuto = 0; + ProcessUserSetManualState(); +} + + diff --git a/MyCode/Gui/Allow.h b/MyCode/Gui/Allow.h new file mode 100644 index 0000000..f65ae69 --- /dev/null +++ b/MyCode/Gui/Allow.h @@ -0,0 +1,110 @@ +#ifndef ALLOW_H_ +#define ALLOW_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TAllow{ + public: + static constexpr unsigned short hList[12] = {82,82,82,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[0] + 560, + .y = Lv.Grid.Top[0] + 6, + }; + enum{ + IsSelf =0, + IsNull =1, + IsMask =2, + IsSlave =3, + IsUnknown + }; + public: + int IsShow; + class TItemList *IList; + + int Sta; + + unsigned char CtlIndex; + unsigned int aAuto; + unsigned int aManual; + + unsigned char IsPermission; + unsigned char PermissionCmd; + unsigned char CtlNumSta; + unsigned char CtlNum; + public: + TAllow(){}; + TAllow(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawCtlNum(); + void DrawCtlNumTip(); + void ShowAuto(); + void DrawFixText(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + void ClearSelected(); + void Check4Selected(void); + void ExtChange(int ExtAuto); + void PermissionCmdGO(); + void PermissionCmdReturnDraw(); + + void LoadData(); + void ShowSta(); + void ShowSta(int aSta); + + static void sRecoverSetDefault(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/AreaCfg.cpp b/MyCode/Gui/AreaCfg.cpp new file mode 100644 index 0000000..eadc01e --- /dev/null +++ b/MyCode/Gui/AreaCfg.cpp @@ -0,0 +1,1052 @@ +#include "AreaCfg.h" +#include "Runtime.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" +} + +//#define dFlash4AreaChip (0) +//#define dFlash4Area (0x00BB'0000) + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const int xNew = 10; +const int xModify = 100; +const int xDelete = 100; +const int xSave = 10; + +static const char CharBcdText[20]= {"0123456789*------\0"}; + +void TAreaCfg::Init() +{ + CtlIndex = 0; + IsShow = 0; + ListPage = 0; + ItemInx = 0; + Sta =0; + + IsPermission =0; + IsEdittingDescp =0; + IsEdittingShortName =0; +} + +void TAreaCfg::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick分区编辑"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "分区号"); + TextRender_string24(Lv.Grid.Left[0] + 186, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 286, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, "分区数量:"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "简称"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "描述"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +114, clNearWhite, "二次码"); + + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "操作"); + TRoundRect::sDrawBySize(xNew, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, "新建", 14, clNearBlack); + //TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, "修改", 14, clNearBlack); + TRoundRect::sDrawBySize(xDelete, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, "删除", 14, clNearBlack); + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Linkage->Zone Setting"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "ZoneID"); + TextRender_string24(Lv.Grid.Left[0] + 186, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 286, Lv.Grid.Top[0] +6, clNearWhite, " Local"); + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, "Amout:"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Brie"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Desc"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +114, clNearWhite, "Aux ID"); + + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Operation"); + TRoundRect::sDrawBySize(xNew, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, "New ", 14, clNearBlack); + //TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, "修改", 14, clNearBlack); + TRoundRect::sDrawBySize(xDelete, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, "Del ", 14, clNearBlack); + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + } +} + +void TAreaCfg::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] +4, 60, 30, 0,0,1,clNearWhite); + IList->Edit[0].Str.Clear(); + IList->Edit[0].SetMaxLen(4); + IList->Edit[0].Enable =1; + + IList->Edit[1].Init(Lv.Grid.Left[1] + 60, Lv.Grid.Top[1] +4, 226, 30, 0,0,1,clNearWhite); + IList->Edit[1].Str.Clear(); + IList->Edit[1].Enable =1; + IList->Edit[1].IsShowCursor =0; + mlEdit.Init(Lv.Grid.Left[1] +60, Lv.Grid.Top[1] +40, 226, 64, 0,0,1,clNearWhite); + mlEdit.SetLineSpacing(4); + mlEdit.Str.Clear(); + mlEdit.Enable =1; + mlEdit.IsShowCursor =0; + + IList->EditUserCode.Init(Lv.Grid.Left[1] + 86, Lv.Grid.Top[1] +110, 200, 30, 0,0,1,clNearWhite); + IList->EditUserCode.Str.Clear(); + IList->EditUserCode.SetMaxLen(8); + IList->EditUserCode.Enable =1; + + IList->Edit[0].Show(); + mlEdit.Show(); + IList->Edit[1].Show(); + IList->EditUserCode.Show(); +} + +void TAreaCfg::Redraw4EditText() +{ + RectFillRender(9, 239, 790, 431, ContentColor); + + for(int i=1; iEdit[0].Show(); + IList->Edit[1].Show(); + mlEdit.Show(); + IList->EditUserCode.Show(); + + Check4Selected(); +} + +void TAreaCfg::Show(void) +{ + IsShow = 1; + RenderBackGround(); + DrawSelf(); + DrawList(); +} + +void TAreaCfg::ShowSta() +{ + if(LanguageEnCn==0){ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "保存成功 "); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "保存失败 "); + }else + if(Sta == 2){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "删除成功 "); + }else + if(Sta == -2){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "删除失败 "); + } + }else{ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Saved OK "); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Save Err "); + }else + if(Sta == 2){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Deleted OK"); + }else + if(Sta == -2){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Failed "); + } + } +} + +void TAreaCfg::CheckCount() +{ + int i; + ItemCount = AreaSetting.Count; +} + +void TAreaCfg::DrawCount() +{ + int i=0; + + TextDigitRender4_24(Lv.Grid.Left[0] + 400 + 110, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, ItemCount); +} + +void TAreaCfg::ShowSta(int aSta) +{ + Sta = aSta; + ShowSta(); +} + +void TAreaCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + ShowSta(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawFixText(); + TextDigitRender2_24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + + IList->Edit[0].Show(); + mlEdit.Show(); + IList->Edit[1].Show(); + IList->EditUserCode.Show(); + if(IsList == 0)Check4Selected(); + DrawList(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +//______________________________________________________________________________________________________________________________ +void TAreaCfg::ClearSelected(void) +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->Edit[0].Selected =0; + IList->Edit[0].Show(); + break; + case 1: + if(LanguageEnCn==0)tText="新建";else tText="New "; + TRoundRect::sDrawBySize(xNew, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 2: + if(LanguageEnCn==0)tText="删除";else tText="Del "; + TRoundRect::sDrawBySize(xDelete, Lv.Grid.Top[0] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 3: + IList->Edit[1].Selected =0; + IList->Edit[1].Show(); + break; + case 4: + mlEdit.Selected =0; + mlEdit.Show(); + break; + case 5: + IList->EditUserCode.Selected =0; + IList->EditUserCode.Show(); + break; + case 6: + if(LanguageEnCn==0)tText="保存";else tText="Save"; + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + default: + + break; + } +} + +void TAreaCfg::Check4Selected(void) +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->Edit[0].Selected =1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + break; + case 1: + if(LanguageEnCn==0)tText="新建";else tText="New "; + TRoundRect::sDrawBySize(xNew, Lv.Grid.Top[0] + 40, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 2: + if(LanguageEnCn==0)tText="删除";else tText="Del "; + TRoundRect::sDrawBySize(xDelete, Lv.Grid.Top[0] + 40, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 3: + IList->Edit[1].Selected =1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + break; + case 4: + mlEdit.Selected =1; + mlEdit.Show(); + break; + case 5: + IList->EditUserCode.Selected =1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + break; + case 6: + if(LanguageEnCn==0)tText="保存";else tText="Save"; + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[2] + 40, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + default: + + break; + } +} + +void TAreaCfg::ShowCfg() +{ + IList->Edit[0].Show(); + IList->Edit[1].Show(); + mlEdit.Show(); + IList->EditUserCode.Show(); + DrawCount(); +} + +void TAreaCfg::Start() +{ + LoadData(); + Check4Selected(); + ShowCfg(); +} + +void TAreaCfg::PermissionCmdGO() +{ + if((PermissionCmd == 1) || (PermissionCmd == 2)){ + RestoreData(); + WriteEntryViaFlash(); + LoadData(); + DrawList(); + } +} + +void TAreaCfg::PermissionCmdReturnDraw() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawList(); +} + +void TAreaCfg::RestoreShortName(char *p) +{ + unsigned int i; + for(i=0; i<16; i++){ + IList->Edit[1].Str.Text[i] = *p; + if(*p == 0){ + break; + } + p++; + } + IList->Edit[1].Str.Text[i] =0; + IList->Edit[1].Str.Text[16] =0; + IList->Edit[1].Str.Text[17] =0; +} + +void TAreaCfg::RestoreDescp(char *p) +{ + unsigned int i; + for(i=0; i<32; i++){ + mlEdit.Str.Text[i] = *p; + if(*p == 0){ + break; + } + p++; + } + mlEdit.Str.Text[i] =0; + mlEdit.Str.Text[32] =0; + mlEdit.Str.Text[33] =0; +} + +void TAreaCfg::InitPanel(char *pText) +{ + int x,y,x2,y2, aW,aH,i; + + x = 10; + y = 240; + x2 = 789; + y2 = 430; + aW = x2 - x +1; + aH = y2 -y +1; + + aPanel->Init(x,y,aW,aH,0,0,clMoneyGreen, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearWhite,clBlue); + if(LanguageEnCn==0)aPanel->Caption.SetText("按中/EN键切换输入法,设置键保存更改,返回键放弃更改并返回",24); + else aPanel->Caption.SetText("Key 中/EN To Switch Input Method,Key Set To Save",24); + aPanel->Caption.Enable = 1; + aPanel->Caption.Visible = 1; + + aPanel->SText[0].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0)TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + else TMyString::sFromStr("Enter Numbers", aPanel->SText[0].Text); + aPanel->SText[0].Enable = 1; + aPanel->SText[0].Visible = 1; + + aPanel->Edit[ 0].Init(10,40,420,30,x,y,1,clNearBlack); + aPanel->Edit[ 0].Str.FromStr(pText); + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 1; + } + + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); +} + +void TAreaCfg::NewEntry() +{ + int i, GotNewInx; + unsigned int sAddr, Idf; + GotNewInx =0; + for(i=0; iaPanel->Edit[0].Str.Text); + }else + if(IsEdittingShortName){ + RestoreShortName(this->aPanel->Edit[0].Str.Text); + } + Redraw4EditText(); + DrawList(); + IsEdittingDescp = 0; + IsEdittingShortName =0; + }else + if(IsExtInput){ + if(aKey == dfKEY_ENCN){ + CnInput.KeyIn(aKey); + if(CnInput.InputMode == 0){ + IsExtInput = 0; + CnInput.OverPrint(this->aPanel->Color); + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + if(LanguageEnCn==0)TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + else TMyString::sFromStr("Enter Numbers", aPanel->SText[0].Text); + aPanel->SText[0].Show(); + } + }else + if(aKey == VK_RETURN){ + //Just return + Redraw4EditText(); + DrawList(); + IsEdittingDescp = 0; + IsEdittingShortName =0; + }else{ + if( (aKey == VK_DELETE) && (CnInput.sEdit.Pst == -1) ){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + }else{ + p = CnInput.KeyIn(aKey); + if(p != nullptr){ + if(CnInput.GotChar[0] != '\0'){ + aPanel->Edit[0].Pst = aPanel->Edit[0].Str.Insert(CnInput.GotChar, aPanel->Edit[0].Pst); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + } + } + } + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + break; + case dfKEY_ENCN: + if(IsExtInput == 0){ + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn==0)TMyString::sFromStr("当前根据输入法输入", aPanel->SText[0].Text); + else TMyString::sFromStr("Pay Attention To The Tip", aPanel->SText[0].Text); + aPanel->SText[0].Show(); + } + break; + case VK_EXECUTE: + + break; + case VK_RETURN: + Redraw4EditText(); + DrawList(); + IsEdittingDescp = 0; + IsEdittingShortName =0; + break; + } + } + }else + if(IsList){ + int PageCountMax = dAreaCountMax / 8; + switch(aKey){ + case VK_LEFT: + if(ListPage >0){ + ListPage -=8; + if(ListPage <0)ListPage = 0; + } + DrawList(); + break; + case VK_RIGHT: + if(ListPage < PageCountMax){ + ListPage +=8; + if(ListPage > (PageCountMax-1))ListPage = PageCountMax-1; + } + DrawList(); + break; + case VK_UP: + if(ListPage >0){ + ListPage--; + if(ListPage <0)ListPage = 0; + } + DrawList(); + break; + case VK_DOWN: + if(ListPage < PageCountMax){ + ListPage ++; + if(ListPage > (PageCountMax-1))ListPage = PageCountMax-1; + } + DrawList(); + break; + case VK_TAB: + IsList = 0; + DrawList(); + Check4Selected(); + break; + case VK_EXECUTE: + + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default : + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(CtlIndex == 0){ + IList->Edit[0].KeyIn(aKey); + int iVal; + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal <1) || (iVal > dAreaCountMax) ){ + IList->Edit[0].SelectedColor = clRed; + }else{ + IList->Edit[0].SelectedColor = clBlue; + iVal--; + if(iVal != ItemInx){ + ItemInx = iVal; + LoadUcBcdText(); + LoadShortName(); + LoadDescp(); + ShowCfg(); + Check4Selected(); + } + } + IList->Edit[0].Show(); + }else + if(CtlIndex == 1){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + }else + if(CtlIndex == 2){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + } + }else + if(CtlIndex == 3){ + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + InitPanel(IList->Edit[1].Str.Text); + IsEdittingShortName = 1; + IsExtInput = 0; + }else + if(CtlIndex == 4){ + mlEdit.Selected = 0; + mlEdit.Show(); + InitPanel(mlEdit.Str.Text); + IsEdittingDescp = 1; + IsExtInput = 0; + }else + if(CtlIndex == 5){ + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + } + break; + case dfKEY_ASTERISK: + if(CtlIndex == 5){ + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex <6){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + break; + + case VK_TAB: + IsList = 1; + DrawList(); + ClearSelected(); + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + + //ShowCfg(); + break; + case VK_EXECUTE: + //Save Data Here + if(CtlIndex == 1){ + NewEntry(); + }else + if(CtlIndex == 2){ + PermissionCmd = 2; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 3){ + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + InitPanel(IList->Edit[1].Str.Text); + IsEdittingShortName = 1; + IsExtInput = 0; + }else + if(CtlIndex == 4){ + mlEdit.Selected = 0; + mlEdit.Show(); + InitPanel(mlEdit.Str.Text); + IsEdittingDescp = 1; + IsExtInput = 0; + }else + if(CtlIndex == 6){ + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default : + break; + } + + if(VK_EXECUTE != aKey){ + if( (IsEdittingDescp == 0) && (IsEdittingShortName == 0) ){ + ShowSta(0); + } + } + } + + return aMsg; +} + +void TAreaCfg::LoadUcBcdText() +{ + int i; + unsigned int Idf, aOrd, sAddr; + + if(ItemInx >= dAreaCountMax ){ + IList->EditUserCode.Str.Text[0] = '\0'; + IList->EditUserCode.Str.Text[1] = '\0'; + return; + } + + sAddr = dAddrSdRam_4Area + (ItemInx * 64); + Idf = *(volatile unsigned int *)(sAddr); + if(Idf == 0xA8A7A6A5){ + sAddr = dAddrSdRam_4Area + (ItemInx * 64) + 4; + for(i=0; i<8; i++){ + IList->EditUserCode.Str.Text[i] = *(volatile unsigned char *)(sAddr +i); + } + IList->EditUserCode.Str.Text[8] = '\0'; + }else{ + IList->EditUserCode.Str.Text[0] = '\0'; + IList->EditUserCode.Str.Text[1] = '\0'; + } +} + +void TAreaCfg::LoadShortName() +{ + unsigned int Idf, sAddr; + + if(ItemInx >= dAreaCountMax ){ + IList->Edit[1].Str.Text[0] = '\0'; + IList->Edit[1].Str.Text[1] = '\0'; + return; + } + + sAddr = dAddrSdRam_4Area + (ItemInx * 64); + Idf = *(volatile unsigned int *)(sAddr); + if(Idf == 0xA8A7A6A5){ + sAddr = dAddrSdRam_4Area + (ItemInx * 64) + 16; + for(int i=0; i<16; i++){ + IList->Edit[1].Str.Text[i] = *(volatile unsigned char *)(sAddr +i); + } + IList->Edit[1].Str.Text[16] = '\0'; + }else{ + IList->Edit[1].Str.Text[0] = '\0'; + IList->Edit[1].Str.Text[1] = '\0'; + } +} + +void TAreaCfg::LoadDescp() +{ + unsigned int Idf, sAddr; + + if(ItemInx >= dAreaCountMax ){ + mlEdit.Str.Text[0] ='\0'; + mlEdit.Str.Text[1] ='\0'; + return; + } + + sAddr = dAddrSdRam_4Area + (ItemInx * 64); + Idf = *(volatile unsigned int *)(sAddr); + if(Idf == 0xA8A7A6A5){ + sAddr = dAddrSdRam_4Area + (ItemInx * 64) + 32; + for(int i=0; i<32; i++){ + mlEdit.Str.Text[i] = *(volatile unsigned char *)(sAddr +i);; + } + mlEdit.Str.Text[32] = '\0'; + }else{ + mlEdit.Str.Text[0] ='\0'; + mlEdit.Str.Text[1] ='\0'; + } +} + +void TAreaCfg::RestoreUcBcdText() +{ + for(int i=0; i<8; i++){ + RawData[i+4] = IList->EditUserCode.Str.Text[i]; + } +} + +void TAreaCfg::RestoreShortName() +{ + for(int i=0; i<16; i++){ + RawData[i+16] = IList->Edit[1].Str.Text[i]; + } +} + +void TAreaCfg::RestoreDescp() +{ + for(int i=0; i<32; i++){ + RawData[i+32] = mlEdit.Str.Text[i]; + } +} + +void TAreaCfg::LoadData() +{ + CheckCount(); + IList->Edit[0].Str.FromUInt4Dg(ItemInx +1); + + LoadUcBcdText(); + LoadShortName(); + LoadDescp(); + ShowCfg(); + Check4Selected(); +} + +void TAreaCfg::RestoreData() +{ + int i; + if(PermissionCmd == 1){ + RestoreUcBcdText(); + RestoreShortName(); + RestoreDescp(); + //Save + for(i=0; i<4; i++)RawData[i] =0xA5 +i; + }else + if(PermissionCmd == 2){ + //Erase + for(i=0; i<64; i++)RawData[i] =0; + } +} + +void TAreaCfg::ReadEntryViaFlash() +{ + +} + +void TAreaCfg::WriteEntryViaFlash() +{ + unsigned int fAddr, sAddr, GetSta; + unsigned int BlockX, PageX, OffSet; + + BlockX = ItemInx * 64 / 4096; + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlash4AreaChip); + }while(GetSta); + fAddr = dFlash4Area + (BlockX * 4096); + nor_erase_sector_4k(dFlash4AreaChip,fAddr); + sDelayMs(100); + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlash4AreaChip); + }while(GetSta); + + sAddr = dAddrSdRam_4Area + (ItemInx * 64); + for(int x=0; x<64; x++){ + *(volatile unsigned char *)(sAddr + x) = RawData[x]; + } + PageX = ItemInx / (256 / 64); + for(int i=0; i<16; i++){ + IList->RealtimeData.Reset(); + sAddr = dAddrSdRam_4Area + ( (BlockX * 16 +i) * 256); + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlash4AreaChip); + }while(GetSta); + for(int x=0;x<256;x++){ + IList->RealtimeData.Data[0][x] = *(volatile unsigned char *)(sAddr + x); + } + fAddr = dFlash4Area + ( (BlockX * 16 + i) * 256); + nor_write_page(dFlash4AreaChip, fAddr, IList->RealtimeData.Data[0]); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlash4AreaChip); + }while(GetSta); + } + + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlash4AreaChip); + }while(GetSta); + Record.Read4Area(); + GetSta =0; + sAddr = dAddrSdRam_4Area + (ItemInx * 64); + for(int i=0; i<64; i++){ + if(RawData[i] != *(volatile unsigned char *)(sAddr +i)){ + GetSta=1; + break; + } + } + + if(GetSta){ + //Write Err + if(PermissionCmd == 1){ + //Save Err + ShowSta(-1); + }else + if(PermissionCmd == 2){ + //Delete Err + ShowSta(-2); + } + }else{ + //Write OK + if(PermissionCmd == 1){ + //Save OK + ShowSta(1); + }else + if(PermissionCmd == 2){ + //Delete OK + ShowSta(2); + } + } +} + +void TAreaCfg::DrawList() +{ + int i, z, x, y; + unsigned int aClr, TopInx, sAddr, Idf; + IsList ? aClr=clBlue : aClr=clMedGray; + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + + const unsigned int PageCount = dAreaCountMax / 8; + if(ListPage >= PageCount) ListPage = 0; + + x = Lv.Panel.Left+6; + y = Lv.Panel.Top +6; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearBlack, PanelColor, "区域号 配置 简称 二次码"); + else TextRender_string24(x, y, clNearBlack, PanelColor, "ZoneID Config Brief Aux ID"); + TopInx = ListPage * 8; + for(i=0,z=TopInx; (i<8) && (z蓝牙传输"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "蓝牙设置"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "工作模式"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "数据权限"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "操作权限"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "开启", 38, clNearBlack); + TRoundRect::sDrawBySize(160, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "关闭", 38, clNearBlack); + TextRender_string24(xFirst + 30, Lv.Grid.Top[1] + 40, clNearWhite, "信息共享"); + TextRender_string24(xSec +30, Lv.Grid.Top[1] + 40, clNearWhite, "调试"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[2] + 40, clNearWhite, "只读"); + TextRender_string24(xSec +30, Lv.Grid.Top[2] + 40, clNearWhite, "读写"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[3] + 40, clNearWhite, "消音"); + TextRender_string24(xSec +30, Lv.Grid.Top[3] + 40, clNearWhite, "复位"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Data Transmission->Blue Tooth"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Blue Tooth Setting"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Mode"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Data Permission"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "Operating Permission"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "Enable", 26, clNearBlack); + TRoundRect::sDrawBySize(160, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "Disable", 26, clNearBlack); + TextRender_string24(xFirst + 30, Lv.Grid.Top[1] + 40, clNearWhite, "Interconnection"); + TextRender_string24(xSec +30, Lv.Grid.Top[1] + 40, clNearWhite, "Test Only"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[2] + 40, clNearWhite, "Read Only"); + TextRender_string24(xSec +30, Lv.Grid.Top[2] + 40, clNearWhite, "Read Write"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[3] + 40, clNearWhite, "Mute"); + TextRender_string24(xSec +30, Lv.Grid.Top[3] + 40, clNearWhite, "Reset"); + } +} + +void TBlueTooth::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i 1){ + ClearSelected(); + CtlIndex-=2; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex < 6){ + ClearSelected(); + CtlIndex+=2; + Check4Selected(); + } + break; + case dfKEY_SETUP: + if(CtlIndex == 2){ + OnOff.Share = OnOff.Share ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 3){ + OnOff.Cmsn = OnOff.Cmsn ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 4){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 5){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 6){ + OnOff.Mute = OnOff.Mute ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 7){ + OnOff.Reset = OnOff.Reset ? 0 : 1; + DrawSetting(); + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + //Active + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Top[1] + 12, 600 , 120, 3); + } + }else + if(CtlIndex == 1){ + //Close + PermissionCmd = 2; + PermissionCmdGO(); + } + if(CtlIndex == 2){ + OnOff.Share = OnOff.Share ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 3){ + OnOff.Cmsn = OnOff.Cmsn ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 4){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 5){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 6){ + OnOff.Mute = OnOff.Mute ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 7){ + OnOff.Reset = OnOff.Reset ? 0 : 1; + DrawSetting(); + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TBlueTooth::sRecoverSetDefault() +{ + + SysLoopTick = 0; +} + +int TBlueTooth::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} + +void TBlueTooth::Task1000Ms() +{ + +} + + + + + + diff --git a/MyCode/Gui/BlueTooth.h b/MyCode/Gui/BlueTooth.h new file mode 100644 index 0000000..39db570 --- /dev/null +++ b/MyCode/Gui/BlueTooth.h @@ -0,0 +1,147 @@ +#ifndef BLUETOOTH_H_ +#define BLUETOOTH_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TBlueTooth{ + public: + static constexpr unsigned short hList[12] = {70,70,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 4, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3] +4, + .Panel.Width = 796, + .Panel.Heigh = 80, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3] +4 + 80 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char CrtNum; + unsigned char CrtNumValid; + + + unsigned char LineType; + unsigned char ReadWrite; + unsigned char IsOnGoing; + + char Text[68]; + + struct{ + unsigned char Share; + unsigned char Cmsn; + unsigned char ReadOnly; + unsigned char Mute; + unsigned char Reset; + unsigned char Sv0; + unsigned char Sv1; + unsigned char Sv2; + }OnOff; + struct{ + unsigned char DeviceOn; + unsigned char Connection; + unsigned char Rsv1; + unsigned char Rsv2; + }State; + + public: + TBlueTooth(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + static void sDelayMs(unsigned int aMs); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + void DrawConnState(); + + void DrawSetting(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + static void sRecoverSetDefault(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + +#endif diff --git a/MyCode/Gui/BoardState.cpp b/MyCode/Gui/BoardState.cpp new file mode 100644 index 0000000..3213563 --- /dev/null +++ b/MyCode/Gui/BoardState.cpp @@ -0,0 +1,500 @@ +#include "RuntimeData.h" +#include "BoardState.h" + +//Not Using This since 2024 04 20 + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +static const unsigned char stCmd[8] = {221,222,223,224,225,226,227,228}; +static const unsigned char stPrm[8] = {0,1,2,3,4,5,6,7}; + +void TBoardState::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+358,Top,434, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + RectPanel.Set(205,78,595,400); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("板卡运行状态-本机", Caption.Text); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + CtlIndex = 0; + Target = 0; + IsShowing = 0; + + for(i=0; i<12; i++){ + RecData[i] = 0; + RecDataUpdateFlag[i] =0; + } +} + +void TBoardState::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TBoardState::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TBoardState::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + TextRender_string24(RectPanel.Left, Bound.Bottom -32 ,clNearBlack, "选中板卡类型时,按TAB键切换类型;"); +} + + +void TBoardState::DrawCaption2(void) +{ + TMyString::sFromStr("xxxxxxx", SText.Text); + //SText.Show(); +} + +void TBoardState::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); +} + +void TBoardState::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ + +void TBoardState::Check4Selected(void) +{ + unsigned int i; + aPanel->Btn[0].Selected = 0; + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Btn[0].Selected = 1; + break; + default: + + break; + } +} + +void TBoardState::FillStateName() +{ + if(Target == 0){ + aPanel->Edit[0].Str.FromStr("总线盘"); + aPanel->Edit[0].ReDraw(); + TMyString::sFromStr("按键数", aPanel->SText[0].Text); + TMyString::sFromStr("允许数", aPanel->SText[1].Text); + TMyString::sFromStr("电压", aPanel->SText[2].Text); + TMyString::sFromStr("电流", aPanel->SText[3].Text); + TMyString::sFromStr("手动允许", aPanel->SText[4].Text); + TMyString::sFromStr("状态值6", aPanel->SText[5].Text); + }else + if(Target ==1){ + aPanel->Edit[0].Str.FromStr("多线盘"); + aPanel->Edit[0].ReDraw(); + TMyString::sFromStr("按键数", aPanel->SText[0].Text); + TMyString::sFromStr("允许数", aPanel->SText[1].Text); + TMyString::sFromStr("电压", aPanel->SText[2].Text); + TMyString::sFromStr("电流", aPanel->SText[3].Text); + TMyString::sFromStr("手动允许", aPanel->SText[4].Text); + TMyString::sFromStr("状态值6", aPanel->SText[5].Text); + }else + if(Target ==2){ + aPanel->Edit[0].Str.FromStr("回路母板"); + aPanel->Edit[0].ReDraw(); + TMyString::sFromStr("最大挂载", aPanel->SText[0].Text); + TMyString::sFromStr("已挂载", aPanel->SText[1].Text); + TMyString::sFromStr("电压", aPanel->SText[2].Text); + TMyString::sFromStr("电流", aPanel->SText[3].Text); + TMyString::sFromStr("联动托管", aPanel->SText[4].Text); + TMyString::sFromStr("状态6", aPanel->SText[5].Text); + }else + if(Target ==3){ + aPanel->Edit[0].Str.FromStr("组网通讯板"); + aPanel->Edit[0].ReDraw(); + TMyString::sFromStr("波特率", aPanel->SText[0].Text); + TMyString::sFromStr("连接", aPanel->SText[1].Text); + TMyString::sFromStr("电压", aPanel->SText[2].Text); + TMyString::sFromStr("电流", aPanel->SText[3].Text); + TMyString::sFromStr("状态5", aPanel->SText[4].Text); + TMyString::sFromStr("状态6", aPanel->SText[5].Text); + }else + if(Target ==4){ + aPanel->Edit[0].Str.FromStr("CRT连接板"); + aPanel->Edit[0].ReDraw(); + TMyString::sFromStr("波特率", aPanel->SText[0].Text); + TMyString::sFromStr("心跳时间", aPanel->SText[1].Text); + TMyString::sFromStr("电压", aPanel->SText[2].Text); + TMyString::sFromStr("电流", aPanel->SText[3].Text); + TMyString::sFromStr("状态5", aPanel->SText[4].Text); + TMyString::sFromStr("状态6", aPanel->SText[5].Text); + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TBoardState::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int iVal; + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) ){ + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].ReDraw(); + } + } + + if( (aKey == VK_UP) || (aKey == VK_DOWN) ){ + if(aPanel->Edit[0].Selected){ + if( aKey == VK_UP ){ + Target--; + if(Target < 0){ + Target = 4; + } + FillStateName(); + aPanel->ReDrawItems(); + } + if( aKey == VK_DOWN ){ + Target++; + if(Target > 4){ + Target = 0; + } + FillStateName(); + aPanel->ReDrawItems(); + } + }else + if(aPanel->Edit[1].Selected){ + iVal = aPanel->Edit[1].Str.ToInteger(); + if((aKey == VK_UP)){ + iVal++; + if(iVal > 40)iVal =40; + } + if((aKey == VK_DOWN)){ + iVal--; + if(iVal <1)iVal =1; + } + aPanel->Edit[1].Str.FromInt(iVal); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[1].Show(); + } + } + + if(aKey == VK_LEFT){ + if(CtlIndex == 1){ + if(aPanel->Edit[1].Pst < 0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + }else{ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 2){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_RIGHT){ + if(CtlIndex == 1){ + if(aPanel->Edit[1].Pst > 0){ + CtlIndex = 2; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + }else{ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 0){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_TAB){ + if(aPanel->Edit[0].Selected){ + Target++; + if(Target > 4){ + Target = 0; + } + FillStateName(); + aPanel->ReDrawItems(); + } + } + if(aKey == VK_EXECUTE){ + //Save Data Here + SendCmd(); + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TBoardState::PanelCanvasOut() +{ + HorizLineRender(RectPanel.Left +6, 317, RectPanel.Width - 12, clSilver); +} + +void TBoardState::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + aPanel->Caption.Text[0] = 0; + + aPanel->SText[0].Init(2,12,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(2,50,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(2,88,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(2,126,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(2,164,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[5].Init(2,202,100,30,x,y,clNearBlack,clFrmFace); + + aPanel->SText[10].Init(200,12,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[11].Init(200,50,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[12].Init(200,88,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[13].Init(200,126,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[14].Init(200,164,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[15].Init(200,202,100,30,x,y,clNearBlack,clFrmFace); + + + aPanel->SText[6].Init(36,247,100,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[7].Init(180,247,60,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[8].Init(205,250,60,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[9].Init(290,250,60,30,x,y,clNearBlack,clFrmFace); + + + TMyString::sFromStr("状态值1", aPanel->SText[0].Text); + TMyString::sFromStr("状态值2", aPanel->SText[1].Text); + TMyString::sFromStr("状态值3", aPanel->SText[2].Text); + TMyString::sFromStr("状态值4", aPanel->SText[3].Text); + TMyString::sFromStr("状态值5", aPanel->SText[4].Text); + TMyString::sFromStr("状态值6", aPanel->SText[5].Text); + + TMyString::sFromStr("返回值1", aPanel->SText[10].Text); + TMyString::sFromStr("返回值2", aPanel->SText[11].Text); + TMyString::sFromStr("返回值3", aPanel->SText[12].Text); + TMyString::sFromStr("返回值4", aPanel->SText[13].Text); + TMyString::sFromStr("返回值5", aPanel->SText[14].Text); + TMyString::sFromStr("返回值6", aPanel->SText[15].Text); + + TMyString::sFromStr("板卡类型", aPanel->SText[6].Text); + TMyString::sFromStr("序号", aPanel->SText[7].Text); + + for(i=0; i<8;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + for(i=10; i<16;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + + aPanel->Edit[4].Init(110,12,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[5].Init(110,50,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[6].Init(110,88,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[7].Init(110,126,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[8].Init(110,164,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[9].Init(110,202,70,30,x,y,clNearBlack,clNearWhite); + + aPanel->Edit[10].Init(306,12,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[11].Init(306,50,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[12].Init(306,88,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[13].Init(306,126,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[14].Init(306,164,70,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[15].Init(306,202,70,30,x,y,clNearBlack,clNearWhite); + + aPanel->Edit[0].Init(8,280,160,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(180,280,56,30,x,y,clNearBlack,clNearWhite); + + for(i=0; i<2;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(8); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.Clear(); + aPanel->Edit[i].Pst = -1; + } + for(i=4; i<16;i++){ + aPanel->Edit[i].Enable = 0; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(5); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.Clear(); + aPanel->Edit[i].Pst = -1; + } + aPanel->Edit[0].SetMaxLen(16); + aPanel->Edit[0].Str.FromStr("总线盘"); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[0].Color = clMoneyGreen; + aPanel->Edit[1].SetMaxLen(2); + aPanel->Edit[1].Str.FromStr("01"); + aPanel->Edit[1].Pst = 1; + aPanel->Edit[0].IsShowCursor = 0; + + aPanel->Btn[0].Init(250,280,128,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("监测状态"); + + for(i=0; i<1;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + FillStateName(); + aPanel->ReDrawItems(); + PanelCanvasOut(); +} + +void TBoardState::SendCmd() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + if(CtlIndex == 10){ + Len = 5; + + Data[0] = 0; + Data[1] = 1; + + //Path 0 + iVal = aPanel->Edit[6].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[2] = cVal; + + //Cmd 1 + iVal = aPanel->Edit[7].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aIde.BitF.Cmd = cVal; + + //Cmd 2 + iVal = aPanel->Edit[8].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[3] = cVal; + + //Prm + iVal = aPanel->Edit[9].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[4] = cVal; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); + } +} + + +int TBoardState::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} + + + + + + diff --git a/MyCode/Gui/BoardState.h b/MyCode/Gui/BoardState.h new file mode 100644 index 0000000..bc468e4 --- /dev/null +++ b/MyCode/Gui/BoardState.h @@ -0,0 +1,77 @@ +#ifndef BOARDSTATE_H_ +#define BOARDSTATE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TBoardState{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect VScrollBarBox; + + TRect Content; + TRect RectPanel; + + TMyString Str; + + unsigned int CtlIndex; + int Target; + + int IsFastCmd; + unsigned char Data[8]; + unsigned short RecData[12]; + unsigned char RecDataUpdateFlag[12]; + unsigned char IsShowing; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TBoardState(){}; + TBoardState(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void PanelCanvasOut(); + void DrawCaption2(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + void FillStateName(); + void SendCmd(); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + diff --git a/MyCode/Gui/BroadcastCfg.cpp b/MyCode/Gui/BroadcastCfg.cpp new file mode 100644 index 0000000..e045c88 --- /dev/null +++ b/MyCode/Gui/BroadcastCfg.cpp @@ -0,0 +1,477 @@ +#include "BroadcastCfg.h" +#include "Runtime.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TBroadcastCfg::Init() +{ + CtlIndex = 0; + IsShow = 0; + IsPermission =0; + Sta =0; +} + +void TBroadcastCfg::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick广播/声光交替设置 "); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "输出模式"); + TextRender_string24(Lv.Grid.Left[0] + 40, Lv.Grid.Top[0] +40, clNearWhite, "并行模式"); + TextRender_string24(Lv.Grid.Left[0] + 190, Lv.Grid.Top[0] +40, clNearWhite, "交替模式"); + + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "声光输出时间"); + + TextRender_string24(Lv.Grid.Left[1] + 60, Lv.Grid.Top[1] +40, clNearWhite, "秒"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "广播输出时间"); + TextRender_string24(Lv.Grid.Left[2] + 60, Lv.Grid.Top[2] +40, clNearWhite, "秒"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Linkage->Broadcast Acoustooptic Alternating"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Mode"); + TextRender_string24(Lv.Grid.Left[0] + 40, Lv.Grid.Top[0] +40, clNearWhite, "Parallel"); + TextRender_string24(Lv.Grid.Left[0] + 190, Lv.Grid.Top[0] +40, clNearWhite, "Alternating"); + + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Acoustooptic Activated Time"); + + TextRender_string24(Lv.Grid.Left[1] + 60, Lv.Grid.Top[1] +40, clNearWhite, "Second"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Broadcast Activated Time"); + TextRender_string24(Lv.Grid.Left[2] + 60, Lv.Grid.Top[2] +40, clNearWhite, "Second"); + } +} + +void TBroadcastCfg::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iEdit[0].Init(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +36,42,30,0,0,1,clNearWhite); + IList->Edit[1].Init(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +36,42,30,0,0,1,clNearWhite); + for(int i=0; i<2;i++){ + IList->Edit[i].Enable = 1; + IList->Edit[i].Visible = 1; + IList->Edit[i].SetMaxLen(3); + IList->Edit[i].SetInputMaskEn(); + IList->Edit[i].Str.FromStr("001"); + IList->Edit[i].SetPstTail(); + } + DrawFixText(); +} + +void TBroadcastCfg::Show(void) +{ + IsShow = 1; + RenderBackGround(); + DrawSelf(); +} + +void TBroadcastCfg::ShowSta() +{ + if(LanguageEnCn==0){ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "保存成功 "); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "保存失败 "); + } + }else{ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Saved OK "); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Failed To Save"); + } + } +} + +void TBroadcastCfg::ShowSta(int aSta) +{ + Sta = aSta; + ShowSta(); +} + +void TBroadcastCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + ShowSta(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; iEdit[0].Show(); + IList->Edit[1].Show(); + DrawFixText(); + Check4Selected(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +//______________________________________________________________________________________________________________________________ +void TBroadcastCfg::ClearSelected(void) +{ + switch(CtlIndex){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, 4, ItemColor); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[0] +160, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, 4, ItemColor); + break; + case 2: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 3: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + default: + + break; + } +} + +void TBroadcastCfg::Check4Selected(void) +{ + switch(CtlIndex){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[0] +160, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 2: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + break; + case 3: + IList->Edit[1].Selected = 1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + break; + default: + + break; + } +} + +void TBroadcastCfg::ShowSyncMode() +{ + if(aBroadcast.SyncMode == 0){ + //并行 + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] +160, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + //交替模式 + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdDisabelClr, 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] +160, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + } +} + +void TBroadcastCfg::PermissionCmdGO() +{ + if(PermissionCmd == 1){ + RestoreData(); + if(Broadcast.SyncMode == 0)InnerCan.SendCmdBroadcastFast(2); + WriteSetting(); + ReadSetting(); + LoadData(); + + if( (aBroadcast.PadAddr == Broadcast.PadAddr) && + (aBroadcast.Addr == Broadcast.Addr) && + (aBroadcast.AreaNum == Broadcast.AreaNum) && + (aBroadcast.SyncMode == Broadcast.SyncMode) && + + (aBroadcast.BroadcastTime == Broadcast.BroadcastTime) && + (aBroadcast.VaTime == Broadcast.VaTime) ) { + ShowSta(1); + Record.OperateAdd_BroadcastVa(Broadcast.PadAddr, Broadcast.Addr, Broadcast.SyncMode); + }else{ + ShowSta(-1); + } + } +} + +void TBroadcastCfg::PermissionCmdReturnDraw() +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iEdit[0].Show(); + IList->Edit[1].Show(); + Check4Selected(); +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TBroadcastCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + int iVal; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex == 0){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex = 1; + Check4Selected(); + } + }else + if(CtlIndex == 1){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex = 0; + Check4Selected(); + } + }else + if(CtlIndex == 2){ + IList->Edit[0].KeyIn(aKey); + IList->Edit[0].Show(); + }else + if(CtlIndex == 3){ + IList->Edit[1].KeyIn(aKey); + IList->Edit[1].Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex <3){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + if( (CtlIndex == 0) || (CtlIndex == 1) ){ + aBroadcast.SyncMode = aBroadcast.SyncMode ? 0 : 0xA5; + ShowSyncMode(); + } + break; + case VK_EXECUTE: + //Save Data Here + PermissionCmd = 1; + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 16, 400, 140, 2); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default : + break; + } + + if(VK_EXECUTE != aKey){ + ShowSta(0); + } + } + + return aMsg; +} + +void TBroadcastCfg::InitPanel(void) +{ + LoadData(); + Check4Selected(); + ShowSyncMode(); +} + +void TBroadcastCfg::LoadData() +{ + aBroadcast.PadAddr = 0;//Broadcast.PadAddr; + aBroadcast.Addr = 0;//Broadcast.Addr; + aBroadcast.AreaNum = 0;//Broadcast.AreaNum; + aBroadcast.SyncMode = Broadcast.SyncMode; + + aBroadcast.BroadcastTime = Broadcast.BroadcastTime; + aBroadcast.VaTime = Broadcast.VaTime; + + IList->Edit[0].Str.FromUInt3Dg(aBroadcast.VaTime); + IList->Edit[1].Str.FromUInt3Dg(aBroadcast.BroadcastTime); + + IList->Edit[0].SetPstTail(); + IList->Edit[1].SetPstTail(); + + + IList->Edit[0].Show(); + IList->Edit[1].Show(); +} + +void TBroadcastCfg::RestoreData() +{ + int iVal; + Broadcast.PadAddr =aBroadcast.PadAddr; + Broadcast.Addr =aBroadcast.Addr; + Broadcast.AreaNum =aBroadcast.AreaNum ; + + Broadcast.SyncMode =aBroadcast.SyncMode; + + iVal = IList->Edit[0].Str.ToInteger(); + if(iVal <0) iVal = 1; + if(iVal > 999) iVal = 999; + aBroadcast.VaTime = iVal; + + iVal = IList->Edit[1].Str.ToInteger(); + if(iVal <0) iVal = 1; + if(iVal > 999) iVal = 999; + aBroadcast.BroadcastTime = iVal; + + Broadcast.BroadcastTime =aBroadcast.BroadcastTime; + Broadcast.VaTime =aBroadcast.VaTime; +} + +void TBroadcastCfg::ReadSetting() +{ + unsigned int tAddr; + unsigned char tData[8]; + //Read ExistTable + tAddr = dEepAddrBroadcastSetting +0; + sDelayMs(10); + eeprom_read_byte(0, tAddr, tData, 8); + + Broadcast.PadAddr = tData[0]; + Broadcast.Addr = tData[1]; + Broadcast.AreaNum = tData[2]; + Broadcast.SyncMode = tData[3]; + if(Broadcast.SyncMode != 0xA5)Broadcast.SyncMode =0; + Broadcast.BroadcastTime = tData[5]; + Broadcast.BroadcastTime <<= 8; + Broadcast.BroadcastTime |= tData[4]; + Broadcast.VaTime = tData[7]; + Broadcast.VaTime <<= 8; + Broadcast.VaTime |= tData[6]; +} + +void TBroadcastCfg::WriteSetting() +{ + unsigned int tAddr; + unsigned char tData[8]; + + tData[0] = Broadcast.PadAddr; + tData[1] = Broadcast.Addr; + tData[2] = Broadcast.AreaNum; + tData[3] = Broadcast.SyncMode ; + tData[4] = static_cast(Broadcast.BroadcastTime & 0x00FF); + tData[5] = static_cast((Broadcast.BroadcastTime >> 8) & 0x00FF); + tData[6] = static_cast(Broadcast.VaTime & 0x00FF); + tData[7] = static_cast((Broadcast.VaTime >> 8) & 0x00FF); + + tAddr = dEepAddrBroadcastSetting + 0; + sDelayMs(10); + eeprom_write_byte_via_page(0, tAddr, tData, 8); + sDelayMs(10); +} + +void TBroadcastCfg::sRecoverSetDefault() +{ + unsigned int tAddr; + unsigned char tData[8]; + + tData[0] = Broadcast.PadAddr; + tData[1] = Broadcast.Addr; + tData[2] = Broadcast.AreaNum; + tData[3] = Broadcast.SyncMode ; + tData[4] = 30; //static_cast(Broadcast.BroadcastTime & 0x00FF); + tData[5] = 0; //static_cast((Broadcast.BroadcastTime >> 8) & 0x00FF); + tData[6] = 30; //static_cast(Broadcast.VaTime & 0x00FF); + tData[7] = 0; //static_cast((Broadcast.VaTime >> 8) & 0x00FF); + + tAddr = dEepAddrBroadcastSetting + 0; + sDelayMs(10); + eeprom_write_byte_via_page(0, tAddr, tData, 8); + sDelayMs(10); + + ReadSetting (); +} + + + + + + + diff --git a/MyCode/Gui/BroadcastCfg.h b/MyCode/Gui/BroadcastCfg.h new file mode 100644 index 0000000..0e44baa --- /dev/null +++ b/MyCode/Gui/BroadcastCfg.h @@ -0,0 +1,112 @@ +#ifndef BROADCASTCFG_H_ +#define BROADCASTCFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +#pragma pack(push, 1) + +class TBroadcastCfg{ + public: + static constexpr unsigned short hList[12] = {82,82,82,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[0] + 650, + .y = Lv.Grid.Top[0] + 6, + }; + public: + int IsShow; + class TItemList *IList; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned int CtlIndex; + + struct{ + unsigned char PadAddr; + unsigned char Addr; + unsigned char AreaNum; + unsigned char SyncMode; + unsigned short BroadcastTime; + unsigned short VaTime; + }aBroadcast; + + int Sta; + public: + TBroadcastCfg(){}; + void Init(); + static void sDelayMs(unsigned int aMs); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void ShowSyncMode(); + void ShowSta(); + void ShowSta(int aSta); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + void ClearSelected(void); + void Check4Selected(void); + + void LoadData(); + void RestoreData(); + + void PermissionCmdGO(); + void PermissionCmdReturnDraw(); + + static void ReadSetting(); + static void WriteSetting(); + + static void sRecoverSetDefault(); + + int ExtRequst(unsigned char Prm){IsShow =0; return 0;} + +}; + + + +#pragma pack(pop) + +#endif + diff --git a/MyCode/Gui/BusPadLnk.cpp b/MyCode/Gui/BusPadLnk.cpp new file mode 100644 index 0000000..e5fbec7 --- /dev/null +++ b/MyCode/Gui/BusPadLnk.cpp @@ -0,0 +1,1224 @@ +#include "RuntimeData.h" +#include "BusPadLnk.h" +#include "DevMask.h" + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" + #include "HW_config.h" +} + + +#define clEnable clDeepGreen +#define clDisable clSilver + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +#define dAddr_DescpBuf dAddrSdRam_Commom + +static const char NonTypeText[12]= {"未知"}; + +static const char CharBcdText[20]= {"0123456789*------\0"}; + +const short AddrLeft[8] = {20,125,260,440,620,630,640,650}; +const short AddrTop[8] = {88, 130,172,214,256,298,252,296}; + +class TItemList *TBusPadLnk::sIList; + +void TBusPadLnk::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "总线盘"); + TextRender_string24(Lv.Grid.Left[0] + 200, Lv.Grid.Top[0] +6, clNearWhite, "盘使能"); + TextRender_string24(Lv.Grid.Left[0] + 320, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 414, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "状态:"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "节点号"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] + 40, clNearWhite, "共"); + TextRender_string24(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 40, clNearWhite, "点"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "匹配方式"); + TextRender_string24(Lv.Grid.Left[1] + 40, Lv.Grid.Top[1] +40, clNearWhite, "分区"); + TextRender_string24(Lv.Grid.Left[1] + 164, Lv.Grid.Top[1] +40, clNearWhite, "二次码"); + //User Code & Area Assign + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "受控设备二次码"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +38, clNearWhite, "受控设备分区号"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "受控设备类型"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "保存", 14, ItemColor); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "清除", 14, ItemColor); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "BusBrd"); + TextRender_string24(Lv.Grid.Left[0] + 200, Lv.Grid.Top[0] +6, clNearWhite, "Enabled"); + TextRender_string24(Lv.Grid.Left[0] + 320, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 414, Lv.Grid.Top[0] +6, clNearWhite, " Local"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "State"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "Node"); + //TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] + 40, clNearWhite, "共"); + TextRender_string24(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 40, clNearWhite, "Pads"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Matching Method"); + TextRender_string24(Lv.Grid.Left[1] + 40, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + TextRender_string24(Lv.Grid.Left[1] + 164, Lv.Grid.Top[1] +40, clNearWhite, "AuxID"); + //User Code & Area Assign + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Matching AuxID"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +38, clNearWhite, "Matching Zone"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "Matching Dev Type"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "Save", 14, ItemColor); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "Del", 14, ItemColor); + } +} + +void TBusPadLnk::Init(u8 aMode) +{ + IsPermission = 0; + IsViewList = 0; + ResultPst = 0; + Tag.Reset(); + EnterMethod = aMode; + ShowwingResult = 0; + JustShowResult = 0; + if(EnterMethod == 0){ + Tag.InxMin = 0; + }else{ + Tag.InxMin = 1; + } + Tag.Inx = Tag.InxMin; +} + +void TBusPadLnk::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TBusPadLnk::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + + +void TBusPadLnk::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn==0){ + if(EnterMethod) + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "手动控制盘->信息->总线配置"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "手动控制盘->总线配置 "); + }else{ + if(EnterMethod) + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Manual Control Unit->Information->Bus Pad Boards Config"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Manual Control Unit->Bus Pad Boards Config "); + } + + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.PanelSmall.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + for(int i=2; iSTextCtlNum.Init(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 6, 120, 30, 0, 0, clNearWhite, ItemColor); + TextDigitRender2Right24(Lv.Grid.Left[0] + 392, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + + //TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, "分区号注释信息:"); + + IList->STextState.Init(Lv.Grid.Left[0] + 730, Lv.Grid.Top[0] + 2, 68, 30, 0, 0, clNearWhite, ItemColor); + + IList->Edit[1].Init(Lv.Grid.Left[0] +186, Lv.Grid.Top[0] + 38, 48,30,0,0,1,clNearBlack); + IList->Edit[1].SetMaxLen(3); + IList->Edit[1].Str.Clear(); + + + IList->EditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 2, 50, 30, 0, 0, 1, clNearWhite); + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + //IList->EditDescpShow.Init(Lv.Grid.Left[0] + 390, Lv.Grid.Top[0] + 36, 400, 30, 0, 0, 1, clNearWhite); + + IList->STextDType.Enable = 1; + IList->STextDType.Visible =1; + IList->STextState.Enable = 1; + IList->STextState.Visible =1; + IList->STextRegisted.Enable = 1; + IList->STextRegisted.Visible =1; + //IList->STextCtlNum.Enable = 1; + //IList->STextCtlNum.Visible =1; + IList->EditPortNum.TextClear(); + IList->EditAddrNum.TextClear(); + IList->EditPortNum.SetMaxLen(2); + IList->EditAddrNum.SetMaxLen(3); + if(EnterMethod) + IList->EditPortNum.Enable = 0; + else + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible = 1; + IList->EditAddrNum.Enable = 1; + IList->EditAddrNum.Visible = 1; + //IList->EditDescpShow.Enable = 1; + //IList->EditDescpShow.Visible = 1; + + IList->EditUserCode.Init(Lv.Grid.Left[2] + 178, Lv.Grid.Top[2] + 6, 108, 30, 0, 0, 1, clNearWhite); + IList->EditAreaAssign.Init(Lv.Grid.Left[2] + 178, Lv.Grid.Top[2] + 40, 108, 30, 0, 0, 1, clNearWhite); + + IList->EditUserCode.Enable = 1; + IList->EditUserCode.Visible =1; + IList->EditUserCode.SetMaxLen(8); + IList->EditAreaAssign.Enable = 1; + IList->EditAreaAssign.Visible =1; + IList->EditAreaAssign.SetMaxLen(5); + + + IList->Edit[0].Init(Lv.Grid.Left[3] +236, Lv.Grid.Top[3] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(3); + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[3] +4, Lv.Grid.Top[3] + 40, 160,30,0,0,clNearWhite,ItemColor); + + + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.PanelSmall.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); +} + +void TBusPadLnk::DrawKeyCount() +{ + if( (Rt.KeyCount != 48) && (Rt.KeyCount != 64) && (Rt.KeyCount != 128) ){ + Rt.KeyCount = 48; + } + IList->Edit[1].Str.FromUInt3Dg(Rt.KeyCount); + IList->Edit[1].Show(); +} + +void TBusPadLnk::Show() +{ + DrawSelf(); +} + +void TBusPadLnk::FullRedraw(int Prm) +{ + int i, x, y; + if(Prm == 0){ + Show(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawFixText(); + TextDigitRender2Right24(Lv.Grid.Left[0] + 392, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + IList->STextState.Show(); + IList->Edit[1].Show(); + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + DrawIsPadDeActive(); + //Match mode + DrawMatchMode(); + //User Code & Area Assign + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + DrawPadBoardCfgList(); + IsViewList ? ClearSelected() : Check4Selected(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TBusPadLnk::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickSTextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("反馈", 24); else IList->STextState.SetText("FBCK", 24); + }else + if(HandCtlBoard[PadNum-1].KeyState[KeyNum-1]){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("启动", 24); else IList->STextState.SetText("ACT.", 24); + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clDeepGreen, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("正常", 24); else IList->STextState.SetText("IDLE", 24); + } + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + IList->STextState.SetText("----", 24); + } + IList->STextState.Show(); +} +/* +void TBusPadLnk::ReLoadAndDrawAreaDescp() +{ + unsigned char tP0, tP1, Ava, tType, tSta; + unsigned int tAddr; + + Ava = 0; + unsigned int aAddr, i; + unsigned int p0, p1; + unsigned char *p; + + if(PadNum <1)return; + if(KeyNum <1)return; + + if( PadNum <= dHANDCTL_MAX_COUNT ){ + if(KeyNum <= dHANDCTL_KEY_MAX_COUNT){ + p0 = PadNum -1; + p1 = (p0 * dHANDCTL_KEY_MAX_COUNT) + (KeyNum); + p0 = dPORT_MAX_COUNT; + aAddr = dAddrSdRam_Descp + (p0 * 8192) + (p1*32); + for(i=0; i<32; i++){ + //IList->EditDescpShow.Str.Text[i] = *(volatile unsigned char *)(aAddr + i); + } + //IList->EditDescpShow.Str.Text[32] = '\0'; + //IList->EditDescpShow.Str.Text[33] = '\0'; + //IList->EditDescpShow.SetPstTail(); + //IList->EditDescpShow.Show(); + //IList->EditDescpShow.ShowCursor(); + } + } +}*/ + +void TBusPadLnk::DrawUserCodeAssignAreaAssignType() +{ + int iVal; + if( (PadNum == 0) || (KeyNum ==0) || (PadNum >dHANDCTL_MAX_COUNT) || (KeyNum >dHANDCTL_KEY_MAX_COUNT) ) { + IList->EditUserCode.Str.FromStr("--------"); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Str.FromStr("----"); + IList->EditAreaAssign.Show(); + IList->Edit[0].Str.FromStr("---"); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.SetText(" ",24); + IList->STextModuleInDefineType.Show(); + + }else{ + LoadUcBcdText(PadNum-1,KeyNum-1); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Str.FromUInt4Dg(HandCtlBoard[PadNum-1].Area[KeyNum-1]); + IList->EditAreaAssign.Show(); + AssignType = HandCtlBoard[PadNum-1].AssignType[KeyNum-1]; + IList->Edit[0].Str.FromUInt3Dg(AssignType); + IList->Edit[0].Show(); + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal > 255) || (iVal <0) ){ + iVal = 0; + IList->STextModuleInDefineType.SetText(" ",24); + }else{ + if(LanguageEnCn==0) + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + else + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + IList->STextModuleInDefineType.Show(); + } +} + +void TBusPadLnk::DrawIsPadDeActive() +{ + if(Rt.IsPadDeActive){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] + 170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] + 170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + } +} + +void TBusPadLnk::LoadCfg4Edit(unsigned char aPath0, unsigned aPath1) +{ + unsigned char aP0, aP1; + if(aPath0 == 0)return; + if(aPath0 > dHANDCTL_MAX_COUNT)return; + if(aPath1 == 0)return; + if(aPath1 > dHANDCTL_KEY_MAX_COUNT)return; + + aP0 = aPath0 -1; + aP1 = aPath1 -1; + + + AssignType = HandCtlBoard[aP0].AssignType[aP1]; + Rt.IsPadDeActive = HandCtlBoard[aP0].PadIsProhibit; + Rt.IsMatchAreaAssign = HandCtlBoard[aP0].IsMatchAreaAssign[aP1]; + Rt.KeyCount = HandCtlBoard[aP0].KeyCount; + + LoadUcBcdText(aP0, aP1); + + DrawKeyCount(); + DrawIsPadDeActive(); + DrawMatchMode(); +} + +void TBusPadLnk::DrawPadBoardCfgList() +{ + int i, z, x, y; + + unsigned int aClr; + IsViewList ? aClr=clBlue : aClr=clMedGray; + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + + if(PadNum==0) return; + if(PadNum > dHANDCTL_MAX_COUNT) return; + + x = Lv.Panel.Left+6; + y = Lv.Panel.Top +6; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearBlack, PanelColor, "节点 二次码 分区号 匹配方式 设备类型"); + }else{ + TextRender_string24(x, y, clNearBlack, PanelColor, "Node AuxID Zone M-Method Dev Type"); + } + int TopCnt = dHANDCTL_KEY_MAX_COUNT; + for(i=0,z=List.CurrentPage*8; (i<8) && (z>= ((7-g)*4); + aOrd = (f & 0x0000'000F); + List.Text[g] = CharBcdText[aOrd]; + } + List.Text[8] = '\0'; + TextRender_string24(x, y, aClr, PanelColor, List.Text); + x+=120; + TextDigitRender4Right24(x, y, aClr, PanelColor, HandCtlBoard[PadNum-1].Area[z]); + x+=96; + if(LanguageEnCn==0){ + if(HandCtlBoard[PadNum-1].IsMatchAreaAssign[z]){ + TextRender_string24(x, y, aClr, PanelColor, " 分区 "); + }else{ + TextRender_string24(x, y, aClr, PanelColor, "二次码"); + } + }else{ + if(HandCtlBoard[PadNum-1].IsMatchAreaAssign[z]){ + TextRender_string24(x, y, aClr, PanelColor, " Zone "); + }else{ + TextRender_string24(x, y, aClr, PanelColor, "AuxID"); + } + } + x+=136; + TextDigitRender3Right24(x,y,aClr, PanelColor, HandCtlBoard[PadNum-1].AssignType[z]); + } +} + +void TBusPadLnk::SetPath(unsigned char aCtlNum, unsigned char aPath0, unsigned char aPath1) +{ + unsigned char tP0, tP1, tT; + //this->CtlNum = aCtlNum; + //#define dHANDCTL_MAX_COUNT 20 + //#define dHANDCTL_KEY_MAX_COUNT 128 + if(aPath0 && (aPath0 <= dHANDCTL_MAX_COUNT)) { + PadNumValid = 1; + IList->EditPortNum.SelectedColor = clBlue; + }else{ + PadNumValid = 0; + IList->EditPortNum.SelectedColor = clRed; + } + if(aPath1 && (aPath1 <= dHANDCTL_KEY_MAX_COUNT)){ + KeyNumValid = 1; + IList->EditAddrNum.SelectedColor = clBlue; + }else{ + KeyNumValid = 0; + IList->EditAddrNum.SelectedColor = clRed; + } + this->PadNum = aPath0; + this->KeyNum = aPath1; + + IList->EditPortNum.Str.FromUInt2Dg(aPath0); + IList->EditAddrNum.Str.FromUInt3Dg(aPath1); + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + + LoadCfg4Edit(aPath0, aPath1); + DrawState(); + //ReLoadAndDrawAreaDescp(); + DrawUserCodeAssignAreaAssignType(); + List.PageCount = dHANDCTL_KEY_MAX_COUNT / 8; + List.CurrentPage = (KeyNum-1) / 8; + if(List.CurrentPage > (dHANDCTL_KEY_MAX_COUNT / 8))List.CurrentPage =0; + DrawPadBoardCfgList(); + + Check4Selected(); +} + +void TBusPadLnk::InitPanel() +{ + int x,y,x2,y2, aW,aH,i; + + x = 20; + y = 150; + x2 = 799; + y2 = 340; + aW = x2 - x +1; + aH = y2 -y +1; + + aPanel->Init(x,y,aW,aH,0,0,clMoneyGreen, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearWhite,clBlue); + if(LanguageEnCn==0){ + aPanel->Caption.SetText("按中/EN键切换输入法,设置键保存更改,返回键放弃更改并返回",24); + }else{ + aPanel->Caption.SetText("Key 中/EN To Switch Input Method,Key Set To Save",24); + } + aPanel->Caption.Enable = 1; + aPanel->Caption.Visible = 1; + + aPanel->SText[0].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0){ + TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr("Enter Numbers ", aPanel->SText[0].Text); + } + aPanel->SText[0].Enable = 1; + aPanel->SText[0].Visible = 1; + + aPanel->Edit[ 0].Init(10,40,420,30,x,y,1,clNearBlack); + aPanel->Edit[ 0].Str.FromStr(IList->EditDescpShow.Str.Text); + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 1; + } + + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); +} + +void TBusPadLnk::ClearSelected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[0] +170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, 4, ItemColor); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + case 4: + TRoundSquare::sSelected(Lv.Grid.Left[1] +12, Lv.Grid.Top[1] + 38, dWWidth, dWHeigh, 4, ItemColor); + break; + case 5: + TRoundSquare::sSelected(Lv.Grid.Left[1] +136, Lv.Grid.Top[1] + 38, dWWidth, dWHeigh, 4, ItemColor); + break; + case 6: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 7: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 8: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 9: + if(LanguageEnCn==0)tText= "保存";else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 10: + if(LanguageEnCn==0)tText= "清除";else tText="Del "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + + } +} + +void TBusPadLnk::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[0] +170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->Edit[1].Selected = 1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + case 4: + TRoundSquare::sSelected(Lv.Grid.Left[1] +12, Lv.Grid.Top[1] + 38, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 5: + TRoundSquare::sSelected(Lv.Grid.Left[1] +136, Lv.Grid.Top[1] + 38, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 6: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 7: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 8: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 9: + if(LanguageEnCn==0)tText= "保存";else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 6, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 10: + if(LanguageEnCn==0)tText= "清除";else tText="Del "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 6, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + + } +} + +void TBusPadLnk::LoadUcBcdText(unsigned char aP0, unsigned char aP1) +{ + int i; + unsigned int f, aOrd; + f = HandCtlBoard[aP0].UcList[aP1].Full; + for(i=0; i<8; i++){ + f = HandCtlBoard[aP0].UcList[aP1].Full; + f >>= ((7-i)*4); + aOrd = (f & 0x0000'000F); + IList->EditUserCode.Str.Text[i] = CharBcdText[aOrd]; + + } + IList->EditUserCode.Str.Text[8] = '\0'; +} + +void TBusPadLnk::ModifyKeyCount() +{ + if(Rt.KeyCount == 48){ + Rt.KeyCount = 64; + }else + if(Rt.KeyCount == 64){ + Rt.KeyCount = 128; + }else + if(Rt.KeyCount == 128){ + Rt.KeyCount = 48; + }else{ + Rt.KeyCount = 48; + } + IList->Edit[1].Str.FromUInt3Dg(Rt.KeyCount); + IList->Edit[1].Show(); +} + +void TBusPadLnk::RestoreUcBcdText(unsigned char aP0, unsigned char aP1) +{ + int i; + unsigned int f, Val; + uCode.Full = 0; + for(i=0; i<8; i++){ + f = 11; + if( (IList->EditUserCode.Str.Text[i] >= '0') && (IList->EditUserCode.Str.Text[i] <= '9') ) { + f = IList->EditUserCode.Str.Text[i] - '0'; + } + if(IList->EditUserCode.Str.Text[i] == '*')f = 10; + f <<= ((7-i) * 4); + uCode.Full |= f; + } +} + +void TBusPadLnk::PermissionCmdReturnDraw() +{ + int x,y; + Check4Selected(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawPadBoardCfgList(); +} + +void TBusPadLnk::PermissionCmdGO() +{ + int aVal; + unsigned char aP0, aP1; + TUserCode tUserCode; + if(PadNum == 0)return; + if(KeyNum == 0)return; + if(PadNum > dHANDCTL_MAX_COUNT)return; + if(KeyNum > dHANDCTL_KEY_MAX_COUNT)return; + aP0 = PadNum -1; + aP1 = KeyNum -1; + if( (PermissionCmd == CmdWrite) || (PermissionCmd == CmdClear) ){ + if(PermissionCmd == CmdWrite){ + RestoreUcBcdText(aP0, aP1); + aVal = IList->EditAreaAssign.Str.ToInteger(); + if( (aVal > -1) && (aVal <= dAreaCountMax) ){ + AreaNum = aVal; + }else{ + AreaNum = 0; + } + aVal = IList->Edit[0].Str.ToInteger(); + if( (aVal < 256) && (aVal>0) ){ + AssignType = static_cast(aVal); + }else{ + AssignType = 0; + } + }else{ + uCode.Full = 0; + AreaNum = 0; + AssignType = 0; + } + Write2Flash(); + LoadBusPadLnk(); + if( (Rt.IsPadDeActive == HandCtlBoard[aP0].PadIsProhibit) && (Rt.KeyCount == HandCtlBoard[aP0].KeyCount) && (Rt.IsMatchAreaAssign == HandCtlBoard[aP0].IsMatchAreaAssign[aP1]) + && (uCode.Full == HandCtlBoard[aP0].UcList[aP1].Full) && (AssignType == HandCtlBoard[aP0].AssignType[aP1]) /*&& (AreaNum == HandCtlBoard[aP0].Area[aP1])*/){ + ShowwingResult = 1; + JustShowResult = 1; + HandCtlBoard[aP0].SendPadCfg2Pad(aP0); + if(LanguageEnCn==0) + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "保存成功 "); + else + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Save OK "); + }else{ + ShowwingResult = 1; + JustShowResult = 1; + if(LanguageEnCn==0) + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "保存失败 "); + else + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Failed To Save "); + } + SetPath(0, PadNum, KeyNum); + } +} + +TGuiMsgReturn TBusPadLnk::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + unsigned char aP0; + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn SubRtnMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + int HadPrc = 0; + int iVal; + JustShowResult = 0; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + }else + if(IsViewList){ + switch(aKey){ + case VK_UP: + if(List.CurrentPage >0){ + List.CurrentPage--; + DrawPadBoardCfgList(); + } + break; + case VK_DOWN: + if(List.CurrentPage < (dHANDCTL_KEY_MAX_COUNT / 8 -1) ){ + List.CurrentPage++; + DrawPadBoardCfgList(); + } + break; + case VK_TAB: + IsViewList = 0; + DrawPadBoardCfgList(); + Check4Selected(); + break; + } + if(aKey == VK_RETURN){ + IsShow = 0; + aMsg = guiMsgReturn; + } + }else{ + switch(aKey){ + case dfKEY_ASTERISK: + if(Tag.Inx == 6){ + //User Code + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + } + break; + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx == 0){ + if(aKey == VK_RIGHT){ + if(IList->EditPortNum.Pst >= IList->EditPortNum.Str.GetEndPst()){ + ClearSelected(); + Tag.Inx = 1; + Check4Selected(); + HadPrc = 1; + } + } + if(HadPrc == 0){ + IList->EditPortNum.KeyIn(aKey); + iVal = IList->EditPortNum.Str.ToInteger(); + if( (iVal) && (iVal <= dDIRECTCTL_MAX_COUNT) ){ + IList->EditPortNum.SelectedColor = clBlue; + PadNumValid = 1; + }else{ + IList->EditPortNum.SelectedColor = clRed; + PadNumValid = 0; + } + if(PadNum != iVal){ + PadNum = iVal; + LoadCfg4Edit(PadNum, KeyNum); + DrawState(); + DrawUserCodeAssignAreaAssignType(); + List.PageCount = dHANDCTL_KEY_MAX_COUNT / 8; + List.CurrentPage = (KeyNum-1) / 8; + if(List.CurrentPage > (dHANDCTL_KEY_MAX_COUNT / 8))List.CurrentPage =0; + DrawPadBoardCfgList(); + } + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + } + }else + if(Tag.Inx == 1){ + if(VK_LEFT == aKey){ + if(Tag.Inx > Tag.InxMin){ + ClearSelected(); + Tag.Inx = 0; + Check4Selected(); + } + } + }else + if(Tag.Inx == 2){ + if(aKey == VK_RIGHT){ + if(IList->EditAddrNum.Pst >= IList->EditAddrNum.Str.GetEndPst()){ + ClearSelected(); + Tag.Inx = 3; + Check4Selected(); + HadPrc = 1; + } + } + if(HadPrc == 0){ + IList->EditAddrNum.KeyIn(aKey); + iVal = IList->EditAddrNum.Str.ToInteger(); + if( (iVal) && (iVal <= dHANDCTL_KEY_MAX_COUNT) ){ + IList->EditAddrNum.SelectedColor = clBlue; + KeyNumValid =1; + }else{ + IList->EditAddrNum.SelectedColor = clRed; + KeyNumValid = 0; + } + if(KeyNum != iVal){ + KeyNum = iVal; + LoadCfg4Edit(PadNum, KeyNum); + DrawState(); + DrawUserCodeAssignAreaAssignType(); + List.PageCount = dHANDCTL_KEY_MAX_COUNT / 8; + List.CurrentPage = (KeyNum-1) / 8; + if(List.CurrentPage > (dHANDCTL_KEY_MAX_COUNT / 8))List.CurrentPage =0; + DrawPadBoardCfgList(); + } + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + } + }else + if(Tag.Inx == 3){ + //KeyCount + ModifyKeyCount(); + }else + if(Tag.Inx == 4){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx = 5; + Check4Selected(); + } + }else + if(Tag.Inx == 5){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx = 4; + Check4Selected(); + } + }else + if(Tag.Inx == 6){ + //User Code + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + }else + if(Tag.Inx == 7){ + //Area + IList->EditAreaAssign.KeyIn(aKey); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + }else + if(Tag.Inx == 8){ + //Define Type + IList->Edit[0].KeyIn(aKey); + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal > 255) || (iVal <0) ){ + iVal = 0; + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText(" ",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + if(LanguageEnCn==0) + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + else + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + AssignType = iVal; + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + IList->STextModuleInDefineType.Show(); + }else + if(Tag.Inx == 9){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx = 10; + Check4Selected(); + } + }else + if(Tag.Inx == 10){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx = 9; + Check4Selected(); + } + } + break; + case VK_UP: + if(Tag.Inx > Tag.InxMin){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx =10; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx < 10){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx = Tag.InxMin; + Check4Selected(); + } + break; + case VK_TAB: + IsViewList = 1; + ClearSelected(); + List.PageCount = dHANDCTL_KEY_MAX_COUNT / 8; + List.CurrentPage = KeyNum / 8; + if(List.CurrentPage > (dHANDCTL_KEY_MAX_COUNT / 8))List.CurrentPage =0; + DrawPadBoardCfgList(); + break; + case dfKEY_ENCN: + + break; + case dfKEY_SETUP: + if(Tag.Inx == 1){ + Rt.IsPadDeActive = Rt.IsPadDeActive ? 0 : 1; + DrawIsPadDeActive(); + }else + if( (Tag.Inx == 4) || (Tag.Inx ==5) ){ + Rt.IsMatchAreaAssign = Rt.IsMatchAreaAssign ? 0 : 1; + DrawMatchMode(); + } + break; + case VK_F2: + + break; + case VK_EXECUTE: + if(Tag.Inx == 1){ + Rt.IsPadDeActive = Rt.IsPadDeActive ? 0 : 1; + DrawIsPadDeActive(); + }else + if( (Tag.Inx == 4) || (Tag.Inx ==5) ){ + Rt.IsMatchAreaAssign = Rt.IsMatchAreaAssign ? 0 : 1; + DrawMatchMode(); + }else + if( (PadNum) && (KeyNum) && (PadNum <= dHANDCTL_MAX_COUNT) && (KeyNum <=dHANDCTL_KEY_MAX_COUNT) ) { + if( (Tag.Inx == 9) || (Tag.Inx == 10) ){ + //Save CFG - + ResultPst = 4; + if(Tag.Inx == 9)PermissionCmd = CmdWrite; else PermissionCmd = CmdClear; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + break; + } + + if(aKey == VK_RETURN){ + IsShow = 0; + aMsg = guiMsgReturn; + } + } + + if( (ShowwingResult) && (JustShowResult == 0) ){ + ShowwingResult = 0; + JustShowResult = 0; + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, " "); + } + return aMsg; +} + +void TBusPadLnk::sWriteOnePad(unsigned char aPad) +{ + unsigned int fAddr; + unsigned int i,x; + volatile unsigned int GetSta; + unsigned char aP0; + + //HandCtlBoard[aP0].UcList[aP1].Full = uCode.Full; + //HandCtlBoard[aP0].Area[aP1] = AreaNum; + //HandCtlBoard[aP0].AssignType[aP1] = AssignType; + //HandCtlBoard[aP0].IsMatchAreaAssign[aP1] = Rt.IsMatchAreaAssign; + //HandCtlBoard[aP0].PadIsProhibit = Rt.IsPadDeActive; + //HandCtlBoard[aP0].KeyCount = Rt.KeyCount; + + if(sIList==nullptr)return; + if(aPad==0)return; + if(aPad>dHANDCTL_KEY_MAX_COUNT)return; + aP0 = aPad-1; + sIList->ReadWriteData.Reset(); + LoopCheck1S(); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(GetSta); + + fAddr = dFlashAddrBusPadLnk + (aP0 * 4096); + nor_erase_sector_4k(dFlashBusPadLnkChipX,fAddr); + sDelayMs(100); + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(GetSta); + LoopCheck1S(); + Crc32Reset(); + //UcList + for(i=0; i<2; i++){ + for(x=0;x<64;x++){ + sIList->ReadWriteData.D32[x] = HandCtlBoard[aP0].UcList[i*64 +x].Full; + Crc32Feed(HandCtlBoard[aP0].UcList[i*64 +x].Full); + } + fAddr = dFlashAddrBusPadLnk + (aP0 * 4096) + (i * 256); + nor_write_page(dFlashBusPadLnkChipX, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(GetSta); + } + LoopCheck1S(); + //AssignType + for(x=0;xReadWriteData.D8[x] = HandCtlBoard[aP0].AssignType[x]; + Crc32Feed(static_cast(HandCtlBoard[aP0].AssignType[x])); + + } + fAddr = dFlashAddrBusPadLnk + (aP0 * 4096) + (2 * 256); + nor_write_page(dFlashBusPadLnkChipX, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(GetSta); + LoopCheck1S(); + //IsMatchAreaAssign + for(x=0;xReadWriteData.D8[x] = HandCtlBoard[aP0].IsMatchAreaAssign[x]; + Crc32Feed(static_cast(HandCtlBoard[aP0].IsMatchAreaAssign[x])); + } + fAddr = dFlashAddrBusPadLnk + (aP0 * 4096) + (3 * 256); + nor_write_page(dFlashBusPadLnkChipX, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(GetSta); + LoopCheck1S(); + //Area Code + for(x=0;xReadWriteData.D16[x] = HandCtlBoard[aP0].Area[x]; + Crc32Feed(static_cast(HandCtlBoard[aP0].Area[x])); + } + fAddr = dFlashAddrBusPadLnk + (aP0 * 4096) + (4 * 256); + nor_write_page(dFlashBusPadLnkChipX, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(GetSta); + LoopCheck1S(); + //IsPadDeActive, KeyCount, Crc; + sIList->ReadWriteData.D8[0] = HandCtlBoard[aP0].PadIsProhibit; + sIList->ReadWriteData.D8[1] = HandCtlBoard[aP0].KeyCount; + Crc32Feed(static_cast(HandCtlBoard[aP0].PadIsProhibit)); + Crc32Feed(static_cast(HandCtlBoard[aP0].KeyCount)); + + sIList->ReadWriteData.D32[1] = Crc32GetResult(); + fAddr = dFlashAddrBusPadLnk + (aP0 * 4096) + (5 * 256); + nor_write_page(dFlashBusPadLnkChipX, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(GetSta); +} + +void TBusPadLnk::Write2Flash() +{ + unsigned int i; + unsigned char aP0, aP1; + + if(PadNum == 0)return; + if(KeyNum == 0)return; + if(PadNum > dHANDCTL_MAX_COUNT) return; + if(KeyNum > dHANDCTL_KEY_MAX_COUNT) return; + if(PadNumValid == 0)return; + if(KeyNumValid == 0)return; + + //Erase 1 * 4K Blocks + aP0 = PadNum -1; + aP1 = KeyNum -1; + + HandCtlBoard[aP0].UcList[aP1].Full = uCode.Full; + HandCtlBoard[aP0].Area[aP1] = AreaNum; + HandCtlBoard[aP0].AssignType[aP1] = AssignType; + HandCtlBoard[aP0].IsMatchAreaAssign[aP1] = Rt.IsMatchAreaAssign; + HandCtlBoard[aP0].PadIsProhibit = Rt.IsPadDeActive; + HandCtlBoard[aP0].KeyCount = Rt.KeyCount; + + sIList = IList; + sWriteOnePad(PadNum); +} + + +void TBusPadLnk::LoadBusPadLnk() +{ + if(PadNum == 0)return; + if(PadNum > dHANDCTL_MAX_COUNT)return; + Record.LoadBusPadLnk(PadNum); +} + +void TBusPadLnk::sRecoverSetDefault() +{ + unsigned char aP0; + //Erase 1 * 4K Blocks + for(aP0=0; aP0 < dHANDCTL_MAX_COUNT; aP0++){ + SysLoopTick = 0; + for(int x=0; xEdit[0].Str.ToInteger(); + if(aVal >1)aVal--; + aPanel->Edit[0].Str.FromInt(aVal); + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[0].Show(); + }else + if(CtlIndex == 2){ + aVal = aPanel->Edit[1].Str.ToInteger(); + if(aVal >1)aVal--; + aPanel->Edit[1].Str.FromInt(aVal); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[1].Show(); + }else + if(CtlIndex == 3){ + if(IsUsing == 0){ + IsUsing = 1; + aPanel->Edit[2].Str.FromStr("启动"); + }else{ + IsUsing = 0; + aPanel->Edit[2].Str.FromStr("禁用"); + } + aPanel->Edit[2].ReDraw(); + } +} + +void TBusPadProgram::TryIncValue() +{ + int aVal; + if(CtlIndex == 1){ + aVal = aPanel->Edit[0].Str.ToInteger(); + if(aVal < 8)aVal++; + aPanel->Edit[0].Str.FromInt(aVal); + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[0].Show(); + }else + if(CtlIndex == 2){ + aVal = aPanel->Edit[1].Str.ToInteger(); + if(aVal < 128)aVal++; + aPanel->Edit[1].Str.FromInt(aVal); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[1].Show(); + }else + if(CtlIndex == 3){ + if(IsUsing == 0){ + IsUsing = 1; + aPanel->Edit[2].Str.FromStr("启动"); + }else{ + IsUsing = 0; + aPanel->Edit[2].Str.FromStr("禁用"); + } + aPanel->Edit[2].ReDraw(); + } +} + +void TBusPadProgram::Check4Selected(void) +{ + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Btn[0].Selected = 0; + EditML.Selected = 0; + switch(CtlIndex){ + case 0: + aPanel->Btn[0].Selected = 1; + break; + case 1: + aPanel->Edit[0].Selected = 1; + break; + case 2: + aPanel->Edit[1].Selected = 1; + break; + case 3: + aPanel->Edit[2].Selected = 1; + break; + case 4: + EditML.Selected = 1; + break; + default: + + break; + } +} + +void TBusPadProgram::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[0].Init(126,39,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[1].Init(126,75,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[2].Init(126,111,70,30,x,yt,clNearBlack,clFrmFace); + + TMyString::sFromStr("盘号", aPanel->SText[0].Text); + TMyString::sFromStr("按键号", aPanel->SText[1].Text); + TMyString::sFromStr("启用或禁用", aPanel->SText[2].Text); + + for(i=0; i<3;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + + aPanel->Edit[0].Init(260,39,80,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(260,75,80,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(260,111,80,30,x,yt,clNearBlack,clNearWhite); + + for(i=0; i<3;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + } + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[0].SetInputMaskEn(); + aPanel->Edit[0].Str.FromStr("01"); + aPanel->Edit[0].Pst = 1; + + aPanel->Edit[1].SetMaxLen(3); + aPanel->Edit[1].SetInputMaskEn(); + aPanel->Edit[1].Str.FromStr("001"); + aPanel->Edit[1].Pst = 2; + + aPanel->Edit[2].SetMaxLen(4); + aPanel->Edit[2].SetInputMaskEn(); + aPanel->Edit[2].Str.FromStr("----"); + aPanel->Edit[2].Pst = 3; + + aPanel->Btn[0].Init(240,0,120,32,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[0].Caption.FromStr("保存所有"); + for(i=0; i<1;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(10); + aPanel->Btn[i].SelectedColor = clBlue; + } + + if(IsProgram == 0){ + aPanel->Edit[2].Enable = 0; + EditML.Enable = 0; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + EditML.Show(); +} + +void TBusPadProgram::LoadExpression() +{ + unsigned int i; + for(i=0; i<190;i++){ +// ExpressionText[i] = 'A'; + } +} + +void TBusPadProgram::SetEditStart(void) +{ + int x,y,w,h; + OnEditing = 1; + EditIndex = CtlIndex; + LoadExpression(); + EditML.SetMaxLen(199); +// EditML.Str.FromStr(ExpressionText); + EditML.SetPstTail(); + EditML.Show(); +} + +void TBusPadProgram::RestoreFromEdit(void) +{ +// TMyString::sFromStr(EditML.Str.Text, ExpressionText); +} + +TGuiMsgReturn TBusPadProgram::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn aMsgMBox; + unsigned char LoadKey; + char LastChr; + + if(0){ + aMsgMBox = MessageBox.KeyIn(aKey); + if(aMsgMBox == guiMsgSel1AndReturn){ + //Read + }else + if(aMsgMBox == guiMsgSel2AndReturn){ + //Write + }else{ + + } + IsReadWriteReq = 0; + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + EditML.ReDraw(); + IsInputSymbol = 0; + return aMsg; + } + if(IsProgram){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + case VK_DECIMAL: + case VK_OEM_2: + LoadKey = aKey; + if( aKey == VK_DECIMAL){ + // '*' + if(CtlIndex ==4){ + if(IsInputSymbol){ + LastChr = EditML.GetCurrentChar(); + if(LastChr == CharBusPadProgram[0])EditML.SetCurrentChar(CharBusPadProgram[1]); + else if(LastChr == CharBusPadProgram[1])EditML.SetCurrentChar(CharBusPadProgram[2]); + else if(LastChr == CharBusPadProgram[2])EditML.SetCurrentChar(CharBusPadProgram[3]); + else if(LastChr == CharBusPadProgram[3])EditML.SetCurrentChar(CharBusPadProgram[4]); + else if(LastChr == CharBusPadProgram[4])EditML.SetCurrentChar(CharBusPadProgram[5]); + else if(LastChr == CharBusPadProgram[5])EditML.SetCurrentChar(CharBusPadProgram[6]); + else if(LastChr == CharBusPadProgram[6])EditML.SetCurrentChar(CharBusPadProgram[7]); + else if(LastChr == CharBusPadProgram[7])EditML.SetCurrentChar(CharBusPadProgram[8]); + else if(LastChr == CharBusPadProgram[8])EditML.SetCurrentChar(CharBusPadProgram[9]); + else if(LastChr == CharBusPadProgram[9])EditML.SetCurrentChar(CharBusPadProgram[0]); + else EditML.KeyIn(CharBusPadProgram[0]); + EditML.ReDraw(); + }else{ + EditML.KeyIn(CharBusPadProgram[0]); + EditML.ReDraw(); + IsInputSymbol = 1; + } + } + }else + if(aKey == VK_OEM_2){ + //'#' + if(CtlIndex ==4){ + IsInputSymbol = 0; + EditML.KeyIn(' '); + EditML.ReDraw(); + } + }else{ + if(CtlIndex ==1){ + if(aPanel != nullptr){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].ReDraw(); + } + }else + if(CtlIndex ==2){ + if(aPanel != nullptr){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].ReDraw(); + } + }else + if(CtlIndex == 3){ + if(IsUsing){ + IsUsing = 0; + if(aPanel != nullptr){ + aPanel->Edit[2].Str.FromStr("禁用"); + aPanel->Edit[2].ReDraw(); + } + }else{ + IsUsing = 1; + if(aPanel != nullptr){ + aPanel->Edit[2].Str.FromStr("启用"); + aPanel->Edit[2].ReDraw(); + } + } + } + if(CtlIndex ==4){ + if(IsInputSymbol){ + IsInputSymbol = 0; + LoadKey = aKey - '0'; + if(LoadKey < 10){ + EditML.SetCurrentChar(CharBusPadProgram[LoadKey]); + EditML.ReDraw(); + } + }else{ + EditML.KeyIn(aKey); + EditML.ReDraw(); + } + } + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + if(aPanel != nullptr){ + Check4Selected(); + aPanel->ReDrawItems(); + } + IsInputSymbol = 0; + EditML.ReDraw(); + } + break; + case VK_DOWN: + if(CtlIndex <4){ + CtlIndex++; + if(aPanel != nullptr){ + Check4Selected(); + aPanel->ReDrawItems(); + } + IsInputSymbol = 0; + EditML.ReDraw(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + TryDecValue(); + break; + case dfKEY_QUERY: //0x71 // Key value for QUERY + TryIncValue(); + break; + case VK_TAB: + /*IsReadWriteReq = 1; + MessageBox.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + MessageBox.SetBtnOk1Ok2Cancel(); + MessageBox.SetReturnValue(guiMsgSel1AndReturn, guiMsgSel2AndReturn, guiMsgReturn, guiMsgNone); + MessageBox.Show(); + MessageBox.DoReadWriteBusPad();*/ + break; + case VK_EXECUTE: + IsInputSymbol = 0; + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(CtlIndex ==1){ + if(aPanel != nullptr){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].ReDraw(); + } + }else + if(CtlIndex ==2){ + if(aPanel != nullptr){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].ReDraw(); + } + } + break; + case VK_UP: + if(CtlIndex >1){ + CtlIndex--; + if(aPanel != nullptr){ + Check4Selected(); + aPanel->ReDrawItems(); + } + EditML.ReDraw(); + } + break; + case VK_DOWN: + if(CtlIndex <2){ + CtlIndex++; + if(aPanel != nullptr){ + Check4Selected(); + aPanel->ReDrawItems(); + } + EditML.ReDraw(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + TryDecValue(); + break; + case dfKEY_QUERY: //0x71 // Key value for QUERY + TryIncValue(); + break; + case VK_TAB: + break; + case VK_EXECUTE: + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + + + + + + + + + + + diff --git a/MyCode/Gui/BusPadProgram.h b/MyCode/Gui/BusPadProgram.h new file mode 100644 index 0000000..c9eb4eb --- /dev/null +++ b/MyCode/Gui/BusPadProgram.h @@ -0,0 +1,105 @@ +#ifndef BUSPADPROGRAM_H_ +#define BUSPADPROGRAM_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "EditML.h" +#include "CtlPanel1.h" + +class TBusPadProgram{ + public: + TStaticText Caption; + + class TEdit vEdit; + class TEditML EditML; + + u32 Color; + + TRect Bound; + TRect Content; + TRect RectPanel; + class TCtlPanel1 *aPanel; + + unsigned char Count; + unsigned char ItemsIndex; + unsigned char EditIndex; + unsigned char OnEditing; + unsigned char CtlIndex; + unsigned char IsUsing; + unsigned char CharIndex; + unsigned char IsInputSymbol; + unsigned char IsReadWriteReq; + unsigned char IsProgram; + + char cText[4]; + public: + TBusPadProgram(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void RenderBackGround(void); + + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void DrawCaption(void); + void Show(); + void Paint(); + + void Check4Selected(); + void InitPanel(); + + void TryDecValue(); + void TryIncValue(); + + void LoadCfg(); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void LoadExpression(); + void SetEditStart(void); + void RestoreFromEdit(void); + + int ExtRequst(unsigned char Prm){return 0;} + +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/CanNetworkInf.cpp b/MyCode/Gui/CanNetworkInf.cpp new file mode 100644 index 0000000..085f0ce --- /dev/null +++ b/MyCode/Gui/CanNetworkInf.cpp @@ -0,0 +1,237 @@ +#include "CanNetworkInf.h" +#include "Runtime.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +//#define dFlash4AreaChip (0) +//#define dFlash4Area (0x00BB'0000) + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TCanNetworkInf::Init() +{ + +} + +void TCanNetworkInf::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick组网信息"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "本机号"); + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[0] + 116, Lv.Grid.Top[0] +6, clNearWhite, "集中机"); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[0] + 116, Lv.Grid.Top[0] +6, clNearWhite, "区域机"); + + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +40, clNearWhite, "集中机号:"); + TextDigitRender2_24(Lv.Grid.Left[0] + 510, Lv.Grid.Top[0] +40, clNearWhite, ProtoC2C.MasterNum); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 116, Lv.Grid.Top[0] +6, clNearWhite, "单机 "); + } + TextRender_string24(Lv.Grid.Left[0] + 460, Lv.Grid.Top[0] +6, clNearWhite, " 屏蔽的控制器号:"); + + TextRender_string24(Lv.Grid.Left[0] + 10 + 0, Lv.Grid.Top[0] +40, clNearWhite, "区域机到集中机连接数:"); + TextDigitRender2_24(Lv.Grid.Left[0] + 10 + 252, Lv.Grid.Top[0] +40, clNearWhite, ProtoC2C.SlaveCount +1); + TextRender_string24(Lv.Grid.Left[0] + 10 + 276, Lv.Grid.Top[0] +40, clNearWhite, "台"); + + TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top +4, clNearWhite, "信息互联的集中机号:"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Local Network->Informatiom"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[0] + 116, Lv.Grid.Top[0] +6, clNearWhite, "Central "); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[0] + 116, Lv.Grid.Top[0] +6, clNearWhite, "Regional "); + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +40, clNearWhite, "CentralID"); + TextDigitRender2_24(Lv.Grid.Left[0] + 510, Lv.Grid.Top[0] +40, clNearWhite, ProtoC2C.MasterNum); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 116, Lv.Grid.Top[0] +6, clNearWhite, "Stand Alone "); + } + TextRender_string24(Lv.Grid.Left[0] + 460, Lv.Grid.Top[0] +6, clNearWhite, "Blocking Ctrl ID(s):"); + + TextRender_string24(Lv.Grid.Left[0] + 10 + 0, Lv.Grid.Top[0] +40, clNearWhite, "Slaver-Master Interlinked Items:"); + TextDigitRender2_24(Lv.Grid.Left[0] + 10 + 384, Lv.Grid.Top[0] +40, clNearWhite, ProtoC2C.SlaveCount +1); + TextRender_string24(Lv.Grid.Left[0] + 10 + 408, Lv.Grid.Top[0] +40, clNearWhite, "Pcs"); + + TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top +4, clNearWhite, "Shared Info Masters List:"); + } +} + +void TCanNetworkInf::DrawSelf(void) +{ + int xp; + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; i0) && (ProtoC2C.SlaveList[i] <=dNETWORK_MACHINE_COUNT) ){ + xp = x + (c *262); + TextDigitRender2_24(xp, y, clNearWhite, ProtoC2C.SlaveList[i]); + if(LanguageEnCn==0)TextRender_string24(xp + 30, y, clNearWhite, "火灾报警控制器"); + else TextRender_string24(xp + 30, y, clNearWhite, "FireAlram Ctrl"); + c++; + if(c > 2){ + c=0; + y+= 28; + } + } + } +} + +//_____________________________________________________________________________________________________________________________ + + +void TCanNetworkInf::DrawHadMask() +{ + if( (ProtoC2C.CtlMask.StartNum) && (ProtoC2C.CtlMask.EndNum) ){ + //TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top +6, clNearWhite, PanelColor, "已屏蔽号段:"); + TextDigitRender2_24(Lv.Grid.Left[0] + 460 + 240 + 0, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, ProtoC2C.CtlMask.StartNum); + TextRender_string24(Lv.Grid.Left[0] + 460 + 240 + 28, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, "-"); + TextDigitRender2_24(Lv.Grid.Left[0] + 460 + 240 + 46, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, ProtoC2C.CtlMask.EndNum); + }else{ + //TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top +6, clNearWhite, PanelColor, "已屏蔽号段:"); + TextRender_string24(Lv.Grid.Left[0] + 460 + 240 + 0, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, "--"); + TextRender_string24(Lv.Grid.Left[0] + 460 + 240 + 28, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, "-"); + TextRender_string24(Lv.Grid.Left[0] + 460 + 240 + 46, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, "--"); + } +} + +void TCanNetworkInf::DrawMasterList() +{ + int x, y, i; + x = Lv.PanelSmall.Left + 10; + y = Lv.PanelSmall.Top + 32; + for(i=0; (i网络屏蔽"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "本机号:"); + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[0] + 126, Lv.Grid.Top[0] +6, clNearWhite, "集中机"); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[0] + 126, Lv.Grid.Top[0] +6, clNearWhite, "区域机"); + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, "集中机号:"); + TextDigitRender2_24(Lv.Grid.Left[0] + 516, Lv.Grid.Top[0] +6, clNearWhite, ProtoC2C.MasterNum); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 126, Lv.Grid.Top[0] +6, clNearWhite, "单机 "); + } + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +40, clNearWhite, "网络机器数:"); + + TextRender_string24(Lv.Grid.Left[0] + 176, Lv.Grid.Top[0] +40, clNearWhite, "台"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "网络屏蔽号段"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +40, clNearWhite, "机器号"); + TRoundRect::sDrawBySize(xMask, Lv.Grid.Top[2] + 76, 76, 30, 7, clNearWhite, "屏蔽", 14, clNearBlack); + TRoundRect::sDrawBySize(xUnMask, Lv.Grid.Top[2] + 76, 124, 30, 7, clNearWhite, "取消屏蔽", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Local Network->Blocking Net Ctrl Unit"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Local:"); + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[0] + 126, Lv.Grid.Top[0] +6, clNearWhite, " Central "); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[0] + 126, Lv.Grid.Top[0] +6, clNearWhite, " Regional "); + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, " CentralID"); + TextDigitRender2_24(Lv.Grid.Left[0] + 516, Lv.Grid.Top[0] +6, clNearWhite, ProtoC2C.MasterNum); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 126, Lv.Grid.Top[0] +6, clNearWhite, " Stand Alone"); + } + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +40, clNearWhite, "On Network"); + + TextRender_string24(Lv.Grid.Left[0] + 176, Lv.Grid.Top[0] +40, clNearWhite, "Pcs,"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Blocking ID Range"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +40, clNearWhite, "CtrlID"); + TRoundRect::sDrawBySize(xMask, Lv.Grid.Top[2] + 76, 76, 30, 7, clNearWhite, "Mask", 14, clNearBlack); + TRoundRect::sDrawBySize(xUnMask, Lv.Grid.Top[2] + 76, 124, 30, 7, clNearWhite, " Clear ", 14, clNearBlack); + } +} + +void TCanNetworkMask::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iEditCtlNum.Init(Lv.Grid.Left[2] + 84, Lv.Grid.Top[2] +36, 36, 32, 0,0, 1, clNearWhite); + IList->EditCtlNum.SetMaxLen(2); + IList->EditCtlNum.TextClear(); + IList->EditCtlNum.SetPstTail(); + IList->EditAddrNum.Init(Lv.Grid.Left[2] + 136, Lv.Grid.Top[2] +36, 36, 32, 0,0, 1, clNearWhite); + IList->EditAddrNum.SetMaxLen(2); + IList->EditAddrNum.TextClear(); + IList->EditAddrNum.SetPstTail(); + IList->EditCtlNum.Show(); + IList->EditAddrNum.Show(); +} + +void TCanNetworkMask::Show(void) +{ + IsShowing = 1; + RenderBackGround(); + DrawSelf(); + Check4Selected(); +} + +void TCanNetworkMask::FullRedraw(int Prm) +{ + if(Prm == 0){ + IsShowing = 1; + RenderBackGround(); + DrawSelf(); + + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; iEditCtlNum.Show(); + IList->EditAddrNum.Show(); + if(IsPermission){ + PmsIntervene4Gui.ReDraw4GuiRecall(); + }else{ + Check4Selected(); + } + } +} + +//_____________________________________________________________________________________________________________________________ +void TCanNetworkMask::DrawHadMask() +{ + if(LanguageEnCn==0)TextRender_string24(Lv.Grid.Left[0] + 240, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "已屏蔽号段:"); + else TextRender_string24(Lv.Grid.Left[0] + 240, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "Blocking ID"); + if( (ProtoC2C.CtlMask.StartNum) && (ProtoC2C.CtlMask.EndNum) ){ + TextDigitRender2_24(Lv.Grid.Left[0] + 380, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, ProtoC2C.CtlMask.StartNum); + TextRender_string24(Lv.Grid.Left[0] + 408, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "-"); + TextDigitRender2_24(Lv.Grid.Left[0] + 426, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, ProtoC2C.CtlMask.EndNum); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 380, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "00"); + TextRender_string24(Lv.Grid.Left[0] + 408, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "-"); + TextRender_string24(Lv.Grid.Left[0] + 426, Lv.Grid.Top[0] +40, clNearWhite, ItemColor, "00"); + } +} + +void TCanNetworkMask::PermissionCmdReturnDraw() +{ + RectFillRender(0, Lv.Grid.Bottom[2] +2, 799, 440, ContentColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +void TCanNetworkMask::PermissionCmdGO() +{ + if(PermissionCmd == 1){ + //Do Mask + ProtoC2C.WriteMaskCtlNum(StartNum, EndNum); + ProtoC2C.ReadMaskCtlNum(); + DrawHadMask(); + }else + if(PermissionCmd == 2){ + //Do UnMask + ProtoC2C.WriteMaskCtlNum(0, 0); + ProtoC2C.ReadMaskCtlNum(); + DrawHadMask(); + } +} + +void TCanNetworkMask::sRecoverSetDefault() +{ + ProtoC2C.WriteMaskCtlNum(0, 0); + ProtoC2C.ReadMaskCtlNum(); +} + + +void TCanNetworkMask::ClearSelected() +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->EditCtlNum.Selected =0; + IList->EditCtlNum.Show(); + break; + case 1: + IList->EditAddrNum.Selected =0; + IList->EditAddrNum.Show(); + break; + case 2: + if(LanguageEnCn==0)tText="屏蔽"; else tText="Mask"; + TRoundRect::sDrawBySize(xMask, Lv.Grid.Top[2] + 76, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 3: + if(LanguageEnCn==0)tText="取消屏蔽"; else tText=" Clear "; + TRoundRect::sDrawBySize(xUnMask, Lv.Grid.Top[2] + 76, 124, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +void TCanNetworkMask::Check4Selected() +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->EditCtlNum.Selected =1; + IList->EditCtlNum.SetPstTail(); + IList->EditCtlNum.Show(); + break; + case 1: + IList->EditAddrNum.Selected =1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + break; + case 2: + if(LanguageEnCn==0)tText="屏蔽"; else tText="Mask"; + TRoundRect::sDrawBySize(xMask, Lv.Grid.Top[2] + 76, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 3: + if(LanguageEnCn==0)tText="取消屏蔽"; else tText=" Clear "; + TRoundRect::sDrawBySize(xUnMask, Lv.Grid.Top[2] + 76, 124, 30, 7, clBlue, tText, 14, clNearWhite); + break; + } +} + +int TCanNetworkMask::CheckStart2EndNumValid() +{ + if( (StartNum) && (EndNum) ){ + if( (StartNum <=dNETWORK_MACHINE_COUNT) && (EndNum <=dNETWORK_MACHINE_COUNT) && (StartNum <= EndNum) ) + Start2EndNumValid = 1; + else + Start2EndNumValid = 0; + }else + if( StartNum || EndNum){ + Start2EndNumValid = 0; + }else{ + Start2EndNumValid = 1; + } + + if(Start2EndNumValid){ + IList->EditCtlNum.SelectedColor = clBlue; + IList->EditAddrNum.SelectedColor = clBlue; + IList->EditCtlNum.Color = clNearWhite; + IList->EditAddrNum.Color = clNearWhite; + }else{ + IList->EditCtlNum.SelectedColor = clRed; + IList->EditAddrNum.SelectedColor = clRed; + IList->EditCtlNum.Color = clRed; + IList->EditAddrNum.Color = clRed; + } + + return Start2EndNumValid; +} + + +TGuiMsgReturn TCanNetworkMask::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + unsigned int aAddr, HadPrc; + TDMix aFullPath; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else + if(IsOnGoing){ + switch(aKey){ + case VK_RETURN: + IsShowing = 0; + IsOnGoing = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + HadPrc =0; + if( (aKey == VK_LEFT) || (aKey == VK_RIGHT) ){ + if(CtlIndex == 0){ + if(aKey == VK_RIGHT){ + if(IList->EditCtlNum.Pst >= IList->EditCtlNum.Str.GetEndPst()){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + } + }else + if(CtlIndex == 1){ + if(aKey == VK_LEFT){ + if(IList->EditAddrNum.Pst < 0){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + } + }else + if(CtlIndex == 2){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 3){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + } + } + if(HadPrc == 0){ + if(CtlIndex == 0){ + IList->EditCtlNum.KeyIn(aKey); + int iVal; + iVal = IList->EditCtlNum.Str.ToInteger(); + if( (iVal <0) || (iVal > dNETWORK_MACHINE_COUNT) ) StartNum = 99; + else StartNum = iVal; + CheckStart2EndNumValid(); + IList->EditCtlNum.Show(); + IList->EditAddrNum.Show(); + }else + if(CtlIndex == 1){ + IList->EditAddrNum.KeyIn(aKey); + int iVal; + iVal = IList->EditAddrNum.Str.ToInteger(); + if( (iVal <0) || (iVal > dNETWORK_MACHINE_COUNT) ) EndNum = 99; + else EndNum = iVal; + CheckStart2EndNumValid(); + IList->EditCtlNum.Show(); + IList->EditAddrNum.Show(); + } + } + break; + case VK_UP: + if(CtlIndex >0){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + }else{ + if(Start2EndNumValid){ + ClearSelected(); + CtlIndex=3; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(CtlIndex <3){ + if(CtlIndex == 1){ + if(Start2EndNumValid){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + if(CtlIndex == 2){ + //Do Mask + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 3){ + //Do UnMask + PermissionCmd = 2; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + + +int TCanNetworkMask::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + IsOnGoing =0; + return 0; +} + diff --git a/MyCode/Gui/CanNetworkMask.h b/MyCode/Gui/CanNetworkMask.h new file mode 100644 index 0000000..11d2e93 --- /dev/null +++ b/MyCode/Gui/CanNetworkMask.h @@ -0,0 +1,151 @@ +#ifndef CNANETWORKMASK_H_ +#define CNANETWORKMASK_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TCanNetworkMask{ + public: + static constexpr unsigned short hList[12] = {36,36,110,72, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2, + .Panel.Width = 796, + .Panel.Heigh = 174, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2 + 174 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + int IsOnGoing; + class TItemList *IList; + unsigned char CtlIndex; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char NwMode; + + unsigned char StartNum; + unsigned char EndNum; + + unsigned char Start2EndNumValid; + + unsigned char Count; + unsigned char CountMater; + unsigned char CountSlave; + unsigned char Done; + + unsigned char TxDataByNetworkFind[12]; + unsigned char RecData[12]; + + unsigned char Path; + unsigned char aNewGot; + unsigned char SearchNumExist; + unsigned char FoundIndex; + + unsigned char SearchingNum; + unsigned char SearchingTick; + + unsigned char RecBlock; + unsigned char IncMaster; + + unsigned char LoadingIndex; + unsigned char LoadingNum; + + char Text[68]; + public: + TCanNetworkMask(){}; + void Init(); + + void SetAndShowCaption(unsigned char aType); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + static void sDelayMs(unsigned int aMs); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + void DrawHadMask(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + int CheckStart2EndNumValid(); + + static void sRecoverSetDefault(); + + int ExtRequst(unsigned char Prm); + +}; + + + +#endif + diff --git a/MyCode/Gui/CanNetworkRegister.cpp b/MyCode/Gui/CanNetworkRegister.cpp new file mode 100644 index 0000000..7839410 --- /dev/null +++ b/MyCode/Gui/CanNetworkRegister.cpp @@ -0,0 +1,2162 @@ +#include "CanNetworkRegister.h" +#include "ProtoC2C.h" +#include "Runtime.h" +#include "server.h" + +#define dDescpOffSet 0x1000 + + +#define dAddrSdRam_TypeList (dAddrSdRam_Commom) +#define dAddrSdRam_DescpGotList (dAddrSdRam_Commom + 256) +#define dAddrSdRam_DescpContent (dAddrSdRam_Commom + 1024) +#define dAddrSdRam_ExistTable (dAddrSdRam_Commom + 0x80000) + +#define dAddrSdRam_LinkMaster (dAddrSdRam_Commom + 0x90000) + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const int xSingle = 160; +const int xSlave = 340; +const int xMaster = 474; + +const int xPst0 = 20; +const int xPst1 = 202; +const int xPst2 = 384; +const int xPst3 = 566; + +const int ListItemsX = 6; +const int ListItemsY = 6; + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +void TCanNetworkRegister::Init() +{ + IsShowing = 0; + IsOnSearching = 0; + LoadingIndex = 0; + CtlIndex = 0; + ListX =0; + ListY =0; + ListWhat = TCanNetworkRegister::TListWhat::Idle; + Done = 0; + GroupSelected = 0; + + IsPermission =0; + + this->MyNum = MainCtl.fData.Split.MyNum; + + SearchStartNum = 0; + SearchEndNum = 0; +} + +void TCanNetworkRegister::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick本机模式与注册"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "本机号:"); + TextRender_string24(Lv.Grid.Left[0] + 146, Lv.Grid.Top[0] +6, clNearWhite, "选中后按确定键保存"); + + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "组网模式:"); + TextRender_string24(xSingle+30, Lv.Grid.Top[1] + 6, clNearWhite, "单机"); + TextRender_string24(xSlave+30, Lv.Grid.Top[1] + 6, clNearWhite, "区域机"); + TextRender_string24(xMaster+30, Lv.Grid.Top[1] + 6, clNearWhite, "集中机"); + + //TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "网络注册与清除"); + //TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +40, clNearWhite, "机器号"); + + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "搜索在线机器", 14, clNearBlack); + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "清集中机列表", 14, clNearBlack); + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "清区域机列表", 14, clNearBlack); + + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "查集中机列表", 14, tColor); + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "查区域机列表", 14, tColor); + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "存集中机列表", 14, tColor); + TRoundRect::sDrawBySize(xPst3, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "存区域机列表", 14, tColor); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Local Network->Mode Setting & Register"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "CtrlID:"); + TextRender_string24(Lv.Grid.Left[0] + 146, Lv.Grid.Top[0] +6, clNearWhite, "Selected Then Press OK to Save"); + + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Network Mode"); + TextRender_string24(xSingle+30, Lv.Grid.Top[1] + 6, clNearWhite, "Stand Alone"); + TextRender_string24(xSlave+30, Lv.Grid.Top[1] + 6, clNearWhite, "Regional"); + TextRender_string24(xMaster+30, Lv.Grid.Top[1] + 6, clNearWhite, "Central"); + + //TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Network Register,Clear"); + //TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +40, clNearWhite, "Ctl ID"); + + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "Search Online", 8, clNearBlack); + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "Clear Masters", 8, clNearBlack); + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "Clear Slavers", 8, clNearBlack); + + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Master List ", 8, tColor); + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Slaver List ", 8, tColor); + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Save Masters", 8, tColor); + TRoundRect::sDrawBySize(xPst3, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Save Slavers", 8, tColor); + } +} + +void TCanNetworkRegister::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Init(Lv.Grid.Left[0] + 100, Lv.Grid.Top[0] +2, 36, 32, 0,0, 1, clNearWhite); + IList->Edit[0].SetMaxLen(2); + IList->Edit[0].TextClear(); + IList->Edit[0].SetPstTail(); + + TextRender_string24(Lv.Grid.Left[2] + 124, Lv.Grid.Top[2] +40, clNearWhite, "-"); + + IList->EditCtlNum.Init(Lv.Grid.Left[2] + 84, Lv.Grid.Top[2] +36, 36, 32, 0,0, 1, clNearWhite); + IList->EditCtlNum.SetMaxLen(2); + IList->EditCtlNum.TextClear(); + IList->EditCtlNum.SetPstTail(); + IList->EditAddrNum.Init(Lv.Grid.Left[2] + 136, Lv.Grid.Top[2] +36, 36, 32, 0,0, 1, clNearWhite); + IList->EditAddrNum.SetMaxLen(2); + IList->EditAddrNum.TextClear(); + IList->EditAddrNum.SetPstTail(); + + + //IList->EditCtlNum.Show(); + //IList->EditAddrNum.Show(); + + DrawFixText(); + + IList->Edit[0].Str.FromUInt2Dg(this->MyNum); + if( (MyNum) && (MyNum <65) ){ + MyNumValid = 1; + IList->Edit[0].SelectedColor = clBlue; + }else{ + MyNumValid = 0; + IList->Edit[0].SelectedColor = clRed; + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + + Start2EndNumValid = 1; +} + +void TCanNetworkRegister::Show(void) +{ + IsShowing = 1; + RenderBackGround(); + DrawSelf(); + DrawNetworkMode(); + Check4Selected(); +} + +void TCanNetworkRegister::DrawCtlNum() +{ + IList->Edit[0].Str.FromUInt2Dg(MainCtl.fData.Split.MyNum); + IList->Edit[0].Show(); +} + +void TCanNetworkRegister::DrawNetworkMode() +{ + if(MainCtl.fData.Split.NetworkMode == 1){ + TRoundSquare::sDrawBySize(xSingle, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(xSlave, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(xMaster, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TRoundSquare::sDrawBySize(xSingle, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(xSlave, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(xMaster, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + TRoundSquare::sDrawBySize(xSingle, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(xSlave, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(xMaster, Lv.Grid.Top[1] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TCanNetworkRegister::RedrawList() +{ + if(ListWhat != TCanNetworkRegister::TListWhat::Idle){ + DrawListTitle(); + if(ListWhat == TCanNetworkRegister::TListWhat::Searching){ + DrawSearchingList(ListDrewIndex); + }else + if(ListWhat == TCanNetworkRegister::TListWhat::QueMaster){ + DrawMasterList(); + }else + if(ListWhat == TCanNetworkRegister::TListWhat::QueSlaver){ + DrawSlaverList(); + } + DrawListSelected(); + } +} + +void TCanNetworkRegister::FullRedraw(int Prm) +{ + if(Prm == 0){ + IsShowing = 1; + RenderBackGround(); + DrawSelf(); + //DrawListStatic(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + TextRender_string24(Lv.Grid.Left[2] + 124, Lv.Grid.Top[2] +40, clNearWhite, "-"); + IList->EditCtlNum.Show(); + IList->EditAddrNum.Show(); + DrawFixText(); + IList->Edit[0].Show(); + DrawNetworkMode(); + RedrawList(); + if(IsPermission){ + PmsIntervene4Gui.ReDraw4GuiRecall(); + }else{ + Check4Selected(); + } + } +} + +//_____________________________________________________________________________________________________________________________ +void TCanNetworkRegister::PermissionCmdReturnDraw() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + Check4Selected(); + RedrawList(); +} + +void TCanNetworkRegister::PermissionCmdGO() +{ + if(PermissionCmd == 1){ + //Go Register + ClearSelected(); + ClearData(); + SearchStartNum = 1; + SearchEndNum = dNETWORK_MACHINE_COUNT; + if( (SearchStartNum) && (SearchEndNum) ){ + if( (SearchStartNum <=dNETWORK_MACHINE_COUNT) && (SearchEndNum <=dNETWORK_MACHINE_COUNT) && (SearchStartNum <= SearchEndNum) ){ + GoStartNum = SearchStartNum; + GoEndNum = SearchEndNum; + }else{ + GoStartNum = 1; + GoEndNum = dNETWORK_MACHINE_COUNT; + } + }else + if( SearchStartNum || SearchEndNum){ + GoStartNum = 1; + GoEndNum = dNETWORK_MACHINE_COUNT; + }else{ + GoStartNum = 1; + GoEndNum = dNETWORK_MACHINE_COUNT; + } + SearchingTick = 0; + IsOnSearching = 1; + ListWhat = TCanNetworkRegister::TListWhat::Searching; + DrawListTitle(); + }else + if(PermissionCmd == 2){ + //Clear Master + int DoAction =0; + MasterListCount = 0; + for(int i=0; i=dNETWORK_MACHINE_MASTER_COUNT)break; + if(CtlSelectedList[i]){ + unsigned char tType = GetRecType(i+1); + if(MainCtl.fData.Split.MyNum == (i+1)) + tType = dNetworkTypeMaster; + if(tType == dNetworkTypeMaster){ + MasterList[MasterListCount]=i+1; + MasterListCount++; + } + } + } + //Save And Send Master List Here + DoAction =1; + }else + if(ListWhat == QueMaster){ + for(int i=0; i=dNETWORK_MACHINE_MASTER_COUNT)break; + if(CtlSelectedList[i]){ + MasterList[MasterListCount]=i+1; + MasterListCount++; + } + } + DoAction =2; + //Save And Send Master List Here + } + if(DoAction){ + Record.SaveNwM2MCfg(MasterListCount, MasterList); + SendMasterList(MasterListCount, MasterList); + Record.ReadNwM2MCfg(); + Record.OperateAdd_RegCanNetwork(3, MainCtl.fData.Split.MyNum, MasterListCount); + unsigned int Failed = 0; + unsigned int tCnt =0; + if(ProtoC2C.M2MList.Cnt != MasterListCount){ + Failed=1; + } + for(int i=0; iMyNum); + sReadNetMode(); + this->MyNum = MainCtl.fData.Split.MyNum; + IList->Edit[0].Str.FromUInt2Dg(this->MyNum); + if( (MyNum) && (MyNum <65) ){ + MyNumValid = 1; + IList->Edit[0].SelectedColor = clBlue; + }else{ + MyNumValid = 0; + IList->Edit[0].SelectedColor = clRed; + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + ShowSaveMyNum(1); + } +} + +void TCanNetworkRegister::ShowSaveMyNum(int aPrm) +{ + if(LanguageEnCn==0){ + if(aPrm){ + TextRender_string24(Lv.Grid.Left[0] + 700, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, "已保存"); + JustShowingSaving =1; + ShowingSavingMyNum =1; + }else{ + TextRender_string24(Lv.Grid.Left[0] + 700, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, " "); + ShowingSavingMyNum =0; + } + }else{ + if(aPrm){ + TextRender_string24(Lv.Grid.Left[0] + 700, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, "Saved "); + JustShowingSaving =1; + ShowingSavingMyNum =1; + }else{ + TextRender_string24(Lv.Grid.Left[0] + 700, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, " "); + ShowingSavingMyNum =0; + } + } +} + +void TCanNetworkRegister::sReadNetMode() +{ + unsigned int aAddr; + int i; + unsigned char tData[4]; + //Read ExistTable + aAddr = dEepAddrMainSet; + sDelayMs(10); + eeprom_read_byte(0, aAddr, tData, 2); + + MainCtl.fData.Split.MyNum = tData[0]; + MainCtl.fData.Split.NetworkMode = tData[1]; + + if( (MainCtl.fData.Split.MyNum == 0) || (MainCtl.fData.Split.MyNum > dNETWORK_MACHINE_COUNT) ) { + MainCtl.fData.Split.MyNum =1; + MainCtl.fData.Split.NetworkMode =0; + }else{ + if(MainCtl.fData.Split.NetworkMode > 2)MainCtl.fData.Split.NetworkMode =0; + } + +} + +void TCanNetworkRegister::ClearData() +{ + int i,x; + unsigned int aAddr; + //Clear + for(i=0; i<64; i++){ + *(volatile unsigned char *)(dAddrSdRam_TypeList + i) = 0; + *(volatile unsigned char *)(dAddrSdRam_DescpGotList + i) = 0; + *(volatile unsigned char *)(dAddrSdRam_ExistTable +i) =0; + *(volatile unsigned char *)(dAddrSdRam_LinkMaster + i) = 0; + } + for(i=0; i<64; i++){ + aAddr = dAddrSdRam_DescpContent + i*32; + for(x=0; x<32; x++){ + *(volatile unsigned char *)(aAddr + x) = 0; + } + } + for(i=0; iProtoC2C.CtlMask.EndNum) || (CtlNum < ProtoC2C.CtlMask.StartNum) ) ) { + CtlList[x] = i; + x++; + }else{ + CtlSelectedList[i] =0; + DrawSearchingItem(i+1); + } + } + } + SelectedList = x; + }else{ + //Save Slaver List + x=0; + for(i=0; iProtoC2C.CtlMask.EndNum) || (CtlNum < ProtoC2C.CtlMask.StartNum) ) ) { + CtlList[x] = i; + x++; + }else{ + CtlSelectedList[i] =0; + DrawSearchingItem(i+1); + } + } + } + SelectedList = x; + } + return SelectedList; +} + +void TCanNetworkRegister::ShowSearchCompleted() +{ + int x, pNum; + unsigned int aAddr; + + IncMaster = 0; + for(x=0; xdNETWORK_MACHINE_COUNT)return; + + y = (aInx-1) / ListItemsX; + x = (aInx-1) % ListItemsX; + + xPos = Lv.Panel.Left +6 + (x * 131); + yPos = Lv.Panel.Top +2 + 31 + (y * 31); + + aAddr = dAddrSdRam_TypeList + aInx-1; + aMcType = *(volatile unsigned char *)(aAddr); + aAddr = dAddrSdRam_LinkMaster + aInx-1; + aLM = *(volatile unsigned char *)(aAddr); + TMyString::sClear(Text); + TMyString::sFrom2Dg(aInx, Text); + //TMyString::sAddOnChar(':', Text); + if(aMcType == dNetworkTypeMaster){ + Color=clNearBlack; + TMyString::sAddOnStr("F-M C", Text); + TMyString::sAddOn2Dg(aLM % 100, Text); + }else + if(aMcType == dNetworkTypeSlave){ + if(aInx == MainCtl.fData.Split.MyNum){ + Color=clRed; + TMyString::sAddOnStr("Dual ", Text); + }else{ + Color=clNearBlack; + TMyString::sAddOnStr("F-S M", Text); + + if(aLM) + TMyString::sAddOn2Dg(aLM % 100, Text); + else + TMyString::sAddOnStr("--", Text); + } + }else + if(aMcType == dNetworkTypeDual){ + Color=clRed; + TMyString::sAddOnStr("Dual ", Text); + }else{ + if(aInx == MainCtl.fData.Split.MyNum){ + Color=clNearBlack; + if(MainCtl.fData.Split.NetworkMode == 1){ + TMyString::sAddOnStr("Self C", Text); + TMyString::sAddOn2Dg(ProtoC2C.SlaveCount % 100, Text); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TMyString::sAddOnStr("Self M", Text); + TMyString::sAddOn2Dg(ProtoC2C.MasterNum % 100, Text); + }else{ + TMyString::sAddOnStr("Self ", Text); + } + }else{ + Color=clSilver; + TMyString::sAddOnStr("nil ", Text); + } + } + if(CtlSelectedList[aInx-1])bColor = clDeepGreen; + else bColor = PanelColor; + TextRender_string24(xPos, yPos, Color, bColor, Text); +} + +void TCanNetworkRegister::DrawMasterItem(int aInx) +{ + int xPos, yPos, x,y; + unsigned char aMcType, aLM; + unsigned int aAddr; + unsigned int Color, bColor; + + if(aInx==0)return; + if(aInx>dNETWORK_MACHINE_COUNT)return; + + y = (aInx-1) / ListItemsX; + x = (aInx-1) % ListItemsX; + + xPos = Lv.Panel.Left +6 + (x * 131); + yPos = Lv.Panel.Top +2 + 31 + (y * 31); + + aAddr = dAddrSdRam_TypeList + aInx-1; + aMcType = *(volatile unsigned char *)(aAddr); + TMyString::sClear(Text); + TMyString::sFrom2Dg(aInx, Text); + //TMyString::sAddOnChar(':', Text); + if(aMcType == dNetworkTypeMaster){ + Color=clNearBlack; + TMyString::sAddOnStr("F-M ", Text); + }else{ + Color=clSilver; + TMyString::sAddOnStr("nil ", Text); + } + if(CtlSelectedList[aInx-1])bColor = clDeepGreen; + else bColor = PanelColor; + TextRender_string24(xPos, yPos, Color, bColor, Text); +} + +void TCanNetworkRegister::DrawSlaverItem(int aInx) +{ + int xPos, yPos, x,y; + unsigned char aMcType, aLM; + unsigned int aAddr; + unsigned int Color, bColor; + + if(aInx==0)return; + if(aInx>dNETWORK_MACHINE_COUNT)return; + + y = (aInx-1) / ListItemsX; + x = (aInx-1) % ListItemsX; + + xPos = Lv.Panel.Left +6 + (x * 131); + yPos = Lv.Panel.Top +2 + 31 + (y * 31); + + aAddr = dAddrSdRam_TypeList + aInx-1; + aMcType = *(volatile unsigned char *)(aAddr); + TMyString::sClear(Text); + TMyString::sFrom2Dg(aInx, Text); + //TMyString::sAddOnChar(':', Text); + if(aMcType == dNetworkTypeMaster){ + Color=clBlack; + TMyString::sAddOnStr("FMaster", Text); + }else + if(aMcType == dNetworkTypeSlave){ + Color=clNavy; + TMyString::sAddOnStr("F-S ", Text); + }else{ + Color=clSilver; + TMyString::sAddOnStr("nil ", Text); + } + if(CtlSelectedList[aInx-1])bColor = clDeepGreen; + else bColor = PanelColor; + TextRender_string24(xPos, yPos, Color, bColor, Text); +} + +void TCanNetworkRegister::DrawListTitle() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + + if(LanguageEnCn==0){ + TextRender_string24(Lv.Panel.Left +6, Lv.Panel.Top +2, clNearWhite, PanelColor, "F:火灾报警控制器 M:集中机 S:区域机"); + }else{ + TextRender_string24(Lv.Panel.Left +6, Lv.Panel.Top +2, clNearWhite, PanelColor, "F:Fire Alram Ctrl M:Master S:Slaver"); + } +} + +void TCanNetworkRegister::DrawSearchingList(int MaxInx) +{ + unsigned int i; + for(i=1; i<=MaxInx; i++){ + DrawSearchingItem(i); + } +} + +void TCanNetworkRegister::DrawMasterList(int MaxInx) +{ + unsigned int i; + for(i=1; i<=MaxInx; i++){ + DrawMasterItem(i); + } +} + +void TCanNetworkRegister::DrawSlaverList(int MaxInx) +{ + unsigned int i; + for(i=1; i<=MaxInx; i++){ + DrawSlaverItem(i); + } +} + +void TCanNetworkRegister::ClearSelected() +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->Edit[0].Selected =0; + IList->Edit[0].Show(); + break; + case 1: + TRoundSquare::sSelected(xSingle, Lv.Grid.Top[1]+8, dWWidth, dWHeigh, 4, ItemColor); + break; + case 2: + TRoundSquare::sSelected(xSlave, Lv.Grid.Top[1]+8, dWWidth, dWHeigh, 4, ItemColor); + break; + case 3: + TRoundSquare::sSelected(xMaster, Lv.Grid.Top[1]+8, dWWidth, dWHeigh, 4, ItemColor); + break; + } + if(LanguageEnCn==0){ + switch(CtlIndex){ + case 4: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "搜索在线机器", 14, clNearBlack); + break; + case 5: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "清集中机列表", 14, clNearBlack); + break; + case 6: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "清区域机列表", 14, clNearBlack); + break; + case 7: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "查集中机列表", 14, clNearBlack); + break; + case 8: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "查区域机列表", 14, clNearBlack); + break; + case 9: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "存集中机列表", 14, clNearBlack); + break; + case 10: + TRoundRect::sDrawBySize(xPst3, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, "存区域机列表", 14, clNearBlack); + break; + } + }else{ + switch(CtlIndex){ + case 4: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "Search Online", 8, clNearBlack); + break; + case 5: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "Clear Masters", 8, clNearBlack); + break; + case 6: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 2, 172, 30, 7, clNearWhite, "Clear Salvers", 8, clNearBlack); + break; + case 7: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Master List ", 8, clNearBlack); + break; + case 8: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Slaver List ", 8, clNearBlack); + break; + case 9: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Save Master ", 8, clNearBlack); + break; + case 10: + TRoundRect::sDrawBySize(xPst3, Lv.Grid.Top[2] + 38, 172, 30, 7, clNearWhite, " Save Master ", 8, clNearBlack); + break; + } + } +} + +void TCanNetworkRegister::Check4Selected() +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->Edit[0].Selected =1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + break; + case 1: + TRoundSquare::sSelected(xSingle, Lv.Grid.Top[1]+8, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 2: + TRoundSquare::sSelected(xSlave, Lv.Grid.Top[1]+8, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 3: + TRoundSquare::sSelected(xMaster, Lv.Grid.Top[1]+8, dWWidth, dWHeigh, 4, clNearWhite); + break; + } + if(LanguageEnCn==0){ + switch(CtlIndex){ + case 4: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 2, 172, 30, 7, clBlue, "搜索在线机器", 14, clNearWhite); + break; + case 5: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 2, 172, 30, 7, clBlue, "清集中机列表", 14, clNearWhite); + break; + case 6: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 2, 172, 30, 7, clBlue, "清区域机列表", 14, clNearWhite); + break; + case 7: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, "查集中机列表", 14, clNearWhite); + break; + case 8: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, "查区域机列表", 14, clNearWhite); + break; + case 9: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, "存集中机列表", 14, clNearWhite); + break; + case 10: + TRoundRect::sDrawBySize(xPst3, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, "存区域机列表", 14, clNearWhite); + break; + } + }else{ + switch(CtlIndex){ + case 4: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 2, 172, 30, 7, clBlue, "Search Online", 8, clNearWhite); + break; + case 5: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 2, 172, 30, 7, clBlue, "Clear Masters", 8, clNearWhite); + break; + case 6: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 2, 172, 30, 7, clBlue, "Clear Salvers", 8, clNearWhite); + break; + case 7: + TRoundRect::sDrawBySize(xPst0, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, " Masters List", 8, clNearWhite); + break; + case 8: + TRoundRect::sDrawBySize(xPst1, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, " Slavers List", 8, clNearWhite); + break; + case 9: + TRoundRect::sDrawBySize(xPst2, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, " Save Masters", 8, clNearWhite); + break; + case 10: + TRoundRect::sDrawBySize(xPst3, Lv.Grid.Top[2] + 38, 172, 30, 7, clBlue, " Save Salvers", 8, clNearWhite); + break; + } + } +} + +void TCanNetworkRegister::SendNwList() +{ + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Priority =1; + + //First Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 6; + ProtoC2C.TxMsg.Data.Data[0] =0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.CtlMask.StartNum; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.CtlMask.EndNum; + + ProtoC2C.oBufInsert(); + + //2th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =1; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[0]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[1]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[2]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[3]; + + ProtoC2C.oBufInsert(); + + //3th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =2; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[4]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[5]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[6]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[7]; + + ProtoC2C.oBufInsert(); + + //4th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =3; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[8]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[9]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[10]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[11]; + + ProtoC2C.oBufInsert(); + + //5th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =4; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[12]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[13]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[14]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[15]; + + ProtoC2C.oBufInsert(); + + //6th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =5; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[16]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[17]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[18]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[19]; + + ProtoC2C.oBufInsert(); + + //7th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =6; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[20]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[21]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[22]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[23]; + + ProtoC2C.oBufInsert(); + + //8th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =7; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[24]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[25]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[26]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[27]; + + ProtoC2C.oBufInsert(); + + //9th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =8; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = CtlList[28]; + ProtoC2C.TxMsg.Data.Data[5] = CtlList[29]; + ProtoC2C.TxMsg.Data.Data[6] = CtlList[30]; + ProtoC2C.TxMsg.Data.Data[7] = CtlList[31]; + + ProtoC2C.oBufInsert(); + + //10th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =9; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = Count; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.CtlMask.StartNum; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.CtlMask.EndNum; + ProtoC2C.TxMsg.Data.Data[6] = 0; + ProtoC2C.TxMsg.Data.Data[7] = 0; + + ProtoC2C.oBufInsert(); +} + +int TCanNetworkRegister::CheckStart2EndNumValid() +{ + if( (SearchStartNum) && (SearchEndNum) ){ + if( (SearchStartNum <= dNETWORK_MACHINE_COUNT) && (SearchEndNum <= dNETWORK_MACHINE_COUNT) && (SearchStartNum <= SearchEndNum) ) + Start2EndNumValid = 1; + else + Start2EndNumValid = 0; + }else + if( SearchStartNum || SearchEndNum){ + Start2EndNumValid = 0; + }else{ + Start2EndNumValid = 1; + } + + if(Start2EndNumValid){ + IList->EditCtlNum.SelectedColor = clBlue; + IList->EditAddrNum.SelectedColor = clBlue; + IList->EditCtlNum.Color = clNearWhite; + IList->EditAddrNum.Color = clNearWhite; + }else{ + IList->EditCtlNum.SelectedColor = clRed; + IList->EditAddrNum.SelectedColor = clRed; + IList->EditCtlNum.Color = clRed; + IList->EditAddrNum.Color = clRed; + } + + return Start2EndNumValid; +} + +TGuiMsgReturn TCanNetworkRegister::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + unsigned int aAddr, HadPrc; + TDMix aFullPath; + + JustShowingSaving =0; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else + if(IsOnSearching){ + switch(aKey){ + case VK_RETURN: + IsShowing = 0; + IsOnSearching = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(CtlIndex == 0){ + IList->Edit[0].KeyIn(aKey); + int iVal; + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal <1) || (iVal > 64) ){ + MyNumValid = 0; + IList->Edit[0].SelectedColor = clRed; + }else{ + MyNumValid = 1; + IList->Edit[0].SelectedColor = clBlue; + if(iVal != MyNum){ + MyNum = iVal; + } + } + IList->Edit[0].Show(); + }else{ + if(aKey == VK_LEFT){ + if((CtlIndex==2)||(CtlIndex==3) || (CtlIndex==5)||(CtlIndex==6) || (CtlIndex==8) || (CtlIndex==9) || (CtlIndex==10) ){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + }else + if(CtlIndex == 11){ + if(ListX>0){ + DrawListDeSelected(); + ListX--; + DrawListSelected(); + } + } + }else + if(aKey == VK_RIGHT){ + if(MainCtl.fData.Split.NetworkMode == 1){ + if((CtlIndex==1)||(CtlIndex==2) || (CtlIndex==4)||(CtlIndex==5) || (CtlIndex==7) || (CtlIndex==8) || (CtlIndex==9) ){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + }else + if(CtlIndex == 11){ + if(ListY0){ + if(CtlIndex<4){ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + }else + if(CtlIndex<7){ + ClearSelected(); + CtlIndex-=3; + Check4Selected(); + }else + if(CtlIndex<10){ + ClearSelected(); + CtlIndex-=3; + Check4Selected(); + }else + if(CtlIndex==10){ + ClearSelected(); + CtlIndex=6; + Check4Selected(); + }else + if(CtlIndex==11){ + if(ListWhat != TCanNetworkRegister::TListWhat::Idle){ + if(ListY==0){ + DrawListDeSelected(); + if(ListX<2){ + CtlIndex=7; + }else{ + CtlIndex=8; + } + Check4Selected(); + }else{ + DrawListDeSelected(); + ListY--; + DrawListSelected(); + } + }else{ + DrawListDeSelected(); + CtlIndex =8; + Check4Selected(); + } + }else{ + DrawListDeSelected(); + ClearSelected(); + CtlIndex =0; + Check4Selected(); + } + }else{ + if(ListWhat == TCanNetworkRegister::TListWhat::Idle){ + ClearSelected(); + if(MainCtl.fData.Split.NetworkMode == 1){ + CtlIndex=7; + Check4Selected(); + }else{ + CtlIndex=4; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex =11; + DrawListDeSelected(); + ListY = ListItemsY-1; + ListX =0; + DrawListSelected(); + } + } + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + break; + case VK_DOWN: + if(MyNumValid){ + if(CtlIndex){ + if(MainCtl.fData.Split.NetworkMode == 1){ + if(CtlIndex<7){ + ClearSelected(); + CtlIndex+=3; + Check4Selected(); + }else + if(CtlIndex<11){ + if(ListWhat != this->TListWhat::Idle){ + ClearSelected(); + CtlIndex=11; + ListY=0; + ListX=0; + DrawListSelected(); + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + }else + if(CtlIndex=11){ + if(ListWhat != this->TListWhat::Idle){ + if((ListYTListWhat::Idle){ + ClearSelected(); + CtlIndex=11; + ListY=0; + ListX=0; + DrawListSelected(); + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + }else + if(CtlIndex==11){ + if(ListWhat != this->TListWhat::Idle){ + if((ListY 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + } + }else + if(CtlIndex == 1){ + PermissionCmd = 11; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 2){ + PermissionCmd = 12; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 3){ + PermissionCmd = 13; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + } + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + PermissionCmd = 21; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 1){ + PermissionCmd = 11; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 2){ + PermissionCmd = 12; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 3){ + PermissionCmd = 13; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 4){ + //Searching + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 5){ + //Clear Master List + PermissionCmd = 2; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 6){ + //Clear Slaver List + PermissionCmd = 3; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 7){ + //Load Master List + ListWhat = this->TListWhat::QueMaster; + for(int i=0; i=ProtoC2C.M2MList.Cnt)break; + if(ProtoC2C.M2MList.Items[i]){ + if(ProtoC2C.M2MList.Items[i] <= dNETWORK_MACHINE_COUNT){ + *(volatile unsigned char *)(dAddrSdRam_TypeList + (ProtoC2C.M2MList.Items[i]-1)) = dNetworkTypeMaster; + } + } + } + DrawListTitle(); + DrawMasterList(); + SetGroupSelected(dNetworkTypeMaster); + }else + if(CtlIndex == 8){ + //Load Slaver List + ListWhat = this->TListWhat::QueSlaver; + for(int i=0; i=ProtoC2C.SlaveCount)break; + if(ProtoC2C.SlaveList[i]){ + if(ProtoC2C.SlaveList[i] <= dNETWORK_MACHINE_COUNT){ + *(volatile unsigned char *)(dAddrSdRam_TypeList + (ProtoC2C.SlaveList[i]-1)) = dNetworkTypeSlave; + } + } + } + if( (ProtoC2C.MasterNum) and (ProtoC2C.MasterNum <=dNETWORK_MACHINE_COUNT) ){ + *(volatile unsigned char *)(dAddrSdRam_TypeList + (ProtoC2C.MasterNum-1)) = dNetworkTypeMaster; + } + DrawListTitle(); + DrawSlaverList(); + SetGroupSelected(dNetworkTypeSlave); + }else + if(CtlIndex == 9){ + //Save Master List + PermissionCmd = 4; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 10){ + //Save Slaver List + PermissionCmd = 5; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + }else + if(CtlIndex == 11){ + if(ListWhat == Searching){ + int tInx = ListY*ListItemsX+ListX; + if(tInxProtoC2C.CtlMask.EndNum) || (pNumProtoC2C.CtlMask.EndNum) ){ + const unsigned char PrvType = *(volatile unsigned char *)(dAddrSdRam_TypeList + aP0); + if( (PrvType) || (Path == MainCtl.fData.Split.MyNum) ){ + //Dual + *(volatile unsigned char *)(dAddrSdRam_TypeList + aP0) = dNetworkTypeDual; + *(volatile unsigned char *)(dAddrSdRam_LinkMaster + aP0) = MasterOrSlaverCnt; + }else{ + *(volatile unsigned char *)(dAddrSdRam_TypeList + aP0) = ada; + *(volatile unsigned char *)(dAddrSdRam_LinkMaster + aP0) = MasterOrSlaverCnt; + } + } + } + } + } + break; + case CmdC2C_RpyNameLen: + + break; + case CmdC2C_RpyNameContent: + if(ada == 0xFF){ + aP0 = Path -1; + if(aP0 <64){ + if( (Path ProtoC2C.CtlMask.EndNum) ){ + aNewGot = 1; + aAddr = dAddrSdRam_DescpGotList + aP0; + *(volatile unsigned char *)(aAddr)= 1; + } + } + }else{ + if(ada < 8){ + x = ada * 4; + aLen = data[4]; + aP0 = Path -1; + if( (Path ProtoC2C.CtlMask.EndNum) ){ + if( (aLen < 5) && (aP0 < 64) ){ + aAddr = dAddrSdRam_DescpContent + aP0 * 32; + for(i=0; idNETWORK_MACHINE_COUNT) )return dNetworkTypeNone; + aP0 = aNum -1; + aAddr = dAddrSdRam_TypeList + aP0; + aType = *(volatile unsigned char *)(aAddr); + return aType; +} + +unsigned char TCanNetworkRegister::CheckRecTypeAva(unsigned char aNum) +{ + unsigned char aType; + unsigned int aP0, aAddr; + aP0 = aNum -1; + aAddr = dAddrSdRam_TypeList + aP0; + aType = *(volatile unsigned char *)(aAddr); + if( (aType == dNetworkTypeMaster) || (aType == dNetworkTypeSlave) ){ + return 1; + }else{ + return 0; + } +} + +unsigned char TCanNetworkRegister::CheckDescpAva(unsigned char aNum) +{ + unsigned char aOk; + unsigned int aP0, aAddr; + aP0 = aNum -1; + aAddr = dAddrSdRam_DescpGotList + aP0; + aOk = *(volatile unsigned char *)(aAddr + aP0); + return aOk; +} + +unsigned char TCanNetworkRegister::GetCtlCount() +{ + unsigned char aType; + unsigned int i, aAddr; + + Count =0; + CountMater =0; + CountSlave =0; + aAddr = dAddrSdRam_TypeList; + for(i=0; i2)GroupSelected=0; + + if(aCtlType ==dNetworkTypeMaster) GroupSelected=1; + else if(aCtlType ==dNetworkTypeSlave) GroupSelected =2; + else GroupSelected = 0; + + DoListSelectAll(aCtlType); + if(ListWhat == this->Searching){ + DrawSearchingList(); + }else + if(ListWhat == this->QueMaster){ + DrawMasterList(); + }else + if(ListWhat == this->QueSlaver){ + DrawSlaverList(); + } +} + +void TCanNetworkRegister::DoGroupSelect() +{ + unsigned char tType; + if(ListWhat == this->Idle)return; + + if(ListWhat == this->Searching){ + switch(GroupSelected){ + case 0:GroupSelected=1;tType =dNetworkTypeMaster; break; + case 1:GroupSelected=2;tType =dNetworkTypeSlave; break; + case 2:GroupSelected=0;tType =0; break; + default:GroupSelected=0;tType =0; break; + } + DoListSelectAll(tType); + DrawSearchingList(); + }else + if(ListWhat == this->QueMaster){ + switch(GroupSelected){ + case 0:GroupSelected=1;tType =dNetworkTypeMaster; break; + case 1:GroupSelected=0;tType =0; break; + default:GroupSelected=0;tType =0; break; + } + DoListSelectAll(tType); + DrawMasterList(); + }else + if(ListWhat == this->QueSlaver){ + switch(GroupSelected){ + case 0:GroupSelected=2;tType =dNetworkTypeSlave; break; + case 2:GroupSelected=0;tType =0; break; + default:GroupSelected=0;tType =0; break; + } + DoListSelectAll(tType); + DrawSlaverList(); + } + DrawListSelected(); +} + +void TCanNetworkRegister::Task1000Ms() +{ + unsigned char x,y; + volatile unsigned int aAddr; + if(IsShowing){ + if(IsOnSearching){ + PreventPermissionDown(); + PreventEventShow(); + if(Done){ + IsOnSearching =0; + ClearSelected(); + CtlIndex=11; + ListY=0; + ListX=0; + SetGroupSelected(dNetworkTypeSlave); + DrawListSelected(); + }else{ + if(SearchingTick == 0)SearchingTick = GoStartNum; + if(SearchingTick >(GoEndNum +2) ){ + SearchingTick = GoEndNum +2 +1; + Count = GetCtlCount(); + //LoadData2Last(); + DrawListTitle(); + DrawSearchingList(); + //ShowSearchCompleted(); + Done = 1; + }else + if( (SearchingTick) && (SearchingTick <= GoEndNum) ){ + SearchingNum = SearchingTick; + SendAskType(SearchingNum); + if(SearchingNum>1){ + DrawSearchingItem(SearchingNum-1); + ListDrewIndex = SearchingNum-1; + } + if(LanguageEnCn==0)TextRender_string24 (Lv.Panel.Left +600, Lv.Panel.Top +2, clNearBlack, PanelColor, "正在搜索:"); + else TextRender_string24 (Lv.Panel.Left +600, Lv.Panel.Top +2, clNearBlack, PanelColor, "Scanning: "); + TextDigitRender2_24 (Lv.Panel.Left +708, Lv.Panel.Top +2, clNearBlack, PanelColor, SearchingNum % 100); + + Count = GetCtlCount(); + //LoadData2Last(); + }else{ + Count = GetCtlCount(); + //LoadData2Last(); + DrawSearchingList(); + if(LanguageEnCn==0) TextRender_string24(Lv.Panel.Left +600, Lv.Panel.Top +2, clNearBlack, PanelColor, "搜索完成 "); + else TextRender_string24(Lv.Panel.Left +600, Lv.Panel.Top +2, clNearBlack, PanelColor, "Scan Completed "); + } + + SearchingTick++; + } + } + } +} + +int TCanNetworkRegister::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + IsOnSearching =0; + return 0; +} + diff --git a/MyCode/Gui/CanNetworkRegister.h b/MyCode/Gui/CanNetworkRegister.h new file mode 100644 index 0000000..e92a839 --- /dev/null +++ b/MyCode/Gui/CanNetworkRegister.h @@ -0,0 +1,230 @@ +#ifndef CNANETWORKREGISTER_H_ +#define CNANETWORKREGISTER_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TCanNetworkRegister{ + public: + static constexpr unsigned short hList[12] = {36,36,72,72, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 3, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2, + .Panel.Width = 796, + .Panel.Heigh = 216, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2 + 216 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + typedef enum{ + Idle =0, + Searching =1, + QueMaster =2, + QueSlaver =3, + }TListWhat; + public: + int IsShowing; + int IsOnSearching; + class TItemList *IList; + unsigned char CtlIndex; + unsigned char ListX; + unsigned char ListY; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char MyNum; + unsigned char SearchStartNum; + unsigned char SearchEndNum; + unsigned char GoStartNum; + unsigned char GoEndNum; + unsigned char GoCount; + + unsigned char MyNumValid; + unsigned char Start2EndNumValid; + + unsigned char Count; + unsigned char CountMater; + unsigned char CountSlave; + unsigned char Done; + + unsigned char TxDataByNetworkFind[12]; + unsigned char RecData[12]; + + unsigned char Path; + unsigned char aNewGot; + unsigned char SearchNumExist; + unsigned char FoundIndex; + + unsigned char SearchingNum; + unsigned char SearchingTick; + + unsigned char RecBlock; + unsigned char IncMaster; + + unsigned char LoadingIndex; + unsigned char LoadingNum; + + unsigned char CtlList[dNETWORK_MACHINE_COUNT]; + unsigned char CtlSelectedList[dNETWORK_MACHINE_COUNT]; + unsigned char MasterList[dNETWORK_MACHINE_MASTER_COUNT]; + unsigned char MasterListRec[dNETWORK_MACHINE_MASTER_COUNT]; + + unsigned char MasterListCount; + unsigned char MasterListCountRec; + unsigned char MasterListRecPiece; + + + char Text[68]; + + char ShowingSavingMyNum; + char JustShowingSaving; + char SelectedList; + unsigned char ListDrewIndex; + + unsigned char GroupSelected; + + TListWhat ListWhat; + public: + TCanNetworkRegister(){}; + void Init(); + + void SetAndShowCaption(unsigned char aType); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawCtlNum(); + void DrawNetworkMode(); + void ClearOutText(); + static void sDelayMs(unsigned int aMs); + + void Show(void); + void ShowCaption(); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawIdfText(); + void DrawFixText(); + + void DrawListDeSelected(); + void DrawListSelected(); + void RedrawList(); + + void DrawListTitle(); + void DrawSearchingItem(int aInx); + void DrawMasterItem(int aInx); + void DrawSlaverItem(int aInx); + void DrawSearchingList(int MaxInx=(dNETWORK_MACHINE_COUNT)); + void DrawMasterList(int MaxInx=(dNETWORK_MACHINE_COUNT)); + void DrawSlaverList(int MaxInx=(dNETWORK_MACHINE_COUNT)); + void ShowSearchCompleted(); + void ShowSaveMyNum(int aPrm); + + void DoListSelectAll(unsigned char aCtlType); + void DoGroupSelect(); + void SetGroupSelected(unsigned char aCtlType); + + void ClearData(); + void LoadData2Last(); + + void SendAskType(unsigned char aNum); + void SendAskDescp(unsigned char aNum); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + unsigned char GetRecType(unsigned char aNum); + unsigned char CheckRecTypeAva(unsigned char aNum); + unsigned char CheckDescpAva(unsigned char aNum); + unsigned char GetCtlCount(); + + void Task1000Ms(); + + void SendfNetMsg(unsigned char aSubCmd, unsigned char *data, int Len); + void PushfNetMsg(unsigned char aSubCmd, unsigned char *data, int Len); + + void PortExistGet(unsigned char aNum, unsigned char aP0, unsigned char aExist); + + int CheckData(int SaveWhat); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void SaveMasterList(unsigned char aCnt, unsigned char *aList); + void SaveSlaverList(); + + void SendMasterList(unsigned char aCnt, unsigned char *aList); + void SendClearMasterList(unsigned char aCnt, unsigned char *aList); + void SendNwList(); + + + static void sReadNetMode(); + int CheckStart2EndNumValid(); + + static void sRecoverSetDefault(); + + int ExtRequst(unsigned char Prm); + +}; + + + +#endif + diff --git a/MyCode/Gui/Chart.cpp b/MyCode/Gui/Chart.cpp new file mode 100644 index 0000000..fd02f35 --- /dev/null +++ b/MyCode/Gui/Chart.cpp @@ -0,0 +1,110 @@ +#include "Chart.h" + +void TChart::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + unsigned short Left,Right,Top,Bottom; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + Content.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + RectDiagram.SetBySize(Content.Left + aW /3, aY+OwnerY +1, aW/3, 50); + + Color = aColor; + + for(Left=0; Left 1)return; + for(i=0; i 1)return; + for(i=0; i 1)return; + vName[Inx].x = aX + Content.Left; + vName[Inx].y = aY + Content.Top; +} + + + diff --git a/MyCode/Gui/Chart.h b/MyCode/Gui/Chart.h new file mode 100644 index 0000000..f0a5e92 --- /dev/null +++ b/MyCode/Gui/Chart.h @@ -0,0 +1,89 @@ +#ifndef CHART_H_ +#define CHART_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" + +#define dfValueCount 2 +#define dfValueLength 1024 +#define dfNameLength 32 + +typedef enum{ + ltNone = 0, + ltPoint = 1, + LtSOlid = 2 +}TLineType; + +class TChart{ + public: + TRect Bound; + TRect Content; + TRect RectDiagram; + u32 Color; + + short Value[dfValueCount][dfValueLength]; + + struct{ + short x; + short y; + char Text[dfNameLength]; + char tUnit[dfNameLength]; + }vName[dfValueCount]; + + struct{ + short StartX; + short StartY; + short EndX; + short EndY; + unsigned int Color; + short GridCount; + + unsigned char IsHoriz; + unsigned char IsShowGrid; + unsigned char IsShowPointedTip; + TLineType GridLineType; + }BaseAxis; + + struct{ + short StartX; + short StartY; + short EndX; + short EndY; + unsigned int Color; + short GridCount; + + unsigned char IsHoriz; + unsigned char IsShowGrid; + unsigned char IsShowPointedTip; + TLineType GridLineType; + }Axis[dfValueCount]; + + public: + TChart(){}; + TChart(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aColor, aBevelOuter); + } + void Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter); + void DrawSelf(void); + void Show(void); + + void DrawBaseAxis(); + void DrawAxis(short aInx); + void DrawAllAxis(); + + void SetName(short Inx, char *P); + void SetName(short Inx, const char *P); + void SetNamePosition(short Inx, short aX, short aY); + +}; + + + + +#endif + diff --git a/MyCode/Gui/CheckNormal.cpp b/MyCode/Gui/CheckNormal.cpp new file mode 100644 index 0000000..b3dcd74 --- /dev/null +++ b/MyCode/Gui/CheckNormal.cpp @@ -0,0 +1,749 @@ +#include "CheckNormal.h" + +#define clOdd clMoneyGreen +#define clEven clWhiteBlue + +static const short GridX [5] = {10, 160, 300, 500, 700}; +static const short GridX2[5] = {156, 296, 496, 696, 786}; +static const short GridY [10] = {86, 126, 496, 696, 786}; +static const short GridY2[10] = {156, 296, 496, 696, 786}; + +void TCheckNormal::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + + Lv.ColHeight = 27; + Lv.RowCount = 10; + Lv.FixColTop = Content.Top + 32; + Lv.FixColBottom = Lv.FixColTop + Lv.ColHeight; + Lv.ColTop[0] = Lv.FixColBottom + 1; + Lv.ColBottom[0] = Lv.ColTop[0] + Lv.ColHeight -1; + + for(i=1; i<12; i++){ + Lv.ColTop[i] = Lv.ColTop[i -1] + Lv.ColHeight; + Lv.ColBottom[i] = Lv.ColBottom[i-1] + Lv.ColHeight; + } + + SlaveCheckInx = 0; + AskInx =0; + for(i=0;i<20;i++)HasDrawData[i] = 0; + + AutoReturnTick = 0; + + CheckDoneClear(); +} + +void TCheckNormal::RenderContent(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TCheckNormal::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); + + SetListColWidth(200,135,135,135,135,2); + RectFillRender(Lv.ColLeft[0], Lv.FixColTop, Lv.ColLeft[5], Lv.FixColBottom, clDeepBlue); + for(x=0; x<(11); x++){ + if(x & 1){ + RectFillRender(Lv.ColLeft[0], Lv.ColTop[x], Lv.ColLeft[5], Lv.ColBottom[x], clEven); + }else{ + RectFillRender(Lv.ColLeft[0], Lv.ColTop[x], Lv.ColLeft[5], Lv.ColBottom[x], clOdd); + } + } + + h = clNearBlack; + for(x=0; x<6; x++){ + VertLineRender (Lv.ColLeft[x], Lv.FixColTop, Lv.ColBottom[10] - Lv.FixColTop +1, h); + } + + HorizLineRender (Lv.ColLeft[0], Lv.FixColTop, Lv.ColLeft[5] - Lv.ColLeft[0] +1, h); + for(y=0; y<12; y++){ + HorizLineRender (Lv.ColLeft[0], Lv.ColTop[y], Lv.ColLeft[5] - Lv.ColLeft[0] +1, h); + } +} + +void TCheckNormal::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5) +{ + unsigned int i; + Lv.ColWidth[0] = w0; + Lv.ColWidth[1] = w1; + Lv.ColWidth[2] = w2; + Lv.ColWidth[3] = w3; + Lv.ColWidth[4] = w4; + Lv.ColWidth[5] = w5; + + Lv.ColLeft[0] = Content.Left +10; + Lv.ColRight[0] = Lv.ColLeft[0] + w0; + for(i=1; i<6; i++){ + Lv.ColLeft[i] = Lv.ColRight[i-1] + 1; + Lv.ColRight[i] = Lv.ColLeft[i] + Lv.ColWidth[i]; + } +} + +void TCheckNormal::DrawCaption(void) +{ + if(LanguageEnCn==0)TMyString::sFromStr("快捷检查", Caption.Text); + else TMyString::sFromStr("CheckOut", Caption.Text); + Caption.Show(); +} + +void TCheckNormal::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + IsShowing = 1; + + DrawGridAndText(); + Record.OperateAdd_UserCheck(MainCtl.fData.Split.MyNum, 1); + + SlaveCheckInx = 0; + LoadCtlNum = 0; + AskInx = 0; + ShowCtlNum(); + + CheckDoneClear(); +} + +void TCheckNormal::ShowCtlNum() +{ + if(MainCtl.fData.Split.NetworkMode == 1){ + if(LoadCtlNum == 0){ + if(LanguageEnCn==0){ + TextRender_string24(300, 73, clNearBlack, Color, "本集中机 " ); + TextDigitRender2Right24(440, 73, clNearBlack, Color, MainCtl.fData.Split.MyNum); + }else{ + TextRender_string24(460, 73, clNearBlack, Color, "This Centre " ); + TextDigitRender2Right24(652, 73, clNearBlack, Color, MainCtl.fData.Split.MyNum); + } + }else + if(LoadCtlNum <= dNETWORK_MACHINE_COUNT){ + if(LanguageEnCn==0){ + TextRender_string24(300, 73, clNearBlack, Color, "区域机 " ); + TextDigitRender2Right24(440, 73, clNearBlack, Color, LoadCtlNum); + }else{ + TextRender_string24(460, 73, clNearBlack, Color, "Remote Regional " ); + TextDigitRender2Right24(652, 73, clNearBlack, Color, LoadCtlNum); + } + }else{ + if(LanguageEnCn==0){ + TextRender_string24(300, 73, clNearBlack, Color, "网络总计 " ); + TextRender_string24(440, 73, clNearBlack, Color, " " ); + }else{ + TextRender_string24(460, 73, clNearBlack, Color, "Network " ); + TextRender_string24(652, 73, clNearBlack, Color, " " ); + } + } + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + if(LanguageEnCn==0){ + TextRender_string24(300, 73, clNearBlack, Color, "本区域机 " ); + TextDigitRender2Right24(440, 73, clNearBlack, Color, MainCtl.fData.Split.MyNum); + }else{ + TextRender_string24(400, 73, clNearBlack, Color, "This Regional " ); + TextDigitRender2Right24(580, 73, clNearBlack, Color, MainCtl.fData.Split.MyNum); + } + }else{ + if(LanguageEnCn==0){ + TextRender_string24(300, 73, clNearBlack, Color, "本机 " ); + TextDigitRender2Right24(440, 73, clNearBlack, Color, MainCtl.fData.Split.MyNum); + }else{ + TextRender_string24(400, 73, clNearBlack, Color, "Stand Alone " ); + TextDigitRender2Right24(560, 73, clNearBlack, Color, MainCtl.fData.Split.MyNum); + } + } +} + + +void TCheckNormal::Hide() +{ + if(IsShowing){ + Record.OperateAdd_UserCheck(MainCtl.fData.Split.MyNum, 0); + IsShowing = 0; + } +} + +void TCheckNormal::ReDraw(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + IsShowing = 1; + DrawGridAndText(); + ShowCtlNum(); + ShowData(1); +} + +void TCheckNormal::ShowData(unsigned int Force) +{ + if(Force){ + if(LoadCtlNum == 0){ + LoadAndDrawData(); + HasDrawData[0] = 1; + }else + if(LoadCtlNum <=dNETWORK_MACHINE_COUNT){ + if(ProtoC2C.IsCheckNormalDataSlaveDone[LoadCtlNum-1]){ + LoadAndDrawDataSlave(LoadCtlNum); + HasDrawData[LoadCtlNum] = 1; + }else{ + HasDrawData[LoadCtlNum] = 0; + } + }else{ + if(IsSlaveDone){ + LoadAndDrawDataAll(); + HasDrawData[dNETWORK_MACHINE_COUNT+1] = 1; + }else{ + HasDrawData[dNETWORK_MACHINE_COUNT+1] = 0; + } + } + }else{ + if(LoadCtlNum == 0){ + if(HasDrawData[0] == 0){ + LoadAndDrawData(); + HasDrawData[0] = 1; + } + }else + if(LoadCtlNum <= dNETWORK_MACHINE_COUNT){ + if(HasDrawData[LoadCtlNum] == 0){ + if(ProtoC2C.IsCheckNormalDataSlaveDone[LoadCtlNum-1]){ + LoadAndDrawDataSlave(LoadCtlNum); + HasDrawData[LoadCtlNum] = 1; + } + } + }else{ + if(HasDrawData[dNETWORK_MACHINE_COUNT+1] == 0){ + if(IsSlaveDone){ + LoadAndDrawDataAll(); + HasDrawData[dNETWORK_MACHINE_COUNT+1] = 1; + } + } + } + } +} + +TGuiMsgReturn TCheckNormal::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + AutoReturnTick = 0; + if(aKey == VK_LEFT){ + if(MainCtl.fData.Split.NetworkMode == 1){ + if(ProtoC2C.SlaveCount >0){ + if(SlaveCheckInx > 0){ + SlaveCheckInx--; + }else{ + SlaveCheckInx = ProtoC2C.SlaveCount +1; + } + + if(SlaveCheckInx == 0){ + LoadCtlNum = 0; + }else + if(SlaveCheckInx < (ProtoC2C.SlaveCount+1)){ + LoadCtlNum = ProtoC2C.SlaveList[SlaveCheckInx-1]; + }else{ + CheckNwAllCount(); + LoadCtlNum = 100; + } + ClearAndDrawData(); + ShowCtlNum(); + ShowData(1); + } + } + }else + if(aKey == VK_RIGHT){ + if(MainCtl.fData.Split.NetworkMode == 1){ + if(ProtoC2C.SlaveCount >0){ + if(SlaveCheckInx < (ProtoC2C.SlaveCount +1)){ + SlaveCheckInx++; + }else{ + SlaveCheckInx =0; + } + + if(SlaveCheckInx == 0){ + LoadCtlNum = 0; + }else + if(SlaveCheckInx < (ProtoC2C.SlaveCount+1)){ + LoadCtlNum = ProtoC2C.SlaveList[SlaveCheckInx-1]; + }else{ + CheckNwAllCount(); + LoadCtlNum = 100; + } + ClearAndDrawData(); + ShowCtlNum(); + ShowData(1); + } + } + }else + if(aKey == VK_EXECUTE){ + + }else + if(aKey == VK_F2){ + + + }else + if(aKey == VK_RETURN){ + Hide(); + aMsg = guiMsgReturn; + } + return aMsg; +} + +void TCheckNormal::DrawGridAndText() +{ + int x,y; + if(LanguageEnCn==0){ + y = Lv.FixColTop +1; + TextRender_string24(Lv.ColLeft[0] + 60, y ,clNearWhite, "类型" ); + TextRender_string24(Lv.ColLeft[1] + 22, y, clNearWhite, "设计数量" ); + TextRender_string24(Lv.ColLeft[2] + 8, y, clNearWhite, "正常工作数" ); + TextRender_string24(Lv.ColLeft[3] + 36, y, clNearWhite, "故障数" ); + TextRender_string24(Lv.ColLeft[4] + 36, y, clNearWhite, "屏蔽数" ); + + x = Lv.ColLeft[0] + 10; + TextRender_string24(x, Lv.ColTop[0] + 1, clNearBlack, clOdd, "烟感" ); + TextRender_string24(x, Lv.ColTop[1] + 1, clNearBlack, clEven, "温感" ); + TextRender_string24(x, Lv.ColTop[2] + 1, clNearBlack, clOdd, "手报" ); + TextRender_string24(x, Lv.ColTop[3] + 1, clNearBlack, clEven, "消钮" ); + TextRender_string24(x, Lv.ColTop[4] + 1, clNearBlack, clOdd, "输入模块" ); + TextRender_string24(x, Lv.ColTop[5] + 1, clNearBlack, clEven, "输入输出模块" ); + TextRender_string24(x, Lv.ColTop[6] + 1, clNearBlack, clOdd, "输出模块" ); + TextRender_string24(x, Lv.ColTop[7] + 1, clNearBlack, clEven, "声光警报器" ); + TextRender_string24(x, Lv.ColTop[8] + 1, clNearBlack, clOdd, "层显" ); + TextRender_string24(x, Lv.ColTop[9] + 1, clNearBlack, clEven, "联动电源" ); + TextRender_string24(x, Lv.ColTop[10] + 1, clNearBlack, clOdd, "其他" ); + }else{ + y = Lv.FixColTop +1; + TextRender_string24(Lv.ColLeft[0] + 60, y ,clNearWhite, "Dev Type" ); + TextRender_string24(Lv.ColLeft[1] + 22, y, clNearWhite, "Designed" ); + TextRender_string24(Lv.ColLeft[2] + 20, y, clNearWhite, "IDLE" ); + TextRender_string24(Lv.ColLeft[3] + 36, y, clNearWhite, "Fault" ); + TextRender_string24(Lv.ColLeft[4] + 36, y, clNearWhite, "Blocking" ); + + x = Lv.ColLeft[0] + 10; + TextRender_string24(x, Lv.ColTop[0] + 1, clNearBlack, clOdd, "Smoke Detector" ); + TextRender_string24(x, Lv.ColTop[1] + 1, clNearBlack, clEven, "Tempe Detector" ); + TextRender_string24(x, Lv.ColTop[2] + 1, clNearBlack, clOdd, "Report KeyPad" ); + TextRender_string24(x, Lv.ColTop[3] + 1, clNearBlack, clEven, "Hydrant KeyPad" ); + TextRender_string24(x, Lv.ColTop[4] + 1, clNearBlack, clOdd, "Input Module" ); + TextRender_string24(x, Lv.ColTop[5] + 1, clNearBlack, clEven, "In/Out Module" ); + TextRender_string24(x, Lv.ColTop[6] + 1, clNearBlack, clOdd, "Output Module" ); + TextRender_string24(x, Lv.ColTop[7] + 1, clNearBlack, clEven, "Acoustooptic" ); + TextRender_string24(x, Lv.ColTop[8] + 1, clNearBlack, clOdd, "Floor Display" ); + TextRender_string24(x, Lv.ColTop[9] + 1, clNearBlack, clEven, "Linkage Power" ); + TextRender_string24(x, Lv.ColTop[10] + 1, clNearBlack, clOdd, "Other" ); + } +} + +void TCheckNormal::LoadAndDrawData(void) +{ + int x; + + //Design Count + //MainCtl.LoadVisioInf(); + MainCtl.LoadNormalInf(); + MainCtl.LoadFaultInf(); + MainCtl.LoadMaskInf(); + + if(IsSelfChecking)return; + if(PmsIntervene.IsShow)return; + + x = Lv.ColLeft[1] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, DesigePrmData.Count.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, DesigePrmData.Count.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, DesigePrmData.Count.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, DesigePrmData.Count.HydrantKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, DesigePrmData.Count.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, DesigePrmData.Count.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, DesigePrmData.Count.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, DesigePrmData.Count.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, DesigePrmData.Count.DisplayPad); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, DesigePrmData.Count.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, DesigePrmData.Count.Other); + + x = Lv.ColLeft[2] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, MainCtl.CountEpNormal.Smoker); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, MainCtl.CountEpNormal.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, MainCtl.CountEpNormal.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, MainCtl.CountEpNormal.Fire_hydrant_Kp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, MainCtl.CountEpNormal.Input); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, MainCtl.CountEpNormal.InOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, MainCtl.CountEpNormal.Output); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, MainCtl.CountEpNormal.VaAlram); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, MainCtl.CountEpNormal.DisplayPad); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, MainCtl.CountEpNormal.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, MainCtl.CountEpNormal.UnDefine + MainCtl.CountEpNormal.Unknown); + + x = Lv.ColLeft[3] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, MainCtl.CountEpFault.Smoker); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, MainCtl.CountEpFault.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, MainCtl.CountEpFault.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, MainCtl.CountEpFault.Fire_hydrant_Kp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, MainCtl.CountEpFault.Input); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, MainCtl.CountEpFault.InOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, MainCtl.CountEpFault.Output); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, MainCtl.CountEpFault.VaAlram); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, MainCtl.CountEpFault.DisplayPad); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, MainCtl.CountEpFault.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, MainCtl.CountEpFault.UnDefine + MainCtl.CountEpFault.Unknown); + + x = Lv.ColLeft[4] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, MainCtl.CountEpMask.Smoker); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, MainCtl.CountEpMask.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, MainCtl.CountEpMask.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, MainCtl.CountEpMask.Fire_hydrant_Kp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, MainCtl.CountEpMask.Input); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, MainCtl.CountEpMask.InOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, MainCtl.CountEpMask.Output); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, MainCtl.CountEpMask.VaAlram); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, MainCtl.CountEpMask.DisplayPad); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, MainCtl.CountEpMask.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, MainCtl.CountEpMask.UnDefine + MainCtl.CountEpMask.Unknown); +} + + +void TCheckNormal::ClearAndDrawData(void) +{ + int x; + + x = Lv.ColLeft[1] + 30; + TextRender_string24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[1] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[3] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[5] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[7] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[9] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, " "); + + x = Lv.ColLeft[2] + 30; + TextRender_string24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[1] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[3] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[5] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[7] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[9] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, " "); + + x = Lv.ColLeft[3] + 30; + TextRender_string24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[1] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[3] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[5] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[7] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[9] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, " "); + + x = Lv.ColLeft[4] + 30; + TextRender_string24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[1] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[3] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[5] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[7] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, " "); + TextRender_string24(x, Lv.ColTop[9] +1, clNearBlack, clEven, " "); + TextRender_string24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, " "); +} + +void TCheckNormal::LoadAndDrawDataSlave(unsigned char aCtlNum) +{ + int x; + unsigned char PNum; + + if(aCtlNum == 0)return; + if(aCtlNum > dNETWORK_MACHINE_COUNT)return; + PNum = aCtlNum-1; + + x = Lv.ColLeft[1] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Designed.cOther); + + x = Lv.ColLeft[2] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Normal.cOther); + + x = Lv.ColLeft[3] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Fault.cOther); + + x = Lv.ColLeft[4] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, ProtoC2C.CheckNormalDataSlave[PNum].Slave.Mask.cOther); +} + + +void TCheckNormal::LoadAndDrawDataAll() +{ + int x; + unsigned char PNum; + + x = Lv.ColLeft[1] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Designed.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, CheckNormalDataAll.All.Designed.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Designed.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, CheckNormalDataAll.All.Designed.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Designed.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, CheckNormalDataAll.All.Designed.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Designed.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, CheckNormalDataAll.All.Designed.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Designed.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, CheckNormalDataAll.All.Designed.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Designed.cOther); + + x = Lv.ColLeft[2] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Normal.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, CheckNormalDataAll.All.Normal.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Normal.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, CheckNormalDataAll.All.Normal.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Normal.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, CheckNormalDataAll.All.Normal.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Normal.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, CheckNormalDataAll.All.Normal.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Normal.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, CheckNormalDataAll.All.Normal.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Normal.cOther); + + x = Lv.ColLeft[3] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Fault.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, CheckNormalDataAll.All.Fault.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Fault.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, CheckNormalDataAll.All.Fault.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Fault.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, CheckNormalDataAll.All.Fault.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Fault.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, CheckNormalDataAll.All.Fault.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Fault.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, CheckNormalDataAll.All.Fault.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Fault.cOther); + + x = Lv.ColLeft[4] + 30; + TextDigitRender6Right24(x, Lv.ColTop[0] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Mask.Smoke); + TextDigitRender6Right24(x, Lv.ColTop[1] +1, clNearBlack, clEven, CheckNormalDataAll.All.Mask.Tempe); + TextDigitRender6Right24(x, Lv.ColTop[2] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Mask.HandReport); + TextDigitRender6Right24(x, Lv.ColTop[3] +1, clNearBlack, clEven, CheckNormalDataAll.All.Mask.HydKp); + TextDigitRender6Right24(x, Lv.ColTop[4] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Mask.ModuleInput); + TextDigitRender6Right24(x, Lv.ColTop[5] +1, clNearBlack, clEven, CheckNormalDataAll.All.Mask.ModuleInOut); + TextDigitRender6Right24(x, Lv.ColTop[6] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Mask.ModuleOutput); + TextDigitRender6Right24(x, Lv.ColTop[7] +1, clNearBlack, clEven, CheckNormalDataAll.All.Mask.Va); + TextDigitRender6Right24(x, Lv.ColTop[8] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Mask.FDisplay); + TextDigitRender6Right24(x, Lv.ColTop[9] +1, clNearBlack, clEven, CheckNormalDataAll.All.Mask.LnkPs); + TextDigitRender6Right24(x, Lv.ColTop[10] +1, clNearBlack, clOdd, CheckNormalDataAll.All.Mask.cOther); +} + +void TCheckNormal::CheckDoneClear() +{ + ProtoC2C.ClearCheckNormalDataSlave(); + IsSlaveDone = 0; +} + +void TCheckNormal::CheckSlaveDone() +{ + int i, x, aDone; + aDone = 1; + for(i=0; i 110){ + Hide(); + return -1; + } + if(MainCtl.fData.Split.NetworkMode != 1){ + return 0; + } + + if(CheckIsFrozeScreen() == 0){ + CheckSlaveDone(); + if(LanguageEnCn==0){ + if(IsSlaveDone){ + TextRender_string24(10, 75, clNearBlack, Color, "区域机加载完成 " ); + }else{ + TextRender_string24(10, 75, clNearBlack, Color, "区域机加载进行中" ); + } + }else{ + if(IsSlaveDone){ + TextRender_string24(10, 75, clNearBlack, Color, "Remote Data Upload Completed" ); + }else{ + TextRender_string24(10, 75, clNearBlack, Color, "Remote Data Uploading " ); + } + } + CheckNwAllCount(); + ShowData(0); + } + + if(AskInx < ProtoC2C.SlaveCount){ + AskNum = ProtoC2C.SlaveList[AskInx]; + ProtoC2C.CheckNormalSlave(AskNum); + AskInx++; + } + return 0; + } + return 0; +} + +int TCheckNormal::ExtRequst(unsigned char Prm) +{ + if(IsShowing){ + Record.OperateAdd_UserCheck(MainCtl.fData.Split.MyNum, 0); + IsShowing =0; + } + return 0; +} + diff --git a/MyCode/Gui/CheckNormal.h b/MyCode/Gui/CheckNormal.h new file mode 100644 index 0000000..834fc00 --- /dev/null +++ b/MyCode/Gui/CheckNormal.h @@ -0,0 +1,173 @@ +#ifndef CHECKNORMAL_H_ +#define CHECKNORMAL_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" + + +//For Idle View or Edit +class TCheckNormal{ + public: + TStaticText Caption; + class TDesignPrmSet *pDesignPrmSet; + + struct{ + short RowCount; + short ColTop[12]; + short ColBottom[12]; + short ColHeight; + short ColWidth[6]; + short ColLeft[6]; + short ColRight[6]; + short FixColTop; + short FixColBottom; + }Lv; + + //TMyString Str[10]; + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + int IsShowing; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + char Text[64]; + struct{ + int DevAll; + int DevRoot; + int DevEp; + int Linkage; + int LinkageActive; + int EventFire; + int EventFault; + int EventSuperSv; + int EventStart; + int EventFeedback; + }Count; + + unsigned char LoadCtlNum; + unsigned char SlaveCheckInx; + unsigned char IsSlaveDone; + unsigned char AskInx; + unsigned char AskNum; + union{ + unsigned int D32[120]; + struct{ + struct{ + unsigned int Smoke; + unsigned int Tempe; + unsigned int HandReport; + unsigned int HydKp; + unsigned int ModuleInput; + unsigned int ModuleInOut; + unsigned int ModuleOutput; + unsigned int Va; + unsigned int FDisplay; + unsigned int LnkPs; + unsigned int cOther; + }Designed; + struct{ + unsigned int Smoke; + unsigned int Tempe; + unsigned int HandReport; + unsigned int HydKp; + unsigned int ModuleInput; + unsigned int ModuleInOut; + unsigned int ModuleOutput; + unsigned int Va; + unsigned int FDisplay; + unsigned int LnkPs; + unsigned int cOther; + }Normal; + struct{ + unsigned int Smoke; + unsigned int Tempe; + unsigned int HandReport; + unsigned int HydKp; + unsigned int ModuleInput; + unsigned int ModuleInOut; + unsigned int ModuleOutput; + unsigned int Va; + unsigned int FDisplay; + unsigned int LnkPs; + unsigned int cOther; + }Fault; + struct{ + unsigned int Smoke; + unsigned int Tempe; + unsigned int HandReport; + unsigned int HydKp; + unsigned int ModuleInput; + unsigned int ModuleInOut; + unsigned int ModuleOutput; + unsigned int Va; + unsigned int FDisplay; + unsigned int LnkPs; + unsigned int cOther; + }Mask; + }All; + }CheckNormalDataAll; + unsigned char HasDrawData[68]; + unsigned int AutoReturnTick; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5); + + public: + TCheckNormal(){}; + TCheckNormal(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void Show(void); + void ShowCtlNum(); + void ReDraw(void); + void DrawCaption(void); + void RenderContent(void); + + void DrawGridAndText(); + void CheckNwAllCount(); + + void ClearAndDrawData(); + void LoadAndDrawData(void); + void LoadAndDrawDataSlave(unsigned char aCtlNum); + void LoadAndDrawDataAll(); + void ShowData(unsigned int Force); + void CheckDoneClear(); + void CheckSlaveDone(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + int Task500Ms(); + void Hide(); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + + + + + diff --git a/MyCode/Gui/CircuitCfg.cpp b/MyCode/Gui/CircuitCfg.cpp new file mode 100644 index 0000000..aa62254 --- /dev/null +++ b/MyCode/Gui/CircuitCfg.cpp @@ -0,0 +1,1165 @@ +#include "RuntimeData.h" +#include "CircuitCfg.h" +#include "gvalue.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 +/* +#define dgTYPE_SMOKE_DETECTOR 0x03 +#define dgTYPE_TEMPE_DETECTOR 0x02 +#define dgTYPE_HAND_REPORT 0x30 +#define dgTYPE_FIRE_HydrantKp 0x31 +#define dgTYPE_IN_MODULE 0x40 +#define dgTYPE_OUT_MODULE 0x43 +#define dgTYPE_INOUT_MODULE_NonSource 0x44 +#define dgTYPE_INOUT_MODULE_Source 0x45 +#define dgType_VAALRAM 0x32 +#define dgTYPE_DISPLAY_PAD 0x50 +*/ +static const unsigned char dTypeList[256] = { + dgTYPE_SMOKE_DETECTOR, + dgTYPE_TEMPE_DETECTOR, + dgType_VAALRAM, +}; + +const unsigned char dSmokeSensGrade_MarkValue[4] = { + //100, 75, 50, 25 + 100, 50, 0, 0 +}; + + +void TCircuitCfg::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+358,Top,434, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + RectPanel.Set(400,76,780,430); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("系统调试->回路设备参数配置", Caption.Text); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + CtlIndex = 0; + + OnActive = 0; + + IsWait4CfgRpy =0; + IsWait4Read =0; + TipState = 0; + IsShow = 0; + + ProcessingRt.Method = 1; + ProcessingRt.P0 = 1; + ProcessingRt.P1 = 1; + ProcessingRt.DevType =0; + ProcessingRt.DataType = 1; +} + +void TCircuitCfg::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TCircuitCfg::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TCircuitCfg::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TCircuitCfg::DrawCaption2(void) +{ + TMyString::sFromStr("/////", SText.Text); + //SText.Show(); +} + +void TCircuitCfg::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + + IsShow = 1; +} + +void TCircuitCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + PanelCanvasOut(); + aPanel->Show(); + ShowState(); + + RedrawMethod(); + RedrawDataType(); + RedrawDataValue(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + PanelCanvasOut(); + aPanel->Show(); + ShowState(); + + RedrawMethod(); + RedrawDataType(); + RedrawDataValue(); + } +} + + +void TCircuitCfg::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ + +void TCircuitCfg::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<4;i++)aPanel->Edit[i].Selected = 0; + for(i=11; i<15;i++)aPanel->Edit[i].Selected = 0; + for(i=0; i<2;i++)aPanel->Btn[i].Selected = 0; + if(CtlIndex < 4){ + aPanel->Edit[CtlIndex].Selected = 1; + }else + if(CtlIndex ==4){ + aPanel->Edit[11].Selected = 1; + } + if(CtlIndex ==5){ + aPanel->Btn[0].Selected = 1; + } + if(CtlIndex == 6){ + aPanel->Btn[1].Selected = 1; + } +} + +void TCircuitCfg::RedrawMethod() +{ + if(ProcessingRt.Method == 0){ + aPanel->ReDrawItems(); + aPanel->Edit[0].Str.FromStr("按设备类型"); + aPanel->Edit[0].ReDraw(); + + TMyString::sFromStr("设备类型", aPanel->SText[13].Text); + aPanel->SText[13].Show(); + + aPanel->Edit[2].IsShowCursor = 0; + RedrawDevType(); + + aPanel->Btn[0].Enable = 0; + aPanel->Btn[0].Show(); + + + }else{ + aPanel->ReDrawItems(); + aPanel->Edit[0].Str.FromStr("按地址"); + aPanel->Edit[0].ReDraw(); + + TMyString::sFromStr("地址", aPanel->SText[13].Text); + aPanel->SText[13].Show(); + + aPanel->Edit[2].IsShowCursor = 1; + RedrawP1(); + + aPanel->Btn[0].Enable = 1; + aPanel->Btn[0].Show(); + + + } +} + +void TCircuitCfg::RedrawDevType() +{ + if(ProcessingRt.DevType == 0){ + aPanel->ReDrawItems(); + aPanel->Edit[2].Str.FromStr("点型烟感"); + aPanel->Edit[2].ReDraw(); + }else + if(ProcessingRt.DevType == 1){ + aPanel->ReDrawItems(); + aPanel->Edit[2].Str.FromStr("点型温感"); + aPanel->Edit[2].ReDraw(); + }else + if(ProcessingRt.DevType == 2){ + aPanel->ReDrawItems(); + aPanel->Edit[2].Str.FromStr("声光警报器"); + aPanel->Edit[2].ReDraw(); + } +} + +void TCircuitCfg::RedrawP1() +{ + aPanel->Edit[2].Str.FromUInt3Dg(ProcessingRt.P1); + aPanel->Edit[2].ReDraw(); + +} + +void TCircuitCfg::RedrawDataType() +{ + //0x01:烟感灵敏度(送检前完成) + //0x02:烟感背景光 + //0x03:烟感标定值 + //0x06:温感类别 + //0x07:声光类别 + //0x08:模块输出线检测 + //0x09:模块输出类别 + //0x20:层显地址段配置 + + switch(ProcessingRt.DataType){ + case 1: + aPanel->Edit[3].Str.FromStr("烟感灵敏度"); + TextOut4SmokeSens(); + break; + case 2: + aPanel->Edit[3].Str.FromStr("烟感背景光"); + TextOut4SmokeBackGroundLight(); + break; + case 3: + aPanel->Edit[3].Str.FromStr("烟感标定值"); + TextOut4SmokeRefrence(); + break; + case 6: + aPanel->Edit[3].Str.FromStr("温感类别"); + TextOut4Tempe(); + break; + case 7: + aPanel->Edit[3].Str.FromStr("声光类别"); + TextOut4Va(); + break; + case 8: + aPanel->Edit[3].Str.FromStr("模块输出线检测"); + TextOut4ModuleOutputChexk(); + break; + case 9: + aPanel->Edit[3].Str.FromStr("模块输出类别"); + TextOut4ModuleOutputType(); + break; + case 0x20: + aPanel->Edit[3].Str.FromStr("层显地址段配置"); + TextOut4FloorDisplay(); + break; + default: + ProcessingRt.DataType = 1; + aPanel->Edit[3].Str.FromStr("烟感灵敏度"); + TextOut4SmokeSens(); + break; + } + + aPanel->Edit[3].Show(); + aPanel->SText[1].Show(); + aPanel->SText[2].Show(); + aPanel->SText[3].Show(); + aPanel->SText[4].Show(); +} + +void TCircuitCfg::RedrawDataValue() +{ + //0x01:烟感灵敏度(送检前完成) + //0x02:烟感背景光 + //0x03:烟感标定值 + //0x06:温感类别 + //0x07:声光类别 + //0x08:模块输出线检测 + //0x09:模块输出类别 + //0x20:层显地址段配置 + + switch(ProcessingRt.DataType){ + case 1: + RedrawSmokeSensValue(); + break; + case 2: + aPanel->Edit[11].Str.Clear(); + aPanel->Edit[12].Str.Clear(); + aPanel->Edit[13].Str.Clear(); + aPanel->Edit[14].Str.Clear(); + break; + case 3: + aPanel->Edit[11].Str.Clear(); + aPanel->Edit[12].Str.Clear(); + aPanel->Edit[13].Str.Clear(); + aPanel->Edit[14].Str.Clear(); + break; + case 6: + RedrawTempeValue(); + break; + case 7: + aPanel->Edit[11].Str.Clear(); + aPanel->Edit[12].Str.Clear(); + aPanel->Edit[13].Str.Clear(); + aPanel->Edit[14].Str.Clear(); + break; + case 8: + aPanel->Edit[11].Str.Clear(); + aPanel->Edit[12].Str.Clear(); + aPanel->Edit[13].Str.Clear(); + aPanel->Edit[14].Str.Clear(); + break; + case 9: + aPanel->Edit[11].Str.Clear(); + aPanel->Edit[12].Str.Clear(); + aPanel->Edit[13].Str.Clear(); + aPanel->Edit[14].Str.Clear(); + break; + case 0x20: + aPanel->Edit[11].Str.Clear(); + aPanel->Edit[12].Str.Clear(); + aPanel->Edit[13].Str.Clear(); + aPanel->Edit[14].Str.Clear(); + break; + default: + aPanel->Edit[11].Str.Clear(); + aPanel->Edit[12].Str.Clear(); + aPanel->Edit[13].Str.Clear(); + aPanel->Edit[14].Str.Clear(); + break; + } + aPanel->Edit[3].Show(); + aPanel->Edit[11].Show(); + aPanel->Edit[12].Show(); + aPanel->Edit[13].Show(); + aPanel->Edit[14].Show(); +} + +void TCircuitCfg::RedrawSmokeSensValue() +{ + /* + if(UserSetData.SmokeSensGrade == 0){ + aPanel->Edit[11].Str.FromStr("低灵敏度"); + }else + if(UserSetData.SmokeSensGrade == 1){ + aPanel->Edit[11].Str.FromStr("中灵敏度"); + }else + if(UserSetData.SmokeSensGrade == 2){ + aPanel->Edit[11].Str.FromStr("高灵敏度"); + }else{ + aPanel->Edit[11].Str.FromStr("未知等级"); + } + */ + if(UserSetData.SmokeSensGrade == 0){ + aPanel->Edit[11].Str.FromStr("标准灵敏度"); + }else + if(UserSetData.SmokeSensGrade == 1){ + aPanel->Edit[11].Str.FromStr("高灵敏度"); + }else{ + aPanel->Edit[11].Str.FromStr("未知等级"); + } + aPanel->Edit[11].Show(); +} + +void TCircuitCfg::RedrawTempeValue() +{ + //1..9 A1、A1R、A1S、A2、A2R、A2S、B、BR、BS + switch(UserSetData.TempeSensType){ + case 1:aPanel->Edit[11].Str.FromStr("1.A1");break; + case 2:aPanel->Edit[11].Str.FromStr("2.A1R");break; + case 3:aPanel->Edit[11].Str.FromStr("3.A1S");break; + case 4:aPanel->Edit[11].Str.FromStr("4.A2");break; + case 5:aPanel->Edit[11].Str.FromStr("5.A2R");break; + case 6:aPanel->Edit[11].Str.FromStr("6.A2S");break; + case 7:aPanel->Edit[11].Str.FromStr("7.B");break; + case 8:aPanel->Edit[11].Str.FromStr("8.BR");break; + case 9:aPanel->Edit[11].Str.FromStr("9.BS");break; + } + aPanel->Edit[11].ReDraw(); +} + + +void TCircuitCfg::PkgSetData() +{ + switch(ProcessingRt.DataType){ + case 1: + if(UserSetData.SmokeSensGrade < 2) + ProcessingRt.dVal[0] = dSmokeSensGrade_MarkValue[UserSetData.SmokeSensGrade]; + else + ProcessingRt.dVal[0] = 0; + ProcessingRt.dVal[1] =0; + ProcessingRt.dVal[2] =0; + ProcessingRt.dVal[3] =0; + break; + case 2: + case 3: + case 6: + case 7: + case 8: + case 9: + case 0x20: + ProcessingRt.dVal[0] =0; + ProcessingRt.dVal[1] =0; + ProcessingRt.dVal[2] =0; + ProcessingRt.dVal[3] =0; + break; + default: + break; + } +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TCircuitCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + if( (IsWait4Read==0) && (IsWait4CfgRpy==0) ){ + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(CtlIndex == 0){ + if(ProcessingRt.Method ==0){ + ProcessingRt.Method =1; + RedrawP1(); + }else{ + ProcessingRt.Method =0; + RedrawDevType(); + } + RedrawMethod(); + }else + if(CtlIndex == 1){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].ReDraw(); + }else + if(CtlIndex == 2){ + if(ProcessingRt.Method == 0){ + ProcessingRt.DevType++; + if(ProcessingRt.DevType >= 3)ProcessingRt.DevType = 0; + RedrawDevType(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].ReDraw(); + } + }else + if(CtlIndex == 3){ + switch(ProcessingRt.DataType){ + case 1: + ProcessingRt.DataType = 2; + break; + case 2: + ProcessingRt.DataType = 3; + break; + case 3: + ProcessingRt.DataType = 6; + break; + case 6: + ProcessingRt.DataType = 7; + break; + case 7: + ProcessingRt.DataType = 8; + break; + case 8: + ProcessingRt.DataType = 9; + break; + case 9: + ProcessingRt.DataType = 0x20; + break; + case 0x20: + ProcessingRt.DataType = 1; + break; + default: + ProcessingRt.DataType = 1; + break; + } + RedrawDataType(); + RedrawDataValue(); + }else + if(CtlIndex == 4){ + switch(ProcessingRt.DataType){ + case 1: + if(UserSetData.SmokeSensGrade <1)UserSetData.SmokeSensGrade++; + else UserSetData.SmokeSensGrade = 0; + break; + case 2: + + break; + case 3: + + break; + case 6: + + break; + case 7: + + break; + case 8: + + break; + case 9: + + break; + case 0x20: + + break; + default: + break; + } + RedrawDataValue(); + }else + if(CtlIndex == 5){ + switch(ProcessingRt.DataType){ + case 2: + + break; + case 3: + + break; + case 7: + + break; + case 9: + break; + case 0x20: + break; + default: + break; + } + }else + if(CtlIndex == 6){ + switch(ProcessingRt.DataType){ + case 2: + + break; + case 3: + + break; + case 9: + + break; + case 0x20: + + break; + default: + break; + } + }else + if(CtlIndex == 7){ + switch(ProcessingRt.DataType){ + case 2: + + break; + case 3: + + break; + case 0x20: + + break; + default: + break; + } + } + } + + if(aKey == VK_UP){ + if(CtlIndex >0){ + CtlIndex--; + }else{ + CtlIndex=6; + } + if(ProcessingRt.Method == 0){ + if(CtlIndex == 5)CtlIndex = 4; + } + Check4Selected(); + aPanel->ReDrawItems(); + }else + if(aKey == VK_DOWN){ + if(CtlIndex <6){ + CtlIndex++; + }else{ + CtlIndex =0; + } + if(ProcessingRt.Method == 0){ + if(CtlIndex == 5)CtlIndex = 6; + } + Check4Selected(); + aPanel->ReDrawItems(); + }else + if(aKey == VK_EXECUTE){ + //Save Data Here + if(TipState != 1){ + if(CtlIndex == 5){ + SendCmdRead(); + IsWait4Read =1; + ShowState(1); + RecRdy = 0; + RecCmd =0; + WaitTick = 0; + }else + if(CtlIndex == 6){ + PkgSetData(); + SendCmdCfg(); + IsWait4CfgRpy =1; + ShowState(1); + RecRdy = 0; + RecCmd =0; + WaitTick = 0; + } + } + } + } + + if(aKey == VK_RETURN){ + TipState = 0; + IsShow = 0; + IsWait4Read =0; + IsWait4CfgRpy =0; + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TCircuitCfg::PanelCanvasOut() +{ + HorizLineRender(RectPanel.Left + 12, RectPanel.Top + 137, RectPanel.Width -34, clGray); + HorizLineRender(RectPanel.Left + 12, RectPanel.Top + 274, RectPanel.Width -34, clGray); + + TextRender_string24(4, 120, clNearBlack, "1.回路号:"); + TextRender_string24(28, 155, clNearBlack, " 0 :无效"); + TextRender_string24(28, 190, clNearBlack, "1~40:单回路"); + + TextRender_string24(4, 230, clNearBlack, "2.地址段:"); + TextRender_string24(28, 265, clNearBlack, "范围:1~250"); + //TextRender_string24(28, 300, clNearBlack, "0~0:回路内所有同类型设备"); + + TextRender_string24(4, 320, clNearBlack, "3.上下键切换选项"); + TextRender_string24(4, 360, clNearBlack, "4.数字键左右键删除键进行编辑"); +} + +void TCircuitCfg::TextOut4All() +{ + TMyString::sFromStr("楼层号", aPanel->SText[1].Text); + TMyString::sFromStr("区域号", aPanel->SText[2].Text); + TMyString::sFromStr("通用参数1", aPanel->SText[3].Text); + TMyString::sFromStr("通用参数2", aPanel->SText[4].Text); + //TMyString::sFromStr("通用参数3", aPanel->SText[5].Text); + //TMyString::sFromStr("通用参数4", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4SmokeSens() +{ + TMyString::sFromStr("灵敏度 ", aPanel->SText[1].Text); + TMyString::sFromStr("不可用", aPanel->SText[2].Text); + TMyString::sFromStr("不可用", aPanel->SText[3].Text); + TMyString::sFromStr("不可用", aPanel->SText[4].Text); + //TMyString::sFromStr("不可用", aPanel->SText[5].Text); + //TMyString::sFromStr("不可用", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4SmokeBackGroundLight() +{ + TMyString::sFromStr("蓝光值", aPanel->SText[1].Text); + TMyString::sFromStr("红光值", aPanel->SText[2].Text); + TMyString::sFromStr("不可用", aPanel->SText[3].Text); + TMyString::sFromStr("不可用", aPanel->SText[4].Text); + //TMyString::sFromStr("不可用", aPanel->SText[5].Text); + //TMyString::sFromStr("不可用", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4SmokeRefrence() +{ + TMyString::sFromStr("蓝光值", aPanel->SText[1].Text); + TMyString::sFromStr("红光值", aPanel->SText[2].Text); + TMyString::sFromStr("不可用", aPanel->SText[3].Text); + TMyString::sFromStr("不可用", aPanel->SText[4].Text); + //TMyString::sFromStr("不可用", aPanel->SText[5].Text); + //TMyString::sFromStr("不可用", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4Tempe() +{ + TMyString::sFromStr("温感类别", aPanel->SText[1].Text); + TMyString::sFromStr("不可用", aPanel->SText[2].Text); + TMyString::sFromStr("不可用", aPanel->SText[3].Text); + TMyString::sFromStr("不可用", aPanel->SText[4].Text); + //TMyString::sFromStr("不可用", aPanel->SText[5].Text); + //TMyString::sFromStr("不可用", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4Va() +{ + TMyString::sFromStr("声光类别", aPanel->SText[1].Text); + TMyString::sFromStr("音调", aPanel->SText[2].Text); + TMyString::sFromStr("不可用", aPanel->SText[3].Text); + TMyString::sFromStr("不可用", aPanel->SText[4].Text); +} + +void TCircuitCfg::TextOut4ModuleOutputChexk() +{ + TMyString::sFromStr("输入检线", aPanel->SText[1].Text); + TMyString::sFromStr("不可用", aPanel->SText[2].Text); + TMyString::sFromStr("不可用", aPanel->SText[3].Text); + TMyString::sFromStr("不可用", aPanel->SText[4].Text); + //TMyString::sFromStr("输出占空比", aPanel->SText[5].Text); + //TMyString::sFromStr("不可用", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4ModuleOutputType() +{ + //TMyString::sFromStr("输出类别", aPanel->SText[1].Text); + //TMyString::sFromStr("输入检线", aPanel->SText[2].Text); + //TMyString::sFromStr("输出检线", aPanel->SText[3].Text); + //TMyString::sFromStr("输入占空比", aPanel->SText[4].Text); + //TMyString::sFromStr("输出占空比", aPanel->SText[5].Text); + //TMyString::sFromStr("不可用", aPanel->SText[6].Text); + + TMyString::sFromStr("输出类别", aPanel->SText[1].Text); + TMyString::sFromStr("输入检线", aPanel->SText[2].Text); + TMyString::sFromStr("输出检线", aPanel->SText[3].Text); + TMyString::sFromStr("输入占空比", aPanel->SText[4].Text); +} + +void TCircuitCfg::TextOut4MotherBoard() +{ + TMyString::sFromStr("最大输出电流", aPanel->SText[1].Text); + TMyString::sFromStr("负荷电流阀值", aPanel->SText[2].Text); + TMyString::sFromStr("时隙1", aPanel->SText[3].Text); + TMyString::sFromStr("时隙2", aPanel->SText[4].Text); + //TMyString::sFromStr("偏移量1", aPanel->SText[5].Text); + //TMyString::sFromStr("偏移量2", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4Circuit() +{ + TMyString::sFromStr("最大输出电流", aPanel->SText[1].Text); + TMyString::sFromStr("负荷电流阀值", aPanel->SText[2].Text); + TMyString::sFromStr("时隙1", aPanel->SText[3].Text); + TMyString::sFromStr("时隙2", aPanel->SText[4].Text); + //TMyString::sFromStr("偏移量1", aPanel->SText[5].Text); + //TMyString::sFromStr("偏移量2", aPanel->SText[6].Text); +} + +void TCircuitCfg::TextOut4FloorDisplay() +{ + TMyString::sFromStr("机器号", aPanel->SText[1].Text); + TMyString::sFromStr("回路", aPanel->SText[2].Text); + TMyString::sFromStr("起始地址", aPanel->SText[3].Text); + TMyString::sFromStr("结束地址", aPanel->SText[4].Text); + //TMyString::sFromStr("偏移量1", aPanel->SText[5].Text); + //TMyString::sFromStr("偏移量2", aPanel->SText[6].Text); +} + +void TCircuitCfg::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[11].Init(6,0, 170,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[12].Init(6,32, 170,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[13].Init(6,64, 170,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[14].Init(6,96, 170,30,x,yt,clNearBlack,clFrmFace); + + aPanel->SText[1].Init(6,138, 170,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[2].Init(6,170, 170,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[3].Init(6,202, 170,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[4].Init(6,234, 170,30,x,yt,clNearBlack,clFrmFace); + + aPanel->SText[5].Init(6,270, 170,30,x,yt,clNearBlack,clFrmFace); + + TMyString::sFromStr("读写方式", aPanel->SText[11].Text); + TMyString::sFromStr("回路", aPanel->SText[12].Text); + TMyString::sFromStr("地址", aPanel->SText[13].Text); + TMyString::sFromStr("数据类型", aPanel->SText[14].Text); + + TMyString::sFromStr("参数1", aPanel->SText[1].Text); + TMyString::sFromStr("参数2", aPanel->SText[2].Text); + TMyString::sFromStr("参数3", aPanel->SText[3].Text); + TMyString::sFromStr("参数4", aPanel->SText[4].Text); + aPanel->SText[5].TextClear(); + + aPanel->SText[2].Enable = 0; + aPanel->SText[3].Enable = 0; + aPanel->SText[4].Enable = 0; + + aPanel->Edit[0].Init(170,0,200,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(170,32,200,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(170,64,200,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[3].Init(170,96,200,30,x,yt,clNearBlack,clNearWhite); + + aPanel->Edit[11].Init(170,138,200,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[12].Init(170,170,200,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[13].Init(170,202,200,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[14].Init(170,234,200,30,x,yt,clNearBlack,clNearWhite); + + for(i=0; i<2;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + for(i=0; i<4;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("0"); + aPanel->Edit[i].Pst = 0; + } + aPanel->Edit[0].SetInputMaskEn(); + aPanel->Edit[0].Pst = -1; + aPanel->Edit[0].SetMaxLen(32); + + aPanel->Edit[1].Str.FromStr("01"); + aPanel->Edit[2].Str.FromStr("001"); + aPanel->Edit[1].Pst = 1; + aPanel->Edit[2].Pst = 2; + aPanel->Edit[1].SetMaxLen(2); + aPanel->Edit[2].SetMaxLen(3); + aPanel->Edit[3].SetMaxLen(3); + aPanel->Edit[4].SetMaxLen(32); + + for(i=11; i<15;i++){ + aPanel->Edit[i].Enable = 0; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + aPanel->Edit[i].Pst = 2; + } + aPanel->Edit[11].Enable = 1; + + aPanel->Edit[0].IsShowCursor = 0; + aPanel->Edit[1].IsShowCursor = 1; + aPanel->Edit[2].IsShowCursor = 0; + aPanel->Edit[3].IsShowCursor = 0; + + aPanel->Edit[11].IsShowCursor = 0; + aPanel->Edit[12].IsShowCursor = 0; + aPanel->Edit[13].IsShowCursor = 0; + aPanel->Edit[14].IsShowCursor = 0; + + aPanel->Btn[0].Init(200,276,160,30,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(200,308,160,30,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("读取配置"); + aPanel->Btn[1].Caption.FromStr("执行配置"); + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + + RedrawMethod(); + RedrawDataType(); + RedrawDataValue(); + +} + +void TCircuitCfg::ShowState() +{ + if(TipState == 0){ + aPanel->SText[5].TextClear(); + }else + if(TipState == 1){ + aPanel->SText[5].SetText("等待回复", 24); + }else + if(TipState == 2){ + aPanel->SText[5].SetText("读取成功", 24); + }else + if(TipState == 3){ + aPanel->SText[5].SetText("写入成功", 24); + }else + if(TipState == 4){ + aPanel->SText[5].SetText("操作失败", 24); + } + + if(TipState == 1){ + aPanel->Btn[0].Enable = 0; + aPanel->Btn[1].Enable = 0; + }else{ + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 1; + } + + aPanel->SText[5].Show(); + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); +} + +void TCircuitCfg::ShowState(int Prm) +{ + TipState = Prm; + ShowState(); +} + +void TCircuitCfg::SendCmdRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + Len =4; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 3; + + iVal = aPanel->Edit[1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aPx = cVal; + Data[1] = aPx; + ProcessingRt.P0 = aPx; + + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aPx = cVal; + Data[2] = aPx; + ProcessingRt.P1 = aPx; + + Data[3] = ProcessingRt.DataType; + + aIde.BitF.Cmd = cmQuerySens; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TCircuitCfg::SendCmdCfg() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + Len =8; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 3; + + iVal = aPanel->Edit[1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aPx = cVal; + Data[1] = aPx; + ProcessingRt.P0 = aPx; + + if(ProcessingRt.Method ==0){ + Data[2] = dTypeList[ProcessingRt.DevType]; + ProcessingRt.dType = Data[2]; + aIde.BitF.Cmd = cmDeviceConfig; + }else{ + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aPx = cVal; + ProcessingRt.P1 = aPx; + Data[2] = ProcessingRt.P1; + + aIde.BitF.Cmd = cmDeviceSetSens; + } + + RedrawSmokeSensValue(); + + Data[3] = ProcessingRt.DataType; + Data[4] = ProcessingRt.dVal[0]; + Data[5] = ProcessingRt.dVal[1]; + Data[6] = ProcessingRt.dVal[2]; + Data[7] = ProcessingRt.dVal[3]; + + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TCircuitCfg::PushInnerCanData(unsigned char aCmd, unsigned char *Data) +{ + int i; + if(aCmd == cmDeviceSetSens){ + for(i=0; i<8; i++)RecData[i] = Data[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) && + (ProcessingRt.dVal[0] == RecData[4])) { + RecRdy =1; + RecCmd =aCmd; + } + }else + if(aCmd == cmDeviceConfig){ + for(i=0; i<8; i++)RecData[i] = Data[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.dType == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) && + (ProcessingRt.dVal[0] == RecData[4]) ) { + RecRdy =1; + RecCmd =aCmd; + } + } + if(aCmd == cmQuerySens){ + for(i=0; i<8; i++)RecData[i] = Data[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ProcessingRt.dValGot[1] = RecData[5]; + ProcessingRt.dValGot[2] = RecData[6]; + ProcessingRt.dValGot[3] = RecData[7]; + RecRdy =1; + RecCmd =aCmd; + } + } +} + +void TCircuitCfg::Task1000Ms() +{ + if(IsShow){ + if(IsWait4Read){ + if(RecRdy){ + if(RecCmd == cmQuerySens){ + RecRdy = 0; + IsWait4Read = 0; + ShowState(2); + //Add Record Here + if(ProcessingRt.DataType == 1){ + if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[0] )UserSetData.SmokeSensGrade = 0; + else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[1] )UserSetData.SmokeSensGrade = 1; + //else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[2] )UserSetData.SmokeSensGrade = 2; + else UserSetData.SmokeSensGrade = 3; + RedrawSmokeSensValue(); + } + } + RecRdy = 0; + } + WaitTick ++; + if(WaitTick > 6){ + IsWait4Read = 0; + ShowState(4); + } + }else + if(IsWait4CfgRpy){ + if(RecRdy){ + if(RecCmd == cmDeviceSetSens){ + IsWait4CfgRpy = 0; + ShowState(3); + //Add Record Here + aFullPath.Body.pCtl = MainCtl.fData.Split.MyNum; + aFullPath.Body.P0 = ProcessingRt.P0; + aFullPath.Body.P1 = ProcessingRt.P1; + if(ProcessingRt.DataType == 1) { + Record.OperateAdd_CfgAddrSmokeSensGrade(aFullPath.D32, UserSetData.SmokeSensGrade); + } + }else + if(RecCmd == cmDeviceConfig){ + IsWait4CfgRpy = 0; + ShowState(3); + //Add Record Here + aFullPath.Body.pCtl = MainCtl.fData.Split.MyNum; + aFullPath.Body.P0 = ProcessingRt.P0; + if(ProcessingRt.DataType == 1){ + Record.OperateAdd_CfgCircuitSmokeSensGrade(aFullPath.D32, UserSetData.SmokeSensGrade); + } + } + RecRdy = 0; + } + WaitTick ++; + if(WaitTick > 6){ + IsWait4CfgRpy = 0; + ShowState(4); + } + } + } +} + +int TCircuitCfg::ExtRequst(unsigned char Prm) +{ + TipState = 0; + IsWait4Read =0; + IsWait4CfgRpy =0; + IsShow = 0; + return 0; +} + + + + diff --git a/MyCode/Gui/CircuitCfg.h b/MyCode/Gui/CircuitCfg.h new file mode 100644 index 0000000..310d308 --- /dev/null +++ b/MyCode/Gui/CircuitCfg.h @@ -0,0 +1,181 @@ +#ifndef CIRCUITCFG_H_ +#define CIRCUITCFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TCircuitCfg{ + public: + int IsShow; + + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect RectCanvas; + + TRect Content; + TRect RectPanel; + + TMyString Str; + + struct{ + unsigned char Method; + unsigned char P0; + unsigned char P1; + unsigned char DevType; + unsigned char DataType; + + unsigned char dVal[4]; + unsigned char dValGot[4]; + unsigned char dType; + }ProcessingRt; + + struct{ + unsigned char SmokeSensGrade; + struct{ + union { + unsigned short D16; + struct{ + unsigned char LowB; + unsigned char HiB; + }D8; + }Blue; + union { + unsigned short D16; + struct{ + unsigned char LowB; + unsigned char HiB; + }D8; + }Red; + }SmokeBackGroundLight; + struct{ + union { + unsigned short D16; + struct{ + unsigned char LowB; + unsigned char HiB; + }D8; + }Blue; + union { + unsigned short D16; + struct{ + unsigned char LowB; + unsigned char HiB; + }D8; + }Red; + }SmokeRefrence; + unsigned char TempeSensType; + struct{ + unsigned char Type; + unsigned char Tone; + }VaType; + }UserSetData; + + union{ + unsigned int D32; + struct{ + unsigned char pCtl; + unsigned char P0; + unsigned char P1; + unsigned char P2; + }Body; + }aFullPath; + + unsigned int CtlIndex; + int IsFastCmd; + unsigned char Data[8]; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char RecData[8]; + + unsigned char IsWait4CfgRpy; + unsigned char IsWait4Read; + unsigned char TipState; + unsigned int WaitTick; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TCircuitCfg(){}; + TCircuitCfg(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void RedrawSmokeSensValue(); + void RedrawTempeValue(); + void RedrawVaValue(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + void RedrawMethod(); + void RedrawP1(); + void RedrawDevType(); + void RedrawDataType(); + void RedrawDataValue(); + + void PkgSetData(); + + void ShowState(); + void ShowState(int Prm); + + void TextOut4All(); + void TextOut4SmokeSens(); + void TextOut4SmokeBackGroundLight(); + void TextOut4SmokeRefrence(); + void TextOut4Tempe(); + void TextOut4Va(); + void TextOut4InOutMdl(); + void TextOut4MotherBoard(); + void TextOut4Circuit(); + + void TextOut4ModuleOutputChexk(); + void TextOut4ModuleOutputType(); + void TextOut4FloorDisplay(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + + void SendCmdRead(); + void SendCmdCfg(); + void PushInnerCanData(unsigned char aCmd, unsigned char *Data); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + +#endif + + + diff --git a/MyCode/Gui/CircuitState.cpp b/MyCode/Gui/CircuitState.cpp new file mode 100644 index 0000000..62841c2 --- /dev/null +++ b/MyCode/Gui/CircuitState.cpp @@ -0,0 +1,543 @@ +#include "RuntimeData.h" +#include "CircuitState.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +static const unsigned char stCmd[8] = {221,222,223,224,225,226,227,228}; +static const unsigned char stPrm[8] = {0,1,2,3,4,5,6,7}; + +void TCircuitState::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+358,Top,434, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + RectPanel.Set(140,78,660,410); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("回路运行状态-本机", Caption.Text); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + CtlIndex = 0; + CtlLevel = 0; + IsShowing = 0; + + for(i=0; i<12; i++){ + RecData[i] = 0; + RecDataUpdateFlag[i] =0; + } +} + +void TCircuitState::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TCircuitState::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TCircuitState::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TCircuitState::DrawCaption2(void) +{ + TMyString::sFromStr("xxxxxxx", SText.Text); + //SText.Show(); +} + +void TCircuitState::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + IsShowing = 1; +} + +void TCircuitState::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + aPanel->Show(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + } +} + +void TCircuitState::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ + +void TCircuitState::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<3;i++)aPanel->Edit[i].Selected = 0; + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Edit[2].Selected = 1; + break; + default: + break; + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TCircuitState::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].ReDraw(); + CheckPathDev(); + }else + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].ReDraw(); + CheckPathDev(); + }else + if(aPanel->Edit[2].Selected){ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].ReDraw(); + CheckPathDev(); + } + } + + if(aKey == VK_UP){ + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_DOWN){ + if(CtlIndex <2){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_TAB){ + + }else + if(aKey == VK_F2){ + SendCmd(0); + }else + if(aKey == VK_EXECUTE){ + //Save Data Here + SendCmd(1); + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TCircuitState::PanelCanvasOut() +{ + //TXBox::sDrawBoxBorder(RectPanel.Left + 8, RectPanel.Top + 3, RectPanel.Left + 362, RectPanel.Top + 150, "自定义命令", 8, 1, 0, clFrmFace); +} + +void TCircuitState::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + aPanel->Caption.Text[0] = 0; + + aPanel->SText[0].Init(2,6,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(2,44,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(2,82,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(2,120,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(2,158,60,30,x,y,clNearBlack,clFrmFace); + + aPanel->SText[5].Init(200,6,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[6].Init(200,44,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[7].Init(200,82,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[8].Init(200,120,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[9].Init(200,158,60,30,x,y,clNearBlack,clFrmFace); + + aPanel->SText[10].Init(16,190,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[11].Init(16,236,60,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("机器号", aPanel->SText[0].Text); + TMyString::sFromStr("回路号", aPanel->SText[1].Text); + TMyString::sFromStr("地址号", aPanel->SText[2].Text); + TMyString::sFromStr("类型", aPanel->SText[3].Text); + TMyString::sFromStr("注释", aPanel->SText[4].Text); + + TMyString::sFromStr("机器号状态", aPanel->SText[5].Text); + TMyString::sFromStr("Circuit", aPanel->SText[6].Text); + TMyString::sFromStr("Addr", aPanel->SText[7].Text); + TMyString::sFromStr("dType", aPanel->SText[8].Text); + TMyString::sFromStr("Descp", aPanel->SText[9].Text); + + + TMyString::sFromStr("1.按确认键启动目标", aPanel->SText[10].Text); + TMyString::sFromStr("2.按设置键停止目标", aPanel->SText[11].Text); + + for(i=0; i<12;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + + aPanel->Edit[0].Init(100,6,60,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(100,44,60,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(100,82,60,30,x,y,clNearBlack,clNearWhite); + + for(i=0; i<3;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(8); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.Clear(); + aPanel->Edit[i].Pst = -1; + } + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[0].Str.FromStr("01"); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[0].Color = clMoneyGreen; + aPanel->Edit[1].SetMaxLen(2); + aPanel->Edit[1].Str.FromStr("01"); + aPanel->Edit[1].Pst = 1; + aPanel->Edit[2].SetMaxLen(3); + aPanel->Edit[2].Str.FromStr("001"); + aPanel->Edit[2].Pst = 2; + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + + CheckPathDev(); +} + +void TCircuitState::CheckPathDev() +{ + unsigned char cVal; + int iVal; + int P0Found = 0; + int P1Found = 0; + unsigned char aCn, aP0, aP1; + unsigned int aAddr,i; + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Path.pNum = cVal; + + iVal = aPanel->Edit[1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Path.P0 = cVal; + + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Path.P1 = cVal; + + for(i=0; i<32; i++){ + aPanel->SText[8].Text[i] = 0; + } + + if(Path.pNum == MainCtl.fData.Split.MyNum){ + if(MainCtl.fData.Split.NetworkMode == 1){ + aPanel->SText[4].SetText("本集中机",24); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + aPanel->SText[4].SetText("本区域机",24); + }else{ + aPanel->SText[4].SetText("本机",24); + } + + if( (Path.P0 >0) && (Path.P0 <= dPORT_MAX_COUNT) ){ + if(MainCtl.fData.Split.ExistTablePort[Path.P0 -1]){ + aPanel->SText[5].SetText(" ",24); + P0Found = 1; + }else{ + aPanel->SText[5].SetText("回路未注册",24); + aPanel->SText[6].SetText(" ",24); + aPanel->SText[7].SetText(" ",24); + aPanel->SText[8].SetText(" ",24); + } + }else{ + aPanel->SText[5].SetText("回路号超出范围",24); + aPanel->SText[6].SetText(" ",24); + aPanel->SText[7].SetText(" ",24); + aPanel->SText[8].SetText(" ",24); + } + + if(P0Found){ + if( (Path.P1 >0) && (Path.P1 <= 251) ){ + if(MainCtl.fData.Split.ExistTablePort[Path.P1 -1]){ + aPanel->SText[6].SetText(" ",24); + P1Found = 1; + }else{ + aPanel->SText[6].SetText("地址未注册",24); + } + }else{ + aPanel->SText[6].SetText("地址号超出范围",24); + } + } + + if(P1Found){ + Path.dType = Port[Path.P0-1].dTypeTable[Path.P1-1]; + TMyString::sFromStr(StrTypeShortName[Path.dType], aPanel->SText[7].Text); + aP0 = Path.P0; + aP1 = Path.P1; + if(aP0 && aP1){ + if(aP0 < dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1 - 1); + aP0 = 40; + } + if(aP0 <= dPORT_MAX_COUNT){ + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=0; i<32; i++){ + aPanel->SText[8].Text[i] = *(volatile unsigned char *)(aAddr + i); + } + aPanel->SText[8].Text[32] = '\0'; + } + } + }else{ + TMyString::sFromStr(" ", aPanel->SText[7].Text); + } + }else{ + if(MainCtl.fData.Split.NetworkMode == 1){ + aPanel->SText[4].SetText(" ",24); + aPanel->SText[5].SetText(" ",24); + aPanel->SText[6].SetText(" ",24); + aPanel->SText[7].SetText(" ",24); + aPanel->SText[8].SetText(" ",24); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + aPanel->SText[4].SetText("本机为区域机,不能操作",24); + aPanel->SText[5].SetText(" ",24); + aPanel->SText[6].SetText(" ",24); + aPanel->SText[7].SetText(" ",24); + aPanel->SText[8].SetText(" ",24); + }else{ + aPanel->SText[4].SetText("本机为单机,不能操作 ",24); + aPanel->SText[5].SetText(" ",24); + aPanel->SText[6].SetText(" ",24); + aPanel->SText[7].SetText(" ",24); + aPanel->SText[8].SetText(" ",24); + } + + if(MainCtl.fData.Split.NetworkMode == 1){ + if( (Path.pNum) && (Path.pNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = Path.pNum -1; + aP0 = Path.P0; + aP1 = Path.P1; + if(aP0 && aP1){ + if(aP0 < dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + if(aP0 <= dPORT_MAX_COUNT){ + aAddr = dAddrSdRam_DescpNw + (aCn*409600)+(aP0*8192) + (aP1*32); + for(i=0; i<32; i++){ + aPanel->SText[8].Text[i] = *(volatile unsigned char *)(aAddr + i); + } + aPanel->SText[8].Text[32] = '\0'; + } + } + } + } + } + aPanel->SText[4].Show(); + aPanel->SText[5].Show(); + aPanel->SText[6].Show(); + aPanel->SText[7].Show(); + aPanel->SText[8].Show(); +} + +void TCircuitState::SendCmd(unsigned int IsStart) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + if(IsStart){ + aIde.BitF.Cmd = cmAutoStart; + }else{ + aIde.BitF.Cmd = cmAutoStop; + } + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Path.pNum = cVal; + + iVal = aPanel->Edit[1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Path.P0 = cVal; + + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Path.P1 = cVal; + + + + + + + Len = 5; + + Data[0] = 0; + + //Path 0 + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[1] = cVal; + + //Cmd 1 + iVal = aPanel->Edit[7].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aIde.BitF.Cmd = cVal; + + //Cmd 2 + iVal = aPanel->Edit[8].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[3] = cVal; + + //Prm + iVal = aPanel->Edit[9].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[4] = cVal; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +int TCircuitState::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} + + + + + + + diff --git a/MyCode/Gui/CircuitState.h b/MyCode/Gui/CircuitState.h new file mode 100644 index 0000000..f12e661 --- /dev/null +++ b/MyCode/Gui/CircuitState.h @@ -0,0 +1,85 @@ +#ifndef CIRCUITSTATE_H_ +#define CIRCUITSTATE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TCircuitState{ + public: + TCtlPanel1 *aPanel; + unsigned int IsShowing; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect VScrollBarBox; + + TRect Content; + TRect RectPanel; + + TMyString Str; + + unsigned int CtlIndex; + unsigned int CtlLevel; + + int IsFastCmd; + unsigned char Data[8]; + unsigned short RecData[12]; + unsigned char RecDataUpdateFlag[12]; + + struct{ + unsigned char pNum; + unsigned char P0; + unsigned char P1; + unsigned char dType; + }Path; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TCircuitState(){}; + TCircuitState(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + void CheckPathDev(); + void SendCmd(unsigned int IsStart); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + diff --git a/MyCode/Gui/CleanUp.cpp b/MyCode/Gui/CleanUp.cpp new file mode 100644 index 0000000..a210cc8 --- /dev/null +++ b/MyCode/Gui/CleanUp.cpp @@ -0,0 +1,533 @@ +#include "CleanUp.h" +#include "Runtime.h" +#include "record.h" + +extern "C"{ + #include "user_norflash.h" + #include "uart_key_drv.h" +} + +void TCleanUp::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("系统设置->清除处理", Caption.Text); + Caption.Visible = 1; + + CtlIndex = 0; + OnActive = 0; +} + +void TCleanUp::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickShow(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + TextRender_string24(66, 240, clNearBlack, "1.上下键切换编辑项目"); + TextRender_string24(66, 280, clNearBlack, "2.选定项目按确定键执行"); + + aPanel->Show(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +//______________________________________________________________________________________________________________________________ + +void TCleanUp::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<9;i++)aPanel->Btn[i].Selected = 0; + if(1){ + switch(CtlIndex){ + case 0: + aPanel->Btn[0].Selected = 1; + break; + case 1: + aPanel->Btn[1].Selected = 1; + break; + case 2: + aPanel->Btn[2].Selected = 1; + break; + case 3: + aPanel->Btn[3].Selected = 1; + break; + case 4: + aPanel->Btn[4].Selected = 1; + break; + case 5: + aPanel->Btn[5].Selected = 1; + break; + case 6: + aPanel->Btn[6].Selected = 1; + break; + case 7: + aPanel->Btn[7].Selected = 1; + break; + case 8: + aPanel->Btn[8].Selected = 1; + break; + default: + + break; + } + } +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TCleanUp::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn MBoxMsg = guiMsgNone; + int iVal; + + switch(aKey){ + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <7){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + break; + case VK_EXECUTE: + //aPanel->Btn[0].Caption.FromStr(" 清除回路终端设备的登记 "); + //aPanel->Btn[1].Caption.FromStr(" 清除总线盘配置 "); + //aPanel->Btn[2].Caption.FromStr(" 清除多线盘配置 "); + //aPanel->Btn[3].Caption.FromStr(" 清除所有联动表达式 "); + //aPanel->Btn[4].Caption.FromStr(" 清除本机终端设备注释 "); + //aPanel->Btn[5].Caption.FromStr(" 清除组网配置 "); + //aPanel->Btn[6].Caption.FromStr(" 清除网络加载的设备注释 "); + + //aPanel->Btn[7].Caption.FromStr(" 预设描述 "); + if(CtlIndex == 0){ + cRegister(); + Record.OperateAdd_CleanUp(0); + }else + if(CtlIndex == 1){ + cBusPad(); + Record.OperateAdd_CleanUp(1); + }else + if(CtlIndex == 2){ + cDirectPad(); + Record.OperateAdd_CleanUp(2); + }else + if(CtlIndex == 3){ + cLinkage(); + Record.OperateAdd_CleanUp(3); + }else + if(CtlIndex == 4){ + cDescp(); + Record.OperateAdd_CleanUp(4); + }else + if(CtlIndex == 5){ + cNetwork(); + Record.OperateAdd_CleanUp(5); + }else + if(CtlIndex == 6){ + cDescpNw(); + Record.OperateAdd_CleanUp(6); + }else + if(CtlIndex == 7){ + cUserCodeAssignType(); + Record.OperateAdd_CleanUp(7); + }else + if(CtlIndex == 8){ + FillDescp(); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + + if(aKey != VK_EXECUTE){ + TextRender_string24(20, 110, clNearBlack, Color, " "); + } + + return aMsg; +} + +void TCleanUp::InitPanel(void) +{ + int x,y,x2,y2,i; + y = y+10; + + aPanel->Init(370,84,384,320,0,0,clFrmFace, bvRaised); + aPanel->Caption.Init(371,86, 384-3 ,32,0,0,clFrmFace,clFrmFace); + + x = aPanel->Bound.Left; + y = aPanel->Bound.Top; + + aPanel->Btn[0].Init(25,10,330,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(25,46,330,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[2].Init(25,82,330,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[3].Init(25,118,330,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[4].Init(25,154,330,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[5].Init(25,190,330,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[6].Init(25,226,330,32,x,y,clNearBlack,clFrmFace); + aPanel->Btn[7].Init(25,262,330,32,x,y,clNearBlack,clFrmFace); + + + aPanel->Btn[8].Init(25,310,330,36,x,y,clNearBlack,clFrmFace); + + aPanel->Btn[0].Caption.FromStr(" 清除回路终端设备的登记 "); + aPanel->Btn[1].Caption.FromStr(" 清除总线盘配置 "); + aPanel->Btn[2].Caption.FromStr(" 清除多线盘配置 "); + aPanel->Btn[3].Caption.FromStr(" 清除所有联动表达式 "); + aPanel->Btn[4].Caption.FromStr(" 清除本机终端设备注释 "); + aPanel->Btn[5].Caption.FromStr(" 清除组网配置 "); + aPanel->Btn[6].Caption.FromStr(" 清除网络加载的设备注释 "); + aPanel->Btn[7].Caption.FromStr(" 清除用户码及设备类型指派 "); + + aPanel->Btn[8].Caption.FromStr(" 预设描述 "); + + for(i=0; i<9;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(7); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); +} + +void TCleanUp::WaitChipIdle(unsigned int ChipX) +{ + volatile unsigned int Sta; + do{ + DelayMs(10); + Sta = nor_get_busy_state(ChipX); + }while(Sta); +} + +void TCleanUp::cRegister() +{ + volatile unsigned int aFlashState, i, m, aWait, aAddr; + + TextRender_string24(20, 110, clNearBlack, Color, "开始清除注册信息"); + + for(i=0; i<8; i++){ + WaitChipIdle(dFlashRegisterDataChip); + aAddr = dFlashRegisterDataAddr + (0x000010000 * i); + nor_erase_sector_64k(dFlashRegisterDataChip,aAddr); + } + + for(m=0; m<40; m++){ + for(i=0; i<250; i++){ + Port[m].ExistTable[i] = 0; + Port[m].dTypeTable[i] = 0; + //EpDev[m][i].fData.Split.dType = 0; + //EpDev[m][i].fData.Split.Id = 0; + } + MainCtl.fData.Split.ExistTablePort[m] = 0; + } + MainCtl.fData.Split.PortCount = 0; + + WaitChipIdle(dFlashRegisterDataChip); + Record.ReadRegisterData(); + TextRender_string24(20, 110, clNearBlack, Color, " 清除完成 "); +} + +void TCleanUp::cBusPad() +{ + unsigned int fAddr, sdAddr; + unsigned int i,m, pc; + volatile unsigned int aWait, x, wP1; + + TextRender_string24(20, 110, clNearBlack, Color, "开始清除总线盘配置"); + + for(x=0; x<2; x++){ + WaitChipIdle(dFlashBusPadLnkChipX); + fAddr = dFlashAddrBusPadLnk + (SizeOf64K * x); + nor_erase_sector_64k(dFlashBusPadLnkChipX,fAddr); + } + + WaitChipIdle(dFlashBusPadLnkChipX); + Record.LoadBusPadLnk(); + TextRender_string24(20, 110, clNearBlack, Color, " 清除完成 "); +} + +void TCleanUp::cDirectPad() +{ + unsigned int fAddr, sdAddr; + unsigned int i,m, pc; + volatile unsigned int aWait, x, wP1; + + TextRender_string24(20, 110, clNearBlack, Color, "开始清除多线盘配置"); + + for(x=0; x<2; x++){ + WaitChipIdle(dFlashDirectPadLnkChipX); + fAddr = dFlashAddrDirectPadLnk + (SizeOf64K * x); + nor_erase_sector_64k(dFlashDirectPadLnkChipX,fAddr); + } + + WaitChipIdle(dFlashDirectPadLnkChipX); + Record.LoadDirectPadCfg(); + TextRender_string24(20, 110, clNearBlack, Color, " 清除完成 "); +} + +void TCleanUp::cDescp() +{ + unsigned int fAddr, sdAddr; + unsigned int i,m; + volatile unsigned int aWait, x, wP1; + + TextRender_string24(20, 110, clNearBlack, Color, "开始清除注释信息"); + + //Erase 8 * 64K Blocks + for(x=0; x<8; x++){ + fAddr = dFlashAddrDescpBase + (SizeOf64K * x); + WaitChipIdle(dEepDescpChip); + nor_erase_sector_64k(dEepDescpChip,fAddr); + } + + WaitChipIdle(dEepDescpChip); + Record.ReadDescp(); + TextRender_string24(20, 110, clNearBlack, Color, " 清除完成 "); +} + +void TCleanUp::cLinkage() +{ + unsigned int i; + unsigned int fAddr64K; + TextRender_string24(20, 110, clNearBlack, Color, "开始清除联动信息"); + for(i=0; i清除注释信息"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "清除注释信息"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "确定", 12, clNearWhite); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Advanced Setup->Clear All Description"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Clear All Description"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "Clear", 6, clNearWhite); + } +} + +void TClearDescp::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "确定", 12, clNearBlack); + else TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "Clear", 6, clNearBlack); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[0] + 40, 600 , 120, 3); + } + } + break; + case VK_RETURN: + IsShowing = 0; + if(Eraser.OnGo){ + ForceExit(); + } + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TClearDescp::Task1000Ms() +{ + volatile unsigned int uiVal; + if(IsShowing){ + if(Eraser.OnGo == 0xB6){ + if(Eraser.Step < 6){ + sDelayMs(2); + uiVal = nor_get_busy_state(dEepDescpChip); + if(uiVal)return; + uiVal = dFlashAddrDescpBase + (Eraser.Step * 0x10000); + nor_erase_sector_64k(dEepDescpChip,uiVal); + Eraser.Step++; + }else + if(Eraser.Step < 7){ + sDelayMs(2); + uiVal = nor_get_busy_state(dEepDescpChip); + if(uiVal)return; + Eraser.Step++; + }else{ + sDelayMs(2); + uiVal = nor_get_busy_state(dEepDescpChip); + if(uiVal)return; + Record.ReadDescp(); + + if(LanguageEnCn==0) TextRender_string24(400, Lv.Grid.Top[0]+ 36, clNearWhite, ItemColor, "清除完成 "); + else TextRender_string24(400, Lv.Grid.Top[0]+ 36, clNearWhite, ItemColor, "Cleared "); + Record.OperateAdd_CleanUp(4); + Eraser.OnGo =0; + } + } + } +} + +void TClearDescp::ForceExit() +{ + Record.ReadDescp(); + Record.OperateAdd_CleanUp(0xF4); + Eraser.OnGo =0; +} + +int TClearDescp::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + if(Eraser.OnGo){ + ForceExit(); + } + return 0; +} + + + + + diff --git a/MyCode/Gui/ClearDescp.h b/MyCode/Gui/ClearDescp.h new file mode 100644 index 0000000..a024d5f --- /dev/null +++ b/MyCode/Gui/ClearDescp.h @@ -0,0 +1,120 @@ +#ifndef CLEARDESCP_H_ +#define CLEARDESCP_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TClearDescp{ + public: + static constexpr unsigned short hList[12] = {76,70,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 1, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4, + .Panel.Width = 796, + .Panel.Heigh = 140, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4 + 140 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + unsigned char PermissionCmd; + unsigned char IsPermission; + unsigned char Rsv1; + + struct{ + unsigned char OnGo; + unsigned char Step; + }Eraser; + public: + TClearDescp(){ + Eraser.OnGo =0; + }; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + static void sDelayMs(unsigned int aMs); + static void sDoClear(); + static void sDoClearNetwork(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + void ForceExit(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + +#endif diff --git a/MyCode/Gui/ClearLinkageCfg.cpp b/MyCode/Gui/ClearLinkageCfg.cpp new file mode 100644 index 0000000..895cb99 --- /dev/null +++ b/MyCode/Gui/ClearLinkageCfg.cpp @@ -0,0 +1,317 @@ +#include "ClearLinkageCfg.h" +#include "Runtime.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" + #include "HW_config.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +static const int xFirst = 10; +class TItemList *TClearLinkageCfg::sIList; + +void TClearLinkageCfg::Init() +{ + CtlIndex = 0; + IsShowing = 0; + + PermissionCmd =0; + IsPermission =0; + + Eraser.OnGo = 0; + Eraser.Step = 0xFF; +} + +void TClearLinkageCfg::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick清除联动编程"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "清除联动编程"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "确定", 12, clNearWhite); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Advanced Setup->Clear Linkage Expression"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Linkage Expression"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "Clear", 6, clNearWhite); + } +} + +void TClearLinkageCfg::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iReadWriteData.Reset(); + + fAddr4K = dFlashAddrLinkageExp + ((ToWriteInx * 1024) & 0x00FF'F000); + for(i=0; i<4; i++){ + Crc32Reset(); + fAddr4Index = fAddr4K + (i * 1024); + for(ord=0; ord<4; ord++){ + for(x=0; x<64; x++){ + sIList->ReadWriteData.D32[x] = 0; + if(ord<3 or x<63)Crc32Feed(sIList->ReadWriteData.D32[x]); + } + if(ord==3)sIList->ReadWriteData.D32[63]=Crc32GetResult(); + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(dFlashLinkageExpChipX); + }while(aFlashState); + nor_write_page(dFlashLinkageExpChipX, fAddr4Index, sIList->ReadWriteData.D8); + fAddr4Index+=256; + } + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(dFlashLinkageExpChipX); + }while(aFlashState); + InterLink.CheckStorageCrc(ToWriteInx+1); + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(dFlashLinkageExpChipX); + }while(aFlashState); + ToWriteInx++; + LoopCheck1S(); + } +} + +void TClearLinkageCfg::sDoClear() +{ + volatile unsigned int aFlashState; + unsigned int i, GroupCnt; + unsigned int fAddr64K; + for(i=0; i 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "确定", 12, clNearBlack); + else TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "Clear", 6, clNearBlack); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[0] + 40, 600 , 120, 3); + } + } + break; + case VK_RETURN: + IsShowing = 0; + if(Eraser.OnGo){ + ForceExit(); + } + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TClearLinkageCfg::Task1000Ms() +{ + //dFlashBlock64kCount4LinkageExp = 32 + volatile unsigned int uiVal; + + return; + if(IsShowing){ + if(Eraser.OnGo == 0xB6){ + if(Eraser.Step < dFlashBlock64kCount4LinkageExp){ + sDelayMs(2); + uiVal = nor_get_busy_state(dFlashLinkageExpChipX); + if(uiVal)return; + uiVal = dFlashAddrLinkageExp + (Eraser.Step * 0x10000); + nor_erase_sector_64k(dFlashLinkageExpChipX,uiVal); + Eraser.Step++; + }else + if(Eraser.Step < 33){ + sDelayMs(2); + uiVal = nor_get_busy_state(dFlashLinkageExpChipX); + if(uiVal)return; + Eraser.Step++; + }else{ + sDelayMs(2); + uiVal = nor_get_busy_state(dFlashLinkageExpChipX); + if(uiVal)return; + InterLink.Init(); + InterLink.LoadExpression2Ram(); + + if(LanguageEnCn==0) TextRender_string24(400, Lv.Grid.Top[0]+ 36, clNearWhite, ItemColor, "清除完成 "); + else TextRender_string24(400, Lv.Grid.Top[0]+ 36, clNearWhite, ItemColor, "Cleared "); + Record.OperateAdd_CleanUp(3); + Eraser.OnGo =0; + } + } + } +} + +void TClearLinkageCfg::ForceExit() +{ + InterLink.Init(); + InterLink.LoadExpression2Ram(); + Record.OperateAdd_CleanUp(0xF3); + Eraser.OnGo =0; +} + +int TClearLinkageCfg::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + if(Eraser.OnGo){ + ForceExit(); + } + return 0; +} + + + + + diff --git a/MyCode/Gui/ClearLinkageCfg.h b/MyCode/Gui/ClearLinkageCfg.h new file mode 100644 index 0000000..736e682 --- /dev/null +++ b/MyCode/Gui/ClearLinkageCfg.h @@ -0,0 +1,120 @@ +#ifndef CLEARLINKAGECFG_H_ +#define CLEARLINKAGECFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TClearLinkageCfg{ + public: + static constexpr unsigned short hList[12] = {76,70,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 1, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4, + .Panel.Width = 796, + .Panel.Heigh = 140, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4 + 140 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + static class TItemList *sIList; + int IsShowing; + unsigned char CtlIndex; + unsigned char PermissionCmd; + unsigned char IsPermission; + unsigned char Rsv1; + struct{ + unsigned char OnGo; + unsigned char Step; + }Eraser; + public: + TClearLinkageCfg(){ + Eraser.OnGo =0; + }; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + static void sDelayMs(unsigned int aMs); + static void sClear4Index(unsigned int aGroup); + static void sDoClear(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + void ForceExit(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + +#endif diff --git a/MyCode/Gui/ClearRegistedInf.cpp b/MyCode/Gui/ClearRegistedInf.cpp new file mode 100644 index 0000000..5dd87af --- /dev/null +++ b/MyCode/Gui/ClearRegistedInf.cpp @@ -0,0 +1,311 @@ +#include "ClearRegistedInf.h" +#include "Runtime.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" + #include "HW_config.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +static const int xFirst = 10; +class TItemList *TClearRegistedInf::sIList; + +void TClearRegistedInf::Init() +{ + CtlIndex = 0; + IsShowing = 0; + + PermissionCmd =0; + IsPermission =0; + + Eraser.OnGo = 0; + Eraser.Step = 0xFF; + Eraser.NotDone = 0; +} + +void TClearRegistedInf::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick清除注册数据"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "清除注册数据"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "确定", 12, clNearWhite); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Advanced Setup->Clear Registed Data"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Registed Data"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "Clear", 6, clNearWhite); + } +} + +void TClearRegistedInf::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iReadWriteData.Reset(); + + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + for(i=0; i<8; i++){ + SysLoopTick = 0; + fAddr = dFlashRegisterDataAddr + (0x000010000 * i); + nor_erase_sector_64k(0,fAddr); + sDelayMs(250); + do{ + sDelayMs(30); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + LoopCheck1S(); + } + + for(i=0; i 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "确定", 12, clNearBlack); + else TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "Clear", 6, clNearBlack); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[0] + 40, 600 , 120, 3); + } + } + break; + case VK_RETURN: + IsShowing = 0; + if(Eraser.OnGo){ + ForceExit(); + } + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TClearRegistedInf::Task1000Ms() +{ + volatile unsigned int uiVal; + return; + if(IsShowing){ + if(Eraser.OnGo == 0xB6){ + if(Eraser.Step < 8){ + sDelayMs(2); + uiVal = nor_get_busy_state(dFlashRegisterDataChip); + if(uiVal)return; + uiVal = dFlashRegisterDataAddr + (0x000010000 * Eraser.Step); + nor_erase_sector_64k(dFlashRegisterDataChip,uiVal); + Eraser.Step++; + }else + if(Eraser.Step < 9){ + sDelayMs(2); + uiVal = nor_get_busy_state(dFlashRegisterDataChip); + if(uiVal)return; + Eraser.Step++; + }else + if(Eraser.Step < 10){ + for(uiVal=0; uiVal<40; uiVal++){ + for(int i=0; i<250; i++){ + Port[uiVal].ExistTable[i] = 0; + Port[uiVal].dTypeTable[i] = 0; + //EpDev[m][i].fData.Split.dType = 0; + //EpDev[m][i].fData.Split.Id = 0; + } + MainCtl.fData.Split.ExistTablePort[uiVal] = 0; + } + MainCtl.fData.Split.PortCount = 0; + Eraser.Step++; + }else{ + sDelayMs(2); + uiVal = nor_get_busy_state(dFlashRegisterDataChip); + if(uiVal)return; + InnerCan.SendCmdClearRegData(); + Record.ReadRegisterData(); + if(LanguageEnCn==0) TextRender_string24(400, Lv.Grid.Top[0]+ 36, clNearWhite, ItemColor, "清除完成 "); + else TextRender_string24(400, Lv.Grid.Top[0]+ 36, clNearWhite, ItemColor, "Cleared "); + Record.OperateAdd_CleanUp(0); + Eraser.OnGo =0; + Eraser.NotDone =0; + } + } + } +} + +void TClearRegistedInf::ForceExit() +{ + sDelayMs(20); + Record.ReadRegisterData(); + Record.OperateAdd_CleanUp(0xF0); + Eraser.OnGo =0; +} + +int TClearRegistedInf::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + if(Eraser.OnGo){ + ForceExit(); + } + return 0; +} + + + + + + diff --git a/MyCode/Gui/ClearRegistedInf.h b/MyCode/Gui/ClearRegistedInf.h new file mode 100644 index 0000000..d22a6fc --- /dev/null +++ b/MyCode/Gui/ClearRegistedInf.h @@ -0,0 +1,121 @@ +#ifndef CLEARREGISTEDINF_H_ +#define CLEARREGISTEDINF_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TClearRegistedInf{ + public: + static constexpr unsigned short hList[12] = {76,70,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 1, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4, + .Panel.Width = 796, + .Panel.Heigh = 140, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4 + 140 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + unsigned char PermissionCmd; + unsigned char IsPermission; + unsigned char Rsv1; + struct{ + unsigned char OnGo; + unsigned char Step; + unsigned char NotDone; + unsigned char dump; + }Eraser; + static class TItemList *sIList; + public: + TClearRegistedInf(){ + Eraser.OnGo =0; + }; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + static void sDelayMs(unsigned int aMs); + static void sDoClear(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + void ForceExit(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + +#endif diff --git a/MyCode/Gui/CnInput.cpp b/MyCode/Gui/CnInput.cpp new file mode 100644 index 0000000..50764d8 --- /dev/null +++ b/MyCode/Gui/CnInput.cpp @@ -0,0 +1,1063 @@ +#include "CnInput.h" + +#define dfClr_PinyinSelBackGround clTeal + +const char ListPayload[10] = {0,0,3,3,3,3,3,4,3,4}; +const char ListCaseUp[10][4] = { +{' ', ' ', ' ', ' '}, +{' ', ' ', ' ', ' '}, +{'A', 'B', 'C', ' '}, +{'D', 'E', 'F', ' '}, +{'G', 'H', 'I', ' '}, +{'J', 'K', 'L', ' '}, +{'M', 'N', 'O', ' '}, +{'P', 'Q', 'R', 'S'}, +{'T', 'U', 'V', ' '}, +{'W', 'X', 'Y', 'Z'} +}; +const char ListCaseLow[10][4] = { +{' ', ' ', ' ', ' '}, +{' ', ' ', ' ', ' '}, +{'A', 'B', 'C', ' '}, +{'D', 'E', 'F', ' '}, +{'G', 'H', 'I', ' '}, +{'J', 'K', 'L', ' '}, +{'M', 'N', 'O', ' '}, +{'P', 'Q', 'R', 'S'}, +{'T', 'U', 'V', ' '}, +{'W', 'X', 'Y', 'Z'} +}; + +const char ccEnList[10][12] = { +{'0', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', 1}, +{'1', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', 2}, +{'2', 'A', 'B', 'C', 'a', 'b', 'c', ' ', ' ', ' ', ' ', 7}, +{'3', 'D', 'E', 'F', 'd', 'e', 'f', ' ', ' ', ' ', ' ', 7}, +{'4', 'G', 'H', 'I', 'g', 'h', 'i', ' ', ' ', ' ', ' ', 7}, +{'5', 'J', 'K', 'L', 'j', 'k', 'l', ' ', ' ', ' ', ' ', 7}, +{'6', 'M', 'N', 'O', 'm', 'n', 'o', ' ', ' ', ' ', ' ', 7}, +{'7', 'P', 'Q', 'R', 'S', 'p', 'q', 'r', 's', ' ', ' ', 9}, +{'8', 'T', 'U', 'V', 't', 'u', 'v', ' ', ' ', ' ', ' ', 7}, +{'9', 'W', 'X', 'Y', 'Z', 'w', 'x', 'y', 'z', ' ', ' ', 9} +}; + +const char ccSymbolList[4][12] = { +{'`', '~', '!', '@', '#', '$', '%', '^', ' ', ' ', ' ', 8}, +{'&', '*', '(', ')', '-', '+', '_', '=', ' ', ' ', ' ', 8}, +{'{', '}', '[', ']', '|', '\\', ':', ';', ' ', ' ', ' ', 8}, +{'"', '\'', '<', '>', ',', '.', '?', '/', ' ', ' ', ' ', 8}, +}; + +void TCnInput::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + unsigned short Left,Right,Top,Bottom; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + Color = aColor; + if(1){ + Left = Bound.Left + 1; + Right = Bound.Right - 2; + Top = Bound.Top + 1; + Bottom = Bound.Bottom - 2; + }else{ + Left = Bound.Left + 2; + Right = Bound.Right - 2; + Top = Bound.Top + 2; + Bottom = Bound.Bottom - 2; + } + Content.Set(Left,Top,Right,Bottom); + + iEdit.Init(0,0,2,28,Content.Left, Content.Top, Color, clDeepGray); + iEdit.Visible = 0; + iEdit.Enable = 1; + iEdit.SetMaxLen(8); + iEdit.Str.Clear(); + iEdit.IsShowCursor =0; + + sEdit.Init(0,0,90,28,Content.Left, Content.Top, Color, clDeepGray); + sEdit.Visible = 1; + sEdit.Enable = 1; + sEdit.SetMaxLen(8); + sEdit.Str.Clear(); + sEdit.IsShowCursor =1; + sEdit.Selected = 1; + + PySelIndex = 0; + CnSelIndex = 0; + + PyCount =0; + CnCount =0; + + IsShowing = 0; + SelectedCn = 0; + InputMode = CnInputModeEn; +} + +void TCnInput::DrawSelf(void) +{ + + /*unsigned int r,g,b, h,l; + h = Color & 0x00FFFFFF; + + r = h / 0x10000; + g = (h / 256) % 256; + b = h % 256; + + h = r * 3 / 2; if(h > 255)h=255; r = h; + h = g * 3 / 2; if(h > 255)h=255; g = h; + h = b * 3 / 2; if(h > 255)h=255; b = h; + h = (r<<16) + (g<<8) + b; + l = r * 2 / 3; r = l; + l = g * 2 / 3; g = l; + l = b * 2 / 3; b = l; + l = (r<<16) + (g<<8) + b; + + + //Draw Border + g = Bound.Right; + b = Bound.Bottom; + + //Draw Right & Bottom + for(r=0; r3)SymbolSelIndex = 0; + aInx = SymbolSelIndex; + aLen = ccSymbolList[SymbolSelIndex][11]; + for(i=0; i 3)aInx = 0; + aLen = ccSymbolList[aInx][11]; + + x = Content.Left + 10; + y = Content.Top + 59; + for(i=0; i 9)break; + if(x> (Content.Right-100))break; + if(z == PySelIndex){ + aClr = clNearWhite; + bClr = dfClr_PinyinSelBackGround; + }else{ + aClr = clNearBlack; + bClr = Color; + } + //gui_write_EN2412(x,y,aClr, bClr, '0' + (z+1) % 10); + //x+=12; + //RectFillRender(x, y, x+4, y+23, bClr); + //x+=4; + p = PinyinT9.GetPinyin(i); + v =0; + while(*p != '\0'){ + gui_write_EN2412(x,y,aClr, bClr, *p); + p++; + v++; + x+=12; + if(v>=7)break; + } + x += 20; + z++; + } +} + +void TCnInput::DrawCnList() +{ + int i,g,v,x,y, aInx; + unsigned int aClr, bClr, iClr; + const char *p; + + x = Content.Left + 6; + y = Content.Top + 57; + + if(SelectedCn == 1){ + iClr = clBlue; + aClr = clNearWhite; + bClr = dfClr_PinyinSelBackGround; + }else{ + iClr = clNearBlack; + aClr = clNearBlack; + bClr = Color; + } + RectFillRender(x, y, Content.Right-2, Content.Bottom - 2, bClr); + + if(PinyinT9.CnResult.CnCount > 0){ + y = Content.Top + 57 + 4; + if(CnSelIndex > 0){ + y = Content.Top + 57 + 4; + for(v=0; v<2; v++){ + aInx = 1; + x = 620; + for(i=0; i<8; i++){ + HorizLineRender(x, y, aInx, clBlue); + x--; + aInx += 2; + y++; + } + y += 3; + } + } + + y = Content.Top + 57 + 6; + if( CnSelIndex < (PinyinT9.CnResult.CnPageCount -1) ){ + for(v=0; v<2; v++){ + aInx = 16; + x = 640; + for(i=0; i<8; i++){ + HorizLineRender(x, y, aInx, clBlue); + x++; + aInx -= 2; + y++; + } + y += 3; + } + } + } + + x = Content.Left + 38; + y = Content.Top + 57; + for(i=0; i<10; i++){ + if(x> (Content.Right-50))break; + aInx = CnSelIndex * 10 + i ; + if( aInx >= PinyinT9.CnResult.CnCount)break; + gui_write_EN2412(x,y,iClr, bClr, '0' + i); + x+=12; + RectFillRender(x, y, x+4, y+23, bClr); + x+=4; + p = &PinyinT9.CnResult.pCn[aInx * 2]; + TextRender_1CN24(x,y,aClr,p); + x+=40; + } +} + +const char * TCnInput::TryGetCn(int cInx) +{ + int PyIndex, CnIndex; + PyIndex = PinyinT9.CnResult.Index[PySelIndex]; + CnIndex = CnSelIndex * 10 + cInx; + if(CnIndex < PinyinT9.CnResult.CnCount){ + TheGotCn = PinyinT9.TryGetCn(PinyinT9.CnResult.Index[PySelIndex], CnIndex); + if(TheGotCn != nullptr){ + iEdit.Str.Clear(); + iEdit.Pst = -1; + iEdit.Show(); + TMyString::sFromStr(iEdit.Str.Text, PinyinT9.InputStr.Num); + PinyinT9.GetMatchedPinyinCode(); + SelectedCn = 0; + PySelIndex = 0; + DrawPinyinList(); + CnSelIndex = 0; + PinyinT9.IdentifyCn(PySelIndex); + DrawCnList(); + GotChar[0] = *TheGotCn; + GotChar[1] = TheGotCn[1]; + GotChar[2] = '\0'; + return TheGotCn; + } + } + return nullptr; +} + +void TCnInput::ClearCnResult() +{ + PinyinT9.CnResult.Count = 0; + PinyinT9.CnResult.CnCount =0; + PinyinT9.CnResult.CnPageCount = 0; + CnSelIndex = 0; + iEdit.Str.Clear(); + iEdit.Pst = -1; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.Show(); + sEdit.ShowCursor(); +} + +void TCnInput::ShowPinyinText() +{ + int i,aLen; + const char *p; + aLen = iEdit.Str.GetEndPst() +1; + if(aLen >6)aLen = 6; + if(PinyinT9.CnResult.Count >0){ + if(PySelIndex < PinyinT9.CnResult.Count){ + p = PinyinT9.GetPinyin(PySelIndex); + for(i=0; i 0){ + SymbolSelIndex--; + DrawSymbolList(); + } + break; + case VK_RIGHT: + if(SymbolSelIndex < 3){ + SymbolSelIndex++; + DrawSymbolList(); + } + break; + case VK_UP: + if(SymbolSelIndex > 0){ + SymbolSelIndex--; + DrawSymbolList(); + } + break; + case VK_DOWN: + if(SymbolSelIndex < 3){ + SymbolSelIndex++; + DrawSymbolList(); + } + break; + case VK_TAB: + break; + case VK_EXECUTE: + break; + case VK_RETURN: + break; + } + return nullptr; +} + +const char * TCnInput::NumKeyIn(unsigned char aKey) +{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + GotChar[0] = aKey; + GotChar[1] = 0; + GotChar[2] = 0; + return GotChar; + break; + } + return nullptr; +} + +const char * TCnInput::CnKeyIn(unsigned char aKey) +{ + int i; + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + if( (SelectedCn == 0) || (aKey == VK_DELETE) ){ + iEdit.KeyIn(aKey); + TMyString::sFromStr(iEdit.Str.Text, PinyinT9.InputStr.Num); + i = PinyinT9.GetMatchedPinyinCode(); + if(0 == i){ + iEdit.KeyIn(VK_DELETE); + TMyString::sFromStr(iEdit.Str.Text, PinyinT9.InputStr.Num); + i = PinyinT9.GetMatchedPinyinCode(); + } + if(i)CnShowTip(1); + else CnShowTip(0); + ShowPinyinText(); + PySelIndex = 0; + DrawPinyinList(); + CnSelIndex = 0; + PinyinT9.IdentifyCn(PySelIndex); + SelectedCn = 0; + DrawCnList(); + } + if(SelectedCn == 1){ + if(aKey != VK_DELETE){ + TheGotCn = PinyinT9.TryGetCn(PinyinT9.CnResult.Index[PySelIndex], CnSelIndex * 10 + (aKey - '0') ); + TheGotCn = TryGetCn(aKey - '0'); + iEdit.Str.Clear(); + iEdit.Pst = -1; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.Show(); + SelectedCn = 0; + ClearCnResult(); + CnShowTip(0); + return TheGotCn; + } + } + break; + case VK_LEFT: + if(PinyinT9.CnResult.Count){ + if(PySelIndex > 0){ + PySelIndex--; + CnSelIndex = 0; + ShowPinyinText(); + DrawPinyinList(); + CnSelIndex = 0; + PinyinT9.IdentifyCn(PySelIndex); + DrawCnList(); + } + } + break; + case VK_RIGHT: + if(PinyinT9.CnResult.Count){ + if(PySelIndex < (PinyinT9.CnResult.Count-1)){ + PySelIndex++; + ShowPinyinText(); + DrawPinyinList(); + CnSelIndex = 0; + PinyinT9.IdentifyCn(PySelIndex); + DrawCnList(); + } + } + break; + case VK_UP: + if(CnSelIndex >0){ + CnSelIndex--; + DrawCnList(); + } + break; + case VK_DOWN: + if(CnSelIndex < (PinyinT9.CnResult.CnPageCount-1) ){ + CnSelIndex++; + DrawCnList(); + } + break; + case VK_TAB: + SelectedCn = 0; + DrawCnList(); + break; + case dfKEY_ASTERISK: + case dfKEY_SIG: + case VK_EXECUTE: + if(SelectedCn == 0){ + SelectedCn = 1; + CnShowTip(2); + DrawCnList(); + }else + if(SelectedCn == 1){ + SelectedCn = 0; + CnShowTip(1); + DrawCnList(); + } + break; + case VK_RETURN: + break; + } + return nullptr; +} + +const char * TCnInput::KeyIn(unsigned char aKey) +{ + if(aKey == dfKEY_ENCN){ + switch(InputMode){ + case CnInputModeEn: + InputMode = CnInputModeSymbol; + CnInputMode = CnInputModeSymbol; + DrawInputType(); + DrawSymbolList(); + + sEdit.Enable = 0; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.IsShowCursor = 0; + sEdit.Show(); + SymbolShowTip(0); + break; + case CnInputModeSymbol: + InputMode = CnInputModeCn; + CnInputMode = CnInputModeCn; + DrawInputType(); + ClearCnResult(); + + SelectedCn = 0; + PySelIndex = 0; + CnSelIndex = 0; + + ShowPinyinText(); + DrawPinyinList(); + DrawCnList(); + + CnShowTip(0); + break; + case CnInputModeCn: + InputMode = CnInputModeNum; + CnInputMode = CnInputModeNum; + DrawInputType(); + DrawEnList(); + + sEdit.Str.Clear(); + sEdit.Enable = 0; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.IsShowCursor = 0; + sEdit.Show(); + NumShowTip(0); + break; + case CnInputModeNum: + InputMode = CnInputModeEn; + CnInputMode = CnInputModeEn; + DrawInputType(); + DrawEnList(); + + sEdit.Str.Clear(); + sEdit.Enable = 1; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.IsShowCursor = 0; + sEdit.Show(); + EnShowTip(0); + break; + } + }else{ + switch(InputMode){ + case CnInputModeEn: + return EnKeyIn(aKey); + break; + case CnInputModeSymbol: + return SymbolKeyIn(aKey); + break; + case CnInputModeCn: + return CnKeyIn(aKey); + break; + case CnInputModeNum: + return NumKeyIn(aKey); + break; + } + } + return nullptr; +} + + +void TCnInput::SetInputMode(TTextInputMode aInputMode) +{ + switch(aInputMode){ + case CnInputModeSymbol: + InputMode = CnInputModeSymbol; + CnInputMode = aInputMode; + DrawInputType(); + DrawSymbolList(); + + sEdit.Enable = 0; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.IsShowCursor = 0; + sEdit.Show(); + SymbolShowTip(0); + break; + case CnInputModeCn: + InputMode = CnInputModeCn; + CnInputMode = aInputMode; + DrawInputType(); + ClearCnResult(); + + SelectedCn = 0; + PySelIndex = 0; + CnSelIndex = 0; + + ShowPinyinText(); + DrawPinyinList(); + DrawCnList(); + + CnShowTip(0); + break; + case CnInputModeEn: + InputMode = CnInputModeEn; + CnInputMode = aInputMode; + DrawInputType(); + DrawEnList(); + + sEdit.Str.Clear(); + sEdit.Enable = 1; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.IsShowCursor = 0; + sEdit.Show(); + EnShowTip(0); + break; + case CnInputModeNum: + InputMode = CnInputModeNum; + CnInputMode = aInputMode; + DrawInputType(); + DrawEnList(); + + sEdit.Str.Clear(); + sEdit.Enable = 0; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.IsShowCursor = 0; + sEdit.Show(); + NumShowTip(0); + break; + default: + InputMode = CnInputModeEn; + CnInputMode = CnInputModeEn; + DrawInputType(); + DrawEnList(); + + sEdit.Str.Clear(); + sEdit.Enable = 0; + sEdit.Str.Clear(); + sEdit.Pst = -1; + sEdit.IsShowCursor = 0; + sEdit.Show(); + EnShowTip(0); + break; + } +} + +int TCnInput::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} diff --git a/MyCode/Gui/CnInput.h b/MyCode/Gui/CnInput.h new file mode 100644 index 0000000..c8b5c33 --- /dev/null +++ b/MyCode/Gui/CnInput.h @@ -0,0 +1,87 @@ +#ifndef CNINPUT_H_ +#define CNINPUT_H_ + +#include "gType.h" +#include "gvalue.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "StaticText.h" +#include "TEdit.h" +#include "Runtime.h" + +class TCnInput{ + public: + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + TRect Bound; + TRect Content; + + class TEdit iEdit; + class TEdit sEdit; + int IsShowing; + + unsigned char SymbolSelIndex; + unsigned char PySelIndex; + unsigned char CnSelIndex; + unsigned char CnPage; + unsigned char PyCount; + unsigned char CnCount; + unsigned char SelectedCn; + const char *TheGotEn; + const char *TheGotSymbol; + const char *TheGotCn; + char GotChar[16]; + + TTextInputMode InputMode; + char NumChar[4]; + public: + TCnInput(){}; + TCnInput(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void Hide(); + void FullRedraw(); + + void DrawInputType(); + void DrawEnList(); + void DrawSymbolList(); + + void ShowPinyinText(); + void DrawPinyinList(); + void DrawCnList(); + + void CalcData(); + + void ClearCnResult(); + + const char * EnKeyIn(unsigned char aKey); + const char * SymbolKeyIn(unsigned char aKey); + const char * CnKeyIn(unsigned char aKey); + const char * NumKeyIn(unsigned char aKey); + const char * KeyIn(unsigned char aKey); + + const char * TryGetCn(int cInx); + + void EnShowTip(int tT); + void SymbolShowTip(int tT); + void CnShowTip(int tT); + void NumShowTip(int tT); + void OverPrint(unsigned int aClr); + + void SetInputMode(TTextInputMode aInputMode = CnInputModeEn); + + int ExtRequst(unsigned char Prm); +}; + +#endif + diff --git a/MyCode/Gui/CtlPanel1.cpp b/MyCode/Gui/CtlPanel1.cpp new file mode 100644 index 0000000..8a5c755 --- /dev/null +++ b/MyCode/Gui/CtlPanel1.cpp @@ -0,0 +1,117 @@ +#include "CtlPanel1.h" +#include "Runtime.h" + + +void TCtlPanel1::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + unsigned short Left,Right,Top,Bottom,i; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + Color = aColor; + BevelOuter = aBevelOuter; + if(BevelOuter == bvRaised){ + Left = Bound.Left + 1; + Right = Bound.Right - 2; + Top = Bound.Top + 1; + Bottom = Bound.Bottom - 2; + }else{ + Left = Bound.Left + 2; + Right = Bound.Right - 2; + Top = Bound.Top + 2; + Bottom = Bound.Bottom - 2; + } + + Caption.Init(Left, Top, Right-Left+1, 32, 0, 0, clNearWhite, clMedBlue); + Content.Set(Left,Top+32,Right,Bottom); + VScrollBarBox.Set(780,80,800,400); + VScrollBar.Color = 0xFF007777; + FixColColor = clMaroon; + FixColTextColor = clNearWhite; + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Caption.Visible = 0; + for(i=0;i<24;i++){ + SText[i].Enable = 0; + Edit[i].Enable = 0; + Btn[i].Enable = 0; + + SText[i].Visible = 0; + Edit[i].Visible = 0; + Btn[i].Visible = 0; + + SText[i].Selected = 0; + Edit[i].Selected = 0; + Btn[i].Selected = 0; + } +} + + +void TCtlPanel1::DrawSelf(void) +{ + unsigned int i; + if (BevelOuter == bvLowered){ + VertLineRender(Bound.Left, Bound.Top, Bound.Height-1, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width-1, 0xFF808080); + + VertLineRender(Bound.Left+1, Bound.Top+1, Bound.Height-2, 0xFF404040); + HorizLineRender(Bound.Left+1, Bound.Top+1, Bound.Width-2, 0xFF404040); + + VertLineRender(Bound.Right-1, Bound.Top+1, Bound.Height-2, 0xFFD4D0C8); + HorizLineRender(Bound.Left+1, Bound.Bottom-1, Bound.Width-2, 0xFFD4D0C8); + + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFFFFFFFF); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFFFFFFFF); + }else + if(BevelOuter == bvRaised){ + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + } + + //Fill Rect Box + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); + + if(Caption.Visible)Caption.Show(); + for(i=0; i<24; i++)if(SText[i].Visible)SText[i].Show(); + for(i=0; i<24; i++)if(Edit[i].Visible)Edit[i].Show(); + for(i=0; i<24; i++)if(Btn[i].Visible)Btn[i].Show(); +} + +void TCtlPanel1::DrawVertScrollBar(void) +{ + +} + +void TCtlPanel1::Show(void) +{ + DrawSelf(); +} + +void TCtlPanel1::ReDrawItems(void) +{ + unsigned int i; + if(Caption.Visible)Caption.Show(); + for(i=0; i<24; i++)if(SText[i].Visible)SText[i].Show(); + for(i=0; i<24; i++)if(Edit[i].Visible)Edit[i].Show(); + for(i=0; i<24; i++)if(Btn[i].Visible)Btn[i].Show(); +} + +void TCtlPanel1::ReDrawEdit(void) +{ + unsigned int i; + for(i=0; i<24; i++)if(Edit[i].Visible)Edit[i].Show(); +} + +void TCtlPanel1::SetEditMode(unsigned int aMode) +{ + +} + +void TCtlPanel1::Clear(void) +{ + +} diff --git a/MyCode/Gui/CtlPanel1.h b/MyCode/Gui/CtlPanel1.h new file mode 100644 index 0000000..67a9c5d --- /dev/null +++ b/MyCode/Gui/CtlPanel1.h @@ -0,0 +1,86 @@ +#ifndef CTLPANEL1_H_ +#define CTLPANEL1_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" +#include "TButton.h" + +//aPanel with Caption, StaticText, Btn, Edit, +class TCtlPanel1{ + private: + int FontSize; + int FontHeight; + int EditMode; + TBvStyle BevelOuter; + struct{ + u16 Width; + unsigned int Color; + }Border; + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + public: + TStaticText Caption; + TStaticText SText[24]; + TButton Btn[24]; + TEdit Edit[24]; + TButton BtnSaveReturn; + TButton BtnCancel; + TButton BtnPrev; + TButton BtnNext; + + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + unsigned char ShowWhat; + + private: + + public: + TCtlPanel1(){}; + TCtlPanel1(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aColor, aBevelOuter); + } + void Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter); + void DrawSelf(void); + void DrawVertScrollBar(void); + void Show(void); + void ReDrawItems(void); + void ReDrawEdit(void); + + void SetEditMode(unsigned int aMode); + + void Clear(void); + void FullRePaint(void); + void RePaint(void); +}; + + + + + + +#endif + + diff --git a/MyCode/Gui/CtlPanelLite.cpp b/MyCode/Gui/CtlPanelLite.cpp new file mode 100644 index 0000000..40591ee --- /dev/null +++ b/MyCode/Gui/CtlPanelLite.cpp @@ -0,0 +1,192 @@ +#include "CtlPanelLite.h" +#include "Runtime.h" + + +void TCtlPanelLite::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + unsigned short Left,Right,Top,Bottom,i; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + Color = aColor; + BevelOuter = aBevelOuter; + if(BevelOuter == bvRaised){ + Left = Bound.Left + 1; + Right = Bound.Right - 2; + Top = Bound.Top + 1; + Bottom = Bound.Bottom - 2; + }else{ + Left = Bound.Left + 2; + Right = Bound.Right - 2; + Top = Bound.Top + 2; + Bottom = Bound.Bottom - 2; + } + + Caption.Init(Left, Top, Right-Left+1, 32, 0, 0, clNearWhite, clMedBlue); + Content.Set(Left,Top+32,Right,Bottom); + VScrollBarBox.Set(780,80,800,400); + VScrollBar.Color = 0xFF007777; + FixColColor = clMaroon; + FixColTextColor = clNearWhite; + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Caption.Visible = 0; + for(i=0;i<4;i++){ + SText[i].Enable = 0; + Edit[i].Enable = 0; + Btn[i].Enable = 0; + + SText[i].Visible = 0; + Edit[i].Visible = 0; + Btn[i].Visible = 0; + + SText[i].Selected = 0; + Edit[i].Selected = 0; + Btn[i].Selected = 0; + } +} + + +void TCtlPanelLite::DrawSelf(void) +{ + unsigned int i; + if (BevelOuter == bvLowered){ + VertLineRender(Bound.Left, Bound.Top, Bound.Height-1, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width-1, 0xFF808080); + + VertLineRender(Bound.Left+1, Bound.Top+1, Bound.Height-2, 0xFF404040); + HorizLineRender(Bound.Left+1, Bound.Top+1, Bound.Width-2, 0xFF404040); + + VertLineRender(Bound.Right-1, Bound.Top+1, Bound.Height-2, 0xFFD4D0C8); + HorizLineRender(Bound.Left+1, Bound.Bottom-1, Bound.Width-2, 0xFFD4D0C8); + + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFFFFFFFF); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFFFFFFFF); + }else + if(BevelOuter == bvRaised){ + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + } + + //Fill Rect Box + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); + + if(Caption.Visible)Caption.Show(); + for(i=0; i<4; i++)if(SText[i].Visible)SText[i].Show(); + for(i=0; i<4; i++)if(Edit[i].Visible)Edit[i].Show(); + for(i=0; i<4; i++)if(Btn[i].Visible)Btn[i].Show(); +} + +void TCtlPanelLite::DrawVertScrollBar(void) +{ + +} + +void TCtlPanelLite::Show(void) +{ + DrawSelf(); +} + +void TCtlPanelLite::ReDrawItems(void) +{ + unsigned int i; + if(Caption.Visible)Caption.Show(); + for(i=0; i<4; i++)if(SText[i].Visible)SText[i].Show(); + for(i=0; i<4; i++)if(Edit[i].Visible)Edit[i].Show(); + for(i=0; i<4; i++)if(Btn[i].Visible)Btn[i].Show(); +} + +void TCtlPanelLite::ReDrawEdit(void) +{ + unsigned int i; + for(i=0; i<4; i++)if(Edit[i].Visible)Edit[i].Show(); +} + +void TCtlPanelLite::SetEditMode(unsigned int aMode) +{ + +} + +void TCtlPanelLite::Clear(void) +{ + +} + +void TCtlPanelLite::GuiLoginIIShow() +{ + Init(150, 120, 500, 150, 0, 0, clFrmFace, bvRaised); + Caption.Visible = 1; + if(LanguageEnCn==0)Caption.SetText("II级登录,请输入密码", 24); + else Caption.SetText("Level 2 Permission Password", 24); + Caption.TextColor = clNearWhite; + Edit[0].Init(30, 60, 446, 32, 150, 120, 2 , clFrmFace); + DrawSelf(); + ShowWhat = dGuiLoginII; + Edit[0].TextClear(); + Edit[0].Enable = 1; + Edit[0].Selected = 1; + Edit[0].SetMaxLen(16); + Edit[0].SetTextShowMaskByAsterisk(); + Edit[0].Show(); +} + +void TCtlPanelLite::GuiLoginIIIShow() +{ + Init(150, 120, 500, 150, 0, 0, clFrmFace, bvRaised); + Caption.Visible = 1; + if(LanguageEnCn==0)Caption.SetText("III级登录,请输入密码", 24); + else Caption.SetText("Level 3 Permission Password", 24); + Caption.TextColor = clNearWhite; + Edit[0].Init(30, 60, 446, 32, 150, 120, 2 , clFrmFace); + DrawSelf(); + ShowWhat = dGuiLoginIII; + Edit[0].TextClear(); + Edit[0].Enable = 1; + Edit[0].Selected = 1; + Edit[0].SetMaxLen(16); + Edit[0].SetTextShowMaskByAsterisk(); + Edit[0].Show(); +} + +void TCtlPanelLite::GuiLoginPasswdErrShow() +{ + + if(LanguageEnCn==0)Caption.SetText("密码错误 !", 24); + else Caption.SetText("Incorrect Password", 24); + Caption.TextColor = clRed; + Caption.Show(); +} + +TGuiMsgReturn TCtlPanelLite::GuiLoginII_KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + Edit[0].KeyIn(aKey); + if(aKey == VK_EXECUTE){ + //go anyway + if(1){ + aGMR = guiMsgOkAndReturn; + } + } + if(aKey == VK_RETURN)aGMR = guiMsgReturn; + return aGMR; +} + +TGuiMsgReturn TCtlPanelLite::GuiLoginIII_KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + Edit[0].KeyIn(aKey); + if(aKey == VK_EXECUTE){ + //go anyway + if(1){ + aGMR = guiMsgOkAndReturn; + } + } + if(aKey == VK_RETURN)aGMR = guiMsgReturn; + return aGMR; +} + + diff --git a/MyCode/Gui/CtlPanelLite.h b/MyCode/Gui/CtlPanelLite.h new file mode 100644 index 0000000..9a99dc8 --- /dev/null +++ b/MyCode/Gui/CtlPanelLite.h @@ -0,0 +1,105 @@ +#ifndef CTLPANELLITE_H_ +#define CTLPANELLITE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TButton.h" +#include "TEdit.h" + +#define dGuiLoginII 0x00 +#define dGuiLogoutII 0x01 +#define dGuiLoginIII 0x02 +#define dGuiLogoutIII 0x03 +#define dGuiQueryDevice 0x10 +#define dGuiQueryAddr 0x11 +#define dGuiQueryMask 0x12 +#define dGuiQueryConfig 0x13 +#define dGuiQueryInterLink 0x14 +#define dGuiQueryHandpadInterLink 0x15 +#define dGuiNetwork 0x16 +#define dGuiHistoryInfAll 0x20 +#define dGuiHistoryFireAlarm 0x21 +#define dGuiHistoryInterLink 0x22 +#define dGuiHistoryFault 0x23 +#define dGuiHistoryOperating 0x24 +#define dGuiHistorySuper 0x25 + +//aPanel with Caption, StaticText, Btn, Edit, +class TCtlPanelLite{ + private: + int FontSize; + int FontHeight; + int EditMode; + TBvStyle BevelOuter; + struct{ + u16 Width; + unsigned int Color; + }Border; + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + public: + TStaticText Caption; + TStaticText SText[4]; + TButton Btn[4]; + TEdit Edit[4]; + TButton BtnSaveReturn; + TButton BtnCancel; + TButton BtnPrev; + TButton BtnNext; + + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + unsigned char ShowWhat; + + private: + + public: + TCtlPanelLite(){}; + TCtlPanelLite(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aColor, aBevelOuter); + } + void Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter); + void DrawSelf(void); + void DrawVertScrollBar(void); + void Show(void); + void ReDrawItems(void); + void ReDrawEdit(void); + + void SetEditMode(unsigned int aMode); + + void Clear(void); + void FullRePaint(void); + void RePaint(void); + + void GuiLoginIIShow(); + void GuiLoginIIIShow(); + void GuiLoginPasswdErrShow(); + + TGuiMsgReturn GuiLoginII_KeyIn(unsigned char aKey); + TGuiMsgReturn GuiLoginIII_KeyIn(unsigned char aKey); +}; + + +#endif diff --git a/MyCode/Gui/DateTImeSet.cpp b/MyCode/Gui/DateTImeSet.cpp new file mode 100644 index 0000000..34c912e --- /dev/null +++ b/MyCode/Gui/DateTImeSet.cpp @@ -0,0 +1,658 @@ +#include "DateTimeSet.h" +#include "XBox.h" +#include "Runtime.h" +#include "CnCpp.h" + + + +static constexpr short svGridX_Date[4] = { +42, +100, +160, +600 +}; + +static constexpr short svGridX_Time[4] = { +16, +64 , +106 , +600 +}; + +void TDateTimeCfg::Init() +{ + IsShow =0; + IsEditing = 0; + OpaState =0; + SlaveDateTimeHasBeenSet = 0; + + Tag.Group = 0; + Tag.Inx0 = 0; + Tag.Inx1 = 0; + + vtValue[0] = 0; + vtValue[1] = 0; + vtValue[2] = 0; + vtValue[3] = 0; + vtValue[4] = 0; + vtValue[5] = 0; +} + +void TDateTimeCfg::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDateTimeCfg::DrawTextFirst() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "本机->日期时间 "); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +10, clNearWhite, "日期"); + //TextRender_string24(Lv.Grid.Left[0] + 10+100, Lv.Grid.Top[0] +10, clRed, "注意:更改日期到上次维保事件之前会清除维保事件"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +10, clNearWhite, "时间"); + TextRender_string24(Lv.Grid.Left[0] +12, Lv.Grid.Top[0] +46, clNearWhite, "20"); + TextRender_string24(Lv.Grid.Left[0] +72, Lv.Grid.Top[0] +46, clNearWhite, "年"); + TextRender_string24(Lv.Grid.Left[0] +128, Lv.Grid.Top[0] +46, clNearWhite, "月"); + TextRender_string24(Lv.Grid.Left[0] +198, Lv.Grid.Top[0] +46, clNearWhite, "日"); + TextRender_string24(Lv.Grid.Left[1] +46, Lv.Grid.Top[1] +46, clNearWhite, ":"); + TextRender_string24(Lv.Grid.Left[1] +88, Lv.Grid.Top[1] +46, clNearWhite, ":"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 12, 122, 40, 7, clDeepBlue, "网络校时", 14, clNearWhite); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Local->Date Time"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +10, clNearWhite, "Date"); + //TextRender_string24(Lv.Grid.Left[0] + 10+100, Lv.Grid.Top[0] +10, clRed, "注意:更改日期到上次维保事件之前会清除维保事件"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +10, clNearWhite, "Time"); + TextRender_string24(Lv.Grid.Left[0] +12, Lv.Grid.Top[0] +46, clNearWhite, "20"); + TextRender_string24(Lv.Grid.Left[0] +72, Lv.Grid.Top[0] +46, clNearWhite, "YY"); + TextRender_string24(Lv.Grid.Left[0] +128, Lv.Grid.Top[0] +46, clNearWhite, "MM"); + TextRender_string24(Lv.Grid.Left[0] +198, Lv.Grid.Top[0] +46, clNearWhite, "DD"); + TextRender_string24(Lv.Grid.Left[1] +46, Lv.Grid.Top[1] +46, clNearWhite, ":"); + TextRender_string24(Lv.Grid.Left[1] +88, Lv.Grid.Top[1] +46, clNearWhite, ":"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 12, 122, 40, 7, clDeepBlue, "Network ", 14, clNearWhite); + } +} + +void TDateTimeCfg::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; i0){ + RestoreFromEdit(); + Tag.Inx0--; + SetEditStart(); + } + }else{ + vEdit.KeyIn(VK_LEFT); + vEdit.Show(); + vEdit.ShowCursor(); + } + } + }else + if(aKey == VK_RIGHT){ + if(Tag.Inx0 <3){ + if(vEdit.Pst >0){ + if(Tag.Inx0 <2){ + RestoreFromEdit(); + Tag.Inx0++; + SetEditStart(); + } + }else{ + vEdit.KeyIn(VK_RIGHT); + vEdit.Show(); + vEdit.ShowCursor(); + } + } + }else + if(aKey == VK_DOWN){ + RestoreFromEdit(); + Tag.Group =1; + Tag.Inx1 = Tag.Inx0; + if(Tag.Inx1 > 2)Tag.Inx1 = 0; + SetEditStart(); + }else + if(aKey == VK_EXECUTE){ + unsigned int tToClear, ClearOk; + CombDt(); + tToClear = Check4ModifiedDate2ClearLastMaintain(vtValue[0], vtValue[1], vtValue[2]); + DataTimeSet(vtValue[0], vtValue[1], vtValue[2], vtValue[3], vtValue[4] ,vtValue[5], 1); //aWk 1..7 + Record.OperateAdd_CfgDateTime(vtValue[0], vtValue[1], vtValue[2], vtValue[3], vtValue[4] ,vtValue[5]);if(MainCtl.fData.Split.NetworkMode == 1){ + if(MainCtl.fData.Split.NetworkMode == 1) + ProtoC2C.DateTimeSet(); + } + NoOpa =0; + if(tToClear == 0){ + ShowSta(1); + }else{ + LastMaintain.Day = 0x02; + LastMaintain.Month = 0x01; + LastMaintain.Year = 0x21; + LastMaintain.Cent = 0x20; + ClearOk = Record.WriteLastMaintainTime(); + if(ClearOk == 0){ + //Clear Maintain OK + ShowSta(11); + }else{ + //Clear Maintain Fail + ShowSta(21); + } + } + Check4MaintainToShow(); + StateBarReflashMaintain(); + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + }else + if(Tag.Group == 1){ + if(aKey == VK_LEFT){ + if(Tag.Inx1 <3){ + if(vEdit.Pst <0){ + if(Tag.Inx1 >0){ + RestoreFromEdit(); + Tag.Inx1--; + SetEditStart(); + } + }else{ + vEdit.KeyIn(VK_LEFT); + vEdit.Show(); + vEdit.ShowCursor(); + } + } + }else + if(aKey == VK_RIGHT){ + if(Tag.Inx1 <3){ + if(vEdit.Pst >0){ + if(Tag.Inx1 <2){ + RestoreFromEdit(); + Tag.Inx1++; + SetEditStart(); + } + }else{ + vEdit.KeyIn(VK_RIGHT); + vEdit.Show(); + vEdit.ShowCursor(); + } + } + }else + if(aKey == VK_UP){ + RestoreFromEdit(); + Tag.Group =0; + Tag.Inx0 = Tag.Inx1; + if(Tag.Inx0 > 2)Tag.Inx0 = 0; + SetEditStart(); + }else + if(aKey == VK_DOWN){ + RestoreFromEdit(); + Tag.Group =2; + DrawNwSetDateTime(1); + }else + if(aKey == VK_EXECUTE){ + unsigned int tToClear, ClearOk; + CombDt(); + tToClear = Check4ModifiedDate2ClearLastMaintain(vtValue[0], vtValue[1], vtValue[2]); + DataTimeSet(vtValue[0], vtValue[1], vtValue[2], vtValue[3], vtValue[4] ,vtValue[5], 1); //aWk 1..7 + Record.OperateAdd_CfgDateTime(vtValue[0], vtValue[1], vtValue[2], vtValue[3], vtValue[4] ,vtValue[5]); + FecStd.TriggerCmd04SyncTime(); + if(MainCtl.fData.Split.NetworkMode == 1){ + ProtoC2C.DateTimeSet(); + } + NoOpa =0; + if(tToClear == 0){ + ShowSta(1); + }else{ + LastMaintain.Day = 0x02; + LastMaintain.Month = 0x01; + LastMaintain.Year = 0x21; + LastMaintain.Cent = 0x20; + ClearOk = Record.WriteLastMaintainTime(); + if(ClearOk == 0){ + //Clear Maintain OK + ShowSta(11); + }else{ + //Clear Maintain Fail + ShowSta(21); + } + } + Check4MaintainToShow(); + StateBarReflashMaintain(); + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + }else + if(Tag.Group == 2){ + if(aKey == VK_UP){ + DrawNwSetDateTime(0); + Tag.Group =1; + if(Tag.Inx1 > 2)Tag.Inx1 = 0; + SetEditStart(); + }else + if(aKey == VK_EXECUTE){ + //Set DateTime + if(MainCtl.fData.Split.NetworkMode == 1){ + ProtoC2C.DateTimeSet(); + NoOpa =0; + ShowSta(2); + }else + if(MainCtl.fData.Split.NetworkMode == 2 ){ + //Req DateTime + ProtoC2C.DateTimeReq(); + SlaveDateTimeHasBeenSet = 0; + NoOpa =0; + ShowSta(3); + }else{ + NoOpa =0; + ShowSta(5); + } + } + } + + if(NoOpa)ShowSta(0); + + if(aKey == VK_RETURN){ + IsShow = 0; + aMsg = guiMsgReturn; + } + return aMsg; +} + +void TDateTimeCfg::CombDt() +{ + unsigned char aC, c, aVal, aMonDaysCount; + if(Tag.Group == 0){ + if(Tag.Inx0 <3){ + vtText[Tag.Inx0][0] = vEdit.Str.Text[0]; + vtText[Tag.Inx0][1] = vEdit.Str.Text[1]; + vtText[Tag.Inx0][2] = 0; + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 <3){ + vtText[Tag.Inx1 +3][0] = vEdit.Str.Text[0]; + vtText[Tag.Inx1 +3][1] = vEdit.Str.Text[1]; + vtText[Tag.Inx1 +3][2] = 0; + } + } + + for(c=0; c<6;c++){ + if( (vtText[c][0] < '0') || (vtText[c][0] > '9') ) { + aVal = 0; + }else{ + aVal = (vtText[c][0] - '0' ) % 10; + } + DecVal[c] = aVal * 10; + aC = aVal << 4; + if( (vtText[c][1] < '0') || (vtText[c][1] > '9') ){ + aVal = 0; + }else{ + aVal = (vtText[c][1] - '0' ) % 10; + } + DecVal[c] += aVal; + vtValue[c] = aC + aVal; + } + if(DecVal[0] > 99){ + DecVal[0] = 24; + vtValue[0] = 0x24; + } + if( (DecVal[1] > 12) || (DecVal[1] == 0) ){ + DecVal[1] = 1; + vtValue[1] = 1; + } + if(DecVal[1] == 2){ + if((DecVal[0] % 4) == 0){ + aMonDaysCount = 29; + }else{ + aMonDaysCount = 28; + } + }else{ + aMonDaysCount = TDateTime::MonthDaysNotLeapYear[DecVal[1] -1]; + } + if( (DecVal[2] > aMonDaysCount) || (DecVal[2] == 0) ){ + DecVal[2] = 1; + vtValue[2] = 1; + } + if(DecVal[3] > 23){ + DecVal[3] = 0; + vtValue[3] = 0; + } + if(DecVal[4] > 59){ + DecVal[4] = 0; + vtValue[4] = 0; + } + + if(DecVal[5] > 59){ + DecVal[5] = 0; + vtValue[5] = 0; + } +} + + + + + + diff --git a/MyCode/Gui/DateTimeSet.h b/MyCode/Gui/DateTimeSet.h new file mode 100644 index 0000000..df122ad --- /dev/null +++ b/MyCode/Gui/DateTimeSet.h @@ -0,0 +1,104 @@ +#ifndef DATETIMECFG_H_ +#define DATETIMECFG_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" + +class TDateTimeCfg{ + public: + static constexpr unsigned short hList[12] = {80,80,60,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + unsigned char IsShow; + unsigned char OpaState; + unsigned char SlaveDateTimeHasBeenSet; + unsigned char Dump0; + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Inx2; + }Tag; + + TRect Bound; + TRect BoundCaption; + TRect Content; + + unsigned char vtValue[8]; + unsigned char DecVal[8]; + unsigned int IsEditing; + + char vtText[6][4]; + char Text[16]; + class TEdit vEdit; + public: + TDateTimeCfg(){}; + void Init(); + void RenderBackGround(void); + void DrawSelf(); + void DrawBoxTimeOutLine(); + void DrawBoxTime(); + void DrawBoxTimeString(); + void DrawDateEntry(); + void DrawTimeEntry(); + void DrawSaveButton(); + void Show(); + void FullRedraw(int Prm); + void DrawTextFirst(); + + void ShowSta(); + void ShowSta(unsigned char aSta); + + void LoadDateTime(); + + void DrawNwSetDateTime(int Selected); + + void SetEditStart(void); + void RestoreFromEdit(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void CombDt(); + + int ExtRequst(unsigned char Prm){IsShow =0; return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/DescpWrite.cpp b/MyCode/Gui/DescpWrite.cpp new file mode 100644 index 0000000..d8b86e8 --- /dev/null +++ b/MyCode/Gui/DescpWrite.cpp @@ -0,0 +1,1394 @@ +#include "RuntimeData.h" +#include "DescpWrite.h" +#include "DevMask.h" +#include "EncodeConv.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +//#define dAddr_DescpBuf dAddrSdRam_Commom +TReadWriteData TDescpWrite::ReadWriteData; + +void TDescpWrite::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->注释编辑"); + TextRender_string24(Lv.Grid.Left[0] + 254, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "地址号"); + + TextRender_string24(Lv.Grid.Left[0] + 138, Lv.Grid.Top[0] + 38, clNearWhite, "-"); + TextRender_string24(Lv.Grid.Left[0] + 370, Lv.Grid.Top[0] + 6, clNearWhite, "起始地址注释信息:(设置键编辑)"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "回路号"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 6, clNearWhite, "执行操作"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +90, Lv.Grid.Top[1] + 36, 68, 30, 5, clNearWhite, "保存", 10, clNearBlack); + + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] + 6, clNearWhite, "超纲汉字输入 Unicode"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Device Annotation"); + TextRender_string24(Lv.Grid.Left[0] + 254, Lv.Grid.Top[0] +6, clNearWhite, " Local"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "Addr"); + TextRender_string24(Lv.Grid.Left[0] + 138, Lv.Grid.Top[0] + 38, clNearWhite, "-"); + TextRender_string24(Lv.Grid.Left[0] + 370, Lv.Grid.Top[0] + 6, clNearWhite, "Begin Addr Note; Key 'Set' To Edit"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "LoopID"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 6, clNearWhite, "Operation"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +90, Lv.Grid.Top[1] + 36, 68, 30, 5, clNearWhite, "Save", 10, clNearBlack); + + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] + 6, clNearWhite, "Enter Unicode16 Code"); + } +} + +void TDescpWrite::Init() +{ + IsShow = 0; + IsEditting = 0; + IsExtInput = 1; + IsShowPresetList = 0; + IsPermission =0; + PermissionCmd =0; + TextCodeOk =0; + + Path0 = 1; + Path1Start = 1; + Path1End = 2; + + Tag.Reset(); + TagPreSetList.Reset(); + TagPanel.Reset(); + + TextCp936[0] = '\0'; + TextCp936[1] = '\0'; + + Ava = 0; + for(int i=0; i<8; i++){ + TextList[i][32] = 0; + } +} + +void TDescpWrite::PreLoadReset() +{ + int x; + for(int i=0; i<8; i++){ + for(x=0; x<36; x++) + TextList[i][x] = 0; + + } +} + +void TDescpWrite::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDescpWrite::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TDescpWrite::RenderContent(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TDescpWrite::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + TextDigitRender2Right24(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + + //IList->STextCtlNum.Init(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 6, 120, 30, 0, 0, clNearWhite, ItemColor); + IList->EditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 2, 50, 30, 0, 0, 1, clNearWhite); + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + IList->Edit[0].Init(Lv.Grid.Left[0] + 152, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + IList->EditDescpShow.Init(Lv.Grid.Left[0] + 390, Lv.Grid.Top[0] + 36, 400, 30, 0, 0, 1, clNearWhite); + + //IList->STextCtlNum.Enable = 1; + //IList->STextCtlNum.Visible =1; + + IList->EditPortNum.SetMaxLen(2); + IList->EditAddrNum.SetMaxLen(3); + IList->Edit[0].SetMaxLen(3); + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible = 1; + IList->EditAddrNum.Enable = 1; + IList->EditAddrNum.Visible = 1; + IList->Edit[0].Enable = 1; + IList->Edit[0].Visible = 1; + IList->EditDescpShow.Enable = 1; + IList->EditDescpShow.Visible = 1; + + for(int i=2; i<5; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + IList->Edit[1].Init(Lv.Grid.Left[2] + 90, Lv.Grid.Top[2] + 36, 106, 30, 0, 0, 1, clNearWhite); + IList->Edit[1].TextClear(); + IList->Edit[1].SetMaxLen(8); + IList->Edit[1].Enable = 1; + IList->Edit[1].Visible = 1; + + //IList->STextCtlNum.Show(); + + IList->EditPortNum.SetText("01", 24); + IList->EditAddrNum.SetText("001", 24); + IList->Edit[0].SetText("002", 24); + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->Edit[0].Show(); + IList->EditDescpShow.Init(Lv.Grid.Left[0] + 390, Lv.Grid.Top[0] + 36, 400, 30, 0, 0, 1, clNearWhite); + + FirstLoadText2Edit(); + IList->EditDescpShow.Show(); + + DrawFixText(); + + Path0Ava =1; + Path1StartAva =1; + Path1EndAva =1; + + Tag.Inx = 1; + Check4Selected(); + + DrawPreSetList(); + DrawPreSetListTip(); +} + + + +void TDescpWrite::Show() +{ + IsShow = 1; + DrawSelf(); + + +} + +void TDescpWrite::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + for(int i=0; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawCommonByExReturn(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDescpWrite::DrawCommonByExReturn() +{ + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + TextDigitRender2Right24(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + + //IList->STextCtlNum.Init(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 6, 120, 30, 0, 0, clNearWhite, ItemColor); + TextRender_string24(Lv.Grid.Left[0] + 138, Lv.Grid.Top[0] + 38, clNearWhite, "-"); + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + DrawFixText(); + + //IList->STextCtlNum.Show(); + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->Edit[0].Show(); + IList->EditDescpShow.Show(); + + Check4Selected(); + + DrawPreSetList(); + //DrawPreSetListTip(); +} + +void TDescpWrite::FirstLoadText2Edit() +{ + unsigned int tAddr; + + tAddr = dAddrSdRam_Descp + ((Path0-1) * 256 * 32) + ( (Path1Start-1) * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + IList->EditDescpShow.SetPstTail(); +} + +void TDescpWrite::ReLoadText2Edit() +{ + FirstLoadText2Edit(); +} + +void TDescpWrite::LoadText2Edit() +{ + unsigned int tAddr; + int NewP1Start, NewP1End, AddrCnt; + + if(Path1End < dEP_MAX_COUNT_PER_PORT){ + AddrCnt = Path1End - Path1Start +1; + NewP1Start = Path1End +1; + NewP1End = NewP1Start + AddrCnt -1; + if(NewP1End > dEP_MAX_COUNT_PER_PORT)NewP1End = dEP_MAX_COUNT_PER_PORT; + + Path1Start = static_cast(NewP1Start); + Path1End = static_cast(NewP1End); + + IList->EditAddrNum.Str.FromUInt3Dg(Path1Start); + IList->Edit[0].Str.FromUInt3Dg(Path1End); + IList->EditAddrNum.SetPstTail(); + IList->Edit[0].SetPstTail(); + IList->EditAddrNum.Show(); + IList->Edit[0].Show(); + + tAddr = dAddrSdRam_Descp + ((Path0-1) * 256 * 32) + ( (Path1Start-1) * 32); + if(*(volatile unsigned char *)(tAddr) != '\0'){ + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + } + }else{ + tAddr = dAddrSdRam_Descp + ((Path0-1) * 256 * 32) + ( (Path1Start-1) * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + } + + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + IList->EditDescpShow.SetPstTail(); +} + +void TDescpWrite::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickInit(x,y,aW,aH,0,0,clMoneyGreen, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearWhite,clBlue); + if(LanguageEnCn==0){ + aPanel->Caption.SetText("按中/EN键切换输入法,设置键更改,返回键放弃更改并返回",24); + }else{ + aPanel->Caption.SetText("Key'中/EN' Switch Input Method,Key 'Set' To Edit",24); + } + aPanel->Caption.Enable = 1; + aPanel->Caption.Visible = 1; + + aPanel->SText[0].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0){ + TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr("Enter Number Keys", aPanel->SText[0].Text); + } + aPanel->SText[0].Enable = 1; + aPanel->SText[0].Visible = 1; + + aPanel->SText[1].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0){ + TMyString::sFromStr("装载预设内容", aPanel->SText[1].Text); + }else{ + TMyString::sFromStr("Load From PreLoad", aPanel->SText[1].Text); + } + aPanel->SText[1].Enable = 1; + aPanel->SText[1].Visible = 1; + + aPanel->SText[2].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0){ + TMyString::sFromStr("保存到预设内容", aPanel->SText[2].Text); + }else{ + TMyString::sFromStr("Save To PreLoad", aPanel->SText[2].Text); + } + aPanel->SText[2].Enable = 1; + aPanel->SText[2].Visible = 1; + + aPanel->Edit[ 0].Init(10,40,420,30,x,y,1,clNearBlack); + aPanel->Edit[ 0].Str.FromStr("gggggg"); + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 1; + } + + aPanel->Edit[ 1].Init(10,80,36,30,x,y,1,clNearBlack); + aPanel->Edit[ 1].Str.FromStr("1"); + for(i=1; i<2;i++){ + //aPanel->Edit[i].Enable = 1; + //aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(1); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 0; + } + + aPanel->Edit[ 2].Init(10,120,36,30,x,y,1,clNearBlack); + aPanel->Edit[ 2].Str.FromStr("1"); + for(i=1; i<2;i++){ + //aPanel->Edit[i].Enable = 1; + //aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(1); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 0; + } + if(EditWhat>7) + aPanel->Edit[0].Str.FromStr(IList->EditDescpShow.Str.Text); + else + aPanel->Edit[0].Str.FromStr(TextList[EditWhat]); + aPanel->Edit[0].SetPstTail(); + + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + //aPanel->SText[1].Show(); + //aPanel->SText[2].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + //aPanel->Edit[1].Show(); + //aPanel->Edit[2].Show(); + + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn==0)TMyString::sFromStr("请根据以下输入法提示输入", aPanel->SText[0].Text); + else TMyString::sFromStr("Pay Attention To The Tip", aPanel->SText[0].Text); + aPanel->SText[0].Show(); + IsExtInput = 1; + +} + +void TDescpWrite::ClearSelected(void) +{ + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 4: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 5: + char *tText; + if(LanguageEnCn==0)tText="保存";else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +90, Lv.Grid.Top[1] + 36, 68, 30, 5, clNearWhite, tText, 10, clNearBlack); + break; + case 6: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + } +} + +void TDescpWrite::Check4Selected(void) +{ + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 4: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.CorrectPst(); + IList->EditDescpShow.Show(); + IList->EditDescpShow.ShowCursor(); + break; + case 5: + char *tText; + if(LanguageEnCn==0)tText="保存";else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +90, Lv.Grid.Top[1] + 36, 68, 30, 5, clBlue, tText, 10, clNearWhite); + break; + case 6: + IList->Edit[1].Selected = 1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + } +} +/* +void TDescpWrite::LoadDescp(int aP0, int aP1, char *p) +{ + unsigned int aAddr, i; + unsigned int p0, p1; + + if(aP0 <1)return; + if(aP1 <1)return; + + if(aP0 <= dPORT_MAX_COUNT){ + p0 = aP0-1; + p1 = aP1-1; + aAddr = dAddrSdRam_Descp + (p0 * 8192) + (p1*32); + for(i=0; i<32; i++){ + *p = *(volatile unsigned char *)(aAddr + i); + p++; + } + *p = '\0'; + aPanel->Edit[2].SetPstTail(); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if(aP1 <= dDIRECTCTL_KEY_MAX_COUNT){ + p0 = aP0 - dADDR_DIRECTPAD_START; + p1 = (p0 * dDIRECTCTL_KEY_MAX_COUNT) + (aP1); + p0 = dPORT_MAX_COUNT; + aAddr = dAddrSdRam_Descp + (p0 * 8192) + (p1*32); + for(i=0; i<32; i++){ + *p = *(volatile unsigned char *)(aAddr + i); + p++; + } + *p = '\0'; + aPanel->Edit[2].SetPstTail(); + } + } +} +*/ + +void TDescpWrite::sRestoreDescp(int aP0, int aP1, char *p) +{ + unsigned int aAddr, i; + unsigned int p0, p1; + + if(aP0 <1)return; + if(aP1 <1)return; + + if(aP0 <= dPORT_MAX_COUNT){ + p0 = aP0-1; + p1 = aP1-1; + aAddr = dAddrSdRam_Descp + (p0 * 8192) + (p1*32); + for(i=0; i<32; i++){ + *(volatile unsigned char *)(aAddr + i) = *p; + p++; + } + *p = '\0'; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if(aP1 <= dDIRECTCTL_KEY_MAX_COUNT){ + p0 = aP0 - dADDR_DIRECTPAD_START; + p1 = (p0 * dDIRECTCTL_KEY_MAX_COUNT) + (aP1); + p0 = dPORT_MAX_COUNT; + aAddr = dAddrSdRam_Descp + (p0 * 8192) + (p1*32); + for(i=0; i<32; i++){ + *(volatile unsigned char *)(aAddr + i) = *p; + p++; + } + *p = '\0'; + } + } +} + +void TDescpWrite::AnalyTextWrite() +{ + int i, FixLen, LastCharPst, Cnt, FirstZeroPst; + /* + char TextNum[16]; + for(i=0; i<36; i++)Text2WriteFix[i] = 0; + for(i=0; i<16; i++)TextNum[i] = 0; + Num2WriteCount = 0; + LastCharPst =0; + FirstZeroPst = 31; + for(i=0; i<32; i++){ + if(IList->EditDescpShow.Str.Text[i] == 0){ + FirstZeroPst = i; + break; + } + } + for(i=FirstZeroPst; i>-1; i--){ + if(IList->EditDescpShow.Str.Text[i] == 0)continue; + if( (IList->EditDescpShow.Str.Text[i] >= '0') && (IList->EditDescpShow.Str.Text[i] <= '9')){ + Num2WriteCount ++; + }else{ + LastCharPst = i; + break; + } + if(Num2WriteCount >7)break; + } + + for(i=0; i<=LastCharPst; i++){ + Text2WriteFix[i] = IList->EditDescpShow.Str.Text[i]; + } + + for(i=LastCharPst+1, Cnt =0; (i<32) && (Cnt<8); i++, Cnt++){ + TextNum[Cnt] = IList->EditDescpShow.Str.Text[i]; + } + + Num2Write = TMyString::sToInteger(TextNum); + if(Num2Write == 0) Num2Write =1; + */ + + + for(i=0; i<32; i++){ + Text2WriteFix[i] = IList->EditDescpShow.Str.Text[i]; + if(Text2WriteFix[i] == '\0')break; + } + Text2WriteFix[32] =0; +} + +void TDescpWrite::FillTextWrite() +{ + int tP0, tStart, tEnd; + int t,i, Cnt; + unsigned int tNum, aAddr; + if(Path0 == 0) return; + if(Path0 > dPORT_MAX_COUNT) return; + if(Path1Start == 0) return; + if(Path1Start > dEP_MAX_COUNT_PER_PORT) return; + if(Path1End == 0) return; + if(Path1End > dEP_MAX_COUNT_PER_PORT) return; + + tP0 = Path0-1; + tStart = Path1Start -1; + tEnd = Path1End -1; + tNum = Num2Write; + + for(t=tStart; t<=tEnd; t++){ + for(i=0; i<48; i++)TextWritting[i] = 0; + TMyString::sFromStr(Text2WriteFix , TextWritting); + //if( (tNum >999'9999) && (Num2WriteCount < 8) )Num2WriteCount =8; + //else if( (tNum > 99'9999) && (Num2WriteCount < 7) )Num2WriteCount =7; + //else if( (tNum > 9'9999) && (Num2WriteCount < 6) )Num2WriteCount =6; + //else if( (tNum > 9999) && (Num2WriteCount < 5) )Num2WriteCount =5; + //else if( (tNum > 999) && (Num2WriteCount < 4) )Num2WriteCount =4; + //else if( (tNum > 99) && (Num2WriteCount < 3) )Num2WriteCount =3; + //else if( (tNum > 9) && (Num2WriteCount < 2) )Num2WriteCount =2; + //else if( ( 1) && (Num2WriteCount < 1) )Num2WriteCount =1; + //TMyString::sAddOn_N_Dg(Num2WriteCount, tNum, TextWritting); + aAddr = dAddrSdRam_Descp + (tP0 * 8192) + (t*32); + for(i=0; i<32; i++){ + *(volatile unsigned char *)(aAddr + i) = TextWritting[i]; + } + //tNum++; + } +} + +void TDescpWrite::EditDescpReturn() +{ + +} + +void TDescpWrite::Redraw4DescpEdit() +{ + IList->EditDescpShow.SetPstTail(); + IList->EditDescpShow.Show(); + + RectFillRender(aPanel->Bound.Left, aPanel->Bound.Top, aPanel->Bound.Right, aPanel->Bound.Bottom, ContentColor); + for(int i=2; iEdit[1].Show(); + if(IsShowPresetList == 0) + Check4Selected(); +} + +void TDescpWrite::PermissionCmdReturnDraw() +{ + DrawPreSetList(); +} + +void TDescpWrite::PermissionCmdGO() +{ + if(PermissionCmd == 1){ + TextRender_string24(Lv.Grid.Left[1] +176,Lv.Grid.Top[1] +4, clNearWhite,ItemColor," "); + AnalyTextWrite(); + FillTextWrite(); + sWrite2Flash(Path0); + if(LanguageEnCn==0) + TextRender_string24(Lv.Grid.Left[1] +176,Lv.Grid.Top[1] +4, clNearWhite,"保存完成"); + else + TextRender_string24(Lv.Grid.Left[1] +176,Lv.Grid.Top[1] +4, clNearWhite,"Saved OK"); + LoadText2Edit(); + IList->EditDescpShow.Show(); + }else + if(PermissionCmd == 2){ + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + EditWhat = 0xFF; + InitPanel(); + IsEditting = 1; + IsExtInput = 1; + } +} + +void TDescpWrite::DrawPreSetList() +{ + int i, x, y; + unsigned int aClr; + if(IsShowPresetList){ + aClr = clBlue; + }else{ + aClr = clMedGray; + } + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + + for(i=0; i<8; i++){ + x = Lv.Panel.Left +6; + y = i * 30 + Lv.Panel.Top +8; + if( (i == TagPreSetList.Inx) && (IsShowPresetList) ){ + aClr = clNearWhite; + }else{ + aClr = clBlack; + } + TextDigitRender1Right24(x,y,aClr, i+1); + TextRender_string24(x+12,y,aClr,"."); + TextRender_string24(x+24,y,aClr,TextList[i]); + } +} + +void TDescpWrite::DrawPreSetListTip() +{ + //注释暂存区:上下键切换条目, + if(LanguageEnCn==0)TextRender_string24(Lv.PanelSmall.Left +6,Lv.PanelSmall.Top +4, clNearWhite, "设置键从编辑栏装载,查询键加载到编辑栏"); + else TextRender_string24(Lv.PanelSmall.Left +6,Lv.PanelSmall.Top +4, clNearWhite, "Key Set Load Form Editor,Key Query SaveTo"); +} + +TGuiMsgReturn TDescpWrite::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + int i,iVal, ava; + unsigned char NewP0; + unsigned char NewP1; + const char *p; + unsigned int Inx; + int HasPrc = 0; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + }else + if(IsEditting){ + const char *p; + if(aKey == dfKEY_SETUP){ + if(EditWhat>7){ + IList->EditDescpShow.Str.FromStr(aPanel->Edit[0].Str.Text); + TMyString::sBrokeFixLen(aPanel->Edit[0].Str.Text, 32); + }else{ + TMyString::sFromStr(aPanel->Edit[0].Str.Text, TextList[EditWhat]); + TMyString::sBrokeFixLen(TextList[EditWhat], 32); + } + Redraw4DescpEdit(); + IsEditting = 0; + }else + if(IsExtInput){ + if(aKey == dfKEY_ENCN){ + CnInput.KeyIn(aKey); + if(0){ + IsExtInput = 0; + CnInput.OverPrint(this->aPanel->Color); + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + if(LanguageEnCn==0)TMyString::sFromStr( "当前快捷输入数字 ", aPanel->SText[0].Text); + else TMyString::sFromStr( "Enter Number Keys", aPanel->SText[0].Text); + aPanel->SText[0].Show(); + } + }else + if(aKey == VK_RETURN){ + //Just return + Redraw4DescpEdit(); + IsEditting = 0; + }else{ + if( (aKey == VK_DELETE) && (CnInput.sEdit.Pst == -1) ){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + }else{ + p = CnInput.KeyIn(aKey); + if(p != nullptr){ + if(CnInput.GotChar[0] != '\0'){ + aPanel->Edit[0].Pst = aPanel->Edit[0].Str.Insert(CnInput.GotChar, aPanel->Edit[0].Pst); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + } + } + } + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + break; + case dfKEY_ENCN: + if(IsExtInput == 0){ + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn==0)TMyString::sFromStr( "当前根据输入法输入", aPanel->SText[0].Text); + else TMyString::sFromStr( "Pay Attention To The Tip", aPanel->SText[0].Text); + aPanel->SText[0].Show(); + } + break; + case VK_EXECUTE: + + break; + case VK_RETURN: + Redraw4DescpEdit(); + IsEditting = 0; + break; + } + } + }else{ + if(IsShowPresetList == 0){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Tag.Inx == 1){ + if( (aKey == VK_RIGHT) && (Path0Ava) ){ + if(IList->EditPortNum.Pst >= IList->EditPortNum.Str.GetEndPst()){ + if(Tag.Inx > Tag.InxMin){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + HasPrc = 1; + } + } + } + if(HasPrc == 0){ + IList->EditPortNum.KeyIn(aKey); + iVal = IList->EditPortNum.Str.ToInteger(); + if( (iVal >0) && (iVal <= dPORT_MAX_COUNT) ){ + IList->EditPortNum.SelectedColor = clBlue; + Path0Ava = 1; + Path0= iVal; + if(Path1StartAva){ + ReLoadText2Edit(); + IList->EditDescpShow.Show(); + } + }else{ + IList->EditPortNum.SelectedColor = clRed; + Path0Ava = 0; + } + IList->EditPortNum.Show(); + } + }else + if(Tag.Inx == 2){ + if( (aKey == VK_RIGHT) && (Path1StartAva) ){ + if(IList->EditAddrNum.Pst >= IList->EditAddrNum.Str.GetEndPst()){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + HasPrc = 1; + } + } + if(HasPrc == 0){ + IList->EditAddrNum.KeyIn(aKey); + iVal = IList->EditAddrNum.Str.ToInteger(); + if( (iVal >0) && (iVal <= dEP_MAX_COUNT_PER_PORT) ){ + IList->EditAddrNum.SelectedColor = clBlue; + Path1StartAva =1; + Path1Start = iVal; + if(Path0Ava){ + ReLoadText2Edit(); + IList->EditDescpShow.Show(); + } + }else{ + IList->EditAddrNum.SelectedColor = clRed; + Path1StartAva =0; + } + IList->EditAddrNum.Show(); + } + }else + if(Tag.Inx == 3){ + if( (aKey == VK_LEFT) && (Path1EndAva) ){ + if(IList->Edit[0].Pst < 0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + HasPrc = 1; + } + }else + if( (aKey == VK_RIGHT) && (Path1EndAva) ){ + if(IList->Edit[0].Pst >= IList->Edit[0].Str.GetEndPst()){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + HasPrc = 1; + } + } + if(HasPrc == 0){ + IList->Edit[0].KeyIn(aKey); + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal >0) && (iVal <= dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[0].SelectedColor = clBlue; + Path1EndAva =1; + Path1End = iVal; + }else{ + IList->Edit[0].SelectedColor = clRed; + Path1EndAva =0; + } + IList->Edit[0].Show(); + } + }else + if(Tag.Inx == 4){ + if( (aKey == VK_LEFT) ){ + if(IList->EditDescpShow.Pst < 0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + HasPrc = 1; + } + } + if(HasPrc == 0){ + IList->EditDescpShow.KeyIn(aKey); + IList->EditDescpShow.Show(); + } + }else + if(Tag.Inx == 6){ + IList->Edit[1].KeyIn(aKey); + IList->Edit[1].Show(); + if(IList->Edit[1].Str.GetLength() > 0){ + UnicodeCode = IList->Edit[1].Str.ToInteger(); + Cp936Code = UnicodeToCP936(UnicodeCode); + TextCodeOk =0; + if(Cp936Code < 32){ + TextCodeOk =1; + }else + if(Cp936Code == 127 ){ + TextCodeOk =1; + }else + if(Cp936Code >127){ + if( (Cp936Code < 0x8140) || (Cp936Code > 0xFEFE) ) { + TextCodeOk =2; + } + } + if(TextCodeOk == 0){ + if(Cp936Code == 0){ + TextCp936[0] =0; + TextCp936[1] =0; + }else{ + if( Cp936Code > 0xFF ){ + if( (Cp936Code & 0x8000) == 0x8000){ + TextCp936[0] = static_cast((Cp936Code >> 8)& 0x00FF); + TextCp936[1] = static_cast(Cp936Code & 0x00FF); + }else{ + TextCp936[0] =0; + TextCp936[1] =0; + } + }else{ + TextCp936[0] = static_cast(Cp936Code & 0x00FF); + TextCp936[1] = 0; + } + TextCp936[2] = 0; + } + TextRender_string24(IList->Edit[1].Bound.Left - 40,IList->Edit[1].Bound.Top +2, ItemColor, ItemColor," "); + TextRender_string24(IList->Edit[1].Bound.Left - 40,IList->Edit[1].Bound.Top +2, clNearWhite,TextCp936); + }else{ + if(TextCodeOk ==1){ + TextCp936[0] = '?'; + TextCp936[1] = 0; + TextRender_string24(IList->Edit[1].Bound.Left - 40,IList->Edit[1].Bound.Top +2, clNearWhite, ItemColor,"? "); + }else{ + TextCp936[0] = '?'; + TextCp936[1] = '?'; + TextRender_string24(IList->Edit[1].Bound.Left - 40,IList->Edit[1].Bound.Top +2, clNearWhite, ItemColor,"??"); + } + TextCp936[2] = 0; + } + TextDigitRender5Right24(IList->Edit[1].Bound.Right +6,IList->Edit[1].Bound.Top +2, clNearWhite,ItemColor,Cp936Code); + }else{ + TextRender_string24(IList->Edit[1].Bound.Left - 40,IList->Edit[1].Bound.Top +2, clNearWhite, ItemColor," "); + TextRender_string24(IList->Edit[1].Bound.Right +6, IList->Edit[1].Bound.Top +2, clNearWhite, ItemColor," "); + TextCp936[0] = '\0'; + TextCp936[1] = '\0'; + } + } + break; + case VK_UP: + if(Tag.Inx > Tag.InxMin){ + //RestoreDescp(Path0, Path1, aPanel->Edit[2].Str.Text); + if(Path0Ava && Path1StartAva && Path1EndAva){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(Tag.Inx <6){ + //RestoreDescp(Path0, Path1, aPanel->Edit[2].Str.Text); + if(Path0Ava && Path1StartAva && Path1EndAva){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + } + break; + case VK_TAB: + IsShowPresetList = 1; + ClearSelected(); + DrawPreSetList(); + break; + case dfKEY_SETUP: + if(Tag.Inx == 4){ + PermissionCmd = 2; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + break; + case VK_EXECUTE: + if(Tag.Inx == 5){ + //Save Here + PermissionCmd = 1; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 6){ + if(TextCp936[0]){ + IList->EditDescpShow.Str.Insert(TextCp936, IList->EditDescpShow.Pst); + IList->EditDescpShow.CorrectPst(); + IList->EditDescpShow.Str.BrokeFixLen(32); + IList->EditDescpShow.CorrectPst(); + IList->EditDescpShow.Show(); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case VK_UP: + if(TagPreSetList.Inx >0){ + TagPreSetList.Inx--; + }else{ + TagPreSetList.Inx=7; + } + DrawPreSetList(); + break; + case VK_DOWN: + if(TagPreSetList.Inx <7){ + TagPreSetList.Inx++; + }else{ + TagPreSetList.Inx=0; + } + DrawPreSetList(); + break; + case dfKEY_SETUP: + Inx = TagPreSetList.Inx; + if(Inx >7)Inx = 0; + for(i=0; i<32; i++){ + TextList[Inx][i] = IList->EditDescpShow.Str.Text[i]; + } + TextList[Inx][32] =0; + TextList[Inx][33] =0; + DrawPreSetList(); + break; + case dfKEY_QUERY: + unsigned int i, Inx; + Inx = TagPreSetList.Inx; + if(Inx >7)Inx = 0; + for(i=0; i<32; i++){ + IList->EditDescpShow.Str.Text[i] = TextList[Inx][i]; + } + IList->EditDescpShow.Str.Text[32] =0; + IList->EditDescpShow.Str.Text[33] =0; + IList->EditDescpShow.Show(); + break; + case VK_TAB: + IsShowPresetList = 0; + DrawPreSetList(); + Check4Selected(); + break; + case VK_EXECUTE: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + EditWhat = TagPreSetList.Inx; + InitPanel(); + IsEditting = 1; + IsExtInput = 0; + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + } + } + return aMsg; +} + +void TDescpWrite::sWrite2Flash(unsigned char aPath0) +{ + unsigned int aP0; + unsigned int aP1; + unsigned int fAddr, sdAddr, GetSta; + unsigned int i,m; + unsigned int wP1; + volatile unsigned int x; + if( (aPath0 >= dADDR_DIRECTPAD_START) && (aPath0 <= dADDR_DIRECTPAD_END) ){ + aP0 = 40; + }else{ + aP0 = aPath0 -1; + } + if(aP0 >= (dPORT_MAX_COUNT +1))return; + + //Erase 2 * 4K Blocks + for(x=0; x<2; x++){ + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(0); + }while(GetSta); + fAddr = dFlashAddrDescpBase + (aP0 * 8192) + (4096 * x); + nor_erase_sector_4k(0,fAddr); + sDelayMs(45); + do{ + sDelayMs(5); + wP1 = nor_get_busy_state(0); + }while(wP1); + } + + //Write 2 Blocks Via 32 Pages * 8 Items + for(x=0; x<32; x++){ + do{ + sDelayMs(1); + GetSta = nor_get_busy_state(0); + }while(GetSta); + m = aP0; + fAddr = dFlashAddrDescpBase + (m * 8192) + (x * 256); + sdAddr = dAddrSdRam_Descp + (m * 8192) + (x * 256); + for(i=0; i<256;i++){ + ReadWriteData.D8[i] = *(volatile unsigned char *)(sdAddr +i); + } + nor_write_page(0, fAddr, ReadWriteData.D8); + do{ + sDelayMs(1); + wP1 = nor_get_busy_state(0); + }while(wP1); + } + + sReadFromFlash(aPath0); +} + +void TDescpWrite::Write2FlashPreSet(unsigned char aPath0) +{ + unsigned int aP0; + unsigned int aP1; + unsigned int fAddr, sdAddr, GetSta; + unsigned int i,m; + unsigned int wP1; + volatile unsigned int x; + if( (aPath0 >= dADDR_DIRECTPAD_START) && (aPath0 <= dADDR_DIRECTPAD_END) ){ + aP0 = 40; + }else{ + aP0 = aPath0 -1; + } + if(aP0 >= (dPORT_MAX_COUNT +1))return; + + //Erase 2 * 4K Blocks + for(x=0; x<2; x++){ + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(0); + }while(GetSta); + fAddr = dFlashAddrDescpBase + (aP0 * 8192) + (4096 * x); + nor_erase_sector_4k(0,fAddr); + sDelayMs(45); + do{ + sDelayMs(5); + wP1 = nor_get_busy_state(0); + }while(wP1); + } + + //Write 2 Blocks Via 32 Pages * 8 Items + for(x=0; x<32; x++){ + do{ + sDelayMs(1); + GetSta = nor_get_busy_state(0); + }while(GetSta); + m = aP0; + fAddr = dFlashAddrDescpBase + (m * 8192) + (x * 256); + sdAddr = dAddrSdRam_Descp + (m * 8192) + (x * 256); + for(i=0; i<256;i++){ + ReadWriteData.D8[i] = *(volatile unsigned char *)(sdAddr +i); + } + nor_write_page(0, fAddr, ReadWriteData.D8); + do{ + sDelayMs(1); + wP1 = nor_get_busy_state(0); + }while(wP1); + } + + sReadFromFlash(aPath0); +} + +void TDescpWrite::sReadFromFlash(unsigned char aPath0) +{ + unsigned int aP0; + unsigned int aP1; + unsigned int fAddr, sdAddr; + unsigned int i; + unsigned int wP1; + volatile unsigned int x; + if( (aPath0 >= dADDR_DIRECTPAD_START) && (aPath0 <= dADDR_DIRECTPAD_END) ){ + aP0 = 40; + }else{ + aP0 = aPath0 -1; + } + if(aP0 >= (dPORT_MAX_COUNT +1))return; + + for(x=0; x<32; x++){ + //2 * 8192 + fAddr = dFlashAddrDescpBase + (aP0 * 8192) + (x * 256); + nor_read_page(0, fAddr, ReadWriteData.D8); + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + sdAddr = dAddrSdRam_Descp + (aP0 * 8192) + (x * 256); + for(i=0; i<64; i++){ + *(volatile unsigned int *)(sdAddr + i *4) = ReadWriteData.D32[i]; + } + } +} + +void TDescpWrite::ReadPreSetStr() +{ + +} + +void TDescpWrite::WritePreSetStr() +{ + +} + + + +void TDescpWrite::Write2Flash() +{ + /*unsigned int fAddr, sdAddr; + unsigned int i,m; + volatile unsigned int x, wP1; + + do{ + DelayMs(5); + wP1 = nor_get_busy_state(0); + }while(wP1); + + //Erase 8 * 64K Blocks + for(x=0; x<8; x++){ + do{ + DelayMs(20); + wP1 = nor_get_busy_state(0); + }while(wP1); + fAddr = dFlashAddrDescpBase + (SizeOf64K * x); + nor_erase_sector_64k(0,fAddr); + do{ + DelayMs(50); + wP1 = nor_get_busy_state(0); + }while(wP1); + } + + for(m=0; mRender(16,Icon16_Up , ArrowUpPoint.x, ArrowUpPoint.y); + IconList->Render(16,Icon16_Down , ArrowDownPoint.x, ArrowDownPoint.y); + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "工程->设计数量"); + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "共 种设备类型. 点位总数 点. 系统总容量 点."); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "共 种设备类型. 点位总数 点. 本机为区域机 "); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "共 种设备类型. 点位总数 点. 本机为单机 "); + } + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Project->Number Of Designe"); + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, " Types Of Dev; Devices ; Devs On Sys: "); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, " Types Of Dev; Devices ; Regional "); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, " Types Of Dev; Devices ; Stand Alone "); + } + } + +} + +void TDesignPrmSet::ShowState() +{ + if(SaveSta == 0){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y ,clNearWhite, ItemColor, " "); + }else + if(SaveSta == 1){ + if(LanguageEnCn==0) TextRender_string24(ResultSavePoint.x, ResultSavePoint.y ,clNearWhite, ItemColor, "保存成功"); + else TextRender_string24(ResultSavePoint.x, ResultSavePoint.y ,clNearWhite, ItemColor, "Saved OK"); + } +} + +void TDesignPrmSet::ShowState(unsigned int aSta) +{ + SaveSta = aSta; + ShowState(); +} + +void TDesignPrmSet::DrawCaption(void) +{ + Caption.Show(); +} + + +void TDesignPrmSet::Show() +{ + RenderBackGround(); + DrawSelf(); +} + +void TDesignPrmSet::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Analy(); + ShowSetting(); + ShowState(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + DrawSelf(); + Analy(); + ShowSetting(); + ShowState(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDesignPrmSet::PermissionCmdReturnDraw() +{ + RectFillRender(Lv.Grid.Left[1] + 200 -10, Lv.Grid.Top[1] + 12 -10, Lv.Grid.Left[1] + 200 -10 + 400 + 20, Lv.Grid.Top[1] + 12 -10 + 140 + 20, ContentColor); + for(int i=1; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + ReAligne(); +} + +void TDesignPrmSet::PermissionCmdGO() +{ + ReStorage(); + Write2Eep(); + ReadData(); + ShowState(1); + ReAligne(); +} + + +void TDesignPrmSet::DrawEntryActive(int aInx, int IsENtryActive) +{ + if(IsENtryActive) + TRoundSquare::sDrawBySize(16, Lv.Grid.Top[aInx + 1] + 6, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + else + TRoundSquare::sDrawBySize(16, Lv.Grid.Top[aInx + 1] + 6, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); +} + +void TDesignPrmSet::DrawEntryTypeString(int aInx) +{ + int x, y, dInx; + unsigned char tType; + x = 46; + y = Lv.Grid.Top[aInx + 1] + 6; + dInx = Setting.TopEntry + aInx; + tType = TypeList.dType[dInx]; + if(LanguageEnCn==0) + TMyString::sFromStr(StrHwType[tType], TextType); + else + TMyString::sFromStr(StrHwTypeEn[tType], TextType); + TMyString::sFillFixLen(TextType, 32); + TextRender_string24(x,y,clNearWhite,ItemColor, TextType); +} + +void TDesignPrmSet::ClearSelected(void) +{ + int i; + for(i=0; i<5; i++){ + aPanel->Edit[i].Selected = 0; + } + switch(Tag.Inx){ + case 0: + TRoundSquare::sSelected(16, Lv.Grid.Top[1] + 6, dWWidth, dWHeigh, 4, ItemColor); + break; + case 1: + aPanel->Edit[0].Show(); + break; + case 2: + TRoundSquare::sSelected(16, Lv.Grid.Top[2] + 6, dWWidth, dWHeigh, 4, ItemColor); + break; + case 3: + aPanel->Edit[1].Show(); + break; + case 4: + TRoundSquare::sSelected(16, Lv.Grid.Top[3] + 6, dWWidth, dWHeigh, 4, ItemColor); + break; + case 5: + aPanel->Edit[2].Show(); + break; + case 6: + TRoundSquare::sSelected(16, Lv.Grid.Top[4] + 6, dWWidth, dWHeigh, 4, ItemColor); + break; + case 7: + aPanel->Edit[3].Show(); + break; + } +} + +void TDesignPrmSet::Check4Selected(void) +{ + int i; + for(i=0; i<5; i++){ + aPanel->Edit[i].Selected = 0; + } + switch(Tag.Inx){ + case 0: + TRoundSquare::sSelected(16, Lv.Grid.Top[1] + 6, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 1: + aPanel->Edit[0].Selected = 1; + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + break; + case 2: + TRoundSquare::sSelected(16, Lv.Grid.Top[2] + 6, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 3: + aPanel->Edit[1].Selected = 1; + aPanel->Edit[1].Show(); + aPanel->Edit[1].ShowCursor(); + break; + case 4: + TRoundSquare::sSelected(16, Lv.Grid.Top[3] + 6, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 5: + aPanel->Edit[2].Selected = 1; + aPanel->Edit[2].Show(); + aPanel->Edit[2].ShowCursor(); + break; + case 6: + TRoundSquare::sSelected(16, Lv.Grid.Top[4] + 6, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 7: + aPanel->Edit[3].Selected = 1; + aPanel->Edit[3].Show(); + aPanel->Edit[3].ShowCursor(); + break; + } +} + +void TDesignPrmSet::InitPanel(void) +{ + aPanel->Init(100,100,10,10,0,0,clFrmFace, bvRaised); + + aPanel->Edit[0].Init(Lv.Grid.Left[1] + 14,Lv.Grid.Top[1] + 36,96,30,0,0,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(Lv.Grid.Left[2] + 14,Lv.Grid.Top[2] + 36,96,30,0,0,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(Lv.Grid.Left[3] + 14,Lv.Grid.Top[3] + 36,96,30,0,0,clNearBlack,clNearWhite); + aPanel->Edit[3].Init(Lv.Grid.Left[4] + 14,Lv.Grid.Top[4] + 36,96,30,0,0,clNearBlack,clNearWhite); + + for(int i=0; i<4;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(6); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("0"); + aPanel->Edit[i].Selected = 0; + } + ReadData(); + Analy(); + ShowSetting(); +} + +void TDesignPrmSet::ShowSetting() +{ + for(int i=Setting.TopEntry, Pcnt=0; (iEdit[Pcnt].Str.FromUInt6Dg(Setting.Count[i]); + aPanel->Edit[Pcnt].SetPstTail(); + aPanel->Edit[Pcnt].Show(); + aPanel->Edit[Pcnt].ShowCursor(); + } + Check4Selected(); +} + +void TDesignPrmSet::LoadData() +{ + int i; + ReadData(); + + aPanel->Edit[0].Str.FromUInt(DesigePrmData.Count.Smoke); + aPanel->Edit[1].Str.FromUInt(DesigePrmData.Count.ModuleInOut); + aPanel->Edit[2].Str.FromUInt(DesigePrmData.Count.Tempe); + aPanel->Edit[3].Str.FromUInt(DesigePrmData.Count.ModuleOutput); + + + for(i=0; i<4; i++){ + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Show(); + } + + aPanel->ReDrawItems(); + Check4Selected(); +} + +void TDesignPrmSet::SaveData() +{ + +} + +TGuiMsgReturn TDesignPrmSet::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int uKey, iVal; + unsigned char aIndex; + char LastChr; + const char *p; + int i; + TGuiMsgReturn PmsRtnMsg; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if(Tag.Inx < 8){ + if(Tag.Inx & 0x01){ + const int eInx = Tag.Inx /2; + aPanel->Edit[eInx].KeyIn(aKey); + iVal = aPanel->Edit[eInx].Str.ToInteger(); + if( (iVal <0) || (iVal>60000) ){ + CntError = 1; + aPanel->Edit[eInx].SelectedColor = clRed; + }else{ + CntError = 0; + aPanel->Edit[eInx].SelectedColor = clBlue; + } + aPanel->Edit[eInx].CorrectPst(); + aPanel->Edit[eInx].Show(); + ReStorage(); + Analy(); + }else{ + const int rInx = Tag.Inx /2 + 1; + Setting.Using[Setting.Entry] = Setting.Using[Setting.Entry] ? 0 : 1; + Setting.Using[Setting.Entry] ? + TRoundSquare::sDrawBySize(Lv.Grid.Left[rInx] + 16, Lv.Grid.Top[rInx] + 6, dWWidth, dWHeigh, dRoundR, dWdClr, 1) : + TRoundSquare::sDrawBySize(Lv.Grid.Left[rInx] + 16, Lv.Grid.Top[rInx] + 6, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + Analy(); + } + } + break; + case VK_UP: + if(CntError == 0){ + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Setting.Entry = Setting.TopEntry + (Tag.Inx /2); + if(Setting.Entry <0)Setting.Entry = 0; + Check4Selected(); + }else{ + if(Setting.TopEntry >0){ + ReStorage(); + ClearSelected(); + Tag.Inx = 1; + Setting.TopEntry--; + Setting.Entry = Setting.TopEntry; + ReAligne(); + Check4Selected(); + } + } + } + break; + case VK_DOWN: + if(CntError == 0){ + if(Tag.Inx < 7){ + ClearSelected(); + Tag.Inx++; + Setting.Entry = Setting.TopEntry + (Tag.Inx /2); + Check4Selected(); + }else{ + if(Setting.Entry < (TypeList.Count -1)){ + ReStorage(); + ClearSelected(); + Tag.Inx = 6; + Setting.TopEntry++; + Setting.Entry++; + ReAligne(); + Check4Selected(); + } + } + } + break; + case VK_TAB: + break; + case dfKEY_SETUP: + if( (Tag.Inx & 0x01) == 0){ + int rInx = Tag.Inx /2 + 1; + Setting.Using[Setting.Entry] = Setting.Using[Setting.Entry] ? 0 : 1; + Setting.Using[Setting.Entry] ? + TRoundSquare::sDrawBySize(Lv.Grid.Left[rInx] + 16, Lv.Grid.Top[rInx] + 6, dWWidth, dWHeigh, dRoundR, dWdClr, 1) : + TRoundSquare::sDrawBySize(Lv.Grid.Left[rInx] + 16, Lv.Grid.Top[rInx] + 6, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + Analy(); + } + break; + case VK_EXECUTE: + if(CntError == 0){ + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 12, 400, 140, 3); + } + } + break; + } + if( (aKey != VK_EXECUTE) && (aKey == VK_RETURN) )ShowState(0); + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + return aMsg; +} + +void TDesignPrmSet::Write2Eep() +{ + unsigned int eAddr; + unsigned int i; + volatile unsigned int aWait, x, wP0, Wait4; + unsigned char Inx; + + //Write Using Count + eAddr = dEepAddrDesignPrm; + DelayMs(10); + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + ReadWriteData.D8[0] = TypeList.Count; + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 1); + DelayMs(10); + + //Write List 1/2 + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + for(i=0; i<128; i++){ + ReadWriteData.D8[i] = Setting.Using[i]; + } + eAddr = dEepAddrDesignPrm + 128; + DelayMs(10); + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 128); + + //Write List 2/2 + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + for(i=0; i<128; i++){ + ReadWriteData.D8[i] = Setting.Using[i +128]; + } + eAddr = dEepAddrDesignPrm + 256; + DelayMs(10); + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 128); + + //Write 8 Times(32 Per Time) = 256 Point Count And Type + for(Inx=0; Inx<8; Inx++){ + eAddr = dEepAddrDesignPrm + 384 + (Inx*128); + if(TypeList.Count > (Inx*32)){ + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + x = Inx*32; + for(i=0; i<32; i++){ + ReadWriteData.Count[i] = Setting.Count[x+i]; + ReadWriteData.Pnt[i].sType = TypeList.dType[x+i]; + } + DelayMs(10); + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 128); + } + } + DelayMs(10); + ReadData(); + LoadData2RuntimeData(); +} + +void TDesignPrmSet::RecoverSetDefault() +{ + unsigned int eAddr; + unsigned int i; + volatile unsigned int aWait, x, wP0, Wait4; + unsigned char Inx; + + //Write Using Count + SysLoopTick = 0; + eAddr = dEepAddrDesignPrm; + DelayMs(10); + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 1); + DelayMs(10); + + //Write List 1/2 + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + eAddr = dEepAddrDesignPrm + 128; + DelayMs(10); + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 128); + + //Write List 2/2 + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + eAddr = dEepAddrDesignPrm + 256; + DelayMs(10); + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 128); + + //Write 8 Times(32 Per Time) = 256 Point Count And Type + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + for(Inx=0; Inx<8; Inx++){ + SysLoopTick = 0; + eAddr = dEepAddrDesignPrm + 384 + (Inx*128); + DelayMs(10); + eeprom_write_byte_via_page(0, eAddr, ReadWriteData.D8, 128); + } +} + +void TDesignPrmSet::ReadData() +{ + unsigned int eAddr; + unsigned int i; + volatile unsigned int x, tCnt; + unsigned char Inx, dType; + + //Read ExistTable + eAddr = dEepAddrDesignPrm; + DelayMs(10); + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + eeprom_read_byte(0, eAddr, ReadWriteData.D8, 1); + DelayMs(10); + + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + eAddr = dEepAddrDesignPrm + 128; + eeprom_read_byte(0, eAddr, ReadWriteData.D8, 128); + for(i=0; i<128; i++){ + TmpUsing[i] = ReadWriteData.D8[i]; + } + + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + eAddr = dEepAddrDesignPrm + 256; + DelayMs(10); + eeprom_read_byte(0, eAddr, ReadWriteData.D8, 128); + for(i=0; i<128; i++){ + TmpUsing[i +128] = ReadWriteData.D8[i]; + } + + for(Inx=0; Inx<8; Inx++){ + eAddr = dEepAddrDesignPrm + 384 + (Inx*128); + if(TypeList.Count > (Inx*32)){ + for(i=0; i<128; i++)ReadWriteData.D8[i] = 0; + DelayMs(10); + eeprom_read_byte(0, eAddr, ReadWriteData.D8, 128); + + x = Inx*32; + for(i=0; i<32; i++){ + tCnt = ReadWriteData.Count[i] & 0x00FFFFFF; + dType = ReadWriteData.Pnt[i].sType; + for(int e=0; e= 60000)DesigePrmData.Count.DisplayPad = 0; + if(DesigePrmData.Count.HandReport >= 60000)DesigePrmData.Count.HandReport = 0; + if(DesigePrmData.Count.HydrantKp >= 60000)DesigePrmData.Count.HydrantKp = 0; + if(DesigePrmData.Count.ModuleInOut >= 60000)DesigePrmData.Count.ModuleInOut = 0; + if(DesigePrmData.Count.ModuleInput >= 60000)DesigePrmData.Count.ModuleInput = 0; + if(DesigePrmData.Count.ModuleOutput >= 60000)DesigePrmData.Count.ModuleOutput = 0; + if(DesigePrmData.Count.Smoke >= 60000)DesigePrmData.Count.Smoke = 0; + if(DesigePrmData.Count.Tempe >= 60000)DesigePrmData.Count.Tempe = 0; + if(DesigePrmData.Count.Va >= 60000)DesigePrmData.Count.Va = 0; + if(DesigePrmData.Count.LnkPs >= 60000)DesigePrmData.Count.LnkPs = 0; + if(DesigePrmData.Count.Other >= 60000)DesigePrmData.Count.Other = 0; +} + +void TDesignPrmSet::BackEnd_LoadData2RuntimeData() +{ + InitBackEnd(); + LoadBaseTypeList(); + ReadData(); + LoadData2RuntimeData(); +} + +void TDesignPrmSet::LoadBaseTypeList() +{ + int i; + unsigned int aAddr; + char *cText; + + TypeList.Count = 0; + for(i=0; i<256; i++){ + TypeList.dType[i] = 0; + } + + //Load Hw Define Type & Manufacturer Define Type + TypeList.Count = 0; + if(LanguageEnCn==0){ + cText = "未"; + for(i=0; i<256; i++){ + if( (StrHwType[i][0] != cText[0]) && (StrHwType[i][1] != cText[1]) ){ + TypeList.dType[TypeList.Count] = i; + TypeList.Count++; + } + } + }else{ + cText = "un"; + for(i=0; i<256; i++){ + if( (StrHwTypeEn[i][0] != cText[0]) && (StrHwTypeEn[i][1] != cText[1]) ){ + TypeList.dType[TypeList.Count] = i; + TypeList.Count++; + } + } + } + + //Load User Define Type + for(i=0; i<256; i++){ + // if( (StrHwType[i][0] != cText[0]) && (StrHwType[i][1] != cText[1]) ){ + // TypeList.dType[TypeList.Count] = i; + // TypeList.Count++; + // } + } +} + +void TDesignPrmSet::ReStorage() +{ + int tEntry = Setting.TopEntry; + for(int i=0; i<4; i++){ + Setting.Count[tEntry] = aPanel->Edit[i].Str.ToInteger(); + tEntry++; + if(tEntry >= TypeList.Count)break; + } +} + +void TDesignPrmSet::ReAligne() +{ + for(int i=Setting.TopEntry, Pcnt=0; (iEdit[Pcnt].Str.FromUInt6Dg(Setting.Count[i]); + aPanel->Edit[Pcnt].SetPstTail(); + aPanel->Edit[Pcnt].Show(); + aPanel->Edit[Pcnt].ShowCursor(); + } +} + +void TDesignPrmSet::Analy() +{ + Setting.UsingTypeCount = 0; + Setting.EpCount =0; + for(int i=0; i探测器曲线", Caption.Text); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + CtlIndex = 0; + FastIndex = 0; + + OnActive = 0; + IsFastCmd = 0; +} + +void TDetectorCurve::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TDetectorCurve::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TDetectorCurve::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TDetectorCurve::DrawCaption2(void) +{ + TMyString::sFromStr("/////", SText.Text); + //SText.Show(); +} + +void TDetectorCurve::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); +} + +void TDetectorCurve::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + aPanel->Show(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + } +} + +void TDetectorCurve::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ + +void TDetectorCurve::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<2;i++)aPanel->Btn[i].Selected = 0; + for(i=0; i<7;i++)aPanel->Edit[i].Selected = 0; + + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Edit[2].Selected = 1; + break; + case 3: + aPanel->Edit[3].Selected = 1; + break; + case 4: + aPanel->Edit[4].Selected = 1; + break; + case 5: + aPanel->Edit[5].Selected = 1; + break; + case 6: + aPanel->Edit[6].Selected = 1; + break; + case 7: + aPanel->Btn[0].Selected = 1; + break; + case 8: + aPanel->Btn[1].Selected = 1; + break; + default: + + break; + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TDetectorCurve::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(CtlIndex < 7){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].ReDraw(); + } + } + + if(aKey == VK_UP){ + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + }else + if(aKey == VK_DOWN){ + if(CtlIndex <8){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + }else + if(aKey == VK_TAB){ + + } + if(aKey == VK_EXECUTE){ + //Save Data Here + SendCmd(); + } + + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TDetectorCurve::PanelCanvasOut() +{ + VertLineRender(RectCanvas.Left, RectCanvas.Top, RectCanvas.Height, clSilver); + VertLineRender(RectCanvas.Right, RectCanvas.Top, RectCanvas.Height, clSilver); + HorizLineRender(RectCanvas.Left, RectCanvas.Top, RectCanvas.Width, clSilver); + HorizLineRender(RectCanvas.Left, RectCanvas.Bottom, RectCanvas.Width, clSilver); + + //VertLineRender(RectPanel.Left + 374, RectPanel.Top + 3, 320, clSilver); +} + +void TDetectorCurve::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + yt = y+6; + aPanel->SText[0].Init(654,3,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[1].Init(658,35,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[2].Init(616,67,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[3].Init(616,99,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[4].Init(616,131,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[5].Init(616,163,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[6].Init(616,195,70,30,x,yt,clNearBlack,clFrmFace); + + yt = y+2; + aPanel->SText[11].Init(360,0, 70,30, x,yt,clNearBlack,clFrmFace); + aPanel->SText[12].Init( 6,0, 70,30, x,yt,clNearBlack,clFrmFace); + aPanel->SText[13].Init(0, 330, 70,30, x,yt,clNearBlack,clFrmFace); + aPanel->SText[14].Init(175,330, 70,30, x,yt,clNearBlack,clFrmFace); + aPanel->SText[15].Init(350,330, 70,30, x,yt,clNearBlack,clFrmFace); + aPanel->SText[16].Init(525,330, 70,30, x,yt,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路号", aPanel->SText[0].Text); + TMyString::sFromStr("地址", aPanel->SText[1].Text); + TMyString::sFromStr("数据1比例", aPanel->SText[2].Text); + TMyString::sFromStr("数据2比例", aPanel->SText[3].Text); + TMyString::sFromStr("数据3比例", aPanel->SText[4].Text); + TMyString::sFromStr("数据4比例", aPanel->SText[5].Text); + TMyString::sFromStr("时间比例", aPanel->SText[6].Text); + + TMyString::sFromStr("正在探测", aPanel->SText[11].Text); + TMyString::sFromStr("类型", aPanel->SText[12].Text); + TMyString::sFromStr("数据名称1", aPanel->SText[13].Text); + TMyString::sFromStr("数据名称2", aPanel->SText[14].Text); + TMyString::sFromStr("数据名称3", aPanel->SText[15].Text); + TMyString::sFromStr("数据名称4", aPanel->SText[16].Text); + + for(i=0; i<6;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + for(i=11; i<17;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + yt = y+6; + aPanel->Edit[0].Init(736,3, 42,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(736,35,42,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(736,67,42,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[3].Init(736,99,42,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[4].Init(736,131,42,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[5].Init(736,163,42,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[6].Init(736,195,42,30,x,yt,clNearBlack,clNearWhite); + yt = y+1; + aPanel->Btn[0].Init(666,240,116,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(666,280,116,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("开始探测"); + aPanel->Btn[1].Caption.FromStr("停止探测"); + + + for(i=0; i<2;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + for(i=0; i<2;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + aPanel->Edit[i].Pst = 2; + } + for(i=2; i<7;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(5); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("10"); + aPanel->Edit[i].Pst = 1; + } + aPanel->Edit[6].Enable = 0; + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); +} + +void TDetectorCurve::SendCmd() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0, aP1; + + Len =5; + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP0 = cVal; + + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP1 = cVal; + + if( (aP0<1) || (aP0 >40) ){ + return; + } + if( (aP1<1) || (aP0 >250) ){ + return; + } + + Path0 = aP0; + Path1 = aP1; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = Path0; + Data[3] = Path1; + + aIde.BitF.Cmd = cVal; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TDetectorCurve::SendCmdAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0, aP1; + + Len =5; + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP0 = cVal; + + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP1 = cVal; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[1] = 0; + Data[2] = Path0; + Data[3] = Path1; + + aIde.BitF.Cmd = cmQueryAbout; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + Data[0] = 0; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +int TDetectorCurve::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + IsOnGoing =0; + SendCmdAbort(); + return 0; +} + + + + diff --git a/MyCode/Gui/DetectorCurve.h b/MyCode/Gui/DetectorCurve.h new file mode 100644 index 0000000..8384f29 --- /dev/null +++ b/MyCode/Gui/DetectorCurve.h @@ -0,0 +1,86 @@ +#ifndef DETETORCURVE_H_ +#define DETETORCURVE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TDetectorCurve{ + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect RectCanvas; + + TRect Content; + TRect RectPanel; + + TMyString Str; + + unsigned int CtlIndex; + unsigned int FastIndex; + unsigned short Scaling[4]; + int IsFastCmd; + unsigned char Data[8]; + unsigned char RecData[8]; + + unsigned char Path0; + unsigned char Path1; + unsigned char IsShowing; + unsigned char IsOnGoing; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TDetectorCurve(){}; + TDetectorCurve(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + + void SendCmd(); + void SendCmdAbort(); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + + + diff --git a/MyCode/Gui/DevAuthorize.cpp b/MyCode/Gui/DevAuthorize.cpp new file mode 100644 index 0000000..786b8b1 --- /dev/null +++ b/MyCode/Gui/DevAuthorize.cpp @@ -0,0 +1,781 @@ +#include "DevAuthorize.h" +#include "Runtime.h" + +extern "C"{ + #include "HW_config.h" + #include "user_eeprom.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +#define genNumValidTime (24*60*60) // 1 day uint:1s +#define validAuthTimeMax (90*24*60*60)//90day + +void TDevAuthorize::Init() +{ + unsigned int i = 0; + unsigned char numChar = 0; + + IsPermission =0; + + + + Tag.Reset(); + SaveSta = 0; + + for(i=0;i<12;i++){ + AuthCfg.prm.serNum[i] = uid_value.val_8[i]; + + if((uid_value.val_8[i] & 0xF0) > 0x90){ + MainCtl.Sn[i*2] = 'A' + ((uid_value.val_8[i]>>4) & 0x0F) - 0x0A; + }else{ + MainCtl.Sn[i*2] = '0' + ((uid_value.val_8[i]>>4) & 0x0F); + } + + if((uid_value.val_8[i] & 0x0F) > 0x09){ + MainCtl.Sn[i*2+1] = 'A' + (uid_value.val_8[i] & 0x0F) - 0x0A; + }else{ + MainCtl.Sn[i*2+1] = '0' + (uid_value.val_8[i] & 0x0F); + } + } + MainCtl.Sn[24] = 0; + MainCtl.Sn[25] = 0; + CommonDelayMs(10); + eeprom_read_byte(0, (dEepAddrAuthorizePrm + 0), ((unsigned char *)(&AuthCfg.prm.workTime)),4); + CommonDelayMs(1); + eeprom_read_byte(0, (dEepAddrAuthorizePrm + 4), ((unsigned char *)(&AuthCfg.prm.genNum)), 4); + CommonDelayMs(1); + eeprom_read_byte(0, (dEepAddrAuthorizePrm + 8), ((unsigned char *)(&AuthCfg.prm.genNumTime)), 4); + CommonDelayMs(1); + eeprom_read_byte(0, (dEepAddrAuthorizePrm +12), ((unsigned char *)(&AuthCfg.prm.validAuthTime)), 4); + + if(0xFFFFFFFF == AuthCfg.prm.genNumTime){ + AuthCfg.prm.genNumTime = 0; + } + + if(0xFFFFFFFF == AuthCfg.prm.workTime){ + AuthCfg.prm.genNumTime = 0; + } + + if((AuthCfg.prm.validAuthTime > 0)&&(AuthCfg.prm.validAuthTime <= 0xAA55AA55)){ + if(0xAA55AA55 == AuthCfg.prm.validAuthTime){ + SysIsAuthState = 2; + SysAuthorize.fDa.Done = 1; + }else + if((AuthCfg.prm.validAuthTime > AuthCfg.prm.workTime) && ((AuthCfg.prm.validAuthTime - AuthCfg.prm.workTime) <= validAuthTimeMax)){ + SysIsAuthState = 1; + SysAuthorize.fDa.Done = 1; + SysRemainAuthTimeHour = (AuthCfg.prm.validAuthTime - AuthCfg.prm.workTime)/3600%1000000; + }else{ + SysAuthorize.fDa.Done = 0; + SysIsAuthState = 0; + } + }else{ + SysAuthorize.fDa.Done = 0; + } + + if((AuthCfg.prm.genNumTime + genNumValidTime > AuthCfg.prm.workTime)&&(AuthCfg.prm.genNum)&&(AuthCfg.prm.genNum < 0xFFFFFFFF)){ + for(i=0;i<8;i++){ + numChar = (AuthCfg.prm.genNum >> (28-i*4)) & 0x0F; + if(numChar > 0x9){ + MainCtl.GenSn[i] = 'A' + numChar - 0x0A; + }else{ + MainCtl.GenSn[i] = '0' + numChar; + } + } + MainCtl.GenSn[8] = 0; + MainCtl.GenSn[9] = 0; + }else{ + MainCtl.GenSn[0] = 0; + MainCtl.GenSn[1] = 0; + } + + TimeSecHasRun = AuthCfg.prm.workTime / 3600; +} + +void TDevAuthorize::GetGenSn() +{ + unsigned int i = 0; + unsigned char numChar = 0; + + for(i=0;i<8;i++){ + numChar = (AuthCfg.prm.genNum >> (28-i*4)) & 0x0F; + if(numChar > 0x9){ + MainCtl.GenSn[i] = 'A' + numChar - 0x0A; + }else{ + MainCtl.GenSn[i] = '0' + numChar; + } + } + MainCtl.GenSn[8] = 0; + MainCtl.GenSn[9] = 0; +} + +void TDevAuthorize::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick系统授权"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "工程名称"); + TextRender_string24(Lv.Grid.Left[0] + 520, Lv.Grid.Top[0] +8, clNearWhite, "运行时长:"); + TextDigitRender5Right24(Lv.Grid.Left[0] + 636, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun / 24); + TextRender_string24(Lv.Grid.Left[0] + 698, Lv.Grid.Top[0] +8, clNearWhite, "天"); + TextDigitRender2Right24(Lv.Grid.Left[0] + 722, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun % 24); + TextRender_string24(Lv.Grid.Left[0] + 746, Lv.Grid.Top[0] +8, clNearWhite, "小时"); + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +8, clNearWhite, "系统授权"); + //TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +50, clNearWhite, "正常运行"); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] +8, clNearWhite, "产品序列号:"); + TextRender_string24(Lv.Grid.Left[2] + 138, Lv.Grid.Top[2] +8, clNearWhite, MainCtl.Sn); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] +46, clNearWhite, "产品生成码:"); + TextRender_string24(Lv.Grid.Left[2] + 280, Lv.Grid.Top[2] +46, clNearWhite, MainCtl.GenSn); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] + 82, clNearWhite, "产品授权码:"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Project->Authorization"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "PrjName"); + TextRender_string24(Lv.Grid.Left[0] + 520, Lv.Grid.Top[0] +8, clNearWhite, "Duration:"); + TextDigitRender5Right24(Lv.Grid.Left[0] + 636, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun / 24); + TextRender_string24(Lv.Grid.Left[0] + 698, Lv.Grid.Top[0] +8, clNearWhite, "D"); + TextDigitRender2Right24(Lv.Grid.Left[0] + 722, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun % 24); + TextRender_string24(Lv.Grid.Left[0] + 746, Lv.Grid.Top[0] +8, clNearWhite, "Hour"); + + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +8, clNearWhite, "Authoriza"); + //TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +50, clNearWhite, "正常运行"); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] +8, clNearWhite, "Ser Number:"); + TextRender_string24(Lv.Grid.Left[2] + 138, Lv.Grid.Top[2] +8, clNearWhite, MainCtl.Sn); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] +46, clNearWhite, "Reg Code "); + TextRender_string24(Lv.Grid.Left[2] + 280, Lv.Grid.Top[2] +46, clNearWhite, MainCtl.GenSn); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] + 82, clNearWhite, "Activation"); + } + + ShowIfDone(); +} + +void TDevAuthorize::Show(void) +{ + RenderBackGround(); + DrawSelf(); +} + +void TDevAuthorize::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + aPanel->ReDrawItems(); + Check4Selected(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + DrawSelf(); + aPanel->ReDrawItems(); + Check4Selected(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +//______________________________________________________________________________________________________________________________ +void TDevAuthorize::ClearSelected(void) +{ + if(Tag.Inx0 == 0){ + aPanel->Btn[1].Selected = 0; + aPanel->Btn[1].Show(); + }else + if(Tag.Inx0 == 1){ + aPanel->Btn[0].Selected = 0; + aPanel->Btn[0].Show(); + }else + if(Tag.Inx0 == 2){ + aPanel->Edit[1].Selected = 0; + aPanel->Edit[1].Show(); + } +} + + +void TDevAuthorize::Check4Selected(void) +{ + if(Tag.Inx0 == 0){ + aPanel->Btn[1].Selected = 1; + aPanel->Btn[1].Show(); + }else + if(Tag.Inx0 == 1){ + aPanel->Btn[0].Selected = 1; + aPanel->Btn[0].Show(); + }else + if(Tag.Inx0 == 2){ + aPanel->Edit[1].Selected = 1; + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[1].Show(); + } +} + +void TDevAuthorize::ShowIfDone() +{ + if(LanguageEnCn==0){ + if(SysAuthorize.fDa.Done){ + TCircle::sRender(Lv.Grid.Left[1] + 24, Lv.Grid.Top[1] +54, 12, clDeepGreen, 1); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "系统已授权"); + if(0xAA55AA55 == AuthCfg.prm.validAuthTime){ + TextRender_string24(Lv.Grid.Left[1] + 186, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "永久使用 "); + }else{ + TMyString::sFromStr("剩余使用时间:",Text); + TMyString::sAddOn4Dg(((AuthCfg.prm.validAuthTime - AuthCfg.prm.workTime)/3600%1000000),Text); + TMyString::sAddOnStr("小时",Text); + TextRender_string24(Lv.Grid.Left[1] + 186, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, Text); + } + }else{ + TCircle::sRender(Lv.Grid.Left[1] + 24, Lv.Grid.Top[1] +54, 12, clRed, 1); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "系统未授权"); + + TextRender_string24(Lv.Grid.Left[1] + 186, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "剩余使用时间: 0小时 "); + } + }else{ + if(SysAuthorize.fDa.Done){ + TCircle::sRender(Lv.Grid.Left[1] + 24, Lv.Grid.Top[1] +54, 12, clDeepGreen, 1); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "Licensed"); + if(0xAA55AA55 == AuthCfg.prm.validAuthTime){ + TextRender_string24(Lv.Grid.Left[1] + 186, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "Forever "); + }else{ + TMyString::sFromStr("Remaining usage",Text); + TMyString::sAddOn4Dg(((AuthCfg.prm.validAuthTime - AuthCfg.prm.workTime)/3600%1000000),Text); + TMyString::sAddOnStr("Hours",Text); + TextRender_string24(Lv.Grid.Left[1] + 186, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, Text); + } + }else{ + TCircle::sRender(Lv.Grid.Left[1] + 24, Lv.Grid.Top[1] +54, 12, clRed, 1); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "Unlicensed"); + TextRender_string24(Lv.Grid.Left[1] + 186, Lv.Grid.Top[1] +42, clNearWhite, ItemColor, "Remaining: 0Hours "); + } + } +} + +void TDevAuthorize::ShowMth() +{ + +} + +void TDevAuthorize::ShowVision() +{ + +} + +void TDevAuthorize::ShowSound() +{ + +} + +void TDevAuthorize::PermissionCmdReturnDraw() +{ + //PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 12, 400, 120, 2); + RectFillRender(Lv.Grid.Left[3] + 200-10, Lv.Grid.Top[3] + 14 -10, Lv.Grid.Left[3] + 200-10 + 420, Lv.Grid.Top[3] + 14 -10 + 138, ContentColor); +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TDevAuthorize::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn MBoxMsg = guiMsgNone; + int iVal; + + TGuiMsgReturn PmsRtnMsg; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx0 ==2){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + aPanel->Edit[1].ShowCursor(); + } + break; + case VK_UP: + if(IfShowAuthorizeButton){ + if(Tag.Inx0 >0){ + ClearSelected(); + Tag.Inx0--; + Check4Selected(); + } + }else{ + if(Tag.Inx0 >1){ + ClearSelected(); + Tag.Inx0--; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(Tag.Inx0 <2){ + ClearSelected(); + Tag.Inx0++; + Check4Selected(); + } + break; + case VK_F1: + break; + case VK_EXECUTE: + if(Tag.Inx0 == 0){ + //Do DisShow + set_auth_function_able(1); + Check2IfShowAuthorizeButton(); + if(IfShowAuthorizeButton == 0){ + IfShowAuthorizeButton = 0; + aPanel->Btn[1].Enable = 0; + ClearSelected(); + Tag.Inx0 =1; + Check4Selected(); + } + }else + //Save Data Here + if(Tag.Inx0 ==1){ + PermissionCmd = 1; + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission =1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 14, 400, 116, 2); + } + }else + if(Tag.Inx0 == 2){ + PermissionCmd = 2; + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission =1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 14, 400, 116, 2); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + if( (aKey != VK_EXECUTE) && (aKey != VK_RETURN) ){ + ShowSta(0); + } + } + + return aMsg; +} + +void TDevAuthorize::PermissionCmdGO() +{ + if(PermissionCmd == 2){ + WriteData(); + }else + if(PermissionCmd == 1){ + GenRandomCode(); + } + IsPermission = 0; +} + +void TDevAuthorize::InitPanel(void) +{ + int i; + aPanel->Init(400,400,10,10,0,0,clFrmFace, bvRaised); + + aPanel->Edit[0].Init(Lv.Grid.Left[0] +104, Lv.Grid.Top[0] + 2, 400, 32, 0,0, 1,ItemColor); + aPanel->Btn[0].Init(Lv.Grid.Left[2] + 138, Lv.Grid.Top[2] + 40,120, 34, 0,0, 1,clFrmFace); + aPanel->Edit[1].Init(Lv.Grid.Left[2] + 138, Lv.Grid.Top[2] + 76,300, 30, 0,0, 1,ItemColor); + + for(i=0; i<1; i++){ + aPanel->Edit[i].IsShowCursor = 0; + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + } + aPanel->Btn[0].Color = clFrmFace; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[0].Visible = 1; + aPanel->Btn[0].SetCaptionLeftSpacing(6); + if(LanguageEnCn==0)aPanel->Btn[0].SetCaption( "确认生成",24); + else aPanel->Btn[0].SetCaption( "Generate",24); + aPanel->Btn[0].SelectedColor = clBlue; + aPanel->Btn[0].SelectedTextColor = clNearWhite; + for(i=1; i<2; i++){ + aPanel->Edit[i].IsShowCursor = 1; + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].MaxLen = 24; + aPanel->Edit[i].IsShowCursor = 1; + aPanel->Edit[i].Str.Clear(); + } + Check2IfShowAuthorizeButton(); + aPanel->Btn[1].Init(Lv.Grid.Left[1] + 138, Lv.Grid.Top[1] + 6,120, 34, 0,0, 1,clFrmFace); + aPanel->Btn[1].Color = clFrmFace; + aPanel->Btn[1].Enable =1; + aPanel->Btn[1].Visible = 1; + aPanel->Btn[1].SetCaptionLeftSpacing(6); + if(LanguageEnCn==0)aPanel->Btn[1].SetCaption("使能授权",24); + else aPanel->Btn[1].SetCaption("Register",24); + aPanel->Btn[1].SelectedColor = clBlue; + aPanel->Btn[1].SelectedTextColor = clNearWhite; +} + +void TDevAuthorize::LoadData() +{ + Setting.IsNormal = RunState; + //Setting.Hours = RunModeData.Hours; + + for(int i=0; i<32; i++){ + aPanel->Edit[0].Str.Text[i] = PrjName[i]; + } + aPanel->Edit[0].Str.Text[32] = '\0'; + aPanel->Edit[0].Str.Text[33] = '\0'; + + if(IfShowAuthorizeButton){ + aPanel->Btn[1].Enable =1; + Tag.Inx0 = 0; + }else{ + aPanel->Btn[1].Enable =0; + Tag.Inx0 = 1; + } + + ShowIfDone(); + aPanel->ReDrawItems(); + + Check4Selected(); +} + +void TDevAuthorize::WriteData() +{ + //RunModeData.IsNormal = Setting.IsNormal; + + unsigned int charLen= aPanel->Edit[1].Str.GetLength(); + if(0 == charLen){ + //请输入授权码 + ShowSta(-2); + }else + if(charLen > 5){ + //请输入正确长度的授权码 + ShowSta(-3); + }else{ + AuthCfg.prm.authNum = aPanel->Edit[1].Str.ToInteger(); + + if(CalcValidDay(&AuthCfg)){ + SysAuthorize.fDa.Done = 0; + AuthCfg.prm.validAuthTime = 0; + DelayMs(10); + eeprom_write_byte_via_page(0, (dEepAddrAuthorizePrm +12), ((unsigned char *)(&AuthCfg.prm.validAuthTime)),4); + DelayMs(10); + + ShowSta(-1); + }else{ + if(0xA5C3 == AuthCfg.prm.validDay){//永久有效 + AuthCfg.prm.validAuthTime = 0xAA55AA55; + }else{ + Setting.Hours = AuthCfg.prm.validDay * 24; + AuthCfg.prm.validAuthTime = AuthCfg.prm.workTime + (AuthCfg.prm.validDay * 24 * 3600); + } + DelayMs(10); + eeprom_write_byte_via_page(0, (dEepAddrAuthorizePrm +12), ((unsigned char *)(&AuthCfg.prm.validAuthTime)),4); + DelayMs(10); + + SysAuthorize.fDa.Done = 1; + + ShowSta(1); + } + + ShowIfDone(); + + if(Setting.Hours == 0) Setting.Hours = 2; + if(Setting.Hours > 99) Setting.Hours = 99; + //RunModeData.Hours = Setting.Hours; + + LoadData(); + } +} + +void TDevAuthorize::ShowSta() +{ + if(LanguageEnCn==0){ + if(SaveSta == 0){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, " "); + }else + if(SaveSta == 1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "授权成功 "); + ShowIfDone(); + }else + if(SaveSta == -1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "授权失败 "); + ShowIfDone(); + }else + if(SaveSta == -2){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "请输入授权码 "); + ShowIfDone(); + }else + if(SaveSta == -3){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "请输入正确长度的授权码"); + ShowIfDone(); + } + }else{ + if(SaveSta == 0){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, " "); + }else + if(SaveSta == 1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "Successfully Registered "); + ShowIfDone(); + }else + if(SaveSta == -1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "Failed To Register "); + ShowIfDone(); + }else + if(SaveSta == -2){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "Enter Activation Key "); + ShowIfDone(); + }else + if(SaveSta == -3){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ItemColor, "Activation Key Error "); + ShowIfDone(); + } + } +} + +void TDevAuthorize::ShowSta(int aSta) +{ + SaveSta = aSta; + ShowSta(); +} + +static const uint16_t crc16Table[256] = { + 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, + 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440, + 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40, + 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841, + 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40, + 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41, + 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641, + 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040, + 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240, + 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441, + 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41, + 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840, + 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41, + 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40, + 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640, + 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041, + 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240, + 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441, + 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41, + 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840, + 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41, + 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40, + 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640, + 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041, + 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241, + 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440, + 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40, + 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841, + 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40, + 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41, + 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641, + 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040 +}; + +static const uint16_t crc16_xmodem_table[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7, + 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6, + 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485, + 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4, + 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC, + 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B, + 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12, + 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A, + 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41, + 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49, + 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70, + 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78, + 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F, + 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E, + 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D, + 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C, + 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3, + 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A, + 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92, + 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9, + 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1, + 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8, + 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0 +}; + +unsigned short TDevAuthorize::myCrc16(unsigned char *pD, unsigned int len) +{ + uint16_t crc = 0x0000; // 初始值，与标准算法一致 + unsigned int i,index; + if (pD == NULL || len == 0) { + return crc; // 空数据返回初始值 + } + + for (i = 0; i < len; i++) { + // 核心查表操作：(CRC左移8位) XOR 查表结果 + crc = (crc << 8) ^ crc16_xmodem_table[(crc >> 8) ^ pD[i]]; + } + + return crc; // 无需异或输出，直接返回结果 +} + +/* +unsigned short TDevAuthorize::myCrc16(unsigned char *pD, unsigned int len) +{ + unsigned int i,index; + unsigned short aCrc = 0xFFFF; + + for (i = 0; i < len; i++) { + index = static_cast(aCrc ^ pD[i]); + aCrc = (aCrc >> 8) ^ crc16Table[index]; + } + + return aCrc; +} +*/ +void TDevAuthorize::GenRandomCode() +{ + unsigned int aRandomCode; + unsigned int aValue; + + aValue = LL_TIM_GetCounter(TIM7); + aValue = aValue & 0xFFFF; + aValue+= ((AuthCfg.prm.workTime>>16)&0xFFFF); + aValue+= ((AuthCfg.prm.workTime<<16)&0xFFFF0000); + + aRandomCode = rand(); + aRandomCode ^= aValue; + aRandomCode += aValue; + + if((0 == aRandomCode)||(0xFFFFFFFF == aRandomCode)){ + aRandomCode = rand(); + aRandomCode ^= aValue; + aRandomCode += aValue; + } + + AuthCfg.prm.genNum = aRandomCode; + + //---------------record genNum and gen time----------------------------------- + DelayMs(10); + eeprom_write_byte_via_page(0, (dEepAddrAuthorizePrm + 4), ((unsigned char *)(&AuthCfg.prm.genNum)),4); + DelayMs(10); + AuthCfg.prm.genNumTime = AuthCfg.prm.workTime; + eeprom_write_byte_via_page(0, (dEepAddrAuthorizePrm + 8), ((unsigned char *)(&AuthCfg.prm.genNumTime)),4); + DelayMs(10); + + GetGenSn(); + TextRender_string24(Lv.Grid.Left[2] + 280, Lv.Grid.Top[2] +46, clNearWhite, ItemColor, MainCtl.GenSn); +} + +unsigned int TDevAuthorize::CalcValidDay(TAuthCalc * aCalcNum) +{ + unsigned int res = 0; + + //生成码过期 + if((aCalcNum->prm.genNumTime + genNumValidTime) < aCalcNum->prm.workTime){ + res = 1; + return res; + } + //先认证是否是长期有效，长期有效码是0xA5C3 + aCalcNum->prm.validDay = 0xA5C3; + if(aCalcNum->prm.authNum == (myCrc16(aCalcNum->d8, 18))){ + return res; + } + //获取有效天数 + for(aCalcNum->prm.validDay = 1;aCalcNum->prm.validDay < 10000;aCalcNum->prm.validDay++){ + if(aCalcNum->prm.authNum == (myCrc16(aCalcNum->d8, 18))){ + return res; + } + } + //成功返回0，失败返回1 + res = 1; + return res; +} + +void TDevAuthorize::Check2IfShowAuthorizeButton() +{ + //Value 1 to Show the Button to Active Function Authorizing + if(!check_auth_function_isenable()){ + IfShowAuthorizeButton =1; + }else{ + IfShowAuthorizeButton =0; + } +} + +void TDevAuthorize::Task1000Ms() +{ + AuthCfg.prm.workTime++; + if(0 == (AuthCfg.prm.workTime % 600)){ + DelayMs(10); + eeprom_write_byte_via_page(0, dEepAddrAuthorizePrm, ((unsigned char *)(&AuthCfg.prm.workTime)),4); + HAL_Delay(10); + } + + if(AuthCfg.prm.validAuthTime < AuthCfg.prm.workTime){//授权结束 + SysAuthorize.fDa.Done = 0; + } +} + + + + + + + + diff --git a/MyCode/Gui/DevAuthorize.h b/MyCode/Gui/DevAuthorize.h new file mode 100644 index 0000000..6007837 --- /dev/null +++ b/MyCode/Gui/DevAuthorize.h @@ -0,0 +1,152 @@ +#ifndef DEVAUTHORIZE_H_ +#define DEVAUTHORIZE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +typedef union{ + unsigned int d32[6]; + unsigned char d8[24]; + struct{ + unsigned char serNum[12]; + unsigned int genNum; + unsigned short validDay; + unsigned short authNum; + + unsigned int workTime; + unsigned int genNumTime; + unsigned int validAuthTime; + }prm; +}TAuthCalc; + +class TDevAuthorize{ + public: + static constexpr unsigned short hList[12] = {36,70,110,156, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[2] + 340, + .y = Lv.Grid.Top[2] + 132, + }; + static constexpr TPoint ResultSavePoint = { + .x = Lv.Grid.Left[2] + 460, + .y = Lv.Grid.Top[2] + 46, + }; + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + + TAuthCalc AuthCfg; + + public: + char Text[32]; + + u32 Color; + + + TRect Bound; + TRect Content; + + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Dump0; + void Reset(){ + Group = 0; + Inx0 = 0; + Inx1 = 0; + } + }Tag; + struct{ + unsigned char IsNormal; + unsigned char Hours; + }Setting; + int SaveSta; + + unsigned char IsPermission; + unsigned char PermissionCmd; + unsigned char IfShowAuthorizeButton; + public: + TDevAuthorize(){}; + void Init(); + + void GetGenSn(); + + void DelayMs(unsigned int aMs); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void FullRedraw(int Prm); + void ReDraw(void); + void ShowMth(); + void ShowVision(); + void ShowSound(); + void ShowIfDone(); + + void ClearSelected(void); + void Check4Selected(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + void ExtLoadData(); + void LoadData(); + void WriteData(); + + void ShowSta(); + void ShowSta(int aSta); + + int ExtRequst(unsigned char Prm){return 0;} + + void PermissionCmdGO(); + void PermissionCmdReturnDraw(); + + unsigned short myCrc16(unsigned char *pD, unsigned int len); + void GenRandomCode(); + unsigned int CalcValidDay(TAuthCalc * aCalcNum); + + void Check2IfShowAuthorizeButton(); + + void Task1000Ms(); +}; + + + +#endif + diff --git a/MyCode/Gui/DevCount.cpp b/MyCode/Gui/DevCount.cpp new file mode 100644 index 0000000..5b281dc --- /dev/null +++ b/MyCode/Gui/DevCount.cpp @@ -0,0 +1,523 @@ +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" +#include "DevCount.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 +#define IconVcnt 5 +#define IconHcnt 10 + +#define HLineTextRight 780 +#define HSpace 33 + +#define clOdd clMoneyGreen +#define clEven clWhiteBlue + +#define dCountDrawX 60 +#define dCountDrawY 120 + +#define dCountDrawWidth 640 +#define dCountDrawHeight 320 + +#define dPortInxMax 24 + +static const int Lv0Left[5] ={ + 10, 130, 280, 460, 610 +}; +static const int Lv1Left[6] ={ + 4, 64, 164, 230, 340, 410 +}; + +void TDevCount::DrawFixText() +{ + volatile int aCn; + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->注册类型数量查看 "); + TextRender_string24(Lv0Left[0],Lv.Grid.Top[1] + 4, clNearWhite, "回路"); + TextRender_string24(Lv0Left[1],Lv.Grid.Top[1] + 4, clNearWhite, "已注册点数"); + TextRender_string24(Lv0Left[2],Lv.Grid.Top[1] + 4, clNearWhite, "未注册点数"); + TextRender_string24(Lv0Left[3],Lv.Grid.Top[1] + 4, clNearWhite, "屏蔽地址数"); + TextRender_string24(Lv0Left[4],Lv.Grid.Top[1] + 4, clNearWhite, "已注册比例"); + + TMyString::sClear(Text); + TMyString::sFromStr("机器号 ", Text); + TMyString::sAddOn2Dg(MainCtl.fData.Split.MyNum,Text); + TMyString::sAddOnStr(" 本机", Text); + TextRender_string24(Lv.Grid.Left[ 0]+ 10, Lv.Grid.Top[ 0]+ 4, clNearWhite, Text); + + TMyString::sClear(Text); + TMyString::sFromStr("总回路数", Text); + TMyString::sAddOn2Dg(MainCtl.fData.Split.PortCount,Text); + TMyString::sAddOnStr(" 已注册总点数",Text); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Amount Of Different Types "); + TextRender_string24(Lv0Left[0],Lv.Grid.Top[1] + 4, clNearWhite, "Loop"); + TextRender_string24(Lv0Left[1],Lv.Grid.Top[1] + 4, clNearWhite, "Registered"); + TextRender_string24(Lv0Left[2],Lv.Grid.Top[1] + 4, clNearWhite, "UnRegister"); + TextRender_string24(Lv0Left[3],Lv.Grid.Top[1] + 4, clNearWhite, "Blockings"); + TextRender_string24(Lv0Left[4],Lv.Grid.Top[1] + 4, clNearWhite, "Reg Ratio"); + + TMyString::sClear(Text); + TMyString::sFromStr("CtlID ", Text); + TMyString::sAddOn2Dg(MainCtl.fData.Split.MyNum,Text); + TMyString::sAddOnStr(" Local", Text); + TextRender_string24(Lv.Grid.Left[ 0]+ 10, Lv.Grid.Top[ 0]+ 4, clNearWhite, Text); + + TMyString::sClear(Text); + TMyString::sFromStr("Loop(s)", Text); + TMyString::sAddOn2Dg(MainCtl.fData.Split.PortCount,Text); + TMyString::sAddOnStr(" Amout Of Registered:",Text); + } + aCn =0; + for(int i=0; idPORT_MAX_COUNT)return; + + unsigned char tP0 = aP0-1; + if(MainCtl.fData.Split.ExistTablePort[tP0] == 0xA5){ + for(int j=0; j<250; j++){ + if(Port[tP0].ExistTable[j]){ + unsigned char aType = Port[tP0].dTypeTable[j]; + if(aType){ + if( (aType == dgTYPE_SMOKE_DETECTOR) ){ + Count.Smoke++; + }else + if( aType == dgTYPE_TEMPE_DETECTOR ){ + Count.Tempe++; + }else + if( (aType == dgTYPE_HAND_REPORT ) ){ + Count.HandReport++; + }else + if( (aType == dgTYPE_FIRE_HydrantKp ) ){ + Count.HydKp++; + }else + if( (aType == dgTYPE_IN_MODULE ) ){ + Count.ModuleInput++; + }else + if( (aType == dgTYPE_INOUT_MODULE_NonSource) || + (aType == dgTYPE_INOUT_MODULE_Source) ){ + Count.ModuleInOut++; + }else + if( (aType == dgTYPE_OUT_MODULE) ){ + Count.ModuleOutput++; + }else + if( (aType == dgType_VAALRAM ) ){ + Count.Va++; + }else + if( aType == dgTYPE_DISPLAY_PAD ){ + Count.FDisplay++; + }else + if( aType == dgTYPE_LINKAGE_POWERSUPLY ){ + Count.LinkPwr++; + }else + if( aType == dgTYPE_SMOKE_TEMPE_DETECTOR ){ + Count.SmokeTempe++; + }else{ + Count.cOther++; + } + } + } + } + } +} + +void TDevCount::DrawPortDevCount() +{ + int x, yOffset; + unsigned char tP0; + + if(HasDraw4P0 > dPORT_MAX_COUNT)return; + RectFillRender(0, Lv.Grid.Top[1] -1, 800 -1, 440 -1, ContentColor); + RectFillRender(dCountDrawX, dCountDrawY, dCountDrawX + dCountDrawWidth -1, dCountDrawY + (7 * 32)-1, clMoneyGreen); + + x = (7 * 32)-1; + VertLineRender(dCountDrawX + 0, dCountDrawY, x, clBlue); + VertLineRender(dCountDrawX + 190, dCountDrawY, x, clBlue); + VertLineRender(dCountDrawX + 320, dCountDrawY, x, clBlue); + VertLineRender(dCountDrawX + 510, dCountDrawY, x, clBlue); + VertLineRender(dCountDrawX + dCountDrawWidth -1, dCountDrawY, x, clBlue); + + for(x=0; x<8;x++){ + HorizLineRender(dCountDrawX, dCountDrawY + (x * 32), dCountDrawWidth -1, clBlue); + } + + Count.Reset(); + if(HasDraw4P0){ + GetOnePortCount(HasDraw4P0); + }else{ + for(int i=0; i dPORT_MAX_COUNT)return; + HasDraw4P0 = aP0; + DrawPortDevCount(); +} + +void TDevCount::ClearSelectedLv0(void) +{ + int iT; + iT = Line + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle +} + +void TDevCount::Check4SelectedLv0(void) +{ + int iT; + iT = Line + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle +} + +TGuiMsgReturn TDevCount::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex, Found; + unsigned char aP0; + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn aMsg2Rtn = guiMsgNone; + //Up or Down One Index___________________ + + if(IsShowingCount == 0){ + if(VK_LEFT ==aKey){ + + }else + if(VK_RIGHT == aKey){ + + }else + if(VK_UP == aKey){ + if(Line >0){ + ClearSelectedLv0(); + Line--; + PortInx--; + Check4SelectedLv0(); + }else{ + if(PortInx >0){ + PortInx--; + PortInxTop = PortInx; + DrawList(); + } + } + }else + if(VK_DOWN == aKey){ + if(Line < 7){ + if(PortInx < dPortInxMax){ + ClearSelectedLv0(); + Line++; + PortInx++; + Check4SelectedLv0(); + } + }else{ + Line = 7; + if(PortInx < dPortInxMax){ + PortInx++; + PortInxTop++; + DrawList(); + } + } + }else + if(aKey == VK_TAB){ + + }else + if(aKey == VK_EXECUTE){ + //Open path Device + IsShowingCount =1; + DrawPortDevCount(PortInx); + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + }else{ + + } + }else{ + if(aKey == VK_RETURN){ + IsShowingCount =0; + RenderBackGround(); + DrawSelf(); + DrawList(); + Check4SelectedLv0(); + }else{ + + } + } + + //____________________________________________________________________<- List View + + return aMsg; + +} + + + + + + + + + + + diff --git a/MyCode/Gui/DevCount.h b/MyCode/Gui/DevCount.h new file mode 100644 index 0000000..14f3df3 --- /dev/null +++ b/MyCode/Gui/DevCount.h @@ -0,0 +1,178 @@ +#ifndef DEVCOUNT_H_ +#define DEVCOUNT_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "Icon.h" + +#define dLISTVIEW_TYPE_DUMP 0 +#define dLISTVIEW_TYPE_SYS 1 +#define dLISTVIEW_TYPE_EP 2 +#define dLISTVIEW_TYPE_PORT 3 +#define dLISTVIEW_TYPE_HANDCTL 4 +#define dLISTVIEW_TYPE_DIRECTCTL 5 + +#define dLISTVIEW_STYLE_LIST 0 +#define dLISTVIEW_STYLE_ICON 1 +#define dLISTVIEW_VSCOLLBAR_WIDTH 20 + +//For Device View or Edit +class TDevCount{ + public: + static constexpr unsigned short hList[12] = {34,34,34,34, 34,34,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]) +4, + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1] +4, + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 10, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + unsigned char PortInx; + unsigned char PortInxTop; + unsigned char Line; + unsigned char IsShowingCount; + struct{ + unsigned short Smoke; + unsigned short Tempe; + + unsigned short HandReport; + unsigned short HydKp; + + unsigned short ModuleInput; + unsigned short ModuleInOut; + + unsigned short ModuleOutput; + unsigned short Va; + + unsigned short FDisplay; + unsigned short SmokeTempe; + + unsigned short LinkPwr; + unsigned short cOther; + + unsigned int Tt; + + void Reset(){ + Smoke =0; + Tempe =0; + HandReport =0; + HydKp =0; + ModuleInput =0; + ModuleInOut =0; + ModuleOutput =0; + Va =0; + FDisplay =0; + SmokeTempe =0; + LinkPwr =0; + cOther =0; + + Tt =0; + } + }Count; + public: + char Text[80]; + unsigned char HasDraw4P0; + int IsShow; + + private: + + public: + TDevCount(){}; + void Init(); + void LoadPath0Item(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawShortList(void); + void DrawList(void); + void Show(void); + void ReDraw(void); + void GetOnePortCount(unsigned char aP0); + void RenderContent(void); + void DrawPortDevCount(unsigned char aP0); + void DrawPortDevCount(); + void FullRedraw(int Prm); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearPath(void); + + void GetTypeAndCount(); + int FindStartPoint(); + + void CheckNewLine(int aLen); + void ShowTypeList(unsigned char aP0, unsigned char Type1, unsigned char Type2, int Is2Type, char *p, int tLen); + + void FullRePaint(void); + void RePaint(void); + + void DevPropertyInit(void); + + void ClearSelectedLv0(void); + void Check4SelectedLv0(void); + + int ExtRequst(unsigned char Prm){ + IsShow = 0; + return 0; + } +}; + + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/DevMask.cpp b/MyCode/Gui/DevMask.cpp new file mode 100644 index 0000000..30ee5e2 --- /dev/null +++ b/MyCode/Gui/DevMask.cpp @@ -0,0 +1,2055 @@ +#include "DevMask.h" +#include "RuntimeData.h" +#include "record.h" + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" + #include "HW_config.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + + +#define dSdAddrMaskTemp dAddrSdRam_Commom +#define dMaskCountPerPage 32 +#define dMaskCountPerS4K 256 + +class TItemList *TDevMask::sIList; + +void TDevMask::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->部件屏蔽"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "回路号"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + TextRender_string24(Lv.Grid.Left[0] + 340, Lv.Grid.Top[0] +6, clNearWhite, "类型:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "状态:"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "地址号"); + TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, "注释信息:"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "二次码"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "分区号"); + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "设备定义"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "监管"); + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, "屏蔽", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 124, 30, 7, clNearWhite, "解除屏蔽", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Device Blocking"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "LoopID"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +6, clNearWhite, "Local"); + TextRender_string24(Lv.Grid.Left[0] + 340, Lv.Grid.Top[0] +6, clNearWhite, "Type:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "State"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "Addr "); + TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, " Note:"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "AuxID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "Assign"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "Fire"); + TextRender_string24(Lv.Grid.Left[3] +236, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "SUPV"); + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 4, clNearWhite, ItemColor, "OPR"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, "Mask", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 124, 30, 7, clNearWhite, " Clear ", 14, clNearBlack); + } +} + +void TDevMask::Init() +{ + IsPermission = 0; + Tag.Reset(); + + SettingData.IsGoMask = 0; + IsShow = 0; +} + +void TDevMask::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickSTextDType.Init(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] + 2, 240, 30, 0, 0, clNearWhite, ItemColor); + IList->STextState.Init(Lv.Grid.Left[0] + 730, Lv.Grid.Top[0] + 2, 68, 30, 0, 0, clNearWhite, ItemColor); + IList->STextRegisted.Init(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] + 36, 120, 30, 0, 0, clNearWhite, ItemColor); + IList->STextCtlNum.Init(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 6, 120, 30, 0, 0, clNearWhite, ItemColor); + + IList->EditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 2, 50, 30, 0, 0, 1, clNearWhite); + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + IList->EditDescpShow.Init(Lv.Grid.Left[0] + 390, Lv.Grid.Top[0] + 36, 400, 30, 0, 0, 1, clNearWhite); + + IList->STextDType.Enable = 0; + IList->STextDType.Visible =1; + IList->STextCtlNum.Enable = 1; + IList->STextCtlNum.Visible =1; + + IList->EditPortNum.SetMaxLen(2); + IList->EditAddrNum.SetMaxLen(3); + IList->EditDescpShow.SetMaxLen(3); + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible = 1; + IList->EditAddrNum.Enable = 1; + IList->EditAddrNum.Visible = 1; + IList->EditDescpShow.Enable = 0; + IList->EditDescpShow.Visible = 1; + + //User Code & Area Assign + + IList->EditUserCode.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 6, 108, 30, 0, 0, 1, clNearWhite); + IList->EditAreaAssign.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 40, 108, 30, 0, 0, 1, clNearWhite); + + IList->EditUserCode.Enable = 0; + IList->EditUserCode.Visible =1; + IList->EditUserCode.SetMaxLen(8); + IList->EditAreaAssign.Enable = 0; + IList->EditAreaAssign.Visible =1; + IList->EditAreaAssign.SetMaxLen(5); + + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 100,30,0,0,1,clNearBlack); + IList->Edit[0].Str.Clear(); + IList->Edit[0].Enable = 0; + IList->Edit[0].Visible = 1; + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 38, 156,30,0,0,clNearWhite, ItemColor); + IList->STextModuleInDefineType.Enable = 1; + IList->STextModuleInDefineType.Visible = 1; + if(LanguageEnCn==0)IList->STextModuleInDefineType.SetText("未定义",24); + else IList->STextModuleInDefineType.SetText("Undefine",24); + + IList->STextLastState.Init(Lv.Grid.Left[4] +120, Lv.Grid.Top[4] + 4, 156, 30, 0, 0, clNearWhite, ItemColor); + IList->STextLastState.TextClear(); + + IList->EditPortNum.SetText("01",24); + IList->EditAddrNum.SetText("001",24); + IList->EditDescpShow.SetText("------",24); + IList->EditUserCode.SetText("00000001",24); + IList->EditAreaAssign.SetText("0001",24); + IList->Edit[0].SetText("000",24); + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->EditDescpShow.Show(); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + IList->Edit[0].Show(); + IList->STextDType.Show(); + IList->STextModuleInDefineType.Show(); + + RedrawModuleInSignalInType(); + + Check4Selected(); + + + + Path0=1; + Path1=1; + Path0Avalble =1; + Path1Avalble =1; + ShowItemDetail(); +} + +void TDevMask::Show(void) +{ + IsShow = 1; + RenderBackGround(); + DrawSelf(); +} + +void TDevMask::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + RedrawCommonByExReturn(); + DrawHtInf(0); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + RedrawCommonByExReturn(); + DrawHtInf(1); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDevMask::RedrawCommonByExReturn() +{ + if( (Path0Avalble && Path1Avalble) ){ + if(IsRegisted){ + if(Port[Path0-1].ExistTable[Path1-1] == 0xA5){ + DrawState(Port[Path0-1].StateTable[Path1-1]); + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + IList->STextLastState.TextClear(); + } + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + IList->STextLastState.TextClear(); + } + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + IList->STextLastState.TextClear(); + } + + DrawFixText(); + + + TextDigitRender2Right24(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->STextCtlType.Show(); + + IList->STextDType.Show(); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + + IList->STextLastState.Show(); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); +} + +void TDevMask::DrawHtInf(int aPrm) +{ + +} + +void TDevMask::RedrawModuleInSignalInType() +{ + if(SignalInputType == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(SignalInputType == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(SignalInputType == 3){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevMask::ClearSelected() +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 1: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 2: + if(LanguageEnCn==0)tText="屏蔽"; else tText="Mask"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 3: + if(LanguageEnCn==0)tText="解除屏蔽"; else tText=" Clear "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 124, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +//______________________________________________________________________________________________________________________________ +void TDevMask::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 1: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 2: + if(LanguageEnCn==0)tText="屏蔽"; else tText="Mask"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 3: + if(LanguageEnCn==0)tText="解除屏蔽"; else tText=" Clear "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 124, 30, 7, clBlue, tText, 14, clNearWhite); + break; + } +} + +void TDevMask::GetMsgViaIndex(int aInx) +{ + volatile unsigned int sAddr; + if(aInx < CtlCenter.ieMsgMask.Count){ + sAddr = dAddrSdRam_MsgMask + aInx* 24; + MaskMsg.D32[0] = *(volatile unsigned int *)(sAddr + 0); + MaskMsg.D32[1] = *(volatile unsigned int *)(sAddr + 4); + MaskMsg.D32[2] = *(volatile unsigned int *)(sAddr + 8); + MaskMsg.D32[3] = *(volatile unsigned int *)(sAddr + 12); + MaskMsg.D32[4] = *(volatile unsigned int *)(sAddr + 16); + MaskMsg.D32[5] = *(volatile unsigned int *)(sAddr + 20); + } +} + +void TDevMask::ClearMsgViaIndex(int aInx) +{ + volatile unsigned int sAddr; + if(aInx < CtlCenter.ieMsgMask.Count){ + sAddr = dAddrSdRam_MsgMask + aInx* 24; + *(volatile unsigned int *)(sAddr + 0) = 0; + *(volatile unsigned int *)(sAddr + 4) = 0; + *(volatile unsigned int *)(sAddr + 8) = 0; + *(volatile unsigned int *)(sAddr + 12) = 0; + *(volatile unsigned int *)(sAddr + 16) = 0; + *(volatile unsigned int *)(sAddr + 20) = 0; + } +} + +void TDevMask::CopyMsgViaIndex(int aInx) +{ + volatile unsigned int sAddr; + sAddr = dAddrSdRam_MsgMask + aInx* 24; + + MaskMsg.Body.iByte0 = 0; + MaskMsg.Body.State = 1; + + *(volatile unsigned int *)(sAddr + 0) = MaskMsg.D32[0]; + *(volatile unsigned int *)(sAddr + 4) = MaskMsg.D32[1]; + *(volatile unsigned int *)(sAddr + 8) = MaskMsg.D32[2]; + *(volatile unsigned int *)(sAddr + 12) = MaskMsg.D32[3]; + *(volatile unsigned int *)(sAddr + 16) = MaskMsg.D32[4]; + *(volatile unsigned int *)(sAddr + 20) = MaskMsg.D32[5]; +} + +void TDevMask::GetTempMsgViaIndex(int aInx) +{ + volatile unsigned int sAddr; + if(aInx < ExistEntryCount){ + sAddr = dSdAddrMaskTemp + aInx* 24; + MaskMsg.D32[0] = *(volatile unsigned int *)(sAddr + 0); + MaskMsg.D32[1] = *(volatile unsigned int *)(sAddr + 4); + MaskMsg.D32[2] = *(volatile unsigned int *)(sAddr + 8); + MaskMsg.D32[3] = *(volatile unsigned int *)(sAddr + 12); + MaskMsg.D32[4] = *(volatile unsigned int *)(sAddr + 16); + MaskMsg.D32[5] = *(volatile unsigned int *)(sAddr + 20); + } +} + +void TDevMask::ClearTempMsgViaIndex(int aInx) +{ + volatile unsigned int sAddr; + if(aInx < ExistEntryCount){ + sAddr = dSdAddrMaskTemp + aInx* 24; + *(volatile unsigned int *)(sAddr + 0) = 0; + *(volatile unsigned int *)(sAddr + 4) = 0; + *(volatile unsigned int *)(sAddr + 8) = 0; + *(volatile unsigned int *)(sAddr + 12) = 0; + *(volatile unsigned int *)(sAddr + 16) = 0; + *(volatile unsigned int *)(sAddr + 20) = 0; + } +} + +void TDevMask::CopyTempMsgViaIndex(int aInx) +{ + volatile unsigned int sAddr; + sAddr = dSdAddrMaskTemp + aInx* 24; + + MaskMsg.Body.iByte0 = 0; + MaskMsg.Body.State = 1; + + *(volatile unsigned int *)(sAddr + 0) = MaskMsg.D32[0]; + *(volatile unsigned int *)(sAddr + 4) = MaskMsg.D32[1]; + *(volatile unsigned int *)(sAddr + 8) = MaskMsg.D32[2]; + *(volatile unsigned int *)(sAddr + 12) = MaskMsg.D32[3]; + *(volatile unsigned int *)(sAddr + 16) = MaskMsg.D32[4]; + *(volatile unsigned int *)(sAddr + 20) = MaskMsg.D32[5]; +} + + +void TDevMask::AddRemoveViaTempMsgList(unsigned char aP0, unsigned char aP1, unsigned int IsAdd) +{ + unsigned char P0, P1; + volatile unsigned int IsFound; + unsigned int FirstNullIndex, Cnt; + volatile int i; + TDMix aAddr; + P0 = aP0-1; P1 = aP1-1; + + if(P0 >= dPORT_MAX_COUNT)return; + IsFound = 0; + if(IsAdd){ + Port[P0].StateTable[P1] |= dEpStateBitMask; + for(i=0; i ieMSG_MASK_MAX_COUNT)FirstNullIndex = i; + }else + if( MaskMsg.D32[2] == aAddr.D32 ){ + ClearTempMsgViaIndex(i); + if(FirstNullIndex > ieMSG_MASK_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_MASK_MAX_COUNT){ + CopyTempMsgViaIndex(FirstNullIndex); + ClearTempMsgViaIndex(i); + FirstNullIndex++; + } + Cnt++; + } + } + ExistEntryCount = Cnt; + } +} + + +void TDevMask::AddRemoveViaCtlCenterMsg(unsigned char aP0, unsigned char aP1, unsigned int aUc, unsigned int IsAdd) +{ + unsigned char P0, P1; + volatile unsigned int IsFound; + unsigned int FirstNullIndex, Cnt; + volatile int i; + TDMix aAddr; + P0 = aP0-1; P1 = aP1-1; + + if(P0 >= dPORT_MAX_COUNT)return; + IsFound = 0; + if(IsAdd){ + Port[P0].StateTable[P1] |= dEpStateBitMask; + for(i=0; i ieMSG_MASK_MAX_COUNT)FirstNullIndex = i; + }else + if( MaskMsg.D32[2] == aAddr.D32 ){ + ClearMsgViaIndex(i); + if(FirstNullIndex > ieMSG_MASK_MAX_COUNT){ + FirstNullIndex = i; + } + CtlCenter.ieMsgMask.ReflashIndex++; + CtlCenter.ieGot = 1; + }else{ + if(FirstNullIndex < ieMSG_MASK_MAX_COUNT){ + CopyMsgViaIndex(FirstNullIndex); + ClearMsgViaIndex(i); + FirstNullIndex++; + } + Cnt++; + } + } + CtlCenter.ieMsgMask.Count = Cnt; + //EventShow.MsgList[4].Count = CtlCenter.ieMsgMask.Count; + //EventShow.MsgList[4].NewCount = CtlCenter.ieMsgMask.Count; + //EventShow.TryGetMaskData(2, 20240428); + } +} + +//_____________________________________________________________________________________________________________________________ +void TDevMask::DrawState(unsigned char aSta) +{ + if(aSta & dEpStateBitFire){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clRed, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("报警", 24); + else IList->STextState.SetText("Fire", 24); + }else + if(aSta & dEpStateBitStart){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("启动", 24); + else IList->STextState.SetText("ACT.", 24); + }else + if(aSta & dEpStateBitSv){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("监管", 24); + else IList->STextState.SetText("SUPV", 24); + }else + if(aSta & dEpStateBitFault){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("故障", 24); + else IList->STextState.SetText("FLT.", 24); + }else + if(aSta & dEpStateBitFeedBack){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("反馈", 24); + else IList->STextState.SetText("FB ", 24); + }else + if(aSta & dEpStateBitMask){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("屏蔽", 24); + else IList->STextState.SetText("Mask", 24); + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clDeepGreen, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("正常", 24); + else IList->STextState.SetText("IDLE", 24); + } + IList->STextState.Show(); +} + +void TDevMask::ShowItemDetail() +{ + int ClearInf = 0; + if( (Path0Avalble && Path1Avalble) ){ + if(Port[Path0-1].ExistTable[Path1-1] == 0xA5){ + IsRegisted = 1; + dType = Port[Path0-1].dTypeTable[Path1-1]; + AssignType = Port[Path0-1].AssignType[Path1-1]; + if(LanguageEnCn==0)IList->STextDType.SetText(StrHwType[dType],24); + else IList->STextDType.SetText(StrHwTypeEn[dType],24); + DrawState(Port[Path0-1].StateTable[Path1-1]); + if(LanguageEnCn==0){ + IList->STextRegisted.SetText("已注册", 24); + IList->STextModuleInDefineType.SetText(StrTypeShortName[AssignType],24); + }else{ + IList->STextRegisted.SetText("Registered", 24); + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[AssignType],24); + } + IList->Edit[0].Str.FromUInt3Dg(AssignType); + }else{ + IsRegisted = 0; + IList->STextDType.SetText("----", 24); + IList->STextState.SetText("----", 24); + if(LanguageEnCn==0)IList->STextRegisted.SetText("未注册", 24); + else IList->STextRegisted.SetText("Un Reg", 24); + IList->Edit[0].Str.FromStr("---"); + IList->STextModuleInDefineType.TextClear(); + } + unsigned int tAddr = dAddrSdRam_Descp + ((Path0-1) * 256 * 32) + ((Path1-1) * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + + IList->EditUserCode.Str.FromUInt8Dg(Port[Path0-1].UcList[Path1-1].Full); + IList->EditAreaAssign.Str.FromUInt4Dg(Port[Path0-1].Area[Path1-1]); + }else{ + IsRegisted = 0; + ClearInf = 1; + } + if(ClearInf){ + IList->STextDType.SetText("------",24); + IList->STextState.SetText("----", 24); + IList->STextRegisted.SetText("------", 24); + IList->EditDescpShow.Str.Text[0] = '\0'; + IList->EditDescpShow.Str.Text[1] = '\0'; + IList->EditUserCode.Str.FromStr("--------"); + IList->EditAreaAssign.Str.FromStr("----"); + IList->Edit[0].Str.FromStr("---"); + IList->STextModuleInDefineType.TextClear(); + + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + } + IList->STextDType.Show(); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + +} + +void TDevMask::sWaitChipIdle() +{ + volatile unsigned int Sta; + do{ + sDelayMs(10); + Sta = nor_get_busy_state(dFlashMaskChip); + }while(Sta); +} + +void TDevMask::WaitChipIdle2() +{ + volatile unsigned int Sta; + do{ + sDelayMs(10); + Sta = nor_get_busy_state(dFlashMaskChip); + }while(Sta); +} + +void TDevMask::ClearAllMask() +{ + unsigned int fAddr, i; + sWaitChipIdle(); + fAddr = dFlashAddrMask; + for(i=0; i<4; i++){ + WaitChipIdle2(); + nor_erase_sector_64k(dFlashMaskChip, fAddr); + fAddr = fAddr + SizeOf64K; + sDelayMs(200); + } + WaitChipIdle2(); +} + +void TDevMask::AddMaskMsg2TempList(int Index, TRecordMaskMsg aMsg) +{ + volatile unsigned int sAddr; + sAddr = dSdAddrMaskTemp + (Index * 24); + *(volatile unsigned int *)(sAddr + 0) = aMsg.D32[0]; + *(volatile unsigned int *)(sAddr + 4) = aMsg.D32[1]; + *(volatile unsigned int *)(sAddr + 8) = aMsg.D32[2]; + *(volatile unsigned int *)(sAddr + 12) = aMsg.D32[3]; + *(volatile unsigned int *)(sAddr + 16) = aMsg.D32[4]; + *(volatile unsigned int *)(sAddr + 20) = aMsg.D32[5]; + +} + +void TDevMask::AddMaskMsg2DymList(int Index, TRecordMaskMsg aMsg) +{ + volatile unsigned int sAddr; + sAddr = dAddrSdRam_MsgMask + (Index * 24); + *(volatile unsigned int *)(sAddr + 0) = aMsg.D32[0]; + *(volatile unsigned int *)(sAddr + 4) = aMsg.D32[1]; + *(volatile unsigned int *)(sAddr + 8) = aMsg.D32[2]; + *(volatile unsigned int *)(sAddr + 12) = aMsg.D32[3]; + *(volatile unsigned int *)(sAddr + 16) = aMsg.D32[4]; + *(volatile unsigned int *)(sAddr + 20) = aMsg.D32[5]; + +} + +int TDevMask::ReadMaskFromFlash2Temp(int xArea) +{ + volatile int i, x, PathAva; + volatile unsigned int BaseAddr, fAddr, MaskCount, suExit; + unsigned char tP0,tP1; + TRecordMaskMsg tMaskMsg; + + MaskCount = 0; + sWaitChipIdle(); + + //Page Count = (ieMSG_MASK_MAX_COUNT=10000 * EntrySize=16) / 16 = 10000; + + for(i=0; i4)ToBeErase64K_Count=4; + sWaitChipIdle(); + for(i=0; i 0){ + suExit = 0; + ToWritePage = ExistEntryCount / 16 +1; + for(i=0; i 0){ + suExit = 0; + ToWritePage = ExistEntryCount / 16 +1; + for(i=0; i 0){ + suExit = 0; + ToWritePage = CtlCenter.ieMsgMask.Count / 16 +1; + for(i=0; i 0){ + suExit = 0; + ToWritePage = CtlCenter.ieMsgMask.Count / 16 +1; + for(i=0; iCrc = rCrc; + Crc32Feed(rCnt); + if(MaskCount==0 and rCnt==0 and rCrc==dMaskNonDataIdf){ + if(CrcFlag){ + CrcFlag=0; + CtlCenter.ieAddBrdFaultCancel(41,TBoardFaultType::StorageMaskData); + } + }else{ + if(Error==0 and rCrc==Crc32GetResult()){ + if(CrcFlag){ + CrcFlag=0; + CtlCenter.ieAddBrdFaultCancel(41,TBoardFaultType::StorageMaskData); + } + }else{ + //error here + CrcFlag=1; + CtlCenter.ieAddBrdFault(41,TBoardFaultType::StorageMaskData); + } + } + return MaskCount; +} + +int TDevMask::ReadMaskFromFlash() +{ + volatile int i, x; + volatile unsigned int fAddr, sAddr, MaskCount, suExit, tUc; + volatile unsigned int ExistCode, rCrc, rCnt, GetSta; + int GoReadAndWrite; + TRecordMaskMsg tMaskMsg; + TRecordCommon aRC; + + MaskCount = 0; + + //Page Count = (ieMSG_MASK_MAX_COUNT=10000 * EntrySize=16) / 16 = 10000; + for(i=0; i 0){ + suExit = 0; + int ToWritePage = rCnt / 16 +1; + for(i=0; iCrc = rCrc; + Crc32Feed(rCnt); + if(MaskCount==0 and rCnt==0 and rCrc==dMaskNonDataIdf){ + if(CrcFlag){ + CrcFlag=0; + CtlCenter.ieAddBrdFaultCancel(41,TBoardFaultType::StorageMaskData); + } + }else{ + if(Error==0 and rCrc==Crc32GetResult()){ + if(CrcFlag){ + CrcFlag=0; + CtlCenter.ieAddBrdFaultCancel(41,TBoardFaultType::StorageMaskData); + } + }else{ + //error here + CrcFlag=1; + CtlCenter.ieAddBrdFault(41,TBoardFaultType::StorageMaskData); + } + } + return MaskCount; +} + + +void TDevMask::PermissionCmdReturnDraw() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + +} + +void TDevMask::PermissionCmdGO() +{ + TDMix aFullPath; + unsigned int tUc; + if(PermissionCmd){ + SettingData.TimeOutTick = 0; + SettingData.RecOK = 0; + SettingData.IsGoMask = 1; + SendToDevice(1); + IList->STextLastState.TextClear(); + IList->STextLastState.Show(); + }else{ + if(Path0 && (Path0 <= dPORT_MAX_COUNT)){ + + }else{ + return; + } + if(MainCtl.fData.Split.ExistTablePort[Path0-1] == 0xA5){ + SettingData.TimeOutTick = 0; + SettingData.RecOK = 0; + SettingData.IsGoMask = 2; + SendToDevice(0); + IList->STextLastState.TextClear(); + IList->STextLastState.Show(); + }else{ + if(MainCtl.fData.Split.NetworkMode == 1){ + if(1){ + aFullPath.D8[0] = MainCtl.fData.Split.MyNum; + aFullPath.D8[1] = Path0; + aFullPath.D8[2] = Path1; + aFullPath.D8[3] = Path0; + tUc = 0; + if(Path0 && Path1){ + if( (Path0 <=dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tUc = Port[Path0-1].UcList[Path1-1].Full; + } + } + Record.OperateAdd_UnMask(aFullPath, dType, tUc); + ExistEntryCount = ReadMaskFromFlash2Temp(0); + AddRemoveViaTempMsgList(Path0, Path1,0); + WriteToFlashMaster(); + ExistEntryCount = ReadMaskFromFlash2Temp(0); + CombMsg4Master(); + (void)CheckStorageData(); + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); + if(CrcFlag==0){ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消成功",24); + else IList->STextLastState.SetText("Clear OK ",24); + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消失败",24); + else IList->STextLastState.SetText("Clr Failed",24); + } + IList->STextLastState.Show(); + SettingData.IsGoMask = 0; + + if(CtlCenter.ieMsgMask.Count == 0){ + if(AlarmSoundWhat > 3)AlarmSoundWhat = 0x07; + } + } + }else{ + if(1){ + aFullPath.D8[0] = MainCtl.fData.Split.MyNum; + aFullPath.D8[1] = Path0; + aFullPath.D8[2] = Path1; + aFullPath.D8[3] = 0; + tUc = 0; + if(Path0 && Path1){ + if( (Path0 <=dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tUc = Port[Path0-1].UcList[Path1-1].Full; + } + } + Record.OperateAdd_UnMask(aFullPath, dType, tUc); + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); + AddRemoveViaCtlCenterMsg(Path0, Path1, tUc, 0); + WriteToFlashSlave(); + CtlCenter.MaskCountSet(ReadMaskFromFlash()); + if(CrcFlag==0){ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消成功",24); + else IList->STextLastState.SetText("Clear OK ",24); + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消失败",24); + else IList->STextLastState.SetText("Clr Failed",24); + } + IList->STextLastState.Show(); + SettingData.IsGoMask = 0; + + if(CtlCenter.ieMsgMask.Count == 0){ + if(AlarmSoundWhat > 3)AlarmSoundWhat = 0x07; + } + } + } + } + } +} + +void TDevMask::CheckToDo() +{ + unsigned char tDType, tSta; + if( (Path0Avalble) && (Path1Avalble) ){ + tDType = Port[Path0-1].dTypeTable[Path1-1]; + tSta = Port[Path0-1].StateTable[Path1-1]; + if( (tDType == dgTYPE_HAND_REPORT) || (tDType == dgType_VAALRAM) ){ + SettingData.DevTypeNotAllow = 1; + }else{ + SettingData.DevTypeNotAllow = 0; + } + if( tSta & (dEpStateBitFire + dEpStateBitStart + dEpStateBitSv + dEpStateBitFault + dEpStateBitFeedBack + dEpStateBitDelayStart) ) { + SettingData.DevStateNotAllow = 1; + }else{ + SettingData.DevStateNotAllow = 0; + } + SettingData.PathError = 0; + }else{ + SettingData.PathError = 1; + } +} + +int TDevMask::CheckInputErrState(int IsMask) +{ + if(SettingData.PathError){ + if(LanguageEnCn==0)IList->STextLastState.SetText("路径错误",24); + else IList->STextLastState.SetText("Path Err ",24); + IList->STextLastState.Show(); + return 0; + }else + if(SettingData.DevStateNotAllow){ + if(LanguageEnCn==0)IList->STextLastState.SetText("状态不允许",24); + else IList->STextLastState.SetText("State Err",24); + IList->STextLastState.Show(); + return 0; + }else + if(SettingData.DevTypeNotAllow){ + if(LanguageEnCn==0)IList->STextLastState.SetText("类型不允许",24); + else IList->STextLastState.SetText("DType Err",24); + IList->STextLastState.Show(); + return 0; + } + if(IsMask){ + if(CtlCenter.ieMsgMask.Count >= ieMSG_MASK_MAX_COUNT){ + if(LanguageEnCn==0)IList->STextLastState.SetText("数量达上限",24); + else IList->STextLastState.SetText("Count Err",24); + IList->STextLastState.Show(); + return 0; + } + } + return 1; +} + + +TGuiMsgReturn TDevMask::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + unsigned char aType; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + } + + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx == 0){ + IList->EditPortNum.KeyIn(aKey); + int iVal = IList->EditPortNum.Str.ToInteger(); + if( (iVal > 0) && (iVal <= dPORT_MAX_COUNT) ){ + IList->EditPortNum.SelectedColor = clBlue; + Path0 = iVal; + Path0Avalble = 1; + }else{ + IList->EditPortNum.SelectedColor = clRed; + Path0Avalble = 0; + } + IList->EditPortNum.Show(); + ShowItemDetail(); + }else + if(Tag.Inx == 1){ + IList->EditAddrNum.KeyIn(aKey); + int iVal = IList->EditAddrNum.Str.ToInteger(); + if( (iVal > 0) && (iVal <= dEP_MAX_COUNT_PER_PORT) ){ + IList->EditAddrNum.SelectedColor = clBlue; + Path1 = iVal; + Path1Avalble = 1; + }else{ + IList->EditAddrNum.SelectedColor = clRed; + Path1Avalble = 0; + } + IList->EditAddrNum.Show(); + ShowItemDetail(); + } + break; + } + if(aKey == VK_UP){ + if(Tag.Inx>0){ + if(Tag.Inx == 1){ + if(Path1Avalble){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }else{ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }else{ + if(Path0Avalble){ + ClearSelected(); + Tag.Inx=3; + Check4Selected(); + } + } + }else + if(aKey == VK_DOWN){ + if(Tag.Inx<3){ + if(Tag.Inx == 0){ + if(Path0Avalble){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx == 1){ + if(Path1Avalble){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else{ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else{ + ClearSelected(); + Tag.Inx=0; + Check4Selected(); + } + }else + if(aKey == VK_F1){ + //Go Modify + }else + if(aKey == VK_TAB){ + + } + if(aKey == VK_EXECUTE){ + //Save Data Here + //Addr Mode + if(Path0Avalble && Path1Avalble && (IsRegisted || (Tag.Inx == 3) ) ){ + if(Tag.Inx == 2){ + //Triget To Mask Here + CheckToDo(); + if(CheckInputErrState(1)){ + if(SystemPermission > 1){ + PermissionCmd = 1; + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + }else + if(Tag.Inx == 3){ + //Triget To UnMask Here + CheckToDo(); + if(CheckInputErrState(0)){ + if(SystemPermission > 1){ + PermissionCmd = 0; + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = 0; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + }else + if(aKey == VK_RETURN){ + IsShow = 0; + SettingData.IsGoMask = 0; + SettingData.RecOK = 0; + aMsg = guiMsgReturn; + } + return aMsg; +} + +void TDevMask::SendToDevice(int IsAdd) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + if(IsAdd == 1){ + aIde.BitF.Cmd = cmEpDeviceMask; + }else{ + aIde.BitF.Cmd = cmEpDeviceMaskRemove; + } + + Len = 4; + + //Prm + Data[0] = 0; + Data[1] = 0; + Data[2] = Path0; + Data[3] = Path1; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + //InnerCan.CmdSendCustom(aIde, Data, Len); + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TDevMask::PushOneDataRec(unsigned char aCmd, unsigned char CtlNum, unsigned char aP0, unsigned char aP1) +{ + if(IsShow){ + if(SettingData.IsGoMask == 1){ + if(aCmd == cmEpDeviceMask){ + if( (aP0 == Path0) && (aP1 == Path1) ) { + SettingData.RecOK = 1; + } + } + }else + if(SettingData.IsGoMask == 2){ + if(aCmd == cmEpDeviceMaskRemove){ + if( (aP0 == Path0) && (aP1 == Path1) ) { + SettingData.RecOK = 1; + } + } + } + } +} + +void TDevMask::Task1000Ms() +{ + TDMix aFullPath; + unsigned int tUc; + if(IsSelfChecking)return; + if(IsShow){ + if( (Path0) and (Path1 ) ){ + if( (Path0 <= dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + if(IsRegisted){ + const unsigned char tSta = Port[Path0-1].StateTable[Path1-1]; + DrawState(tSta); + } + } + } + if(SettingData.IsGoMask){ + SettingData.TimeOutTick++; + if(SettingData.TimeOutTick > 6){ + SettingData.IsGoMask = 0; + if(LanguageEnCn==0)IList->STextLastState.SetText("操作失败",24); + else IList->STextLastState.SetText("OPR Fail",24); + IList->STextLastState.Show(); + }else{ + if(MainCtl.fData.Split.NetworkMode == 1){ + if(SettingData.IsGoMask == 1){ + if(SettingData.RecOK){ + aFullPath.D8[0] = MainCtl.fData.Split.MyNum; + aFullPath.D8[1] = Path0; + aFullPath.D8[2] = Path1; + aFullPath.D8[3] = 0; + tUc = 0; + if(Path0 && Path1){ + if( (Path0 <=dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tUc = Port[Path0-1].UcList[Path1-1].Full; + } + } + Record.OperateAdd_Mask(aFullPath, dType, tUc); + ExistEntryCount = ReadMaskFromFlash2Temp(0); + AddRemoveViaTempMsgList(Path0, Path1,1); + WriteToFlashMaster(); + ExistEntryCount = ReadMaskFromFlash2Temp(0); + CombMsg4Master(); + (void)CheckStorageData(); + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); + if(CrcFlag==0){ + if(LanguageEnCn==0)IList->STextLastState.SetText("屏蔽成功",24); + else IList->STextLastState.SetText("Blocked OK",24); + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("屏蔽失败",24); + else IList->STextLastState.SetText("Blk Failed",24); + } + IList->STextLastState.Show(); + SettingData.IsGoMask = 0; + + if(CtlCenter.ieMsgMask.Count >0){ + if(AlarmSoundWhat > 3)AlarmSoundWhat = 4; + } + } + }else + if(SettingData.IsGoMask == 2){ + if(SettingData.RecOK){ + aFullPath.D8[0] = MainCtl.fData.Split.MyNum; + aFullPath.D8[1] = Path0; + aFullPath.D8[2] = Path1; + aFullPath.D8[3] = Path0; + tUc = 0; + if(Path0 && Path1){ + if( (Path0 <=dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tUc = Port[Path0-1].UcList[Path1-1].Full; + } + } + Record.OperateAdd_UnMask(aFullPath, dType, tUc); + ExistEntryCount = ReadMaskFromFlash2Temp(0); + AddRemoveViaTempMsgList(Path0, Path1,0); + WriteToFlashMaster(); + ExistEntryCount = ReadMaskFromFlash2Temp(0); + CombMsg4Master(); + (void)CheckStorageData(); + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); + if(CrcFlag==0){ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消成功",24); + else IList->STextLastState.SetText("Clear OK ",24); + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消失败",24); + else IList->STextLastState.SetText("Clr Failed",24); + } + IList->STextLastState.Show(); + SettingData.IsGoMask = 0; + + if(CtlCenter.ieMsgMask.Count == 0){ + if(AlarmSoundWhat > 3)AlarmSoundWhat = 0x07; + } + } + } + }else{ + if(SettingData.IsGoMask == 1){ + if(SettingData.RecOK){ + aFullPath.D8[0] = MainCtl.fData.Split.MyNum; + aFullPath.D8[1] = Path0; + aFullPath.D8[2] = Path1; + aFullPath.D8[3] = 0; + tUc = 0; + if(Path0 && Path1){ + if( (Path0 <=dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tUc = Port[Path0-1].UcList[Path1-1].Full; + } + } + Record.OperateAdd_Mask(aFullPath, dType, tUc); + AddRemoveViaCtlCenterMsg(Path0, Path1,tUc,1); + WriteToFlashSlave(); + CtlCenter.MaskCountSet(ReadMaskFromFlash()); + if(CrcFlag==0){ + if(LanguageEnCn==0)IList->STextLastState.SetText("屏蔽成功",24); + else IList->STextLastState.SetText("Blocked OK",24); + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("屏蔽失败",24); + else IList->STextLastState.SetText("Blk Failed",24); + } + IList->STextLastState.Show(); + SettingData.IsGoMask = 0; + + if(CtlCenter.ieMsgMask.Count >0){ + if(AlarmSoundWhat > 3)AlarmSoundWhat = 4; + } + } + }else + if(SettingData.IsGoMask == 2){ + if(SettingData.RecOK){ + aFullPath.D8[0] = MainCtl.fData.Split.MyNum; + aFullPath.D8[1] = Path0; + aFullPath.D8[2] = Path1; + aFullPath.D8[3] = 0; + tUc = 0; + if(Path0 && Path1){ + if( (Path0 <=dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tUc = Port[Path0-1].UcList[Path1-1].Full; + } + } + Record.OperateAdd_UnMask(aFullPath, dType, tUc); + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); + AddRemoveViaCtlCenterMsg(Path0, Path1, tUc, 0); + WriteToFlashSlave(); + CtlCenter.MaskCountSet(ReadMaskFromFlash()); + if(CrcFlag==0){ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消成功",24); + else IList->STextLastState.SetText("Clear OK ",24); + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("取消失败",24); + else IList->STextLastState.SetText("Clr Failed",24); + } + IList->STextLastState.Show(); + SettingData.IsGoMask = 0; + + if(CtlCenter.ieMsgMask.Count == 0){ + if(AlarmSoundWhat > 3)AlarmSoundWhat = 0x07; + } + } + } + } + } + } + } +} + +void TDevMask::RecallCrcFaultMsg() +{ + if(CrcFlag) + CtlCenter.ieAddBrdFault(41,TBoardFaultType::StorageMaskData); +} + +void TDevMask::sRecoverSetDefault() +{ + volatile int i, x, aInx; + volatile unsigned int fAddr, AddrSd; + volatile unsigned int GetSta; + + //User Code and Assign Type + //First 32 Port + if(sIList==nullptr)return; + sIList->ReadWriteData.Reset(); + + LoopCheck1S(); + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashMaskChip); + }while(GetSta); + + fAddr = dFlashAddrMask; + for(i=0; i<4; i++){ + LoopCheck1S(); + nor_erase_sector_64k(dFlashMaskChip, fAddr); + sDelayMs(400); + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashMaskChip); + }while(GetSta); + fAddr = fAddr + SizeOf64K; + } + //Mark Crc 4 None Data + fAddr = dFlashAddrMask + dMaskCrcCntOffset; + sIList->ReadWriteData.D32[0] = 0; + sIList->ReadWriteData.D32[1] = dMaskNonDataIdf; + nor_write_page(dFlashMaskChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashMaskChip); + }while(GetSta); + + //Clear Backup + fAddr = dFlashAddrMask_II; + for(i=0; i<4; i++){ + LoopCheck1S(); + nor_erase_sector_64k(dFlashMaskChip, fAddr); + sDelayMs(400); + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashMaskChip); + }while(GetSta); + fAddr = fAddr + SizeOf64K; + } + + LoopCheck1S(); + CtlCenter.CrcFlag.Mask =0; + CtlCenter.ieMsgMask.Count = 0; + CtlCenter.ieMsgMask.ReflashIndex++; + for(i=0; i批量查询模块输出端口检线"); //"工程->批量设置模块输出端口检线"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "本机可输出模块数量:"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "设定回路地址段以查询"); //"单回路地址段查询或配置"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "回路号"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 72, clNearWhite, ItemColor, "起始地址"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 106, clNearWhite, ItemColor, "结束地址"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 140, clNearWhite, ItemColor, "检线设定"); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 8, clNearWhite, ItemColor, "查询"); //"查询或执行设定"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, "开始查询", 14, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, "保存配置", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Project->Output Line Inspection"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "Modules with Output"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "Set The Scope Of One Loop"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "Loop:"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 72, clNearWhite, ItemColor, "Begin Ad"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 106, clNearWhite, ItemColor, "End Addr"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 140, clNearWhite, ItemColor, "Inspect "); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 8, clNearWhite, ItemColor, "Query"); //"Query Or Set"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, " Query ", 14, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, " Config ", 14, clNearBlack); + } +} + +void TDevOutputCfg::Init() +{ + IsPermission = 0; + Path0 = 1; + StartAddr = 1; + EndAddr = 250; + State = Idle; + Tag.Inx = 0; + WriteResult =0; + WritingCfByte =0; + IList = nullptr; + + KeepOnMeJustEnter = nullptr; + KeepUiOnMe = nullptr; +} + +void TDevOutputCfg::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDevOutputCfg::DrawSelf(void) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + + for(int i=0; iEdit[0].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 36, 100,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(2); + IList->Edit[0].Str.Clear(); + TMyString::sFrom2Dg(Path0,Text); + IList->Edit[0].SetText(Text, 24); + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + + IList->Edit[1].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 70, 100,30,0,0,1,clNearBlack); + IList->Edit[1].SetMaxLen(3); + IList->Edit[1].Str.Clear(); + TMyString::sFrom3Dg(StartAddr,Text); + IList->Edit[1].SetText(Text, 24); + IList->Edit[1].Show(); + + IList->Edit[2].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 104, 100,30,0,0,1,clNearBlack); + IList->Edit[2].SetMaxLen(3); + IList->Edit[2].Str.Clear(); + TMyString::sFrom3Dg(EndAddr,Text); + IList->Edit[2].SetText(Text, 24); + IList->Edit[2].Show(); + + IList->Edit[3].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 138, 100,30,0,0,1,clNearBlack); + RedrawCfgByte(); + + DrawFixText(); + + InitReadData(); + Check4Selected(); + +} + +void TDevOutputCfg::Show() +{ + IsShow = 1; + DrawSelf(); +} + +void TDevOutputCfg::Init4DrawRead() +{ + unsigned int x, y, x2, y2, w, h; + + Bound.SetBySize(0, 36, 800, 406); + Content.Set(Bound.Left +3, Bound.Top+3 + 30, Bound.Right-4, Bound.Bottom -4); + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clNearWhite); + + #define GS 24 + #define TS 96 + + unsigned int aLeft, aTop, aTopR; + + aLeft = Content.Left + 10; + aTop = Content.Top +4; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "回路"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Loop"); + TextDigitRender2_24(aLeft +50, aTop, clNearBlack, clNearWhite, Path0); + + aLeft = Content.Left + 170; + aTop = Content.Top +4; + aTopR = Content.Top +6; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clSilver); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "非输出"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Others"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clRed); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "未读"); + else TextRender_string24(aLeft,aTop,clNearBlack, "UnRead"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clBlue); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "不检线"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Ignore"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clDeepGreen); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "检线"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Inspect"); + + aLeft += TS; +} + +void TDevOutputCfg::Draw4Read() +{ + int a, x,y,t,b; + unsigned char p = Path0-1; + unsigned int tClr; + RectFillRender(Content.Left, Content.Top + 30, Content.Right, Content.Bottom, clNearWhite); + if(p>dPORT_MAX_COUNT)return; + if(IList == nullptr)return; + for(a=0; aReadWriteData.D8[a+1]){ + if(IList->RealtimeData.Data[0][a+1]){ + //Is Setting Check + tClr = clDeepGreen; + }else{ + //Is Not Setting Check + tClr = clBlue; + } + }else{ + //Still wait for Done This Addr + tClr = clRed; + } + RectFillRender( svGrid1X[x], t, svGrid1X2[x], b, tClr); + }else{ + RectFillRender( svGrid1X[x], t, svGrid1X2[x], b, clSilver); + } + TMyString::sFrom3Dg(a+1, Text); + lcd_draw_str_8x16( svGrid1X[x]+6, t+5, clNearWhite, Text); + } + } +} + +void TDevOutputCfg::FullRedraw(int Prm) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Show(); + IList->Edit[1].Show(); + IList->Edit[2].Show(); + RedrawCfgByte(); + + DrawFixText(); + + Check4Selected(); + if(State != RangeReading){ + DrawWriteResult(); + } + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); +} + +void TDevOutputCfg::PermissionCmdReturnDraw() +{ + FullRedraw(1); +} + +void TDevOutputCfg::RedrawCfgByte() +{ + if(IList == nullptr)return; + if(LanguageEnCn==0){ + if(WritingCfByte) + IList->Edit[3].SetText("检线", 24); + else + IList->Edit[3].SetText("不检线", 24); + }else{ + if(WritingCfByte) + IList->Edit[3].SetText("Inspect", 24); + else + IList->Edit[3].SetText("Ignore", 24); + } + IList->Edit[3].Show(); +} + +void TDevOutputCfg::DrawWriteResult() +{ + if(LanguageEnCn==0){ + if(WriteResult == 0){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, " "); + }else + if(WriteResult == 1){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "写入成功 "); + }else + if(WriteResult == 2){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "写入失败 "); + }else + if(WriteResult == 3){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "正在写入 "); + } + }else{ + if(WriteResult == 0){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, " "); + }else + if(WriteResult == 1){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Wrote OK "); + }else + if(WriteResult == 2){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Failed To Write"); + }else + if(WriteResult == 3){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Writing "); + } + } +} + +void TDevOutputCfg::DrawWriteTime() +{ + unsigned int tClr; + if(IsSelfChecking != 0)return; + if(RunData.WaitTick < 300)tClr = clNearWhite; else tClr = clRed; + if(LanguageEnCn==0)TextRender_string24(TipPoint.x+220, TipPoint.y, clNearWhite, ContentColor, "用时: "); + else TextRender_string24(TipPoint.x+220, TipPoint.y, clNearWhite, ContentColor, "Time: "); + TextDigitRender3_24(TipPoint.x+220+60, TipPoint.y, tClr, ContentColor, RunData.WaitTick); +} + +void TDevOutputCfg::DrawWriteResult(unsigned char aResult) +{ + WriteResult = aResult; + DrawWriteResult(); +} + +void TDevOutputCfg::InitReadData() +{ + int i; + RunData.WaitTick =0; + RunData.RecReadUpData = 0; + if(IList == nullptr)return; + IList->ReadWriteData.Reset(); + IList->RealtimeData.Reset(); +} + +void TDevOutputCfg::InitWriteData() +{ + RunData.WaitTick =0; + RunData.RecWriteOk =0; +} + +void TDevOutputCfg::CheckHostCount() +{ + int x,y; + Count.Total =0; + for(x=0; xEdit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 1: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + case 2: + IList->Edit[2].Selected = 0; + IList->Edit[2].Show(); + break; + case 3: + IList->Edit[3].Selected = 0; + IList->Edit[3].Show(); + break; + case 4: + if(LanguageEnCn==0)tText="开始查询"; else tText=" Query "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 5: + if(LanguageEnCn==0)tText="保存配置"; else tText=" Config "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +void TDevOutputCfg::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 1: + IList->Edit[1].Selected = 1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + case 2: + IList->Edit[2].Selected = 1; + IList->Edit[2].SetPstTail(); + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + break; + case 3: + IList->Edit[3].Selected = 1; + IList->Edit[3].Show(); + break; + case 4: + if(LanguageEnCn==0)tText="开始查询"; else tText=" Query "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 5: + if(LanguageEnCn==0)tText="保存配置"; else tText=" Config "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + } +} + +void TDevOutputCfg::PushInnerCanData(unsigned char aCmd, unsigned char *pBuf) +{ + if(aCmd == cmQueryStaticDataAddrSegment){ + //Read + if(IList == nullptr)return; + if(State == RangeReading){ + if( (pBuf[1] == Path0) && (pBuf[2] >= StartAddr) && (pBuf[2] <= EndAddr) && (pBuf[3] == 0x08) ){ + IList->ReadWriteData.D8[pBuf[2]] =1; + IList->RealtimeData.Data[0][pBuf[2]] = pBuf[4]; + RunData.RecReadUpData = 1; + } + } + }else + if(aCmd == cmSetConfigAddrSegment){ + //Write + if(State == RangeWriting){ + if( (pBuf[1] == Path0) && (pBuf[2] == StartAddr) && (pBuf[3] == EndAddr) && (pBuf[4] == 0x08) && (pBuf[5] == WritingCfByte) ){ + RunData.RecWriteOk = 1; + } + } + } +} + +void TDevOutputCfg::SendCmdReadOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =5; + + aIde.BitF.Cmd = cmQueryStaticDataAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = aPort; + Data[2] = aStartAddr; + Data[3] = aEndAddr; + Data[4] = 0x08; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TDevOutputCfg::SendCmdReadOutputIsCheckAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =5; + + aIde.BitF.Cmd = cmQueryStaticDataAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 255; + Data[2] = 0; + Data[3] = 0; + Data[4] = 0; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TDevOutputCfg::SendCmdWriteOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr, unsigned char aSet) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =6; + + aIde.BitF.Cmd = cmSetConfigAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = aPort; + Data[2] = aStartAddr; + Data[3] = aEndAddr; + Data[4] = 0x08; + Data[5] = aSet; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + + +TGuiMsgReturn TDevOutputCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char tCtlNum, aCc, Ow, Err; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + } + + if(State == RangeReading){ + switch(aKey){ + case VK_RETURN: + State = Idle; + SendCmdReadOutputIsCheckAbort(); + FullRedraw(1); + break; + } + }else + if(State == RangeWriting){ + switch(aKey){ + case VK_RETURN: + State =Idle; + IsShow = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Tag.Inx ==0){ + IList->Edit[0].KeyIn(aKey); + aCc = IList->Edit[0].Str.ToInteger(); + if( (aCc == 0) || (aCc > dPORT_MAX_COUNT) ){ + IList->Edit[0].SelectedColor = clRed; + }else{ + IList->Edit[0].SelectedColor = clBlue; + } + Path0 = aCc; + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + }else + if(Tag.Inx ==1){ + IList->Edit[1].KeyIn(aKey); + aCc = IList->Edit[1].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[1].SelectedColor = clRed; + }else{ + IList->Edit[1].SelectedColor = clBlue; + } + StartAddr = aCc; + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + }else + if(Tag.Inx ==2){ + IList->Edit[2].KeyIn(aKey); + aCc = IList->Edit[2].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[2].SelectedColor = clRed; + }else{ + IList->Edit[2].SelectedColor = clBlue; + } + EndAddr = aCc; + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + }else + if(Tag.Inx ==3){ + WritingCfByte = WritingCfByte ? 0: 1; + RedrawCfgByte(); + }/*else + if(Tag.Inx ==4){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx ==5){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }*/ + break; + case VK_UP: + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx <4){ + //if(Tag.Inx <5){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + if(Tag.Inx ==3){ + WritingCfByte = WritingCfByte ? 0: 1; + RedrawCfgByte(); + } + break; + case dfKEY_QUERY: + + break; + case VK_EXECUTE: + if(Tag.Inx == 4){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + PermissionCmd = 0; + PermissionCmdGO(); + } + } + }else + if(Tag.Inx == 5){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[1] +300, Lv.Grid.Top[1] + 16, 400, 140, 3); + } + } + } + } + break; + case VK_RETURN: + State =Idle; + IsShow = 0; + if(State == RangeReading)SendCmdReadOutputIsCheckAbort(); + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TDevOutputCfg::PermissionCmdGO() +{ + if(PermissionCmd == 0){ + //Go Action + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + InitReadData(); + State = RangeReading; + SendCmdReadOutputIsCheck(Path0, StartAddr, EndAddr); + Init4DrawRead(); + Draw4Read(); + } + } + }else + if(PermissionCmd == 1){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + DrawWriteResult(3); + State = RangeWriting; + RunData.WaitTick = 0; + SendCmdWriteOutputIsCheck(Path0, StartAddr, EndAddr, WritingCfByte); + } + } + } +} + +void TDevOutputCfg::Task1000Ms() +{ + if(IsShow == 0)return; + if(State == RangeReading){ + if(RunData.WaitTick<120){ + RunData.WaitTick++; + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + } + if(RunData.RecReadUpData){ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + RunData.RecReadUpData = 0; + Draw4Read(); + } + } + }else + if(State == RangeWriting){ + RunData.WaitTick++; + DrawWriteTime(); + if(RunData.WaitTick <360){ + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + if(RunData.RecWriteOk){ + //Write Ok + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawWriteResult(1); + }else{ + WriteResult = 1; + } + State = Idle; + } + }else{ + //Write Fail + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawWriteResult(2); + }else{ + WriteResult = 2; + } + State = Idle; + } + } +} + +int TDevOutputCfg::ExtRequst(unsigned char Prm) +{ + IsShow = 0; + if(State == RangeReading)SendCmdReadOutputIsCheckAbort(); + State =Idle; + return 0; +} + diff --git a/MyCode/Gui/DevOutputCfg.h b/MyCode/Gui/DevOutputCfg.h new file mode 100644 index 0000000..964526d --- /dev/null +++ b/MyCode/Gui/DevOutputCfg.h @@ -0,0 +1,177 @@ +#ifndef DEVOUTPUTCFG_H_ +#define DEVOUTPUTCFG_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" + + +class TDevOutputCfg{ + public: + static constexpr unsigned short hList[12] = {38,184,78,28, 26,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 220, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 72, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1 + 72 -1, + }; + static constexpr TPoint TipPoint ={ + .x = 16, + .y = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + 6, + }; + typedef enum{ + Idle =0, + RangeReading =1, + RangeWriting + }TState; + public: + class TItemList *IList; + void (*KeepOnMeJustEnter)(void); + void (*KeepUiOnMe)(void); + TRect Bound; + TRect Content; + unsigned char Path0; + unsigned char StartAddr; + unsigned char EndAddr; + unsigned char WritingCfByte; + + struct{ + unsigned int Port; + unsigned int Total; + }Count; + + struct{ + unsigned int WaitTick; + unsigned char RecReadUpData; + unsigned char RecWriteOk; + unsigned char Dump0; + unsigned char Dump1; + }RunData; + TState State; + + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + void Reset(){ + Inx = 0; + InxMin = 0; + InxMax =2; + } + }Tag; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char IsShow; + unsigned char WriteResult; + + unsigned int fAddr; + + unsigned char Data[12]; + char Text[12]; + + public: + TDevOutputCfg(){ + IsShow = 0; + State = Idle; + }; + void Init(); + void RenderBackGround(void); + + void DrawSelf(void); + void Show(); + void FullRedraw(int Prm); + void RedrawCfgByte(); + void Init4DrawRead(); + void Draw4Read(); + void DrawFixText(); + + void DrawWriteTime(); + void DrawWriteResult(); + void DrawWriteResult(unsigned char aResult); + + void DelayMs(unsigned int aMs); + + void CheckHostCount(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void ClearSelected(void); + void Check4Selected(); + + void InitReadData(); + void InitWriteData(); + void PushInnerCanData(unsigned char aCmd, unsigned char *pBuf); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void SendCmdReadOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr); + void SendCmdReadOutputIsCheckAbort(); + void SendCmdWriteOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr, unsigned char aSet); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); +}; + + +#endif diff --git a/MyCode/Gui/DevPptCurve.cpp b/MyCode/Gui/DevPptCurve.cpp new file mode 100644 index 0000000..44cac87 --- /dev/null +++ b/MyCode/Gui/DevPptCurve.cpp @@ -0,0 +1,450 @@ +#include "Gui.h" +#include "DevProperty.h" + +void TDevProperty::CurveInit(short aLeft, short aTop, short aWidth, short aHeight, short aDataTypeCnt) +{ + Curve.UsingDataTypeCnt = aDataTypeCnt; + Curve.Left = aLeft; + Curve.Top = aTop; + Curve.Width = aWidth; + Curve.Height = aHeight; + Curve.Right = aLeft + aWidth -1; + Curve.Bottom = aTop + aHeight -1; + + Curve.CurrentPst =0; + Curve.DataLen =0; + + Curve.Smoke.DataAva[0] =0; + Curve.Smoke.DataAva[1] =0; + Curve.Smoke.DataAva[2] =0; + Curve.Tempe.DataAva[0] =0; + Curve.Tempe.DataAva[1] =0; + + Curve.HasUpdate = 0; + Curve.HasDrawOutline =0; +} + +void TDevProperty::CurveSetMargin(short aLeft, short aTop, short aRight, short aBottom) +{ + Curve.Canvas.OrgX = Curve.Left + aLeft; + Curve.Canvas.OrgY = Curve.Bottom - aBottom; + Curve.Canvas.MaxX = Curve.Right - aRight; + Curve.Canvas.MaxY = Curve.Top + aTop; + + Curve.Canvas.Width = Curve.Canvas.MaxX - Curve.Canvas.OrgX +1; + Curve.Canvas.Height = Curve.Canvas.OrgY - Curve.Canvas.MaxY +1; + + if(Curve.Canvas.Width > TItemList::RtDataMaxLen)Curve.Canvas.Width = TItemList::RtDataMaxLen; + Curve.MaxDataLen = Curve.Canvas.Width -2; + if(Curve.MaxDataLen <0)Curve.MaxDataLen =0; +} + +void TDevProperty::CurveSetGrid(short xCnt, short yCnt, short xWidth, short yHeight) +{ + Curve.GridXCount = xCnt; + Curve.GridYCount = yCnt; + if(Curve.GridXCount >16)Curve.GridXCount = 16; + if(Curve.GridYCount >16)Curve.GridYCount = 16; + Curve.GridXWidth = xWidth; + Curve.GridYHeight = yHeight; + + Curve.GridX[0] = Curve.Canvas.OrgX; + Curve.GridY[0] = Curve.Canvas.OrgY; + for(int i=1; i<16; i++){ + Curve.GridX[i] = Curve.GridX[0] + (xWidth * i); + if( Curve.GridX[i] > Curve.Canvas.MaxX){ + Curve.GridX[i] =Curve.GridX[0]; + } + Curve.GridY[i] = Curve.GridY[0] - (yHeight * i); + if( Curve.GridY[i] < Curve.Canvas.MaxY){ + Curve.GridY[i] = Curve.GridY[0]; + } + } +} + +void TDevProperty::CurveSetColor(u32 aClr0, u32 aClr1, u32 aClr2, u32 aClr3) +{ + Curve.Color[0]=aClr0; + Curve.Color[1]=aClr1; + Curve.Color[2]=aClr2; + Curve.Color[3]=aClr3; +} + +void TDevProperty::CurveSetScaling() +{ + if(HwDevType == htSmoker){ + Curve.Scaling[0] = 0.01; + Curve.Scaling[1] = 0.1; + Curve.Scaling[2] = 0.1; + }else + if(HwDevType == htTempe){ + Curve.Scaling[0] = 0.2; + Curve.Scaling[1] = 0.78039; + Curve.Scaling[2] = 1.0; + } +} + +void TDevProperty::CurveDrawText() +{ + int x,y; + if(HwDevType == htSmoker){ + x = Curve.Canvas.OrgX - 40; + y = Curve.Canvas.MaxY -4; + TextRender_string24(x, y, Curve.Color[0], PanelColor, "20K"); + y += 88; + TextRender_string24(x, y, Curve.Color[0], PanelColor, "10K"); + + x = Curve.Canvas.MaxX + 4; + y = Curve.Canvas.MaxY -4; + TextRender_string24(x, y, Curve.Color[1], PanelColor, "2K"); + y += 88; + TextRender_string24(x, y, Curve.Color[1], PanelColor, "1K"); + + x = Curve.Canvas.OrgX - 56; + y = Curve.Canvas.MaxY -4; + TextRender_string24(x, y, Curve.Color[2], PanelColor, "2"); + y += 88; + TextRender_string24(x, y, Curve.Color[2], PanelColor, "1"); + }else + if(HwDevType == htTempe){ + x = Curve.Canvas.OrgX - 40; + y = Curve.Canvas.MaxY -4; + TextRender_string24(x, y, Curve.Color[0], PanelColor, "10K"); + x += 12; + y += 88; + TextRender_string24(x, y, Curve.Color[0], PanelColor, "5K"); + + x = Curve.Canvas.MaxX + 1; + y = Curve.Canvas.MaxY -4; + TextRender_string24(x, y, Curve.Color[1], PanelColor, "+128"); + TCircle::sRender(x+48+4, y + 6, 2, Curve.Color[1], 0); + TextRender_string24(x+48+4+4, y, Curve.Color[1], PanelColor, "C"); + x += 12; + y += 88; + TextRender_string24(x, y, Curve.Color[1], PanelColor, " 0"); + TCircle::sRender(x+24+4, y + 6, 2, Curve.Color[1], 0); + TextRender_string24(x+24+4+4, y, Curve.Color[1], PanelColor, "C"); + x = Curve.Canvas.MaxX + 1; + y += 88; + TextRender_string24(x, y, Curve.Color[1], PanelColor, "-128"); + TCircle::sRender(x+48+4, y + 6, 2, Curve.Color[1], 0); + TextRender_string24(x+48+4+4, y, Curve.Color[1], PanelColor, "C"); + } +} + +void TDevProperty::CurvePutDataSmoke(unsigned short aD0, unsigned short aD1, unsigned short aD2, unsigned short aD3) +{ + float fV1, fV2; + unsigned int iVal; + Curve.DataLen++; + if(Curve.DataLen >(Curve.MaxDataLen))Curve.DataLen = Curve.MaxDataLen; + Curve.CurrentPst++; + if(Curve.CurrentPst >= Curve.MaxDataLen){ + Curve.CurrentPst =0; + } + fV1 = aD0; + fV2 = fV1 * Curve.Scaling[0]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[0][Curve.CurrentPst] = static_cast(iVal); + + fV1 = aD1; + fV2 = fV1 * Curve.Scaling[1]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[1][Curve.CurrentPst] = static_cast(iVal); + + fV1 = aD2; + fV2 = fV1 * Curve.Scaling[2]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[2][Curve.CurrentPst] = static_cast(iVal); + + fV1 = aD3; + fV2 = fV1 * Curve.Scaling[3]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[3][Curve.CurrentPst] = static_cast(iVal); +} + +void TDevProperty::CurvePutDataTempe(unsigned short aD0, unsigned short aD1, unsigned short aD2, unsigned short aD3) +{ + float fV1, fV2; + unsigned char cVal; + unsigned int iVal; + Curve.DataLen++; + if(Curve.DataLen >(Curve.MaxDataLen))Curve.DataLen = Curve.MaxDataLen; + Curve.CurrentPst++; + if(Curve.CurrentPst >= Curve.MaxDataLen){ + Curve.CurrentPst =0; + } + fV1 = aD0; + fV2 = fV1 * Curve.Scaling[0]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[0][Curve.CurrentPst] = static_cast(iVal); + + cVal = static_cast(aD1); + if(cVal<128)cVal+=128; + else cVal=cVal-128; + fV1 = cVal; + fV2 = fV1 * Curve.Scaling[1]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[1][Curve.CurrentPst] = static_cast(iVal); + + fV1 = aD2; + fV2 = fV1 * Curve.Scaling[2]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[2][Curve.CurrentPst] = static_cast(iVal); + + fV1 = aD3; + fV2 = fV1 * Curve.Scaling[3]; + iVal = static_cast(round(fV2)); + if(iVal >(Curve.Canvas.Height-2))iVal = Curve.Canvas.Height-2; + IList->RealtimeData.Data[3][Curve.CurrentPst] = static_cast(iVal); +} + +void TDevProperty::CurveDrawOutline() +{ + HorizLineRender(Curve.Canvas.OrgX, Curve.Canvas.MaxY, Curve.Canvas.Width, dCurveGridClr); + HorizLineRender(Curve.Canvas.OrgX, Curve.Canvas.OrgY, Curve.Canvas.Width, dCurveGridClr); + VertLineRender(Curve.Canvas.OrgX, Curve.Canvas.MaxY, Curve.Canvas.Height, dCurveGridClr); + VertLineRender(Curve.Canvas.MaxX, Curve.Canvas.MaxY, Curve.Canvas.Height, dCurveGridClr); +} + +void TDevProperty::CurveDrawGrid() +{ + int i; + for(i=0; iRealtimeData.Data[c][i]; + PixelRender(x,v[c],PanelColor); + PixelRender(x,v[c]-1,PanelColor); + } + x++; + } + }else{ + x = Curve.Canvas.OrgX+1; + y = Curve.Canvas.OrgY-1; + for(i=Curve.HasDraw.PstEnd; iRealtimeData.Data[c][i]; + PixelRender(x,v[c],PanelColor); + PixelRender(x,v[c]-1,PanelColor); + } + x++; + } + for(i=0; i<=Curve.HasDraw.PstStart; i++){ + for(c=0;(cRealtimeData.Data[c][i]; + PixelRender(x,v[c],PanelColor); + PixelRender(x,v[c]-1,PanelColor); + } + x++; + } + } +} + +void TDevProperty::CurveDrawData() +{ + int i; + int x,y; + Curve.HasDraw.PstEnd = Curve.CurrentPst; + Curve.HasDraw.PstStart = Curve.HasDraw.PstEnd - Curve.DataLen +1; + if(Curve.HasDraw.PstStart <0)Curve.HasDraw.PstStart += Curve.DataLen; + x = Curve.Canvas.OrgX +1; + y = Curve.Canvas.OrgY -1; + int c, v[4]; + if(Curve.HasDraw.PstStart <= Curve.HasDraw.PstEnd){ + x = Curve.Canvas.OrgX+1; + y = Curve.Canvas.OrgY-1; + for(i=Curve.HasDraw.PstStart; i<=Curve.HasDraw.PstEnd; i++){ + for(c=0;(cRealtimeData.Data[c][i]; + PixelRender(x,v[c],Curve.Color[c]); + PixelRender(x,v[c]-1,Curve.Color[c]); + } + if(Curve.UsingDataTypeCnt == 2){ + if(v[0] == v[1]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + }else + if(Curve.UsingDataTypeCnt == 3){ + if(v[0] == v[1]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + if(v[0] == v[2]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + if(v[1] == v[2]){ + PixelRender(x,v[1],clNearWhite); + PixelRender(x,v[1]-1,clNearWhite); + } + }else + if(Curve.UsingDataTypeCnt == 4){ + + } + x++; + } + }else{ + x = Curve.Canvas.OrgX+1; + y = Curve.Canvas.OrgY-1; + for(i=Curve.HasDraw.PstEnd; iRealtimeData.Data[c][i]; + PixelRender(x,v[c],Curve.Color[c]); + PixelRender(x,v[c]-1,Curve.Color[c]); + } + if(Curve.UsingDataTypeCnt == 2){ + if(v[0] == v[1]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + }else + if(Curve.UsingDataTypeCnt == 3){ + if(v[0] == v[1]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + if(v[0] == v[2]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + if(v[1] == v[2]){ + PixelRender(x,v[1],clNearWhite); + PixelRender(x,v[1]-1,clNearWhite); + } + }else + if(Curve.UsingDataTypeCnt == 4){ + + } + x++; + } + for(i=0; i<=Curve.HasDraw.PstStart; i++){ + for(c=0;(cRealtimeData.Data[c][i]; + PixelRender(x,v[c],Curve.Color[c]); + PixelRender(x,v[c]-1,Curve.Color[c]); + } + if(Curve.UsingDataTypeCnt == 2){ + if(v[0] == v[1]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + }else + if(Curve.UsingDataTypeCnt == 3){ + if(v[0] == v[1]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + if(v[0] == v[2]){ + PixelRender(x,v[0],clNearWhite); + PixelRender(x,v[0]-1,clNearWhite); + } + if(v[1] == v[2]){ + PixelRender(x,v[1],clNearWhite); + PixelRender(x,v[1]-1,clNearWhite); + } + }else + if(Curve.UsingDataTypeCnt == 4){ + + } + x++; + } + } +} + +void TDevProperty::CurveDrawLastData() +{ + +} + +void TDevProperty::CurveDraw(int IsFullRedraw) +{ + if(IsFullRedraw){ + CurveDrawOutline(); + CurveDrawText(); + CurveDrawGrid(); + if(Curve.DataLen){ + CurveDrawData(); + } + Curve.HasUpdate =0; + }else{ + if(Curve.DataLen){ + if(Curve.DataLen >= Curve.MaxDataLen){ + CurveRecover(); + CurveDrawGrid(); + } + CurveDrawData(); + } + Curve.HasUpdate =0; + } +} + +void TDevProperty::CurveHide() +{ + Curve.HasDrawOutline =0; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/DevPptDisplayPad.cpp b/MyCode/Gui/DevPptDisplayPad.cpp new file mode 100644 index 0000000..4030cda --- /dev/null +++ b/MyCode/Gui/DevPptDisplayPad.cpp @@ -0,0 +1,1219 @@ +#include "Gui.h" +#include "DevProperty.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TDevProperty::DrawFixTextDisplayPad() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "显示匹配方式"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "分区"); + TextRender_string24(Lv.Grid.Left[2] +140, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "二次码"); + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +226, Lv.Grid.Top[2] + 36, 54, 30, 7, clNearWhite, "读取", 4, clSilver); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "显示范围"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clNearWhite, "保存", 4, clNearBlack); + + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 6, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +80, Lv.Grid.Top[4] + 40, 60, 30, 7, clNearWhite, "消音", 4, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, Lv.Grid.Top[4] + 40, 104, 30, 7, clNearWhite, "下载注释", 4, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "MATCH METHOD"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "Zone"); + TextRender_string24(Lv.Grid.Left[2] +140, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "AuxID"); + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +226, Lv.Grid.Top[2] + 36, 54, 30, 7, clNearWhite, "读取", 4, clSilver); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "DP-RANGE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clNearWhite, "Save", 4, clNearBlack); + + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 6, clNearWhite, ItemColor, "OPER"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +80, Lv.Grid.Top[4] + 40, 60, 30, 7, clNearWhite, "Mute", 4, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, Lv.Grid.Top[4] + 40, 104, 30, 7, clNearWhite, "LOWNNOTE", 4, clNearBlack); + } +} + +void TDevProperty::FullRedrawhtDisplayPad(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + RedrawDisplayPadMatchMode(); + DrawDisplayPadReadWriteStates(); + DisplayPadShowDownloadDescpSta(); + RedrawPanelData(); + Redraw4DisplayPadSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtDisplayPad(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + DrawFixTextDisplayPad(); + IList->Edit[0].Show(); + RedrawDisplayPadMatchMode(); + DrawDisplayPadReadWriteStates(); + DisplayPadShowDownloadDescpSta(); + RedrawPanelData(); + Redraw4DisplayPadSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtDisplayPad(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDevProperty::DrawDisplayPadReadWriteStates() +{ + char *tText; + if(IsHotKeyCheckingPermission)return; + if(VaReadWriteSta ==0 ){ + tText = " "; + //TextRender_string24(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, " "); + }else + if(VaReadWriteSta == 1){ + if(LanguageEnCn==0)tText ="读取成功"; else tText="Read OK "; + //TextRender_string24(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "读取成功"); + }else + if(VaReadWriteSta == 2){ + if(LanguageEnCn==0)tText ="读取失败"; else tText="Read Err"; + //TextRender_string24(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "读取失败"); + }else + if(VaReadWriteSta == 3){ + if(LanguageEnCn==0)tText ="保存成功"; else tText="Save OK "; + //TextRender_string24(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "保存成功"); + }else + if(VaReadWriteSta == 4){ + if(LanguageEnCn==0)tText ="保存失败"; else tText="Save Err"; + //TextRender_string24(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "保存失败"); + }else + if(VaReadWriteSta == 5){ + if(LanguageEnCn==0)tText ="获取中 "; else tText="Reading "; + //TextRender_string24(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "获取中 "); + }else + if(VaReadWriteSta == 6){ + if(LanguageEnCn==0)tText ="写入中 "; else tText="Writing "; + //TextRender_string24(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "写入中 "); + } + TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, tText); +} + +void TDevProperty::DrawDisplayPadReadWriteStates(unsigned char aNewState) +{ + VaReadWriteSta = aNewState; + DrawDisplayPadReadWriteStates(); +} + +void TDevProperty::DisplayPadShowDownloadDescpSta() +{ + char *tText; + if(DisplayPadDownloadDescpSta == 0){ + tText= " "; + }else + if(DisplayPadDownloadDescpSta == 1){ + if(LanguageEnCn==0)tText ="下载成功"; else tText="Down OK "; + }else + if(DisplayPadDownloadDescpSta == 2){ + if(LanguageEnCn==0)tText ="下载失败"; else tText="Down Err"; + }else + if(DisplayPadDownloadDescpSta == 3){ + if(LanguageEnCn==0)tText ="正在下载"; else tText="OnGoing "; + } + TextRender_string24(Lv.Grid.Left[4] + 190, Lv.Grid.Top[4] + 6, clNearWhite, ItemColor, tText); +} + +void TDevProperty::DisplayPadShowDownloadDescpSta(unsigned char aSta) +{ + DisplayPadDownloadDescpSta = aSta; + DisplayPadShowDownloadDescpSta(); +} + +void TDevProperty::InitHtDisplayPad() +{ + PanelIsUsingText = 1; + + for(int i=2; i<5; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + DrawFixTextDisplayPad(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + if( (Path0) && (Path1) && (Path0 <= dPORT_MAX_COUNT) ){ + unsigned char aP0 = Path0 -1; + for(int i=0; iEditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + TRoundSquare::sSelected(Lv.Grid.Left[2] +12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, 4, ItemColor); + break; + case 7: + TRoundSquare::sSelected(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, 4, ItemColor); + break; + case 8: + if(LanguageEnCn==0)tText="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +226, Lv.Grid.Top[2] + 36, 54, 30, 7, clNearWhite, tText, 4, clNearBlack); + break; + case 9: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clNearWhite, tText, 4, clNearBlack); + break; + } + if(Data.DisplayPadMatchMode == 0){ + switch(Tag.Inx){ + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, ItemColor); + break; + case 11: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + case 12: + TRoundSquare::sSelected(Lv.Grid.Left[3] +154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, ItemColor); + break; + case 13: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + + + case 14: + if(LanguageEnCn==0)tText="消音"; else tText="Mute"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +80, Lv.Grid.Top[4] + 40, 60, 30, 7, clNearWhite, tText, 4, clNearBlack); + break; + case 15: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, Lv.Grid.Top[4] + 40, 104, 30, 7, clNearWhite, "下载注释", 4, clNearBlack); + break; + } + }else{ + switch(Tag.Inx){ + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, ItemColor); + break; + case 11: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + case 12: + TRoundSquare::sSelected(Lv.Grid.Left[3] +104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, ItemColor); + break; + case 13: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + case 14: + TRoundSquare::sSelected(Lv.Grid.Left[3] +200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, ItemColor); + break; + case 15: + IList->Edit[2].Selected = 0; + IList->Edit[2].Show(); + break; + + + case 16: + if(LanguageEnCn==0)tText="消音"; else tText="Mute"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +80, Lv.Grid.Top[4] + 40, 60, 30, 7, clNearWhite, tText, 4, clNearBlack); + break; + case 17: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, Lv.Grid.Top[4] + 40, 104, 30, 7, clNearWhite, "下载注释", 4, clNearBlack); + break; + } + } +} +void TDevProperty::Check4SelectedHtDisplayPad() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + TRoundSquare::sSelected(Lv.Grid.Left[2] +12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 7: + TRoundSquare::sSelected(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 8: + if(LanguageEnCn==0)tText="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +226, Lv.Grid.Top[2] + 36, 54, 30, 7, clDeepBlue, tText, 4, clNearWhite); + break; + case 9: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clDeepBlue, tText, 4, clNearWhite); + break; + } + if(Data.DisplayPadMatchMode == 0){ + switch(Tag.Inx){ + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 11: + IList->Edit[0].Selected = 1; + IList->Edit[0].Show(); + break; + case 12: + TRoundSquare::sSelected(Lv.Grid.Left[3] +154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 13: + IList->Edit[1].Selected = 1; + IList->Edit[1].Show(); + break; + + case 14: + if(LanguageEnCn==0)tText="消音"; else tText="Mute"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +80, Lv.Grid.Top[4] + 40, 60, 30, 7, clDeepBlue, tText, 4, clNearWhite); + break; + case 15: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, Lv.Grid.Top[4] + 40, 104, 30, 7, clDeepBlue, "下载注释", 4, clNearWhite); + break; + } + }else{ + switch(Tag.Inx){ + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 11: + IList->Edit[0].Selected = 1; + IList->Edit[0].Show(); + break; + case 12: + TRoundSquare::sSelected(Lv.Grid.Left[3] +104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 13: + IList->Edit[1].Selected = 1; + IList->Edit[1].Show(); + break; + case 14: + TRoundSquare::sSelected(Lv.Grid.Left[3] +200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 15: + IList->Edit[2].Selected = 1; + IList->Edit[2].Show(); + break; + case 16: + if(LanguageEnCn==0)tText="消音"; else tText="Mute"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +80, Lv.Grid.Top[4] + 40, 60, 30, 7, clDeepBlue, tText, 4, clNearWhite); + break; + case 17: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, Lv.Grid.Top[4] + 40, 104, 30, 7, clDeepBlue, "下载注释", 4, clNearWhite); + break; + } + } +} + +void TDevProperty::RedrawDisplayPadMatchMode() +{ + if(Data.DisplayPadMatchMode){ + //1 By Area Num + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 110, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + //0 By User Code + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 110, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + } +} + +void TDevProperty::RedrawDisplayPadMatchData() +{ + for(int i=3; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "显示范围"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clNearWhite, "保存", 4, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "DP-RANGE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clNearWhite, "Save", 4, clNearBlack); + } + if(Data.DisplayPadMatchMode){ + //1 By Area Num + if(Data.DisplayPadAreaUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + if(Data.DisplayPadAreaUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + if(Data.DisplayPadAreaUsing[2]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + IList->Edit[0].Init(Lv.Grid.Left[3] + 34, Lv.Grid.Top[3] + 38, 60, 32, 0,0,1,ItemColor); + IList->Edit[1].Init(Lv.Grid.Left[3] + 132, Lv.Grid.Top[3] + 38, 60, 32, 0,0,1,ItemColor); + IList->Edit[2].Init(Lv.Grid.Left[3] + 228, Lv.Grid.Top[3] + 38, 60, 32, 0,0,1,ItemColor); + IList->Edit[0].Str.Clear(); + IList->Edit[1].Str.Clear(); + IList->Edit[2].Str.Clear(); + IList->Edit[0].SetMaxLen(4); + IList->Edit[1].SetMaxLen(4); + IList->Edit[2].SetMaxLen(4); + + IList->Edit[0].Str.FromUInt4Dg(Data.DisplayPadArea0); + IList->Edit[1].Str.FromUInt4Dg(Data.DisplayPadArea1); + IList->Edit[2].Str.FromUInt4Dg(Data.DisplayPadArea2); + + IList->Edit[0].Show(); + IList->Edit[1].Show(); + IList->Edit[2].Show(); + }else{ + //0 By User Code + if(Data.DisplayPadUserCodeUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + if(Data.DisplayPadUserCodeUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + IList->Edit[0].Init(Lv.Grid.Left[3] + 42, Lv.Grid.Top[3] + 38, 104, 32, 0,0,1,ItemColor); + IList->Edit[1].Init(Lv.Grid.Left[3] + 184, Lv.Grid.Top[3] + 38, 104, 32, 0,0,1,ItemColor); + + IList->Edit[0].Str.Clear(); + IList->Edit[1].Str.Clear(); + IList->Edit[0].SetMaxLen(8); + IList->Edit[1].SetMaxLen(8); + + LoadUcBcdText(Data.DisplayUserCode0, IList->Edit[0].Str.Text); + LoadUcBcdText(Data.DisplayUserCode1, IList->Edit[1].Str.Text); + + IList->Edit[0].Show(); + IList->Edit[1].Show(); + } +} + +void TDevProperty::PushDisplayPadCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmSetDisplayPadPositionInf){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (1 == RecData[0]) && + (MainCtl.fData.Split.MyNum == RecData[1]) && + (Path0 == RecData[2]) && + (Path1 == RecData[3]) ) { + DisplayPadRt.RecRdy =1; + DisplayPadRt.RecCmd =aCmd; + } + } +} + +TGuiMsgReturn TDevProperty::KeyInHtDisplayPad(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int HasPrc = 0; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + case dfKEY_ASTERISK: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + if(aKey == VK_RIGHT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 7; + Check4SelectedHtDisplayPad(); + } + }else + if(Tag.Inx == 7){ + if(aKey == VK_RIGHT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 9; + Check4SelectedHtDisplayPad(); + }else + if(aKey == VK_LEFT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 6; + Check4SelectedHtDisplayPad(); + } + }else + if(Tag.Inx == 8){ + + }else + if(Tag.Inx == 9){ + + }else{ + if(Data.DisplayPadMatchMode){ + if(Tag.Inx == 10){ + if(aKey == VK_RIGHT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 11; + Check4SelectedHtDisplayPad(); + } + }else + if(Tag.Inx == 11){ + if(aKey == VK_LEFT){ + if(IList->Edit[0].Pst < 0){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 10; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + }else + if(aKey == VK_LEFT){ + if(IList->Edit[0].Pst >= IList->Edit[0].Str.GetLength()){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 12; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + } + if( (HasPrc == 0) && (aKey != dfKEY_ASTERISK) ){ + IList->Edit[0].KeyIn(aKey); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + } + }else + if(Tag.Inx == 12){ + if(aKey == VK_RIGHT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 13; + Check4SelectedHtDisplayPad(); + }else + if(aKey == VK_LEFT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 11; + Check4SelectedHtDisplayPad(); + } + }else + if(Tag.Inx == 13){ + if(aKey == VK_LEFT){ + if(IList->Edit[1].Pst < 0){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 12; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + }else + if(aKey == VK_LEFT){ + if(IList->Edit[1].Pst >= IList->Edit[1].Str.GetLength()){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 14; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + } + if( (HasPrc == 0) && (aKey != dfKEY_ASTERISK) ){ + IList->Edit[1].KeyIn(aKey); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + } + }else + if(Tag.Inx == 14){ + if(aKey == VK_LEFT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 13; + Check4SelectedHtDisplayPad(); + } + }else + if(Tag.Inx == 15){ + if(aKey == VK_LEFT){ + if(IList->Edit[2].Pst < 0){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 14; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + } + if( (HasPrc == 0) && (aKey != dfKEY_ASTERISK) ){ + IList->Edit[2].KeyIn(aKey); + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + } + }else + if(Tag.Inx == 16){ + //Mute + //if(aKey == VK_RIGHT){ + // ClearSelectedHtDisplayPad(); + // Tag.Inx = 17; + // Check4SelectedHtDisplayPad(); + //} + }else + if(Tag.Inx == 17){ + //DownLoad Descp + if(aKey == VK_LEFT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 16; + Check4SelectedHtDisplayPad(); + } + } + }else{ + if(Tag.Inx == 10){ + if(aKey == VK_RIGHT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 11; + Check4SelectedHtDisplayPad(); + } + } + if(Tag.Inx == 11){ + if(aKey == VK_LEFT){ + if(IList->Edit[0].Pst < 0){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 10; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + }else + if(aKey == VK_RIGHT){ + if(IList->Edit[0].Pst >= IList->Edit[0].Str.GetLength()){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 12; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + } + if( (HasPrc == 0) ){ + IList->Edit[0].KeyIn(aKey); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + } + }else + if(Tag.Inx == 12){ + if(aKey == VK_LEFT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 11; + Check4SelectedHtDisplayPad(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 13; + Check4SelectedHtDisplayPad(); + } + }else + if(Tag.Inx == 13){ + if(aKey == VK_LEFT){ + if(IList->Edit[1].Pst < 0){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 12; + Check4SelectedHtDisplayPad(); + HasPrc = 1; + } + } + if( (HasPrc == 0) ){ + IList->Edit[1].KeyIn(aKey); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + } + }else + if(Tag.Inx == 14){ + //Mute + //if(aKey == VK_RIGHT){ + // ClearSelectedHtDisplayPad(); + // Tag.Inx = 15; + // Check4SelectedHtDisplayPad(); + //} + }else + if(Tag.Inx == 15){ + //DownLoad Descp + if(aKey == VK_LEFT){ + ClearSelectedHtDisplayPad(); + Tag.Inx = 14; + Check4SelectedHtDisplayPad(); + } + } + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtDisplayPad(); + if(Data.DisplayPadMatchMode){ + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 17; + if(Tag.Inx == 8)Tag.Inx =7; + }else{ + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 15; + if(Tag.Inx == 8)Tag.Inx =7; + } + Check4SelectedHtDisplayPad(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtDisplayPad(); + if(Data.DisplayPadMatchMode){ + Tag.Inx < 16 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + if(Tag.Inx == 8)Tag.Inx =9; + }else{ + Tag.Inx < 14 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + if(Tag.Inx == 8)Tag.Inx =9; + } + Check4SelectedHtDisplayPad(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + if(Tag.Inx == 6){ + Data.DisplayPadMatchMode = Data.DisplayPadMatchMode ? 0 : 1; + RedrawDisplayPadMatchMode(); + RedrawDisplayPadMatchData(); + }else + if(Tag.Inx == 7){ + Data.DisplayPadMatchMode = Data.DisplayPadMatchMode ? 0 : 1; + RedrawDisplayPadMatchMode(); + RedrawDisplayPadMatchData(); + }else + if(Data.DisplayPadMatchMode){ + if(Tag.Inx == 10){ + Data.DisplayPadAreaUsing[0] = Data.DisplayPadAreaUsing[0] ? 0 : 1; + if(Data.DisplayPadAreaUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Tag.Inx == 12){ + Data.DisplayPadAreaUsing[1] = Data.DisplayPadAreaUsing[1] ? 0 : 1; + if(Data.DisplayPadAreaUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + + }else + if(Tag.Inx == 14){ + Data.DisplayPadAreaUsing[2] = Data.DisplayPadAreaUsing[2] ? 0 : 1; + if(Data.DisplayPadAreaUsing[2]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + + } + }else{ + if(Tag.Inx == 10){ + Data.DisplayPadUserCodeUsing[0] = Data.DisplayPadUserCodeUsing[0] ? 0 : 1; + if(Data.DisplayPadUserCodeUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + + }else + if(Tag.Inx == 12){ + Data.DisplayPadUserCodeUsing[1] = Data.DisplayPadUserCodeUsing[1] ? 0 : 1; + if(Data.DisplayPadUserCodeUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + } + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + Data.DisplayPadMatchMode = Data.DisplayPadMatchMode ? 0 : 1; + RedrawDisplayPadMatchMode(); + RedrawDisplayPadMatchData(); + }else + if(Tag.Inx == 7){ + Data.DisplayPadMatchMode = Data.DisplayPadMatchMode ? 0 : 1; + RedrawDisplayPadMatchMode(); + RedrawDisplayPadMatchData(); + }else + if(Tag.Inx == 8){ + //Read Data + + }else + if(Tag.Inx == 9){ + //Save Data + if( (Path0) && (Path1) && (Path0 <= dPORT_MAX_COUNT) ){ + PermissionCmd = pcWriteDisplayPadMatchData; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + }else{ + if(Data.DisplayPadMatchMode){ + if(Tag.Inx == 10){ + Data.DisplayPadAreaUsing[0] = Data.DisplayPadAreaUsing[0] ? 0 : 1; + if(Data.DisplayPadAreaUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Tag.Inx == 11){ + //is Editor, Do nothing + }else + if(Tag.Inx == 12){ + Data.DisplayPadAreaUsing[1] = Data.DisplayPadAreaUsing[1] ? 0 : 1; + if(Data.DisplayPadAreaUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + + }else + if(Tag.Inx == 13){ + //is Editor, Do nothing + }else + if(Tag.Inx == 14){ + Data.DisplayPadAreaUsing[2] = Data.DisplayPadAreaUsing[2] ? 0 : 1; + if(Data.DisplayPadAreaUsing[2]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + + }else + if(Tag.Inx == 15){ + //is Editor, Do nothing + }else + if(Tag.Inx == 16){ + //Mute + if(SystemPermission >1){ + SendDisplayPadMute(); + }else{ + IsPermission = 1; + PermissionCmd = pcDisplayPadMute; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + }else + if(Tag.Inx == 17){ + //DownLoad Descp + //PermissionCmd = pcDownLoadDescp; + //PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + }else{ + if(Tag.Inx == 10){ + Data.DisplayPadUserCodeUsing[0] = Data.DisplayPadUserCodeUsing[0] ? 0 : 1; + if(Data.DisplayPadUserCodeUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + + }else + if(Tag.Inx == 11){ + //is Editor, Do nothing + }else + if(Tag.Inx == 12){ + Data.DisplayPadUserCodeUsing[1] = Data.DisplayPadUserCodeUsing[1] ? 0 : 1; + if(Data.DisplayPadUserCodeUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Tag.Inx == 13){ + //is Editor, Do nothing + }else + if(Tag.Inx == 14){ + //Mute + SendDisplayPadMute(); + }else + if(Tag.Inx == 15){ + //DownLoad Descp + PermissionCmd = pcDownLoadDescp; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + return aMsg; + +} + +void TDevProperty::SendDisplayPadMute() +{ + SendCmdMuteBroadcast(); + SendCmdMute(); +} + +void TDevProperty::SendDisplayPadDescpDownload() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + volatile unsigned int tAddr; + int iVal; + unsigned char aPx; + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 0; + CommData[1] = Path0; + CommData[2] = Path1; + CommData[3] = 0; + + aIde.BitF.Cmd = cmSetDisplayPadPositionInf; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + DisplayPadRt.IsDownloadDescp =1; + DisplayPadRt.RecRdy = 0; + DisplayPadRt.WaitTick =0; + DisplayPadShowDownloadDescpSta(3); //"正在下载"); + + Len = 8; + for(i=0; i<32; i++){ + DisplayPadRt.DescpText[i] = '\0'; + } + if((Path0)&&(Path1)){ + if((Path0<=dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT)){ + tAddr = dAddrSdRam_Descp + ((Path0-1) * 256 * 32) + ((Path1-1) * 32); + for(i=0; i<32; i++)DisplayPadRt.DescpText[i] = *(volatile unsigned char *)(tAddr +i); + } + } + for(int Inx=0; Inx<8; Inx++){ + CommData[3] = Inx +1; + CommData[4] = DisplayPadRt.DescpText[Inx *4 +0]; + CommData[5] = DisplayPadRt.DescpText[Inx *4 +1]; + CommData[6] = DisplayPadRt.DescpText[Inx *4 +2]; + CommData[7] = DisplayPadRt.DescpText[Inx *4 +3]; + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); + } +} + +void TDevProperty::WriteDisplayPadMatchData() +{ + int i; + unsigned char aP0; + + DrawDisplayPadReadWriteStates(0); + + for(i=0; i<16; i++)DpSetting.MemBytes[i] =0; + + if(Path0 == 0)return; + if(Path0 > dPORT_MAX_COUNT)return; + aP0 = Path0-1; + DpSetting.Addr = Path1; + + if(Data.DisplayPadMatchMode) DpSetting.CfgBits |= TPort::DisplayPadByAreaModeBit; + if(Data.DisplayPadAreaUsing[0]) DpSetting.CfgBits |= TPort::DisplayPadUsingAreaEx0; + if(Data.DisplayPadAreaUsing[1]) DpSetting.CfgBits |= TPort::DisplayPadUsingAreaEx1; + if(Data.DisplayPadAreaUsing[2]) DpSetting.CfgBits |= TPort::DisplayPadUsingAreaEx2; + if(Data.DisplayPadUserCodeUsing[0]) DpSetting.CfgBits |= TPort::DisplayPadUsingUcEx0; + if(Data.DisplayPadUserCodeUsing[1]) DpSetting.CfgBits |= TPort::DisplayPadUsingUcEx1; + + if(Data.DisplayPadMatchMode){ + DpSetting.AreaEx[0] = IList->Edit[0].Str.ToInteger(); + DpSetting.AreaEx[1] = IList->Edit[1].Str.ToInteger(); + DpSetting.AreaEx[2] = IList->Edit[2].Str.ToInteger(); + if(DpSetting.AreaEx[0] > dAreaCountMax)DpSetting.AreaEx[0] =0; + if(DpSetting.AreaEx[1] > dAreaCountMax)DpSetting.AreaEx[1] =0; + if(DpSetting.AreaEx[2] > dAreaCountMax)DpSetting.AreaEx[2] =0; + + for(i=0; iEdit[0].Str.Text); + DpSetting.UcList[1].Full = RestoreUcBcdText(IList->Edit[1].Str.Text); + + for(i=0; i 10){ + DisplayPadRt.IsDownloadDescp = 0; + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DisplayPadShowDownloadDescpSta(2);// "下载失败"); + }else{ + DisplayPadDownloadDescpSta = 2; + } + } + } + Redraw4DisplayPadSmallPanelData(); +} + + + + + + + + diff --git a/MyCode/Gui/DevPptHandPad.cpp b/MyCode/Gui/DevPptHandPad.cpp new file mode 100644 index 0000000..0c3d259 --- /dev/null +++ b/MyCode/Gui/DevPptHandPad.cpp @@ -0,0 +1,315 @@ +#include "Gui.h" +#include "DevProperty.h" + +void TDevProperty::DrawFixTextHandPad() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "操作"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "灯点", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clNearWhite, "模拟报警", 14, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "OPER"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "LED ", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clNearWhite, "SimAlarm", 14, aClr); + } +} + +void TDevProperty::FullRedrawhtHandPad(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +116, Lv.Grid.Top[2] + 4, 60,30,0,0,1,clNearBlack); + IList->Edit[0].Str.Clear(); + + DrawLightOnStateHandPad(); +} + +void TDevProperty::EditDescpReturnHtHandPad() +{ + PanelIsUsingText = 1; + for(int i=2; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + DrawFixTextHandPad(); + DrawLightOnStateHandPad(); + ReDrawPanel(); +} + +void TDevProperty::Redraw4HandPadNewLoad() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawLightOnStateHandPad(); +} + +void TDevProperty::Redraw4HandPadSmallPanelData() +{ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::ClearSelectedHtHandPad() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "灯点", 14, clNearBlack); + DrawLightOnStateHandPad(-1); + break; + case 7: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clNearWhite, tText, 14, aClr); + break; + } +} +void TDevProperty::Check4SelectedHtHandPad() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clDeepBlue, "灯点", 14, clNearWhite); + DrawLightOnStateHandPad(); + break; + case 7: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clDeepBlue, tText, 14, aClr); + break; + } +} + +TGuiMsgReturn TDevProperty::KeyInHtHandPad(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Light Up + if(aKey == VK_RIGHT){ + ClearSelectedHtHandPad(); + Tag.Inx = 7; + Check4SelectedHtHandPad(); + } + }else + if(Tag.Inx == 7){ + //Sim Alram + if(aKey == VK_LEFT){ + ClearSelectedHtHandPad(); + Tag.Inx = 6; + Check4SelectedHtHandPad(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtHandPad(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 7; + Check4SelectedHtHandPad(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtHandPad(); + Tag.Inx < 7 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtHandPad(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Light Up + if(RunState == TRunModeCfg::RunModeAdjust){ + SendCmdLightOn(); + DrawLightOnStateHandPad(); + } + }else + if(Tag.Inx == 7){ + //Sim Alram + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimAlram; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; + +} + +void TDevProperty::DrawLightOnStateHandPad(int aPrm) +{ + unsigned char aP0, aP1; + char *tText; + unsigned int TextColor, bClr; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + if( (Tag.Inx == 6) && (aPrm != -1) ){ + TextColor = clNearWhite; + bClr = clDeepBlue; + }else{ + if(RunState == TRunModeCfg::RunModeAdjust)TextColor = clNearBlack;else TextColor = clSilver; + bClr = clNearWhite; + } + if(Port[aP0].HasSetLightOn[aP1]){ + TextColor = clRed; + } + if(LanguageEnCn == 0)tText = "灯点"; else tText = "LED "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, bClr, tText, 14, TextColor); + } +} + +void TDevProperty::Task1000MsHandPad() +{ + Redraw4HandPadSmallPanelData(); +} + + + + diff --git a/MyCode/Gui/DevPptHydrantPad.cpp b/MyCode/Gui/DevPptHydrantPad.cpp new file mode 100644 index 0000000..d8376f5 --- /dev/null +++ b/MyCode/Gui/DevPptHydrantPad.cpp @@ -0,0 +1,321 @@ +#include "Gui.h" +#include "DevProperty.h" + +void TDevProperty::DrawFixTextHydrantPad() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "操作"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "灯点", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clNearWhite, "模拟报警", 14, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "OPER"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "LED ", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clNearWhite, "SimAlarm", 14, aClr); + } +} + +void TDevProperty::FullRedrawhtHydrantPad(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +116, Lv.Grid.Top[2] + 4, 60,30,0,0,1,clNearBlack); + IList->Edit[0].Str.Clear(); + + DrawLightOnStateHydrantPad(); +} + +void TDevProperty::EditDescpReturnHtHydrantPad() +{ + PanelIsUsingText = 1; + + for(int i=2; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + DrawFixTextHydrantPad(); + + DrawLightOnStateHydrantPad(); + ReDrawPanel(); +} + +void TDevProperty::Redraw4HydrantPadNewLoad() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawLightOnStateHydrantPad(); +} + +void TDevProperty::Redraw4HydrantPadSmallPanelData() +{ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::ClearSelectedHtHydrantPad() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "灯点", 14, clNearBlack); + DrawLightOnStateHydrantPad(-1); + break; + case 7: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clNearWhite, tText, 14, aClr); + break; + } +} +void TDevProperty::Check4SelectedHtHydrantPad() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clDeepBlue, "灯点", 14, clNearWhite); + DrawLightOnStateHydrantPad(); + break; + case 7: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 36, 124, 30, 7, clDeepBlue, tText, 14, aClr); + break; + } +} + +TGuiMsgReturn TDevProperty::KeyInHtHydrantPad(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Light Up + if(aKey == VK_RIGHT){ + ClearSelectedHtHydrantPad(); + Tag.Inx = 7; + Check4SelectedHtHydrantPad(); + } + }else + if(Tag.Inx == 7){ + //Sim Alram + if(aKey == VK_LEFT){ + ClearSelectedHtHydrantPad(); + Tag.Inx = 6; + Check4SelectedHtHydrantPad(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtHydrantPad(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 7; + Check4SelectedHtHydrantPad(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtHydrantPad(); + Tag.Inx < 7 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtHydrantPad(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Light Up + if(RunState == TRunModeCfg::RunModeAdjust){ + SendCmdLightOn(); + DrawLightOnStateHydrantPad(); + } + }else + if(Tag.Inx == 7){ + //Sim Start + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimStart; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; + +} + +void TDevProperty::DrawLightOnStateHydrantPad(int aPrm) +{ + unsigned char aP0, aP1; + char *tText; + unsigned int TextColor, bClr; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + if( (Tag.Inx == 6) && (aPrm != -1) ){ + TextColor = clNearWhite; + bClr = clDeepBlue; + }else{ + if(RunState == TRunModeCfg::RunModeAdjust)TextColor = clNearBlack;else TextColor = clSilver; + bClr = clNearWhite; + } + if(Port[aP0].HasSetLightOn[aP1]){ + TextColor = clRed; + } + if(LanguageEnCn==0)tText=""; else tText="LED "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, bClr, tText, 14, TextColor); + } +} + +void TDevProperty::Task1000MsHydrantPad() +{ + Redraw4HandPadSmallPanelData(); +} + + + + + + diff --git a/MyCode/Gui/DevPptLinkagePowerSuply.cpp b/MyCode/Gui/DevPptLinkagePowerSuply.cpp new file mode 100644 index 0000000..14a7886 --- /dev/null +++ b/MyCode/Gui/DevPptLinkagePowerSuply.cpp @@ -0,0 +1,297 @@ +#include "Gui.h" +#include "DevProperty.h" + +#define cmDeviceRuntimeData 207 +#define cmDeviceLinkagePowerSuplyMute 208 + +void TDevProperty::DrawFixTextLinkagePowerSuply() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "消音", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "OPER"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "Mute", 14, clNearBlack); + } +} + +void TDevProperty::FullRedrawhtLinkagePowerSuply(int Prm) +{ + if(Prm == 0){ + for(int i=0; iEditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + if(LanguageEnCn==0)tText="消音";else tText="Mute"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} +void TDevProperty::Check4SelectedHtLinkagePowerSuply() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + if(LanguageEnCn==0)tText="消音";else tText="Mute"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 36, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + } +} + +TGuiMsgReturn TDevProperty::KeyInHtLinkagePowerSuply(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Light Up + if(aKey == VK_RIGHT){ + ClearSelectedHtLinkagePowerSuply(); + Tag.Inx = 7; + Check4SelectedHtLinkagePowerSuply(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtLinkagePowerSuply(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 6; + Check4SelectedHtLinkagePowerSuply(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtLinkagePowerSuply(); + Tag.Inx < 6 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtLinkagePowerSuply(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + SendLinkagePowerSuplyMute(); + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; +} + +void TDevProperty::PushLinkagePowerSuplyCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmDeviceRuntimeData){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (1 == RecData[0]) && + (MainCtl.fData.Split.MyNum == RecData[1]) && + (Path0 == RecData[2]) && + (Path1 == RecData[3]) ) { + RuntimeData.OutputVoltage = RecData[4]; + RuntimeData.OutputCurrent = RecData[5]; + RuntimeData.PwrLoaddingPercent = RecData[6]; + //RuntimeData.OutputCurrent = RecData[7]; + } + } +} + +void TDevProperty::SendLinkagePowerSuplyMute() +{ + SendCmdMute(); +} + +void TDevProperty::Task1000MsLinkagePowerSuply() +{ + Redraw4LinkagePowerSuplySmallPanelData(); +} + + + + + diff --git a/MyCode/Gui/DevPptModulaIn.cpp b/MyCode/Gui/DevPptModulaIn.cpp new file mode 100644 index 0000000..1d765d1 --- /dev/null +++ b/MyCode/Gui/DevPptModulaIn.cpp @@ -0,0 +1,831 @@ +#include "Gui.h" +#include "DevProperty.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define cmDeviceSetSignalInOutType 199 +#define cmDeviceQuerySignalInOutType 200 + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TDevProperty::DrawFixTextModuleIn() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "监管"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "读取", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[4] +6, ModuleRectLv4.Top + 8, clNearWhite, ItemColor, "操作"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +64, ModuleRectLv4.Top + 6, 76, 30, 7, clNearWhite, "灯点", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, ModuleRectLv4.Top + 6, 124, 30, 7, clNearWhite, "模拟输入", 14, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "Fire"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "SUPV"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Read", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[4] +6, ModuleRectLv4.Top + 8, clNearWhite, ItemColor, "OPER"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +64, ModuleRectLv4.Top + 6, 76, 30, 7, clNearWhite, "LED ", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, ModuleRectLv4.Top + 6, 124, 30, 7, clNearWhite, "SimInput", 14, aClr); + } +} + +void TDevProperty::FullRedrawhtModuleIn(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + IList->STextModuleInDefineType.Show(); + + DrawLightOnStateModuleIn(); + RedrawPanelData(); + Redraw4ModuleInSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtModuleIn(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + DrawFixTextModuleIn(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + RedrawPanelData(); + Redraw4ModuleInSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtModuleIn(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDevProperty::InitHtModuleIn() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextModuleIn(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(3); + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 196,30,0,0,clNearWhite,ItemColor); + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE " , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + //ModuleInRt.IsWait4ReadSignalType = 1; + //ModuleInRt.IsWait4WriteSignalType = 0; + //ModuleInRt.RecRdy = 0; + //ModuleInRt.RecCmd = 0; + //ModuleInRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + + DrawLightOnStateModuleIn(); + Data.ModuleSignalInType = Port[Path0-1].FuncSetByte[Path1-1]; + + RedrawModuleInSignalInType(); +} + +void TDevProperty::EditDescpReturnHtModuleIn() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + + DrawFixTextModuleIn(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + RedrawModuleInSignalInType(); + DrawLightOnStateModuleIn(); + + ReDrawPanel(); +} + +void TDevProperty::Redraw4ModuleInNewLoad() +{ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("None Type " , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + ModuleInRt.IsWait4ReadSignalType = 1; + ModuleInRt.IsWait4WriteSignalType = 0; + ModuleInRt.RecRdy = 0; + ModuleInRt.RecCmd = 0; + ModuleInRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + //SendModuleSignalInOutTypeRead(); + + Data.ModuleSignalInType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleInSignalInType(); + + DrawLightOnStateModuleIn(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +void TDevProperty::Redraw4ModuleInSmallPanelData() +{ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::ClearSelectedHtModuleIn() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 7: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 11: + if(LanguageEnCn==0)tText="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 12: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 13: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +64, ModuleRectLv4.Top + 6, 76, 30, 7, clNearWhite, "灯点", 14, clNearBlack); + DrawLightOnStateModuleIn(-1); + break; + case 14: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, ModuleRectLv4.Top + 6, 124, 30, 7, clNearWhite, tText, 14, aClr); + break; + } +} +void TDevProperty::Check4SelectedHtModuleIn() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 7: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 11: + if(LanguageEnCn==0)tText="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 12: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 13: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +64, ModuleRectLv4.Top + 6, 76, 30, 7, clDeepBlue, "灯点", 14, clNearWhite); + DrawLightOnStateModuleIn(); + break; + case 14: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +160, ModuleRectLv4.Top + 6, 124, 30, 7, clDeepBlue, tText, 14, aClr); + break; + } +} + +void TDevProperty::RedrawModuleInDefineType() +{ + int iVal; + iVal =IList->Edit[0].Str.ToInteger(); + if(LanguageEnCn==0){ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("未指派类型",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + } + }else{ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("NONE TYPE ",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); +} + +void TDevProperty::RedrawModuleInSignalInType() +{ + if(Data.ModuleSignalInType == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.ModuleSignalInType == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.ModuleSignalInType == 4){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevProperty::SendModuleSignalInOutTypeRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 3; + + CommData[1] = Path0; + ProcessingRt.P0 = Path0; + + CommData[2] = Path1; + ProcessingRt.P1 = Path1; + + CommData[3] = ProcessingRt.DataType; + + aIde.BitF.Cmd = cmDeviceQuerySignalInOutType; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendModuleSignalInOutTypeWrite() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 3; + + CommData[1] = Path0; + ProcessingRt.P0 = Path0; + + CommData[2] = Path1; + ProcessingRt.P1 = Path1; + + CommData[3] = ProcessingRt.DataType; + + aIde.BitF.Cmd = cmDeviceSetSignalInOutType; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::PushModuleInCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmDeviceSetSignalInOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) && + (ProcessingRt.dVal[0] == RecData[4])) { + ModuleInRt.RecRdy =1; + ModuleInRt.RecCmd =aCmd; + } + }else + if(aCmd == cmDeviceQuerySignalInOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ModuleInRt.RecRdy =1; + ModuleInRt.RecCmd =aCmd; + } + } +} + +TGuiMsgReturn TDevProperty::KeyInHtModuleIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int HasPrc = 0; + char *tText; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + IList->Edit[0].KeyIn(aKey); + RedrawModuleInDefineType(); + }else + if(Tag.Inx == 7){ + //Save Define Type + }else + if(Tag.Inx == 8){ + //Set As Feed Back + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 9; + Check4SelectedHtModuleIn(); + } + }else + if(Tag.Inx == 9){ + //Set As Alram + if(aKey == VK_LEFT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 8; + Check4SelectedHtModuleIn(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 10; + Check4SelectedHtModuleIn(); + } + }else + if(Tag.Inx == 10){ + //Set As Sv + if(aKey == VK_LEFT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 9; + Check4SelectedHtModuleIn(); + } + } + if(Tag.Inx == 11){ + //Read Input Type + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 12; + Check4SelectedHtModuleIn(); + } + }else + if(Tag.Inx == 12){ + //Save Input Type + if(aKey == VK_LEFT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 11; + Check4SelectedHtModuleIn(); + } + }else + if(Tag.Inx == 13){ + //Set Light On + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 14; + Check4SelectedHtModuleIn(); + } + }else + if(Tag.Inx == 14){ + //Sim Alram + if(aKey == VK_LEFT){ + ClearSelectedHtModuleIn(); + Tag.Inx = 13; + Check4SelectedHtModuleIn(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtModuleIn(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 14; + Check4SelectedHtModuleIn(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtModuleIn(); + Tag.Inx < 14 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtModuleIn(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + if(Tag.Inx == 8){ + Data.ModuleSignalInType = Data.ModuleSignalInType==1 ? 0 : 1; + RedrawModuleInSignalInType(); + }else + if(Tag.Inx == 9){ + Data.ModuleSignalInType = Data.ModuleSignalInType==2 ? 0 : 2; + RedrawModuleInSignalInType(); + }else + if(Tag.Inx == 10){ + Data.ModuleSignalInType = Data.ModuleSignalInType==4 ? 0 : 4; + RedrawModuleInSignalInType(); + } + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + }else + if(Tag.Inx == 7){ + //Save Define Type And Add Record + if( (Path0 >0) && (Path0 <= dPORT_MAX_COUNT) && (Path1 >0) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + HasPrc = IList->Edit[0].Str.ToInteger(); + if( (HasPrc >-1) && (HasPrc < 256) ){ + AssignTypeSetting = HasPrc; + if(SystemPermission >2){ + if(LanguageEnCn==0)tText="写入中 "; else tText="Writing "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + WriteAAssignType2Flash(Path0, Path1, AssignTypeSetting); + Record.ReadDevUserSet(); + if(HasPrc == Port[Path0-1].AssignType[Path1-1]){ + if(LanguageEnCn==0)tText="写入成功"; else tText="WroteOK "; + }else{ + if(LanguageEnCn==0)tText="写入失败"; else tText="WroteOK "; + } + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else{ + IsPermission = 1; + PermissionCmd = pcWriteAssignType; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + }else + if(Tag.Inx == 8){ + Data.ModuleSignalInType = Data.ModuleSignalInType==1 ? 0 : 1; + RedrawModuleInSignalInType(); + }else + if(Tag.Inx == 9){ + Data.ModuleSignalInType = Data.ModuleSignalInType==2 ? 0 : 2; + RedrawModuleInSignalInType(); + }else + if(Tag.Inx == 10){ + Data.ModuleSignalInType = Data.ModuleSignalInType==4 ? 0 : 4; + RedrawModuleInSignalInType(); + }else + if(Tag.Inx == 11){ + //Read Signal In Type + //ModuleInRt.IsWait4ReadSignalType = 1; + //ModuleInRt.IsWait4WriteSignalType = 0; + //ModuleInRt.RecRdy = 0; + //ModuleInRt.RecCmd = 0; + //ModuleInRt.WaitTick = 0; + //SendModuleSignalInOutTypeRead(); + //TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取中 "); + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + Data.ModuleSignalInType = Port[Path0-1].FuncSetByte[Path1-1]; + }else{ + Data.ModuleSignalInType =0; + } + RedrawModuleInSignalInType(); + }else + if(Tag.Inx == 12){ + //Write Signal In Type + PermissionCmd = pcWriteModuleSignalInType; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 13){ + if(RunState == TRunModeCfg::RunModeAdjust){ + SendCmdLightOn(); + DrawLightOnStateModuleIn(); + } + }else + if(Tag.Inx == 14){ + //Sim Feed Back + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimInputActive; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; +} + +void TDevProperty::WriteMouelaInputSignal() +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + Port[aP0].FuncSetByte[aP1] = Data.ModuleSignalInType; + sIList = IList; + sWriteAuxIdAssignTypeSignalType(Path0); + + Record.ReadDevUserSet(); + Data.ModuleSignalInType = Port[aP0].FuncSetByte[aP1]; + RedrawModuleInSignalInType(); + } +} + +void TDevProperty::DrawLightOnStateModuleIn(int aPrm) +{ + unsigned char aP0, aP1; + char *tText; + unsigned int TextColor, bClr; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + if( (Tag.Inx == 13) && (aPrm != -1) ){ + TextColor = clNearWhite; + bClr = clDeepBlue; + }else{ + if(RunState == TRunModeCfg::RunModeAdjust)TextColor = clNearBlack;else TextColor = clSilver; + bClr = clNearWhite; + } + if(Port[aP0].HasSetLightOn[aP1]){ + TextColor = clRed; + } + if(LanguageEnCn == 0)tText="灯点"; else tText="LED "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +64, ModuleRectLv4.Top + 6, 76, 30, 7, bClr, tText, 14, TextColor); + } +} + +void TDevProperty::Task1000MsModuleIn() +{ + /*if(ModuleInRt.IsWait4ReadSignalType){ + if(ModuleInRt.RecRdy){ + if(ModuleInRt.RecCmd == cmQuerySens){ + ModuleInRt.RecRdy = 0; + ModuleInRt.IsWait4ReadSignalType = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + Data.ModuleSignalInType = RecData[4]; + RedrawModuleInSignalInType(); + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + } + } + ModuleInRt.RecRdy = 0; + } + ModuleInRt.WaitTick ++; + if(ModuleInRt.WaitTick > 6){ + ModuleInRt.IsWait4ReadSignalType = 0; + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + } + }else + if(ModuleInRt.IsWait4WriteSignalType){ + if(ModuleInRt.RecRdy){ + if(ModuleInRt.RecCmd == cmDeviceSetSens){ + ModuleInRt.IsWait4WriteSignalType = 0; + //Add Record Here + aFullPath.Body.pCtl = MainCtl.fData.Split.MyNum; + aFullPath.Body.P0 = ProcessingRt.P0; + aFullPath.Body.P1 = ProcessingRt.P1; + if(ProcessingRt.DataType == 1) { + //Record.OperateAdd_CfgAddrSmokeSensGrade(aFullPath.D32, Data.Modu); + } + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "保存成功"); + } + ModuleInRt.RecRdy = 0; + } + ModuleInRt.WaitTick ++; + if(ModuleInRt.WaitTick > 6){ + ModuleInRt.IsWait4WriteSignalType = 0; + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "保存失败"); + } + }*/ + Redraw4ModuleInSmallPanelData(); +} + + + diff --git a/MyCode/Gui/DevPptModulaInOut.cpp b/MyCode/Gui/DevPptModulaInOut.cpp new file mode 100644 index 0000000..c9ce914 --- /dev/null +++ b/MyCode/Gui/DevPptModulaInOut.cpp @@ -0,0 +1,885 @@ +#include "Gui.h" +#include "DevProperty.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define cmDeviceSetSignalInOutType 199 +#define cmDeviceQuerySignalInOutType 200 + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TDevProperty::DrawFixTextModuleInOut() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "监管"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "点动"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "读取", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clNearWhite, "灯点", 4, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "模拟输入", 4, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "模拟启动", 4, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "Fire"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "SUPV"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "PulseE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Read", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clNearWhite, "LED", 4, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "SimInput", 4, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "SimStart", 4, aClr); + } +} + +void TDevProperty::FullRedrawhtModuleInOut(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + IList->STextModuleInDefineType.Show(); + + DrawLightOnStateModuleInOut(); + RedrawPanelData(); + Redraw4ModuleInOutSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtModuleInOut(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + DrawFixTextModuleInOut(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + RedrawPanelData(); + Redraw4ModuleInOutSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtModuleInOut(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + DrawLightOnStateModuleInOut(); + } +} + +void TDevProperty::InitHtModuleInOut() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextModuleInOut(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(3); + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 196,30,0,0,clNearWhite,ItemColor); + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + + //ModuleInOutRt.IsWait4ReadSignalType = 1; + //ModuleInOutRt.IsWait4WriteSignalType = 0; + //ModuleInOutRt.RecRdy = 0; + //ModuleInOutRt.RecCmd = 0; + //ModuleInOutRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleInOutSignalType(); + + DrawLightOnStateModuleInOut(); +} + +void TDevProperty::EditDescpReturnHtModuleInOut() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + + DrawFixTextModuleInOut(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + RedrawModuleInOutSignalType(); + DrawLightOnStateModuleInOut(); + + ReDrawPanel(); +} + +void TDevProperty::Redraw4ModuleInOutNewLoad() +{ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("None TYPE" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + //ModuleInOutRt.IsWait4ReadSignalType = 1; + //ModuleInOutRt.IsWait4WriteSignalType = 0; + //ModuleInOutRt.RecRdy = 0; + //ModuleInOutRt.RecCmd = 0; + //ModuleInOutRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + //SendModuleSignalInOutTypeRead(); + + Data.ModuleSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleInOutSignalType(); + DrawLightOnStateModuleInOut(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +void TDevProperty::Redraw4ModuleInOutSmallPanelData() +{ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::ClearSelectedHtModuleInOut() +{ + unsigned int aClr; + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 7: + if(LanguageEnCn==0)tText = "保存"; else tText = "Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 11: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, 4, ItemColor); + break; + case 12: + if(LanguageEnCn==0)tText = "读取"; else tText = "Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 13: + if(LanguageEnCn==0)tText = "保存"; else tText = "Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 14: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clNearWhite, "灯点", 4, clNearBlack); + DrawLightOnStateModuleInOut(-1); + break; + case 15: + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText = "模拟输入"; else tText = "SimInput"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, tText, 4, aClr); + break; + case 16: + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText = "模拟启动"; else tText = "SimStart"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, tText, 4, aClr); + break; + } +} + +void TDevProperty::Check4SelectedHtModuleInOut() +{ + unsigned int aClr; + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 7: + if(LanguageEnCn==0)tText = "保存"; else tText = "Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 11: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 12: + if(LanguageEnCn==0)tText = "读取"; else tText = "Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 13: + if(LanguageEnCn==0)tText = "保存"; else tText = "Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 14: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clDeepBlue, "灯点", 4, clNearWhite); + DrawLightOnStateModuleInOut(); + break; + case 15: + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite; else aClr = clSilver; + if(LanguageEnCn==0)tText = "模拟输入"; else tText = "SimInput"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clDeepBlue, tText, 4, aClr); + break; + case 16: + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite; else aClr = clSilver; + if(LanguageEnCn==0)tText = "模拟启动"; else tText = "SimStart"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clDeepBlue, tText, 4, aClr); + break; + } +} + +void TDevProperty::RedrawModuleInOutDefineType() +{ + int iVal; + iVal =IList->Edit[0].Str.ToInteger(); + if(LanguageEnCn==0){ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("未指派类型",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + } + }else{ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("NONE TYPE",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); +} + +void TDevProperty::RedrawModuleInOutSignalType() +{ + if((Data.ModuleSignalInOutType & 0x07) == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if((Data.ModuleSignalInOutType & 0x07) == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if((Data.ModuleSignalInOutType & 0x07) == 4){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + + if(Data.ModuleSignalInOutType & 0x08){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevProperty::PushModuleInOutCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmDeviceSetSignalInOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) && + (ProcessingRt.dVal[0] == RecData[4])) { + ModuleInOutRt.RecRdy =1; + ModuleInOutRt.RecCmd =aCmd; + } + }else + if(aCmd == cmDeviceQuerySignalInOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ModuleInOutRt.RecRdy =1; + ModuleInOutRt.RecCmd =aCmd; + } + } +} + +TGuiMsgReturn TDevProperty::KeyInHtModuleInOut(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aBits; + char *tText; + int HasPrc = 0; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + IList->Edit[0].KeyIn(aKey); + RedrawModuleInOutDefineType(); + }else + if(Tag.Inx == 7){ + //Save Define Type + }else + if(Tag.Inx == 8){ + //Set As Feed Back + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 9; + Check4SelectedHtModuleInOut(); + } + }else + if(Tag.Inx == 9){ + //Set As Alram + if(aKey == VK_LEFT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 8; + Check4SelectedHtModuleInOut(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 10; + Check4SelectedHtModuleInOut(); + } + }else + if(Tag.Inx == 10){ + //Set As Sv + if(aKey == VK_LEFT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 9; + Check4SelectedHtModuleInOut(); + } + } + if(Tag.Inx == 11){ + //Set Output type + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 12; + Check4SelectedHtModuleInOut(); + } + }else + if(Tag.Inx == 12){ + //Read Input Type + if(aKey == VK_LEFT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 11; + Check4SelectedHtModuleInOut(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 13; + Check4SelectedHtModuleInOut(); + } + }else + if(Tag.Inx == 13){ + //Save Input Type + if(aKey == VK_LEFT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 12; + Check4SelectedHtModuleInOut(); + } + }else + if(Tag.Inx == 14){ + //Set Light On + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 15; + Check4SelectedHtModuleInOut(); + } + }else + if(Tag.Inx == 15){ + //Sim Alram + if(aKey == VK_LEFT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 14; + Check4SelectedHtModuleInOut(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 16; + Check4SelectedHtModuleInOut(); + } + }else + if(Tag.Inx == 16){ + //Sim Start + if(aKey == VK_LEFT){ + ClearSelectedHtModuleInOut(); + Tag.Inx = 15; + Check4SelectedHtModuleInOut(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtModuleInOut(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 16; + Check4SelectedHtModuleInOut(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtModuleInOut(); + Tag.Inx < 16 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtModuleInOut(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + if(Tag.Inx == 8){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.ModuleSignalInOutType |= 0x01; + }else + if( (aBits & 0x07) == 1){ + Data.ModuleSignalInOutType &= ~0x07; + }else{ + Data.ModuleSignalInOutType &= ~0x07; + Data.ModuleSignalInOutType |= 0x01; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 9){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.ModuleSignalInOutType |= 0x02; + }else + if( (aBits & 0x07) == 2){ + Data.ModuleSignalInOutType &= ~0x07; + }else{ + Data.ModuleSignalInOutType &= ~0x07; + Data.ModuleSignalInOutType |= 0x02; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 10){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.ModuleSignalInOutType |= 0x04; + }else + if( (aBits & 0x07) == 4){ + Data.ModuleSignalInOutType &= ~0x07; + }else{ + Data.ModuleSignalInOutType &= ~0x07; + Data.ModuleSignalInOutType |= 0x04; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 11){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x08) == 0){ + Data.ModuleSignalInOutType |= 0x08; + }else{ + Data.ModuleSignalInOutType &= ~0x08; + } + RedrawModuleInOutSignalType(); + } + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + }else + if(Tag.Inx == 7){ + //Save Define Type And Add Record + if( (Path0 >0) && (Path0 <= dPORT_MAX_COUNT) && (Path1 >0) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + HasPrc = IList->Edit[0].Str.ToInteger(); + if( (HasPrc >-1) && (HasPrc < 256) ){ + AssignTypeSetting = HasPrc; + if(SystemPermission >2){ + if(LanguageEnCn==0)tText = "写入中 "; else tText = "Writing "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + WriteAAssignType2Flash(Path0, Path1, AssignTypeSetting); + Record.ReadDevUserSet(); + if(HasPrc == Port[Path0-1].AssignType[Path1-1]){ + if(LanguageEnCn==0)tText = "写入成功"; else tText = "WroteOK "; + }else{ + if(LanguageEnCn==0)tText = "写入失败"; else tText = "WriteErr"; + } + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else{ + IsPermission = 1; + PermissionCmd = pcWriteAssignType; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + }else + if(Tag.Inx == 8){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.ModuleSignalInOutType |= 0x01; + }else + if( (aBits & 0x07) == 1){ + Data.ModuleSignalInOutType &= ~0x07; + }else{ + Data.ModuleSignalInOutType &= ~0x07; + Data.ModuleSignalInOutType |= 0x01; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 9){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.ModuleSignalInOutType |= 0x02; + }else + if( (aBits & 0x07) == 2){ + Data.ModuleSignalInOutType &= ~0x07; + }else{ + Data.ModuleSignalInOutType &= ~0x07; + Data.ModuleSignalInOutType |= 0x02; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 10){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.ModuleSignalInOutType |= 0x04; + }else + if( (aBits & 0x07) == 4){ + Data.ModuleSignalInOutType &= ~0x07; + }else{ + Data.ModuleSignalInOutType &= ~0x07; + Data.ModuleSignalInOutType |= 0x04; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 11){ + aBits = Data.ModuleSignalInOutType; + if( (aBits & 0x08) == 0){ + Data.ModuleSignalInOutType |= 0x08; + }else{ + Data.ModuleSignalInOutType &= ~0x08; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 12){ + if( (Path0) && (Path1) && (Path0 <= dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + Data.ModuleSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + } + RedrawModuleInOutSignalType(); + }else + if(Tag.Inx == 13){ + //Write Signal In Type + PermissionCmd = pcWriteModuleSignalInOutType; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = pcWriteModuleSignalInOutType; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 14){ + //Light On + if(RunState == TRunModeCfg::RunModeAdjust){ + SendCmdLightOn(); + DrawLightOnStateModuleInOut(); + } + }else + if(Tag.Inx == 15){ + //Sim Feed Back + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimInputActive; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + }else + if(Tag.Inx == 16){ + //Sim Start + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimStart; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; + +} + +void TDevProperty::WriteMouelaInOutSignal() +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + Port[aP0].FuncSetByte[aP1] = Data.ModuleSignalInOutType; + sIList = IList; + sWriteAuxIdAssignTypeSignalType(Path0); + + Record.ReadDevUserSet(); + Data.ModuleSignalInOutType = Port[aP0].FuncSetByte[aP1]; + RedrawModuleInOutSignalType(); + + } +} + +void TDevProperty::DrawLightOnStateModuleInOut(int aPrm) +{ + unsigned char aP0, aP1; + char *tText; + unsigned int TextColor, bClr; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + if( (Tag.Inx == 14) && (aPrm != -1) ){ + TextColor = clNearWhite; + bClr = clDeepBlue; + }else{ + if(RunState == TRunModeCfg::RunModeAdjust)TextColor = clNearBlack;else TextColor = clSilver; + bClr = clNearWhite; + } + if(Port[aP0].HasSetLightOn[aP1]){ + TextColor = clRed; + } + if(LanguageEnCn == 0)tText ="灯点"; else tText = "LED "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, bClr, tText, 4, TextColor); + } +} + +void TDevProperty::Task1000MsModuleInOut() +{ + /*if(ModuleInOutRt.IsWait4ReadSignalType){ + if(ModuleInOutRt.RecRdy){ + if(ModuleInOutRt.RecCmd == cmQuerySens){ + ModuleInOutRt.RecRdy = 0; + ModuleInOutRt.IsWait4ReadSignalType = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + Data.ModuleSignalInType = RecData[4]; + RedrawModuleInSignalInType(); + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + } + } + ModuleInOutRt.RecRdy = 0; + } + ModuleInOutRt.WaitTick ++; + if(ModuleInOutRt.WaitTick > 6){ + ModuleInOutRt.IsWait4ReadSignalType = 0; + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + } + }else + if(ModuleInOutRt.IsWait4WriteSignalType){ + if(ModuleInOutRt.RecRdy){ + if(ModuleInOutRt.RecCmd == cmDeviceSetSens){ + ModuleInOutRt.IsWait4WriteSignalType = 0; + //Add Record Here + aFullPath.Body.pCtl = MainCtl.fData.Split.MyNum; + aFullPath.Body.P0 = ProcessingRt.P0; + aFullPath.Body.P1 = ProcessingRt.P1; + if(ProcessingRt.DataType == 1) { + //Record.OperateAdd_CfgAddrSmokeSensGrade(aFullPath.D32, Data.Modu); + } + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "保存成功"); + } + ModuleInOutRt.RecRdy = 0; + } + ModuleInOutRt.WaitTick ++; + if(ModuleInOutRt.WaitTick > 6){ + ModuleInOutRt.IsWait4WriteSignalType = 0; + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "保存失败"); + } + } + */ + Redraw4ModuleInSmallPanelData(); +} + + + diff --git a/MyCode/Gui/DevPptModulaOut.cpp b/MyCode/Gui/DevPptModulaOut.cpp new file mode 100644 index 0000000..37eef0e --- /dev/null +++ b/MyCode/Gui/DevPptModulaOut.cpp @@ -0,0 +1,823 @@ +#include "Gui.h" +#include "DevProperty.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define cmDeviceSetSignalOutType 199 +#define cmDeviceQuerySignalOutType 200 + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TDevProperty::DrawFixTextModuleOut() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "输出信号"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clSilver, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clSilver, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clSilver, ItemColor, "监管"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "点动"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "读取", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clNearWhite, "灯点", 4, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "模拟输入", 4, clSilver); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "模拟启动", 4, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clSilver, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clSilver, ItemColor, "Fire"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clSilver, ItemColor, "SUPV"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "Pulse"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Read", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clNearWhite, "LED ", 4, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "SimInput", 4, clSilver); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "Sim-Act", 4, aClr); + } +} + +void TDevProperty::FullRedrawhtModuleOut(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + IList->STextModuleInDefineType.Show(); + RedrawPanelData(); + Redraw4ModuleOutSmallPanelData(); + DrawLightOnStateModuleOut(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtModuleOut(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + DrawFixTextModuleOut(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + RedrawPanelData(); + Redraw4ModuleOutSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtModuleOut(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + DrawLightOnStateModuleOut(); + } +} + +void TDevProperty::InitHtModuleOut() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextModuleOut(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(3); + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 196,30,0,0,clNearWhite,ItemColor); + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE " , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + DrawLightOnStateModuleOut(); + //ModuleOutRt.IsWait4ReadSignalType = 1; + //ModuleOutRt.IsWait4WriteSignalType = 0; + //ModuleOutRt.RecRdy = 0; + //ModuleOutRt.RecCmd = 0; + //ModuleOutRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleOutSignalType(); +} + +void TDevProperty::EditDescpReturnHtModuleOut() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + + DrawFixTextModuleOut(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + RedrawModuleOutSignalType(); + DrawLightOnStateModuleOut(); + + ReDrawPanel(); +} + +void TDevProperty::Redraw4ModuleOutNewLoad() +{ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE " , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + //ModuleOutRt.IsWait4ReadSignalType = 1; + //ModuleOutRt.IsWait4WriteSignalType = 0; + //ModuleOutRt.RecRdy = 0; + //ModuleOutRt.RecCmd = 0; + //ModuleOutRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + //SendModuleSignalInOutTypeRead(); + Data.ModuleSignalOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleOutSignalType(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawLightOnStateModuleOut(); +} + +void TDevProperty::Redraw4ModuleOutSmallPanelData() +{ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::ClearSelectedHtModuleOut() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 7: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 11: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, 4, ItemColor); + break; + case 12: + if(LanguageEnCn==0)tText ="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 13: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 14: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clNearWhite, "灯点", 4, clNearBlack); + DrawLightOnStateModuleOut(-1); + break; + case 15: + if(LanguageEnCn==0)tText ="模拟输入"; else tText="SimInput"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, tText, 4, clSilver); + break; + case 16: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText ="模拟启动"; else tText="Sim-Act"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, tText, 4, aClr); + break; + } +} +void TDevProperty::Check4SelectedHtModuleOut() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 7: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 11: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 12: + if(LanguageEnCn==0)tText ="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 13: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 14: + //TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, clDeepBlue, "灯点", 4, clNearWhite); + DrawLightOnStateModuleOut(); + break; + case 15: + if(LanguageEnCn==0)tText ="模拟输入"; else tText="SimInput"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +66, ModuleRectLv4.Top + 6, 104, 30, 7, clDeepBlue, tText, 4, clSilver); + break; + case 16: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite;else aClr = clSilver; + if(LanguageEnCn==0)tText ="模拟启动"; else tText="Sim-Act"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clDeepBlue, tText, 4, aClr); + break; + } +} + +void TDevProperty::RedrawModuleOutDefineType() +{ + int iVal; + iVal =IList->Edit[0].Str.ToInteger(); + if(LanguageEnCn==0){ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("未指派类型",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + } + }else{ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("NONE TYPE ",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); +} + +void TDevProperty::RedrawModuleOutSignalType() +{ + if(0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, clSilver , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, clSilver , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, clSilver , 0); + } + + if(Data.ModuleSignalOutType & 0x08){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevProperty::PushModuleOutCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmDeviceSetSignalOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) && + (ProcessingRt.dVal[0] == RecData[4])) { + ModuleOutRt.RecRdy =1; + ModuleOutRt.RecCmd =aCmd; + } + }else + if(aCmd == cmDeviceQuerySignalOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ModuleOutRt.RecRdy =1; + ModuleOutRt.RecCmd =aCmd; + } + } +} + +TGuiMsgReturn TDevProperty::KeyInHtModuleOut(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aBits; + char *tText; + int HasPrc = 0; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + IList->Edit[0].KeyIn(aKey); + RedrawModuleOutDefineType(); + }else + if(Tag.Inx == 7){ + //Save Define Type + }else + if(Tag.Inx == 8){ + + }else + if(Tag.Inx == 9){ + + }else + if(Tag.Inx == 10){ + + } + if(Tag.Inx == 11){ + //Set Output type + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleOut(); + Tag.Inx = 12; + Check4SelectedHtModuleOut(); + } + }else + if(Tag.Inx == 12){ + //Read Input Type + if(aKey == VK_LEFT){ + ClearSelectedHtModuleOut(); + Tag.Inx = 11; + Check4SelectedHtModuleOut(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleOut(); + Tag.Inx = 13; + Check4SelectedHtModuleOut(); + } + }else + if(Tag.Inx == 13){ + //Save Input Type + if(aKey == VK_LEFT){ + ClearSelectedHtModuleOut(); + Tag.Inx = 12; + Check4SelectedHtModuleOut(); + } + }else + if(Tag.Inx == 14){ + //Set Light On + if(aKey == VK_RIGHT){ + ClearSelectedHtModuleOut(); + Tag.Inx = 16; + Check4SelectedHtModuleOut(); + } + }else + if(Tag.Inx == 15){ + + }else + if(Tag.Inx == 16){ + //Sim Start + if(aKey == VK_LEFT){ + ClearSelectedHtModuleOut(); + Tag.Inx = 14; + Check4SelectedHtModuleOut(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtModuleOut(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 16; + if( (Tag.Inx == 8) || (Tag.Inx == 9) || (Tag.Inx == 10) )Tag.Inx =7; + if( Tag.Inx == 15 )Tag.Inx =14; + Check4SelectedHtModuleOut(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtModuleOut(); + Tag.Inx < 16 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + if( (Tag.Inx == 8) || (Tag.Inx == 9) || (Tag.Inx == 10) )Tag.Inx =11; + if( Tag.Inx == 15 )Tag.Inx =16; + Check4SelectedHtModuleOut(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + if(Tag.Inx == 8){ + + }else + if(Tag.Inx == 9){ + + }else + if(Tag.Inx == 10){ + + }else + if(Tag.Inx == 11){ + aBits = Data.ModuleSignalOutType; + if( (aBits & 0x08) == 0){ + Data.ModuleSignalOutType |= 0x08; + }else{ + Data.ModuleSignalOutType &= ~0x08; + } + RedrawModuleOutSignalType(); + } + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + }else + if(Tag.Inx == 7){ + //Save Define Type And Add Record + if( (Path0 >0) && (Path0 <= dPORT_MAX_COUNT) && (Path1 >0) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + HasPrc = IList->Edit[0].Str.ToInteger(); + if( (HasPrc >-1) && (HasPrc < 256) ){ + AssignTypeSetting = HasPrc; + if(SystemPermission >2){ + if(LanguageEnCn==0)tText= "写入中 "; else tText="Writing "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + WriteAAssignType2Flash(Path0, Path1, AssignTypeSetting); + Record.ReadDevUserSet(); + if(HasPrc == Port[Path0-1].AssignType[Path1-1]){ + if(LanguageEnCn==0)tText= "写入成功"; else tText="WroteOK "; + }else{ + if(LanguageEnCn==0)tText= "写入失败"; else tText="WriteErr"; + } + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else{ + IsPermission = 1; + PermissionCmd = pcWriteAssignType; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + }else + if(Tag.Inx == 8){ + + }else + if(Tag.Inx == 9){ + + }else + if(Tag.Inx == 10){ + + }else + if(Tag.Inx == 11){ + aBits = Data.ModuleSignalOutType; + if( (aBits & 0x08) == 0){ + Data.ModuleSignalOutType |= 0x08; + }else{ + Data.ModuleSignalOutType &= ~0x08; + } + RedrawModuleOutSignalType(); + }else + if(Tag.Inx == 12){ + if( (Path0) && (Path1) && (Path0 <= dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + Data.ModuleSignalOutType = Port[Path0-1].FuncSetByte[Path1-1]; + } + RedrawModuleOutSignalType(); + }else + if(Tag.Inx == 13){ + //Write Signal In Type + PermissionCmd = pcWriteModuleSignalOutType; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = pcWriteModuleSignalOutType; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 14){ + //Light On + if(RunState == TRunModeCfg::RunModeAdjust){ + SendCmdLightOn(); + DrawLightOnStateModuleOut(); + } + }else + if(Tag.Inx == 15){ + //No Sim Alram + }else + if(Tag.Inx == 16){ + //Sim Start + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimStart; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; + +} + +void TDevProperty::WriteMouelaOutSignal() +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + + return; + + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + sDelayMs(100); + + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + for(i=0; i<4; i++){ + for(x=0;x<64;x++){ + ReadWriteData.D32[x] = Port[aP0].UcList[i*64 + x].Full; + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (i * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } + + for(x=0;x<256;x++){ + ReadWriteData.D8[x] = Port[aP0].AssignType[x]; + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (4 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Signal Type + Port[aP0].FuncSetByte[aP1] = Data.ModuleSignalOutType; + for(x=0;x<256;x++){ + ReadWriteData.D8[x] = Port[aP0].FuncSetByte[x]; + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (5 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + Record.ReadDevUserSet(); + Data.ModuleSignalOutType = Port[aP0].FuncSetByte[aP1]; + RedrawModuleOutSignalType(); + + } +} + +void TDevProperty::DrawLightOnStateModuleOut(int aPrm) +{ + unsigned char aP0, aP1; + char *tText; + unsigned int TextColor, bClr; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + if( (Tag.Inx == 14) && (aPrm != -1) ){ + TextColor = clNearWhite; + bClr = clDeepBlue; + }else{ + if(RunState == TRunModeCfg::RunModeAdjust)TextColor = clNearBlack;else TextColor = clSilver; + bClr = clNearWhite; + } + if(Port[aP0].HasSetLightOn[aP1]){ + TextColor = clRed; + } + if(LanguageEnCn == 0)tText = "灯点"; else tText="LED "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +4, ModuleRectLv4.Top + 6, 54, 30, 7, bClr , tText, 4, TextColor); + + } +} + +void TDevProperty::Task1000MsModuleOut() +{ + /*if(ModuleInOutRt.IsWait4ReadSignalType){ + if(ModuleInOutRt.RecRdy){ + if(ModuleInOutRt.RecCmd == cmQuerySens){ + ModuleInOutRt.RecRdy = 0; + ModuleInOutRt.IsWait4ReadSignalType = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + Data.ModuleSignalInType = RecData[4]; + RedrawModuleInSignalInType(); + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + } + } + ModuleInOutRt.RecRdy = 0; + } + ModuleInOutRt.WaitTick ++; + if(ModuleInOutRt.WaitTick > 6){ + ModuleInOutRt.IsWait4ReadSignalType = 0; + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + } + }else + if(ModuleInOutRt.IsWait4WriteSignalType){ + if(ModuleInOutRt.RecRdy){ + if(ModuleInOutRt.RecCmd == cmDeviceSetSens){ + ModuleInOutRt.IsWait4WriteSignalType = 0; + //Add Record Here + aFullPath.Body.pCtl = MainCtl.fData.Split.MyNum; + aFullPath.Body.P0 = ProcessingRt.P0; + aFullPath.Body.P1 = ProcessingRt.P1; + if(ProcessingRt.DataType == 1) { + //Record.OperateAdd_CfgAddrSmokeSensGrade(aFullPath.D32, Data.Modu); + } + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "保存成功"); + } + ModuleInOutRt.RecRdy = 0; + } + ModuleInOutRt.WaitTick ++; + if(ModuleInOutRt.WaitTick > 6){ + ModuleInOutRt.IsWait4WriteSignalType = 0; + if(EdittingDescp == 0)TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "保存失败"); + } + }*/ + Redraw4ModuleInSmallPanelData(); +} + diff --git a/MyCode/Gui/DevPptNoType.cpp b/MyCode/Gui/DevPptNoType.cpp new file mode 100644 index 0000000..4c6be14 --- /dev/null +++ b/MyCode/Gui/DevPptNoType.cpp @@ -0,0 +1,656 @@ +#include "Gui.h" +#include "DevProperty.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TDevProperty::DrawFixTextNoType() +{ + if(LanguageEnCn == 0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "监管"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "点动"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "读取", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "Fire"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "SUPV"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "Pulse"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Read", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + } +} + +void TDevProperty::FullRedrawNoType(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + IList->STextModuleInDefineType.Show(); + + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + ClearSelectedNoType(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + if(LanguageEnCn == 0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedNoType(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } + + Redraw4NoTypeSmallPanelWithNoData(); +} + +void TDevProperty::InitNoType() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + DrawFixTextNoType(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(3); + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 196,30,0,0,clNearWhite,ItemColor); + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + Data.NoTypeSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawNoTypeSignalType(); + + Redraw4NoTypeSmallPanelWithNoData(); +} + + +void TDevProperty::EditDescpReturnHtNoType() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + + DrawFixTextNoType(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + RedrawNoTypeSignalType(); + + ReDrawPanel(); +} + +void TDevProperty::Redraw4NoTypeNewLoad() +{ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE" , 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + Data.NoTypeSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawNoTypeSignalType(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +void TDevProperty::RedrawNoTypeDefineType() +{ + int iVal; + iVal =IList->Edit[0].Str.ToInteger(); + if(LanguageEnCn==0){ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("未指派类型",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + } + }else{ + if( (iVal <0) || (iVal > 255) ){ + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText("NONE TYPE",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + } + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); +} + +void TDevProperty::RedrawNoTypeSignalType() +{ + if((Data.NoTypeSignalInOutType & 0x07) == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if((Data.NoTypeSignalInOutType & 0x07) == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if((Data.NoTypeSignalInOutType & 0x07) == 4){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + + if(Data.NoTypeSignalInOutType & 0x08){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevProperty::ClearSelectedNoType() +{ + unsigned int aClr; + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 7: + if(LanguageEnCn == 0)tText = "保存\0"; else tText="Save\0"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 11: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, 4, ItemColor); + break; + case 12: + if(LanguageEnCn == 0)tText = "读取\0"; else tText="Read\0"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 13: + if(LanguageEnCn == 0)tText = "保存\0"; else tText="Save\0"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} +void TDevProperty::Check4SelectedNoType() +{ + unsigned int aClr; + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 7: + if(LanguageEnCn == 0)tText = "保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 40, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 11: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 12: + if(LanguageEnCn == 0)tText = "读取\0"; else tText="Read\0"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 13: + if(LanguageEnCn == 0)tText = "保存\0"; else tText="Save\0"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + } +} + + +TGuiMsgReturn TDevProperty::KeyInHtNoType(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + char *tText; + unsigned char aBits; + int HasPrc = 0; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + IList->Edit[0].KeyIn(aKey); + RedrawNoTypeDefineType(); + }else + if(Tag.Inx == 7){ + //Save Define Type + }else + if(Tag.Inx == 8){ + //Set As Feed Back + if(aKey == VK_RIGHT){ + ClearSelectedNoType(); + Tag.Inx = 9; + Check4SelectedNoType(); + } + }else + if(Tag.Inx == 9){ + //Set As Alram + if(aKey == VK_LEFT){ + ClearSelectedNoType(); + Tag.Inx = 8; + Check4SelectedNoType(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedNoType(); + Tag.Inx = 10; + Check4SelectedNoType(); + } + }else + if(Tag.Inx == 10){ + //Set As Sv + if(aKey == VK_LEFT){ + ClearSelectedNoType(); + Tag.Inx = 9; + Check4SelectedNoType(); + } + } + if(Tag.Inx == 11){ + //Set Output type + if(aKey == VK_RIGHT){ + ClearSelectedNoType(); + Tag.Inx = 12; + Check4SelectedNoType(); + } + }else + if(Tag.Inx == 12){ + //Read Input Type + if(aKey == VK_LEFT){ + ClearSelectedNoType(); + Tag.Inx = 11; + Check4SelectedNoType(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedNoType(); + Tag.Inx = 13; + Check4SelectedNoType(); + } + }else + if(Tag.Inx == 13){ + //Save Input Type + if(aKey == VK_LEFT){ + ClearSelectedNoType(); + Tag.Inx = 12; + Check4SelectedNoType(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedNoType(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 13; + Check4SelectedNoType(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedNoType(); + Tag.Inx < 13 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedNoType(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + if(Tag.Inx == 8){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.NoTypeSignalInOutType |= 0x01; + }else + if( (aBits & 0x07) == 1){ + Data.NoTypeSignalInOutType &= ~0x07; + }else{ + Data.NoTypeSignalInOutType &= ~0x07; + Data.NoTypeSignalInOutType |= 0x01; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 9){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.NoTypeSignalInOutType |= 0x02; + }else + if( (aBits & 0x07) == 2){ + Data.NoTypeSignalInOutType &= ~0x07; + }else{ + Data.NoTypeSignalInOutType &= ~0x07; + Data.NoTypeSignalInOutType |= 0x02; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 10){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.NoTypeSignalInOutType |= 0x04; + }else + if( (aBits & 0x07) == 4){ + Data.NoTypeSignalInOutType &= ~0x07; + }else{ + Data.NoTypeSignalInOutType &= ~0x07; + Data.NoTypeSignalInOutType |= 0x04; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 11){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x08) == 0){ + Data.NoTypeSignalInOutType |= 0x08; + }else{ + Data.NoTypeSignalInOutType &= ~0x08; + } + RedrawNoTypeSignalType(); + } + break; + case dfKEY_QUERY: + //PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + //SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Define Type + }else + if(Tag.Inx == 7){ + //Save Define Type And Add Record + if( (Path0 >0) && (Path0 <= dPORT_MAX_COUNT) && (Path1 >0) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + HasPrc = IList->Edit[0].Str.ToInteger(); + if( (HasPrc >-1) && (HasPrc < 256) ){ + AssignTypeSetting = HasPrc; + PermissionCmd = pcWriteAssignType; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + }else + if(Tag.Inx == 8){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.NoTypeSignalInOutType |= 0x01; + }else + if( (aBits & 0x07) == 1){ + Data.NoTypeSignalInOutType &= ~0x07; + }else{ + Data.NoTypeSignalInOutType &= ~0x07; + Data.NoTypeSignalInOutType |= 0x01; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 9){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.NoTypeSignalInOutType |= 0x02; + }else + if( (aBits & 0x07) == 2){ + Data.NoTypeSignalInOutType &= ~0x07; + }else{ + Data.NoTypeSignalInOutType &= ~0x07; + Data.NoTypeSignalInOutType |= 0x02; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 10){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x07) == 0){ + Data.NoTypeSignalInOutType |= 0x04; + }else + if( (aBits & 0x07) == 4){ + Data.NoTypeSignalInOutType &= ~0x07; + }else{ + Data.NoTypeSignalInOutType &= ~0x07; + Data.NoTypeSignalInOutType |= 0x04; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 11){ + aBits = Data.NoTypeSignalInOutType; + if( (aBits & 0x08) == 0){ + Data.NoTypeSignalInOutType |= 0x08; + }else{ + Data.NoTypeSignalInOutType &= ~0x08; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 12){ + if( (Path0) && (Path1) && (Path0 <= dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + Data.NoTypeSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + } + RedrawNoTypeSignalType(); + }else + if(Tag.Inx == 13){ + //Write Signal In Type + PermissionCmd = pcWriteNoTypeSignalInOutType; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = pcWriteNoTypeSignalInOutType; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + return aMsg; +} + +void TDevProperty::WriteNoTypeInOutSignal() +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + Port[aP0].FuncSetByte[aP1] = Data.NoTypeSignalInOutType; + sIList = IList; + sWriteAuxIdAssignTypeSignalType(Path0); + + Record.ReadDevUserSet(); + Data.NoTypeSignalInOutType = Port[aP0].FuncSetByte[aP1]; + RedrawNoTypeSignalType(); + } +} + +void TDevProperty::Redraw4NoTypeSmallPanelWithNoData() +{ + //RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); +} + +void TDevProperty::Task1000MsNoType() +{ + +} + + diff --git a/MyCode/Gui/DevPptSmokerDotLight.cpp b/MyCode/Gui/DevPptSmokerDotLight.cpp new file mode 100644 index 0000000..07c8983 --- /dev/null +++ b/MyCode/Gui/DevPptSmokerDotLight.cpp @@ -0,0 +1,712 @@ +#include "Gui.h" +#include "DevProperty.h" + +void TDevProperty::DrawFixTextSmoker() +{ + if(LanguageEnCn == 0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "灵敏度"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "读取", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "操作"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clNearWhite, "灯点", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clNearWhite, "模拟报警", 14, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "SENSIT"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Read", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "OPR"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clNearWhite, "LED ", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clNearWhite, "SimAlarm", 14, aClr); + } +} + +void TDevProperty::FullRedrawhtSmoker(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + DrawSmokerReadWriteStates(); + DrawLightOnStateSmoke(); + RedrawPanelData(); + Redraw4SmokerSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtSmoker(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + DrawFixTextSmoker(); + IList->Edit[0].Show(); + DrawSmokerReadWriteStates(); + RedrawPanelData(); + DrawLightOnStateSmoke(); + Redraw4SmokerSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtSmoker(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDevProperty::DrawSmokerReadWriteStates() +{ + char *tText; + if(IsHotKeyCheckingPermission)return; + if(SmokerReadWriteSta == 0){ + tText=" "; + }else + if(SmokerReadWriteSta == 1){ + if(LanguageEnCn==0)tText="获取中 "; else tText="Reading "; + }else + if(SmokerReadWriteSta == 2){ + if(LanguageEnCn==0)tText="获取成功"; else tText="Read OK "; + }else + if(SmokerReadWriteSta == 3){ + if(LanguageEnCn==0)tText="获取失败"; else tText="Read Err"; + }else + if(SmokerReadWriteSta == 4){ + if(LanguageEnCn==0)tText="正在保存"; else tText="Saving "; + }else + if(SmokerReadWriteSta == 5){ + if(LanguageEnCn==0)tText="保存成功"; else tText="Save OK "; + }else + if(SmokerReadWriteSta == 6){ + if(LanguageEnCn==0)tText="保存失败"; else tText="Save Err"; + } + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); +} + +void TDevProperty::DrawSmokerReadWriteStates(unsigned char aNewState) +{ + SmokerReadWriteSta = aNewState; + DrawSmokerReadWriteStates(); +} + +void TDevProperty::InitHtSmoker() +{ + PanelIsUsingText = 1; + + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +86, Lv.Grid.Top[2] + 4, 100,30,0,0,1,clNearBlack); + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + DrawSmokerReadWriteStates(1);//"获取中" + + + DrawLightOnStateSmoke(); +} + +void TDevProperty::EditDescpReturnHtSmoker() +{ + PanelIsUsingText = 1; + + for(int i=2; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + DrawFixTextSmoker(); + + DrawLightOnStateSmoke(); + + IList->Edit[0].Show(); + + ReDrawPanel(); +} + +void TDevProperty::Redraw4SmokerNewLoad() +{ + //for(int i=2; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + DrawSmokerReadWriteStates(1);//"获取中" + + //TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "操作"); + //TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clNearWhite, "灯点", 14, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clNearWhite, "模拟报警", 14, clNearBlack); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + + CurveInit(Lv.Panel.Left+8, Lv.Panel.Top+8, Lv.Panel.Width-16, Lv.Panel.Heigh-16, 3); + CurveSetMargin(60, 2, 60, 2); + CurveSetGrid(6, 6, 50, 50); + CurveSetColor(clRed, clBlue, clDeepGreen, clDeepGreen); + CurveSetScaling(); + + DrawLightOnStateSmoke(); +} + +void TDevProperty::Redraw4SmokerSmallPanelData() +{ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + RectFillRender(Lv.PanelSmall.Left + 120, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 120 + 20, Lv.PanelSmall.Top + 6 + 20, clPurple); + RectFillRender(Lv.PanelSmall.Left + 260, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 260 + 20, Lv.PanelSmall.Top + 6 + 20, clRed); + RectFillRender(Lv.PanelSmall.Left + 370, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 370 + 20, Lv.PanelSmall.Top + 6 + 20, clBlue); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + TMyString::sClear(TextDraw); + TMyString::sAddOnStr("M=", TextDraw); + TMyString::sAddOn1Dg(RuntimeData.SmokerPrmM % 10000 / 1000, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn3Dg(RuntimeData.SmokerPrmM % 1000, TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 146, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + TMyString::sFrom4Dg(RuntimeData.SmokerIR, TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 286, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + TMyString::sFrom4Dg(RuntimeData.SmokerBL, TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 396, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::ClearSelectedHtSmoker() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + } + + switch(Tag.Inx){ + case 7: + if(LanguageEnCn==0)tText="读取";else tText = "Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + if(LanguageEnCn==0)tText="保存";else tText = "Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 9: + //TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clNearWhite, "灯点", 14, clNearBlack); + DrawLightOnStateSmoke(-1); + break; + case 10: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警";else tText = "SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clNearWhite, tText, 14, aClr); + break; + } +} +void TDevProperty::Check4SelectedHtSmoker() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[0].Selected = 1; + IList->Edit[0].Show(); + break; + } + + switch(Tag.Inx){ + case 7: + if(LanguageEnCn==0)tText="读取";else tText = "Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 8: + if(LanguageEnCn==0)tText="保存";else tText = "Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +150, Lv.Grid.Top[2] + 40, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 9: + //TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clDeepBlue, "灯点", 14, clNearWhite); + DrawLightOnStateSmoke(); + break; + case 10: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警";else tText = "SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clDeepBlue, tText, 14, aClr); + break; + } +} + +void TDevProperty::RedrawSmokeSensValue() +{ + char *tText; + if(Data.SmokerSens == 1){ + if(LanguageEnCn==0)tText="灵敏"; else tText ="Normal"; + }else + if(Data.SmokerSens == 2){ + if(LanguageEnCn==0)tText="中灵敏"; else tText ="Middle"; + }else + if(Data.SmokerSens == 3){ + if(LanguageEnCn==0)tText="高灵敏"; else tText ="ExHigh"; + }else + if(Data.SmokerSens == 4){ + if(LanguageEnCn==0)tText="超灵敏"; else tText ="Ultra"; + }else{ + if(LanguageEnCn==0)tText="未知 "; else tText ="Unknown"; + } + IList->Edit[0].Str.FromStr(tText); + if(EdittingDescp == 0)IList->Edit[0].Show(); +} + +void TDevProperty::SendSmokeCmdRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 3; + + CommData[1] = Path0; + ProcessingRt.P0 = Path0; + + CommData[2] = Path1; + ProcessingRt.P1 = Path1; + + CommData[3] = ProcessingRt.DataType; + + aIde.BitF.Cmd = cmQuerySens; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendSmokeCmdCfg() +{ + TCanHeaderID aIde; + unsigned char cVal, tP0, tP1; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + if(Data.SmokerSens < 4) + ProcessingRt.dVal[0] = dSmokeSensGrade_MarkValue[Data.SmokerSens]; + else + ProcessingRt.dVal[0] = 0; + ProcessingRt.dVal[1] =0; + ProcessingRt.dVal[2] =0; + ProcessingRt.dVal[3] =0; + + Len =8; + for(i=0; i<8; i++){ + CommData[i] = 0; + } + CommData[0] = 3; + + CommData[1] = Path0; + ProcessingRt.P0 = Path0; + ProcessingRt.P1 = Path1; + CommData[2] = ProcessingRt.P1; + + aIde.BitF.Cmd = cmDeviceSetSens; + + + RedrawSmokeSensValue(); + + CommData[3] = ProcessingRt.DataType; + CommData[4] = ProcessingRt.dVal[0]; + CommData[5] = ProcessingRt.dVal[1]; + CommData[6] = ProcessingRt.dVal[2]; + CommData[7] = ProcessingRt.dVal[3]; + + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::PushSmokeCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmDeviceSetSens){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) && + (ProcessingRt.dVal[0] == RecData[4])) { + SmokerRt.RecRdy =1; + SmokerRt.RecCmd =aCmd; + } + }else + if(aCmd == cmQuerySens){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ProcessingRt.dValGot[1] = RecData[5]; + ProcessingRt.dValGot[2] = RecData[6]; + ProcessingRt.dValGot[3] = RecData[7]; + SmokerRt.RecRdy =1; + SmokerRt.RecCmd =aCmd; + } + } +} + +TGuiMsgReturn TDevProperty::KeyInHtSmoker(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int HasPrc = 0; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Sens + Data.SmokerSens++; + if(Data.SmokerSens >= 5){ + Data.SmokerSens = 1; + } + RedrawSmokeSensValue(); + }else + if(Tag.Inx == 7){ + //Read Sens + if(aKey == VK_RIGHT){ + ClearSelectedHtSmoker(); + Tag.Inx = 8; + Check4SelectedHtSmoker(); + } + }else + if(Tag.Inx == 8){ + //Set Sens + if(aKey == VK_LEFT){ + ClearSelectedHtSmoker(); + Tag.Inx = 7; + Check4SelectedHtSmoker(); + } + }else + if(Tag.Inx == 9){ + //Light Up + if(aKey == VK_RIGHT){ + ClearSelectedHtSmoker(); + Tag.Inx = 10; + Check4SelectedHtSmoker(); + } + }else + if(Tag.Inx == 10){ + //Sim Alram + if(aKey == VK_LEFT){ + ClearSelectedHtSmoker(); + Tag.Inx = 9; + Check4SelectedHtSmoker(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtSmoker(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 10; + Check4SelectedHtSmoker(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtSmoker(); + Tag.Inx < 10 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtSmoker(); + } + break; + case VK_TAB: + PanelIsUsingText = PanelIsUsingText ? 0 : 1; + if(PanelIsUsingText == 0){ + CurveHide(); + } + Check4Selected(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + RedrawPanelData(); + break; + case dfKEY_SETUP: + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Sens + + }else + if(Tag.Inx == 7){ + //Read Sens + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + SendSmokeCmdRead(); + DrawSmokerReadWriteStates(1);//"获取中" + }else + if(Tag.Inx == 8){ + //Set Sens + if(SystemPermission >2){ + SmokerRt.IsWait4ReadSens = 0; + SmokerRt.IsWait4WriteSens = 1; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + SendSmokeCmdCfg(); + DrawSmokerReadWriteStates(4);//"写入中 ") + }else{ + IsPermission = 1; + PermissionCmd = pcWriteSmokerSens; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 9){ + //Light Up + if(RunState == TRunModeCfg::RunModeAdjust){ + SendCmdLightOn(); + DrawLightOnStateSmoke(); + } + }else + if(Tag.Inx == 10){ + //Sim Alram + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimAlram; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; + +} + +void TDevProperty::DrawLightOnStateSmoke(int aPrm) +{ + unsigned char aP0, aP1; + char *tText; + unsigned int TextColor, bClr, tPrm; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + if( (Tag.Inx == 9) && (aPrm != -1) ){ + TextColor = clNearWhite; + bClr = clDeepBlue; + }else{ + if(RunState == TRunModeCfg::RunModeAdjust)TextColor = clNearBlack;else TextColor = clSilver; + bClr = clNearWhite; + } + if(Port[aP0].HasSetLightOn[aP1]){ + TextColor = clRed; + } + if(LanguageEnCn == 0)tText="灯点"; else tText="LED"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, bClr, tText, 14, TextColor); + } +} + +void TDevProperty::Task1000MsSmoker() +{ + if(SmokerRt.IsWait4ReadSens){ + if(SmokerRt.RecRdy){ + if(SmokerRt.RecCmd == cmQuerySens){ + SmokerRt.RecRdy = 0; + SmokerRt.IsWait4ReadSens = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[1] )Data.SmokerSens = 1; + else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[2] )Data.SmokerSens = 2; + else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[3] )Data.SmokerSens = 3; + else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[4] )Data.SmokerSens = 4; + else Data.SmokerSens = 5; + RedrawSmokeSensValue(); + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawSmokerReadWriteStates(2);//"获取中""读取成功"); + }else{ + SmokerReadWriteSta =2; + } + } + } + SmokerRt.RecRdy = 0; + } + SmokerRt.WaitTick ++; + if(SmokerRt.WaitTick > 6){ + SmokerRt.IsWait4ReadSens = 0; + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawSmokerReadWriteStates(3);//"读取失败"); + }else{ + SmokerReadWriteSta =3; + } + } + }else + if(SmokerRt.IsWait4WriteSens){ + if(SmokerRt.RecRdy){ + if(SmokerRt.RecCmd == cmDeviceSetSens){ + SmokerRt.IsWait4WriteSens = 0; + //Add Record Here + aFullPath.Body.pCtl = MainCtl.fData.Split.MyNum; + aFullPath.Body.P0 = ProcessingRt.P0; + aFullPath.Body.P1 = ProcessingRt.P1; + if(ProcessingRt.DataType == 1) { + Record.OperateAdd_CfgAddrSmokeSensGrade(aFullPath.D32, Data.SmokerSens); + } + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawSmokerReadWriteStates(5);//"保存成功"); + }else{ + SmokerReadWriteSta = 5; + } + } + SmokerRt.RecRdy = 0; + } + SmokerRt.WaitTick ++; + if(SmokerRt.WaitTick > 6){ + SmokerRt.IsWait4WriteSens = 0; + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawSmokerReadWriteStates(6);//"保存失败"); + }else{ + SmokerReadWriteSta = 6; + } + } + } + Redraw4SmokerSmallPanelData(); +} + + diff --git a/MyCode/Gui/DevPptTempe.cpp b/MyCode/Gui/DevPptTempe.cpp new file mode 100644 index 0000000..eebf2b7 --- /dev/null +++ b/MyCode/Gui/DevPptTempe.cpp @@ -0,0 +1,621 @@ +#include "Gui.h" +#include "DevProperty.h" + +#define cmDeviceSetTempeSensType 211 +#define cmDeviceReadTempeSensType 212 + +//1～9=A1、A1R、A1S、A2、A2R、A2S、B、BR、BS + +void TDevProperty::DrawFixTextTempe() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "探测类型"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "读取", 14, clNearBlack); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "操作"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clNearWhite, "灯点", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clNearWhite, "模拟报警", 14, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "DET TYPE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, "Read", 14, clNearBlack); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "OPER"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clNearWhite, "LED", 14, aClr); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clNearWhite, "SimAlarm", 14, aClr); + } +} + +void TDevProperty::FullRedrawhtTempe(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + DrawTempeReadStates(); + DrawLightOnStateTempe(); + RedrawPanelData(); + Redraw4TempeSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtTempe(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + DrawFixTextTempe(); + IList->Edit[0].Show(); + DrawTempeReadStates(); + + DrawLightOnStateTempe(); + RedrawPanelData(); + Redraw4TempeSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtTempe(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDevProperty::DrawTempeReadStates() +{ + char *tText; + if(TempeReadSta == 0){ + tText=" "; + }else + if(TempeReadSta == 1){ + if(LanguageEnCn==0)tText="获取中 "; else tText="Reading "; + }else + if(TempeReadSta == 2){ + if(LanguageEnCn==0)tText="获取成功"; else tText="ReadOK "; + }else + if(TempeReadSta == 3){ + if(LanguageEnCn==0)tText="获取失败"; else tText="ReadErr "; + } + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); +} + +void TDevProperty::DrawTempeReadStates(unsigned char aNewState) +{ + TempeReadSta = aNewState; + DrawTempeReadStates(); +} + +void TDevProperty::InitHtTempe() +{ + PanelIsUsingText = 1; + + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +116, Lv.Grid.Top[2] + 4, 60,30,0,0,1,clNearBlack); + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + SendTempeCmdRead(); + DrawTempeReadStates(1); //"获取中 "); +} + +void TDevProperty::EditDescpReturnHtTempe() +{ + PanelIsUsingText = 1; + + for(int i=2; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + DrawFixTextTempe(); + + DrawLightOnStateTempe(); + + IList->Edit[0].Init(Lv.Grid.Left[2] +116, Lv.Grid.Top[2] + 4, 60,30,0,0,1,clNearBlack); + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + ReDrawPanel(); +} + +void TDevProperty::Redraw4TempeNewLoad() +{ + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + SendTempeCmdRead(); + DrawTempeReadStates(1); //"获取中 "); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + + CurveInit(Lv.Panel.Left+8, Lv.Panel.Top+8, Lv.Panel.Width-16, Lv.Panel.Heigh-16, 2); + CurveSetMargin(60, 2, 60, 2); + CurveSetGrid(6, 6, 50, 50); + CurveSetColor(clDeepGreen, clPurple, clDeepGreen, clDeepGreen); + CurveSetScaling(); + + DrawLightOnStateTempe(); +} + +void TDevProperty::Redraw4TempeSmallPanelData() +{ + unsigned char tCelsius, iVal; + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + RectFillRender(Lv.PanelSmall.Left + 120, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 120 + 20, Lv.PanelSmall.Top + 6 + 20, clPurple); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + TMyString::sClear(TextDraw); + iVal = static_cast(RuntimeData.TempeCelsiusData); + if(iVal>127){ + tCelsius = (255-iVal)+1; + TMyString::sAddOnChar('-', TextDraw); + }else{ + tCelsius=iVal; + TMyString::sAddOnChar('+', TextDraw); + } + TMyString::sAddOn3Dg(tCelsius % 1000, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 164, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::ClearSelectedHtTempe() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 7: + if(LanguageEnCn==0)tText="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + //TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clNearWhite, "灯点", 14, clNearBlack); + DrawLightOnStateTempe(-1); + break; + case 9: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clNearWhite, tText, 14, aClr); + break; + } +} +void TDevProperty::Check4SelectedHtTempe() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[0].Selected = 1; + IList->Edit[0].Show(); + break; + case 7: + if(LanguageEnCn==0)tText="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 40, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 8: + //TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, clDeepBlue, "灯点", 14, clNearWhite); + DrawLightOnStateTempe(); + break; + case 9: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite;else aClr = clSilver; + if(LanguageEnCn==0)tText="模拟报警"; else tText="SimAlarm"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +150, Lv.Grid.Top[3] + 36, 124, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + } +} + +void TDevProperty::RedrawTempeSensType() +{ + //1～9=A1、A1R、A1S、A2、A2R、A2S、B、BR、BS + char *tText; + if(Data.TempeSenType == 1){ + IList->Edit[0].Str.FromStr("A1"); + }else + if(Data.TempeSenType == 2){ + IList->Edit[0].Str.FromStr("A1R"); + }else + if(Data.TempeSenType == 3){ + IList->Edit[0].Str.FromStr("A1S"); + }else + if(Data.TempeSenType == 4){ + IList->Edit[0].Str.FromStr("A2"); + }else + if(Data.TempeSenType == 5){ + IList->Edit[0].Str.FromStr("A2R"); + }else + if(Data.TempeSenType == 6){ + IList->Edit[0].Str.FromStr("A2S"); + }else + if(Data.TempeSenType == 7){ + IList->Edit[0].Str.FromStr("B"); + }else + if(Data.TempeSenType == 8){ + IList->Edit[0].Str.FromStr("BR"); + }else + if(Data.TempeSenType == 9){ + IList->Edit[0].Str.FromStr("BS"); + }else{ + if(LanguageEnCn==0)tText="未知 "; else tText="Unknown"; + IList->Edit[0].Str.FromStr(tText); + } + IList->Edit[0].Show(); +} + +void TDevProperty::SendTempeCmdRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + TempeRt.IsWait4ReadSensType = 1; + TempeRt.RecRdy = 0; + TempeRt.RecCmd = 0; + TempeRt.WaitTick = 0; + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = Path0; + ProcessingRt.P0 = Path0; + CommData[3] = Path1; + ProcessingRt.P1 = Path1; + + CommData[4] = 0x06; + + aIde.BitF.Cmd = cmQueryStaticData; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, 6); +} + +void TDevProperty::SendTempeCmdCfg() +{ +/* TCanHeaderID aIde; + unsigned char cVal, tP0, tP1; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + if(Data.SmokerSens < 4) + ProcessingRt.dVal[0] = dSmokeSensGrade_MarkValue[Data.SmokerSens]; + else + ProcessingRt.dVal[0] = 0; + ProcessingRt.dVal[1] =0; + ProcessingRt.dVal[2] =0; + ProcessingRt.dVal[3] =0; + + Len =8; + for(i=0; i<8; i++){ + CommData[i] = 0; + } + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = Path0; + ProcessingRt.P0 = Path0; + ProcessingRt.P1 = Path1; + CommData[3] = ProcessingRt.P1; + + aIde.BitF.Cmd = cmQueryStaticData; + + RedrawSmokeSensValue(); + + CommData[3] = ProcessingRt.DataType; + CommData[4] = ProcessingRt.dVal[0]; + CommData[5] = ProcessingRt.dVal[1]; + CommData[6] = ProcessingRt.dVal[2]; + CommData[7] = ProcessingRt.dVal[3]; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len);*/ +} + +void TDevProperty::PushTempeCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmQueryStaticData){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) ){ + if( RecData[3] == 0 ){ + Data.TempeSenType = RecData[5]; + TempeRt.RecRdy =1; + TempeRt.RecCmd =aCmd; + } + } + } +} + +TGuiMsgReturn TDevProperty::KeyInHtTempe(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Sens Type + + }else + if(Tag.Inx == 7){ + //Read Sens + }else + if(Tag.Inx == 8){ + //Light Up + if(aKey == VK_RIGHT){ + ClearSelectedHtTempe(); + Tag.Inx = 9; + Check4SelectedHtTempe(); + } + }else + if(Tag.Inx == 9){ + //Sim Alram + if(aKey == VK_LEFT){ + ClearSelectedHtTempe(); + Tag.Inx = 8; + Check4SelectedHtTempe(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtTempe(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 9; + Check4SelectedHtTempe(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtTempe(); + Tag.Inx < 9 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtTempe(); + } + break; + case VK_TAB: + PanelIsUsingText = PanelIsUsingText ? 0 : 1; + if(PanelIsUsingText == 0){ + CurveHide(); + } + Check4Selected(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + RedrawPanelData(); + break; + case dfKEY_SETUP: + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Sens + + }else + if(Tag.Inx == 7){ + //Read Sens + SendTempeCmdRead(); + DrawTempeReadStates(1); //"获取中 "); + }else + if(Tag.Inx == 8){ + //Light Up + if(RunState == TRunModeCfg::RunModeAdjust){ + SendCmdLightOn(); + DrawLightOnStateTempe(); + } + }else + if(Tag.Inx == 9){ + //Sim Alram + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimAlram; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; +} + +void TDevProperty::DrawLightOnStateTempe(int aPrm) +{ + unsigned char aP0, aP1; + char *tText; + unsigned int TextColor, bClr; + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0 -1; + aP1 = Path1 -1; + if( (Tag.Inx == 8) && (aPrm != -1) ){ + TextColor = clNearWhite; + bClr = clDeepBlue; + }else{ + if(RunState == TRunModeCfg::RunModeAdjust)TextColor = clNearBlack;else TextColor = clSilver; + bClr = clNearWhite; + } + if(Port[aP0].HasSetLightOn[aP1]){ + TextColor = clRed; + } + if(LanguageEnCn == 0)tText="灯点";else tText="LED "; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +60, Lv.Grid.Top[3] + 36, 76, 30, 7, bClr, tText, 14, TextColor); + } +} + + +void TDevProperty::Task1000MsTempe() +{ + if(TempeRt.IsWait4ReadSensType){ + if(TempeRt.RecRdy){ + if(TempeRt.RecCmd == cmQueryStaticData){ + TempeRt.RecRdy = 0; + TempeRt.IsWait4ReadSensType = 0; + //Add Record Here + if(Data.TempeSenType){ + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + RedrawTempeSensType(); + DrawTempeReadStates(2); //"获取成功") + }else{ + TempeReadSta = 2; + } + } + } + TempeRt.RecRdy = 0; + } + TempeRt.WaitTick ++; + if(TempeRt.WaitTick > 6){ + TempeRt.IsWait4ReadSensType = 0; + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawTempeReadStates(3); //"读取失败"); + }else{ + TempeReadSta = 3; + } + } + } + /*if( (Data.GotTempeSensType[0] == 0xF1) && (Data.GotTempeSensType[4] == 0) ){ + if( (Data.GotTempeSensType[1] == Path0) && (Data.GotTempeSensType[2] == Path1) ){ + Data.TempeSenType = Data.GotTempeSensType[3]; + if(IsHotKeyCheckingPermission == 0){ + RedrawTempeSensType(); + DrawTempeReadStates(2); //"获取成功") + Data.GotTempeSensType[4] =1; + } + } + }*/ + Redraw4TempeSmallPanelData(); +} + + + diff --git a/MyCode/Gui/DevPptVa.cpp b/MyCode/Gui/DevPptVa.cpp new file mode 100644 index 0000000..db32d98 --- /dev/null +++ b/MyCode/Gui/DevPptVa.cpp @@ -0,0 +1,813 @@ +#include "Gui.h" +#include "DevProperty.h" + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TDevProperty::DrawFixTextVa() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "控制"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "联动"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "警报形式"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "声光"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "声"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "光"); + + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "读取", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[4] +10, ModuleRectLv4.Top + 6, clNearWhite, ItemColor, "操作"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, "模拟启动", 4, aClr); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "CTRL"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "LINK"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "ALAEMTYP"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "S-L"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "S."); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "L."); + + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Read", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + + TextRender_string24(Lv.Grid.Left[4] +10, ModuleRectLv4.Top + 6, clNearWhite, ItemColor, "Operation"); + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, " Sim Act", 4, aClr); + } +} + +void TDevProperty::FullRedrawhtVa(int Prm) +{ + if(Prm == 0){ + for(int i=2; iEdit[0].Show(); + RedrawVaIs4Linkage(); + RedrawVaSetting(); + DrawVaReadWriteStates(); + RedrawPanelData(); + Redraw4VaSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtVa(); + } + }else{ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + ReDrawCommonInf(); + DrawFixTextVa(); + IList->Edit[0].Show(); + RedrawVaIs4Linkage(); + DrawVaReadWriteStates(); + RedrawPanelData(); + Redraw4VaSmallPanelData(); + if(EdittingDescp){ + CnInput.FullRedraw(); + }else{ + Check4SelectedHtVa(); + } + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDevProperty::DrawVaReadWriteStates() +{ + char *tText; + if(IsHotKeyCheckingPermission)return; + if(VaReadWriteSta ==0 ){ + TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, " "); + tText=" "; + }else + if(VaReadWriteSta == 1){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "读取成功"); + if(LanguageEnCn==0)tText="读取成功"; else tText="Read OK "; + }else + if(VaReadWriteSta == 2){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "读取失败"); + if(LanguageEnCn==0)tText="读取失败"; else tText="Read Err"; + }else + if(VaReadWriteSta == 3){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "保存成功"); + if(LanguageEnCn==0)tText="保存成功"; else tText="Save OK "; + }else + if(VaReadWriteSta == 4){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "保存失败"); + if(LanguageEnCn==0)tText="保存失败"; else tText="Save Err"; + }else + if(VaReadWriteSta == 5){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "获取中 "); + if(LanguageEnCn==0)tText="获取中 "; else tText="Reading "; + }else + if(VaReadWriteSta == 6){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "写入中 "); + if(LanguageEnCn==0)tText="写入中 "; else tText="Writing "; + } + TextRender_string24(Lv.Grid.Left[3] + 190, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, tText); +} + +void TDevProperty::DrawVaReadWriteStates(unsigned char aNewState) +{ + VaReadWriteSta = aNewState; + DrawVaReadWriteStates(); +} + +void TDevProperty::InitHtVa() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextVa(); + IList->Edit[0].Init(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 72, 100,30,0,0,1,clNearBlack); + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + SendVaSettingRead(); + + RedrawVaIs4Linkage(); + RedrawVaSetting(); +} + +void TDevProperty::EditDescpReturnHtVa() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + + DrawFixTextVa(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + RedrawVaIs4Linkage(); + RedrawVaSetting(); + + ReDrawPanel(); + DrawVaReadWriteStates(); +} + +void TDevProperty::Redraw4VaNewLoad() +{ + IList->Edit[0].Show(); + SendVaSettingRead(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +void TDevProperty::Redraw4VaSmallPanelData() +{ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + + DrawMac(); +} + +void TDevProperty::SendVaSettingRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + VaRt.IsWait4ReadVaSetting = 1; + VaRt.IsWait4WriteVaSetting = 0; + VaRt.RecRdy = 0; + VaRt.RecCmd = 0; + VaRt.WaitTick = 0; + DrawVaReadWriteStates(5); + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 3; + CommData[1] = MainCtl.fData.Split.MyNum; + + CommData[2] = Path0; + ProcessingRt.P0 = Path0; + + CommData[3] = Path1; + ProcessingRt.P1 = Path1; + + aIde.BitF.Cmd = cmQueryStaticData; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendVaSettingWrite() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + VaRt.IsWait4ReadVaSetting = 0; + VaRt.IsWait4WriteVaSetting = 1; + VaRt.RecRdy = 0; + VaRt.RecCmd = 0; + VaRt.WaitTick = 0; + DrawVaReadWriteStates(6); + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =7; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 0; + CommData[1] = Path0; + ProcessingRt.P0 = Path0; + + //Start Addr End Addr + CommData[2] = Path1; + ProcessingRt.P1 = Path1; + CommData[3] = 0x07; //0x07:声光类别 + + //Set Linkage + //CommData[4] = Data.VaIs4Linkage; + //ExData.VaIs4Linkage = Data.VaIs4Linkage; + + //Set Tone + CommData[4] = Data.VaSoundType; + ExData.VaSoundType = Data.VaSoundType; + + //Set Sound And Visible + CommData[5] = Data.VaVisionType; + ExData.VaVisionType = Data.VaVisionType; + + Data.VaIs4Linkage =1; + CommData[6] = Data.VaIs4Linkage; + ExData.VaIs4Linkage = Data.VaIs4Linkage; + + aIde.BitF.Cmd = cmDeviceSetSens; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::ClearSelectedHtVa() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + TRoundSquare::sSelected(Lv.Grid.Left[2] +12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, 4, ItemColor); + break; + case 7: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 36, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 11: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 12: + if(LanguageEnCn==0)tText ="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 13: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 14: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearBlack;else aClr = clSilver; + if(LanguageEnCn==0)tText ="模拟启动"; else tText=" Sim Act"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clNearWhite, tText, 4, aClr); + break; + } +} +void TDevProperty::Check4SelectedHtVa() +{ + char *tText; + switch(Tag.Inx){ + case 0: + + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + TRoundSquare::sSelected(Lv.Grid.Left[2] +12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 7: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +210, Lv.Grid.Top[2] + 36, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 10: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 11: + IList->Edit[0].Selected = 1; + IList->Edit[0].Show(); + break; + case 12: + if(LanguageEnCn==0)tText ="读取"; else tText="Read"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +120, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 13: + if(LanguageEnCn==0)tText ="保存"; else tText="Save"; + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +210, ModuleRectLv3.Top + 72, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 14: + unsigned int aClr; + if(RunState == TRunModeCfg::RunModeAdjust)aClr = clNearWhite;else aClr = clSilver; + if(LanguageEnCn==0)tText ="模拟启动"; else tText=" Sim Act"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +180, ModuleRectLv4.Top + 6, 104, 30, 7, clDeepBlue, tText, 4, aClr); + break; + } +} + +void TDevProperty::RedrawVaIs4Linkage() +{ + if(Data.VaIs4Linkage){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevProperty::RedrawVaSetting() +{ + char *tText; + if(Data.VaVisionType == 0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.VaVisionType == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.VaVisionType == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + + if(Data.VaSoundType == 0){ + if(LanguageEnCn==0)tText="未知 "; else tText="Unknown"; + }else + if(Data.VaSoundType == 1){ + if(LanguageEnCn==0)tText="119 "; else tText="Std"; + }else + if(Data.VaSoundType == 2){ + if(LanguageEnCn==0)tText="滴滴 "; else tText="Beep "; + }else + if(Data.VaSoundType == 3){ + if(LanguageEnCn==0)tText="警报声"; else tText="ALERTS"; + } + + if(LanguageEnCn==0)tText="音调 0"; else tText="Tone 0"; + IList->Edit[0].SetText(tText ,24); + + IList->Edit[0].Show(); +} + +void TDevProperty::PushVaCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + if(aCmd == cmDeviceSetSens){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + ( 0x07 == RecData[3]) && + (ExData.VaSoundType == RecData[4]) && + (ExData.VaVisionType == RecData[5]) && + (ExData.VaIs4Linkage == RecData[6]) ) { + VaRt.RecRdy =1; + VaRt.RecCmd =aCmd; + } + }else + if(aCmd == cmQueryStaticData){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + ( 0 == RecData[3]) ){ + Data.VaSoundType = RecData[4]; + Data.VaVisionType = RecData[5]; + Data.VaIs4Linkage = RecData[6]; + VaRt.RecRdy =1; + VaRt.RecCmd =aCmd; + } + } +} + +TGuiMsgReturn TDevProperty::KeyInHtVa(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int HasPrc = 0; + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx < 6){ + KeyInCommonEdit(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Is4Linkage Type + if(aKey == VK_RIGHT){ + ClearSelectedHtVa(); + Tag.Inx = 7; + Check4SelectedHtVa(); + } + }else + if(Tag.Inx == 7){ + //Save Define Type + if(aKey == VK_LEFT){ + ClearSelectedHtVa(); + Tag.Inx = 6; + Check4SelectedHtVa(); + } + }else + if(Tag.Inx == 8){ + //Set As Feed Back + if(aKey == VK_RIGHT){ + ClearSelectedHtVa(); + Tag.Inx = 9; + Check4SelectedHtVa(); + } + }else + if(Tag.Inx == 9){ + //Set As Alram + if(aKey == VK_LEFT){ + ClearSelectedHtVa(); + Tag.Inx = 8; + Check4SelectedHtVa(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtVa(); + Tag.Inx = 10; + Check4SelectedHtVa(); + } + }else + if(Tag.Inx == 10){ + //Set As Sv + if(aKey == VK_LEFT){ + ClearSelectedHtVa(); + Tag.Inx = 9; + Check4SelectedHtVa(); + } + } + if(Tag.Inx == 11){ + //Set Output type + if(aKey == VK_RIGHT){ + ClearSelectedHtVa(); + Tag.Inx = 12; + Check4SelectedHtVa(); + } + }else + if(Tag.Inx == 12){ + //Read Input Type + if(aKey == VK_LEFT){ + ClearSelectedHtVa(); + Tag.Inx = 11; + Check4SelectedHtVa(); + }else + if(aKey == VK_RIGHT){ + ClearSelectedHtVa(); + Tag.Inx = 13; + Check4SelectedHtVa(); + } + }else + if(Tag.Inx == 13){ + //Save Input Type + if(aKey == VK_LEFT){ + ClearSelectedHtVa(); + Tag.Inx = 12; + Check4SelectedHtVa(); + } + }else + if(Tag.Inx == 14){ + ////Sim Start + if(aKey == VK_RIGHT){ + ClearSelectedHtVa(); + Tag.Inx = 15; + Check4SelectedHtVa(); + } + } + } + break; + case VK_UP: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtVa(); + Tag.Inx > Tag.InxMin ? Tag.Inx-- : Tag.Inx = 16; + Check4SelectedHtVa(); + } + break; + case VK_DOWN: + if(PortNumValid && AddrNumValid){ + ClearSelectedHtVa(); + Tag.Inx < 16 ? Tag.Inx++ : Tag.Inx = Tag.InxMin; + Check4SelectedHtVa(); + } + break; + case VK_TAB: + //PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + if(Tag.Inx == 6){ + Data.VaIs4Linkage = Data.VaIs4Linkage ? 0 :1; + Data.VaIs4Linkage =1; + RedrawVaIs4Linkage(); + }else + if(Tag.Inx == 8){ + Data.VaVisionType = 0; + RedrawVaSetting(); + }else + if(Tag.Inx == 9){ + Data.VaVisionType = 1; + RedrawVaSetting(); + }else + if(Tag.Inx == 10){ + Data.VaVisionType = 2; + RedrawVaSetting(); + }else + if(Tag.Inx == 11){ + Data.VaSoundType++; + if(Data.VaSoundType>3)Data.VaSoundType = 1; + + Data.VaSoundType = 0; + RedrawVaSetting(); + } + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case dfKEY_ENCN: + SendReqMac(); + break; + case VK_EXECUTE: + if(PortNumValid && AddrNumValid){ + if(Tag.Inx <6){ + KeyInCommonEnter(aKey); + }else{ + if(Tag.Inx == 6){ + //Change Linkage Type + Data.VaIs4Linkage = Data.VaIs4Linkage ? 0 :1; + Data.VaIs4Linkage =1; + RedrawVaIs4Linkage(); + }else + if(Tag.Inx == 7){ + //Write Va Setting + PermissionCmd = pcWriteVaSetting; + if(SystemPermission >2){ + SendVaSettingWrite(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 8){ + Data.VaVisionType = 0; + RedrawVaSetting(); + }else + if(Tag.Inx == 9){ + Data.VaVisionType = 1; + RedrawVaSetting(); + }else + if(Tag.Inx == 10){ + Data.VaVisionType = 2; + RedrawVaSetting(); + }else + if(Tag.Inx == 11){ + Data.VaSoundType++; + if(Data.VaSoundType>3)Data.VaSoundType = 1; + Data.VaSoundType = 0; + RedrawVaSetting(); + }else + if(Tag.Inx == 12){ + //Read Va Setting + SendVaSettingRead(); + }else + if(Tag.Inx == 13){ + //Write Va Setting + PermissionCmd = pcWriteVaSetting; + const unsigned char NeedPmsLevel = 2; + if(SystemPermission >2){ + SendVaSettingWrite(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 14){ + //Sim Start + if(RunState == TRunModeCfg::RunModeAdjust){ + PermissionCmd = pcSimStart; //pcSimAlram,pcSimStart,pcSimInputActive, + if(SystemPermission >1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + RealTimeSendCmdAbort(); + aMsg = guiMsgReturn; + break; + } + + + return aMsg; + +} + +void TDevProperty::Task1000MsVa() +{ + if(VaRt.IsWait4ReadVaSetting){ + if(VaRt.RecRdy){ + if(VaRt.RecCmd == cmQueryStaticData){ + VaRt.RecRdy = 0; + VaRt.IsWait4ReadVaSetting = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawVaReadWriteStates(1); + RedrawVaIs4Linkage(); + RedrawVaSetting(); + }else{ + VaReadWriteSta =1; + } + } + } + VaRt.RecRdy = 0; + } + VaRt.WaitTick ++; + if(VaRt.WaitTick > 6){ + VaRt.IsWait4ReadVaSetting = 0; + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawVaReadWriteStates(2); + }else{ + VaReadWriteSta =2; + } + } + }else + if(VaRt.IsWait4WriteVaSetting){ + if(VaRt.RecRdy){ + if(VaRt.RecCmd == cmDeviceSetSens){ + VaRt.IsWait4WriteVaSetting = 0; + //Add Record Here + Data.VaIs4Linkage = ExData.VaIs4Linkage; + Data.VaIs4Linkage =1; + Data.VaSoundType = ExData.VaSoundType; + Data.VaVisionType = ExData.VaVisionType; + //Record.OperateAdd_CfgAddrSmokeSensGrade(aFullPath.D32, Data.Modu); + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawVaReadWriteStates(3); + }else{ + VaReadWriteSta =3; + } + } + VaRt.RecRdy = 0; + } + VaRt.WaitTick ++; + if(VaRt.WaitTick > 6){ + VaRt.IsWait4WriteVaSetting = 0; + if( (EdittingDescp == 0) && (IsHotKeyCheckingPermission == 0) ){ + DrawVaReadWriteStates(4); + }else{VaReadWriteSta =4; + } + } + } + Redraw4VaSmallPanelData(); +} + + + + + diff --git a/MyCode/Gui/DevProperty.cpp b/MyCode/Gui/DevProperty.cpp new file mode 100644 index 0000000..348392a --- /dev/null +++ b/MyCode/Gui/DevProperty.cpp @@ -0,0 +1,2905 @@ +#include "Gui.h" +#include "DevProperty.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" + #include "HW_config.h" +} + +#define cmDeviceRuntimeDataStart 207 +#define cmDeviceRuntimeDataStop 208 + +static const char CharBcdText[20]= {"0123456789*------\0"}; +static const unsigned char stHexNum[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +//For Query Device Function to PopUp Show One Device Property Key:Value Edit or View + +//Root Device +//static const char cAvtive[12] = {"已挂载数量"}; +//static const char cCarry[12] = {"登记数量"}; +//static const char cVoltage[12] = {"电压V"}; +//static const char cCurrent[8] = {"电流A"}; +//static const char cTempe[8] = {"摄氏度"}; +//static const char cVer[8] = {"版本V"}; + +//static const char cFBV[16] = {"回码电压"}; +//static const char cFBC[16] = {"回码电流"}; + +//static const char cFBCZero[12] = {"静态电流mA"}; +//static const char cFBCFull[12] = {"动态电流mA"}; +//static const char cFBVZero[12] = {"静态电压V"}; +//static const char cFBVOL[12] = {"动态电压V"}; + +//static const char cConnectCount[12] = "已连接数量"; +//static const char cK[4] = "K"; +//static const char cCAN[8] = "CAN"; +//static const char cRS485[8] = "RS485"; +//static const char cEth[8] = "以太网"; +//static const char cSpeed[12] = "速度 KHz"; +//static const char cEth100M[12] = "100M 以太网"; +//static const char cEth1G[12] = "1G 以太网"; +//static const char cCommType[12] = "通讯类型"; + + +char TDevProperty::Text4CmpInc[16] = "芃\0\0" ; + +class TItemList *TDevProperty::sIList; + +void TDevProperty::DrawCommonInfTitleFixText() +{ + if(LanguageEnCn == 0){ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "回路号"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + + TextDigitRender2Right24(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] +6, clNearWhite, CtlNum); + TextRender_string24(Lv.Grid.Left[0] + 254, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + + TextRender_string24(Lv.Grid.Left[0] + 340, Lv.Grid.Top[0] +6, clNearWhite, "类型:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "状态:"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "地址号"); + TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, "注释信息:"); + + //User Code & Area Assign + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "二次码"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "分区号"); + }else + if(LanguageEnCn == 1){ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "LoopID"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "HostID"); + + TextDigitRender2Right24(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] +6, clNearWhite, CtlNum); + TextRender_string24(Lv.Grid.Left[0] + 254, Lv.Grid.Top[0] +6, clNearWhite, " Local"); + + TextRender_string24(Lv.Grid.Left[0] + 340, Lv.Grid.Top[0] +6, clNearWhite, "Type:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "State"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "Addr"); + TextRender_string24(Lv.Grid.Left[0] + 320, Lv.Grid.Top[0] + 40, clNearWhite, "Note:"); + + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "AuxID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + } +} + +void TDevProperty::Init(THwDevType aDevType, int aMode) +{ + HwDevType = aDevType; + IsPermission = 0; + PanelIsUsingText = 1; + Tag.Reset(); + EdittingDescp = 0; + IsExtInput = 1; + SetEnterMethod(aMode); + RuntimeData.Reset(); + PanelDrawData.Reset(); + PanelDrawData.TextDrawLine = 0; + + SmokerReadWriteSta =0; + TempeReadSta = 0; + VaReadWriteSta =0; + DisplayPadReadWriteSta =0; + DisplayPadDownloadDescpSta =0; + + + for(int i=0; i<16; i++)DebugBytes[i] = Text4CmpInc[i]; +} + +void TDevProperty::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + } + RedrawCommonInfTitle(); + switch(HwDevType){ + case htNoType: + FullRedrawNoType(Prm); + break; + case htSmoker: + FullRedrawhtSmoker(Prm); + break; + case htTempe: + FullRedrawhtTempe(Prm); + break; + case htHandPad: + FullRedrawhtHandPad(Prm); + break; + case htHydrantPad: + FullRedrawhtHydrantPad(Prm); + break; + case htModuleIn: + FullRedrawhtModuleIn(Prm); + break; + case htModuleInOut: + FullRedrawhtModuleInOut(Prm); + break; + case htModuleOut: + FullRedrawhtModuleOut(Prm); + break; + case htVa: + FullRedrawhtVa(Prm); + break; + case htDisplayPad: + FullRedrawhtDisplayPad(Prm); + break; + case htLinkagePowerSuply: + FullRedrawhtLinkagePowerSuply(Prm); + break; + default : + break; + } +} + +void TDevProperty::DrawStateCn(unsigned char aSta) +{ + +} + +void TDevProperty::DrawStateEn(unsigned char aSta) +{ + +} + +void TDevProperty::DrawState(unsigned char aSta) +{ + if(LanguageEnCn == 0){ + if(aSta & dEpStateBitFire){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clRed, 0xF); + IList->STextState.SetText("报警", 24); + }else + if(aSta & dEpStateBitStart){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("启动", 24); + }else + if(aSta & dEpStateBitSv){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("启动", 24); + }else + if(aSta & dEpStateBitFault){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("故障", 24); + }else + if(aSta & dEpStateBitFeedBack){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + IList->STextState.SetText("反馈", 24); + }else + if(aSta & dEpStateBitMask){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("屏蔽", 24); + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clDeepGreen, 0xF); + IList->STextState.SetText("正常", 24); + } + }else + if(LanguageEnCn == 1){ + if(aSta & dEpStateBitFire){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clRed, 0xF); + IList->STextState.SetText("Fire", 24); + }else + if(aSta & dEpStateBitStart){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("LINK", 24); + }else + if(aSta & dEpStateBitSv){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("SUPV", 24); + }else + if(aSta & dEpStateBitFault){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("Fail", 24); + }else + if(aSta & dEpStateBitFeedBack){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + IList->STextState.SetText("FBCK", 24); + }else + if(aSta & dEpStateBitMask){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + IList->STextState.SetText("Mask", 24); + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clDeepGreen, 0xF); + IList->STextState.SetText("Idle", 24); + } + } +} + +void TDevProperty::DrawMac() +{ + unsigned char Num, Num10; + TMyString::sClear(TextDraw); + TMyString::sAddOnStr("MAC:", TextDraw); + for(int i=0; i<6; i++){ + Num = RuntimeData.Mac[i] % 16; + Num10 = RuntimeData.Mac[i] / 16 % 16; + TMyString::sAddOnChar(stHexNum[Num10], TextDraw); + TMyString::sAddOnChar(stHexNum[Num], TextDraw); + if(i&0x01)TMyString::sAddOnChar(' ', TextDraw); + } + TextRender_string24(Lv.PanelSmall.Left + 256, Lv.PanelSmall.Top + 36, clNearWhite, SmallPanelColor, TextDraw); +} + +void TDevProperty::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick注册信息->单回路部件数据"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "回路->部件数据"); + }else{ + if(EnterMethod) + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Loop->Registed Info->Single Loop Device"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Loop->Device"); + } + + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); +} + +void TDevProperty::DrawCaption(void) +{ + +} + +void TDevProperty::InitPanel() +{ + int x,y,x2,y2, aW,aH,i; + + x = 20; + y = 150; + x2 = 799; + y2 = 340; + aW = x2 - x +1; + aH = y2 -y +1; + + aPanel->Init(x,y,aW,aH,0,0,clMoneyGreen, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearWhite,clBlue); + if(LanguageEnCn == 0){ + aPanel->Caption.SetText("按中/EN键切换输入法,设置键保存更改,返回键放弃更改并返回",24); + }else + if(LanguageEnCn == 1){ + aPanel->Caption.SetText("Key 中/EN To Switch Input Method,Key Set To Save",24); + } + aPanel->Caption.Enable = 1; + aPanel->Caption.Visible = 1; + + aPanel->SText[0].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn == 0){ + TMyString::sFromStr("请根据以下输入法提示输入", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr("Pay Attention To The Tip", aPanel->SText[0].Text); + } + aPanel->SText[0].Enable = 1; + aPanel->SText[0].Visible = 1; + + aPanel->Edit[ 0].Init(10,40,420,30,x,y,1,clNearBlack); + aPanel->Edit[ 0].Str.FromStr(IList->EditDescpShow.Str.Text); + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 1; + } + + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn == 0){ + TMyString::sFromStr("请根据以下输入法提示输入", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr("Pay Attention To The Tip", aPanel->SText[0].Text); + } + aPanel->SText[0].Show(); +} + +void TDevProperty::SetPath(unsigned char aCtlNum, unsigned char aPath0, unsigned char aPath1) +{ + unsigned char tP0, tP1, tT; + this->CtlNum = aCtlNum; + if(aPath0 && (aPath0 <= dPORT_MAX_COUNT)) PortNumValid = 1; else PortNumValid = 0; + if(aPath1 && (aPath1 <= dEP_MAX_COUNT_PER_PORT)) AddrNumValid = 1; else AddrNumValid = 0; + this->Path0 = aPath0; + this->Path1 = aPath1; + + tP0 = aPath0-1; + tP1 = aPath1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + dType = Port[tP0].dTypeTable[tP1]; + }else{ + dType = 0; + } +} + +void TDevProperty::Init4DType() +{ + Data.Reset(); + IList->TextOutClear(); + RectFillRender(Lv.Grid.Left[0], Lv.Grid.Top[3], Lv.Grid.Right[3], Lv.Grid.Bottom[4], ContentColor); + if(dType == dgTYPE_SMOKE_DETECTOR){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htSmoker; + InitHtSmoker(); + ResetTargetData(); + RealTimeSendCmd(1); + SendReqMac(); + CurveInit(Lv.Panel.Left+8, Lv.Panel.Top+8, Lv.Panel.Width-16, Lv.Panel.Heigh-16, 3); + CurveSetMargin(60, 2, 60, 2); + CurveSetGrid(6, 6, 50, 50); + CurveSetColor(clRed, clBlue, clPurple, clDeepGreen); + CurveSetScaling(); + }else + if(dType == dgTYPE_TEMPE_DETECTOR){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htTempe; + InitHtTempe(); + ResetTargetData(); + CurveInit(Lv.Panel.Left+8, Lv.Panel.Top+8, Lv.Panel.Width-16, Lv.Panel.Heigh-16, 2); + CurveSetMargin(60, 2, 60, 2); + CurveSetGrid(6, 6, 50, 50); + CurveSetColor(clDeepGreen, clPurple, clDeepGreen, clDeepGreen); + CurveSetScaling(); + }else + if(dType == dgTYPE_HAND_REPORT){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htHandPad; + InitHtHandPad(); + ResetTargetData(); + }else + if(dType == dgTYPE_FIRE_HydrantKp){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htHydrantPad; + InitHtHydrantPad(); + ResetTargetData(); + }else + if(dType == dgTYPE_IN_MODULE){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htModuleIn; + InitHtModuleIn(); + ResetTargetData(); + }else + if(dType == dgTYPE_OUT_MODULE){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htModuleOut; + InitHtModuleOut(); + ResetTargetData(); + }else + if(dType == dgTYPE_INOUT_MODULE_NonSource){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htModuleInOut; + InitHtModuleInOut(); + ResetTargetData(); + }else + if(dType == dgType_VAALRAM){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htVa; + InitHtVa(); + ResetTargetData(); + }else + if(dType == dgTYPE_DISPLAY_PAD){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htDisplayPad; + InitHtDisplayPad(); + ResetTargetData(); + }else + if(dType == dgTYPE_LINKAGE_POWERSUPLY){ + PanelDrawData.TextDrawLine = 0; + HwDevType = htLinkagePowerSuply; + InitHtLinkagePowerSuply(); + ResetTargetData(); + }else{ + PanelDrawData.TextDrawLine = 0; + HwDevType = htNoType; + ResetTargetData(); + InitNoType(); + } +} + +void TDevProperty::UpdataOnlineData() +{ + if(dType == dgTYPE_SMOKE_DETECTOR){ + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + SendSmokeCmdRead(); + if(EdittingDescp == 0){ + if(LanguageEnCn == 0){ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "获取中 "); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "Reading "); + } + } + }else + if(dType == dgTYPE_TEMPE_DETECTOR){ + TempeRt.IsWait4ReadSensType = 1; + TempeRt.RecRdy = 0; + TempeRt.RecCmd = 0; + TempeRt.WaitTick = 0; + SendTempeCmdRead(); + if(EdittingDescp == 0){ + if(LanguageEnCn == 0){ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "获取中 "); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "Reading "); + } + } + }else + if(dType == dgTYPE_HAND_REPORT){ + + }else + if(dType == dgTYPE_FIRE_HydrantKp){ + + }else + if(dType == dgTYPE_IN_MODULE){ + + }else + if(dType == dgTYPE_OUT_MODULE){ + + }else + if(dType == dgTYPE_INOUT_MODULE_NonSource){ + + }else + if(dType == dgType_VAALRAM){ + + }else + if(dType == dgTYPE_DISPLAY_PAD){ + + }else + if(dType == dgTYPE_LINKAGE_POWERSUPLY){ + + } +} + +void TDevProperty::RenewCommonInf() +{ + unsigned char tP0, tP1, Found, tType, tSta; + unsigned int tAddr; + //Draw Port Num + IList->EditPortNum.Str.FromUInt2Dg(Path0); + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + if(IList->EditPortNum.Selected)IList->EditPortNum.ShowCursor(); + + //Draw Addr Num + IList->EditAddrNum.Str.FromUInt3Dg(Path1); + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + if(IList->EditAddrNum.Selected)IList->EditAddrNum.ShowCursor(); + + Found = 0; + if(CtlNum == MainCtl.fData.Split.MyNum){ + //Draw If Registed + if( (Path0) && (Path0 <= dPORT_MAX_COUNT) ){ + if( (Path1) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + Found = 1; + tType = Port[tP0].dTypeTable[tP1]; + dType = tType; + tSta = Port[tP0].StateTable[tP1]; + } + } + } + if(Found){ + if(LanguageEnCn==0)IList->STextDType.SetText(StrTypeShortName[tType],24); + else IList->STextDType.SetText(StrTypeShortNameEn[tType],24); + DrawState(tSta); + if(LanguageEnCn == 0){ + IList->STextRegisted.SetText("已注册", 24); + }else{ + IList->STextRegisted.SetText("Reg", 24); + } + IsRegisted = 1; + }else{ + IList->STextDType.SetText("---------", 24); + IList->STextState.SetText("----", 24); + if(LanguageEnCn == 0){ + IList->STextRegisted.SetText("未注册", 24); + }else{ + IList->STextRegisted.SetText("Not Reg", 24); + } + IsRegisted = 0; + } + tAddr = dAddrSdRam_Descp + (tP0 * 256 * 32) + (tP1 * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + + IList->EditUserCode.Str.FromUInt8Dg(Port[tP0].UcList[tP1].Full); + IList->EditAreaAssign.Str.FromUInt4Dg(Port[tP0].Area[tP1]); + + IList->STextDType.Show(); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + + Check4Selected(); + }else{ + + } +} + +void TDevProperty::ReDrawCommonInf() +{ + unsigned char tP0, tP1, Found, tType, tSta; + unsigned int tAddr; + //Draw Port Num + + Found = 0; + if(CtlNum == MainCtl.fData.Split.MyNum){ + //Draw If Registed + if( (Path0) && (Path0 <= dPORT_MAX_COUNT) ){ + if( (Path1) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + Found = 1; + tType = Port[tP0].dTypeTable[tP1]; + tSta = Port[tP0].StateTable[tP1]; + } + } + } + if(Found){ + if(LanguageEnCn==0)IList->STextDType.SetText(StrTypeShortName[tType],24); + else IList->STextDType.SetText(StrTypeShortNameEn[tType],24); + DrawState(tSta); + if(LanguageEnCn == 0){ + IList->STextRegisted.SetText("已注册", 24); + }else{ + IList->STextRegisted.SetText("Reg", 24); + } + IsRegisted = 1; + }else{ + IList->STextDType.SetText("---------", 24); + IList->STextState.SetText("----", 24); + if(LanguageEnCn == 0){ + IList->STextRegisted.SetText("未注册", 24); + }else{ + IList->STextRegisted.SetText("Not Reg", 24); + } + IsRegisted = 0; + } + tAddr = dAddrSdRam_Descp + (tP0 * 256 * 32) + (tP1 * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + + IList->EditUserCode.Str.FromUInt8Dg(Port[tP0].UcList[tP1].Full); + IList->EditAreaAssign.Str.FromUInt4Dg(Port[tP0].Area[tP1]); + + IList->STextDType.Show(); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + }else{ + + } +} + +void TDevProperty::ClearCommonInf() +{ + IList->STextDType.SetText("------",24); + IList->STextState.SetText("----", 24); + IList->STextRegisted.SetText("------", 24); + IList->EditDescpShow.Str.Text[0] = '\0'; + IList->EditDescpShow.Str.Text[1] = '\0'; + IList->EditUserCode.Str.FromStr("--------"); + IList->EditAreaAssign.Str.FromStr("----"); + + IList->STextDType.Show(); + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + +} + +void TDevProperty::ReLoadAndDrawDescp() +{ + unsigned char tP0, tP1, Ava, tType, tSta; + unsigned int tAddr; + + Ava = 0; + if(CtlNum == MainCtl.fData.Split.MyNum){ + //Draw If Registed + if( (Path0) && (Path0 <= dPORT_MAX_COUNT) ){ + if( (Path1) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tP0 = Path0-1; + tP1 = Path1-1; + Ava = 1; + } + } + if(Ava){ + tAddr = dAddrSdRam_Descp + (tP0 * 256 * 32) + (tP1 * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + IList->EditDescpShow.Show(); + } + } +} + + +void TDevProperty::DrawCommonInfTitle() +{ + DrawCommonInfTitleFixText(); + + IList->STextDType.Init(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] + 2, 240, 30, 0, 0, clNearWhite, ItemColor); + IList->STextState.Init(Lv.Grid.Left[0] + 730, Lv.Grid.Top[0] + 2, 70, 30, 0, 0, clNearWhite, ItemColor); + IList->STextRegisted.Init(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] + 36, 120, 30, 0, 0, clNearWhite, ItemColor); + IList->STextCtlNum.Init(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 6, 120, 30, 0, 0, clNearWhite, ItemColor); + + IList->EditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 2, 50, 30, 0, 0, 1, clNearWhite); + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + IList->EditDescpShow.Init(Lv.Grid.Left[0] + 390, Lv.Grid.Top[0] + 36, 400, 30, 0, 0, 1, clNearWhite); + + IList->STextDType.Enable = 1; + IList->STextDType.Visible =1; + IList->STextState.Enable = 1; + IList->STextState.Visible =1; + IList->STextRegisted.Enable = 1; + IList->STextRegisted.Visible =1; + IList->STextCtlNum.Enable = 1; + IList->STextCtlNum.Visible =1; + + IList->EditPortNum.SetMaxLen(2); + IList->EditAddrNum.SetMaxLen(3); + if(EnterMethod) + IList->EditPortNum.Enable = 0; + else + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible = 1; + IList->EditAddrNum.Enable = 1; + IList->EditAddrNum.Visible = 1; + IList->EditDescpShow.Enable = 1; + IList->EditDescpShow.Visible = 1; + IList->EditDescpShow.IsShowCursor = 0; + + //User Code & Area Assign + if(LanguageEnCn == 0){ + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "二次码"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "分区号"); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "AuxID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + } + IList->EditUserCode.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 6, 108, 30, 0, 0, 1, clNearWhite); + IList->EditAreaAssign.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 40, 108, 30, 0, 0, 1, clNearWhite); + + IList->EditUserCode.Enable = 1; + IList->EditUserCode.Visible =1; + IList->EditUserCode.SetMaxLen(8); + IList->EditAreaAssign.Enable = 1; + IList->EditAreaAssign.Visible =1; + IList->EditAreaAssign.SetMaxLen(4); +} + +void TDevProperty::RedrawCommonInfTitle() +{ + DrawCommonInfTitleFixText(); + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); +} + +void TDevProperty::Redraw4DescpEdit() +{ + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.SetPstTail(); + IList->EditDescpShow.Show(); + + RectFillRender(aPanel->Bound.Left, aPanel->Bound.Top, aPanel->Bound.Right, aPanel->Bound.Bottom, ContentColor); + if( (HwDevType == htVa ) || (HwDevType == htModuleIn) || (HwDevType == htModuleInOut) ) { + for(int i=1; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + }else{ + for(int i=1; iEditUserCode.Show(); + IList->EditAreaAssign.Show(); + + switch(HwDevType){ + case htNoType: + EditDescpReturnHtNoType(); + break; + case htSmoker: + EditDescpReturnHtSmoker(); + break; + case htTempe: + EditDescpReturnHtTempe(); + break; + case htHandPad: + EditDescpReturnHtHandPad(); + break; + case htHydrantPad: + EditDescpReturnHtHydrantPad(); + break; + case htModuleIn: + EditDescpReturnHtModuleIn(); + break; + case htModuleInOut: + EditDescpReturnHtModuleInOut(); + break; + case htModuleOut: + EditDescpReturnHtModuleOut(); + break; + case htVa: + EditDescpReturnHtVa(); + break; + case htDisplayPad: + EditDescpReturnHtDisplayPad(); + break; + case htLinkagePowerSuply: + EditDescpReturnHtLinkagePowerSuply(); + break; + default : + + break; + } +} + +void TDevProperty::Redraw4NewLoad() +{ + Data.Reset(); + IList->TextOutClear(); + switch(HwDevType){ + case htNoType: + Redraw4NoTypeNewLoad(); + break; + case htSmoker: + Redraw4SmokerNewLoad(); + break; + case htTempe: + Redraw4TempeNewLoad(); + break; + case htHandPad: + Redraw4HandPadNewLoad(); + break; + case htHydrantPad: + Redraw4HydrantPadNewLoad(); + break; + case htModuleIn: + Redraw4ModuleInNewLoad(); + break; + case htModuleInOut: + Redraw4ModuleInOutNewLoad(); + break; + case htModuleOut: + Redraw4ModuleOutNewLoad(); + break; + case htVa: + Redraw4VaNewLoad(); + break; + case htDisplayPad: + Redraw4DisplayPadNewLoad(); + break; + case htLinkagePowerSuply: + Redraw4LinkagePowerSuplyNewLoad(); + break; + default : + + break; + } +} + +TGuiMsgReturn TDevProperty::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn SubRtnMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + }else + if(EdittingDescp){ + const char *p; + if(aKey == dfKEY_SETUP){ + //Save and return + TMyString::sFromStr(aPanel->Edit[0].Str.Text, IList->EditDescpShow.Str.Text); + TMyString::sBrokeFixLen(IList->EditDescpShow.Str.Text, 32); + Redraw4DescpEdit(); + EdittingDescp = 0; + }else + if(IsExtInput){ + if(aKey == dfKEY_ENCN){ + CnInput.KeyIn(aKey); + if(0){ + IsExtInput = 1; + CnInput.OverPrint(this->aPanel->Color); + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + if(LanguageEnCn == 0){ + TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr("Enter The Numbers Directly", aPanel->SText[0].Text); + } + aPanel->SText[0].Show(); + } + }else + if(aKey == VK_RETURN){ + //Just return + Redraw4DescpEdit(); + EdittingDescp = 0; + }else{ + if( (aKey == VK_DELETE) && (CnInput.sEdit.Pst == -1) ){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + }else{ + p = CnInput.KeyIn(aKey); + if(p != nullptr){ + if(CnInput.GotChar[0] != '\0'){ + aPanel->Edit[0].Pst = aPanel->Edit[0].Str.Insert(CnInput.GotChar, aPanel->Edit[0].Pst); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + } + } + } + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + break; + case dfKEY_ENCN: + if(IsExtInput == 0){ + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn == 0){ + TMyString::sFromStr("当前根据输入法输入", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr("Enter The Numbers Directly", aPanel->SText[0].Text); + } + aPanel->SText[0].Show(); + } + break; + case VK_EXECUTE: + + break; + case VK_RETURN: + Redraw4DescpEdit(); + EdittingDescp = 0; + break; + } + } + }else{ + if( (aKey == dfKEY_SETUP) && (Tag.Inx == 3) ){ + //Descp Show + PermissionCmd = pcEditDescp; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + switch(HwDevType){ + case htNoType: + SubRtnMsg = KeyInHtNoType(aKey); + break; + case htSmoker: + SubRtnMsg = KeyInHtSmoker(aKey); + break; + case htTempe: + SubRtnMsg = KeyInHtTempe(aKey); + break; + case htHandPad: + SubRtnMsg = KeyInHtHandPad(aKey); + break; + case htHydrantPad: + SubRtnMsg = KeyInHtHydrantPad(aKey); + break; + case htModuleIn: + SubRtnMsg = KeyInHtModuleIn(aKey); + break; + case htModuleInOut: + SubRtnMsg = KeyInHtModuleInOut(aKey); + break; + case htModuleOut: + SubRtnMsg = KeyInHtModuleOut(aKey); + break; + case htVa: + SubRtnMsg = KeyInHtVa(aKey); + break; + case htDisplayPad: + SubRtnMsg = KeyInHtDisplayPad(aKey); + break; + case htLinkagePowerSuply: + SubRtnMsg = KeyInHtLinkagePowerSuply(aKey); + break; + default : + SubRtnMsg = guiMsgReturn; + break; + } + return SubRtnMsg; + } + return aMsg; +} + + + +TGuiMsgReturn TDevProperty::KeyInCommonEdit(unsigned char aKey) +{ + int tVal; + unsigned char tP0, tP1, NewType, IsNewTarget; + TGuiMsgReturn aMsg = guiMsgNone; + int HasPrcKey = 0; + if(Tag.Inx == 0){ + //Ctl Num + }else + if(Tag.Inx == 1){ + //Port Num + IsNewTarget = 0; + IList->EditPortNum.KeyIn(aKey); + tVal = IList->EditPortNum.Str.ToInteger(); + if( (tVal >0) && (tVal <= dPORT_MAX_COUNT) )PortNumValid = 1; else PortNumValid = 0; + if( PortNumValid && AddrNumValid){ + if(Path0 != tVal){ + ClearReqDataState(); + Path0 = tVal; + IList->EditPortNum.SelectedColor = clBlue; + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + NewType = Port[tP0].dTypeTable[tP1]; + }else{ + NewType = 0; + } + if(NewType == dType){ + //Load New Addr Inf + Redraw4NewLoad(); + UpdataOnlineData(); + ResetTargetData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + } + }else{ + ClearReqDataState(); + Path0 = 0; + if(dType != 0){ + dType = 0; + Init4DType(); + } + RealTimeSendCmdAbort(); + IList->EditPortNum.SelectedColor = clRed; + ClearCommonInf(); + } + IList->EditPortNum.Show(); + }else + if(Tag.Inx == 2){ + //Addr Num + if(aKey == VK_RIGHT){ + if(IList->EditAddrNum.Pst >= IList->EditAddrNum.Str.GetEndPst()){ + if( PortNumValid && AddrNumValid){ + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + Tag.Inx = 3; + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.Show(); + HasPrcKey = 1; + } + } + } + if(HasPrcKey == 0){ + IsNewTarget = 0; + IList->EditAddrNum.KeyIn(aKey); + tVal = IList->EditAddrNum.Str.ToInteger(); + if( (tVal >0) && (tVal <= dEP_MAX_COUNT_PER_PORT) )AddrNumValid = 1; else AddrNumValid = 0; + if( PortNumValid && AddrNumValid){ + if(Path1 != tVal){ + ClearReqDataState(); + Path1 = tVal; + IList->EditAddrNum.SelectedColor = clBlue; + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + NewType = Port[tP0].dTypeTable[tP1]; + }else{ + NewType = 0; + } + if(NewType == dType){ + //Load New Addr Inf + + Redraw4NewLoad(); + UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + } + }else{ + ClearReqDataState(); + Path1 = 0; + if(dType != 0){ + dType = 0; + Init4DType(); + } + RealTimeSendCmdAbort(); + IList->EditAddrNum.SelectedColor = clRed; + ClearCommonInf(); + } + IList->EditAddrNum.Show(); + } + }else + if(Tag.Inx == 3){ + //Descp Show + if(aKey == VK_LEFT){ + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + Tag.Inx = 2; + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + } + }else + if(Tag.Inx == 4){ + //User Code + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + }else + if(Tag.Inx == 5){ + //Area + IList->EditAreaAssign.KeyIn(aKey); + IList->EditAreaAssign.Show(); + } + return aMsg; +} + +TGuiMsgReturn TDevProperty::KeyInCommonEnter(unsigned char aKey) +{ + int aVal; + TGuiMsgReturn aMsg = guiMsgNone; + if(Tag.Inx == 0){ + //Ctl Num + }else + if(Tag.Inx == 1){ + //Port Num + }else + if(Tag.Inx == 2){ + //Addr Num + }else + if(Tag.Inx == 3){ + //Descp Show + PermissionCmd = pcWriteDescp; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 4){ + //User Code + if(SystemPermission >2){ + if( Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + aVal = IList->EditUserCode.Str.ToInteger(); + if( (aVal < 100000000) && (aVal>0) ){ + aUcSetting.Full = aVal; + WriteAUserCode2Flash(Path0, Path1, aUcSetting); + ReadAllEpUserCode(); + if(aVal == Port[Path0-1].UcList[Path1-1].Full){ + if(LanguageEnCn == 0){ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "保存成功"); + }else{ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "Save OK "); + } + }else{ + if(LanguageEnCn == 0){ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "保存失败"); + }else{ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "Save Err"); + } + } + IList->EditUserCode.Str.FromUInt8Dg(Port[Path0-1].UcList[Path1-1].Full); + IList->EditUserCode.Show(); + } + } + }else{ + ClearSelected(); + IsPermission = 1; + PermissionCmd = pcWriteUserCode; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 5){ + //Area + aVal = IList->EditAreaAssign.Str.ToInteger(); + aVal &= 0x0000FFFF; + AreaNum = aVal; + if((AreaNum >-1) && (AreaNum <= dAreaCountMax)){ + if(SystemPermission >2){ + if( Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + PermissionCmd = pcWriteAreaInx; + PermissionCmdGO(); + } + }else{ + ClearSelected(); + IsPermission = 1; + PermissionCmd = pcWriteAreaInx; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + return aMsg; +} + + +void TDevProperty::ReadAllEpUserCode() +{ + Record.ReadDevUserSet(); +} + +void TDevProperty::ResetTargetData() +{ + RuntimeData.Reset(); + IList->RealtimeData.Reset(); + IList->TextOutClear(); + PanelDrawData.ResetNotFull(); + switch(HwDevType){ + case htNoType: + + break; + case htSmoker: + RealTimeSendCmd(1); + SendSmokeCmdRead(); + SendReqMac(); + break; + case htTempe: + RealTimeSendCmd(1); + SendTempeCmdRead(); + SendReqMac(); + break; + case htHandPad: + RealTimeSendCmd(1); + SendReqMac(); + break; + case htHydrantPad: + RealTimeSendCmd(1); + SendReqMac(); + break; + case htModuleIn: + RealTimeSendCmd(1); + SendModuleSignalInOutTypeRead(); + SendReqMac(); + break; + case htModuleInOut: + RealTimeSendCmd(1); + SendModuleSignalInOutTypeRead(); + SendReqMac(); + break; + case htModuleOut: + RealTimeSendCmd(1); + SendModuleSignalInOutTypeRead(); + SendReqMac(); + break; + case htVa: + RealTimeSendCmd(1); + SendVaSettingRead(); + SendReqMac(); + break; + case htDisplayPad: + RealTimeSendCmd(1); + SendReqMac(); + break; + case htLinkagePowerSuply: + RealTimeSendCmd(1); + SendReqMac(); + break; + default : + + break; + } +} + +void TDevProperty::PushInnerCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + unsigned char Inx = pData[3]; + + if(aCmd == cmQueryMacCode){ + if(pData[0] == 1){ + if( (pData[2] == Path0) && (pData[3] == Path1) ) { + RuntimeData.MacPath0 = Path0; + RuntimeData.MacPath1 = Path1; + RuntimeData.MacHasUpdate |= 1; + RuntimeData.Mac[0] = pData[4]; + RuntimeData.Mac[1] = pData[5]; + RuntimeData.Mac[2] = pData[6]; + RuntimeData.Mac[3] = pData[7]; + } + }else + if(pData[0] == 2){ + if( (pData[2] == Path0) && (pData[3] == Path1) ) { + RuntimeData.MacPath0 = Path0; + RuntimeData.MacPath1 = Path1; + RuntimeData.MacHasUpdate |= 2; + + RuntimeData.Mac[4] = pData[4]; + RuntimeData.Mac[5] = pData[5]; + RuntimeData.Mac[6] = pData[6]; + RuntimeData.Mac[7] = 0; + } + } + return; + } + + switch(HwDevType){ + case htNoType: + + break; + case htSmoker: + PushSmokeCanData(aCmd, pData); + break; + case htTempe: + PushTempeCanData(aCmd, pData); + break; + case htHandPad: + + break; + case htHydrantPad: + + break; + case htModuleIn: + PushModuleInCanData(aCmd, pData); + break; + case htModuleInOut: + PushModuleInOutCanData(aCmd, pData); + break; + case htModuleOut: + PushModuleOutCanData(aCmd, pData); + break; + case htVa: + PushVaCanData(aCmd, pData); + break; + case htDisplayPad: + PushDisplayPadCanData(aCmd, pData); + break; + case htLinkagePowerSuply: + PushLinkagePowerSuplyCanData(aCmd, pData); + break; + default : + + break; + } +} + + +void TDevProperty::PushInnerCanRuntimeData(unsigned char aCmd, unsigned char *pData) +{ + int i; + switch(HwDevType){ + case htNoType: + + break; + case htSmoker: + + break; + case htTempe: + + break; + case htHandPad: + + break; + case htHydrantPad: + + break; + case htModuleIn: + + break; + case htModuleInOut: + + break; + case htModuleOut: + + break; + case htVa: + + break; + case htDisplayPad: + + break; + case htLinkagePowerSuply: + + break; + default : + + break; + } +} + +void TDevProperty::Show(void) +{ + IsShow = 1; + DrawSelf(); +} + +void TDevProperty::Task1000Ms() +{ + if(IsShow == 0) return; + if( (Path0) && (Path1 ) ){ + if( (Path0 <= dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + if(IsRegisted){ + const unsigned char tSta = Port[Path0-1].StateTable[Path1-1]; + DrawState(tSta); + IList->STextState.Show(); + } + } + } + switch(HwDevType){ + case htNoType: + + break; + case htSmoker: + Task1000MsSmoker(); + break; + case htTempe: + Task1000MsTempe(); + break; + case htHandPad: + Task1000MsHandPad(); + break; + case htHydrantPad: + Task1000MsHydrantPad(); + break; + case htModuleIn: + Task1000MsModuleIn(); + break; + case htModuleInOut: + Task1000MsModuleInOut(); + break; + case htModuleOut: + Task1000MsModuleOut(); + break; + case htVa: + Task1000MsVa(); + break; + case htDisplayPad: + Task1000MsDisplayPad(); + break; + case htLinkagePowerSuply: + Task1000MsLinkagePowerSuply(); + break; + default : + + break; + } +} + +void TDevProperty::RunTimeSendCmd(const int StartStop) +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[2] = Path0; + CommData[3] = Path1; + + if(StartStop != 0){ + aIde.BitF.Cmd = cmDeviceRuntimeDataStart; + }else{ + aIde.BitF.Cmd = cmDeviceRuntimeDataStop; + } + Len = 4; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::RealTimeSendCmd(const int StartStop) +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[2] = Path0; + CommData[3] = Path1; + + if(StartStop != 0){ + aIde.BitF.Cmd = cmQueryRuntimeData; + }else{ + aIde.BitF.Cmd = cmQueryAbout; + } + Len = 4; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::RealTimeSendCmdAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + aIde.BitF.Cmd = cmQueryAbout; + Len = 4; + //Prm + CommData[0] = 0; + CommData[1] = 0; + CommData[2] = Path0; + CommData[3] = Path1; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendReqMac() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + aIde.BitF.Cmd = cmQueryMacCode; + Len = 4; + //Prm + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = Path0; + CommData[3] = Path1; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendCmdLightOn() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + aIde.BitF.Cmd = cmDevLightOn; + Len = 5; + //Prm + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = Path0; + CommData[3] = Path1; + CommData[4] = 1; + CommData[5] = 0; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + + if( (Path0) && (Path0<=dPORT_MAX_COUNT) && (Path1) ){ + aP0 = Path0-1; + aP1 = Path1-1; + Port[aP0].HasSetLightOn[aP1] = 1; + } + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendCmdLightOff() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + aIde.BitF.Cmd = cmDevLightOn; + Len = 6; + //Prm + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = 255; + CommData[3] = 255; + CommData[4] = 0; + CommData[5] = 0; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendCmdMuteBroadcast() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + aIde.BitF.Cmd = cmDevMute; + Len = 4; + //Prm + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = 255; + CommData[3] = 255; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::SendCmdMute() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + aIde.BitF.Cmd = cmDevMute; + Len = 4; + //Prm + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = Path0; + CommData[3] = Path1; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevProperty::RuntimeDataPrc(u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3) +{ + unsigned short tDa; + if(aInx ==0){ + RuntimeData.voltage = D1; + switch(HwDevType){ + case htSmoker: tDa = D2; tDa<<=8; tDa |= D3; RuntimeData.SmokerBL = tDa;break; + case htTempe: tDa = D2; tDa<<=8; tDa |= D3; RuntimeData.TempeOriginData = tDa;break; + case htModuleIn: RuntimeData.ModuleInAdVal = D2; break; + case htModuleInOut: RuntimeData.ModuleInAdVal = D2; break; + case htDisplayPad: tDa = D2; tDa<<=8; tDa |= D3; RuntimeData.DisplayPadAlramCount = tDa; break; + case htLinkagePowerSuply:tDa = D2; tDa<<=8; tDa |= D3; RuntimeData.BatVoltage = tDa; break; + default : + break; + } + if(HwDevType == htSmoker){ + Curve.Smoke.DataAva[0] =1; + Curve.Smoke.Blue = RuntimeData.SmokerBL; + }else + if(HwDevType == htTempe){ + Curve.Tempe.DataAva[0] =1; + Curve.Tempe.Val = RuntimeData.TempeOriginData; + } + }else + if(aInx == 1){ + switch(HwDevType){ + case htSmoker: tDa = D0; tDa<<=8; tDa |= D1; RuntimeData.SmokerIR = tDa;break; + case htTempe: RuntimeData.TempeCelsiusData = D0; break; + case htLinkagePowerSuply: + RuntimeData.BatEnergy = D0; + tDa = D1; tDa<<=8; tDa |= D2; + RuntimeData.OutputVoltage = tDa; + RuntimeData.OutputCurrent = D3; + RuntimeData.OutputCurrent<<=8; + break; + default : + break; + } + if(HwDevType == htSmoker){ + Curve.Smoke.DataAva[1] =1; + Curve.Smoke.IR = RuntimeData.SmokerIR; + }else + if(HwDevType == htTempe){ + Curve.Tempe.DataAva[1] =1; + Curve.Tempe.Celsius = RuntimeData.TempeCelsiusData; + if(Curve.Tempe.DataAva[0]){ + CurvePutDataTempe(Curve.Tempe.Val,Curve.Tempe.Celsius,0,0); + Curve.HasUpdate =1; + } + } + Curve.Tempe.DataAva[0] =0; + Curve.Tempe.DataAva[1] =0; + }else + if(aInx == 2){ + switch(HwDevType){ + case htSmoker: + tDa = D2; tDa<<=8; tDa |= D3; RuntimeData.SmokerPrmM = tDa; + Curve.Smoke.MVal = RuntimeData.SmokerPrmM; + Curve.Smoke.DataAva[2] =1; + if(Curve.Smoke.DataAva[0] && Curve.Smoke.DataAva[1]){ + CurvePutDataSmoke(Curve.Smoke.IR, Curve.Smoke.Blue, Curve.Smoke.MVal, 0); + Curve.HasUpdate =1; + } + break; + case htTempe: + //Data.GotTempeSensType[0] = 0xF1; + //Data.GotTempeSensType[1] = Path0; + //Data.GotTempeSensType[2] = Path1; + //Data.GotTempeSensType[3] = D1; + break; + case htLinkagePowerSuply: + RuntimeData.OutputCurrent |= D0; + RuntimeData.PwrLoaddingPercent = D1; + break; + default : + break; + } + Curve.Smoke.DataAva[0] =0; + Curve.Smoke.DataAva[1] =0; + Curve.Smoke.DataAva[2] =0; + }else + if(aInx == 3){ + switch(HwDevType){ + case htSmoker: + + break; + default : + break; + } + } + + if(Curve.HasUpdate){ + if(PanelIsUsingText == 0){ + if(Curve.HasDrawOutline == 0){ + if( (EdittingDescp == 0) && (IsPermission == 0) ) + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + CurveDraw(1); + }else{ + if( (EdittingDescp == 0) && (IsPermission == 0) ) + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + CurveDraw(0); + } + } + } +} + +void TDevProperty::PushOneRealDataReport(u8 aP0, u8 aP1, u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3) +{ + unsigned int aAddr, i, Num, Num10, Pst; + unsigned char Da[4]; + int x,y; + + const int MaxLen=41; + + if(IsShow == 0)return; + + if(aP0 != Path0)return; + if(aP1 != Path1)return; + + RuntimeDataPrc(aInx, D0,D1,D2,D3); + + Da[0] = D0; + Da[1] = D1; + Da[2] = D2; + Da[3] = D3; + if(PanelDrawData.TextDrawLine >7){ + PanelDrawData.Reset(); + } + if(aInx == 0){ + PanelDrawData.TextDrawLine++; + if(PanelDrawData.TextDrawLine >7){ + PanelDrawData.Reset(); + } + + if(PanelDrawData.TextDrawLine == 0){ + for(int z=0; z<8; z++){ + for(int g=0; g<80; g++){ + IList->TextOut[z][g] = '\0'; + } + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + } + } + } + for(int g=0; gTextOut[PanelDrawData.TextDrawLine][g] = ' '; + } + for(int g=MaxLen; g<80; g++){ + IList->TextOut[PanelDrawData.TextDrawLine][g] = '\0'; + } + y = Lv.Panel.Top + 1; + y = y + PanelDrawData.TextDrawLine * 27; + x = Lv.Panel.Left + 2; + TMyString::sClear(TextTmp); + PanelDrawData.UsingTextHex = PanelDrawData.DesertTextHex; + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtNone){ + if(PanelDrawData.UsingTextHex)PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] =dtHex; + else PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] =dtDec; + } + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtHex){ + for(i=0; i<4; i++){ + Pst= 0 + i*3; + Num = Da[i] % 16; + Num10 = Da[i] / 16 % 16; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = stHexNum[Num10]; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = stHexNum[Num]; + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ','; + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + }else + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtDec){ + for(i=0; i<4; i++){ + Pst= 0 + i*4; + Num = Da[i] / 100; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = Num + '0'; + Num = Da[i] % 100 / 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = Num + '0'; + Num = Da[i] % 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = Num + '0'; + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ','; + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + } + }else + if(aInx < 4){ + y = Lv.Panel.Top + 1; + y = y + PanelDrawData.TextDrawLine * 27; + x = Lv.Panel.Left + 2; + TMyString::sClear(TextTmp); + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtHex){ + for(i=0; i<4; i++){ + Pst= aInx*12 + i*3; + if(Pst > (MaxLen-1-2))break; + Num = Da[i] % 16; + Num10 = Da[i] / 16 % 16; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = stHexNum[Num10]; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = stHexNum[Num]; + if((Pst+2)<=(MaxLen-1)){ + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ','; + } + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) /*&& (aInx == 3)*/ ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + }else + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtDec){ + for(i=0; i<4; i++){ + Pst= aInx*16 + i*4; + if(Pst > (MaxLen-1-3))break; + Num = Da[i] / 100; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = Num + '0'; + Num = Da[i] % 100 / 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = Num + '0'; + Num = Da[i] % 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = Num + '0'; + if((Pst+3)<=(MaxLen-1)){ + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ','; + } + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) /*&& (aInx == 3)*/ ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + } + } +} + +void TDevProperty::PermissionCmdGO() +{ + int aVal; + unsigned char aBits; + switch(PermissionCmd){ + case pcWriteDescp: + TDescpWrite::sRestoreDescp(Path0, Path1, IList->EditDescpShow.Str.Text); + IList->EditDescpShow.SelectedColor = clDeepGreen; + if(LanguageEnCn == 0){ + IList->EditDescpShow.Str.FromStr("写入注释信息, 重新读取注释信息"); + }else{ + IList->EditDescpShow.Str.FromStr("Save And Reload"); + } + IList->EditDescpShow.Show(); + sDelayMs(100); + IList->EditDescpShow.SelectedColor = clBlue; + TDescpWrite::sWrite2Flash(Path0); + ReLoadAndDrawDescp(); + break; + case pcWriteUserCode: + if( Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + aVal = IList->EditUserCode.Str.ToInteger(); + if( (aVal < 100000000) && (aVal>0) ){ + aUcSetting.Full = aVal; + WriteAUserCode2Flash(Path0, Path1, aUcSetting); + ReadAllEpUserCode(); + if(LanguageEnCn == 0){ + if(aVal == Port[Path0-1].UcList[Path1-1].Full){ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "保存成功"); + }else{ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "保存失败"); + } + }else{ + if(aVal == Port[Path0-1].UcList[Path1-1].Full){ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "Save OK "); + }else{ + TextRender_string24(IList->EditUserCode.Bound.Right + 2, IList->EditUserCode.Bound.Top +4, clNearWhite, ItemColor, "Save Err"); + } + } + IList->EditUserCode.Str.FromUInt8Dg(Port[Path0-1].UcList[Path1-1].Full); + IList->EditUserCode.Show(); + } + } + break; + case pcWriteAssignType: + if( Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + if(LanguageEnCn == 0){ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "写入中 "); + WriteAAssignType2Flash(Path0, Path1, AssignTypeSetting); + Record.ReadDevUserSet(); + if(AssignTypeSetting == Port[Path0-1].AssignType[Path1-1]){ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "写入成功"); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "写入失败"); + } + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "Saving "); + WriteAAssignType2Flash(Path0, Path1, AssignTypeSetting); + Record.ReadDevUserSet(); + if(AssignTypeSetting == Port[Path0-1].AssignType[Path1-1]){ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "Save OK "); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "Save Err"); + } + } + } + break; + case pcWriteAreaInx: + if( Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + if(LanguageEnCn == 0){ + TextRender_string24(IList->EditAreaAssign.Bound.Right + 2, IList->EditAreaAssign.Bound.Top + 4, clNearWhite, ItemColor, "写入中 "); + WriteAreaNum2Flash(Path0, Path1, AreaNum); + Record.ReadDevAreaNum(); + if(AreaNum == Port[Path0-1].Area[Path1-1]){ + TextRender_string24(IList->EditAreaAssign.Bound.Right + 2, IList->EditAreaAssign.Bound.Top + 4, clNearWhite, ItemColor, "写入成功"); + }else{ + TextRender_string24(IList->EditAreaAssign.Bound.Right + 2, IList->EditAreaAssign.Bound.Top + 4, clNearWhite, ItemColor, "写入失败"); + } + }else{ + TextRender_string24(IList->EditAreaAssign.Bound.Right + 2, IList->EditAreaAssign.Bound.Top + 4, clNearWhite, ItemColor, "Saving "); + WriteAreaNum2Flash(Path0, Path1, AreaNum); + Record.ReadDevAreaNum(); + if(AreaNum == Port[Path0-1].Area[Path1-1]){ + TextRender_string24(IList->EditAreaAssign.Bound.Right + 2, IList->EditAreaAssign.Bound.Top + 4, clNearWhite, ItemColor, "Save OK "); + }else{ + TextRender_string24(IList->EditAreaAssign.Bound.Right + 2, IList->EditAreaAssign.Bound.Top + 4, clNearWhite, ItemColor, "Save Err"); + } + } + } + break; + case pcWriteSmokerSens: + SmokerRt.IsWait4ReadSens = 0; + SmokerRt.IsWait4WriteSens = 1; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + SendSmokeCmdCfg(); + if(LanguageEnCn == 0){ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "写入中 "); + }else + if(LanguageEnCn == 1){ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "Saving "); + } + break; + case pcWriteTempeSensType: + + break; + case pcWriteModuleDefineType: + + break; + case pcWriteModuleSignalInType: + //ModuleInRt.IsWait4ReadSignalType = 0; + //ModuleInRt.IsWait4WriteSignalType = 1; + //ModuleInRt.RecRdy = 0; + //ModuleInRt.RecCmd = 0; + //ModuleInRt.WaitTick = 0; + //SendModuleSignalInOutTypeWrite(); + aBits = Data.ModuleSignalInType; + WriteMouelaInputSignal(); + if(LanguageEnCn == 0){ + if(aBits == Data.ModuleSignalInType) + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "写入成功"); + else + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "写入失败"); + }else + if(LanguageEnCn == 1){ + if(aBits == Data.ModuleSignalInType) + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "Save OK "); + else + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "Save Err"); + } + break; + case pcWriteNoTypeSignalInOutType: + //ModuleInOutRt.IsWait4ReadSignalType = 0; + //ModuleInOutRt.IsWait4WriteSignalType = 1; + //ModuleInOutRt.RecRdy = 0; + //ModuleInOutRt.RecCmd = 0; + //ModuleInOutRt.WaitTick = 0; + //SendModuleSignalInOutTypeWrite(); + aBits = Data.NoTypeSignalInOutType; + WriteNoTypeInOutSignal(); + if(LanguageEnCn == 0){ + if(aBits == Data.NoTypeSignalInOutType) + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "写入成功"); + else + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "写入失败"); + }else{ + if(aBits == Data.NoTypeSignalInOutType) + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "Save OK "); + else + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "Save Err"); + } + break; + case pcWriteModuleSignalInOutType: + //ModuleInOutRt.IsWait4ReadSignalType = 0; + //ModuleInOutRt.IsWait4WriteSignalType = 1; + //ModuleInOutRt.RecRdy = 0; + //ModuleInOutRt.RecCmd = 0; + //ModuleInOutRt.WaitTick = 0; + //SendModuleSignalInOutTypeWrite(); + aBits = Data.ModuleSignalInOutType; + WriteMouelaInOutSignal(); + if(LanguageEnCn == 0){ + if(aBits == Data.ModuleSignalInOutType) + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "写入成功"); + else + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "写入失败"); + }else{ + if(aBits == Data.ModuleSignalInOutType) + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "Save OK "); + else + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "Save Err"); + } + break; + case pcWriteModuleSignalOutType: + + break; + case pcWriteVaIsLinkageAble: + //Write to Flash No This Function See WriteVaSetting + break; + case pcWriteVaSetting: + SendVaSettingWrite(); + break; + case pcWriteDisplayPadMatchData: + WriteDisplayPadMatchData(); + break; + case pcLightUp: + //No Permission Requst, See KeyIn-Function + break; + case pcSimAlram: + SimFire(Path0, Path1); + break; + case pcSimStart: + SimStart(Path0, Path1); + break; + case pcSimInputActive: + SimFeedBack(Path0, Path1); + break; + case pcDisplayPadMute: + SendDisplayPadMute(); + break; + case pcDownLoadDescp: + SendDisplayPadDescpDownload(); + break; + case pcEditDescp: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + InitPanel(); + EdittingDescp = 1; + IsExtInput = 1; + break; + } +} + +void TDevProperty::RedrawPanelData() +{ + int x,y; + if(PanelIsUsingText){ + for(int i=0; i<8; i++){ + y = Lv.Panel.Top + 1; + y = y + i * 27; + x = Lv.Panel.Left + 2; + if(EdittingDescp == 0){ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + TextRender_string24(x,y,clNearBlack, IList->TextOut[i]); + } + } + }else{ + if(EdittingDescp == 0){ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + CurveDraw(1); + } + } +} + +void TDevProperty::PermissionCmdReturnDraw() +{ + Check4Selected(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + RedrawPanelData(); +} + +void TDevProperty::ReDrawPanel() +{ + PermissionCmdReturnDraw(); +} + +void TDevProperty::ClearSelected() +{ + switch(HwDevType){ + case htNoType: ClearSelectedNoType(); break; + case htSmoker: ClearSelectedHtSmoker(); break; + case htTempe: ClearSelectedHtTempe(); break; + case htHandPad: ClearSelectedHtHandPad(); break; + case htHydrantPad: ClearSelectedHtHydrantPad(); break; + case htModuleIn: ClearSelectedHtModuleIn(); break; + case htModuleInOut: ClearSelectedHtModuleInOut(); break; + case htModuleOut: ClearSelectedHtModuleOut(); break; + case htVa: ClearSelectedHtVa(); break; + case htDisplayPad: ClearSelectedHtDisplayPad(); break; + case htLinkagePowerSuply:ClearSelectedHtLinkagePowerSuply(); break; + default :break; + } +} + +void TDevProperty::Check4Selected() +{ + switch(HwDevType){ + case htNoType: Check4SelectedNoType(); break; + case htSmoker: Check4SelectedHtSmoker(); break; + case htTempe: Check4SelectedHtTempe(); break; + case htHandPad: Check4SelectedHtHandPad(); break; + case htHydrantPad: Check4SelectedHtHydrantPad(); break; + case htModuleIn: Check4SelectedHtModuleIn(); break; + case htModuleInOut: Check4SelectedHtModuleInOut(); break; + case htModuleOut: Check4SelectedHtModuleOut(); break; + case htVa: Check4SelectedHtVa(); break; + case htDisplayPad: Check4SelectedHtDisplayPad(); break; + case htLinkagePowerSuply:Check4SelectedHtLinkagePowerSuply(); break; + default :break; + } +} + +void TDevProperty::ClearReqDataState() +{ + SmokerRt.IsWait4ReadSens = 0; + SmokerRt.IsWait4WriteSens = 0; + TempeRt.IsWait4ReadSensType =0; + ModuleInRt.IsWait4ReadSignalType =0; + ModuleInRt.IsWait4WriteSignalType =0; + ModuleInOutRt.IsWait4ReadStaticData =0; + ModuleInOutRt.IsWait4WriteStaticData =0; + ModuleOutRt.IsWait4ReadStaticData =0; + ModuleOutRt.IsWait4WriteStaticData =0; + VaRt.IsWait4ReadVaSetting =0; + VaRt.IsWait4WriteVaSetting =0; + DisplayPadRt.IsMute =0; + DisplayPadRt.IsDownloadDescp =0; +} + +void TDevProperty::sWriteAuxIdAssignTypeSignalType(unsigned char aPath0) +{ + unsigned int fAddr; + unsigned int i; + TDMix tCrc; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + + if(sIList == nullptr)return; + sIList->ReadWriteData.Reset(); + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (aPath0 >0) && (aPath0 <= dPORT_MAX_COUNT) ){ + aP0 = aPath0 -1; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + sDelayMs(100); + + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + Crc32Reset(); + for(i=0; iReadWriteData.D32[x] = Port[aP0].UcList[i*64 + x].Full; + } + if(i==3){ + sIList->ReadWriteData.D32[63] = tCrc.D32; + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (i * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } + + Crc32Reset(); + for(x=0; x(Port[aP0].AssignType[x])); + tCrc.D32 = Crc32GetResult(); + for(x=0;xReadWriteData.D8[x] = Port[aP0].AssignType[x]; + } + sIList->ReadWriteData.D8[252] = tCrc.D8[0]; + sIList->ReadWriteData.D8[253] = tCrc.D8[1]; + sIList->ReadWriteData.D8[254] = tCrc.D8[2]; + sIList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (4 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Signal Type + Crc32Reset(); + for(x=0; x(Port[aP0].FuncSetByte[x])); + tCrc.D32 = Crc32GetResult(); + for(x=0;xReadWriteData.D8[x] = Port[aP0].FuncSetByte[x]; + } + sIList->ReadWriteData.D8[252] = tCrc.D8[0]; + sIList->ReadWriteData.D8[253] = tCrc.D8[1]; + sIList->ReadWriteData.D8[254] = tCrc.D8[2]; + sIList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (5 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } +} + + +void TDevProperty::sWriteAuxIdAssignTypeSignalTypeDefault(unsigned char aPath0) +{ + unsigned int fAddr; + unsigned int i; + TDMix tCrc; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + + if(sIList == nullptr)return; + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (aPath0 >0) && (aPath0 <= dPORT_MAX_COUNT) ){ + aP0 = aPath0 -1; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + sDelayMs(100); + + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + Crc32Reset(); + for(i=0; iReadWriteData.D32[x] = Port[aP0].UcList[i*64 + x].Full; + } + if(i==3){ + sIList->ReadWriteData.D32[63] = tCrc.D32; + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (i * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + LoopCheck1S(); + } + + Crc32Reset(); + for(x=0; x(Port[aP0].AssignType[x])); + } + tCrc.D32 = Crc32GetResult(); + for(x=0;xReadWriteData.D8[x] = Port[aP0].AssignType[x]; + } + sIList->ReadWriteData.D8[252] = tCrc.D8[0]; + sIList->ReadWriteData.D8[253] = tCrc.D8[1]; + sIList->ReadWriteData.D8[254] = tCrc.D8[2]; + sIList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (4 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + LoopCheck1S(); + + //Signal Type + Crc32Reset(); + for(x=0; x(Port[aP0].FuncSetByte[x])); + } + tCrc.D32 = Crc32GetResult(); + for(x=0;xReadWriteData.D8[x] = Port[aP0].FuncSetByte[x]; + } + sIList->ReadWriteData.D8[252] = tCrc.D8[0]; + sIList->ReadWriteData.D8[253] = tCrc.D8[1]; + sIList->ReadWriteData.D8[254] = tCrc.D8[2]; + sIList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (5 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + LoopCheck1S(); + } +} + +void TDevProperty::WriteAUserCode2Flash(unsigned char aPath0, unsigned char aAddr, TUserCode aUc) +{ + unsigned int fAddr; + unsigned int i; + TDMix tCrc; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + + + //Erase 1 * 4K Blocks + if( (aPath0 >0) && (aPath0 <= dPORT_MAX_COUNT) ){ + aP0 = aPath0 -1; + aP1 = aAddr -1; + Port[aP0].UcList[aP1].Full = aUc.Full; + sIList = IList; + sWriteAuxIdAssignTypeSignalType(aPath0); + } +} + +void TDevProperty::WriteAAssignType2Flash(unsigned char aPath0, unsigned char aAddr, unsigned char aNewAssignType) +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (aPath0 >0) && (aPath0 <= dPORT_MAX_COUNT) ){ + aP0 = aPath0 -1; + aP1 = aAddr -1; + Port[aP0].AssignType[aP1] = aNewAssignType; + sIList = IList; + sWriteAuxIdAssignTypeSignalType(aPath0); + } +} + +void TDevProperty::WriteAreaNum2Flash(unsigned char aPath0, unsigned char aAddr, unsigned short aNum) +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + TDMix tCrc; + + if(aPath0 <1)return; + if(aPath0 >dPORT_MAX_COUNT)return; + + aP0 = aPath0 -1; + aP1 = aAddr -1; + Port[aP0].Area[aP1] = aNum; + + sIList = IList; + sWriteAreaNumOnePort(aPath0); +} + +void TDevProperty::sWriteAreaNumOnePort(unsigned char aPort) +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + TDMix tCrc; + + if(aPort==0)return; + if(aPort>dPORT_MAX_COUNT)return; + + if(sIList==nullptr)return; + sIList->ReadWriteData.Reset(); + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + + aP0 = aPort -1; + fAddr = dFlash4DevAreaNum + (aP0 / 8 * 4096); + nor_erase_sector_4k(dFlash4DevAreaNumChip,fAddr); + sDelayMs(100); + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + for(i=0; i<8; i++){ + Crc32Reset(); + for(int Gg=0; Gg<2; Gg++){ + for(x=0;x<128;x++){ + sIList->ReadWriteData.D16[x] = Port[ (aP0 & 0xF8) +i].Area[Gg * 128 + x]; + if(sIList->ReadWriteData.D16[x] > dAreaCountMax)sIList->ReadWriteData.D16[x] =0; + if(Gg==0 or (x<(dEP_MAX_COUNT_PER_PORT-128))){ + Crc32Feed(static_cast(sIList->ReadWriteData.D16[x])); + } + } + if(Gg==1){ + tCrc.D32 = Crc32GetResult(); + sIList->ReadWriteData.D8[252] = tCrc.D8[0]; + sIList->ReadWriteData.D8[253] = tCrc.D8[1]; + sIList->ReadWriteData.D8[254] = tCrc.D8[2]; + sIList->ReadWriteData.D8[255] = tCrc.D8[3]; + } + fAddr = dFlash4DevAreaNum + ( aP0/8 * 4096 + (i * 512) ) + (Gg * 256); + nor_write_page(dFlash4DevAreaNumChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + } + } +} + +void TDevProperty::sWriteAreaNumDefault() +{ + unsigned int fAddr; + unsigned int i,m,t; + volatile unsigned int x, GetSta; + TDMix tCrc; + + if(sIList==nullptr)return; + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + for(t=0; t<(dPORT_MAX_COUNT/8) ;t++){ + fAddr = dFlash4DevAreaNum + (t * 4096); + nor_erase_sector_4k(dFlash4DevAreaNumChip,fAddr); + sDelayMs(100); + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + for(i=0; i<8; i++){ + SysLoopTick = 0; + sIList->ReadWriteData.Reset(); + for(m=0; mReadWriteData.D16[x] = Port[ (t *8) +i].Area[Gg * 128 + x]; + if(Gg==0 or (x<(dEP_MAX_COUNT_PER_PORT-128))){ + Crc32Feed(static_cast(sIList->ReadWriteData.D16[x])); + } + } + if(Gg==1){ + tCrc.D32 = Crc32GetResult(); + sIList->ReadWriteData.D8[252] = tCrc.D8[0]; + sIList->ReadWriteData.D8[253] = tCrc.D8[1]; + sIList->ReadWriteData.D8[254] = tCrc.D8[2]; + sIList->ReadWriteData.D8[255] = tCrc.D8[3]; + } + fAddr = dFlash4DevAreaNum + ( t * 4096 + (i * 512) ) + (Gg * 256); + nor_write_page(dFlash4DevAreaNumChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + } + } + } +} + +void TDevProperty::sRecoverSetDefault() +{ + unsigned int fAddr; + unsigned int i,x; + volatile unsigned int GetSta; + + //User Code and Assign Type + //First 32 Port + + SysLoopTick = 0; + for(i=0; i>= ((7-i)*4); + aOrd = (f & 0x0000'000F); + pText[i] = CharBcdText[aOrd]; + + } + pText[8] = '\0'; +} + +unsigned int TDevProperty::RestoreUcBcdText(char * pText) +{ + int i; + unsigned int f, Val, tResult; + tResult = 0; + for(i=0; i<8; i++){ + f = 11; + if( (pText[i] >= '0') && (pText[i] <= '9') ) { + f = pText[i] - '0'; + } + if(pText[i] == '*')f = 10; + f <<= ((7-i) * 4); + tResult |= f; + } + return tResult; +} + +void TDevProperty::FireSimulation(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUcCode, unsigned short aArea) +{ + + if(CtlNum == MainCtl.fData.Split.MyNum){ + + }else{ + + } +} + + +void TDevProperty::SimFire(unsigned char aP0, unsigned char aP1) +{ + //Smoker Tempe HandReport + if(aP0 == 0)return; + if(aP1 == 0)return; + if(aP0 >dPORT_MAX_COUNT)return; + if(aP1 >dEP_MAX_COUNT_PER_PORT)return; + + Record.InnerMsgSetYear (0, DateTime.Date.Split.Year); + Record.InnerMsgSetMonth (0, DateTime.Date.Split.Month); + Record.InnerMsgSetDay (0, DateTime.Date.Split.Day); + Record.InnerMsgSetHour (0, DateTime.Time.Split.Hour); + Record.InnerMsgSetMinute (0, DateTime.Time.Split.Minute); + Record.InnerMsgSetSecond (0, DateTime.Time.Split.Second); + Record.InnerMsgSet_mType (0, CmdActiveDefaultSet[cmPublishAlram][7]); + Record.InnerMsgSet_CtlNum (0, MainCtl.fData.Split.MyNum ); //(0,aRxMsg.Data.D8[1]); + + Record.InnerMsgSet_P0 (0,aP0); + Record.InnerMsgSet_P1 (0,aP1); + Record.InnerMsgSet_P2 (0,0); + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,0); + Record.InnerMsgSet_Data1 (0,0); + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[cmPublishAlram][8]); + Record.InnerMsgSet_iByte1 (0,0); + + InnerCan.GetEpUserCodeAreaNumDevType(aP0, aP1, &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + + if(Register.IsDevRegisting != 0x00A5A5A5){ + if(CtlCenter.ieMsgFire.Count <1)Record.InnerMsgSet_Data1 (0,1); + else Record.InnerMsgSet_Data1 (0,0); + + Record.InnerMsgSet_Data0(0,TControlCenter::LinkInputTypeFireSimulate); + + if(CtlCenter.IsMsgReseting == 0){ + if(CtlCenter.iePushOneMsgFireSimulate(Record.iMsgRx,0)){ + //ProtoC2C.MasterDoPublishFire(aCtlNum, aIm.Splite.P0, aIm.Splite.P1, aIm.Splite.dType); + ProtoC2C.SlaveDoSend2MasterMachine(Record.iMsgRx, cmVIrtualAlram, TProtoC2C::mtFire); + //ExRecord.SetStateCodeFire(); + //FecBusCRT.SetStateCodeFire(); + Record.FireAdd(Record.iMsgRx); + } + } + } +} + +void TDevProperty::SimStart(unsigned char aP0, unsigned char aP1) +{ + if(aP0 == 0)return; + if(aP1 == 0)return; + if(aP0 >dPORT_MAX_COUNT)return; + if(aP1 >dEP_MAX_COUNT_PER_PORT)return; + + Record.InnerMsgSetYear (0, DateTime.Date.Split.Year); + Record.InnerMsgSetMonth (0, DateTime.Date.Split.Month); + Record.InnerMsgSetDay (0, DateTime.Date.Split.Day); + Record.InnerMsgSetHour (0, DateTime.Time.Split.Hour); + Record.InnerMsgSetMinute (0, DateTime.Time.Split.Minute); + Record.InnerMsgSetSecond (0, DateTime.Time.Split.Second); + Record.InnerMsgSet_mType (0, CmdActiveDefaultSet[cmAutoStart][7]); + Record.InnerMsgSet_CtlNum (0, MainCtl.fData.Split.MyNum ); //(0,aRxMsg.Data.D8[1]); + + Record.InnerMsgSet_P0 (0,aP0); + Record.InnerMsgSet_P1 (0,aP1); + Record.InnerMsgSet_P2 (0,0); + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,0); + Record.InnerMsgSet_Data1 (0,TControlCenter::StartTypeSimulate); + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[cmAutoStart][8]); + Record.InnerMsgSet_iByte1 (0,0); + + InnerCan.GetEpUserCodeAreaNumDevType(aP0, aP1, &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + + if(Register.IsDevRegisting != 0x00A5A5A5){ + if(CtlCenter.iePushOneMsgLinkageStartSimulate(Record.iMsgRx)){ + //ExRecord.SetStateCodeStart(); + //FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(Record.iMsgRx); + ProtoC2C.SlaveDoSend2MasterMachine(Record.iMsgRx, cmVIrtualStart, TProtoC2C::mtLink); + } + } +} + +void TDevProperty::SimSv(unsigned char aP0, unsigned char aP1) +{ + if(aP0 == 0)return; + if(aP1 == 0)return; + if(aP0 >dPORT_MAX_COUNT)return; + if(aP1 >dEP_MAX_COUNT_PER_PORT)return; + + Record.InnerMsgSetYear (0, DateTime.Date.Split.Year); + Record.InnerMsgSetMonth (0, DateTime.Date.Split.Month); + Record.InnerMsgSetDay (0, DateTime.Date.Split.Day); + Record.InnerMsgSetHour (0, DateTime.Time.Split.Hour); + Record.InnerMsgSetMinute (0, DateTime.Time.Split.Minute); + Record.InnerMsgSetSecond (0, DateTime.Time.Split.Second); + Record.InnerMsgSet_mType (0, CmdActiveDefaultSet[cmAutoStart][7]); + Record.InnerMsgSet_CtlNum (0, MainCtl.fData.Split.MyNum ); //(0,aRxMsg.Data.D8[1]); + + Record.InnerMsgSet_P0 (0,aP0); + Record.InnerMsgSet_P1 (0,aP1); + Record.InnerMsgSet_P2 (0,0); + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,0); + Record.InnerMsgSet_Data1 (0,TControlCenter::StartTypeSimulate); + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[cmAutoStart][8]); + Record.InnerMsgSet_iByte1 (0,0); + + InnerCan.GetEpUserCodeAreaNumDevType(aP0, aP1, &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + + if(Register.IsDevRegisting != 0x00A5A5A5){ + if(CtlCenter.iePushOneMsgSvSimulate(Record.iMsgRx)){ + //ExRecord.SetStateCodeStart(); + //FecBusCRT.SetStateCodeStart(); + Record.SvAdd(Record.iMsgRx); + ProtoC2C.SlaveDoSend2MasterMachine(Record.iMsgRx, cmVIrtualSuperVi, TProtoC2C::mtSv); + } + } +} + +void TDevProperty::SimFeedBack(unsigned char aP0, unsigned char aP1) +{ + unsigned char tP0,tP1; + if(aP0 == 0)return; + if(aP1 == 0)return; + if(aP0 >dPORT_MAX_COUNT)return; + if(aP1 >dEP_MAX_COUNT_PER_PORT)return; + + tP0 = aP0-1; tP1 = aP1 -1; + + if( (Port[tP0].FuncSetByte[tP1] & 0x07) == 0x02){ + SimFire(aP0,aP1); + return; + }else + if( (Port[tP0].FuncSetByte[tP1] & 0x07) == 0x04){ + SimSv(aP0,aP1); + return; + } + + Record.InnerMsgSetYear (0, DateTime.Date.Split.Year); + Record.InnerMsgSetMonth (0, DateTime.Date.Split.Month); + Record.InnerMsgSetDay (0, DateTime.Date.Split.Day); + Record.InnerMsgSetHour (0, DateTime.Time.Split.Hour); + Record.InnerMsgSetMinute (0, DateTime.Time.Split.Minute); + Record.InnerMsgSetSecond (0, DateTime.Time.Split.Second); + Record.InnerMsgSet_mType (0, CmdActiveDefaultSet[cmAck][7]); + Record.InnerMsgSet_CtlNum (0, MainCtl.fData.Split.MyNum ); //(0,aRxMsg.Data.D8[1]); + + Record.InnerMsgSet_P0 (0,aP0); + Record.InnerMsgSet_P1 (0,aP1); + Record.InnerMsgSet_P2 (0,0); + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,0); + Record.InnerMsgSet_Data1 (0,TControlCenter::StartTypeSimulate); + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[cmAck][8]); + Record.InnerMsgSet_iByte1 (0,0); + + InnerCan.GetEpUserCodeAreaNumDevType(aP0, aP1, &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + + if(Register.IsDevRegisting != 0x00A5A5A5){ + if(CtlCenter.iePushOneMsgLinkageFbSimulate(Record.iMsgRx)){ + Record.LinkageAdd(Record.iMsgRx); + ProtoC2C.SlaveDoSend2MasterMachine(Record.iMsgRx, cmVIrtualAck, TProtoC2C::mtLink); + } + } +} + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/DevProperty.h b/MyCode/Gui/DevProperty.h new file mode 100644 index 0000000..e0873a3 --- /dev/null +++ b/MyCode/Gui/DevProperty.h @@ -0,0 +1,795 @@ +#ifndef DEVPROPERTY_H_ +#define DEVPROPERTY_H_ + + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" +#include "CtlPanel1.h" + +#define dCurveGridClr clBlack + +//For Query Device Function to PopUp Show One Device Property Key:Value Edit or View +class TDevProperty{ + public: + static constexpr unsigned short hList[12] = {72,72,72,72, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,290,290,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 5, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 220, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1, + + .PanelSmall.Active = 1, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 72, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1 + 72 -1, + }; + static constexpr TRect ModuleRectLv3 = { + .Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3] + 30, + + }; + static constexpr TRect ModuleRectLv4 = { + .Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + 30, + .Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + }; + static const unsigned int LvGridHighBottom3 = 102; + static constexpr unsigned char dTypeList[256] = { + dgTYPE_SMOKE_DETECTOR, + dgTYPE_TEMPE_DETECTOR, + dgType_VAALRAM, + }; + static constexpr unsigned char dSmokeSensGrade_MarkValue[8] = { + //100, 75, 50, 25 + 0, 100, 75, 50, 25, 0, 0, 0 + }; + enum THwDevType{ + htNoType = 0, + htSmoker = 1, + htTempe =2, + htHandPad, + htHydrantPad, + htModuleIn, + htModuleInOut, + htModuleOut, + htVa, + htDisplayPad, + htLinkagePowerSuply + }; + enum TPermissionCmd{ + pcWriteDescp = 0, + pcWriteUserCode = 1, + pcWriteAssignType, + pcWriteAreaInx, + pcWriteSmokerSens, + pcWriteTempeSensType, + pcWriteModuleDefineType, + pcWriteModuleSignalInType, + pcWriteModuleSignalInOutType, + pcWriteModuleSignalOutType, + pcWriteVaIsLinkageAble, + pcWriteVaSetting, + pcWriteDisplayPadMatchData, + pcLightUp, + pcSimAlram, + pcSimStart, + pcSimInputActive, + pcDisplayPadMute, + pcDownLoadDescp, + pcStart, + pcStop, + pcEditDescp, + pcWriteNoTypeSignalInOutType, + }; + enum TDrawTextType{ + dtNone = 0, + dtHex =1, + dtDec =2 + }; + static char Text4CmpInc[16]; + private: + int EnterMethod; + int IsPermission; + TPermissionCmd PermissionCmd; + int EdittingDescp; + int IsExtInput; + unsigned char PortNumValid; + unsigned char AddrNumValid; + unsigned char PanelIsUsingText; + TStaticText Caption; + + unsigned int Index; + unsigned int BorderWidth; + + TRect Bound; + TRect Content; + TRect ValueArea; + TRect RectCaption; + + unsigned int Color; + unsigned int xKey; + unsigned int xValue; + unsigned int yLine[8]; + + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + void Reset(){ + InxMin = 0; + InxMax =2; + } + }Tag; + + union{ + unsigned char D8[256]; + unsigned short D16[128]; + unsigned int D32[64]; + }ReadWriteData; + TUserCode aUcSetting; + unsigned char AssignTypeSetting; + unsigned short AreaNum; + + unsigned char RecData[8]; + + union{ + unsigned int D32; + struct{ + unsigned char pCtl; + unsigned char P0; + unsigned char P1; + unsigned char P2; + }Body; + }aFullPath; + + char TextTmp[24]; + struct{ + int TextDrawLine; + int FigInx; + unsigned char IsHexList[8]; + unsigned char LinePiece[4]; + unsigned char DesertTextHex; + unsigned char UsingTextHex; + void Reset(){ + for(int i=0; i<8; i++)IsHexList[i]=dtNone; + LinePiece[0]=0;LinePiece[1]=0;LinePiece[2]=0;LinePiece[3]=0; + TextDrawLine = 0; + FigInx = 0; + //DesertTextHex = 0; + //UsingTextHex = 0; + } + void ResetNotFull(){ + TextDrawLine = 0; + FigInx = 0; + LinePiece[0]=0;LinePiece[1]=0;LinePiece[2]=0;LinePiece[3]=0; + } + }PanelDrawData; + + struct{ + unsigned int Color[4]; + int UsingDataTypeCnt; + int MaxDataLen; + int DataLen; + int CurrentPst; + int HasDrawOutline; + struct{ + int PstStart; + int PstEnd; + }HasDraw; + + float Scaling[4]; + + struct{ + short Width; + short Height; + short OrgX; + short OrgY; + short MaxX; + short MaxY; + }Canvas; + + short Left; + short Top; + short Right; + short Bottom; + short Width; + short Height; + + short GridX[16]; + short GridY[16]; + short GridXCount; + short GridYCount; + short GridXWidth; + short GridYHeight; + + struct{ + unsigned char DataAva[4]; + short IR; + short Blue; + short MVal; + short Dump0; + }Smoke; + struct{ + unsigned char DataAva[4]; + short Val; + short Celsius; + short Dump0; + short Dump1; + }Tempe; + unsigned short HasUpdate; + }Curve; + public: + static class TItemList *sIList; + class TItemList *IList; + int IsShow; + TCtlPanel1 *aPanel; + unsigned char CtlNum; + unsigned char Path0; + unsigned char Path1; + unsigned char dType; + unsigned char IsRegisted; + + unsigned char SmokerReadWriteSta; + unsigned char TempeReadSta; + unsigned char VaReadWriteSta; + unsigned char DisplayPadReadWriteSta; + unsigned char DisplayPadDownloadDescpSta; + + THwDevType HwDevType; + TRootDevice *RootDev; + TEpDevice *EpDev; + + TDisplayPadSetting DpSetting; + + struct{ + TUserCode UserCode; + unsigned char NoTypeSignalInOutType; + unsigned char SmokerSens; + unsigned char TempeSenType; + unsigned char ModuleDefineType; + + unsigned char ModuleSignalInType; + unsigned char ModuleSignalInOutType; + unsigned char ModuleSignalOutType; + unsigned char VaIs4Linkage; + + unsigned char VaVisionType; + unsigned char VaSoundType; + unsigned char DisplayPadMatchMode; //0:By User Code; 1:By Area Assign + unsigned char DumpChar0; + + unsigned char DisplayPadAreaUsing[4]; + unsigned char DisplayPadUserCodeUsing[4]; + unsigned short DisplayPadArea0; + unsigned short DisplayPadArea1; + unsigned short DisplayPadArea2; + unsigned short DumpShort0; + unsigned int DisplayUserCode0; + unsigned int DisplayUserCode1; + unsigned char GotTempeSensType[8]; + void Reset(){ + UserCode.Full =0; + NoTypeSignalInOutType =0; + SmokerSens = 0; + TempeSenType = 0; + ModuleDefineType =0; + ModuleSignalInType =0; + ModuleSignalInOutType =0; + ModuleSignalOutType =0; + VaIs4Linkage =0; + VaVisionType =0; + VaSoundType =0; + DisplayPadMatchMode =0; //0:By User Code; 1:By Area Assign + DisplayPadAreaUsing[0] = 0; + DisplayPadAreaUsing[1] = 0; + DisplayPadAreaUsing[2] = 0; + DisplayPadUserCodeUsing[0] = 0; + DisplayPadUserCodeUsing[1] = 0; + DisplayPadArea0 =0; + DisplayPadArea1 =0; + DisplayPadArea2 =0; + DisplayUserCode0 =0; + DisplayUserCode1 =0; + GotTempeSensType[0] =0; + GotTempeSensType[1] =0; + GotTempeSensType[2] =0; + GotTempeSensType[3] =0; + GotTempeSensType[4] =0; + } + }Data; + struct{ + unsigned char VaIs4Linkage; + unsigned char VaVisionType; + unsigned char VaSoundType; + unsigned char Dump0; + }ExData; + struct{ + unsigned short voltage; + unsigned short SmokerPrmM; + unsigned short SmokerIR; + unsigned short SmokerBL; + unsigned short TempeOriginData; + unsigned short TempeCelsiusData; + unsigned short ModuleInAdVal; + unsigned short DisplayPadAlramCount; + unsigned short BatVoltage; + unsigned short BatEnergy; + unsigned short OutputVoltage; + unsigned short OutputCurrent; + unsigned short PwrLoaddingPercent; + unsigned char MacHasUpdate; + unsigned char MacPath0; + unsigned char MacPath1; + unsigned char DumpByte; + unsigned char Mac[8]; + void Reset(){ + voltage =0; + SmokerPrmM =0; + SmokerIR =0; + SmokerBL =0; + TempeOriginData =0; + TempeCelsiusData =0; + ModuleInAdVal =0; + DisplayPadAlramCount =0; + BatVoltage =0; + BatEnergy =0; + OutputVoltage =0; + OutputCurrent =0; + PwrLoaddingPercent =0; + MacHasUpdate =0; + MacPath0=0; + MacPath1=0; + for(int i=0; i<8; i++)Mac[i] =0; + } + }RuntimeData; + unsigned char CommData[16]; + struct{ + unsigned char Method; + unsigned char P0; + unsigned char P1; + unsigned char DevType; + unsigned char DataType; + + unsigned char dVal[4]; + unsigned char dValGot[4]; + unsigned char dType; + }ProcessingRt; + struct{ + unsigned char IsWait4ReadOutputLineCheck; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + unsigned char IsToCheck; + }NoTypeRt; + struct{ + unsigned char IsWait4ReadSens; + unsigned char IsWait4WriteSens; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }SmokerRt; + struct{ + unsigned char IsWait4ReadSensType; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }TempeRt; + struct{ + unsigned char IsWait4ReadSignalType; + unsigned char IsWait4WriteSignalType; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }ModuleInRt; + struct{ + unsigned char IsWait4ReadStaticData; + unsigned char IsWait4WriteStaticData; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + unsigned char rOutputType; + unsigned char wOutputType; + unsigned char rCheck; + unsigned char wCheck; + }ModuleInOutRt; + struct{ + unsigned char IsWait4ReadStaticData; + unsigned char IsWait4WriteStaticData; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + unsigned char rOutputType; + unsigned char wOutputType; + unsigned char rCheck; + unsigned char wCheck; + }ModuleOutRt; + struct{ + unsigned char IsWait4ReadVaSetting; + unsigned char IsWait4WriteVaSetting; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }VaRt; + struct{ + unsigned char IsMute; + unsigned char IsDownloadDescp; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + char DescpText[36]; + }DisplayPadRt; + char TextDraw[40]; + char DebugBytes[16]; + struct{ + unsigned char HasOn; + unsigned char PNum; + unsigned char P0; + unsigned char P1; + }HasLightOn; + unsigned char DevLightOn; + public: + TDevProperty(){}; + void Init(THwDevType aDevType, int aMode); + static void sDelayMs(unsigned int aMs); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void SetEditMode(unsigned int aMode); + + void DrawSelf(void); + void DrawCaption(void); + void RenderProperty(unsigned int DrawType); //DrawType=1:Draw Key; DrawType=2:Draw Value; DrawType=3:Draw Key & Value + void DrawStrKey(void); + void DrawStrValue(void); + void Show(void); + void FullRedraw(int Prm); + + void DrawStateCn(unsigned char aSta); + void DrawStateEn(unsigned char aSta); + void DrawState(unsigned char aSta); + void DrawMac(); + + void DisplayPadShowDownloadDescpSta(); + void DisplayPadShowDownloadDescpSta(unsigned char aSta); + + void Redraw4NoTypeSmallPanelWithNoData(); + void Redraw4SmokerSmallPanelData(); + void Redraw4TempeSmallPanelData(); + void Redraw4HandPadSmallPanelData(); + void Redraw4HydrantPadSmallPanelData(); + void Redraw4ModuleInSmallPanelData(); + void Redraw4ModuleInOutSmallPanelData(); + void Redraw4ModuleOutSmallPanelData(); + void Redraw4VaSmallPanelData(); + void Redraw4DisplayPadSmallPanelData(); + void Redraw4LinkagePowerSuplySmallPanelData(); + + void ReDrawCommonInf(); + void ClearCommonInf(); + + void Redraw4NewLoad(); + void Redraw4NoTypeNewLoad(); + void Redraw4SmokerNewLoad(); + void Redraw4TempeNewLoad(); + void Redraw4HandPadNewLoad(); + void Redraw4HydrantPadNewLoad(); + void Redraw4ModuleInNewLoad(); + void Redraw4ModuleInOutNewLoad(); + void Redraw4ModuleOutNewLoad(); + void Redraw4VaNewLoad(); + void Redraw4DisplayPadNewLoad(); + void Redraw4LinkagePowerSuplyNewLoad(); + + void SetPath(unsigned char aCtlNum, unsigned char Path0, unsigned char Path1); + + void UpdataOnlineData(); + void DrawCommonInfTitle(); + void RedrawCommonInfTitle(); + void RenewCommonInf(); + void Redraw4DescpEdit(); + void ReLoadAndDrawDescp(); + void ReadAllEpUserCode(); + + void Init4DType(); + void InitNoType(); + void InitHtSmoker(); + void InitHtTempe(); + void InitHtHandPad(); + void InitHtHydrantPad(); + void InitHtModuleIn(); + void InitHtModuleInOut(); + void InitHtModuleOut(); + void InitHtVa(); + void InitHtDisplayPad(); + void InitHtLinkagePowerSuply(); + + void EditDescpReturnHtNoType(); + void EditDescpReturnHtSmoker(); + void EditDescpReturnHtTempe(); + void EditDescpReturnHtHandPad(); + void EditDescpReturnHtHydrantPad(); + void EditDescpReturnHtModuleIn(); + void EditDescpReturnHtModuleInOut(); + void EditDescpReturnHtModuleOut(); + void EditDescpReturnHtVa(); + void EditDescpReturnHtDisplayPad(); + void EditDescpReturnHtLinkagePowerSuply(); + + void ClearSelected(); + void ClearSelectedNoType(); + void ClearSelectedHtSmoker(); + void ClearSelectedHtTempe(); + void ClearSelectedHtHandPad(); + void ClearSelectedHtHydrantPad(); + void ClearSelectedHtModuleIn(); + void ClearSelectedHtModuleInOut(); + void ClearSelectedHtModuleOut(); + void ClearSelectedHtVa(); + void ClearSelectedHtDisplayPad(); + void ClearSelectedHtLinkagePowerSuply(); + + void Check4Selected(); + void Check4SelectedNoType(); + void Check4SelectedHtSmoker(); + void Check4SelectedHtTempe(); + void Check4SelectedHtHandPad(); + void Check4SelectedHtHydrantPad(); + void Check4SelectedHtModuleIn(); + void Check4SelectedHtModuleInOut(); + void Check4SelectedHtModuleOut(); + void Check4SelectedHtVa(); + void Check4SelectedHtDisplayPad(); + void Check4SelectedHtLinkagePowerSuply(); + + void DrawLightOnStateSmoke(int aPrm =0); + void DrawLightOnStateTempe(int aPrm =0); + void DrawLightOnStateHandPad(int aPrm =0); + void DrawLightOnStateHydrantPad(int aPrm =0); + void DrawLightOnStateModuleIn(int aPrm =0); + void DrawLightOnStateModuleInOut(int aPrm =0); + void DrawLightOnStateModuleOut(int aPrm =0); + + void DrawCommonInfTitleFixText(); + void DrawFixTextNoType(); + void DrawFixTextSmoker(); + void DrawFixTextTempe(); + void DrawFixTextHandPad(); + void DrawFixTextHydrantPad(); + void DrawFixTextModuleIn(); + void DrawFixTextModuleInOut(); + void DrawFixTextModuleOut(); + void DrawFixTextVa(); + void DrawFixTextDisplayPad(); + void DrawFixTextLinkagePowerSuply(); + + TGuiMsgReturn KeyInHtNoType(unsigned char aKey); + TGuiMsgReturn KeyInHtSmoker(unsigned char aKey); + TGuiMsgReturn KeyInHtTempe(unsigned char aKey); + TGuiMsgReturn KeyInHtHandPad(unsigned char aKey); + TGuiMsgReturn KeyInHtHydrantPad(unsigned char aKey); + TGuiMsgReturn KeyInHtModuleIn(unsigned char aKey); + TGuiMsgReturn KeyInHtModuleInOut(unsigned char aKey); + TGuiMsgReturn KeyInHtModuleOut(unsigned char aKey); + TGuiMsgReturn KeyInHtVa(unsigned char aKey); + TGuiMsgReturn KeyInHtDisplayPad(unsigned char aKey); + TGuiMsgReturn KeyInHtLinkagePowerSuply(unsigned char aKey); + + TGuiMsgReturn KeyIn(unsigned char aKey); + TGuiMsgReturn KeyInCommonEdit(unsigned char aKey); + TGuiMsgReturn KeyInCommonEnter(unsigned char aKey); + + void SetEnterMethod(int aMt); + + void InitPanel(); + + void SendSmokeCmdRead(); + void SendTempeCmdRead(); + void SendSmokeCmdCfg(); + void SendTempeCmdCfg(); + void SendModuleSignalInOutTypeRead(); + void SendModuleSignalInOutTypeWrite(); + void SendModuleSignalOutTypeRead(); + void SendModuleSignalOutTypeWrite(); + void SendVaSettingRead(); + void SendVaSettingWrite(); + void SendDisplayPadDescpDownload(); + + void SendReqMac(); + void SendCmdLightOn(); + void SendCmdLightOff(); + void SendCmdMuteBroadcast(); + void SendCmdMute(); + void SendDisplayPadMute(); + void SendLinkagePowerSuplyMute(); + + void RedrawSmokeSensValue(); + void RedrawTempeSensType(); + void RedrawModuleInDefineType(); + void RedrawModuleInSignalInType(); + void RedrawModuleInOutDefineType(); + void RedrawModuleOutDefineType(); + void RedrawModuleInOutSignalType(); + void RedrawModuleOutSignalType(); + void RedrawVaIs4Linkage(); + void RedrawVaSetting(); + void RedrawDisplayPadMatchMode(); + void RedrawDisplayPadMatchData(); + + void ResetTargetData(); + void RealTimeSendCmd(const int StartStop); + void RealTimeSendCmdAbort(); + void RunTimeSendCmd(const int StartStop); + + void PushInnerCanData(unsigned char aCmd, unsigned char *pData); + void PushSmokeCanData(unsigned char aCmd, unsigned char *pData); + void PushTempeCanData(unsigned char aCmd, unsigned char *pData); + void PushModuleInCanData(unsigned char aCmd, unsigned char *pData); + void PushModuleInOutCanData(unsigned char aCmd, unsigned char *pData); + void PushModuleOutCanData(unsigned char aCmd, unsigned char *pData); + void PushVaCanData(unsigned char aCmd, unsigned char *pData); + void PushDisplayPadCanData(unsigned char aCmd, unsigned char *pData); + void PushLinkagePowerSuplyCanData(unsigned char aCmd, unsigned char *pData); + + void PushInnerCanRuntimeData(unsigned char aCmd, unsigned char *pData); + + void PushOneRealDataReport(u8 aP0, u8 aP1, u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3); + void RuntimeDataPrc(u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3); + + + + void PermissionCmdGO(); + void PermissionCmdReturnDraw(); + void ReDrawPanel(); + void RedrawPanelData(); + + void LoadUcBcdText(unsigned int aUcFull, char * pText); + unsigned int RestoreUcBcdText(char * pText); + + void ClearReqDataState(); + void FullRedrawNoType(int Prm); + void FullRedrawhtSmoker(int Prm); + void FullRedrawhtTempe(int Prm); + void FullRedrawhtHandPad(int Prm); + void FullRedrawhtHydrantPad(int Prm); + void FullRedrawhtModuleIn(int Prm); + void FullRedrawhtModuleInOut(int Prm); + void FullRedrawhtModuleOut(int Prm); + void FullRedrawhtVa(int Prm); + void FullRedrawhtDisplayPad(int Prm); + void FullRedrawhtLinkagePowerSuply(int Prm); + + void DrawSmokerReadWriteStates(); + void DrawSmokerReadWriteStates(unsigned char aNewState); + void DrawTempeReadStates(); + void DrawTempeReadStates(unsigned char aNewState); + void DrawVaReadWriteStates(); + void DrawVaReadWriteStates(unsigned char aNewState); + void DrawDisplayPadReadWriteStates(); + void DrawDisplayPadReadWriteStates(unsigned char aNewState); + + void FireSimulation(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType=0, unsigned int aUcCode=0, unsigned short aArea=0); + + void CurveInit(short aLeft, short aTop, short aWidth, short aHeight, short aDataTypeCnt); + void CurveSetMargin(short aLeft, short aTop, short aRight, short aBottom); + void CurveSetGrid(short xCnt, short yCnt, short xWidth, short yHeight); + void CurveSetColor(u32 aClr0, u32 aClr1, u32 aClr2, u32 aClr3); + void CurveSetScaling(); + void CurvePutDataSmoke(unsigned short aD0, unsigned short aD1, unsigned short aD2, unsigned short aD3); + void CurvePutDataTempe(unsigned short aD0, unsigned short aD1, unsigned short aD2, unsigned short aD3); + void CurveDrawText(); + void CurveDrawOutline(); + void CurveDrawGrid(); + void CurveRecover(); + void CurveDrawData(); + void CurveDrawLastData(); + void CurveDraw(int IsFullRedraw); + void CurveHide(); + + void SimFire(unsigned char aP0, unsigned char aP1); + void SimStart(unsigned char aP0, unsigned char aP1); + void SimSv(unsigned char aP0, unsigned char aP1); + void SimFeedBack(unsigned char aP0, unsigned char aP1); + + void Task1000Ms(); + void Task1000MsNoType(); + void Task1000MsSmoker(); + void Task1000MsTempe(); + void Task1000MsHandPad(); + void Task1000MsHydrantPad(); + void Task1000MsModuleIn(); + void Task1000MsModuleInOut(); + void Task1000MsModuleOut(); + void Task1000MsVa(); + void Task1000MsDisplayPad(); + void Task1000MsLinkagePowerSuply(); + + void RedrawNoTypeDefineType(); + void RedrawNoTypeSignalType(); + + void WriteAUserCode2Flash(unsigned char aPath0, unsigned char aAddr, TUserCode aUc); + void WriteAAssignType2Flash(unsigned char aPath0, unsigned char aAddr, unsigned char aNewAssignType); + void WriteAreaNum2Flash(unsigned char aPath0, unsigned char aAddr, unsigned short aNum); + + static void sWriteAuxIdAssignTypeSignalType(unsigned char aPath0); + static void sWriteAuxIdAssignTypeSignalTypeDefault(unsigned char aPath0); + + static void sWriteAreaNumOnePort(unsigned char aPort); + static void sWriteAreaNumDefault(); + + static void sRecoverSetDefault(); + + void WriteNoTypeInOutSignal(); + void WriteMouelaInputSignal(); + void WriteMouelaInOutSignal(); + void WriteMouelaOutSignal(); + void WriteDisplayPadMatchData(); + + int ExtRequst(unsigned char Prm){ + RealTimeSendCmdAbort(); + IsShow = 0; + return 0; + } +}; + + + + + + +#endif + + + \ No newline at end of file diff --git a/MyCode/Gui/DevSensitiveCfg.cpp b/MyCode/Gui/DevSensitiveCfg.cpp new file mode 100644 index 0000000..3a17e00 --- /dev/null +++ b/MyCode/Gui/DevSensitiveCfg.cpp @@ -0,0 +1,834 @@ +#include "RuntimeData.h" +#include "DevProperty.h" +#include "DevSensitiveCfg.h" +#include "DevMask.h" +#include "server.h" + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" + #include "fdcan_task.h" + #include "uart_key_drv.h" +} + +static const short svGrid1X[20] = { + 13, 52, 91, 130, 169, 208, 247, 286, 325, 364, 403, 442, 481, 520, 559, 598, 637, 676, 715, 754 +}; +static const short svGrid1X2[20] = { + 48, 87, 126, 165, 204, 243, 282, 321, 360, 399, 438, 477, 516, 555, 594, 633, 672, 711, 750, 789 +}; + +void TDevSensitiveCfg::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "工程->批量查询烟感灵敏度"); //"工程->批量设置烟感灵敏度"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "本机带烟感设备数量:"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "设定回路地址段以查询"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "回路号"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 72, clNearWhite, ItemColor, "起始地址"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 106, clNearWhite, ItemColor, "结束地址"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 140, clNearWhite, ItemColor, "灵敏度"); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 8, clNearWhite, ItemColor, "查询"); //"查询或执行设定"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, "开始查询", 14, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, "保存配置", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Project->Smoke Detetor Sensitivity"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "Smoke Detetors:"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "Set The Scope Of One Loop"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "Loop"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 72, clNearWhite, ItemColor, "Begin AD"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 106, clNearWhite, ItemColor, "End Addr"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 140, clNearWhite, ItemColor, "Sensit-y"); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 8, clNearWhite, ItemColor, "Query"); //"Query Or Set"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, " Query ", 14, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, " Config ", 14, clNearBlack); + } +} + +void TDevSensitiveCfg::Init() +{ + Path0 = 1; + StartAddr = 1; + EndAddr = 250; + State = Idle; + Tag.Inx = 0; + WriteResult =0; + WritingCfByte = TDevProperty::dSmokeSensGrade_MarkValue[1]; + IList = nullptr; + KeepOnMeJustEnter = nullptr; + KeepUiOnMe = nullptr; +} + +void TDevSensitiveCfg::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDevSensitiveCfg::DrawSelf(void) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 36, 100,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(2); + IList->Edit[0].Str.Clear(); + TMyString::sFrom2Dg(Path0,Text); + IList->Edit[0].SetText(Text, 24); + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + + IList->Edit[1].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 70, 100,30,0,0,1,clNearBlack); + IList->Edit[1].SetMaxLen(3); + IList->Edit[1].Str.Clear(); + TMyString::sFrom3Dg(StartAddr,Text); + IList->Edit[1].SetText(Text, 24); + IList->Edit[1].Show(); + + IList->Edit[2].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 104, 100,30,0,0,1,clNearBlack); + IList->Edit[2].SetMaxLen(3); + IList->Edit[2].Str.Clear(); + TMyString::sFrom3Dg(EndAddr,Text); + IList->Edit[2].SetText(Text, 24); + IList->Edit[2].Show(); + + IList->Edit[3].Init(Lv.Grid.Left[1] +114, Lv.Grid.Top[1] + 138, 100,30,0,0,1,clNearBlack); + RedrawCfgByte(); + DrawFixText(); + + InitReadData(); + Check4Selected(); + +} + +void TDevSensitiveCfg::Show() +{ + IsShow = 1; + DrawSelf(); +} + +void TDevSensitiveCfg::Init4DrawRead() +{ + unsigned int x, y, x2, y2, w, h; + + Bound.SetBySize(0, 36, 800, 406); + Content.Set(Bound.Left +3, Bound.Top+3 + 30, Bound.Right-4, Bound.Bottom -4); + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clNearWhite); + + #define GS 24 + #define TS 96 + + unsigned int aLeft, aTop, aTopR; + + aLeft = Content.Left + 10; + aTop = Content.Top +4; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "回路"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Loop"); + TextDigitRender2_24(aLeft +50, aTop, clNearBlack, clNearWhite, Path0); + + aLeft = Content.Left + 100; + aTop = Content.Top +4; + aTopR = Content.Top +6; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clSilver); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "非烟感"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Others"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clRed); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "未读"); + else TextRender_string24(aLeft,aTop,clNearBlack, "UnRead"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clDeepGreen); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "灵敏"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Std "); + aLeft += TS -20; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clTeal); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "中灵敏"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Middle"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clNavy); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "高灵敏"); + else TextRender_string24(aLeft,aTop,clNearBlack, "ExHigh"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clPurple); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "超灵敏"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Ultra "); + aLeft += TS; +} + +void TDevSensitiveCfg::Draw4Read() +{ + int a, x,y,t,b; + unsigned char p = Path0-1; + unsigned int tClr; + RectFillRender(Content.Left, Content.Top + 30, Content.Right, Content.Bottom, clNearWhite); + if(p>dPORT_MAX_COUNT)return; + if(IList == nullptr)return; + for(a=0; aReadWriteData.D8[a+1]){ + if(IList->RealtimeData.Data[0][a+1] == TDevProperty::dSmokeSensGrade_MarkValue[1]){ + //Is Setting Check + tClr = clDeepGreen; + }else + if(IList->RealtimeData.Data[0][a+1] == TDevProperty::dSmokeSensGrade_MarkValue[2]){ + //Is Not Setting Check + tClr = clTeal; + }else + if(IList->RealtimeData.Data[0][a+1] == TDevProperty::dSmokeSensGrade_MarkValue[3]){ + //Is Not Setting Check + tClr = clNavy; + }else + if(IList->RealtimeData.Data[0][a+1] == TDevProperty::dSmokeSensGrade_MarkValue[4]){ + //Is Not Setting Check + tClr = clPurple; + }else{ + tClr = clBlack; + } + }else{ + //Still wait for Done This Addr + tClr = clRed; + } + RectFillRender( svGrid1X[x], t, svGrid1X2[x], b, tClr); + }else{ + RectFillRender( svGrid1X[x], t, svGrid1X2[x], b, clSilver); + } + TMyString::sFrom3Dg(a+1, Text); + lcd_draw_str_8x16( svGrid1X[x]+6, t+5, clNearWhite, Text); + } + } +} + +void TDevSensitiveCfg::FullRedraw(int Prm) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Show(); + IList->Edit[1].Show(); + IList->Edit[2].Show(); + RedrawCfgByte(); + DrawFixText(); + Check4Selected(); + if(State != RangeReading){ + DrawWriteResult(0); + } + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); +} + +void TDevSensitiveCfg::PermissionCmdReturnDraw() +{ + FullRedraw(1); +} + +void TDevSensitiveCfg::RedrawCfgByte() +{ + if(IList == nullptr)return; + if(LanguageEnCn==0){ + switch(WritingCfByte){ + case TDevProperty::dSmokeSensGrade_MarkValue[1]: + IList->Edit[3].SetText("灵敏 ", 24); + break; + case TDevProperty::dSmokeSensGrade_MarkValue[2]: + IList->Edit[3].SetText("中灵敏", 24); + break; + case TDevProperty::dSmokeSensGrade_MarkValue[3]: + IList->Edit[3].SetText("高灵敏", 24); + break; + case TDevProperty::dSmokeSensGrade_MarkValue[4]: + IList->Edit[3].SetText("超灵敏", 24); + break; + } + }else{ + switch(WritingCfByte){ + case TDevProperty::dSmokeSensGrade_MarkValue[1]: + IList->Edit[3].SetText("Normal", 24); + break; + case TDevProperty::dSmokeSensGrade_MarkValue[2]: + IList->Edit[3].SetText("Middle", 24); + break; + case TDevProperty::dSmokeSensGrade_MarkValue[3]: + IList->Edit[3].SetText("ExHigh", 24); + break; + case TDevProperty::dSmokeSensGrade_MarkValue[4]: + IList->Edit[3].SetText("Ultra ", 24); + break; + } + } + IList->Edit[3].Show(); +} + +void TDevSensitiveCfg::DrawWriteTime() +{ + unsigned int tClr; + if(IsSelfChecking != 0)return; + if(RunData.WaitTick < 300)tClr = clNearWhite; else tClr = clRed; + if(LanguageEnCn==0)TextRender_string24(TipPoint.x+220, TipPoint.y, clNearWhite, ContentColor, "用时: "); + else TextRender_string24(TipPoint.x+220, TipPoint.y, clNearWhite, ContentColor, "Time: "); + TextDigitRender3_24(TipPoint.x+220+60, TipPoint.y, tClr, ContentColor, RunData.WaitTick); +} + +void TDevSensitiveCfg::DrawWriteResult() +{ + if(LanguageEnCn==0){ + if(WriteResult == 0){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, " "); + }else + if(WriteResult == 1){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "写入成功 "); + }else + if(WriteResult == 2){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "写入失败 "); + }else + if(WriteResult == 3){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "正在写入 "); + } + }else{ + if(WriteResult == 0){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, " "); + }else + if(WriteResult == 1){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Wrote OK "); + }else + if(WriteResult == 2){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Failed To Write"); + }else + if(WriteResult == 3){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Writing "); + } + } +} + +void TDevSensitiveCfg::DrawWriteResult(unsigned char aResult) +{ + WriteResult = aResult; + DrawWriteResult(); +} + +void TDevSensitiveCfg::InitReadData() +{ + int i; + RunData.WaitTick =0; + RunData.RecReadUpData = 0; + if(IList == nullptr)return; + IList->ReadWriteData.Reset(); + IList->RealtimeData.Reset(); +} + +void TDevSensitiveCfg::InitWriteData() +{ + RunData.WaitTick =0; + RunData.RecWriteOk =0; +} + +void TDevSensitiveCfg::CheckHostCount() +{ + int x,y; + Count.Total =0; + for(x=0; xEdit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 1: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + case 2: + IList->Edit[2].Selected = 0; + IList->Edit[2].Show(); + break; + case 3: + IList->Edit[3].Selected = 0; + IList->Edit[3].Show(); + break; + case 4: + if(LanguageEnCn==0)tText="开始查询"; else tText=" Query "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 5: + if(LanguageEnCn==0)tText="保存配置"; else tText=" Config "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +void TDevSensitiveCfg::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 1: + IList->Edit[1].Selected = 1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + case 2: + IList->Edit[2].Selected = 1; + IList->Edit[2].SetPstTail(); + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + break; + case 3: + IList->Edit[3].Selected = 1; + IList->Edit[3].Show(); + break; + case 4: + if(LanguageEnCn==0)tText="开始查询"; else tText=" Query "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +40, Lv.Grid.Top[2] + 42, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 5: + if(LanguageEnCn==0)tText="保存配置"; else tText=" Config "; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +180, Lv.Grid.Top[2] + 42, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + } +} + +void TDevSensitiveCfg::PushInnerCanData(unsigned char aCmd, unsigned char *pBuf) +{ + if(aCmd == cmQueryStaticDataAddrSegment){ + //Read + if(IList == nullptr)return; + if(State == RangeReading){ + if( (pBuf[1] == Path0) && (pBuf[2] >= StartAddr) && (pBuf[2] <= EndAddr) && (pBuf[3] ==0x01) ){ + IList->ReadWriteData.D8[pBuf[2]] =1; + IList->RealtimeData.Data[0][pBuf[2]] = pBuf[4]; + RunData.RecReadUpData = 1; + } + } + }else + if(aCmd == cmSetConfigAddrSegment){ + //Write + if(State == RangeWriting){ + if( (pBuf[1] == Path0) && (pBuf[2] == StartAddr) && (pBuf[3] == EndAddr) && (pBuf[4] ==0x01) && (pBuf[5] == WritingCfByte) ){ + RunData.RecWriteOk = 1; + } + } + } +} + +void TDevSensitiveCfg::SendCmdReadOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =5; + + aIde.BitF.Cmd = cmQueryStaticDataAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = aPort; + Data[2] = aStartAddr; + Data[3] = aEndAddr; + Data[4] = 0x01; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TDevSensitiveCfg::SendCmdReadOutputIsCheckAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =5; + + aIde.BitF.Cmd = cmQueryStaticDataAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 255; + Data[2] = 0; + Data[3] = 0; + Data[4] = 0; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TDevSensitiveCfg::SendCmdWriteOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr, unsigned char aSet) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =6; + + aIde.BitF.Cmd = cmSetConfigAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = aPort; + Data[2] = aStartAddr; + Data[3] = aEndAddr; + Data[4] = 0x01; + Data[5] = aSet; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + + +TGuiMsgReturn TDevSensitiveCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char tCtlNum, aCc, Ow, Err; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + } + + if(State == RangeReading){ + switch(aKey){ + case VK_RETURN: + State = Idle; + SendCmdReadOutputIsCheckAbort(); + FullRedraw(1); + break; + } + }else + if(State == RangeWriting){ + switch(aKey){ + case VK_RETURN: + State =Idle; + IsShow = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Tag.Inx ==0){ + IList->Edit[0].KeyIn(aKey); + aCc = IList->Edit[0].Str.ToInteger(); + if( (aCc == 0) || (aCc > dPORT_MAX_COUNT) ){ + IList->Edit[0].SelectedColor = clRed; + }else{ + IList->Edit[0].SelectedColor = clBlue; + } + Path0 = aCc; + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + }else + if(Tag.Inx ==1){ + IList->Edit[1].KeyIn(aKey); + aCc = IList->Edit[1].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[1].SelectedColor = clRed; + }else{ + IList->Edit[1].SelectedColor = clBlue; + } + StartAddr = aCc; + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + }else + if(Tag.Inx ==2){ + IList->Edit[2].KeyIn(aKey); + aCc = IList->Edit[2].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[2].SelectedColor = clRed; + }else{ + IList->Edit[2].SelectedColor = clBlue; + } + EndAddr = aCc; + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + }else + if(Tag.Inx ==3){ + switch(WritingCfByte){ + case TDevProperty::dSmokeSensGrade_MarkValue[1]:WritingCfByte = TDevProperty::dSmokeSensGrade_MarkValue[2];break; + case TDevProperty::dSmokeSensGrade_MarkValue[2]:WritingCfByte = TDevProperty::dSmokeSensGrade_MarkValue[3];break; + case TDevProperty::dSmokeSensGrade_MarkValue[3]:WritingCfByte = TDevProperty::dSmokeSensGrade_MarkValue[4];break; + case TDevProperty::dSmokeSensGrade_MarkValue[4]:WritingCfByte = TDevProperty::dSmokeSensGrade_MarkValue[1];break; + default:WritingCfByte = TDevProperty::dSmokeSensGrade_MarkValue[1];break; + } + RedrawCfgByte(); + }/*else + if(Tag.Inx ==4){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx ==5){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }*/ + break; + case VK_UP: + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx <4){ + //if(Tag.Inx <5){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + if(Tag.Inx ==3){ + WritingCfByte = WritingCfByte ? 0: 1; + RedrawCfgByte(); + } + break; + case dfKEY_QUERY: + + break; + case VK_EXECUTE: + if(Tag.Inx == 4){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + PermissionCmd = 0; + PermissionCmdGO(); + } + } + }else + if(Tag.Inx == 5){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[1] +300, Lv.Grid.Top[1] + 16, 400, 140, 3); + } + } + } + } + break; + case VK_RETURN: + State =Idle; + IsShow = 0; + if(State == RangeReading)SendCmdReadOutputIsCheckAbort(); + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TDevSensitiveCfg::PermissionCmdGO() +{ + if(PermissionCmd == 0){ + //Go Action + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + InitReadData(); + State = RangeReading; + SendCmdReadOutputIsCheck(Path0, StartAddr, EndAddr); + Init4DrawRead(); + Draw4Read(); + } + } + }else + if(PermissionCmd == 1){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + DrawWriteResult(3); + State = RangeWriting; + RunData.WaitTick =0; + SendCmdWriteOutputIsCheck(Path0, StartAddr, EndAddr, WritingCfByte); + } + } + } +} + +void TDevSensitiveCfg::Task1000Ms() +{ + if(IsShow == 0)return; + if(State == RangeReading){ + if(RunData.WaitTick<60){ + RunData.WaitTick++; + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + } + if(RunData.RecReadUpData){ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + RunData.RecReadUpData = 0; + Draw4Read(); + } + } + }else + if(State == RangeWriting){ + RunData.WaitTick++; + DrawWriteTime(); + if(RunData.WaitTick <360){ + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + if(RunData.RecWriteOk){ + //Write Ok + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawWriteResult(1); + }else{ + WriteResult = 1; + } + State = Idle; + } + }else{ + //Write Fail + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawWriteResult(2); + }else{ + WriteResult = 2; + } + State = Idle; + } + } +} + +int TDevSensitiveCfg::ExtRequst(unsigned char Prm) +{ + IsShow = 0; + if(State == RangeReading)SendCmdReadOutputIsCheckAbort(); + State =Idle; + return 0; +} + diff --git a/MyCode/Gui/DevSensitiveCfg.h b/MyCode/Gui/DevSensitiveCfg.h new file mode 100644 index 0000000..73d7dd7 --- /dev/null +++ b/MyCode/Gui/DevSensitiveCfg.h @@ -0,0 +1,177 @@ +#ifndef DEVSENSITIVECFG_H_ +#define DEVSENSITIVECFG_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" + + +class TDevSensitiveCfg{ + public: + static constexpr unsigned short hList[12] = {38,184,78,28, 26,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 220, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 72, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1 + 72 -1, + }; + static constexpr TPoint TipPoint ={ + .x = 16, + .y = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + 6, + }; + typedef enum{ + Idle =0, + RangeReading =1, + RangeWriting + }TState; + public: + class TItemList *IList; + void (*KeepOnMeJustEnter)(void); + void (*KeepUiOnMe)(void); + TRect Bound; + TRect Content; + unsigned char Path0; + unsigned char StartAddr; + unsigned char EndAddr; + unsigned char WritingCfByte; + + struct{ + unsigned int Port; + unsigned int Total; + }Count; + + struct{ + unsigned int WaitTick; + unsigned char RecReadUpData; + unsigned char RecWriteOk; + unsigned char Dump0; + unsigned char Dump1; + }RunData; + TState State; + + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + void Reset(){ + Inx = 0; + InxMin = 0; + InxMax =2; + } + }Tag; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char IsShow; + unsigned char WriteResult; + + unsigned int fAddr; + + unsigned char Data[12]; + char Text[12]; + + public: + TDevSensitiveCfg(){ + IsShow = 0; + State = Idle; + }; + void Init(); + void RenderBackGround(void); + + void DrawSelf(void); + void Show(); + void FullRedraw(int Prm); + void RedrawCfgByte(); + void Init4DrawRead(); + void Draw4Read(); + void DrawFixText(); + + void DrawWriteTime(); + void DrawWriteResult(); + void DrawWriteResult(unsigned char aResult); + + void DelayMs(unsigned int aMs); + + void CheckHostCount(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void ClearSelected(void); + void Check4Selected(); + + void InitReadData(); + void InitWriteData(); + void PushInnerCanData(unsigned char aCmd, unsigned char *pBuf); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void SendCmdReadOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr); + void SendCmdReadOutputIsCheckAbort(); + void SendCmdWriteOutputIsCheck(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr, unsigned char aSet); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); +}; + + +#endif diff --git a/MyCode/Gui/DevStartStop.cpp b/MyCode/Gui/DevStartStop.cpp new file mode 100644 index 0000000..99cf702 --- /dev/null +++ b/MyCode/Gui/DevStartStop.cpp @@ -0,0 +1,3044 @@ +#include "RuntimeData.h" +#include "DevStartStop.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +static const unsigned char stCmd[8] = {221,222,223,224,225,226,227,228}; +static const unsigned char stPrm[8] = {0,1,2,3,4,5,6,7}; + +static const unsigned char stHexNum[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; +static const char CharBcdText[20]= {"0123456789*------\0"}; + +void TDevStartStop::DrawFixTextNoType() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "Operation"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextSmoker() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "灵敏度"); + TextRender_string24(Lv.Grid.Left[2] +28, Lv.Grid.Top[2] + 36, clNearWhite, ItemColor, "按设置键重新查询数据"); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "SENSIT"); + TextRender_string24(Lv.Grid.Left[2] +28, Lv.Grid.Top[2] + 36, clNearWhite, ItemColor, "Set:Read"); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "Operation"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextTempe() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "探测类型"); + TextRender_string24(Lv.Grid.Left[2] +28, Lv.Grid.Top[2] + 40, clNearWhite, ItemColor, "按设置键重新查询数据"); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "DET TYPE"); + TextRender_string24(Lv.Grid.Left[2] +28, Lv.Grid.Top[2] + 40, clNearWhite, ItemColor, "Set:Read"); + + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "Operation"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextHandPad() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "Operation"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextHydrantPad() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "Operation"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextModuleIn() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "监管"); + //TextRender_string24(Lv.Grid.Left[3] +28, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "按设置键重新查询数据"); + TextRender_string24(Lv.Grid.Left[4] +6, ModuleRectLv4.Top + 8, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "FIRE"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "SUPV"); + //TextRender_string24(Lv.Grid.Left[3] +28, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "按设置键重新查询数据"); + TextRender_string24(Lv.Grid.Left[4] +6, ModuleRectLv4.Top + 8, clNearWhite, ItemColor, "OPR"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextModuleInOut() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clSilver, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clSilver, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clSilver, ItemColor, "监管"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "点动"); + //TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "设置键重查询"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clSilver, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clSilver, ItemColor, "FIRE"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clSilver, ItemColor, "SUPV"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "Pulse"); + //TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "设置键重查询"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextModuleOut() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "监管"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "点动"); + //TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "设置键重查询"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "FIRE"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "SUPV"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "Pulse"); + //TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "设置键重查询"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextVa() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "控制"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "联动"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "警报形式"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "声光"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "声"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "光"); + IList->Edit[0].Show(); + TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "设置键重查询"); + TextRender_string24(Lv.Grid.Left[4] +10, ModuleRectLv4.Top + 6, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "CTRL"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "LINK"); + TextRender_string24(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 6, clNearWhite, ItemColor, "Alram Type"); + TextRender_string24(Lv.Grid.Left[3] +42, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "S+L"); + TextRender_string24(Lv.Grid.Left[3] +140, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "S"); + TextRender_string24(Lv.Grid.Left[3] +236, ModuleRectLv3.Top + 36, clNearWhite, ItemColor, "L"); + IList->Edit[0].Show(); + TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "Set:Read"); + TextRender_string24(Lv.Grid.Left[4] +10, ModuleRectLv4.Top + 6, clNearWhite, ItemColor, "OPR"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextDisplayPad() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "显示匹配方式"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "分区"); + TextRender_string24(Lv.Grid.Left[2] +140, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "二次码"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "显示范围"); + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 6, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "MATCH METHOD"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "Zone"); + TextRender_string24(Lv.Grid.Left[2] +140, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "AuxID"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "DP-RANGE"); + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 6, clNearWhite, ItemColor, "Operation"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::DrawFixTextLinkagePowerSuply() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "启动", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "停止", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "Operation"); + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, "Act", 14, clNearBlack); + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, "Stop", 14, clNearBlack); + } +} + +void TDevStartStop::Init(TDevProperty::THwDevType aDevType, int aMode) +{ + HwDevType = aDevType; + IsPermission = 0; + Tag.Reset(); + RuntimeData.Reset(); + PanelDrawData.TextDrawLine = 0; + + if(MainCtl.fData.Split.NetworkMode == 1){ + Tag.InxMin = 0; + }else{ + Tag.InxMin = 1; + } + Tag.Inx = 1; + + CtlNumValid = 1; + PortNumValid =1; + AddrNumValid =1; + IsSelfCtl = 1; + + CtlNum = MainCtl.fData.Split.MyNum; + Path0 = 1; + Path1 = 1; +} + +void TDevStartStop::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDevStartStop::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TDevStartStop::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + RedrawCommonByExReturn(); + DrawHtInf(0); + RedrawSmallPanelData(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + RedrawCommonByExReturn(); + DrawHtInf(1); + RedrawSmallPanelData(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDevStartStop::RedrawCommonByExReturn() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "回路号"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, "类型:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "状态:"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "地址号"); + TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, "注释信息:"); + //User Code & Area Assign + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "二次码"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "分区号"); + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("本集中机",24); + else if(MainCtl.fData.Split.NetworkMode == 2){ + IList->STextCtlType.SetText("本区域机",24); + IList->EditCtlNum.Enable = 0; + }else{ + IList->STextCtlType.SetText("本单机",24); + IList->EditCtlNum.Enable = 0; + } + }else{ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "LoopID"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, "TYPE:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "State"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "Addre"); + TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, "Note:"); + //User Code & Area Assign + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "AuxID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("MAINHOST",24); + else if(MainCtl.fData.Split.NetworkMode == 2){ + IList->STextCtlType.SetText("REGIONAL",24); + IList->EditCtlNum.Enable = 0; + }else{ + IList->STextCtlType.SetText("ALONE",24); + IList->EditCtlNum.Enable = 0; + } + } + IList->EditCtlNum.Show(); + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->STextCtlType.Show(); + + IList->STextDType.Show(); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); +} + +void TDevStartStop::DrawHtInf(int aPrm) +{ + PanelIsUsingText = 1; + if(dType == dgTYPE_SMOKE_DETECTOR){ + if(aPrm == 0){ + for(int i=2; iEdit[0].Show(); + }else{ + DrawFixTextSmoker(); + IList->Edit[0].Show(); + } + }else + if(dType == dgTYPE_TEMPE_DETECTOR){ + if(aPrm == 0){ + for(int i=2; iEdit[0].Show(); + }else{ + DrawFixTextTempe(); + IList->Edit[0].Show(); + } + }else + if(dType == dgTYPE_HAND_REPORT){ + if(aPrm ==0){ + for(int i=2; iEdit[0].Show(); + }else{ + DrawFixTextHandPad(); + IList->Edit[0].Show(); + } + }else + if(dType == dgTYPE_FIRE_HydrantKp){ + if(aPrm == 0){ + for(int i=2; iEdit[0].Show(); + }else{ + DrawFixTextHydrantPad(); + IList->Edit[0].Show(); + } + }else + if(dType == dgTYPE_IN_MODULE){ + if(aPrm ==0){ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + DrawFixTextModuleIn(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + if(IsSelfCtl)IList->STextModuleInDefineType.Show(); + IList->Edit[0].Show(); + if(Path0 && (Path0 <= dPORT_MAX_COUNT))Data.ModuleSignalInType = Port[Path0-1].FuncSetByte[Path1-1]; else Data.ModuleSignalInType = 0; + RedrawModuleInSignalInType(); + }else{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + } + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + if(IsSelfCtl)IList->STextModuleInDefineType.Show(); + IList->Edit[0].Show(); + } + }else + if(dType == dgTYPE_OUT_MODULE){ + if(aPrm == 0){ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + DrawFixTextModuleOut(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + if(IsSelfCtl)IList->STextModuleInDefineType.Show(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + if(Path0 && (Path0 <= dPORT_MAX_COUNT))Data.ModuleSignalOutType = Port[Path0-1].FuncSetByte[Path1-1]; else Data.ModuleSignalOutType = 0; + RedrawModuleOutSignalType(); + }else{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + } + //TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "设置键重查询"); + if(IsSelfCtl)IList->STextModuleInDefineType.Show(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + } + }else + if(dType == dgTYPE_INOUT_MODULE_NonSource){ + if(aPrm == 0){ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + DrawFixTextModuleInOut(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + if(IsSelfCtl)IList->STextModuleInDefineType.Show(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + if(Path0 && (Path0 <= dPORT_MAX_COUNT))Data.ModuleSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; else Data.ModuleSignalInOutType = 0; + RedrawModuleInOutSignalType(); + }else{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "DEF TYPE"); + } + //TextRender_string24(Lv.Grid.Left[3] +136, ModuleRectLv3.Top + 72, clNearWhite, ItemColor, "设置键重查询"); + if(IsSelfCtl)IList->STextModuleInDefineType.Show(); + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + } + }else + if(dType == dgType_VAALRAM){ + if(aPrm == 0){ + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + DrawFixTextVa(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + RedrawVaIs4Linkage(); + RedrawVaSetting(); + }else{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "控制"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "联动"); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "CTRL"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "LINK"); + } + IList->Edit[0].Show(); + } + }else + if(dType == dgTYPE_DISPLAY_PAD){ + if(aPrm == 0){ + for(int i=2; i<5; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + DrawFixTextDisplayPad(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + RedrawDisplayPadMatchData(); + }else{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "显示匹配方式"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "分区"); + TextRender_string24(Lv.Grid.Left[2] +140, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "二次码"); + }else{ + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "MATCH METHOD"); + TextRender_string24(Lv.Grid.Left[2] +42, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "Zone"); + TextRender_string24(Lv.Grid.Left[2] +140, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "AuxID"); + } + } + RedrawDisplayPadMatchMode(); + }else + if(dType == dgTYPE_LINKAGE_POWERSUPLY){ + if(aPrm == 0){ + for(int i=2; iSTextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clRed, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("报警", 24); + else IList->STextState.SetText("Fire", 24); + }else + if(aSta & dEpStateBitStart){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("启动", 24); + else IList->STextState.SetText("Act", 24); + }else + if(aSta & dEpStateBitSv){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("监管", 24); + else IList->STextState.SetText("SUPV", 24); + }else + if(aSta & dEpStateBitFault){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("故障", 24); + else IList->STextState.SetText("Fail", 24); + }else + if(aSta & dEpStateBitFeedBack){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("反馈", 24); + else IList->STextState.SetText("FBCK", 24); + }else + if(aSta & dEpStateBitMask){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("屏蔽", 24); + else IList->STextState.SetText("Mask", 24); + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clDeepGreen, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("正常", 24); + else IList->STextState.SetText("IDLE", 24); + } + IList->STextState.Show(); +} + +void TDevStartStop::DrawStateNone() +{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clDeepGreen, 0xF); + IList->STextState.SetText("----", 24); + IList->STextState.Show(); +} + +void TDevStartStop::DrawMac() +{ + unsigned char Num, Num10; + TMyString::sClear(TextDraw); + TMyString::sAddOnStr("MAC:", TextDraw); + for(int i=0; i<6; i++){ + Num = RuntimeData.Mac[i] % 16; + Num10 = RuntimeData.Mac[i] / 16 % 16; + TMyString::sAddOnChar(stHexNum[Num10], TextDraw); + TMyString::sAddOnChar(stHexNum[Num], TextDraw); + if( (i&0x01) && (i<5) )TMyString::sAddOnChar(' ', TextDraw); + } + TextRender_string24(Lv.PanelSmall.Left + 256, Lv.PanelSmall.Top + 36, clNearWhite, SmallPanelColor, TextDraw); +} + +void TDevStartStop::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickCtlNum = aCtlNum; + if(aPath0 && (aPath0 <= dPORT_MAX_COUNT)) PortNumValid = 1; else PortNumValid = 0; + if(aPath1 && (aPath1 <= dEP_MAX_COUNT_PER_PORT)) AddrNumValid = 1; else AddrNumValid = 0; + this->Path0 = aPath0; + this->Path1 = aPath1; + + tP0 = aPath0-1; + tP1 = aPath1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + dType = Port[tP0].dTypeTable[tP1]; + }else{ + dType = 0; + } +} + +void TDevStartStop::Show(void) +{ + RenderBackGround(); + DrawSelf(); + DrawCommonInfTitle(); + IsShow = 1; +} + +void TDevStartStop::DrawSelf() +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->部件控制"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Device Control"); + } + if(RunState == TRunModeCfg::RunModeAdjust){ + if(LanguageEnCn==0) + TextRender_string24(Lv.Caption.Left + 10 + (14*12 + 20), Lv.Caption.Top +4, clRed, CaptionColor, "(注意:真实启动或停止)"); + else + TextRender_string24(Lv.Caption.Left + 10 + (14*12 + 20), Lv.Caption.Top +4, clRed, CaptionColor, "(Notice:Real Action)"); + } + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); +} + +void TDevStartStop::DrawCommonInfTitle() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "回路号"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + + + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, "类型:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "状态:"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "地址号"); + TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, "注释信息:"); + }else{ + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "LoopID"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + + + TextRender_string24(Lv.Grid.Left[0] + 400, Lv.Grid.Top[0] +6, clNearWhite, "Type:"); + TextRender_string24(Lv.Grid.Left[0] + 640, Lv.Grid.Top[0] +6, clNearWhite, "State"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "Addr"); + TextRender_string24(Lv.Grid.Left[0] + 280, Lv.Grid.Top[0] + 40, clNearWhite, " Note:"); + } + + IList->STextCtlType.Init(Lv.Grid.Left[0] + 272, Lv.Grid.Top[0] + 2, 106, 30, 0, 0, clNearWhite, ItemColor); + IList->STextDType.Init(Lv.Grid.Left[0] + 460, Lv.Grid.Top[0] + 2, 168, 30, 0, 0, clNearWhite, ItemColor); + IList->STextState.Init(Lv.Grid.Left[0] + 730, Lv.Grid.Top[0] + 2, 68, 30, 0, 0, clNearWhite, ItemColor); + IList->STextRegisted.Init(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] + 36, 120, 30, 0, 0, clNearWhite, ItemColor); + IList->STextCtlNum.Init(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 6, 120, 30, 0, 0, clNearWhite, ItemColor); + + + IList->EditCtlNum.Init(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] + 2, 36, 30, 0, 0, 1, clNearWhite); + IList->EditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 2, 50, 30, 0, 0, 1, clNearWhite); + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + IList->EditDescpShow.Init(Lv.Grid.Left[0] + 390, Lv.Grid.Top[0] + 36, 400, 30, 0, 0, 1, clNearWhite); + + IList->STextCtlType.Enable = 1; + IList->STextCtlType.Visible = 1; + IList->STextDType.Enable = 1; + IList->STextDType.Visible =1; + IList->STextState.Enable = 1; + IList->STextState.Visible =1; + IList->STextRegisted.Enable = 1; + IList->STextRegisted.Visible =1; + IList->STextCtlNum.Enable = 1; + IList->STextCtlNum.Visible =1; + + IList->EditCtlNum.SetMaxLen(2); + IList->EditPortNum.SetMaxLen(2); + IList->EditAddrNum.SetMaxLen(3); + IList->EditCtlNum.Enable = 1; + IList->EditCtlNum.Visible = 1; + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible = 1; + IList->EditAddrNum.Enable = 1; + IList->EditAddrNum.Visible = 1; + IList->EditDescpShow.Enable = 0; + IList->EditDescpShow.Visible = 1; + + //User Code & Area Assign + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "二次码"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "分区号"); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "AuxID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + } + IList->EditUserCode.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 6, 108, 30, 0, 0, 1, clNearWhite); + IList->EditAreaAssign.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 40, 108, 30, 0, 0, 1, clNearWhite); + + IList->EditUserCode.Enable = 1; + IList->EditUserCode.Visible =1; + IList->EditUserCode.SetMaxLen(8); + IList->EditAreaAssign.Enable = 0; + IList->EditAreaAssign.Visible =1; + IList->EditAreaAssign.SetMaxLen(5); + if(LanguageEnCn==0){ + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("本集中机",24); + else if(MainCtl.fData.Split.NetworkMode == 2){ + IList->STextCtlType.SetText("本区域机",24); + IList->EditCtlNum.Enable = 0; + }else{ + IList->STextCtlType.SetText("本单机",24); + IList->EditCtlNum.Enable = 0; + } + }else{ + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("MAINHOST",24); + else if(MainCtl.fData.Split.NetworkMode == 2){ + IList->STextCtlType.SetText("REGIONAL",24); + IList->EditCtlNum.Enable = 0; + }else{ + IList->STextCtlType.SetText("ALONE",24); + IList->EditCtlNum.Enable = 0; + } + } + IList->STextCtlType.Show(); +} + +void TDevStartStop::ReDrawCommonInf() +{ + unsigned char tP0, tP1, Found, tType, tSta; + unsigned int tAddr; + //Draw Port Num + + Found = 0; + if(CtlNum == MainCtl.fData.Split.MyNum){ + //Draw If Registed + if(LanguageEnCn==0){ + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("本集中机",24); + else if(MainCtl.fData.Split.NetworkMode == 2) + IList->STextCtlType.SetText("本区域机",24); + else + IList->STextCtlType.SetText("本单机",24); + }else{ + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("MAINHOST",24); + else if(MainCtl.fData.Split.NetworkMode == 2){ + IList->STextCtlType.SetText("REGIONAL",24); + }else{ + IList->STextCtlType.SetText("ALONE",24); + } + } + IList->STextCtlType.Show(); + if( (Path0) && (Path0 <= dPORT_MAX_COUNT) ){ + if( (Path1) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + Found = 1; + //if(Port[tP0].AssignType[tP1] != 0){ + // tType = Port[tP0].AssignType[tP1]; + //}else{ + tType = Port[tP0].dTypeTable[tP1]; + //} + tSta = Port[tP0].StateTable[tP1]; + } + } + } + if(Found){ + if(LanguageEnCn==0)IList->STextDType.SetText(StrTypeShortName[tType],24); + else IList->STextDType.SetText(StrTypeShortNameEn[tType],24); + DrawState(tSta); + if(LanguageEnCn==0)IList->STextRegisted.SetText("已注册", 24); + else IList->STextRegisted.SetText("Registered ", 24); + IsRegisted = 1; + }else{ + IList->STextDType.SetText("----", 24); + DrawStateNone(); + if(LanguageEnCn==0)IList->STextRegisted.SetText("未注册", 24); + else IList->STextRegisted.SetText("Un Reg ", 24); + IsRegisted = 0; + } + tAddr = dAddrSdRam_Descp + (tP0 * 256 * 32) + (tP1 * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + + IList->EditUserCode.Str.FromUInt8Dg(Port[tP0].UcList[tP1].Full); + IList->EditAreaAssign.Str.FromUInt4Dg(Port[tP0].Area[tP1]); + + IList->STextDType.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + + Check4Selected(); + + }else{ + IList->STextDType.SetText("----", 24); + DrawStateNone(); + if( (CtlNum) && (CtlNum <= dNETWORK_MACHINE_COUNT) && (Path0) && (Path0 <= dPORT_MAX_COUNT) && (Path1) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + unsigned char aCn = CtlNum -1; + unsigned char aP0 = Path0-1; + unsigned char aP1 = Path1; + unsigned int aAddr; + if(aP0 < dPORT_MAX_COUNT){ + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(int i=0; i<32; i++){ + IList->EditDescpShow.Str.Text[i] = *(volatile unsigned char *)(aAddr + i); + } + IList->EditDescpShow.Str.Text[32] = '\0'; + } + } + IList->STextDType.Show(); + IList->STextState.Show(); + IList->EditDescpShow.Show(); + Check4Selected(); + } +} + + +void TDevStartStop::RenewCommonInf() +{ + unsigned char tP0, tP1, Found, tType, tSta; + unsigned int tAddr; + //Draw Ctl Num + IList->EditCtlNum.Str.FromUInt2Dg(CtlNum); + IList->EditCtlNum.SetPstTail(); + IList->EditCtlNum.Show(); + if(IList->EditCtlNum.Selected)IList->EditCtlNum.ShowCursor(); + + //Draw Port Num + IList->EditPortNum.Str.FromUInt2Dg(Path0); + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + if(IList->EditPortNum.Selected)IList->EditPortNum.ShowCursor(); + + //Draw Addr Num + IList->EditAddrNum.Str.FromUInt3Dg(Path1); + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + if(IList->EditAddrNum.Selected)IList->EditAddrNum.ShowCursor(); + + Found = 0; + if(CtlNum == MainCtl.fData.Split.MyNum){ + //Draw If Registed + if( (Path0) && (Path0 <= dPORT_MAX_COUNT) ){ + if( (Path1) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + Found = 1; + //if(Port[tP0].AssignType[tP1] != 0){ + // tType = Port[tP0].AssignType[tP1]; + //}else{ + tType = Port[tP0].dTypeTable[tP1]; + dType = tType; + //} + tSta = Port[tP0].StateTable[tP1]; + } + } + } + if(Found){ + if(LanguageEnCn==0)IList->STextDType.SetText(StrTypeShortName[tType],24); + else IList->STextDType.SetText(StrTypeShortNameEn[tType],24); + DrawState(tSta); + if(LanguageEnCn==0)IList->STextRegisted.SetText("已注册", 24); + else IList->STextRegisted.SetText("Registered", 24); + IsRegisted = 1; + }else{ + IList->STextDType.SetText("----", 24); + IList->STextState.SetText("----", 24); + if(LanguageEnCn==0)IList->STextRegisted.SetText("未注册", 24); + else IList->STextRegisted.SetText("Un Reg ", 24); + IsRegisted = 0; + } + tAddr = dAddrSdRam_Descp + (tP0 * 256 * 32) + (tP1 * 32); + for(int g=0; g<32; g++){ + IList->EditDescpShow.Str.Text[g] = *(volatile unsigned char *)(tAddr + g); + if( (IList->EditDescpShow.Str.Text[g] == '\0') || (IList->EditDescpShow.Str.Text[g] == 0) ){ + break; + } + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + + IList->EditUserCode.Str.FromUInt8Dg(Port[tP0].UcList[tP1].Full); + IList->EditAreaAssign.Str.FromUInt4Dg(Port[tP0].Area[tP1]); + + IList->STextDType.Show(); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + + Check4Selected(); + } +} + + +void TDevStartStop::RedrawModuleInSignalInType() +{ + if(Data.ModuleSignalInType == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.ModuleSignalInType == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.ModuleSignalInType == 4){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevStartStop::RedrawModuleInOutSignalType() +{ + if((Data.ModuleSignalInOutType & 0x07) == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if((Data.ModuleSignalInOutType & 0x07) == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if((Data.ModuleSignalInOutType & 0x07) == 4){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + + if(Data.ModuleSignalInOutType & 0x08){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevStartStop::RedrawModuleOutSignalType() +{ + if(0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, clSilver , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, clSilver , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, clSilver , 0); + } + + if(Data.ModuleSignalOutType & 0x08){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 72, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevStartStop::RedrawVaIs4Linkage() +{ + if(Data.VaIs4Linkage){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDevStartStop::RedrawVaSetting() +{ + if(Data.VaVisionType == 0){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.VaVisionType == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(Data.VaVisionType == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 12, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 110, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 206, ModuleRectLv3.Top + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + + char *tText; + if(Data.VaSoundType == 0){ + if(LanguageEnCn==0)tText="未知 "; else tText="Unknown"; + }else + if(Data.VaSoundType == 1){ + if(LanguageEnCn==0)tText="119 "; else tText="Std"; + }else + if(Data.VaSoundType == 2){ + if(LanguageEnCn==0)tText="滴滴 "; else tText="Beep "; + }else + if(Data.VaSoundType == 3){ + if(LanguageEnCn==0)tText="警报声"; else tText="ALERTS"; + } + + if(LanguageEnCn==0)tText="音调 0"; else tText="Tone 0"; + IList->Edit[0].SetText(tText ,24); + IList->Edit[0].Show(); +} + +void TDevStartStop::RedrawDisplayPadMatchMode() +{ + if(Data.DisplayPadMatchMode){ + //1 By Area Num + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 110, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + //0 By User Code + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 12, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[2] + 110, Lv.Grid.Top[2] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + } +} + +void TDevStartStop::LoadUcBcdText(unsigned int aUcFull, char *pText) +{ + int i; + unsigned int f, aOrd; + f = aUcFull; + for(i=0; i<8; i++){ + f = aUcFull; + f >>= ((7-i)*4); + aOrd = (f & 0x0000'000F); + pText[i] = CharBcdText[aOrd]; + + } + pText[8] = '\0'; +} + +void TDevStartStop::RedrawDisplayPadMatchData() +{ + for(int i=3; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "显示范围"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clNearWhite, "保存", 4, clNearBlack); + }else{ + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "DP-RANGE"); + TRoundRect::sDrawBySize(Lv.Grid.Left[3] +226, Lv.Grid.Top[3] + 4, 54, 30, 7, clNearWhite, "Save", 4, clNearBlack); + } + if(Data.DisplayPadMatchMode){ + //1 By Area Num + if(Data.DisplayPadAreaUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + if(Data.DisplayPadAreaUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 104, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + if(Data.DisplayPadAreaUsing[2]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 200, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + IList->Edit[0].Init(Lv.Grid.Left[3] + 34, Lv.Grid.Top[3] + 38, 60, 32, 0,0,1,ItemColor); + IList->Edit[1].Init(Lv.Grid.Left[3] + 132, Lv.Grid.Top[3] + 38, 60, 32, 0,0,1,ItemColor); + IList->Edit[2].Init(Lv.Grid.Left[3] + 228, Lv.Grid.Top[3] + 38, 60, 32, 0,0,1,ItemColor); + IList->Edit[0].Str.Clear(); + IList->Edit[1].Str.Clear(); + IList->Edit[2].Str.Clear(); + IList->Edit[0].SetMaxLen(4); + IList->Edit[1].SetMaxLen(4); + IList->Edit[2].SetMaxLen(4); + + IList->Edit[0].Str.FromUInt4Dg(Data.DisplayPadArea0); + IList->Edit[1].Str.FromUInt4Dg(Data.DisplayPadArea1); + IList->Edit[2].Str.FromUInt4Dg(Data.DisplayPadArea2); + + IList->Edit[0].Show(); + IList->Edit[1].Show(); + IList->Edit[2].Show(); + }else{ + //0 By User Code + if(Data.DisplayPadUserCodeUsing[0]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + if(Data.DisplayPadUserCodeUsing[1]) + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + else + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 154, Lv.Grid.Top[3] + 42, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + IList->Edit[0].Init(Lv.Grid.Left[3] + 42, Lv.Grid.Top[3] + 38, 104, 32, 0,0,1,ItemColor); + IList->Edit[1].Init(Lv.Grid.Left[3] + 184, Lv.Grid.Top[3] + 38, 104, 32, 0,0,1,ItemColor); + + IList->Edit[0].Str.Clear(); + IList->Edit[1].Str.Clear(); + IList->Edit[0].SetMaxLen(8); + IList->Edit[1].SetMaxLen(8); + + LoadUcBcdText(Data.DisplayUserCode0, IList->Edit[0].Str.Text); + LoadUcBcdText(Data.DisplayUserCode1, IList->Edit[1].Str.Text); + + IList->Edit[0].Show(); + IList->Edit[1].Show(); + } +} + +void TDevStartStop::Redraw4NewLoad() +{ + char *tText; + Data.Reset(); + switch(HwDevType){ + case TDevProperty::htNoType: + //for(int i=2; iEdit[0].Str.Clear(); + IList->Edit[0].Show(); + if(IsSelfCtl){ + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + SendSmokeCmdRead(); + if(LanguageEnCn==0)tText="获取中 ";else tText="Reading "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "--------"); + } + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htTempe: + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + if(IsSelfCtl){ + TempeRt.IsWait4ReadSensType = 1; + TempeRt.RecRdy = 0; + TempeRt.RecCmd = 0; + TempeRt.WaitTick = 0; + SendTempeCmdRead(); + if(LanguageEnCn==0)tText="获取中 ";else tText="Reading "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "--------"); + } + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htHandPad: + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htHydrantPad: + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htModuleIn: + if(IsSelfCtl){ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE ", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + }else{ + IList->Edit[0].Str.FromStr("----"); + IList->STextModuleInDefineType.SetText("--------" , 24); + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + if(IsSelfCtl){ + //ModuleInRt.IsWait4ReadSignalType = 1; + //ModuleInRt.IsWait4WriteSignalType = 0; + //ModuleInRt.RecRdy = 0; + //ModuleInRt.RecCmd = 0; + //ModuleInRt.WaitTick = 0; + //SendModuleSignalInOutTypeRead(); + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalInType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleInSignalInType(); + }else{ + TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htModuleInOut: + if(IsSelfCtl){ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE ", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + }else{ + IList->Edit[0].Str.FromStr("----"); + IList->STextModuleInDefineType.SetText("--------" , 24); + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + if(IsSelfCtl){ + //ModuleInOutRt.IsWait4ReadSignalType = 1; + //ModuleInOutRt.IsWait4WriteSignalType = 0; + //ModuleInOutRt.RecRdy = 0; + //ModuleInOutRt.RecCmd = 0; + //ModuleInOutRt.WaitTick = 0; + //SendModuleSignalInOutTypeRead(); + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleInOutSignalType(); + }else{ + TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htModuleOut: + if(IsSelfCtl){ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("NONE TYPE ", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + }else{ + IList->Edit[0].Str.FromStr("----"); + IList->STextModuleInDefineType.SetText("--------" , 24); + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + if(IsSelfCtl){ + //ModuleOutRt.IsWait4ReadSignalType = 1; + //ModuleOutRt.IsWait4WriteSignalType = 0; + //ModuleOutRt.RecRdy = 0; + //ModuleOutRt.RecCmd = 0; + //ModuleOutRt.WaitTick = 0; + //SendModuleSignalInOutTypeRead(); + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalOutType = Port[Path0-1].FuncSetByte[Path1-1]; + RedrawModuleOutSignalType(); + }else{ + TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htVa: + IList->Edit[0].Show(); + if(IsSelfCtl){ + VaRt.IsWait4ReadVaSetting = 1; + VaRt.IsWait4WriteVaSetting = 0; + VaRt.RecRdy = 0; + VaRt.RecCmd = 0; + VaRt.WaitTick = 0; + SendVaSettingRead(); + DrawVaReadWriteStates(5); + }else{ + TextRender_string24(Lv.Grid.Left[3] +190, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htDisplayPad: + RedrawDisplayPadMatchMode(); + RedrawDisplayPadMatchData(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + case TDevProperty::htLinkagePowerSuply: + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + break; + default : + for(int i=2; iEditCtlNum.Selected = 0; + IList->EditCtlNum.Show(); + break; + case 1: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 4: + if(LanguageEnCn==0)tText="启动"; else tText="Act "; + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 5: + if(LanguageEnCn==0)tText="停止"; else tText="Stop"; + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +void TDevStartStop::Check4Selected() +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditCtlNum.Selected = 1; + IList->EditCtlNum.SetPstTail(); + IList->EditCtlNum.Show(); + IList->EditCtlNum.ShowCursor(); + break; + case 1: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 4: + if(LanguageEnCn==0)tText="启动"; else tText="Act "; + TRoundRect::sDrawBySize(PtStart.x, PtStart.y, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + case 5: + if(LanguageEnCn==0)tText="停止"; else tText="Stop"; + TRoundRect::sDrawBySize(PtStop.x, PtStop.y, 76, 30, 7, clDeepBlue, tText, 14, clNearWhite); + break; + } +} + +void TDevStartStop::PermissionCmdReturnDraw() +{ + int x,y; + Check4Selected(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(PanelIsUsingText){ + for(int i=0; i<8; i++){ + y = Lv.Panel.Top + 1; + y = y + i * 27; + x = Lv.Panel.Left + 2; + if(EdittingDescp == 0){ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + TextRender_string24(x,y,clNearBlack, IList->TextOut[i]); + } + } + } +} + +void TDevStartStop::ReDrawPanel() +{ + PermissionCmdReturnDraw(); +} +//_____________________________________________________________________________________________________________________________ + + +void TDevStartStop::ResetTargetData() +{ + RuntimeData.Reset(); + IList->RealtimeData.Reset(); + IList->TextOutClear(); + PanelDrawData.ResetNotFull(); + switch(HwDevType){ + case TDevProperty::htNoType: + + break; + case TDevProperty::htSmoker: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + SendSmokeCmdRead(); + } + break; + case TDevProperty::htTempe: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + SendTempeCmdRead(); + } + break; + case TDevProperty::htHandPad: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + } + break; + case TDevProperty::htHydrantPad: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + } + break; + case TDevProperty::htModuleIn: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + SendModuleSignalInOutTypeRead(); + } + break; + case TDevProperty::htModuleInOut: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + SendModuleSignalInOutTypeRead(); + } + break; + case TDevProperty::htModuleOut: + + break; + case TDevProperty::htVa: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + SendVaSettingRead(); + } + break; + case TDevProperty::htDisplayPad: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + } + break; + case TDevProperty::htLinkagePowerSuply: + if(MainCtl.fData.Split.MyNum == CtlNum){ + RealTimeSendCmd(1); + } + break; + default : + + break; + } +} + + +void TDevStartStop::Init4DType() +{ + Data.Reset(); + RectFillRender(Lv.Grid.Left[0], Lv.Grid.Top[3], Lv.Grid.Right[3], Lv.Grid.Bottom[4], ContentColor); + if(dType == dgTYPE_SMOKE_DETECTOR){ + PtStart.x = Lv.Grid.Left[3] + 56; + PtStart.y = Lv.Grid.Top[3] + 38; + PtStop.x = Lv.Grid.Left[3] + 180; + PtStop.y = Lv.Grid.Top[3] + 38; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htSmoker; + InitHtSmoker(); + ResetTargetData(); + RealTimeSendCmd(1); + + }else + if(dType == dgTYPE_TEMPE_DETECTOR){ + PtStart.x = Lv.Grid.Left[3] + 56; + PtStart.y = Lv.Grid.Top[3] + 38; + PtStop.x = Lv.Grid.Left[3] + 180; + PtStop.y = Lv.Grid.Top[3] + 38; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htTempe; + InitHtTempe(); + ResetTargetData(); + }else + if(dType == dgTYPE_HAND_REPORT){ + PtStart.x = Lv.Grid.Left[2] + 56; + PtStart.y = Lv.Grid.Top[2] + 38; + PtStop.x = Lv.Grid.Left[2] + 180; + PtStop.y = Lv.Grid.Top[2] + 38; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htHandPad; + InitHtHandPad(); + ResetTargetData(); + }else + if(dType == dgTYPE_FIRE_HydrantKp){ + PtStart.x = Lv.Grid.Left[2] + 56; + PtStart.y = Lv.Grid.Top[2] + 38; + PtStop.x = Lv.Grid.Left[2] + 180; + PtStop.y = Lv.Grid.Top[2] + 38; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htHydrantPad; + InitHtHydrantPad(); + ResetTargetData(); + }else + if(dType == dgTYPE_IN_MODULE){ + PtStart.x = ModuleRectLv4.Left + 56; + PtStart.y = ModuleRectLv4.Top + 6; + PtStop.x = ModuleRectLv4.Left + 180; + PtStop.y = ModuleRectLv4.Top + 6; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htModuleIn; + InitHtModuleIn(); + ResetTargetData(); + }else + if(dType == dgTYPE_OUT_MODULE){ + PtStart.x = ModuleRectLv4.Left + 56; + PtStart.y = ModuleRectLv4.Top + 6; + PtStop.x = ModuleRectLv4.Left + 180; + PtStop.y = ModuleRectLv4.Top + 6; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htModuleOut; + InitHtModuleOut(); + ResetTargetData(); + }else + if(dType == dgTYPE_INOUT_MODULE_NonSource){ + PtStart.x = ModuleRectLv4.Left + 56; + PtStart.y = ModuleRectLv4.Top + 6; + PtStop.x = ModuleRectLv4.Left + 180; + PtStop.y = ModuleRectLv4.Top + 6; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htModuleInOut; + InitHtModuleInOut(); + ResetTargetData(); + }else + if(dType == dgType_VAALRAM){ + PtStart.x = ModuleRectLv4.Left + 76; + PtStart.y = ModuleRectLv4.Top + 6; + PtStop.x = ModuleRectLv4.Left + 190; + PtStop.y = ModuleRectLv4.Top + 6; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htVa; + InitHtVa(); + ResetTargetData(); + }else + if(dType == dgTYPE_DISPLAY_PAD){ + PtStart.x = Lv.Grid.Left[4] + 76; + PtStart.y = Lv.Grid.Top[4] + 36; + PtStop.x = Lv.Grid.Left[4] + 190; + PtStop.y = Lv.Grid.Top[4] + 36; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htDisplayPad; + InitHtDisplayPad(); + ResetTargetData(); + }else + if(dType == dgTYPE_LINKAGE_POWERSUPLY){ + PtStart.x = Lv.Grid.Left[2] + 56; + PtStart.y = Lv.Grid.Top[2] + 38; + PtStop.x = Lv.Grid.Left[2] + 180; + PtStop.y = Lv.Grid.Top[2] + 38; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htLinkagePowerSuply; + InitHtLinkagePowerSuply(); + ResetTargetData(); + }else{ + PtStart.x = Lv.Grid.Left[2] + 56; + PtStart.y = Lv.Grid.Top[2] + 38; + PtStop.x = Lv.Grid.Left[2] + 180; + PtStop.y = Lv.Grid.Top[2] + 38; + PanelDrawData.TextDrawLine = 0; + HwDevType = TDevProperty::htNoType; + ResetTargetData(); + InitNoType(); + } +} + +void TDevStartStop::ClearCommonInf() +{ + IList->STextDType.SetText("------",24); + IList->STextState.SetText("----", 24); + IList->STextRegisted.SetText("------", 24); + IList->EditDescpShow.Str.Text[0] = '\0'; + IList->EditDescpShow.Str.Text[1] = '\0'; + IList->EditUserCode.Str.FromStr("--------"); + IList->EditAreaAssign.Str.FromStr("----"); + + IList->STextDType.Show(); + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + IList->STextState.Show(); + IList->STextRegisted.Show(); + IList->EditDescpShow.Show(); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + +} + +void TDevStartStop::InitNoType() +{ + PanelIsUsingText = 1; + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +86, Lv.Grid.Top[2] + 4, 100,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + if(IsSelfCtl){ + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + char *tText; + if(LanguageEnCn==0)tText="获取中 "; else tText="Reading "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "--------"); + } +} + +void TDevStartStop::InitHtTempe() +{ + PanelIsUsingText = 1; + + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +116, Lv.Grid.Top[2] + 4, 60,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + if(IsSelfCtl){ + TempeRt.IsWait4ReadSensType = 1; + TempeRt.RecRdy = 0; + TempeRt.RecCmd = 0; + TempeRt.WaitTick = 0; + char *tText; + if(LanguageEnCn==0)tText="获取中 "; else tText="Reading "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else{ + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "--------"); + } +} + +void TDevStartStop::InitHtHandPad() +{ + PanelIsUsingText = 1; + + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +116, Lv.Grid.Top[2] + 4, 60,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); +} + +void TDevStartStop::InitHtHydrantPad() +{ + PanelIsUsingText = 1; + + for(int i=2; iEdit[0].Init(Lv.Grid.Left[2] +116, Lv.Grid.Top[2] + 4, 60,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); +} + +void TDevStartStop::InitHtModuleIn() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextModuleIn(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 196,30,0,0,clNearWhite,ItemColor); + if(IsSelfCtl){ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("Nont Type ", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + }else{ + IList->Edit[0].Str.FromStr("----"); + IList->STextModuleInDefineType.SetText("--------" , 24); + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + if(IsSelfCtl){ + //ModuleInRt.IsWait4ReadSignalType = 1; + //ModuleInRt.IsWait4WriteSignalType = 0; + //ModuleInRt.RecRdy = 0; + //ModuleInRt.RecCmd = 0; + //ModuleInRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalInType = Port[Path0-1].FuncSetByte[Path1-1]; + }else{ + TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + RedrawModuleInSignalInType(); +} + +void TDevStartStop::InitHtModuleInOut() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextModuleInOut(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 160,30,0,0,clNearWhite,ItemColor); + if(IsSelfCtl){ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("None Type ", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + + } + }else{ + IList->Edit[0].Str.FromStr("----"); + IList->STextModuleInDefineType.SetText("--------" , 24); + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + if(IsSelfCtl){ + //ModuleInOutRt.IsWait4ReadSignalType = 1; + //ModuleInOutRt.IsWait4WriteSignalType = 0; + //ModuleInOutRt.RecRdy = 0; + //ModuleInOutRt.RecCmd = 0; + //ModuleInOutRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalInOutType = Port[Path0-1].FuncSetByte[Path1-1]; + }else{ + TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + RedrawModuleInOutSignalType(); +} + +void TDevStartStop::InitHtModuleOut() +{ + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextModuleOut(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + IList->Edit[0].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 160,30,0,0,clNearWhite,ItemColor); + if(IsSelfCtl){ + unsigned char tType = Port[Path0-1].AssignType[Path1-1]; + IList->Edit[0].Str.FromUInt3Dg(tType); + if(LanguageEnCn==0){ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("未指派类型", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + } + }else{ + if(tType == 0){ + IList->STextModuleInDefineType.SetText("None Type", 24); + }else{ + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[tType] , 24); + } + } + }else{ + IList->Edit[0].Str.FromStr("----"); + IList->STextModuleInDefineType.SetText("--------" , 24); + } + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + if(IsSelfCtl){ + //ModuleOutRt.IsWait4ReadSignalType = 1; + //ModuleOutRt.IsWait4WriteSignalType = 0; + //ModuleOutRt.RecRdy = 0; + //ModuleOutRt.RecCmd = 0; + //ModuleOutRt.WaitTick = 0; + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + Data.ModuleSignalOutType = Port[Path0-1].FuncSetByte[Path1-1]; + }else{ + TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + RedrawModuleOutSignalType(); +} + +void TDevStartStop::InitHtVa() +{ + char *tText; + PanelIsUsingText = 1; + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + RectFillRender(Lv.Grid.Left[3], ModuleRectLv3.Top, Lv.Grid.Right[3], ModuleRectLv3.Bottom, ItemColor); + RectFillRender(Lv.Grid.Left[4], ModuleRectLv4.Top, Lv.Grid.Right[4], ModuleRectLv4.Bottom, ItemColor); + + DrawFixTextVa(); + + IList->Edit[0].Init(Lv.Grid.Left[3] +10, ModuleRectLv3.Top + 72, 100,30,0,0,1,clNearBlack); + IList->Edit[0].Enable = 0; + IList->Edit[0].Str.Clear(); + IList->Edit[0].Show(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + if(IsSelfCtl){ + VaRt.IsWait4ReadVaSetting = 1; + VaRt.IsWait4WriteVaSetting = 0; + VaRt.RecRdy = 0; + VaRt.RecCmd = 0; + VaRt.WaitTick = 0; + DrawVaReadWriteStates(5); + }else{ + TextRender_string24(Lv.Grid.Left[3] +190, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "--------"); + } + + RedrawVaIs4Linkage(); + RedrawVaSetting(); +} + +void TDevStartStop::InitHtDisplayPad() +{ + PanelIsUsingText = 1; + + for(int i=2; i<5; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + DrawFixTextDisplayPad(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + + RedrawDisplayPadMatchMode(); + RedrawDisplayPadMatchData(); +} + + +void TDevStartStop::InitHtLinkagePowerSuply() +{ + PanelIsUsingText = 1; + + for(int i=2; iEdit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "--------"); + return; + } + if(dType == dgTYPE_SMOKE_DETECTOR){ + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + SendSmokeCmdRead(); + if(LanguageEnCn==0)tText="获取中 "; else tText="Reading "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else + if(dType == dgTYPE_TEMPE_DETECTOR){ + TempeRt.IsWait4ReadSensType = 1; + TempeRt.RecRdy = 0; + TempeRt.RecCmd = 0; + TempeRt.WaitTick = 0; + SendTempeCmdRead(); + if(LanguageEnCn==0)tText="获取中 "; else tText="Reading "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + }else + if(dType == dgTYPE_IN_MODULE){ + //ModuleInRt.IsWait4ReadSignalType = 1; + //ModuleInRt.IsWait4WriteSignalType = 0; + //ModuleInRt.RecRdy = 0; + //ModuleInRt.RecCmd = 0; + //ModuleInRt.WaitTick = 0; + //SendModuleSignalInOutTypeRead(); + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + }else + if(dType == dgTYPE_OUT_MODULE){ + //ModuleOutRt.IsWait4ReadSignalType = 1; + //ModuleOutRt.IsWait4WriteSignalType = 0; + //ModuleOutRt.RecRdy = 0; + //ModuleOutRt.RecCmd = 0; + //ModuleOutRt.WaitTick = 0; + //SendModuleSignalInOutTypeRead(); + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + }else + if(dType == dgTYPE_INOUT_MODULE_NonSource){ + //ModuleInOutRt.IsWait4ReadSignalType = 1; + //ModuleInOutRt.IsWait4WriteSignalType = 0; + //ModuleInOutRt.RecRdy = 0; + //ModuleInOutRt.RecCmd = 0; + //ModuleInOutRt.WaitTick = 0; + //SendModuleSignalInOutTypeRead(); + //TextRender_string24(Lv.Grid.Left[3] +160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "获取中 "); + }else + if(dType == dgType_VAALRAM){ + VaRt.IsWait4ReadVaSetting = 1; + VaRt.IsWait4WriteVaSetting = 0; + VaRt.RecRdy = 0; + VaRt.RecCmd = 0; + VaRt.WaitTick = 0; + SendVaSettingRead(); + DrawVaReadWriteStates(5); + } +} + + +TGuiMsgReturn TDevStartStop::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + int HasPrcKey = 0; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(VK_LEFT == aKey){ + if(Tag.Inx == 0){ + if(IList->EditCtlNum.Pst < 0){ + if(CtlNumValid){ + ClearSelected(); + Tag.Inx = 1; + Check4Selected(); + HasPrcKey = 1; + } + } + }else + if(Tag.Inx == 5){ + ClearSelected(); + Tag.Inx = 4; + Check4Selected(); + HasPrcKey = 1; + } + }else + if(VK_RIGHT == aKey){ + if(Tag.Inx == 1){ + if(IList->EditPortNum.Pst >= IList->EditPortNum.Str.GetEndPst()){ + if(Tag.InxMin == 0){ + if(PortNumValid){ + ClearSelected(); + Tag.Inx = 0; + Check4Selected(); + HasPrcKey = 1; + } + } + } + }else + if(Tag.Inx == 4){ + ClearSelected(); + Tag.Inx = 5; + Check4Selected(); + HasPrcKey = 1; + } + } + if( HasPrcKey == 0) + KeyInCommonEdit(aKey); + break; + case VK_UP: + if(Tag.Inx > Tag.InxMin){ + if(Tag.Inx == 1){ + if(PortNumValid){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }else + if(Tag.Inx == 2){ + if(AddrNumValid){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }else{ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(Tag.Inx < 5){ + if(Tag.Inx == 0){ + if(CtlNumValid){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx == 1){ + if(PortNumValid){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx == 2){ + if(AddrNumValid){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else{ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + } + break; + case VK_TAB: + PanelIsUsingText = PanelIsUsingText ? 0 : 1; + break; + case dfKEY_SETUP: + ReReadCmdSend(); + break; + case dfKEY_QUERY: + PanelDrawData.DesertTextHex = PanelDrawData.DesertTextHex ? 0: 1; + break; + case VK_EXECUTE: + KeyInCommonEnter(aKey); + break; + case VK_RETURN: + IsShow = 0; + aMsg = guiMsgReturn; + break; + } + } + return aMsg; +} + + +TGuiMsgReturn TDevStartStop::KeyInCommonEdit(unsigned char aKey) +{ + int tVal; + unsigned char tP0, tP1, NewType, IsNewTarget; + TGuiMsgReturn aMsg = guiMsgNone; + int HasPrcKey = 0; + if(Tag.Inx == 0){ + //Ctl Num + pNumFound = 0; + IsNewTarget = 0; + IList->EditCtlNum.KeyIn(aKey); + tVal = IList->EditCtlNum.Str.ToInteger(); + if(tVal == MainCtl.fData.Split.MyNum){ + if(LanguageEnCn==0)IList->STextCtlType.SetText("本集中机",24); + else IList->STextCtlType.SetText("MainHost",24); + IList->EditCtlNum.SelectedColor = clBlue; + IsSelfCtl = 1; + CtlNumValid =1; + if(CtlNum != tVal){ + CtlNum = tVal; + ClearReqDataState(); + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + NewType = Port[tP0].dTypeTable[tP1]; + }else{ + NewType = 0; + Init4DType(); + } + if(NewType == dType){ + //Load New Addr Inf + Redraw4NewLoad(); + //UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + } + }else{ + if( (tVal >0) && (tVal <=dNETWORK_MACHINE_COUNT)){ + pNumFound = 1; + } + if(pNumFound){ + if(LanguageEnCn==0)IList->STextCtlType.SetText("区域机 ",24); + else IList->STextCtlType.SetText("REGIONAL",24); + IList->EditCtlNum.SelectedColor = clBlue; + CtlNumValid =1; + }else{ + if(LanguageEnCn==0)IList->STextCtlType.SetText("无效机号",24); + else IList->STextCtlType.SetText("Invalid",24); + IList->EditCtlNum.SelectedColor = clRed; + CtlNumValid =0; + } + IsSelfCtl = 0; + if(CtlNum != tVal){ + CtlNum = tVal; + ClearReqDataState(); + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + + NewType = 0; + if(NewType == dType){ + //Load New Addr Inf + //Redraw4NewLoad(); + //UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + } + } + IList->EditCtlNum.Show(); + IList->STextCtlType.Show(); + }else + if(Tag.Inx == 1){ + //Port Num + IsNewTarget = 0; + IList->EditPortNum.KeyIn(aKey); + tVal = IList->EditPortNum.Str.ToInteger(); + if( (tVal >0) && (tVal <= dPORT_MAX_COUNT) )PortNumValid = 1; else PortNumValid = 0; + if(IsSelfCtl){ + if( PortNumValid && AddrNumValid){ + if(Path0 != tVal){ + ClearReqDataState(); + Path0 = tVal; + IList->EditPortNum.SelectedColor = clBlue; + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + NewType = Port[tP0].dTypeTable[tP1]; + }else{ + NewType = 0; + Init4DType(); + } + if(NewType == dType){ + //Load New Addr Inf + Redraw4NewLoad(); + //UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + } + }else{ + ClearReqDataState(); + Path0 = 0; + if(dType != 0){ + dType = 0; + Init4DType(); + } + RealTimeSendCmdAbort(); + IList->EditPortNum.SelectedColor = clRed; + ClearCommonInf(); + } + }else{ + if( PortNumValid && AddrNumValid){ + if(Path0 != tVal){ + ClearReqDataState(); + Path0 = tVal; + IList->EditPortNum.SelectedColor = clBlue; + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + NewType = 0; + Init4DType(); + if(NewType == dType){ + //Load New Addr Inf + Redraw4NewLoad(); + //UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + } + }else{ + ClearReqDataState(); + Path0 = 0; + if(dType != 0){ + dType = 0; + Init4DType(); + } + RealTimeSendCmdAbort(); + IList->EditPortNum.SelectedColor = clRed; + ClearCommonInf(); + } + } + IList->EditPortNum.Show(); + }else + if(Tag.Inx == 2){ + //Addr Num + if(HasPrcKey == 0){ + IsNewTarget = 0; + IList->EditAddrNum.KeyIn(aKey); + tVal = IList->EditAddrNum.Str.ToInteger(); + if( (tVal >0) && (tVal <= dEP_MAX_COUNT_PER_PORT) )AddrNumValid = 1; else AddrNumValid = 0; + if(IsSelfCtl){ + if( PortNumValid && AddrNumValid){ + if(Path1 != tVal){ + ClearReqDataState(); + Path1 = tVal; + IList->EditAddrNum.SelectedColor = clBlue; + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + NewType = Port[tP0].dTypeTable[tP1]; + }else{ + NewType = 0; + Init4DType(); + } + if(NewType == dType){ + //Load New Addr Inf + + Redraw4NewLoad(); + //UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + } + }else{ + ClearReqDataState(); + Path1 = 0; + if(dType != 0){ + dType = 0; + Init4DType(); + } + RealTimeSendCmdAbort(); + IList->EditAddrNum.SelectedColor = clRed; + ClearCommonInf(); + } + }else{ + if( PortNumValid && AddrNumValid){ + if(Path1 != tVal){ + ClearReqDataState(); + Path1 = tVal; + IList->EditAddrNum.SelectedColor = clBlue; + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + NewType = 0; + Init4DType(); + if(NewType == dType){ + //Load New Addr Inf + Redraw4NewLoad(); + //UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + } + }else{ + ClearReqDataState(); + Path1 = 0; + if(dType != 0){ + dType = 0; + Init4DType(); + } + RealTimeSendCmdAbort(); + IList->EditAddrNum.SelectedColor = clRed; + ClearCommonInf(); + } + } + IList->EditAddrNum.Show(); + } + }else + if(Tag.Inx == 3){ + //User Code Here + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + } + return aMsg; +} + +TGuiMsgReturn TDevStartStop::KeyInCommonEnter(unsigned char aKey) +{ + int aVal; + TGuiMsgReturn aMsg = guiMsgNone; + if(Tag.Inx == 0){ + //Ctl Num + }else + if(Tag.Inx == 1){ + //Port Num + }else + if(Tag.Inx == 2){ + //Addr Num + }else + if(Tag.Inx == 3){ + //User Code + unsigned char tP0, tP1; + int Found =0; + int x; + aVal = IList->EditUserCode.Str.ToInteger(); + for(int i=0; i= Port[i].UserCodeMin) && (aVal <= Port[i].UserCodeMax) ){ + for(x=0; xEditPortNum.Color = clDeepGreen; + IList->EditAddrNum.Color = clDeepGreen; + IList->EditUserCode.SelectedColor = clDeepGreen; + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->EditUserCode.Show(); + DelayMs(150); + IList->EditPortNum.Color = clNearWhite; + IList->EditAddrNum.Color = clNearWhite; + IList->EditUserCode.SelectedColor = clBlue; + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->EditUserCode.Show(); + + CtlNumValid = 1; + PortNumValid =1; + AddrNumValid =1; + + ClearReqDataState(); + IList->EditCtlNum.Str.FromUInt2Dg(CtlNum); + IList->EditPortNum.Str.FromUInt2Dg(Path0); + IList->EditAddrNum.Str.FromUInt3Dg(Path1); + IList->EditCtlNum.Show(); + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + ReDrawCommonInf(); + Check4Selected(); + RealTimeSendCmdAbort(); + tP0 = Path0-1; + tP1 = Path1-1; + if(Port[tP0].ExistTable[tP1] == 0xA5){ + NewType = Port[tP0].dTypeTable[tP1]; + }else{ + NewType = 0; + Init4DType(); + } + if(NewType == dType){ + //Load New Addr Inf + Redraw4NewLoad(); + //UpdataOnlineData(); + }else{ + //Load 4 New Type + dType = NewType; + Init4DType(); + } + ResetTargetData(); + }else{ + IList->EditUserCode.SelectedColor = clRed; + IList->EditUserCode.Show(); + DelayMs(150); + IList->EditUserCode.SelectedColor = clBlue; + IList->EditUserCode.Show(); + } + }else + if(Tag.Inx == 4){ + //Start + if(SystemPermission >1){ + if(CtlNumValid && Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + SendStartStopCmd(1); + } + }else{ + if(CtlNumValid && Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + IsPermission = 1; + PermissionCmd = TDevProperty::pcStart; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + }else + if(Tag.Inx == 5){ + //Stop + if(SystemPermission >1){ + if(CtlNumValid && Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + SendStartStopCmd(0); + } + }else{ + if(CtlNumValid && Path0 && Path1 && (Path0 <= dPORT_MAX_COUNT) && (Path1<=dEP_MAX_COUNT_PER_PORT) ){ + IsPermission = 1; + PermissionCmd = TDevProperty::pcStop; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + return aMsg; +} + +void TDevStartStop::RedrawSmallPanelData() +{ + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + if(IsSelfCtl){ + RectFillRender(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 10 + 20, Lv.PanelSmall.Top + 6 + 20, clGreen); + TMyString::sClear(TextDraw); + TMyString::sFrom2Dg(RuntimeData.voltage % 100, TextDraw); + TMyString::sAddOnChar('.', TextDraw); + TMyString::sAddOn1Dg(0, TextDraw); + TMyString::sAddOnChar('V', TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 32, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, TextDraw); + if(Port[Path0-1].StateTable[Path1-1] & dEpStateBitStart){ + RectFillRender(Lv.PanelSmall.Left + 120, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 120 + 20, Lv.PanelSmall.Top + 6 + 20, clRed); + RectFillRender(Lv.PanelSmall.Left + 230, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 230 + 20, Lv.PanelSmall.Top + 6 + 20, clNearWhite); + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left + 146, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "已启动"); + TextRender_string24(Lv.PanelSmall.Left + 256, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "未停止 "); + }else{ + TextRender_string24(Lv.PanelSmall.Left + 146, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "Actived"); + TextRender_string24(Lv.PanelSmall.Left + 256, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "Not Stop"); + } + }else{ + RectFillRender(Lv.PanelSmall.Left + 120, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 120 + 20, Lv.PanelSmall.Top + 6 + 20, clNearWhite ); + RectFillRender(Lv.PanelSmall.Left + 230, Lv.PanelSmall.Top + 6, Lv.PanelSmall.Left + 230 + 20, Lv.PanelSmall.Top + 6 + 20, clRed ); + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left + 146, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "未启动"); + TextRender_string24(Lv.PanelSmall.Left + 256, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "已停止"); + }else{ + TextRender_string24(Lv.PanelSmall.Left + 146, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "Idle"); + TextRender_string24(Lv.PanelSmall.Left + 256, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "Stop"); + } + } + unsigned char Num, Num10; + TMyString::sClear(TextDraw); + TMyString::sAddOnStr("MAC:", TextDraw); + for(int i=0; i<6; i++){ + Num = RuntimeData.Mac[i] % 16; + Num10 = RuntimeData.Mac[i] / 16 % 16; + TMyString::sAddOnChar(stHexNum[Num10], TextDraw); + TMyString::sAddOnChar(stHexNum[Num], TextDraw); + if( (i&0x01) && (i<5) )TMyString::sAddOnChar(' ', TextDraw); + } + TextRender_string24(Lv.PanelSmall.Left + 280, Lv.PanelSmall.Top + 36, clNearWhite, SmallPanelColor, TextDraw); + }else{ + TMyString::sClear(TextDraw); + if(LanguageEnCn==0)TMyString::sAddOnStr("远程机状态未知,请查阅启动事件窗口", TextDraw); + else TMyString::sAddOnStr("The net machine status is unknown", TextDraw); + TextRender_string24(Lv.PanelSmall.Left + 20, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, TextDraw); + } +} + +void TDevStartStop::DrawVaReadWriteStates() +{ + char *tText; + if(VaReadWriteSta ==0 ){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, " "); + if(LanguageEnCn==0)tText =" "; else tText=" "; + }else + if(VaReadWriteSta == 1){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "读取成功"); + if(LanguageEnCn==0)tText ="读取成功"; else tText="Read OK "; + }else + if(VaReadWriteSta == 2){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "读取失败"); + if(LanguageEnCn==0)tText ="读取失败"; else tText="Read Err"; + }else + if(VaReadWriteSta == 3){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "保存成功"); + if(LanguageEnCn==0)tText ="保存成功"; else tText="Save OK "; + }else + if(VaReadWriteSta == 4){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "保存失败"); + if(LanguageEnCn==0)tText ="保存失败"; else tText="Save Err"; + }else + if(VaReadWriteSta == 5){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "获取中 "); + if(LanguageEnCn==0)tText ="获取中 "; else tText="Reading "; + }else + if(VaReadWriteSta == 6){ + //TextRender_string24(Lv.Grid.Left[3] + 190, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "写入中 "); + if(LanguageEnCn==0)tText ="写入中 "; else tText="Writing "; + } + TextRender_string24(Lv.Grid.Left[3] + 190, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, tText); +} + + +void TDevStartStop::DrawVaReadWriteStates(unsigned char aNewState) +{ + VaReadWriteSta = aNewState; + DrawVaReadWriteStates(); +} + +void TDevStartStop::Task1000Ms() +{ + char *tText; + if(IsShow == 0) return; + if( (IsSelfCtl) and (Path0) and (Path1 ) ){ + if( (Path0 <= dPORT_MAX_COUNT) && (Path1 <= dEP_MAX_COUNT_PER_PORT) ){ + if(IsRegisted){ + const unsigned char tSta = Port[Path0-1].StateTable[Path1-1]; + DrawState(tSta); + } + } + } + switch(HwDevType){ + case TDevProperty::htNoType: + + break; + case TDevProperty::htSmoker: + if(SmokerRt.IsWait4ReadSens){ + if(SmokerRt.RecRdy){ + if(SmokerRt.RecCmd == cmQuerySens){ + SmokerRt.RecRdy = 0; + SmokerRt.IsWait4ReadSens = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[1] )Data.SmokerSens = 1; + else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[2] )Data.SmokerSens = 2; + else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[3] )Data.SmokerSens = 3; + else if(ProcessingRt.dValGot[0] == dSmokeSensGrade_MarkValue[4] )Data.SmokerSens = 4; + else Data.SmokerSens = 5; + if(Data.SmokerSens == 1){ + if(LanguageEnCn==0)tText="灵敏 "; + else tText="Normal"; + }else + if(Data.SmokerSens == 2){ + if(LanguageEnCn==0)tText="中灵敏"; + else tText="Middle"; + }else + if(Data.SmokerSens == 3){ + if(LanguageEnCn==0)tText="高灵敏"; + else tText="ExHigh"; + }else + if(Data.SmokerSens == 4){ + if(LanguageEnCn==0)tText="超灵敏"; + else tText="Ultra"; + }else{ + if(LanguageEnCn==0)tText="未知 "; + else tText="UnKnown"; + } + IList->Edit[0].Str.FromStr(tText); + IList->Edit[0].Show(); + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + if(LanguageEnCn==0)tText="读取成功"; else tText="Read OK "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + } + } + } + SmokerRt.RecRdy = 0; + } + SmokerRt.WaitTick ++; + if(SmokerRt.WaitTick > 6){ + SmokerRt.IsWait4ReadSens = 0; + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + if(LanguageEnCn==0)tText="读取失败"; else tText="Read Err"; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + } + } + } + break; + case TDevProperty::htTempe: + if(TempeRt.IsWait4ReadSensType){ + if(TempeRt.RecRdy){ + if(TempeRt.RecCmd == cmQueryStaticData){ + TempeRt.RecRdy = 0; + TempeRt.IsWait4ReadSensType = 0; + //Add Record Here + if(1){ + if(Data.TempeSenType == 1){ + IList->Edit[0].Str.FromStr("A1"); + }else + if(Data.TempeSenType == 2){ + IList->Edit[0].Str.FromStr("A1R"); + }else + if(Data.TempeSenType == 3){ + IList->Edit[0].Str.FromStr("A1S"); + }else + if(Data.TempeSenType == 4){ + IList->Edit[0].Str.FromStr("A2"); + }else + if(Data.TempeSenType == 5){ + IList->Edit[0].Str.FromStr("A2R"); + }else + if(Data.TempeSenType == 6){ + IList->Edit[0].Str.FromStr("A2S"); + }else + if(Data.TempeSenType == 7){ + IList->Edit[0].Str.FromStr("B"); + }else + if(Data.TempeSenType == 8){ + IList->Edit[0].Str.FromStr("BR"); + }else + if(Data.TempeSenType == 9){ + IList->Edit[0].Str.FromStr("BS"); + }else{ + if(LanguageEnCn==0)IList->Edit[0].Str.FromStr("未知 "); + else IList->Edit[0].Str.FromStr("UnKnown"); + } + IList->Edit[0].Show(); + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + if(LanguageEnCn==0)tText="读取成功"; else tText="Read OK "; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + } + } + } + TempeRt.RecRdy = 0; + } + TempeRt.WaitTick ++; + if(TempeRt.WaitTick > 6){ + TempeRt.IsWait4ReadSensType = 0; + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + if(LanguageEnCn==0)tText="读取失败"; else tText="Read Err"; + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, tText); + } + } + } + /*if( (Data.GotTempeSensType[0] == 0xF1) && (Data.GotTempeSensType[4] == 0) ){ + if( (Data.GotTempeSensType[1] == Path0) && (Data.GotTempeSensType[2] == Path1) ){ + Data.TempeSenType = Data.GotTempeSensType[3]; + //1～9=A1、A1R、A1S、A2、A2R、A2S、B、BR、BS + if(Data.TempeSenType == 1){ + IList->Edit[0].Str.FromStr("A1"); + }else + if(Data.TempeSenType == 2){ + IList->Edit[0].Str.FromStr("A1R"); + }else + if(Data.TempeSenType == 3){ + IList->Edit[0].Str.FromStr("A1S"); + }else + if(Data.TempeSenType == 4){ + IList->Edit[0].Str.FromStr("A2"); + }else + if(Data.TempeSenType == 5){ + IList->Edit[0].Str.FromStr("A2R"); + }else + if(Data.TempeSenType == 6){ + IList->Edit[0].Str.FromStr("A2S"); + }else + if(Data.TempeSenType == 7){ + IList->Edit[0].Str.FromStr("B"); + }else + if(Data.TempeSenType == 8){ + IList->Edit[0].Str.FromStr("BR"); + }else + if(Data.TempeSenType == 9){ + IList->Edit[0].Str.FromStr("BS"); + }else{ + IList->Edit[0].Str.FromStr("未知 "); + } + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + IList->Edit[0].Show(); + TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "读取成功"); + Data.GotTempeSensType[4] =1; + } + } + }*/ + break; + case TDevProperty::htHandPad: + break; + case TDevProperty::htHydrantPad: + break; + case TDevProperty::htModuleIn: + /*if(ModuleInRt.IsWait4ReadSignalType){ + if(ModuleInRt.RecRdy){ + if(ModuleInRt.RecCmd == cmQuerySens){ + ModuleInRt.RecRdy = 0; + ModuleInRt.IsWait4ReadSignalType = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + Data.ModuleSignalInType = RecData[4]; + RedrawModuleInSignalInType(); + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + }else{ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + } + } + } + ModuleInRt.RecRdy = 0; + } + ModuleInRt.WaitTick ++; + if(ModuleInRt.WaitTick > 6){ + ModuleInRt.IsWait4ReadSignalType = 0; + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + }else{ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + } + } + }*/ + break; + case TDevProperty::htModuleInOut: + /*if(ModuleInOutRt.IsWait4ReadSignalType){ + if(ModuleInOutRt.RecRdy){ + if(ModuleInOutRt.RecCmd == cmQuerySens){ + ModuleInOutRt.RecRdy = 0; + ModuleInOutRt.IsWait4ReadSignalType = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + Data.ModuleSignalInType = RecData[4]; + RedrawModuleInSignalInType(); + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + }else{ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + } + } + } + ModuleInOutRt.RecRdy = 0; + } + ModuleInOutRt.WaitTick ++; + if(ModuleInOutRt.WaitTick > 6){ + ModuleInOutRt.IsWait4ReadSignalType = 0; + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + }else{ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + } + } + }*/ + break; + case TDevProperty::htModuleOut: + /*if(ModuleOutRt.IsWait4ReadSignalType){ + if(ModuleOutRt.RecRdy){ + if(ModuleOutRt.RecCmd == cmQuerySens){ + ModuleOutRt.RecRdy = 0; + ModuleOutRt.IsWait4ReadSignalType = 0; + //Add Record Here + if(ProcessingRt.DataType == 1){ + Data.ModuleSignalInType = RecData[4]; + RedrawModuleInSignalInType(); + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + }else{ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取成功"); + } + } + } + ModuleOutRt.RecRdy = 0; + } + ModuleOutRt.WaitTick ++; + if(ModuleOutRt.WaitTick > 6){ + ModuleOutRt.IsWait4ReadSignalType = 0; + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + }else{ + TextRender_string24(Lv.Grid.Left[3] + 160, ModuleRectLv3.Top + 4, clNearWhite, ItemColor, "读取失败"); + } + } + }*/ + break; + case TDevProperty::htVa: + if(VaRt.IsWait4ReadVaSetting){ + if(VaRt.RecRdy){ + if(VaRt.RecCmd == cmQueryStaticData){ + VaRt.IsWait4ReadVaSetting = 0; + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + RedrawVaIs4Linkage(); + RedrawVaSetting(); + DrawVaReadWriteStates(1); + }else{ + VaReadWriteSta =1; + } + } + VaRt.RecRdy = 0; + } + VaRt.WaitTick ++; + if(VaRt.WaitTick > 6){ + VaRt.IsWait4ReadVaSetting = 0; + if( (IsHotKeyCheckingPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawVaReadWriteStates(2); + }else{ + VaReadWriteSta =2; + } + } + } + break; + case TDevProperty::htDisplayPad: + break; + case TDevProperty::htLinkagePowerSuply: + break; + default : + + break; + } + RedrawSmallPanelData(); +} + +int TDevStartStop::ExtRequst(unsigned char Prm) +{ + IsShow = 0; + return 0; +} + + + + + + + diff --git a/MyCode/Gui/DevStartStop.h b/MyCode/Gui/DevStartStop.h new file mode 100644 index 0000000..f9ca56f --- /dev/null +++ b/MyCode/Gui/DevStartStop.h @@ -0,0 +1,415 @@ +#ifndef DEVSTARTSTOP_H_ +#define DEVSTARTSTOP_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "DevProperty.h" +#include "ItemList.h" + +class TDevStartStop{ + public: + static constexpr unsigned short hList[12] = {72,72,72,72, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,290,290,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 5, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 220, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1, + + .PanelSmall.Active = 1, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 72, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1 + 72 -1, + }; + static constexpr TRect ModuleRectLv3 = { + .Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3] + 30, + + }; + static constexpr TRect ModuleRectLv4 = { + .Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + 30, + .Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + }; + static const unsigned int LvGridHighBottom3 = 102; + static constexpr unsigned char dTypeList[256] = { + dgTYPE_SMOKE_DETECTOR, + dgTYPE_TEMPE_DETECTOR, + dgType_VAALRAM, + }; + static constexpr unsigned char dSmokeSensGrade_MarkValue[8] = { + //100, 75, 50, 25 + 0, 100, 75, 50, 25, 0, 0, 0 + }; + + enum TDrawTextType{ + dtNone = 0, + dtHex =1, + dtDec =2 + }; + private: + unsigned char VaReadWriteSta; + public: + class TItemList *IList; + int IsShow; + TCtlPanel1 *aPanel; + unsigned char CtlNum; + unsigned char Path0; + unsigned char Path1; + unsigned char dType; + unsigned char pNumFound; + unsigned char IsRegisted; + unsigned char IsSelfCtl; + TStaticText Caption; + + int IsPermission; + TDevProperty::TPermissionCmd PermissionCmd; + int EdittingDescp; + int IsExtInput; + unsigned char CtlNumValid; + unsigned char PortNumValid; + unsigned char AddrNumValid; + unsigned char PanelIsUsingText; + + TDevProperty::THwDevType HwDevType; + TRootDevice *RootDev; + TEpDevice *EpDev; + + struct{ + unsigned char Inx; + unsigned char InxMin; + void Reset(){ + Inx = 0; + InxMin =0; + } + }Tag; + + TUserCode aUcSetting; + + unsigned char RecData[8]; + + char TextTmp[24]; + struct{ + int TextDrawLine; + int FigInx; + unsigned char IsHexList[8]; + unsigned char DesertTextHex; + unsigned char UsingTextHex; + void Reset(){ + for(int i=0; i<8; i++)IsHexList[i]=dtNone; + TextDrawLine = 0; + FigInx = 0; + //DesertTextHex = 0; + //UsingTextHex = 0; + } + void ResetNotFull(){ + TextDrawLine = 0; + FigInx = 0; + } + }PanelDrawData; + + struct{ + TUserCode UserCode; + unsigned char SmokerSens; + unsigned char TempeSenType; + unsigned char ModuleDefineType; + unsigned char ModuleSignalInType; + unsigned char ModuleSignalInOutType; + unsigned char ModuleSignalOutType; + unsigned char VaIs4Linkage; + unsigned char VaVisionType; + unsigned char VaSoundType; + unsigned char DisplayPadMatchMode; //0:By User Code; 1:By Area Assign + unsigned char DisplayPadAreaUsing[3]; + unsigned char DisplayPadUserCodeUsing[2]; + unsigned short DisplayPadArea0; + unsigned short DisplayPadArea1; + unsigned short DisplayPadArea2; + unsigned int DisplayUserCode0; + unsigned int DisplayUserCode1; + unsigned char GotTempeSensType[8]; + void Reset(){ + UserCode.Full =0; + SmokerSens = 0; + TempeSenType = 0; + ModuleDefineType =0; + ModuleSignalInType =0; + ModuleSignalInOutType =0; + ModuleSignalOutType =0; + VaIs4Linkage =0; + VaVisionType =0; + VaSoundType =0; + DisplayPadMatchMode =0; //0:By User Code; 1:By Area Assign + DisplayPadAreaUsing[0] = 0; + DisplayPadAreaUsing[1] = 0; + DisplayPadAreaUsing[2] = 0; + DisplayPadUserCodeUsing[0] = 0; + DisplayPadUserCodeUsing[1] = 0; + DisplayPadArea0 =0; + DisplayPadArea1 =0; + DisplayPadArea2 =0; + DisplayUserCode0 =0; + DisplayUserCode1 =0; + GotTempeSensType[0] =0; + GotTempeSensType[1] =0; + GotTempeSensType[2] =0; + GotTempeSensType[3] =0; + GotTempeSensType[4] =0; + } + }Data; + struct{ + unsigned int voltage; + unsigned int SmokerPrmM; + unsigned int SmokerIR; + unsigned int SmokerBR; + unsigned int Celsius; + unsigned int AlramCount0; + unsigned int AlramCount1; + unsigned int OutputVoltage; + unsigned int OutputCurrent; + unsigned int PwrLoaddingPercent; + unsigned char Mac[8]; + void Reset(){ + voltage =0; + SmokerPrmM =0; + SmokerIR =0; + SmokerBR =0; + Celsius =0; + AlramCount0 =0; + AlramCount1 =0; + OutputVoltage =0; + OutputCurrent =0; + PwrLoaddingPercent =0; + for(int i=0; i<8; i++)Mac[i] =0; + } + }RuntimeData; + + unsigned char CommData[16]; + struct{ + unsigned char Method; + unsigned char P0; + unsigned char P1; + unsigned char DevType; + unsigned char DataType; + + unsigned char dVal[4]; + unsigned char dValGot[4]; + unsigned char dType; + }ProcessingRt; + struct{ + unsigned char IsWait4ReadSens; + unsigned char IsWait4WriteSens; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }SmokerRt; + struct{ + unsigned char IsWait4ReadSensType; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }TempeRt; + struct{ + unsigned char IsWait4ReadSignalType; + unsigned char IsWait4WriteSignalType; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }ModuleInRt; + struct{ + unsigned char IsWait4ReadSignalType; + unsigned char IsWait4WriteSignalType; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }ModuleInOutRt; + struct{ + unsigned char IsWait4ReadSignalType; + unsigned char IsWait4WriteSignalType; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }ModuleOutRt; + struct{ + unsigned char IsWait4ReadVaSetting; + unsigned char IsWait4WriteVaSetting; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + }VaRt; + struct{ + unsigned char IsMute; + unsigned char IsDownloadDescp; + unsigned char RecRdy; + unsigned char RecCmd; + unsigned char WaitTick; + char DescpText[36]; + }DisplayPadRt; + struct{ + unsigned char VaIs4Linkage; + unsigned char VaVisionType; + unsigned char VaSoundType; + unsigned char Dump0; + }ExData; + char TextDraw[40]; + TPoint PtStart; + TPoint PtStop; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TDevStartStop(){}; + void Init(TDevProperty::THwDevType aDevType, int aMode); + void DelayMs(unsigned int aMs); + void DrawSelf(); + void RedrawCommonByExReturn(); + void DrawHtInf(int aPrm); + void DrawState(unsigned char aSta); + void DrawStateNone(); + void DrawMac(); + void SetPath(unsigned char aCtlNum, unsigned char aPath0, unsigned char aPath1); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void PermissionCmdReturnDraw(); + void ReDrawPanel(); + void ClearCommonInf(); + + void DrawCommonInfTitle(); + void ReDrawCommonInf(); + void RenewCommonInf(); + void Redraw4NewLoad(); + void RedrawModuleInSignalInType(); + void RedrawModuleInOutSignalType(); + void RedrawModuleOutSignalType(); + void RedrawVaIs4Linkage(); + void RedrawVaSetting(); + void RedrawDisplayPadMatchMode(); + void RedrawDisplayPadMatchData(); + void RedrawSmallPanelData(); + + void DrawFixTextNoType(); + void DrawFixTextSmoker(); + void DrawFixTextTempe(); + void DrawFixTextHandPad(); + void DrawFixTextHydrantPad(); + void DrawFixTextModuleIn(); + void DrawFixTextModuleInOut(); + void DrawFixTextModuleOut(); + void DrawFixTextVa(); + void DrawFixTextDisplayPad(); + void DrawFixTextLinkagePowerSuply(); + + void ResetTargetData(); + + void Init4DType(); + void InitNoType(); + void InitHtSmoker(); + void InitHtTempe(); + void InitHtHandPad(); + void InitHtHydrantPad(); + void InitHtModuleIn(); + void InitHtModuleInOut(); + void InitHtModuleOut(); + void InitHtVa(); + void InitHtDisplayPad(); + void InitHtLinkagePowerSuply(); + + void ReReadCmdSend(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + TGuiMsgReturn KeyInCommonEdit(unsigned char aKey); + TGuiMsgReturn KeyInCommonEnter(unsigned char aKey); + + void InitPanel(); + void ShowStartNewMsg(unsigned char Hour, unsigned char Min, unsigned char Sec); + void ClearSelected(); + void Check4Selected(); + void CheckPathDev(); + void SendCmd(unsigned int IsStart); + + void SendStartStopCmd(unsigned int IsStart); + void SendSmokeCmdRead(); + void SendTempeCmdRead(); + void SendModuleSignalInOutTypeRead(); + void SendVaSettingRead(); + + void RealTimeSendCmd(const int StartStop); + void RealTimeSendCmdAbort(); + void RunTimeSendCmd(const int StartStop); + void PermissionCmdGO(); + void ClearReqDataState(); + void UpdataOnlineData(); + + void PushOneRealDataReport(u8 aP0, u8 aP1, u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3); + void PushInnerCanData(unsigned char aCmd, unsigned char *pData); + void PushInnerRuntimeCanData(unsigned char aCmd, unsigned char *pData); + + void LoadUcBcdText(unsigned int aUcFull, char *pText); + void DrawVaReadWriteStates(); + void DrawVaReadWriteStates(unsigned char aNewState); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + + diff --git a/MyCode/Gui/DevStartStopCmd.cpp b/MyCode/Gui/DevStartStopCmd.cpp new file mode 100644 index 0000000..ec45c21 --- /dev/null +++ b/MyCode/Gui/DevStartStopCmd.cpp @@ -0,0 +1,621 @@ +#include "RuntimeData.h" +#include "DevStartStop.h" + +#define cmDeviceSetTempeSensType 211 +#define cmDeviceReadTempeSensType 212 + +#define cmDeviceSetSignalInOutType 199 +#define cmDeviceQuerySignalInOutType 200 + +#define cmDeviceDisplayPadMute 203 +#define cmDeviceDisplayPadDescpSet 204 + +#define cmDeviceRuntimeDataStart 207 +#define cmDeviceRuntimeDataStop 208 + +#define cmDeviceLinkagePowerSuplyMute 209 + +static const unsigned char stHexNum[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +void TDevStartStop::SendStartStopCmd(unsigned int IsStart) +{ + unsigned char tCmd; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0, aP1; + + if(IsSelfCtl){ + if(IsStart){ + tCmd = cmAutoStart; + }else{ + tCmd = cmAutoStop; + } + for(i=0; i<8; i++){ + CommData[i] = 0; + } + CommData[0] = 0; + CommData[1] = CtlNum; + CommData[2] = Path0; + CommData[3] = Path1; + CommData[4] = 0; + CommData[5] = dType; + aP0 = Path0 -1; aP1 = Path1 -1; + if( (Port[aP0].StateTable[aP1] & dEpStateBitMask) == 0){ + InnerCan.OBufFastInsert(1, tCmd, CommData, 6); + }else{ + } + }else{ + if(MainCtl.fData.Split.NetworkMode == 1){ + if(pNumFound){ + ProtoC2C.MasterDoDevRemoteStart(CtlNum, Path0, Path1, IsStart); + }else{ + } + }else{ + + } + } +} + +void TDevStartStop::SendSmokeCmdRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 3; + + CommData[1] = Path0; + ProcessingRt.P0 = Path0; + + CommData[2] = Path1; + ProcessingRt.P1 = Path1; + + CommData[3] = ProcessingRt.DataType; + + aIde.BitF.Cmd = cmQuerySens; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevStartStop::SendTempeCmdRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + Len =8; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = Path0; + ProcessingRt.P0 = Path0; + + CommData[3] = Path1; + ProcessingRt.P1 = Path1; + + ProcessingRt.DataType = 0x06; + + CommData[4] = ProcessingRt.DataType; + + aIde.BitF.Cmd = cmQueryStaticData; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevStartStop::SendModuleSignalInOutTypeRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 3; + + CommData[1] = Path0; + ProcessingRt.P0 = Path0; + + CommData[2] = Path1; + ProcessingRt.P1 = Path1; + + CommData[3] = ProcessingRt.DataType; + + aIde.BitF.Cmd = cmDeviceQuerySignalInOutType; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevStartStop::SendVaSettingRead() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + ProcessingRt.DevType = 0; //点型烟感 + ProcessingRt.DataType = 1; //烟感灵敏度 + + Len =4; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 3; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = Path0; + ProcessingRt.P0 = Path0; + + CommData[3] = Path1; + ProcessingRt.P1 = Path1; + + CommData[4] = 0; + + aIde.BitF.Cmd = cmQueryStaticData; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevStartStop::RealTimeSendCmd(const int StartStop) +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[2] = Path0; + CommData[3] = Path1; + + if(StartStop != 0){ + aIde.BitF.Cmd = cmQueryRuntimeData; + }else{ + aIde.BitF.Cmd = cmQueryAbout; + } + Len = 4; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevStartStop::RealTimeSendCmdAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + aIde.BitF.Cmd = cmQueryAbout; + Len = 4; + //Prm + CommData[0] = 0; + CommData[1] = 0; + CommData[2] = Path0; + CommData[3] = Path1; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevStartStop::RunTimeSendCmd(const int StartStop) +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[2] = Path0; + CommData[3] = Path1; + + if(StartStop != 0){ + aIde.BitF.Cmd = cmDeviceRuntimeDataStart; + }else{ + aIde.BitF.Cmd = cmDeviceRuntimeDataStop; + } + Len = 4; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); +} + +void TDevStartStop::PermissionCmdGO() +{ + int aVal; + switch(PermissionCmd){ + case TDevProperty::pcStart: + SendStartStopCmd(1); + break; + case TDevProperty::pcStop: + SendStartStopCmd(0); + break; + } +} + +void TDevStartStop::ClearReqDataState() +{ + SmokerRt.IsWait4ReadSens = 0; + SmokerRt.IsWait4WriteSens = 0; + TempeRt.IsWait4ReadSensType =0; + ModuleInRt.IsWait4ReadSignalType =0; + ModuleInRt.IsWait4WriteSignalType =0; + ModuleInOutRt.IsWait4ReadSignalType =0; + ModuleInOutRt.IsWait4WriteSignalType =0; + ModuleOutRt.IsWait4ReadSignalType =0; + ModuleOutRt.IsWait4WriteSignalType =0; + VaRt.IsWait4ReadVaSetting =0; + VaRt.IsWait4WriteVaSetting =0; + DisplayPadRt.IsMute =0; + DisplayPadRt.IsDownloadDescp =0; +} + +void TDevStartStop::UpdataOnlineData() +{ + if(dType == dgTYPE_SMOKE_DETECTOR){ + if(IsSelfCtl){ + SmokerRt.IsWait4ReadSens = 1; + SmokerRt.IsWait4WriteSens = 0; + SmokerRt.RecRdy = 0; + SmokerRt.RecCmd = 0; + SmokerRt.WaitTick = 0; + SendSmokeCmdRead(); + if(EdittingDescp == 0)TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "获取中 "); + }else{ + if(EdittingDescp == 0)TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "--------"); + } + }else + if(dType == dgTYPE_TEMPE_DETECTOR){ + if(IsSelfCtl){ + TempeRt.IsWait4ReadSensType = 1; + TempeRt.RecRdy = 0; + TempeRt.RecCmd = 0; + TempeRt.WaitTick = 0; + SendTempeCmdRead(); + if(EdittingDescp == 0)TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "获取中 "); + }else{ + if(EdittingDescp == 0)TextRender_string24(IList->Edit[0].Bound.Right + 6, IList->Edit[0].Bound.Top + 4, clNearWhite, ItemColor, "--------"); + } + }else + if(dType == dgTYPE_HAND_REPORT){ + + }else + if(dType == dgTYPE_FIRE_HydrantKp){ + + }else + if(dType == dgTYPE_IN_MODULE){ + + }else + if(dType == dgTYPE_OUT_MODULE){ + + }else + if(dType == dgTYPE_INOUT_MODULE_NonSource){ + + }else + if(dType == dgType_VAALRAM){ + + }else + if(dType == dgTYPE_DISPLAY_PAD){ + + }else + if(dType == dgTYPE_LINKAGE_POWERSUPLY){ + + } +} + +void TDevStartStop::PushOneRealDataReport(u8 aP0, u8 aP1, u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3) +{ + unsigned int aAddr, i, Num, Num10, Pst; + unsigned char Da[4]; + int x,y; + + const int MaxLen=41; + + if(IsShow == 0)return; + + if(aP0 != Path0)return; + if(aP1 != Path1)return; + + Da[0] = D0; + Da[1] = D1; + Da[2] = D2; + Da[3] = D3; + if(PanelDrawData.TextDrawLine >7){ + PanelDrawData.Reset(); + } + if(aInx == 0){ + RuntimeData.voltage = Da[1]; + PanelDrawData.TextDrawLine++; + if(PanelDrawData.TextDrawLine >7){ + PanelDrawData.Reset(); + } + if(PanelDrawData.TextDrawLine == 0){ + for(int z=0; z<8; z++){ + for(int g=0; g<80; g++){ + IList->TextOut[z][g] = '\0'; + } + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + } + } + } + y = Lv.Panel.Top + 1; + y = y + PanelDrawData.TextDrawLine * 27; + x = Lv.Panel.Left + 2; + TMyString::sClear(TextTmp); + PanelDrawData.UsingTextHex = PanelDrawData.DesertTextHex; + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtNone){ + if(PanelDrawData.UsingTextHex)PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] =dtHex; + else PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] =dtDec; + } + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtHex){ + for(i=0; i<4; i++){ + Pst= 0 + i*3; + Num = Da[i] % 16; + Num10 = Da[i] / 16 % 16; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = stHexNum[Num10]; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = stHexNum[Num]; + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ','; + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + }else + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtDec){ + for(i=0; i<4; i++){ + Pst= 0 + i*4; + Num = Da[i] / 100; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = Num + '0'; + Num = Da[i] % 100 / 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = Num + '0'; + Num = Da[i] % 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = Num + '0'; + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ','; + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + } + }else + if(aInx < 4){ + if(aInx == 2){ + /*if(dType == dgTYPE_TEMPE_DETECTOR){ + Data.GotTempeSensType[0] = 0xF1; + Data.GotTempeSensType[1] = Path0; + Data.GotTempeSensType[2] = Path1; + Data.GotTempeSensType[3] = D1; + }*/ + } + + y = Lv.Panel.Top + 1; + y = y + PanelDrawData.TextDrawLine * 27; + x = Lv.Panel.Left + 2; + TMyString::sClear(TextTmp); + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtHex){ + for(i=0; i<4; i++){ + Pst= aInx*12 + i*3; + if(Pst > (MaxLen-1-2))break; + Num = Da[i] % 16; + Num10 = Da[i] / 16 % 16; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = stHexNum[Num10]; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = stHexNum[Num]; + if((Pst+2)<=(MaxLen-1)){ + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = ','; + } + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) /*&& (aInx == 3)*/ ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + }else + if(PanelDrawData.IsHexList[PanelDrawData.TextDrawLine] == dtDec){ + for(i=0; i<4; i++){ + Pst= aInx*16 + i*4; + if(Pst > (MaxLen-1-3))break; + Num = Da[i] / 100; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+0] = Num + '0'; + Num = Da[i] % 100 / 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+1] = Num + '0'; + Num = Da[i] % 10; + IList->TextOut[PanelDrawData.TextDrawLine][Pst+2] = Num + '0'; + if((Pst+3)<=(MaxLen-1)){ + if(i<3)IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ' '; + else IList->TextOut[PanelDrawData.TextDrawLine][Pst+3] = ','; + } + } + if( (EdittingDescp == 0) && (IsPermission == 0) ){ + if( PanelIsUsingText && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) /*&& (aInx == 3)*/ ) + TextRender_string24(x,y,clNearBlack, PanelColor, IList->TextOut[PanelDrawData.TextDrawLine]); + } + } + } +} + +void TDevStartStop::PushInnerCanData(unsigned char aCmd, unsigned char *pData) +{ + int i; + switch(HwDevType){ + case TDevProperty::htNoType: + + break; + case TDevProperty::htSmoker: + if(aCmd == cmQuerySens){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ProcessingRt.dValGot[1] = RecData[5]; + ProcessingRt.dValGot[2] = RecData[6]; + ProcessingRt.dValGot[3] = RecData[7]; + SmokerRt.RecRdy =1; + SmokerRt.RecCmd =aCmd; + } + } + break; + case TDevProperty::htTempe: + if(aCmd == cmQueryStaticData){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) ){ + if( RecData[3] == 0 ){ + Data.TempeSenType = RecData[5]; + TempeRt.RecRdy =1; + TempeRt.RecCmd =aCmd; + } + } + } + break; + case TDevProperty::htHandPad: + + break; + case TDevProperty::htHydrantPad: + + break; + case TDevProperty::htModuleIn: + if(aCmd == cmDeviceQuerySignalInOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ModuleInRt.RecRdy =1; + ModuleInRt.RecCmd =aCmd; + } + } + break; + case TDevProperty::htModuleInOut: + if(aCmd == cmDeviceQuerySignalInOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ModuleInOutRt.RecRdy =1; + ModuleInOutRt.RecCmd =aCmd; + } + } + break; + case TDevProperty::htModuleOut: + if(aCmd == cmDeviceQuerySignalInOutType){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + (ProcessingRt.DataType == RecData[3]) ){ + ProcessingRt.dValGot[0] = RecData[4]; + ModuleOutRt.RecRdy =1; + ModuleOutRt.RecCmd =aCmd; + } + } + break; + case TDevProperty::htVa: + if(aCmd == cmQueryStaticData){ + for(i=0; i<8; i++)RecData[i] = pData[i]; + if( (ProcessingRt.P0 == RecData[1]) && + (ProcessingRt.P1 == RecData[2]) && + ( 0 == RecData[3]) ){ + Data.VaSoundType = RecData[4]; + Data.VaVisionType = RecData[5]; + Data.VaIs4Linkage = RecData[6]; + VaRt.RecRdy =1; + VaRt.RecCmd =aCmd; + } + } + break; + case TDevProperty::htDisplayPad: + + break; + case TDevProperty::htLinkagePowerSuply: + + break; + default : + + break; + } +} + + diff --git a/MyCode/Gui/DevVaCfg.cpp b/MyCode/Gui/DevVaCfg.cpp new file mode 100644 index 0000000..e805dc5 --- /dev/null +++ b/MyCode/Gui/DevVaCfg.cpp @@ -0,0 +1,903 @@ +#include "RuntimeData.h" +#include "DevVaCfg.h" +#include "DevMask.h" +#include "server.h" + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" + #include "fdcan_task.h" + #include "uart_key_drv.h" +} + +//Acoustooptic Parameter + +static const short svGrid1X[20] = { + 13, 52, 91, 130, 169, 208, 247, 286, 325, 364, 403, 442, 481, 520, 559, 598, 637, 676, 715, 754 +}; +static const short svGrid1X2[20] = { + 48, 87, 126, 165, 204, 243, 282, 321, 360, 399, 438, 477, 516, 555, 594, 633, 672, 711, 750, 789 +}; + +void TDevVaCfg::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "工程->批量查询声光属性"); //"工程->批量设置声光属性"); + TextRender_string24(Lv.Grid.Left[0] +520, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "本机声光数量:"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "设定回路地址段以查询"); //"单回路地址段查询或配置"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 38, clNearWhite, ItemColor, "回路号"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 72, clNearWhite, ItemColor, "起始地址"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 106, clNearWhite, ItemColor, "结束地址"); + + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 140, clNearWhite, ItemColor, "联动设定"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 174, clNearWhite, ItemColor, "声光设定"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 208, clNearWhite, ItemColor, "音调设定"); + + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 8, clNearWhite, ItemColor, "查询"); //"查询或执行设定"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +40, Lv.Grid.Top[1] + 42, 120, 30, 7, clNearWhite, "开始查询", 14, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[1] +180, Lv.Grid.Top[1] + 42, 120, 30, 7, clNearWhite, "保存配置", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Project->Acoustooptic Parameter"); + TextRender_string24(Lv.Grid.Left[0] +520, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "Acoustooptics"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "Set The Scope Of One Loop"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 38, clNearWhite, ItemColor, "Loop"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 72, clNearWhite, ItemColor, "Begin Ad"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 106, clNearWhite, ItemColor, "End Addr"); + + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 140, clNearWhite, ItemColor, "Linkage "); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 174, clNearWhite, ItemColor, "V And S "); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 208, clNearWhite, ItemColor, "Tone "); + + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 8, clNearWhite, ItemColor, "Query"); //"Query Or Set"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +40, Lv.Grid.Top[1] + 42, 120, 30, 7, clNearWhite, " Query ", 14, clNearBlack); + //TRoundRect::sDrawBySize(Lv.Grid.Left[1] +180, Lv.Grid.Top[1] + 42, 120, 30, 7, clNearWhite, " Config ", 14, clNearBlack); + } +} + +void TDevVaCfg::Init() +{ + IsPermission = 0; + Path0 = 1; + StartAddr = 1; + EndAddr = 250; + State = Idle; + Tag.Inx = 0; + WriteResult =0; + WritingCfBytes.IsLink =1; + WritingCfBytes.VnA = 0; + WritingCfBytes.Tone = 0; + + IList = nullptr; + + KeepOnMeJustEnter = nullptr; + KeepUiOnMe = nullptr; +} + +void TDevVaCfg::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDevVaCfg::DrawSelf(void) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + + for(int i=0; iEdit[0].Init(Lv.Grid.Left[0] +114, Lv.Grid.Top[0] + 36, 100,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(2); + IList->Edit[0].Str.Clear(); + TMyString::sFrom2Dg(Path0,Text); + IList->Edit[0].SetText(Text, 24); + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + + IList->Edit[1].Init(Lv.Grid.Left[0] +114, Lv.Grid.Top[0] + 70, 100,30,0,0,1,clNearBlack); + IList->Edit[1].SetMaxLen(3); + IList->Edit[1].Str.Clear(); + TMyString::sFrom3Dg(StartAddr,Text); + IList->Edit[1].SetText(Text, 24); + IList->Edit[1].Show(); + + IList->Edit[2].Init(Lv.Grid.Left[0] +114, Lv.Grid.Top[0] + 104, 100,30,0,0,1,clNearBlack); + IList->Edit[2].SetMaxLen(3); + IList->Edit[2].Str.Clear(); + TMyString::sFrom3Dg(EndAddr,Text); + IList->Edit[2].SetText(Text, 24); + IList->Edit[2].Show(); + + IList->Edit[3].Init(Lv.Grid.Left[0] +114, Lv.Grid.Top[0] + 138, 100,30,0,0,1,clNearBlack); + IList->EditCtlNum.Init(Lv.Grid.Left[0] +114, Lv.Grid.Top[0] + 172, 100,30,0,0,1,clNearBlack); + IList->EditUserCode.Init(Lv.Grid.Left[0] +114, Lv.Grid.Top[0] + 206, 100,30,0,0,1,clNearBlack); + RedrawCfgByte(); + + DrawFixText(); + + InitReadData(); + Check4Selected(); + +} + +void TDevVaCfg::Show() +{ + IsShow = 1; + DrawSelf(); +} + +void TDevVaCfg::Init4DrawRead() +{ + unsigned int x, y, x2, y2, w, h; + + Bound.SetBySize(0, 36, 800, 406); + Content.Set(Bound.Left +3, Bound.Top+3 + 30, Bound.Right-4, Bound.Bottom -4); + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clNearWhite); + + #define GS 24 + #define TS 96 + + unsigned int aLeft, aTop, aTopR; + + aLeft = Content.Left + 10; + aTop = Content.Top +4; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "回路"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Loop"); + TextDigitRender2_24(aLeft +50, aTop, clNearBlack, clNearWhite, Path0); + + aLeft = Content.Left + 120; + aTop = Content.Top +4; + aTopR = Content.Top +6; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clSilver); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "非输出"); + else TextRender_string24(aLeft,aTop,clNearBlack, "Others"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clRed); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "未读"); + else TextRender_string24(aLeft,aTop,clNearBlack, "UnRead"); + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clBlue); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "声光"); + else TextRender_string24(aLeft,aTop,clNearBlack, "V+S"); + aLeft += TS - 24; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clDeepGreen); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "声"); + else TextRender_string24(aLeft,aTop,clNearBlack, "S "); + aLeft += TS -24; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clPurple); + aLeft += GS; + if(LanguageEnCn==0)TextRender_string24(aLeft,aTop,clNearBlack, "光"); + else TextRender_string24(aLeft,aTop,clNearBlack, "V "); + aLeft += TS -24; +} + +void TDevVaCfg::Draw4Read() +{ + int a, x,y,t,b; + unsigned char p = Path0-1; + unsigned int tClr; + RectFillRender(Content.Left, Content.Top + 30, Content.Right, Content.Bottom, clNearWhite); + if(p>dPORT_MAX_COUNT)return; + if(IList == nullptr)return; + for(a=0; aReadWriteData.D8[a+1]){ + if(IList->RealtimeData.Data[1][a+1] == 0){ + //Is Setting Check + tClr = clBlue; + }else + if(IList->RealtimeData.Data[1][a+1] == 1){ + //Is Setting Check + tClr = clDeepGreen; + }else + if(IList->RealtimeData.Data[1][a+1] == 2){ + //Is Setting Check + tClr = clPurple; + }else{ + //Is Not Setting Check + tClr = clRed; + } + }else{ + //Still wait for Done This Addr + tClr = clRed; + } + RectFillRender( svGrid1X[x], t, svGrid1X2[x], b, tClr); + }else{ + RectFillRender( svGrid1X[x], t, svGrid1X2[x], b, clSilver); + } + TMyString::sFrom3Dg(a+1, Text); + lcd_draw_str_8x16( svGrid1X[x]+6, t+5, clNearWhite, Text); + } + } +} + +void TDevVaCfg::FullRedraw(int Prm) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Show(); + IList->Edit[1].Show(); + IList->Edit[2].Show(); + RedrawCfgByte(); + + DrawFixText(); + + Check4Selected(); + if(State != RangeReading){ + DrawWriteResult(); + } + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); +} + +void TDevVaCfg::PermissionCmdReturnDraw() +{ + FullRedraw(1); +} + +void TDevVaCfg::RedrawCfgByte() +{ + if(IList == nullptr)return; + if(LanguageEnCn==0){ + if(WritingCfBytes.IsLink) + IList->Edit[3].SetText("联动", 24); + else + IList->Edit[3].SetText("不联动", 24); + + if(WritingCfBytes.VnA ==0) + IList->EditCtlNum.SetText("声光", 24); + else + if(WritingCfBytes.VnA ==1) + IList->EditCtlNum.SetText("声", 24); + else + if(WritingCfBytes.VnA ==2) + IList->EditCtlNum.SetText("光", 24); + else + IList->EditCtlNum.SetText("未定义", 24); + + if(WritingCfBytes.Tone < 10) + IList->EditUserCode.Str.FromInt(WritingCfBytes.Tone); + else + IList->EditUserCode.SetText("未定义", 24); + }else{ + if(WritingCfBytes.IsLink) + IList->Edit[3].SetText("Link ", 24); + else + IList->Edit[3].SetText("Not Link", 24); + + if(WritingCfBytes.VnA ==0) + IList->EditCtlNum.SetText("S+V", 24); + else + if(WritingCfBytes.VnA ==1) + IList->EditCtlNum.SetText("S Only", 24); + else + if(WritingCfBytes.VnA ==2) + IList->EditCtlNum.SetText("V Only", 24); + else + IList->EditCtlNum.SetText("Un def", 24); + + if(WritingCfBytes.Tone < 10) + IList->EditUserCode.Str.FromInt(WritingCfBytes.Tone); + else + IList->EditUserCode.SetText("Un def", 24); + } + + IList->Edit[3].Show(); + IList->EditCtlNum.Show(); + IList->EditUserCode.Show(); +} + +void TDevVaCfg::DrawWriteResult() +{ + if(LanguageEnCn==0){ + if(WriteResult == 0){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, " "); + }else + if(WriteResult == 1){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "写入成功 "); + }else + if(WriteResult == 2){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "写入失败 "); + }else + if(WriteResult == 3){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "正在写入 "); + } + }else{ + if(WriteResult == 0){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, " "); + }else + if(WriteResult == 1){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Wrote OK "); + }else + if(WriteResult == 2){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Failed To Write"); + }else + if(WriteResult == 3){ + TextRender_string24(TipPoint.x, TipPoint.y, clNearWhite, ContentColor, "Writing "); + } + } +} + +void TDevVaCfg::DrawWriteTime() +{ + unsigned int tClr; + if(IsSelfChecking != 0)return; + if(RunData.WaitTick < 300)tClr = clNearWhite; else tClr = clRed; + if(LanguageEnCn==0)TextRender_string24(TipPoint.x+220, TipPoint.y, clNearWhite, ContentColor, "用时: "); + else TextRender_string24(TipPoint.x+220, TipPoint.y, clNearWhite, ContentColor, "Time: "); + TextDigitRender3_24(TipPoint.x+220+60, TipPoint.y, tClr, ContentColor, RunData.WaitTick); +} + +void TDevVaCfg::DrawWriteResult(unsigned char aResult) +{ + WriteResult = aResult; + DrawWriteResult(); +} + +void TDevVaCfg::InitReadData() +{ + int i; + RunData.WaitTick =0; + RunData.RecReadUpData = 0; + if(IList == nullptr)return; + IList->ReadWriteData.Reset(); + IList->RealtimeData.Reset(); +} + +void TDevVaCfg::InitWriteData() +{ + RunData.WaitTick =0; + RunData.RecWriteOk =0; +} + +void TDevVaCfg::CheckHostCount() +{ + int x,y; + Count.Total =0; + for(x=0; xEdit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 1: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + case 2: + IList->Edit[2].Selected = 0; + IList->Edit[2].Show(); + break; + case 3: + IList->Edit[3].Selected = 0; + IList->Edit[3].Show(); + break; + case 4: + IList->EditCtlNum.Selected = 0; + IList->EditCtlNum.Show(); + break; + case 5: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 6: + if(LanguageEnCn==0)tText="开始查询"; else tText=" Query "; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +40, Lv.Grid.Top[1] + 42, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 7: + if(LanguageEnCn==0)tText="保存配置"; else tText=" Config "; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +180, Lv.Grid.Top[1] + 42, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +void TDevVaCfg::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 1: + IList->Edit[1].Selected = 1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + case 2: + IList->Edit[2].Selected = 1; + IList->Edit[2].SetPstTail(); + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + break; + case 3: + IList->Edit[3].Selected = 1; + IList->Edit[3].Show(); + break; + case 4: + IList->EditCtlNum.Selected = 1; + IList->EditCtlNum.Show(); + break; + case 5: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.Show(); + break; + case 6: + if(LanguageEnCn==0)tText="开始查询"; else tText=" Query "; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +40, Lv.Grid.Top[1] + 42, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 7: + if(LanguageEnCn==0)tText="保存配置"; else tText=" Config "; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +180, Lv.Grid.Top[1] + 42, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + } +} + +void TDevVaCfg::PushInnerCanData(unsigned char aCmd, unsigned char *pBuf) +{ + if(aCmd == cmQueryStaticDataAddrSegment){ + //Read + if(IList == nullptr)return; + if(State == RangeReading){ + if( (pBuf[1] == Path0) && (pBuf[2] >= StartAddr) && (pBuf[2] <= EndAddr) && (pBuf[3] == 0x07) ){ + IList->ReadWriteData.D8[pBuf[2]] =1; + IList->RealtimeData.Data[0][pBuf[2]] = pBuf[4]; + IList->RealtimeData.Data[1][pBuf[2]] = pBuf[5]; + IList->RealtimeData.Data[2][pBuf[2]] = pBuf[6]; + RunData.RecReadUpData = 1; + } + } + }else + if(aCmd == cmSetConfigAddrSegment){ + //Write + if(State == RangeWriting){ + if( (pBuf[1] == Path0) && (pBuf[2] == StartAddr) && (pBuf[3] == EndAddr) && (pBuf[4] == 0x07) && + (pBuf[5] == WritingCfBytes.IsLink) && (pBuf[6] == WritingCfBytes.VnA) && (pBuf[7] == WritingCfBytes.Tone) ){ + RunData.RecWriteOk = 1; + } + } + } +} + +void TDevVaCfg::SendCmdRead(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =5; + + aIde.BitF.Cmd = cmQueryStaticDataAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = aPort; + Data[2] = aStartAddr; + Data[3] = aEndAddr; + Data[4] = 0x07; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TDevVaCfg::SendCmdReadAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =5; + + aIde.BitF.Cmd = cmQueryStaticDataAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 255; + Data[2] = 0; + Data[3] = 0; + Data[4] = 0; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TDevVaCfg::SendCmdWrite(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr, unsigned char aLink, unsigned char aVnA, unsigned char aTone) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =8; + + aIde.BitF.Cmd = cmSetConfigAddrSegment; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = aPort; + Data[2] = aStartAddr; + Data[3] = aEndAddr; + Data[4] = 0x07; + Data[5] = aLink; + Data[6] = aVnA; + Data[7] = aTone; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + + +TGuiMsgReturn TDevVaCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char tCtlNum, aCc, Ow, Err; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + } + + if(State == RangeReading){ + switch(aKey){ + case VK_RETURN: + State = Idle; + SendCmdReadAbort(); + FullRedraw(1); + break; + } + }else + if(State == RangeWriting){ + switch(aKey){ + case VK_RETURN: + State =Idle; + IsShow = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Tag.Inx ==0){ + IList->Edit[0].KeyIn(aKey); + aCc = IList->Edit[0].Str.ToInteger(); + if( (aCc == 0) || (aCc > dPORT_MAX_COUNT) ){ + IList->Edit[0].SelectedColor = clRed; + }else{ + IList->Edit[0].SelectedColor = clBlue; + } + Path0 = aCc; + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + }else + if(Tag.Inx ==1){ + IList->Edit[1].KeyIn(aKey); + aCc = IList->Edit[1].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[1].SelectedColor = clRed; + }else{ + IList->Edit[1].SelectedColor = clBlue; + } + StartAddr = aCc; + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + }else + if(Tag.Inx ==2){ + IList->Edit[2].KeyIn(aKey); + aCc = IList->Edit[2].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[2].SelectedColor = clRed; + }else{ + IList->Edit[2].SelectedColor = clBlue; + } + EndAddr = aCc; + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + }else + if(Tag.Inx ==3){ + WritingCfBytes.IsLink = WritingCfBytes.IsLink ? 0: 1; + WritingCfBytes.IsLink =1; + RedrawCfgByte(); + }else + if(Tag.Inx ==4){ + if(WritingCfBytes.VnA <2)WritingCfBytes.VnA++; + else WritingCfBytes.VnA =0; + RedrawCfgByte(); + }else + if(Tag.Inx ==5){ + if(WritingCfBytes.Tone <9)WritingCfBytes.Tone++; + else WritingCfBytes.Tone =0; + WritingCfBytes.Tone =0; + RedrawCfgByte(); + }/*else + if(Tag.Inx ==6){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx ==7){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }*/ + break; + case VK_UP: + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx <6){ + //if(Tag.Inx <7){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + if(Tag.Inx ==3){ + WritingCfBytes.IsLink = WritingCfBytes.IsLink ? 0: 1; + WritingCfBytes.IsLink =1; + RedrawCfgByte(); + }else + if(Tag.Inx ==4){ + if(WritingCfBytes.VnA <2)WritingCfBytes.VnA++; + else WritingCfBytes.VnA =0; + RedrawCfgByte(); + }else + if(Tag.Inx ==5){ + if(WritingCfBytes.Tone <9)WritingCfBytes.Tone++; + else WritingCfBytes.Tone =0; + WritingCfBytes.Tone =0; + RedrawCfgByte(); + } + break; + case dfKEY_QUERY: + + break; + case VK_EXECUTE: + if(Tag.Inx == 6){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + PermissionCmd = 0; + PermissionCmdGO(); + } + } + }else + if(Tag.Inx == 7){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[0] +300, Lv.Grid.Top[0] + 66, 400, 140, 3); + } + } + } + } + break; + case VK_RETURN: + State =Idle; + IsShow = 0; + if(State == RangeReading)SendCmdReadAbort(); + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TDevVaCfg::PermissionCmdGO() +{ + if(PermissionCmd == 0){ + //Go Action + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + InitReadData(); + State = RangeReading; + SendCmdRead(Path0, StartAddr, EndAddr); + Init4DrawRead(); + Draw4Read(); + } + } + }else + if(PermissionCmd == 1){ + if(Path0 && StartAddr && EndAddr){ + if( (Path0 < dPORT_MAX_COUNT) && (StartAddr >0) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) && (StartAddr <= EndAddr)){ + DrawWriteResult(3); + State = RangeWriting; + RunData.WaitTick = 0; + SendCmdWrite(Path0, StartAddr, EndAddr, WritingCfBytes.IsLink, WritingCfBytes.VnA, WritingCfBytes.Tone); + } + } + } +} + +void TDevVaCfg::Task1000Ms() +{ + if(IsShow == 0)return; + if(State == RangeReading){ + if(RunData.WaitTick<120){ + RunData.WaitTick++; + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + } + if(RunData.RecReadUpData){ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + RunData.RecReadUpData = 0; + Draw4Read(); + } + } + }else + if(State == RangeWriting){ + RunData.WaitTick++; + DrawWriteTime(); + if(RunData.WaitTick <360){ + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + if(RunData.RecWriteOk){ + //Write Ok + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawWriteResult(1); + }else{ + WriteResult = 1; + } + State = Idle; + } + }else{ + //Write Fail + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawWriteResult(2); + }else{ + WriteResult = 2; + } + State = Idle; + } + } +} + +int TDevVaCfg::ExtRequst(unsigned char Prm) +{ + IsShow = 0; + if(State == RangeReading)SendCmdReadAbort(); + State =Idle; + return 0; +} + diff --git a/MyCode/Gui/DevVaCfg.h b/MyCode/Gui/DevVaCfg.h new file mode 100644 index 0000000..bb60e7b --- /dev/null +++ b/MyCode/Gui/DevVaCfg.h @@ -0,0 +1,183 @@ +#ifndef DEVVACFG_H_ +#define DEVVACFG_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" + + +class TDevVaCfg{ + public: + static constexpr unsigned short hList[12] = {252,78,78,28, 26,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 220, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 72, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1 + 72 -1, + }; + static constexpr TPoint TipPoint ={ + .x = 16, + .y = (36 + 32 +2) + (2 + hList[0]) + hList[1] + 6, + }; + typedef enum{ + Idle =0, + RangeReading =1, + RangeWriting + }TState; + public: + class TItemList *IList; + void (*KeepOnMeJustEnter)(void); + void (*KeepUiOnMe)(void); + TRect Bound; + TRect Content; + unsigned char Path0; + unsigned char StartAddr; + unsigned char EndAddr; + unsigned char Dump0; + struct{ + unsigned char IsLink; + unsigned char VnA; + unsigned char Tone; + unsigned char Dump; + }WritingCfBytes; + + struct{ + unsigned int Port; + unsigned int Total; + }Count; + + struct{ + unsigned int WaitTick; + unsigned char RecReadUpData; + unsigned char RecWriteOk; + unsigned char Dump0; + unsigned char Dump1; + }RunData; + TState State; + + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + void Reset(){ + Inx = 0; + InxMin = 0; + InxMax =2; + } + }Tag; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char IsShow; + unsigned char WriteResult; + + unsigned int fAddr; + + unsigned char Data[12]; + char Text[12]; + + public: + TDevVaCfg(){ + IsShow = 0; + State = Idle; + }; + void Init(); + void RenderBackGround(void); + + void DrawSelf(void); + void Show(); + void FullRedraw(int Prm); + void RedrawCfgByte(); + void Init4DrawRead(); + void Draw4Read(); + void DrawFixText(); + + void DrawWriteTime(); + void DrawWriteResult(); + void DrawWriteResult(unsigned char aResult); + + void DelayMs(unsigned int aMs); + + void CheckHostCount(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void ClearSelected(void); + void Check4Selected(); + + void InitReadData(); + void InitWriteData(); + void PushInnerCanData(unsigned char aCmd, unsigned char *pBuf); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void SendCmdRead(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr); + void SendCmdReadAbort(); + void SendCmdWrite(unsigned char aPort, unsigned char aStartAddr, unsigned char aEndAddr, unsigned char aLink, unsigned char aVnA, unsigned char aTone); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); +}; + + +#endif diff --git a/MyCode/Gui/DeviceDymPrm.cpp b/MyCode/Gui/DeviceDymPrm.cpp new file mode 100644 index 0000000..61279a5 --- /dev/null +++ b/MyCode/Gui/DeviceDymPrm.cpp @@ -0,0 +1,1164 @@ +#include "DeviceDymPrm.h" +#include "gvalue.h" +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "RuntimeData2.h" +#include "Runtime.h" +#include "Gui.h" + +#define dDdpLvLineCount 10 +#define TextTopOffSet 6 + +const char cType[12] = {" 类型"}; +const char cIndex[12] = {"编号"}; + +const char cCarry[12] = {"搭载"}; +const char cPLoad[12] = {"已登记"}; +const char cVoltage[12] = {"电压"}; +const char cCurrent[12] = {"电流"}; +const char cDescp[12] = {"描述"}; + +const char cUserCode[12] = {"用户码"}; +const char cAddr[12] = {"地址"}; +const char cPrm1[12] = {"参数1"}; +const char cPrm2[12] = {"参数2"}; +const char cPrm3[12] = {"参数3"}; +const char cPrm4[12] = {"参数4"}; + +void TDevDymPrm::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX +x1, OwnerY +y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top +3; + Width = aW-7; + Height = aH-7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right-20, Bottom); + VScrollBarBox.Set(Right-20 +1, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + //SetFontSize(9); + + RootItems.Count=0; + EpItems.Count=0; + RootItems.SelectedIndex=0; + EpItems.SelectedIndex=0; + + Lv.ColHeight = 33; + Lv.TopIndex=0; + Lv.FixColTop = Content.Top; + Lv.FixColBottom = Lv.FixColTop + Lv.ColHeight -1; + Lv.ColTop[0] = Lv.FixColBottom + 1; + Lv.ColBottom[0] = Lv.ColTop[0] + Lv.ColHeight -1; + Lv.ColLeft[0] = 1; + Lv.ColRight[0] = Lv.ColWidth[0] +1; + for(i=1; i<12; i++){ + Lv.ColTop[i] = Lv.ColTop[i -1] + Lv.ColHeight; + Lv.ColBottom[i] = Lv.ColBottom[i-1] + Lv.ColHeight; + } + + PathX = 0; + RootItems.Selected_dType = dgTYPE_PORT; //dRootDevTypeMin; + RootItems.ActiveLineNum =0; + RootItems.TopIndex =0; + EpItems.Selected_dType = dgTYPE_SMOKE_DETECTOR_I;//dEpDevTypeMin; + EpItems.ActiveLineNum =0; + EpItems.TopIndex =0; + + FixColColor = clMedGray; + FixColTextColor = clNearWhite; + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Caption.Border.Color = clGray; + VScrollBar.Color = clFrmFace; + VScrollBar.RibbonColor = clGray; + + //PercentBar.SetColor(clBlue, clGray); + + //ClearPath(); + + Caption.Color = clMaroon; + Caption.TextColor = clNearWhite; +} + + +void TDevDymPrm::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5, int w6, int w7, int w8, int w9, int w10, int w11, int w12, int w13) +{ + //0.Image, 1,dType, 2.UserCode, 3.Id, 4.Updata, 5.Prm1, 6.Prm2, 7.Prm3, 8.Prm4 + unsigned int i; + Lv.ColWidth[0] = w0; + Lv.ColWidth[1] = w1; + Lv.ColWidth[2] = w2; + Lv.ColWidth[3] = w3; + Lv.ColWidth[4] = w4; + Lv.ColWidth[5] = w5; + Lv.ColWidth[6] = w6; + Lv.ColWidth[7] = w7; + Lv.ColWidth[8] = w8; + Lv.ColWidth[9] = w9; + Lv.ColWidth[10] = w10; + Lv.ColWidth[11] = w11; + Lv.ColWidth[12] = w12; + Lv.ColWidth[13] = w13; + + Lv.ColLeft[0] = Content.Left +1; + Lv.ColRight[0] = Lv.ColLeft[0] + w0; + for(i=1; i<14; i++){ + Lv.ColLeft[i] = Lv.ColRight[i-1] +1; + Lv.ColRight[i] = Lv.ColLeft[i] + Lv.ColWidth[i]; + } +} + +void TDevDymPrm::SetFontSize(int size) +{ + FontSize = size; + FontHeight = GetFontHeight(FontSize); +} + +void TDevDymPrm::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TDevDymPrm::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TDevDymPrm::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + //Fill Rect Box + RenderContent(); +} + +void TDevDymPrm::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; + unsigned int aTopIndex, aSelectedIndex, aCol; + if(PathX == 0){ + aTopIndex = RootItems.TopIndex; + aSelectedIndex = RootItems.SelectedIndex; + }else{ + aTopIndex = EpItems.TopIndex; + aSelectedIndex = EpItems.SelectedIndex; + } + aCol = aSelectedIndex - aTopIndex; + + RectFillRender(Content.Left, Lv.FixColTop, Content.Right, Lv.FixColBottom, FixColColor); + + y = Lv.FixColBottom + 1; + for(x=0; x Content.Bottom)y2 = Content.Bottom; + if(x == aCol){ + RectFillRender(Content.Left, y, Content.Right, y2, clBlue); + }else{ + if(x & 1){ + RectFillRender(Content.Left, y, Content.Right, y2, OddColor); + }else{ + RectFillRender(Content.Left, y, Content.Right, y2, Color); + } + } + y = y2 + 1; + if(y>Content.Bottom)break; + } +} + +void TDevDymPrm::DrawCaption(void) +{ + Caption.Show(); +} + +void TDevDymPrm::DrawVertScrollBar(void) +{ + int RibbonHeight; + int RibbonBottom; + int RibbonTop; + int UpRemain; + int DownRemain; + float f1,f2,f3,f4; + + if(EpItems.Count <= dDdpLvLineCount){ + RibbonTop = VScrollBarBox.Top+1; + RibbonBottom = VScrollBarBox.Bottom - 1; + RibbonHeight = VScrollBarBox.Height - 2; + }else{ + //get RibbonHeight + f1 = static_cast(dDdpLvLineCount); + f2 = static_cast(EpItems.Count); + f3 = static_cast(VScrollBarBox.Height); + f4 = f1/f2*f3; + RibbonHeight = static_cast(f4) ; + if(RibbonHeight > VScrollBarBox.Height) RibbonHeight = VScrollBarBox.Height; + if(RibbonHeight < 10) RibbonHeight = 10; + f2 = f4/f1; //Get One Item Height + + //get RibbonCenter + UpRemain = EpItems.TopIndex; + DownRemain = EpItems.Count - EpItems.TopIndex - dDdpLvLineCount; + if(UpRemain < DownRemain){ + f1 = UpRemain; + RibbonTop = static_cast(f1*f2) + VScrollBarBox.Top + 1; + RibbonBottom = RibbonTop + RibbonHeight; + if( RibbonBottom > (VScrollBarBox.Bottom -1) )RibbonBottom = VScrollBarBox.Bottom - 1; + }else{ + f1 = DownRemain; + RibbonBottom = VScrollBarBox.Bottom - static_cast(f1*f2); + RibbonTop = RibbonBottom - RibbonHeight; + if( RibbonTop < (VScrollBarBox.Top +1) )RibbonTop = VScrollBarBox.Top +1; + } + } + + //Draw Vert ScrollBar BackGround + RectFillRender(VScrollBarBox.Left, VScrollBarBox.Top, VScrollBarBox.Right, VScrollBarBox.Bottom, VScrollBar.Color); + //Draw Vert ScrollBar Ribbon + RectFillRender(VScrollBarBox.Left, RibbonTop, VScrollBarBox.Right, RibbonBottom, VScrollBar.RibbonColor); +} + +void TDevDymPrm::DrawRootDevList(void) +{ + int i,j, index, BGClr, TextClr, aTop; + unsigned int idx; + + switch(RootItems.Selected_dType){ + case dgTYPE_POWER_SUPPLY: + DrawPowerSpply(); + break; + case dgTYPE_BATTERY: + DrawBattery(); + break; + case dgTYPE_COMM_GRAPH: + DrawGraphCtl(); + break; + case dgTYPE_COMM_CAN: + DrawCommCan(); + break; + case dgTYPE_COMM_MULTI: + DrawCommCan(); + break; + case dgTYPE_LCD_BOARD: + DrawLcdBoard(); + break; + case dgTYPE_KEY_BOARD_1: + case dgTYPE_KEY_BOARD_2: + DrawKeyBoard(); + break; + case dgTYPE_MOTHER_BOARD: + DrawMotherBoard(); + break; + case dgTYPE_HAND_CTL: + DrawHandPad(); + break; + case dgTYPE_DIRECT_CTL: + DrawDirectCtl(); + break; + case dgTYPE_PORT: + DrawPort(); + break; + } +} + +void TDevDymPrm::DrawEpDevList(void) +{ + switch(EpItems.Selected_dType){ + case dgTYPE_SMOKE_DETECTOR_I: + case dgTYPE_SMOKE_DETECTOR_II : + DrawSmokeDet(); //Req 1, IR Raw Data; 2, Blue Raw Data; + break; + case dgTYPE_TEMPE_DETECTOR_I: + DrawTempeDet(); //Req 1, Tempe in Celsius degree; 2, Raw Data; + break; + case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + DrawSmokeTempeDet(); //Req 1, IR Raw Data; 2, Blue Raw Data; 3, Tempe in Celsius degree; 4, Raw Data; + break; + case dgTYPE_HAND_REPORT : + + break; + case dgTYPE_IN_MODULE : + + break; + case dgTYPE_OUT_MODULE: + + break; + case dgTYPE_INOUT_MODULE: + + break; + case dgTYPE_BUS_BROKE: + + break; + + case dgTYPE_DISPLAY_PAD_I: + + break; + + } +} + + +void TDevDymPrm::DrawList(void) +{ + RenderContent(); + DrawVertScrollBar(); + if(PathX == 0){ + DrawRootDevList(); + }else + if(PathX == 1){ + DrawEpDevList(); + } +} + +void TDevDymPrm::Show(void) +{ + DrawSelf(); + DrawVertScrollBar(); + DrawList(); +} + +void TDevDymPrm::ClearPath(void) +{ + unsigned int i; + for(i=0;i<256;i++){ + RootItems.Dev[i] = nullptr; + EpItems.Dev[i] = nullptr; + } + RootItems.Count = 0; + RootItems.SelectedIndex = 0; + RootItems.TopIndex = 0; + + EpItems.Count = 0; + EpItems.SelectedIndex = 0; + EpItems.TopIndex = 0; +} + +void TDevDymPrm::ClearPath1(void) +{ + unsigned int i; + for(i=0;i<256;i++){ + EpItems.Dev[i] = nullptr; + } + EpItems.Count = 0; + EpItems.SelectedIndex = 0; + EpItems.TopIndex = 0; +} + +void TDevDymPrm::LoadPath0Item(TRootDevice *pItem) +{ + if(RootItems.Count < 256){ + RootItems.Dev[RootItems.Count] = pItem; + RootItems.Count++; + } +} + +void TDevDymPrm::LoadPath1Item(TEpDevice *pItem ) +{ + if(EpItems.Count < 256){ + EpItems.Dev[EpItems.Count]= pItem; + EpItems.Count++; + } +} + + +void TDevDymPrm::LoadPath0(void) +{ + int i; + ClearPath(); + switch(RootItems.Selected_dType){ + case dgTYPE_POWER_SUPPLY: + + break; + case dgTYPE_BATTERY: + + break; + case dgTYPE_COMM_GRAPH: + + break; + case dgTYPE_COMM_CAN: + for(i=0; i dDIRECTCTL_MAX_COUNT)MainCtl.fData.Split.DirectCtlCount = dDIRECTCTL_MAX_COUNT; + for(i=0; i dPORT_MAX_COUNT ) + MainCtl.fData.Split.PortCount = dPORT_MAX_COUNT; + for(i=0; i0){ + RootItems.SelectedIndex = 0; + Lv.SelectedCol = 0; + Lv.TopIndex = 0; + } +} + +void TDevDymPrm::LoadPath1(void) +{ + TRootDevice *theRDev = nullptr; + TPort *thePort; + unsigned int i, px, ex; + + ClearPath1(); + if( RootItems.Dev[RootItems.SelectedIndex] == nullptr ) return; + theRDev = RootItems.Dev[RootItems.SelectedIndex]; + if(theRDev != nullptr){ + if(theRDev->fData.Common.dType == dgTYPE_PORT){ + px = theRDev->fData.Port.Id; + thePort = (TPort *)theRDev; + for(i=0; i< dEP_MAX_COUNT_PER_PORT; i++){ + if(Port[px].ExistTable[i] == 0xA5) + if(EpItems.Selected_dType == EpDev[px][i].fData.Split.dType) + LoadPath1Item(&EpDev[px][ex]); + } + + TMyString::sFromStr("回路",Caption.Text ); + TMyString::sAddOn3Dg(theRDev->fData.Common.Id, Caption.Text); + TMyString::sAddOnStr(" ", Caption.Text); + + TMyString::sAddOnStr(StrType[EpItems.Selected_dType], Caption.Text); + TMyString::sAddOnStr(" ", Caption.Text); + TMyString::sAddOn3Dg(EpItems.Count, Caption.Text); + Caption.FullRedraw(); + if(EpItems.Count >0) { + EpItems.SelectedIndex = 0; + Lv.SelectedCol = 0; + Lv.TopIndex = 0; + } + }else{ + + } + } + + switch(EpItems.Selected_dType){ + case dgTYPE_SMOKE_DETECTOR_I: + case dgTYPE_SMOKE_DETECTOR_II : + case dgTYPE_TEMPE_DETECTOR_I: + case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + case dgTYPE_HAND_REPORT : + case dgTYPE_IN_MODULE : + case dgTYPE_OUT_MODULE: + case dgTYPE_INOUT_MODULE : + case dgTYPE_BUS_BROKE: + case dgTYPE_DISPLAY_PAD_I: + break; + } +} + +void TDevDymPrm::SetEditMode(unsigned int aMode) +{ + +} + +void TDevDymPrm::SendReqCmd(void) +{ + FCBusTx.WriteOneMsg(CmdBuf, 17); +} + +void TDevDymPrm::DrawPowerSpply(void) +{ + unsigned int i,j, idx, aTop; + SetListColWidth(30,80,48,120,80,60,60,60,60,1,1,1,1,1); + aTop = Lv.FixColTop ; + TextRender_string24(Lv.ColLeft[1],aTop,TextColor, cUserCode); + TextRender_string24(Lv.ColLeft[2],aTop,TextColor, cIndex); + TextRender_string24(Lv.ColLeft[3],aTop,TextColor, cType); + TextRender_string24(Lv.ColLeft[4],aTop,TextColor, "标记"); + TextRender_string24(Lv.ColLeft[5],aTop,TextColor, "更新"); + TextRender_string24(Lv.ColLeft[6],aTop,TextColor, "电压"); + TextRender_string24(Lv.ColLeft[7],aTop,TextColor, "电流"); + TextRender_string24(Lv.ColLeft[8],aTop,TextColor, "功率"); + + if(RootItems.Count < 1)return; + + idx = RootItems.TopIndex; + aTop = Lv.FixColBottom +1; + for(i=0; ifData.Common.dType, Lv.ColLeft[0], aTop, Content.Right, Content.Bottom); + if(Lv.SelectedCol == i){ + aClr = clNearWhite; + aClr2 = clGreen; + }else{ + aClr = clNearBlack; + aClr2 = clBlue; + } + RootItems.Dev[idx]->PrintProperty(&Str[0],&Str[1],&Str[2]); + TextRender_string24(Lv.ColLeft[1], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[2], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[3], aTop, aClr, Str[2].Text); + + TextRender_string24(Lv.ColLeft[4], aTop, aClr, "Tag0"); + + PercentBar.SetSize(Lv.ColLeft[5] +1, aTop +1, Lv.ColRight[5] -1, aTop +26); + PercentBar.PercentRender(DymPrm.UpdataSeconed[idx],256, DymPrm.GotUpdata[idx]); + + RootItems.Dev[idx]->PrintDynamicsData(&Str[0],&Str[1],&Str[2],&Str[3],&Str[4],&Str[5],&Str[6],&Str[7]); + TextRender_string24(Lv.ColLeft[6], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[7], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[8], aTop, aClr2, Str[2].Text); + } + } + idx++; + aTop = aTop + Lv.ColHeight; + } +} + +void TDevDymPrm::DrawDirectCtl(void) +{ + unsigned int i,j, idx, aTop, aClr, aClr2; + SetListColWidth(30,80,48,120,60,60,80,80,160,1,1,1,1,1); + aTop = Lv.FixColTop ; + TextRender_string24(Lv.ColLeft[1],aTop,TextColor, cUserCode); + TextRender_string24(Lv.ColLeft[2],aTop,TextColor, cIndex); + TextRender_string24(Lv.ColLeft[3],aTop,TextColor, cType); + TextRender_string24(Lv.ColLeft[4],aTop,TextColor, "标记"); + TextRender_string24(Lv.ColLeft[5],aTop,TextColor, "更新"); + TextRender_string24(Lv.ColLeft[6],aTop,TextColor, "电压"); + TextRender_string24(Lv.ColLeft[7],aTop,TextColor, "电流"); + TextRender_string24(Lv.ColLeft[8],aTop,TextColor, "已启动"); + if(RootItems.Count < 1)return; + idx = RootItems.TopIndex; + aTop = Lv.FixColBottom +1; + for(i=0; ifData.Common.dType, Lv.ColLeft[0], aTop, Content.Right, Content.Bottom); + if(Lv.SelectedCol == i){ + aClr = clNearWhite; + aClr2 = clGreen; + }else{ + aClr = clNearBlack; + aClr2 = clBlue; + } + RootItems.Dev[idx]->PrintProperty(&Str[0],&Str[1],&Str[2]); + TextRender_string24(Lv.ColLeft[1], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[2], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[3], aTop, aClr, Str[2].Text); + + TextRender_string24(Lv.ColLeft[4], aTop, aClr, "Tag0"); + + PercentBar.SetSize(Lv.ColLeft[5] +1, aTop +1, Lv.ColRight[5] -1, aTop +26); + PercentBar.PercentRender(DymPrm.UpdataSeconed[idx],256, DymPrm.GotUpdata[idx]); + + RootItems.Dev[idx]->PrintDynamicsData(&Str[0],&Str[1],&Str[2],&Str[3],&Str[4],&Str[5],&Str[6],&Str[7]); + TextRender_string24(Lv.ColLeft[6], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[7], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[8], aTop, aClr2, Str[2].Text); + } + } + idx++; + aTop = aTop + Lv.ColHeight; + } +} + +void TDevDymPrm::DrawPort(void) +{ + unsigned int i,j, idx, aTop, aClr, aClr2; + SetListColWidth(30,80,48,120,80,60,60,60,80,60,1,1,1,1); + aTop = Lv.FixColTop ; + TextRender_string24(Lv.ColLeft[1],aTop,TextColor, cUserCode); + TextRender_string24(Lv.ColLeft[2],aTop,TextColor, cIndex); + TextRender_string24(Lv.ColLeft[3],aTop,TextColor, cType); + TextRender_string24(Lv.ColLeft[4],aTop,TextColor, "标记"); + TextRender_string24(Lv.ColLeft[5],aTop,TextColor, "更新"); + TextRender_string24(Lv.ColLeft[6],aTop,TextColor, "电压"); + TextRender_string24(Lv.ColLeft[7],aTop,TextColor, "电流"); + TextRender_string24(Lv.ColLeft[8],aTop,TextColor, "已挂载"); + TextRender_string24(Lv.ColLeft[9],aTop,TextColor, "温度"); + if(RootItems.Count < 1)return; + + idx = RootItems.TopIndex; + aTop = Lv.FixColBottom +1; + for(i=0; ifData.Common.dType, Lv.ColLeft[0], aTop, Content.Right, Content.Bottom); + if(Lv.SelectedCol == i){ + aClr = clNearWhite; + aClr2 = clGreen; + }else{ + aClr = clNearBlack; + aClr2 = clBlue; + } + RootItems.Dev[idx]->PrintProperty(&Str[0],&Str[1],&Str[2]); + TextRender_string24(Lv.ColLeft[1], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[2], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[3], aTop, aClr, Str[2].Text); + + TextRender_string24(Lv.ColLeft[4], aTop, aClr, "Tag0"); + + PercentBar.SetSize(Lv.ColLeft[5] +1, aTop +1, Lv.ColRight[5] -1, aTop +26); + PercentBar.PercentRender(DymPrm.UpdataSeconed[idx],256, DymPrm.GotUpdata[idx]); + + RootItems.Dev[idx]->PrintDynamicsData(&Str[0],&Str[1],&Str[2],&Str[3],&Str[4],&Str[5],&Str[6],&Str[7]); + TextRender_string24(Lv.ColLeft[6], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[7], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[8], aTop, aClr2, Str[2].Text); + TextRender_string24(Lv.ColLeft[9], aTop, aClr2, Str[3].Text); + } + } + idx++; + aTop = aTop + Lv.ColHeight; + } +} + +void TDevDymPrm::DrawSmokeDet(void) +{ + //0.Image, 1,dType, 2.UserCode, 3.Id, 4.Updata, 5.Prm1, 6.Prm2, 7.Prm3, 8.Prm4 + unsigned int i,j, idx, aTop, aClr, aClr2; + SetListColWidth(30,80,48,120,60,60,60,120,120,1,1,1,1,1); + aTop = Lv.FixColTop ; + if(1){ + TextRender_string24(Lv.ColLeft[1],aTop,TextColor, cUserCode); + TextRender_string24(Lv.ColLeft[2],aTop,TextColor, cIndex); + TextRender_string24(Lv.ColLeft[3],aTop,TextColor, cType); + TextRender_string24(Lv.ColLeft[4],aTop,TextColor, "灵敏"); + TextRender_string24(Lv.ColLeft[5],aTop,TextColor, "污染"); + TextRender_string24(Lv.ColLeft[6],aTop,TextColor, "更新"); + TextRender_string24(Lv.ColLeft[7],aTop,TextColor, "红外值"); + TextRender_string24(Lv.ColLeft[8],aTop,TextColor, "蓝光值"); + if(EpItems.Count < 1)return; + + idx = EpItems.TopIndex; + aTop = Lv.FixColBottom +1; + for(i=0; ifData.Split.dType, Lv.ColLeft[0], aTop, Content.Right, Content.Bottom); + if(Lv.SelectedCol == i){ + aClr = clNearWhite; + aClr2 = clGreen; + }else{ + aClr = clNearBlack; + aClr2 = clBlue; + } + EpItems.Dev[idx]->PrintProperty(&Str[0],&Str[1],&Str[2]); + TextRender_string24(Lv.ColLeft[1], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[2], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[3], aTop, aClr, Str[2].Text); + + EpItems.Dev[idx]->PrintAttribute(&Str[3],&Str[4],&Str[5],&Str[6]); + TextRender_string24(Lv.ColLeft[4], aTop, aClr, Str[3].Text); + TextRender_string24(Lv.ColLeft[5], aTop, aClr, Str[6].Text); + + PercentBar.SetSize(Lv.ColLeft[6] +1, aTop +1, Lv.ColRight[6] -1, aTop +26); + PercentBar.PercentRender(DymPrm.UpdataSeconed[idx],256, DymPrm.GotUpdata[idx]); + + Str[7].FromUInt4Dg(DymPrm.Value[idx][0]); // IR Value + Str[8].FromUInt4Dg(DymPrm.Value[idx][1]); // Blue Value + TextRender_string24(Lv.ColLeft[7], aTop, aClr2, Str[7].Text); + TextRender_string24(Lv.ColLeft[8], aTop, aClr2, Str[8].Text); + } + } + idx++; + aTop = aTop + Lv.ColHeight; + } + } +} + +void TDevDymPrm::DrawTempeDet(void) +{ + //0.Image, 1,dType, 2.UserCode, 3.Id, 4.Updata, 5.Prm1, 6.Prm2, 7.Prm3, 8.Prm4 + unsigned int i,j, idx, aTop, aClr,aClr2;; + SetListColWidth(30,80,48,120,80,80,60,100,100,1,1,1,1,1); + aTop = Lv.FixColTop ; + if(1){ + TextRender_string24(Lv.ColLeft[1],aTop,TextColor, cUserCode); + TextRender_string24(Lv.ColLeft[2],aTop,TextColor, cIndex); + TextRender_string24(Lv.ColLeft[3],aTop,TextColor, cType); + TextRender_string24(Lv.ColLeft[4],aTop,TextColor, "报警值"); + TextRender_string24(Lv.ColLeft[5],aTop,TextColor, "时间值"); + TextRender_string24(Lv.ColLeft[6],aTop,TextColor, "更新"); + TextRender_string24(Lv.ColLeft[7],aTop,TextColor, "温度值"); + TextRender_string24(Lv.ColLeft[8],aTop,TextColor, "模拟值"); + if(EpItems.Count < 1)return; + idx = Lv.TopIndex; + aTop = Lv.FixColBottom + 1; + for(i=0; ifData.Split.dType, Lv.ColLeft[0], aTop, Content.Right, Content.Bottom); + if(Lv.SelectedCol == i){ + aClr = clNearWhite; + aClr2 = clGreen; + }else{ + aClr = clNearBlack; + aClr2 = clBlue; + } + + EpItems.Dev[idx]->PrintProperty(&Str[0],&Str[1],&Str[2]); + TextRender_string24(Lv.ColLeft[1], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[2], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[3], aTop, aClr, Str[2].Text); + + EpItems.Dev[idx]->PrintAttribute(&Str[3],&Str[4],&Str[5],&Str[6]); + TextRender_string24(Lv.ColLeft[4], aTop, aClr, Str[3].Text); + TextRender_string24(Lv.ColLeft[5], aTop, aClr, Str[5].Text); + + PercentBar.SetSize(Lv.ColLeft[6] +1, aTop +1, Lv.ColRight[6] -1, aTop +26); + PercentBar.PercentRender(DymPrm.UpdataSeconed[idx],256, DymPrm.GotUpdata[idx]); + + Str[7].FromUInt4Dg(DymPrm.Value[idx][0]); // Deg Value + Str[8].FromUInt4Dg(DymPrm.Value[idx][1]); // Raw Data Value + TextRender_string24(Lv.ColLeft[7], aTop, aClr2, Str[7].Text); + TextRender_string24(Lv.ColLeft[8], aTop, aClr2, Str[8].Text); + } + } + idx++; + aTop = aTop + Lv.ColHeight; + } + } +} + +void TDevDymPrm::DrawSmokeTempeDet(void) +{ + //0.Image, 1,dType, 2.UserCode, 3.Id, 4.Updata, 5.Prm1, 6.Prm2, 7.Prm3, 8.Prm4 + unsigned int i,j, idx, aTop, aClr,aClr2; + SetListColWidth(30,80,48,120,60,60,60,60,60,60,60,1,1,1); + aTop = Lv.FixColTop ; + if(1){ + TextRender_string24(Lv.ColLeft[1],aTop,TextColor, cUserCode); + TextRender_string24(Lv.ColLeft[2],aTop,TextColor, cIndex); + TextRender_string24(Lv.ColLeft[3],aTop,TextColor, cType); + + TextRender_string24(Lv.ColLeft[4],aTop,TextColor, "灵敏"); + TextRender_string24(Lv.ColLeft[5],aTop,TextColor, "报警"); + TextRender_string24(Lv.ColLeft[6],aTop,TextColor, "更新"); + TextRender_string24(Lv.ColLeft[7],aTop,TextColor, "红外"); + TextRender_string24(Lv.ColLeft[8],aTop,TextColor, "蓝光"); + TextRender_string24(Lv.ColLeft[9],aTop,TextColor, "温度"); + TextRender_string24(Lv.ColLeft[10],aTop,TextColor, "模拟"); + if(EpItems.Count < 1)return; + idx = EpItems.TopIndex; + aTop = Lv.FixColBottom +1; + for(i=0; ifData.Split.dType, Lv.ColLeft[0], aTop, Content.Right, Content.Bottom); + if(Lv.SelectedCol == i){ + aClr = clNearWhite; + aClr2 = clGreen; + }else{ + aClr = clNearBlack; + aClr2 = clBlue; + } + EpItems.Dev[idx]->PrintProperty(&Str[0],&Str[1],&Str[2]); + TextRender_string24(Lv.ColLeft[1], aTop, aClr, Str[0].Text); + TextRender_string24(Lv.ColLeft[2], aTop, aClr, Str[1].Text); + TextRender_string24(Lv.ColLeft[3], aTop, aClr, Str[2].Text); + + EpItems.Dev[idx]->PrintAttribute(&Str[3],&Str[4],&Str[5],&Str[6]); + TextRender_string24(Lv.ColLeft[4], aTop, aClr, Str[3].Text); + TextRender_string24(Lv.ColLeft[5], aTop, aClr, Str[5].Text); + + PercentBar.SetSize(Lv.ColLeft[6] +1, aTop +1, Lv.ColRight[6] -1, aTop +26); + PercentBar.PercentRender(DymPrm.UpdataSeconed[idx],256, DymPrm.GotUpdata[idx]); + + Str[7].FromUInt4Dg(DymPrm.Value[idx][0]); // IR Value + Str[8].FromUInt4Dg(DymPrm.Value[idx][1]); // Blue Value + Str[9].FromUInt4Dg(DymPrm.Value[idx][2]); // Deg Value + Str[10].FromUInt4Dg(DymPrm.Value[idx][3]); // Raw Data Value + TextRender_string24(Lv.ColLeft[7], aTop, aClr2, Str[7].Text); // IR Value + TextRender_string24(Lv.ColLeft[8], aTop, aClr2, Str[8].Text); // Blue Value + TextRender_string24(Lv.ColLeft[9], aTop, aClr2, Str[9].Text); // Deg Value + TextRender_string24(Lv.ColLeft[10], aTop, aClr2, Str[10].Text); // Raw Data Value + } + } + idx++; + aTop = aTop + Lv.ColHeight; + } + } +} + + +void TDevDymPrm::SetActive(void) +{ + Active = 1; +} + +void TDevDymPrm::SetDeActive(void) +{ + Active = 0; +} + +void TDevDymPrm::TimeTickTask(void) +{ + unsigned int i; + if(Active != 1) return; + + for(i=0; i 0) DymPrm.UpdataSeconed[i]--; + } + DrawEpDevList(); +} + +void TDevDymPrm::UpChange_dType(void) +{ + if(PathX == 0){ + RootItems.Selected_dType++; + if(RootItems.Selected_dType > dRootDevTypeMax) + RootItems.Selected_dType = dRootDevTypeMin; + LoadPath0(); + }else + if(PathX == 1){ + EpItems.Selected_dType++; + if(EpItems.Selected_dType > dEpDevTypeMax) + EpItems.Selected_dType = dEpDevTypeMin; + LoadPath1(); + } + DrawList(); +} + +void TDevDymPrm::DownChange_dType(void) +{ + if(PathX == 0){ + if(RootItems.Selected_dType > dRootDevTypeMin){ + RootItems.Selected_dType--; + }else{ + RootItems.Selected_dType = dRootDevTypeMax; + } + LoadPath0(); + }else + if(PathX == 1){ + if(EpItems.Selected_dType > dEpDevTypeMin){ + EpItems.Selected_dType--; + }else{ + EpItems.Selected_dType = dEpDevTypeMax; + } + LoadPath1(); + } + DrawList(); +} + +TGuiMsgReturn TDevDymPrm::KeyIn(unsigned char aKey) +{ + int ind,i; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + if(PathX == 0){ + switch(aKey){ + //case VK_SELECT: + case VK_RIGHT: + UpChange_dType(); + break; + case VK_LEFT: + DownChange_dType(); + break; + case VK_UP: + if(RootItems.SelectedIndex > 0){ + RootItems.SelectedIndex--; + if(RootItems.SelectedIndex= dDdpLvLineCount){ + RootItems.TopIndex += 1; + } + Lv.SelectedCol = RootItems.SelectedIndex - RootItems.TopIndex; + DrawList(); + } + break; + case VK_EXECUTE: + PathX = 1; + EpItems.Selected_dType = dgTYPE_SMOKE_DETECTOR_I; + LoadPath1(); + DrawList(); + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + case VK_F2: + //start to query + SendReqCmd(); + break; + } + }else + if(PathX == 1){ + switch(aKey){ + case VK_RIGHT: + UpChange_dType(); + break; + case VK_LEFT: + DownChange_dType(); + break; + case VK_UP: + if(EpItems.SelectedIndex>0){ + EpItems.SelectedIndex--; + if(EpItems.SelectedIndex= dDdpLvLineCount ){ + EpItems.TopIndex += 1; + } + Lv.SelectedCol = EpItems.SelectedIndex - EpItems.TopIndex; + DrawList(); + } + break; + case VK_RETURN: + PathX = 0; + LoadPath0(); + DrawList(); + break; + case VK_F2: + //start to query + SendReqCmd(); + break; + } + }else{ + PathX = 0; + LoadPath0(); + DrawList(); + } + return aMsg; +} + + + + diff --git a/MyCode/Gui/DeviceDymPrm.h b/MyCode/Gui/DeviceDymPrm.h new file mode 100644 index 0000000..551c82c --- /dev/null +++ b/MyCode/Gui/DeviceDymPrm.h @@ -0,0 +1,212 @@ +#ifndef DEVICE_DYM_PRM_H_ +#define DEVICE_DYM_PRM_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" + +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" + +#include "StaticText.h" + +//have two list to View Root device and Endpoing device's Dynamics Analog Value Parameter + +class TBasePercentBar{ + public: + int x0,y0,x1,y1; + int Len, Width,Height; + unsigned int BgColor; + unsigned int Color; + + public: + void SetSize(short aX0, short aY0, short aX1, short aY1){ + x0 = aX0; y0 = aY0; x1 = aX1; y1 = aY1; + Width = x1 - x0; + Height = y1 - y0; + } + void SetColor(u32 aColor, u32 aBgColor){ + Color = aColor; + BgColor = aBgColor; + } + void PercentRender(float da, float tt, unsigned char aGotUpdata){ + int i, ax; + float f1 = da / tt * static_cast(Width); + Len = static_cast(f1); + if(Len < 1)Len = 1; + if(aGotUpdata == 0) Len = 0; + ax = x0; + for(i=0; iShow(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + } +} + +void TDeviceSetup::ShowCaption() +{ + TMyString::sFromStr("系统设置->设备定义", Caption.Text); + Caption.Show(); +} + +//______________________________________________________________________________________________________________________________ +void TDeviceSetup::InitPanel(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + if(aPanel == nullptr)return; + + aPanel->Init(200,40,400,260,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("选择设置模式", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->Btn[0].Init(96,16,220,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(96,66,220,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[2].Init(96,116,220,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[3].Init(96,166,220,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("回路设备连续定义"); + aPanel->Btn[1].Caption.FromStr("回路设备一般修改"); + aPanel->Btn[2].Caption.FromStr("回路设备快速定义"); + aPanel->Btn[3].Caption.FromStr(" 多线盘节点定义 "); + + aPanel->Btn[0].Visible = 1; + aPanel->Btn[1].Visible = 1; + aPanel->Btn[2].Visible = 1; + aPanel->Btn[3].Visible = 1; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 1; + aPanel->Btn[2].Enable = 1; + aPanel->Btn[3].Enable = 1; + + aPanel->Btn[0].SetCaptionLeftSpacing(6); + aPanel->Btn[1].SetCaptionLeftSpacing(6); + aPanel->Btn[2].SetCaptionLeftSpacing(6); + aPanel->Btn[3].SetCaptionLeftSpacing(6); + + RenderBackGround(); + SetupMode = 0; + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); +} + +void TDeviceSetup::DrawTip(void) +{ + if(SetupMode == 1) + TextRender_string24(60, 60, clNearBlack, Color, "回路设备连续定义"); + if(SetupMode == 2) + TextRender_string24(60, 60, clNearBlack, Color, "回路设备一般修改"); + if(SetupMode == 3) + TextRender_string24(60, 60, clNearBlack, Color, "回路设备快速定义"); + if(SetupMode == 4) + TextRender_string24(60, 60, clNearBlack, Color, " 多线盘节点定义 "); + + if(SetupMode == 4){ + TextRender_string24(16, 110, clNearBlack, Color, "1.设定为消防泵的"); + TextRender_string24(16, 142, clNearBlack, Color, " 指派类型无效"); + + TextRender_string24(16, 210, clNearBlack, Color, "2.设置键查询键更改类型"); + + TextRender_string24(16, 246, clNearBlack, Color, "3.上下键切换选项"); + TextRender_string24(16, 282, clNearBlack, Color, "4.左右键数字键编辑"); + TextRender_string24(16, 318, clNearBlack, Color, "5.确认键保存"); + }else{ + TextRender_string24(16, 110, clNearBlack, Color, "1.联动类型未指派的"); + TextRender_string24(16, 142, clNearBlack, Color, " 按原设备类型执行联动"); + TextRender_string24(16, 174, clNearBlack, Color, " 指派后行为覆盖原类型"); + + TextRender_string24(16, 210, clNearBlack, Color, "2.设置键查询键更改类型"); + + TextRender_string24(16, 246, clNearBlack, Color, "3.上下键切换选项"); + TextRender_string24(16, 282, clNearBlack, Color, "4.左右键数字键编辑"); + TextRender_string24(16, 318, clNearBlack, Color, "5.确认键保存"); + + if(SetupMode == 1){ + TextRender_string24(16, 356, clNearBlack, Color, "6.保存后地址及二次码"); + TextRender_string24(16, 392, clNearBlack, Color, " 自动加一"); + }else + if(SetupMode == 2){ + TextRender_string24(16, 356, clNearBlack, Color, "6.保存后重新加载"); + } + } + +} + +void TDeviceSetup::InitPanel4Setup(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + if(aPanel == nullptr)return; + + aPanel->Init(300,26,480,320,x,y,clFrmFace, bvRaised); + aPanel->Caption.TextClear(); + aPanel->Caption.Color=clFrmFace; + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + + x = aPanel->Content.Left; + y = aPanel->Bound.Top + 4; + + aPanel->SText[0].Init(6,6,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(6,46,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(6,86,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(6,126,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(6,166,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[5].Init(6,206,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[6].Init(26,240,400,30,x,y,clNearBlack,clFrmFace); + + aPanel->SText[11].Init(170,126,48,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[12].Init(222,126,246,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[13].Init(222,166,246,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[20].Init(270,6,200,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路号:", aPanel->SText[0].Text); + TMyString::sFromStr("地址号:", aPanel->SText[1].Text); + TMyString::sFromStr("二次码:", aPanel->SText[2].Text); + TMyString::sFromStr("原设备类型:", aPanel->SText[3].Text); + TMyString::sFromStr("指派联动类型:", aPanel->SText[4].Text); + TMyString::sFromStr("位置描述信息:", aPanel->SText[5].Text); + TMyString::sFromStr("12345678901234567890123456789012", aPanel->SText[6].Text); + + TMyString::sFromStr("xxx", aPanel->SText[11].Text); + TMyString::sFromStr("12345678901234567890", aPanel->SText[12].Text); + TMyString::sFromStr("12345678901234567890", aPanel->SText[13].Text); + TMyString::sFromStr(" ", aPanel->SText[20].Text); + + aPanel->Edit[0].Init(170,6,48,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[1].Init(170,46,48,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[2].Init(170,86,120,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[3].Init(170,166,48,32,x,y,clNearBlack,clFrmFace); + + for(i=0; i<4; i++){ + aPanel->Edit[i].Enable =1; + aPanel->Edit[i].Visible =1; + } + aPanel->Edit[0].Str.FromStr("xx"); + aPanel->Edit[1].Str.FromStr("xxx"); + aPanel->Edit[2].Str.FromStr("xxxxxxxx"); + aPanel->Edit[3].Str.FromStr("xxx"); + aPanel->Edit[0].MaxLen = 2; + aPanel->Edit[1].MaxLen = 3; + aPanel->Edit[2].MaxLen = 8; + aPanel->Edit[3].MaxLen = 3; + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[2].SetPstTail(); + aPanel->Edit[3].SetPstTail(); + + RenderBackGround(); + DrawTip(); + CtlIndex =0; + aPanel->Show(); + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + LoadStart(); +} + + +void TDeviceSetup::InitPanel4Fast(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + if(aPanel == nullptr)return; + + aPanel->Init(300,46,480,280,x,y,clFrmFace, bvRaised); + aPanel->Caption.TextClear(); + aPanel->Caption.Color=clFrmFace; + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Bound.Top + 4; + + aPanel->SText[0].Init(6,6,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(6,46,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(6,86,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(6,126,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(6,166,110,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[5].Init(6,206,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[6].Init(6,206,110,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[7].Init(6,286,110,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[8].Init(26,320,400,30,x,y,clNearBlack,clFrmFace); + + //aPanel->SText[11].Init(170,206,102,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[12].Init(220,206,102,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[13].Init(220,206,246,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[20].Init(270,6,200,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路号:", aPanel->SText[0].Text); + TMyString::sFromStr("起始地址:", aPanel->SText[1].Text); + TMyString::sFromStr("结束地址:", aPanel->SText[2].Text); + TMyString::sFromStr("二次码:", aPanel->SText[3].Text); + TMyString::sFromStr("步长:", aPanel->SText[4].Text); + //TMyString::sFromStr("原设备类型", aPanel->SText[5].Text); + TMyString::sFromStr("指派联动类型:", aPanel->SText[6].Text); + //TMyString::sFromStr("位置描述信息:", aPanel->SText[7].Text); + //TMyString::sFromStr("12345678901234567890123456789012", aPanel->SText[8].Text); + + //TMyString::sFromStr("xxx", aPanel->SText[11].Text); + //TMyString::sFromStr("12345678901234567890", aPanel->SText[12].Text); + TMyString::sFromStr("12345678901234567890", aPanel->SText[13].Text); + TMyString::sFromStr(" ", aPanel->SText[20].Text); + + aPanel->Edit[0].Init(170,6,48,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[1].Init(170,46,48,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[2].Init(170,86,48,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[3].Init(170,126,120,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[4].Init(170,166,80,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[5].Init(170,206,48,32,x,y,clNearBlack,clFrmFace); + + for(i=0; i<6; i++){ + aPanel->Edit[i].Enable =1; + aPanel->Edit[i].Visible =1; + } + aPanel->Edit[0].Str.FromStr("xx"); + aPanel->Edit[1].Str.FromStr("xxx"); + aPanel->Edit[2].Str.FromStr("xxx"); + aPanel->Edit[3].Str.FromStr("xxxxxxxx"); + aPanel->Edit[4].Str.FromStr("xxxx"); + aPanel->Edit[5].Str.FromStr("---"); + aPanel->Edit[6].Str.FromStr("---"); + aPanel->Edit[0].MaxLen = 2; + aPanel->Edit[1].MaxLen = 3; + aPanel->Edit[2].MaxLen = 3; + aPanel->Edit[3].MaxLen = 8; + aPanel->Edit[4].MaxLen = 4; + aPanel->Edit[5].MaxLen = 3; + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[2].SetPstTail(); + aPanel->Edit[3].SetPstTail(); + aPanel->Edit[4].SetPstTail(); + aPanel->Edit[5].SetPstTail(); + + RenderBackGround(); + DrawTip(); + CtlIndex =0; + aPanel->Show(); + Check4SelectedInFast(); + aPanel->ReDrawItems(); + LoadStart(); +} + + +void TDeviceSetup::InitPanel4DirectPad(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + if(aPanel == nullptr)return; + + aPanel->Init(300,26,480,320,x,y,clFrmFace, bvRaised); + aPanel->Caption.TextClear(); + aPanel->Caption.Color=clFrmFace; + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + + x = aPanel->Content.Left; + y = aPanel->Bound.Top + 4; + + aPanel->SText[0].Init(6,6,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(6,46,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(6,86,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(6,126,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(6,166,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[5].Init(6,206,110,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[6].Init(26,240,400,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[7].Init(222,46,80,30,x,y,clNearBlack,clFrmFace); + + aPanel->SText[11].Init(170,126,48,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[12].Init(222,126,246,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[13].Init(222,166,246,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[20].Init(270,6,200,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("多线盘号:", aPanel->SText[0].Text); + TMyString::sFromStr("节点号:", aPanel->SText[1].Text); + TMyString::sFromStr("二次码:", aPanel->SText[2].Text); + TMyString::sFromStr("已设定消防泵:", aPanel->SText[3].Text); + TMyString::sFromStr("指派联动类型:", aPanel->SText[4].Text); + TMyString::sFromStr("位置描述信息:", aPanel->SText[5].Text); + TMyString::sFromStr("12345678901234567890123456789012", aPanel->SText[6].Text); + TMyString::sFromStr("未注册", aPanel->SText[7].Text); + + TMyString::sFromStr("xxx", aPanel->SText[11].Text); + TMyString::sFromStr(" ", aPanel->SText[12].Text); + TMyString::sFromStr("12345678901234567890", aPanel->SText[13].Text); + TMyString::sFromStr(" ", aPanel->SText[20].Text); + + aPanel->Edit[0].Init(170,6,48,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[1].Init(170,46,48,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[2].Init(170,86,120,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[3].Init(170,166,48,32,x,y,clNearBlack,clFrmFace); + + for(i=0; i<4; i++){ + aPanel->Edit[i].Enable =1; + aPanel->Edit[i].Visible =1; + } + aPanel->Edit[0].Str.FromStr("xx"); + aPanel->Edit[1].Str.FromStr("xxx"); + aPanel->Edit[2].Str.FromStr("xxxxxxxx"); + aPanel->Edit[3].Str.FromStr("xxx"); + aPanel->Edit[0].MaxLen = 2; + aPanel->Edit[1].MaxLen = 3; + aPanel->Edit[2].MaxLen = 8; + aPanel->Edit[3].MaxLen = 3; + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[2].SetPstTail(); + aPanel->Edit[3].SetPstTail(); + + RenderBackGround(); + DrawTip(); + CtlIndex =0; + aPanel->Show(); + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + LoadStart(); +} + + +//_____________________________________________________________________________________________________________________________ + +void TDeviceSetup::ShowSaveOk() +{ + TMyString::sFromStr("保存成功", aPanel->SText[20].Text); + aPanel->SText[20].Show(); +} + +void TDeviceSetup::ShowSaveNotOk() +{ + TMyString::sFromStr("写入失败", aPanel->SText[20].Text); + aPanel->SText[20].Show(); +} + +void TDeviceSetup::ShowCheckDataFail() +{ + TMyString::sFromStr("请检查设置值", aPanel->SText[20].Text); + aPanel->SText[20].Show(); +} + +void TDeviceSetup::ClearOutText() +{ + TMyString::sClear(aPanel->SText[20].Text); + aPanel->SText[20].Show(); +} + +void TDeviceSetup::Check4Selected() +{ + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[2].Selected = 0; + aPanel->Btn[3].Selected = 0; + if(CtlIndex == 0){ + aPanel->Btn[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Btn[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Btn[2].Selected = 1; + }else + if(CtlIndex == 3){ + aPanel->Btn[3].Selected = 1; + } +} + +void TDeviceSetup::Check4SelectedInSetup() +{ + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 0; + + if(CtlIndex == 0){ + aPanel->Edit[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Edit[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Edit[2].Selected = 1; + }else + if(CtlIndex == 3){ + aPanel->Edit[3].Selected = 1; + } +} + +void TDeviceSetup::Check4SelectedInFast() +{ + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 0; + aPanel->Edit[4].Selected = 0; + aPanel->Edit[5].Selected = 0; + + if(CtlIndex == 0){ + aPanel->Edit[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Edit[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Edit[2].Selected = 1; + }else + if(CtlIndex == 3){ + aPanel->Edit[3].Selected = 1; + }else + if(CtlIndex == 4){ + aPanel->Edit[4].Selected = 1; + }else + if(CtlIndex == 5){ + aPanel->Edit[5].Selected = 1; + } +} + +void TDeviceSetup::GetNewPathAddr() +{ + unsigned int iVal; + iVal = aPanel->Edit[0].Str.ToInteger(); + if( (iVal >0) && (iVal<=dPORT_MAX_COUNT) ){ + Path0 = iVal; + }else{ + Path0 = 0; + } + iVal = aPanel->Edit[1].Str.ToInteger(); + if( (iVal >0) && (iVal<=250) ){ + Addr = iVal; + }else{ + Addr = 0; + } +} + +void TDeviceSetup::LoadData(int Inc) +{ + unsigned int aAddr,i; + unsigned char aP0, aP1; + if( (SetupMode ==1) || (SetupMode == 2) ){ + if( (Path0>0) && (Path00) && (Addr<=250) ){ + aP0 = Path0-1; + aP1 = Addr-1; + if(Port[aP0].ExistTable[aP1]){ + IsFound =1; + }else{ + IsFound =0; + } + }else{ + IsFound =0; + } + if(IsFound){ + if(SetupMode ==1){ + if(Inc){ + aPanel->Edit[2].Str.FromUInt8Dg(UserCode.Full); + aPanel->Edit[3].Str.FromUInt3Dg(AssignType); + }else{ + AssignType = Port[aP0].AssignType[aP1]; + + aPanel->Edit[2].Str.FromUInt8Dg(Port[aP0].UcList[aP1].Full); + aPanel->Edit[3].Str.FromUInt3Dg(AssignType); + } + }else + if(SetupMode ==2){ + aPanel->Edit[2].Str.FromUInt8Dg(Port[aP0].UcList[aP1].Full); + aPanel->Edit[3].Str.FromUInt3Dg(Port[aP0].AssignType[aP1]); + } + TMyString::sFrom3Dg(Port[aP0].dTypeTable[aP1], aPanel->SText[11].Text); + TMyString::sFromStr(StrTypeShortName[Port[aP0].dTypeTable[aP1]], aPanel->SText[12].Text); + TMyString::sFromStr(StrTypeShortName[AssignType], aPanel->SText[13].Text); + + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=0; i<8; i++){ + ReadWriteData.D32[i] = *(volatile unsigned int *)(aAddr + (i *4)); + } + for(i=0; i<32; i++){ + aPanel->SText[6].Text[i] = ReadWriteData.D8[i]; + } + aPanel->SText[6].Text[32] = '\0'; + aPanel->Edit[2].Show(); + aPanel->Edit[3].Show(); + aPanel->SText[11].Show(); + aPanel->SText[12].Show(); + aPanel->SText[13].Show(); + aPanel->SText[6].Show(); + }else{ + aPanel->Edit[2].Str.FromUInt8Dg(0); + aPanel->Edit[3].Str.FromUInt3Dg(0); + TMyString::sFromStr("xxx", aPanel->SText[11].Text); + TMyString::sFromStr("无效", aPanel->SText[12].Text); + TMyString::sFromStr("无效", aPanel->SText[13].Text); + + TMyString::sFromStr("此地址未登记", aPanel->SText[6].Text); + + + aPanel->Edit[2].Show(); + aPanel->Edit[3].Show(); + aPanel->SText[11].Show(); + aPanel->SText[12].Show(); + aPanel->SText[13].Show(); + aPanel->SText[6].Show(); + } + }else + if(SetupMode == 3){ + + } +} + + +void TDeviceSetup::DrawFast() +{ + unsigned int aAddr,i; + unsigned char aP0, aP1; + + if(SetupMode == 3){ + + } +} + +void TDeviceSetup::FindType(int Dir) +{ + unsigned char aInx; + int i; + aInx = AssignType; + if(Dir == -1){ + for(i=0; i<257; i++){ + aInx--; + if( (StrTypeShortName[aInx][0] != NonTypeText[0]) && (StrTypeShortName[aInx][1] != NonTypeText[1]) ){ + AssignType = aInx; + break; + } + } + }else{ + for(i=0; i<257; i++){ + aInx++; + if( (StrTypeShortName[aInx][0] != NonTypeText[0]) && (StrTypeShortName[aInx][1] != NonTypeText[1]) ){ + AssignType = aInx; + break; + } + } + } + + if( (SetupMode == 1) || (SetupMode == 2) || (SetupMode == 4)){ + aPanel->Edit[3].Str.FromUInt3Dg(AssignType); + aPanel->Edit[3].Show(); + }else + if(SetupMode == 3){ + aPanel->Edit[5].Str.FromUInt3Dg(AssignType); + aPanel->Edit[5].Show(); + } + TMyString::sFromStr(StrTypeShortName[AssignType], aPanel->SText[13].Text); + aPanel->SText[13].Show(); +} + +void TDeviceSetup::CheckDirectPadAva() +{ + int iVal0, iVal1; + unsigned char OldAva; + OldAva = DirectPadAva; + iVal0 = aPanel->Edit[0].Str.ToInteger(); + iVal1 = aPanel->Edit[1].Str.ToInteger(); + + if( (iVal0 !=0) && (iVal0 <= dDIRECTCTL_MAX_COUNT) && (iVal1 !=0) && (iVal1 <= dDIRECTCTL_KEY_MAX_COUNT) ){ + DirectPadAva = 1; + DirectPadNum = iVal0 -1; + NodeNum = iVal1 -1; + }else{ + DirectPadAva = 0; + } + + if( DirectPadAva == 0 ){ + aPanel->SText[7].Enable =0; + aPanel->SText[7].TextClear(); + aPanel->SText[7].Show(); + aPanel->Edit[2].Enable = 0; + aPanel->Edit[3].Enable = 0; + aPanel->Edit[2].Str.Clear(); + aPanel->Edit[3].Str.Clear(); + aPanel->Edit[2].Show(); + aPanel->Edit[3].Show(); + }else{ + if(OldAva != DirectPadAva){ + aPanel->SText[7].Enable =1; + aPanel->Edit[2].Enable = 1; + aPanel->Edit[3].Enable = 1; + } + aPanel->Edit[2].Show(); + aPanel->Edit[3].Show(); + } +} + +void TDeviceSetup::DirectPadDataShow() +{ + unsigned int aAddr,i; + unsigned char aP0, aP1; + + if(DirectPadAva == 0 ) return; + + UserCode.Full = DirectCtlBoard[DirectPadNum].UcList[NodeNum].Full; + AssignType = DirectCtlBoard[DirectPadNum].AssignType[NodeNum]; + if(DirectCtlBoard[DirectPadNum].IsRegisted[NodeNum]){ + TMyString::sFromStr("已注册", aPanel->SText[7].Text); + }else{ + TMyString::sFromStr("未注册", aPanel->SText[7].Text); + } + if(DirectCtlBoard[DirectPadNum].IsPump[NodeNum]){ + TMyString::sFromStr("是", aPanel->SText[11].Text); + }else{ + TMyString::sFromStr("否", aPanel->SText[11].Text); + } + + aPanel->Edit[0].Str.FromUInt2Dg(DirectPadNum +1); + aPanel->Edit[1].Str.FromUInt3Dg(NodeNum +1); + aPanel->Edit[2].Str.FromUInt8Dg(UserCode.Full); + aPanel->Edit[3].Str.FromUInt3Dg(AssignType); + aPanel->Edit[0].Show(); + aPanel->Edit[1].Show(); + aPanel->Edit[2].Show(); + aPanel->Edit[3].Show(); + TMyString::sFromStr(StrTypeShortName[AssignType], aPanel->SText[13].Text); + aPanel->SText[11].Show(); + aPanel->SText[13].Show(); + + aP1 = DirectPadNum * dDIRECTCTL_KEY_MAX_COUNT + (NodeNum +1); + aAddr = dAddrSdRam_Descp + (40 * 256 * 32) + (aP1 * 32); + for(i=0; i<8; i++)ReadWriteData.D32[i] = *(volatile unsigned int *)(aAddr + (i) *4); + for(i=0; i<32; i++)aPanel->SText[6].Text[i] = ReadWriteData.D8[i]; + aPanel->SText[6].Text[32] = '\0'; + + aPanel->SText[6].Show(); + aPanel->SText[7].Show(); +} + +void TDeviceSetup::GetMinMax(unsigned int aP0) +{ + unsigned int p0, x; + if(aP0 == 0)return; + if(aP0 >dPORT_MAX_COUNT)return; + + p0 = aP0; + + Port[p0].UserCodeMin = 0xFFFFFFFF; + Port[p0].UserCodeMax = 0; + + for(x=0;x<256;x++){ + if(Port[p0].UcList[x].Full < Port[p0].UserCodeMin){ + Port[p0].UserCodeMin = Port[p0].UcList[x].Full; + } + if(Port[p0].UcList[x].Full > Port[p0].UserCodeMax){ + Port[p0].UserCodeMax = Port[p0].UcList[x].Full; + } + } +} + + +TGuiMsgReturn TDeviceSetup::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + unsigned char Path0Old, AddrOld; + unsigned int aAddr, aUcFull; + int iVal; + int SaveOk; + TDMix aFullPath; + + if(SetupMode == 1){ + //Continute + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + Path0Old = Path0; + AddrOld = Addr; + if(CtlIndex <4){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex <2){ + GetNewPathAddr(); + if( (Path0Old != Path0) || (AddrOld != Addr) ){ + LoadData(0); + } + }else + if(CtlIndex == 3){ + iVal = aPanel->Edit[3].Str.ToInteger(); + if(iVal < 256){ + AssignType = iVal; + }else{ + AssignType = 255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + aPanel->Edit[CtlIndex].Show(); + } + aPanel->SText[13].SetText(StrTypeShortName[AssignType],24); + aPanel->SText[13].Show(); + } + break; + case VK_DELETE: + Path0Old = Path0; + AddrOld = Addr; + if(CtlIndex <4){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex <2){ + GetNewPathAddr(); + if( (Path0Old != Path0) || (AddrOld != Addr) ){ + LoadData(0); + } + }else + if(CtlIndex == 3){ + iVal = aPanel->Edit[3].Str.ToInteger(); + if(iVal < 256){ + AssignType = iVal; + }else{ + AssignType = 255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + aPanel->Edit[CtlIndex].Show(); + } + aPanel->SText[13].SetText(StrTypeShortName[AssignType],24); + aPanel->SText[13].Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <3){ + CtlIndex++; + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + } + break; + case dfKEY_SETUP: + if(CtlIndex == 3){ + FindType(-1); + } + break; + case dfKEY_QUERY: + if(CtlIndex == 3){ + FindType(1); + } + break; + case VK_EXECUTE: + if(PrepData2Write()){ + Write2Flash(); + Record.ReadDevUserSet(); + if(Port[Path0-1].UcList[Addr-1].Full == UserCode.Full){ + SaveOk =1; + ShowSaveOk(); + LoadNext(); + LoadData(1); + }else{ + SaveOk =0; + ShowSaveNotOk(); + } + }else{ + ShowCheckDataFail(); + } + break; + case VK_RETURN: + CtlIndex =0; + InitPanel(); + break; + } + if( (VK_EXECUTE != aKey) && (VK_RETURN != aKey) ){ + ClearOutText(); + } + }else + if(SetupMode == 2){ + // Inh + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + Path0Old = Path0; + AddrOld = Addr; + if(CtlIndex <4){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex <2){ + GetNewPathAddr(); + if( (Path0Old != Path0) || (AddrOld != Addr) ){ + LoadData(0); + } + }else + if(CtlIndex == 3){ + iVal = aPanel->Edit[3].Str.ToInteger(); + if(iVal < 256){ + AssignType = iVal; + }else{ + AssignType = 255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + aPanel->Edit[CtlIndex].Show(); + } + aPanel->SText[13].SetText(StrTypeShortName[AssignType],24); + aPanel->SText[13].Show(); + } + break; + case VK_DELETE: + Path0Old = Path0; + AddrOld = Addr; + if(CtlIndex <4){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex <2){ + GetNewPathAddr(); + if( (Path0Old != Path0) || (AddrOld != Addr) ){ + LoadData(0); + } + }else + if(CtlIndex == 3){ + iVal = aPanel->Edit[3].Str.ToInteger(); + if(iVal < 256){ + AssignType = iVal; + }else{ + AssignType = 255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + aPanel->Edit[CtlIndex].Show(); + } + aPanel->SText[13].SetText(StrTypeShortName[AssignType],24); + aPanel->SText[13].Show(); + } + break; + case dfKEY_SETUP: + if(CtlIndex == 3){ + FindType(-1); + } + break; + case dfKEY_QUERY: + if(CtlIndex == 3){ + FindType(1); + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <3){ + CtlIndex++; + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + } + break; + case VK_EXECUTE: + if(PrepData2Write()){ + Write2Flash(); + Record.ReadDevUserSet(); + if(Port[Path0-1].UcList[Addr-1].Full == UserCode.Full){ + SaveOk =1; + ShowSaveOk(); + LoadData(0); + }else{ + SaveOk =0; + ShowSaveNotOk(); + } + }else{ + ShowCheckDataFail(); + } + break; + case VK_RETURN: + CtlIndex =1; + InitPanel(); + break; + } + if( (VK_EXECUTE != aKey) && (VK_RETURN != aKey) ){ + ClearOutText(); + } + }else + if(SetupMode == 3){ + //Fast + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex <6){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex == 5){ + iVal = aPanel->Edit[CtlIndex].Str.ToInteger(); + if(iVal >255){ + AssignType=255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + }else{ + AssignType = iVal; + } + aPanel->Edit[CtlIndex].Show(); + aPanel->SText[13].SetText(StrTypeShortName[AssignType], 24); + aPanel->SText[13].Show(); + } + break; + case VK_DELETE: + if(CtlIndex <6){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex == 5){ + iVal = aPanel->Edit[CtlIndex].Str.ToInteger(); + if(iVal >255){ + AssignType=255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + }else{ + AssignType = iVal; + } + aPanel->Edit[CtlIndex].Show(); + aPanel->SText[13].SetText(StrTypeShortName[AssignType], 24); + aPanel->SText[13].Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4SelectedInFast(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <5){ + CtlIndex++; + Check4SelectedInFast(); + aPanel->ReDrawItems(); + } + break; + case dfKEY_SETUP: + if(CtlIndex == 5){ + FindType(-1); + } + break; + case dfKEY_QUERY: + if(CtlIndex == 5){ + FindType(1); + } + break; + case VK_EXECUTE: + if(PrepData2Write()){ + Write2Flash(); + Record.ReadDevUserSet(); + aUcFull = UserCode.Full; + SaveOk =1; + for(x=AddrStart-1; xEdit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex <2){ + CheckDirectPadAva(); + DirectPadDataShow(); + }else + if(CtlIndex == 3){ + iVal = aPanel->Edit[3].Str.ToInteger(); + if(iVal < 256){ + AssignType = iVal; + }else{ + AssignType = 255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + aPanel->Edit[CtlIndex].Show(); + } + aPanel->SText[13].SetText(StrTypeShortName[AssignType],24); + aPanel->SText[13].Show(); + } + break; + case VK_DELETE: + Path0Old = Path0; + AddrOld = Addr; + if(CtlIndex <4){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].Show(); + } + if(CtlIndex <2){ + CheckDirectPadAva(); + DirectPadDataShow(); + }else + if(CtlIndex == 3){ + iVal = aPanel->Edit[3].Str.ToInteger(); + if(iVal < 256){ + AssignType = iVal; + }else{ + AssignType = 255; + aPanel->Edit[CtlIndex].Str.FromUInt3Dg(AssignType); + aPanel->Edit[CtlIndex].Show(); + } + aPanel->SText[13].SetText(StrTypeShortName[AssignType],24); + aPanel->SText[13].Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex < 1){ + CtlIndex++; + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + }else + if(CtlIndex <3){ + if(DirectPadAva){ + CtlIndex++; + Check4SelectedInSetup(); + aPanel->ReDrawItems(); + } + } + break; + case dfKEY_SETUP: + if(CtlIndex == 3){ + FindType(-1); + } + break; + case dfKEY_QUERY: + if(CtlIndex == 3){ + FindType(1); + } + break; + case VK_EXECUTE: + if(PrepData2Write()){ + WriteDirectPad2Flash(); + Record.ReadDirectPadUserSet(); + if(DirectCtlBoard[DirectPadNum].UcList[NodeNum].Full == UserCode.Full){ + SaveOk =1; + ShowSaveOk(); + }else{ + SaveOk =0; + ShowSaveNotOk(); + } + }else{ + ShowCheckDataFail(); + } + break; + case VK_RETURN: + CtlIndex =3; + InitPanel(); + break; + } + if( (VK_EXECUTE != aKey) && (VK_RETURN != aKey) ){ + ClearOutText(); + } + }else{ + //Start to Selecte Setup Mode + switch(aKey){ + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <3){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + SetupMode = 1; + InitPanel4Setup(); + }else + if(CtlIndex == 1){ + SetupMode = 2; + InitPanel4Setup(); + }else + if(CtlIndex == 2){ + SetupMode = 3; + InitPanel4Fast(); + }else + if(CtlIndex == 3){ + SetupMode = 4; + InitPanel4DirectPad(); + } + break; + case VK_RETURN: + SetupMode = 0; + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TDeviceSetup::LoadStart() +{ + int aP0, aP1,i; + unsigned int aAddr; + IsFound = 0; + if( (SetupMode == 1) || (SetupMode == 2) ){ + for(aP0=0; aP0Edit[0].Str.FromUInt2Dg(Path0); + aPanel->Edit[1].Str.FromUInt3Dg(Addr); + aPanel->Edit[2].Str.FromUInt8Dg(UserCode.Full); + aPanel->Edit[3].Str.FromUInt3Dg(AssignType); + aPanel->Edit[0].Show(); + aPanel->Edit[1].Show(); + aPanel->Edit[2].Show(); + aPanel->Edit[3].Show(); + TMyString::sFrom3Dg(Port[aP0].dTypeTable[aP1], aPanel->SText[11].Text); + TMyString::sFromStr(StrTypeShortName[Port[aP0].dTypeTable[aP1]], aPanel->SText[12].Text); + TMyString::sFromStr(StrTypeShortName[AssignType], aPanel->SText[13].Text); + aPanel->SText[11].Show(); + aPanel->SText[12].Show(); + aPanel->SText[13].Show(); + + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=0; i<8; i++){ + ReadWriteData.D32[i] = *(volatile unsigned int *)(aAddr + (i *4)); + } + for(i=0; i<32; i++){ + aPanel->SText[6].Text[i] = ReadWriteData.D8[i]; + } + aPanel->SText[6].Text[32] = '\0'; + aPanel->SText[6].Show(); + break; + } + } + } + if(IsFound){ + break; + } + } + }else + if(SetupMode == 3){ + for(aP0=0; aP0 250)AddrEnd=250; + UserCode.Full = 1010101; + Pitch = 1; + AssignType = 0; + + aPanel->Edit[0].Str.FromUInt2Dg(Path0); + aPanel->Edit[1].Str.FromUInt3Dg(AddrStart); + aPanel->Edit[2].Str.FromUInt3Dg(AddrStart); + aPanel->Edit[3].Str.FromUInt8Dg(UserCode.Full); + aPanel->Edit[4].Str.FromUInt4Dg(Pitch); + aPanel->Edit[5].Str.FromUInt3Dg(AssignType); + + aPanel->Edit[0].Show(); + aPanel->Edit[1].Show(); + aPanel->Edit[2].Show(); + aPanel->Edit[3].Show(); + aPanel->Edit[4].Show(); + aPanel->Edit[5].Show(); + + TMyString::sFromStr(StrTypeShortName[AssignType], aPanel->SText[13].Text); + aPanel->SText[13].Show(); + break; + } + } + } + if(IsFound){ + break; + } + } + }else + if(SetupMode == 4){ + DirectPadNum =0; + NodeNum =0; + DirectPadAva = 1; + + DirectPadDataShow(); + + } +} + +void TDeviceSetup::LoadNext() +{ + int aP0, aP1, i; + int FoundHere; + FoundHere = 0; + if( (Path0>0) && (Path0<=dPORT_MAX_COUNT) && (Addr >0) && (Addr<=250) ){ + aP0 = Path0-1; + aP1 = Addr -1; + aP1++; + if(aP1<=250){ + for(; aP1<250; aP1++){ + if(Port[aP0].ExistTable[aP1]){ + FoundHere = 1; + if(UserCode.Full < 99999999)UserCode.Full++; + IsFound =1; + Path0 = aP0+1; + Addr = aP1+1; + aPanel->Edit[0].Str.FromUInt2Dg(Path0); + aPanel->Edit[1].Str.FromUInt3Dg(Addr); + aPanel->Edit[0].Show(); + aPanel->Edit[1].Show(); + break; + } + } + } + if(FoundHere == 0){ + for(i=0; i= dPORT_MAX_COUNT) aP0 = 0; + if(MainCtl.fData.Split.ExistTablePort[aP0]){ + for(aP1=0; aP1<250; aP1++){ + if(Port[aP0].ExistTable[aP1]){ + FoundHere = 1; + if(UserCode.Full < 99999999)UserCode.Full++; + IsFound =1; + Path0 = aP0+1; + Addr = aP1+1; + aPanel->Edit[0].Str.FromUInt2Dg(Path0); + aPanel->Edit[1].Str.FromUInt3Dg(Addr); + aPanel->Edit[0].Show(); + aPanel->Edit[1].Show(); + break; + } + if(FoundHere){ + break; + } + } + } + if(FoundHere){ + break; + } + } + } + }else{ + for(aP0=0; aP0Edit[0].Str.FromUInt2Dg(Path0); + aPanel->Edit[1].Str.FromUInt3Dg(Addr); + aPanel->Edit[0].Show(); + aPanel->Edit[1].Show(); + break; + } + } + } + if(FoundHere){ + break; + } + } + } +} + +int TDeviceSetup::PrepData2Write() +{ + int i; + unsigned char aP0, aP1; + if( (SetupMode == 1) || (SetupMode == 2) ){ + Path0 = aPanel->Edit[0].Str.ToInteger(); + Addr = aPanel->Edit[1].Str.ToInteger(); + UserCode.Full = aPanel->Edit[2].Str.ToInteger(); + AssignType = aPanel->Edit[3].Str.ToInteger(); + if( (Path0>0) && (Path0 <= dPORT_MAX_COUNT) && (Addr >0) && (Addr <= 250) ){ + //if( (UserCode.Full <= 99999999) && (AssignType >0) && (AssignType < 256) ){ + if( (UserCode.Full <= 99999999) && (AssignType < 256) ){ + return 1; + } + } + }else + if(SetupMode == 3){ + Path0 = aPanel->Edit[0].Str.ToInteger(); + AddrStart = aPanel->Edit[1].Str.ToInteger(); + AddrEnd = aPanel->Edit[2].Str.ToInteger(); + UserCode.Full = aPanel->Edit[3].Str.ToInteger(); + Pitch = aPanel->Edit[4].Str.ToInteger(); + AssignType = aPanel->Edit[5].Str.ToInteger(); + if( (Path0>0) && (Path0 <= dPORT_MAX_COUNT) && (AddrStart >0) && (AddrStart <= 250) && (AddrEnd >0) && (AddrEnd <= 250) ){ + //if( (UserCode.Full <= 99999999) && (AssignType >0) && (AssignType < 256) ){ + if( (UserCode.Full <= 99999999) && (AssignType < 256) ){ + return 1; + } + } + }else + if(SetupMode == 4){ + UserCode.Full = aPanel->Edit[2].Str.ToInteger(); + AssignType = aPanel->Edit[3].Str.ToInteger(); + if( (DirectPadNum < dDIRECTCTL_MAX_COUNT) && (NodeNum < dDIRECTCTL_KEY_MAX_COUNT) ){ + //if( (UserCode.Full <= 99999999) && (AssignType >0) && (AssignType < 256) ){ + if( (UserCode.Full <= 99999999) && (AssignType < 256) ){ + return 1; + } + } + } + return 0; +} + +void TDeviceSetup::Write2Flash() +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (Path0 >0) && (Path0 <= dPORT_MAX_COUNT) ){ + aP0 = Path0 -1; + aP1 = Addr -1; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + DelayMs(100); + + do{ + DelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + aUcFull = UserCode.Full; + for(i=0; i<4; i++){ + for(x=0;x<64;x++){ + ReadWriteData.D32[x] = Port[aP0].UcList[i*64 + x].Full; + if( (SetupMode == 1) || (SetupMode == 2) ){ + if( (i*64 + x) == (Addr -1))ReadWriteData.D32[x] = UserCode.Full; + }else + if(SetupMode == 3){ + wP1 = i*64 + x; + if( (wP1>= (AddrStart -1)) && (wP1 <= (AddrEnd-1) ) ){ + ReadWriteData.D32[x] = aUcFull; + aUcFull += Pitch; + } + } + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (i * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } + + for(x=0;x<256;x++){ + ReadWriteData.D8[x] = Port[aP0].AssignType[x]; + if( (SetupMode == 1) || (SetupMode == 2) ){ + if(x == (Addr -1) )ReadWriteData.D8[x] = AssignType; + }else + if(SetupMode == 3){ + wP1 = AddrStart -1; + if( (x >= wP1) && (x <= (AddrEnd-1)) ){ + ReadWriteData.D8[x] = AssignType; + } + } + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (i * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } +} + +void TDeviceSetup::WriteDirectPad2Flash() +{ + unsigned int fAddr; + unsigned int i; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (DirectPadNum < dDIRECTCTL_MAX_COUNT) && (NodeNum < dDIRECTCTL_KEY_MAX_COUNT) ){ + aP0 = DirectPadNum; + aP1 = NodeNum; + fAddr = dFlashAddrDirectPadUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + DelayMs(100); + + do{ + DelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + for(x=0;x<8;x++){ + ReadWriteData.D32[x] = DirectCtlBoard[aP0].UcList[x].Full; + } + for(x=0;x<8;x++){ + ReadWriteData.D8[x +32] = DirectCtlBoard[aP0].AssignType[x]; + } + ReadWriteData.D32[NodeNum] = UserCode.Full; + ReadWriteData.D8[NodeNum + 32] = AssignType; + + fAddr = dFlashAddrDirectPadUserCode + (aP0 * 4096) + (0 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } +} + +void TDeviceSetup::ClearAll() +{ + unsigned int fAddr; + volatile unsigned int x, GetSta; + + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + for( x=0; xSTextState.Show(); + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->EditDescpShow.Show(); + + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + DrawPadBoardCfgList(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + if(EdittingDescp){} + } +} + +void TDirectPadCfg::DrawState() +{ + unsigned char aSta; + if(Path0 && Path1 && (Path0 <= dDIRECTCTL_MAX_COUNT) && (Path1 <= dDIRECTCTL_KEY_MAX_COUNT) ){ + if(DirectCtlBoard[Path0-1].FaultState[Path1-1]){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clOrange, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("故障", 24); else IList->STextState.SetText("FLT.", 24); + }else + if(DirectCtlBoard[Path0-1].FeedbackState[Path1-1]){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("反馈", 24);else IList->STextState.SetText("FBCK", 24); + }else + if(DirectCtlBoard[Path0-1].OutputState[Path1-1]){ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clBlue, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("启动", 24);else IList->STextState.SetText("ACT.", 24); + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, clDeepGreen, 0xF); + if(LanguageEnCn==0)IList->STextState.SetText("正常", 24);else IList->STextState.SetText("IDLE", 24); + } + }else{ + TCircle::sRender(IList->STextState.Bound.Left -12, IList->STextState.Bound.Top +14, 10, ItemColor, 0xF); + IList->STextState.SetText("----", 24); + } + IList->STextState.Show(); +} + +void TDirectPadCfg::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn==0){ + if(EnterMethod) + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "手动控制盘->信息->多线配置"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "手动控制盘->多线配置 "); + }else{ + if(EnterMethod) + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Manual Control Unit->Information->Direct Pad Boards Config"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Manual Control Unit->Direct Pad Boards Config "); + } + + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.PanelSmall.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + for(int i=2; iSTextCtlNum.Init(Lv.Grid.Left[0] + 236, Lv.Grid.Top[0] + 6, 120, 30, 0, 0, clNearWhite, ItemColor); + TextDigitRender2Right24(Lv.Grid.Left[0] + 392, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + IList->STextState.Init(Lv.Grid.Left[0] + 730, Lv.Grid.Top[0] + 2, 68, 30, 0, 0, clNearWhite, ItemColor); + + IList->EditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 2, 50, 30, 0, 0, 1, clNearWhite); + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + IList->EditDescpShow.Init(Lv.Grid.Left[0] + 390, Lv.Grid.Top[0] + 36, 400, 30, 0, 0, 1, clNearWhite); + + IList->STextDType.Enable = 1; + IList->STextDType.Visible =1; + IList->STextState.Enable = 1; + IList->STextState.Visible =1; + IList->STextRegisted.Enable = 1; + IList->STextRegisted.Visible =1; + //IList->STextCtlNum.Enable = 1; + //IList->STextCtlNum.Visible =1; + IList->EditPortNum.TextClear(); + IList->EditAddrNum.TextClear(); + IList->EditPortNum.SetMaxLen(2); + IList->EditAddrNum.SetMaxLen(2); + if(EnterMethod) + IList->EditPortNum.Enable = 0; + else + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible = 1; + IList->EditAddrNum.Enable = 1; + IList->EditAddrNum.Visible = 1; + IList->EditDescpShow.Enable = 1; + IList->EditDescpShow.Visible = 1; + + //User Code & Area Assign + IList->EditUserCode.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 6, 108, 30, 0, 0, 1, clNearWhite); + IList->EditAreaAssign.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 40, 108, 30, 0, 0, 1, clNearWhite); + + IList->EditUserCode.Enable = 1; + IList->EditUserCode.Visible =1; + IList->EditUserCode.SetMaxLen(8); + IList->EditAreaAssign.Enable = 1; + IList->EditAreaAssign.Visible =1; + IList->EditAreaAssign.SetMaxLen(4); + + IList->Edit[0].Init(Lv.Grid.Left[2] +146, Lv.Grid.Top[2] + 4, 48,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(3); + IList->Edit[0].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +4, Lv.Grid.Top[2] + 40, 260,30,0,0,clNearWhite,ItemColor); + //if(Path0Valid && Path1Valid){ + // unsigned char tType = DirectCtlBoard[Path0-1].AssignType[Path1-1]; + // IList->Edit[0].Str.FromUInt3Dg(tType); + // if(tType == 0){ + // IList->STextModuleInDefineType.SetText("未指派类型" , 24); + // }else{ + // IList->STextModuleInDefineType.SetText(StrTypeShortName[tType] , 24); + // } + //}else{ + // IList->STextModuleInDefineType.SetText("----" , 24); + //} + //IList->Edit[0].Show(); + //IList->STextModuleInDefineType.Show(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.PanelSmall.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); +} + +void TDirectPadCfg::DrawPadBoardCfgList() +{ + int i, x, y; + x = Lv.Panel.Left+6; + y = Lv.Panel.Top +2; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearBlack, PanelColor, "节点 二次码 分区 故障检测 启用"); + }else{ + TextRender_string24(x, y, clNearBlack, PanelColor, "Node AuxID Zone CheckLine InUse"); + } + int TopCnt = dDIRECTCTL_KEY_MAX_COUNT; + if( TopCnt >8) TopCnt = 8; + for(i=0; iEditDescpShow.Str.Text[i] = *(volatile unsigned char *)(aAddr + i); + } + IList->EditDescpShow.Str.Text[32] = '\0'; + IList->EditDescpShow.Str.Text[33] = '\0'; + IList->EditDescpShow.SetPstTail(); + IList->EditDescpShow.Show(); + IList->EditDescpShow.ShowCursor(); + } + } +} + +void TDirectPadCfg::DrawUserCodeAssignAreaAssignType() +{ + int iVal; + IList->EditUserCode.Str.FromUInt8Dg(DirectCtlBoard[Path0-1].UcList[Path1-1].Full); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Str.FromUInt4Dg(DirectCtlBoard[Path0-1].Area[Path1-1]); + IList->EditAreaAssign.Show(); + IList->Edit[0].Str.FromUInt3Dg(DirectCtlBoard[Path0-1].AssignType[Path1-1]); + IList->Edit[0].Show(); + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal > 255) || (iVal <0) ){ + iVal = 0; + IList->STextModuleInDefineType.SetText(" ",24); + }else{ + if(LanguageEnCn==0) + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + else + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + IList->STextModuleInDefineType.Show(); +} + + + +void TDirectPadCfg::SetPath(unsigned char aCtlNum, unsigned char aPath0, unsigned char aPath1) +{ + unsigned char tP0, tP1, tT; + //this->CtlNum = aCtlNum; + if(aPath0 && (aPath0 <= dDIRECTCTL_MAX_COUNT)) { + Path0Valid = 1; + IList->EditPortNum.SelectedColor = clBlue; + }else{ + Path0Valid = 0; + IList->EditPortNum.SelectedColor = clRed; + } + if(aPath1 && (aPath1 <= dDIRECTCTL_KEY_MAX_COUNT)){ + Path1Valid = 1; + IList->EditAddrNum.SelectedColor = clBlue; + }else{ + Path1Valid = 0; + IList->EditAddrNum.SelectedColor = clRed; + } + this->Path0 = aPath0; + this->Path1 = aPath1; + + IList->EditPortNum.Str.FromUInt2Dg(aPath0); + IList->EditAddrNum.Str.FromUInt2Dg(aPath1); + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + + DrawState(); + ReLoadAndDrawDescp(); + DrawUserCodeAssignAreaAssignType(); + LoadCfg4Edit(aPath0, aPath1); + + DrawPadBoardCfgList(); + + Check4Selected(); +} + +void TDirectPadCfg::Show(void) +{ + DrawSelf(); + IsShow = 1; +} + +void TDirectPadCfg::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickEditDescpShow.Selected = 1; + IList->EditDescpShow.SetPstTail(); + IList->EditDescpShow.Show(); + + RectFillRender(aPanel->Bound.Left, aPanel->Bound.Top, aPanel->Bound.Right, aPanel->Bound.Bottom, ContentColor); + for(int i=1; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.PanelSmall.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "二次码"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "分区号"); + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "定义类型"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "故障检测"); + TextRender_string24(Lv.Grid.Left[3] +50, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "开启"); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "AuxID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "Assign Type"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "Inspection"); + TextRender_string24(Lv.Grid.Left[3] +50, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "In USe"); + } + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + + IList->Edit[0].Show(); + IList->STextModuleInDefineType.Show(); + + DrawISCheckFault(); + + DrawPadBoardCfgList(); +} + +void TDirectPadCfg::PermissionCmdReturnDraw() +{ + int x,y; + Check4Selected(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawPadBoardCfgList(); +} + +void TDirectPadCfg::InitPanel() +{ + int x,y,x2,y2, aW,aH,i; + + x = 20; + y = 150; + x2 = 799; + y2 = 340; + aW = x2 - x +1; + aH = y2 -y +1; + + aPanel->Init(x,y,aW,aH,0,0,clMoneyGreen, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearWhite,clBlue); + if(LanguageEnCn==0) + aPanel->Caption.SetText("按中/EN键切换输入法,设置键保存更改,返回键放弃更改并返回",24); + else + aPanel->Caption.SetText("Key 中/EN To Switch Input Method,Key Set To Save",24); + aPanel->Caption.Enable = 1; + aPanel->Caption.Visible = 1; + + aPanel->SText[0].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0){ + TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr("Enter Numbers ", aPanel->SText[0].Text); + } + aPanel->SText[0].Enable = 1; + aPanel->SText[0].Visible = 1; + + aPanel->Edit[ 0].Init(10,40,420,30,x,y,1,clNearBlack); + aPanel->Edit[ 0].Str.FromStr(IList->EditDescpShow.Str.Text); + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 1; + } + + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn==0){ + TMyString::sFromStr("请根据以下输入法提示输入", aPanel->SText[0].Text); + }else{ + //TMyString::sFromStr("Pay Attention To The Tip", aPanel->SText[0].Text); + TMyString::sFromStr(" ", aPanel->SText[0].Text); + } + aPanel->SText[0].Show(); +} + + +void TDirectPadCfg::ClearSelected() +{ + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[0] +170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, 4, ItemColor); + break; + case 2: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + break; + case 3: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + break; + case 6: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 7: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[4] +12, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[4] +140, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + } +} + +void TDirectPadCfg::Check4Selected() +{ + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[0] +170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 2: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 3: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.SetPstTail(); + IList->EditDescpShow.Show(); + IList->EditDescpShow.ShowCursor(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 7: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[4] +12, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[4] +140, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + } +} + +TGuiMsgReturn TDirectPadCfg::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + unsigned char aP0; + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn SubRtnMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + int HadPrc = 0; + int iVal; + JustShowResult = 0; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + }else + if(EdittingDescp){ + const char *p; + if(aKey == dfKEY_SETUP){ + //Save and return + IList->EditDescpShow.Str.FromStr(this->aPanel->Edit[0].Str.Text); + IList->EditDescpShow.Show(); + EdittingDescp = 0; + Redraw4DescpEdit(); + }else + if(IsExtInput){ + if(aKey == dfKEY_ENCN){ + CnInput.KeyIn(aKey); + if(0){ + IsExtInput = 0; + CnInput.OverPrint(this->aPanel->Color); + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + aPanel->SText[0].Show(); + } + }else + if(aKey == VK_RETURN){ + //Just return + Redraw4DescpEdit(); + EdittingDescp = 0; + }else{ + if( (aKey == VK_DELETE) && (CnInput.sEdit.Pst == -1) ){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + }else{ + p = CnInput.KeyIn(aKey); + if(p != nullptr){ + if(CnInput.GotChar[0] != '\0'){ + aPanel->Edit[0].Pst = aPanel->Edit[0].Str.Insert(CnInput.GotChar, aPanel->Edit[0].Pst); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + } + } + } + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + break; + case dfKEY_ENCN: + if(IsExtInput == 0){ + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn==0){ + TMyString::sFromStr("当前根据输入法输入", aPanel->SText[0].Text); + }else{ + TMyString::sFromStr(" ", aPanel->SText[0].Text); + } + aPanel->SText[0].Show(); + } + break; + case VK_EXECUTE: + + break; + case VK_RETURN: + Redraw4DescpEdit(); + EdittingDescp = 0; + break; + } + } + }else{ + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx == 0){ + if(aKey == VK_RIGHT){ + if(IList->EditPortNum.Pst >= IList->EditPortNum.Str.GetEndPst()){ + ClearSelected(); + Tag.Inx = 1; + Check4Selected(); + HadPrc = 1; + } + } + if(HadPrc == 0){ + IList->EditPortNum.KeyIn(aKey); + iVal = IList->EditPortNum.Str.ToInteger(); + if( (iVal) && (iVal <= dDIRECTCTL_MAX_COUNT) ){ + IList->EditPortNum.SelectedColor = clBlue; + Path0Valid = 1; + }else{ + IList->EditPortNum.SelectedColor = clRed; + Path0Valid = 0; + } + if(Path0 != iVal){ + Path0 = iVal; + DrawState(); + ReLoadAndDrawDescp(); + DrawUserCodeAssignAreaAssignType(); + LoadCfg4Edit(Path0, Path1); + DrawPadBoardCfgList(); + } + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + } + }else + if(Tag.Inx == 1){ + if(VK_LEFT == aKey){ + if(Tag.Inx > Tag.InxMin){ + ClearSelected(); + Tag.Inx = 0; + Check4Selected(); + } + } + }else + if(Tag.Inx == 2){ + if(aKey == VK_RIGHT){ + if(IList->EditAddrNum.Pst >= IList->EditAddrNum.Str.GetEndPst()){ + ClearSelected(); + Tag.Inx = 3; + Check4Selected(); + HadPrc = 1; + } + } + if(HadPrc == 0){ + IList->EditAddrNum.KeyIn(aKey); + iVal = IList->EditAddrNum.Str.ToInteger(); + if( (iVal) && (iVal <= dDIRECTCTL_KEY_MAX_COUNT) ){ + IList->EditAddrNum.SelectedColor = clBlue; + Path1Valid =1; + }else{ + IList->EditAddrNum.SelectedColor = clRed; + Path1Valid = 0; + } + if(Path1 != iVal){ + Path1 = iVal; + DrawState(); + ReLoadAndDrawDescp(); + DrawUserCodeAssignAreaAssignType(); + LoadCfg4Edit(Path0, Path1); + } + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + } + }else + if(Tag.Inx == 3){ + //DescpShow + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx = 2; + Check4Selected(); + HadPrc =1; + } + }else + if(Tag.Inx == 4){ + //User Code + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + }else + if(Tag.Inx == 5){ + //Area + IList->EditAreaAssign.KeyIn(aKey); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + }else + if(Tag.Inx == 6){ + //Define Type + IList->Edit[0].KeyIn(aKey); + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal > 255) || (iVal <0) ){ + iVal = 0; + IList->Edit[0].SelectedColor = clRed; + IList->STextModuleInDefineType.SetText(" ",24); + }else{ + IList->Edit[0].SelectedColor = clBlue; + if(LanguageEnCn==0) + IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + else + IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + } + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + IList->STextModuleInDefineType.Show(); + }else + if(Tag.Inx == 8){ + //Define Type + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx = 9; + Check4Selected(); + } + }else + if(Tag.Inx == 9){ + //Define Type + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx = 8; + Check4Selected(); + } + } + break; + case VK_UP: + if(Tag.Inx > Tag.InxMin){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx =9; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx < 9){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx = Tag.InxMin; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case dfKEY_ENCN: + + break; + case dfKEY_SETUP: + if(Tag.Inx == 1){ + Rt.IsPadDeActive = Rt.IsPadDeActive ? 0 : 1; + DrawIsPadDeActive(); + }else + if(Tag.Inx == 3){ + PermissionCmd = CmdEditDescp; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 7){ + Rt.IsCheckFault = Rt.IsCheckFault ? 0 : 1; + DrawISCheckFault(); + }else + if( (Tag.Inx == 8) || (Tag.Inx == 9) ){ + Rt.IsNodeUsing = Rt.IsNodeUsing ? 0 : 1; + DrawIsNodeUsing(); + } + break; + case VK_F2: + + break; + case VK_EXECUTE: + if( (Path0) && (Path1) && (Path0 <= dDIRECTCTL_MAX_COUNT) && (Path1 <=dDIRECTCTL_KEY_MAX_COUNT) ) { + if(Tag.Inx == 1){ + //Save CFG - PadActive, + ResultPst = 0; + PermissionCmd = CmdWriteCfg; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 3){ + PermissionCmd = CmdWriteDescp; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 4){ + //Save UserCode + PermissionCmd = CmdWriteUserCode; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 5){ + //Save Area Code + PermissionCmd = CmdWriteAreaCode; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 6){ + //Save Assign Type + PermissionCmd = CmdWriteAssignType; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 7){ + //Save CFG - + ResultPst = 3; + PermissionCmd = CmdWriteCfg; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if( (Tag.Inx == 8) || (Tag.Inx == 9) ){ + //Save CFG - + ResultPst = 4; + PermissionCmd = CmdWriteCfg; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + break; + } + + if(aKey == VK_RETURN){ + IsShow = 0; + aMsg = guiMsgReturn; + } + } + + if(JustShowResult ==0)TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, " "); + return aMsg; +} + +void TDirectPadCfg::PermissionCmdGO() +{ + int aVal, IsSaveFail; + TUserCode tUserCode; + IsSaveFail = 0; + switch(PermissionCmd){ + case CmdEditDescp: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + InitPanel(); + EdittingDescp = 1; + IsExtInput = 1; + break; + case CmdWriteUserCode: + case CmdWriteAreaCode: + case CmdWriteAssignType: + case CmdWriteCfg: + case CmdWriteDescp: + if( Path0 && Path1 && (Path0 <= dDIRECTCTL_MAX_COUNT) && (Path1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + aVal = IList->EditUserCode.Str.ToInteger(); + if( (aVal < 100000000) && (aVal>-1) ){ + tUserCode.Full = aVal; + WriteUserCode2Flash(Path0, Path1, tUserCode); + Record.ReadDirectPadUserSet(Path0); + if(aVal != DirectCtlBoard[Path0-1].UcList[Path1-1].Full){ + IsSaveFail = 1; + } + }else{ + IsSaveFail =1; + } + }else{ + IsSaveFail =1; + } + if( Path0 && Path1 && (Path0 <= dDIRECTCTL_MAX_COUNT) && (Path1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + aVal = IList->Edit[0].Str.ToInteger(); + if( (aVal < 256) && (aVal>-1) ){ + const unsigned char aAssignType = static_cast(aVal); + WriteAssignType2Flash(Path0, Path1, aAssignType); + Record.ReadDirectPadUserSet(Path0); + if(aVal != DirectCtlBoard[Path0-1].AssignType[Path1-1]){ + IsSaveFail = 2; + } + }else{ + IsSaveFail =2; + } + }else{ + IsSaveFail =2; + } + if(IsSaveFail ==1){ + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "用户码保存失败"); + }else{ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Failed To Save AuxID "); + } + ShowResultTick =5; + JustShowResult = 1; + return; + } + if(IsSaveFail ==2){ + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "类型保存失败 "); + }else{ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Failed To Save Type "); + } + ShowResultTick =5; + JustShowResult = 1; + return; + } + IList->EditUserCode.Str.FromUInt8Dg(DirectCtlBoard[Path0-1].UcList[Path1-1].Full); + IList->EditUserCode.Show(); + IList->Edit[0].Str.FromUInt3Dg(DirectCtlBoard[Path0-1].AssignType[Path1-1]); + IList->Edit[0].Show(); + //___________________________________________________________________________________________________________ + if( Path0 && Path1 && (Path0 <= dDIRECTCTL_MAX_COUNT) && (Path1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + aVal = IList->EditAreaAssign.Str.ToInteger(); + aVal &= 0x0000FFFF; + if(aVal < dAreaCountMax){ + AreaNum = aVal; + WriteAreaNum2Flash(Path0, Path1, AreaNum); + Record.ReadDirectPadAreaNum(); + if(aVal != DirectCtlBoard[Path0-1].Area[Path1-1]){ + IsSaveFail = 1; + } + IList->EditAreaAssign.Str.FromUInt4Dg(DirectCtlBoard[Path0-1].Area[Path1-1]); + IList->EditAreaAssign.Show(); + }else{ + IsSaveFail =1; + } + }else{ + IsSaveFail =1; + } + if(IsSaveFail){ + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "区域号指派失败"); + }else{ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Failed To Save Zone "); + } + ShowResultTick =5; + JustShowResult = 1; + return; + } + Write2Flash(Path0, Path1); + ReadDirectPadCfg(Path0); + if( (Rt.IsPadDeActive == DirectCtlBoard[Path0-1].PadIsProhibit) && (Rt.IsNodeUsing == DirectCtlBoard[Path0-1].IsRegisted[Path1-1]) && (Rt.IsCheckFault == DirectCtlBoard[Path0-1].IsCheckError[Path1-1]) ){ + + }else{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "配置保存失败 "); + }else{ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Failed To Save Configure "); + } + ShowResultTick =5; + JustShowResult = 1; + IsSaveFail =1; + } + LoadCfg4Edit(Path0, Path1); + DrawPadBoardCfgList(); + if(IsSaveFail)return; + + TMyString::sFromStr(IList->EditDescpShow.Str.Text, TextHasSave); + sRestoreDescp(Path0, Path1, IList->EditDescpShow.Str.Text); + WriteDescp2Flash(); + ReLoadAndDrawDescp(); + if(TMyString::sCompStr32Char(IList->EditDescpShow.Str.Text, TextHasSave) != 0){ + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "描述保存失败 "); + }else{ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Failed To Save Note "); + } + ShowResultTick =5; + IsSaveFail =1; + } + if(IsSaveFail)return; + + ShowResultTick =5; + JustShowResult = 1; + if(LanguageEnCn==0){ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "保存成功 "); + }else{ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, "Saved Completed "); + } + break; + } +} + +void TDirectPadCfg::WriteDescp2Flash() +{ + TDescpWrite::sWrite2Flash(dADDR_DIRECTPAD_START); +} + +void TDirectPadCfg::sWriteUserCodeAssignType(unsigned char aPath0) +{ + unsigned int fAddr; + unsigned int i; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1; + TDMix tCrc1,tCrc2; + + if(sIList==nullptr)return; + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (aPath0 >0) && (aPath0 <= dDIRECTCTL_MAX_COUNT) ){ + aP0 = aPath0 -1; + sIList->ReadWriteData.Reset(); + fAddr = dFlashAddrDirectPadUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + sDelayMs(100); + + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + Crc32Reset(); + for(x=0;xReadWriteData.D32[x] = DirectCtlBoard[aP0].UcList[x].Full; + Crc32Feed(sIList->ReadWriteData.D32[x]); + } + tCrc1.D32 = Crc32GetResult(); + + Crc32Reset(); + for(x=0;xReadWriteData.D8[x + 32] = DirectCtlBoard[aP0].AssignType[x]; + Crc32Feed(static_cast(sIList->ReadWriteData.D8[x + 32])); + } + tCrc2.D32 = Crc32GetResult(); + + sIList->ReadWriteData.D8[32+8 +0] =tCrc1.D8[0]; + sIList->ReadWriteData.D8[32+8 +1] =tCrc1.D8[1]; + sIList->ReadWriteData.D8[32+8 +2] =tCrc1.D8[2]; + sIList->ReadWriteData.D8[32+8 +3] =tCrc1.D8[3]; + sIList->ReadWriteData.D8[32+8 +4] =tCrc2.D8[0]; + sIList->ReadWriteData.D8[32+8 +5] =tCrc2.D8[1]; + sIList->ReadWriteData.D8[32+8 +6] =tCrc2.D8[2]; + sIList->ReadWriteData.D8[32+8 +7] =tCrc2.D8[3]; + + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } +} + +void TDirectPadCfg::WriteUserCode2Flash(unsigned char aPath0, unsigned char aPath1, TUserCode aUc) +{ + unsigned char aP0, aP1; + + //Erase 1 * 4K Blocks + if( (aPath0 >0) && (aPath0 <= dDIRECTCTL_MAX_COUNT) ){ + if( (aPath1 >0) && (aPath1 <= dDIRECTCTL_KEY_MAX_COUNT) ){ + aP0 = aPath0 -1; + aP1 = aPath1 -1; + DirectCtlBoard[aP0].UcList[aP1].Full = aUc.Full; + sIList = IList; + sWriteUserCodeAssignType(aPath0); + } + } +} + +void TDirectPadCfg::WriteAssignType2Flash(unsigned char aPath0, unsigned char aPath1, unsigned char aAssignType) +{ + unsigned char aP0, aP1; + + //Erase 1 * 4K Blocks + if( (aPath0 >0) && (aPath0 <= dDIRECTCTL_MAX_COUNT) ){ + if( (aPath1 >0) && (aPath1 <= dDIRECTCTL_KEY_MAX_COUNT) ){ + aP0 = aPath0 -1; + aP1 = aPath1 -1; + DirectCtlBoard[aP0].AssignType[aP1] = aAssignType; + sIList = IList; + sWriteUserCodeAssignType(aPath0); + } + } +} + +void TDirectPadCfg::sWrite2Flash(unsigned char aPath0) +{ + unsigned int fAddr; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1; + TDMix tCrc; + + if(sIList==nullptr)return; + sIList->ReadWriteData.Reset(); + + if(aPath0 == 0)return; + if(aPath0 > dDIRECTCTL_MAX_COUNT)return; + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlashDirectPadLnkChipX); + }while(GetSta); + + //Erase 1 * 4K Blocks + aP0 = aPath0 -1; + fAddr = dFlashAddrDirectPadLnk + (aP0 * 4096); + nor_erase_sector_4k(dFlashDirectPadLnkChipX,fAddr); + sDelayMs(100); + + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlashDirectPadLnkChipX); + }while(GetSta); + Crc32Reset(); + for(x=0;xReadWriteData.D8[x*8 +0] = DirectCtlBoard[aP0].IsRegisted[x]; + sIList->ReadWriteData.D8[x*8 +1] = DirectCtlBoard[aP0].IsCheckError[x]; + sIList->ReadWriteData.D8[x*8 +2] = 0; + sIList->ReadWriteData.D8[x*8 +3] = 0; + sIList->ReadWriteData.D8[x*8 +4] = 0; + sIList->ReadWriteData.D8[x*8 +5] = 0; + sIList->ReadWriteData.D8[x*8 +6] = 0; + sIList->ReadWriteData.D8[x*8 +7] = DirectCtlBoard[aP0].PadIsProhibit; + + Crc32Feed(static_cast(DirectCtlBoard[aP0].IsRegisted[x])); + Crc32Feed(static_cast(DirectCtlBoard[aP0].IsCheckError[x])); + Crc32Feed(static_cast(DirectCtlBoard[aP0].PadIsProhibit)); + } + tCrc.D32 = Crc32GetResult(); + sIList->ReadWriteData.D32[dDIRECTCTL_KEY_MAX_COUNT*2+0] = tCrc.D32; + fAddr = dFlashAddrDirectPadLnk + (aP0 * 4096); + nor_write_page(dFlashDirectPadLnkChipX, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlashDirectPadLnkChipX); + }while(GetSta); +} + +void TDirectPadCfg::Write2Flash(unsigned char aPath0, unsigned char aPath1) +{ + unsigned int fAddr; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1; + TDMix tCrc; + + if(aPath0 == 0)return; + if(aPath0 > dDIRECTCTL_MAX_COUNT)return; + if(aPath1 == 0)return; + if(aPath1 > dDIRECTCTL_KEY_MAX_COUNT)return; + + aP0 = aPath0-1; + aP1 = aPath1-1; + + DirectCtlBoard[aP0].IsRegisted[aP1] = Rt.IsNodeUsing;; + DirectCtlBoard[aP0].IsCheckError[aP1] = Rt.IsCheckFault; + //DirectCtlBoard[aP0].IsPump[aP1]=0; + DirectCtlBoard[aP0].IsProhibitLinkage[aP1]=0; + DirectCtlBoard[aP0].IsOutputState[aP1]=0; + DirectCtlBoard[aP0].PadIsProhibit = Rt.IsPadDeActive; + + sIList=IList; + sWrite2Flash(aPath0); +} + +void TDirectPadCfg::ReadDirectPadCfg(unsigned char aPath0) +{ + Record.LoadDirectPadCfg(aPath0); +} + +void TDirectPadCfg::DrawIsPadDeActive() +{ + if(Rt.IsPadDeActive){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] + 170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[0] + 170, Lv.Grid.Top[0] + 6, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + } +} + +void TDirectPadCfg::DrawIsNodeUsing() +{ + if(Rt.IsNodeUsing){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[4] + 12, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[4] + 140, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[4] + 12, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[4] + 140, Lv.Grid.Top[4] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + } +} + +void TDirectPadCfg::DrawISCheckFault() +{ + if(Rt.IsCheckFault){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDirectPadCfg::LoadCfg4Edit(unsigned char aPath0, unsigned aPath1) +{ + unsigned char aP0, aP1; + if(aPath0 == 0)return; + if(aPath0 > dDIRECTCTL_MAX_COUNT)return; + if(aPath1 == 0)return; + if(aPath1 > dDIRECTCTL_KEY_MAX_COUNT)return; + + aP0 = aPath0 -1; + aP1 = aPath1 -1; + + Rt.IsPadDeActive = DirectCtlBoard[aP0].PadIsProhibit; + Rt.IsNodeUsing = DirectCtlBoard[aP0].IsRegisted[aP1]; + Rt.IsCheckFault = DirectCtlBoard[aP0].IsCheckError[aP1]; + + DrawIsPadDeActive(); + DrawIsNodeUsing(); + DrawISCheckFault(); +} + +void TDirectPadCfg::sWriteAreaNum() +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + TDMix tCrc; + + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + + if(sIList==nullptr)return; + sIList->ReadWriteData.Reset(); + + //Erase 1 * 4K Blocks + fAddr = dFlash4DevAreaNum + (40 / 8 * 4096); + nor_erase_sector_4k(dFlash4DevAreaNumChip,fAddr); + sDelayMs(100); + + LoopCheck1S(); + + do{ + sDelayMs(10); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + for(i=0; i<10; i++){ + Crc32Reset(); + for(x=0;xReadWriteData.D16[i*(dDIRECTCTL_KEY_MAX_COUNT+2) + x] = DirectCtlBoard[i].Area[x]; + Crc32Feed(static_cast(DirectCtlBoard[i].Area[x])); + } + tCrc.D32 = Crc32GetResult(); + sIList->ReadWriteData.D16[i*(dDIRECTCTL_KEY_MAX_COUNT+2) + dDIRECTCTL_KEY_MAX_COUNT +0] = tCrc.D16[0]; + sIList->ReadWriteData.D16[i*(dDIRECTCTL_KEY_MAX_COUNT+2) + dDIRECTCTL_KEY_MAX_COUNT +1] = tCrc.D16[1]; + + } + fAddr = dFlash4DevAreaNum + (40 * 512) + (0 * 256); + nor_write_page(dFlash4DevAreaNumChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + + for(i=10; i<20; i++){ + Crc32Reset(); + for(x=0;xReadWriteData.D16[(i-10)*(dDIRECTCTL_KEY_MAX_COUNT+2) + x] = DirectCtlBoard[i].Area[x]; + Crc32Feed(static_cast(DirectCtlBoard[i].Area[x])); + } + tCrc.D32 = Crc32GetResult(); + sIList->ReadWriteData.D16[(i-10)*(dDIRECTCTL_KEY_MAX_COUNT+2) + dDIRECTCTL_KEY_MAX_COUNT +0] = tCrc.D16[0]; + sIList->ReadWriteData.D16[(i-10)*(dDIRECTCTL_KEY_MAX_COUNT+2) + dDIRECTCTL_KEY_MAX_COUNT +1] = tCrc.D16[1]; + } + fAddr = dFlash4DevAreaNum + (40 * 512) + (1 * 256); + nor_write_page(dFlash4DevAreaNumChip, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(5); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); +} + +void TDirectPadCfg::WriteAreaNum2Flash(unsigned char aPath0, unsigned char aAddr, unsigned short aNum) +{ + unsigned char aP0, aP1; + + if(aPath0 <1)return; + if(aPath0 >dDIRECTCTL_MAX_COUNT)return; + if(aAddr <1)return; + if(aAddr >dDIRECTCTL_KEY_MAX_COUNT)return; + + aP0 = aPath0 -1; + aP1 = aAddr -1; + DirectCtlBoard[aP0].Area[aP1] = aNum; + sIList = IList; + sWriteAreaNum(); +} + +void TDirectPadCfg::Task1000Ms() +{ + if(IsShow){ + DrawState(); + if(ShowResultTick){ + ShowResultTick--; + if(ShowResultTick == 0){ + TextRender_string24(Lv.PanelSmall.Left+ 10, Lv.PanelSmall.Top +2, clNearWhite, ItemColor, " "); + } + } + } +} + + +void TDirectPadCfg::sRecoverSetDefault() +{ + unsigned int fAddr; + unsigned int i; + volatile unsigned int x, GetSta; + + SysLoopTick = 0; + do{ + sDelayMs(3); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + + //Cfg + for(i=0; i楼层显示设置", Caption.Text); + Caption.Show(); +} + +void TDisplayPadCfg::Show() +{ + DrawSelf(); + DrawCaption(); + TextRender_string24(80, 360 ,clNearBlack, "1.TAB键更改回路号,设置键上一个层显,查询键下一个层显"); + TextRender_string24(80, 400 ,clNearBlack, "2.上下左右数字键编辑地址段,按确定键保存"); +} + +void TDisplayPadCfg::ShowSta() +{ + if(Sta == 0){ + TextRender_string24(560, 92, clNearBlack, clFrmFace, " "); + }else + if(Sta == 1){ + TextRender_string24(560, 92, clNearBlack, clFrmFace, "保存成功 "); + } +} + +void TDisplayPadCfg::ShowSta(int aSta) +{ + Sta = aSta; + ShowSta(); + +} + +void TDisplayPadCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + Show(); + aPanel->Show(); + ShowSta(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + ShowSta(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDisplayPadCfg::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickEdit[i].Selected = 0; + } + if( (CtlIndex > 10) && (CtlIndex < 23) ){ + aPanel->Edit[CtlIndex].Selected = 1; + } + +} + +void TDisplayPadCfg::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + + RectPanel.Set(80,80, 720, 350); + + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[0].Init(20,0,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[1].Init(AddrLeft[0]+6,AddrTop[1],70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[2].Init(AddrLeft[0]+6,AddrTop[2],70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[3].Init(AddrLeft[0]+6,AddrTop[3],70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[4].Init(AddrLeft[1]+6,88,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[5].Init(AddrLeft[1]+122,88,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[6].Init(AddrLeft[1]+236,88,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[7].Init(AddrLeft[1]+356,88,70,30,x,yt,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路 层显地址 描述字", aPanel->SText[0].Text); + TMyString::sFromStr("匹配段1", aPanel->SText[1].Text); + TMyString::sFromStr("匹配段2", aPanel->SText[2].Text); + TMyString::sFromStr("匹配段3", aPanel->SText[3].Text); + TMyString::sFromStr("机器号", aPanel->SText[4].Text); + TMyString::sFromStr("回路号", aPanel->SText[5].Text); + TMyString::sFromStr("开始地址", aPanel->SText[6].Text); + TMyString::sFromStr("结束地址", aPanel->SText[7].Text); + for(i=0; i<8;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + + aPanel->Edit[0].Init(26 ,36 + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(104,36 + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(200,36 + 1,390,30,x,yt,clNearBlack,clNearWhite); + + for(i=0; i<2;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + aPanel->Edit[i].Pst = 2; + aPanel->Edit[i].Selected = 0; + } + aPanel->Edit[2].Enable = 0; + aPanel->Edit[2].Visible = 1; + aPanel->Edit[2].SetMaxLen(34); + aPanel->Edit[2].Str.FromStr("未加载"); + + aPanel->Edit[11].Init(AddrLeft[1] + 26,AddrTop[1] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[12].Init(AddrLeft[2] + 32,AddrTop[1] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[13].Init(AddrLeft[3] + 36,AddrTop[1] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[14].Init(AddrLeft[4] + 32,AddrTop[1] + 1,48,30,x,yt,clNearBlack,clNearWhite); + + aPanel->Edit[15].Init(AddrLeft[1] + 26,AddrTop[2] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[16].Init(AddrLeft[2] + 32,AddrTop[2] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[17].Init(AddrLeft[3] + 36,AddrTop[2] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[18].Init(AddrLeft[4] + 32,AddrTop[2] + 1,48,30,x,yt,clNearBlack,clNearWhite); + + aPanel->Edit[19].Init(AddrLeft[1] + 26,AddrTop[3] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[20].Init(AddrLeft[2] + 32,AddrTop[3] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[21].Init(AddrLeft[3] + 36,AddrTop[3] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[22].Init(AddrLeft[4] + 32,AddrTop[3] + 1,48,30,x,yt,clNearBlack,clNearWhite); + + for(i=11; i<23;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].Str.FromStr("000"); + aPanel->Edit[i].Pst = 2; + aPanel->Edit[i].Selected = 0; + } + + aPanel->Edit[11].SetMaxLen(2); + aPanel->Edit[11].Str.FromStr("00"); + aPanel->Edit[11].Pst = 1; + aPanel->Edit[12].SetMaxLen(2); + aPanel->Edit[12].Str.FromStr("00"); + aPanel->Edit[12].Pst = 1; + aPanel->Edit[15].SetMaxLen(2); + aPanel->Edit[15].Str.FromStr("00"); + aPanel->Edit[15].Pst = 1; + aPanel->Edit[16].SetMaxLen(2); + aPanel->Edit[16].Str.FromStr("00"); + aPanel->Edit[16].Pst = 1; + aPanel->Edit[19].SetMaxLen(2); + aPanel->Edit[19].Str.FromStr("00"); + aPanel->Edit[19].Pst = 1; + aPanel->Edit[20].SetMaxLen(2); + aPanel->Edit[20].Str.FromStr("00"); + aPanel->Edit[20].Pst = 1; + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + x = RectPanel.Left; + y = RectPanel.Top; + for(i=0; i<6; i++){ + VertLineRender(AddrLeft[i] + 80, y + AddrTop[0], 166, clGray); + } + for(i=0; i<5; i++){ + HorizLineRender(AddrLeft[0] + 80, y + AddrTop[i], 570, clGray); + } + + FindNextPadViaCircuit(); +} + +void TDisplayPadCfg::DrawItem() +{ + unsigned int fAddr, iP0, iP1; + if(Loaded.P0Found){ + aPanel->Edit[0].Str.FromUInt2Dg(Loaded.P0); + if(Loaded.P1Found){ + iP0 = Loaded.P0 -1; + iP1 = Loaded.P1 -1; + fAddr = dAddrSdRam_Descp + (iP0 * 8192) + (iP1 * 32); + aPanel->Edit[1].Str.FromUInt3Dg(Loaded.P1); + ReadWriteData.D32[0] = *(volatile unsigned int *)(fAddr + 0); + ReadWriteData.D32[1] = *(volatile unsigned int *)(fAddr + 4); + ReadWriteData.D32[2] = *(volatile unsigned int *)(fAddr + 8); + ReadWriteData.D32[3] = *(volatile unsigned int *)(fAddr + 12); + ReadWriteData.D32[4] = *(volatile unsigned int *)(fAddr + 16); + ReadWriteData.D32[5] = *(volatile unsigned int *)(fAddr + 20); + ReadWriteData.D32[6] = *(volatile unsigned int *)(fAddr + 24); + ReadWriteData.D32[7] = *(volatile unsigned int *)(fAddr + 28); + ReadWriteData.D32[8] = 0; + if(ReadWriteData.D8[0] == '\0'){ + aPanel->Edit[2].Str.FromStr("未定义描述字"); + }else{ + aPanel->Edit[2].Str.FromStr(ReadWriteData.D8); + } + + LoadData(); + } + }else{ + aPanel->Edit[0].Str.FromStr("xx"); + aPanel->Edit[1].Str.FromStr("xxx"); + } + + aPanel->Edit[0].Show(); + aPanel->Edit[1].Show(); + aPanel->Edit[2].Show(); +} + +int TDisplayPadCfg::FindNextPadViaCircuit() +{ + int i,x; + unsigned char aP0 = Loaded.P0; + unsigned char InxCount; + unsigned int aAddr; + Loaded.P0Found = 0; + aP0--; + if(aP0 >= dPORT_MAX_COUNT)aP0 = 0; + for(i=0; i= dPORT_MAX_COUNT)aP0 = 0; + if(Port[aP0].DisplayPadCount >0){ + InxCount = Port[aP0].DisplayPadCount; + if(InxCount > dDISPLAYPAD_MAX_COUNT){ + InxCount = dDISPLAYPAD_MAX_COUNT; + } + Loaded.P0 = aP0+1; + Loaded.P0Found = 1; + break; + } + } + if(Loaded.P0Found){ + Loaded.Inx = 0; + Loaded.P1 = Port[aP0].DisplayPadAddr[Loaded.Inx]; + Loaded.P1Found = 1; + } + + aP0 = Loaded.P0Found -1; + if(Loaded.P0Found && Loaded.P1Found){ + if(aP0 <= dPORT_MAX_COUNT){ + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + ((Loaded.P1-1) * 32); + for(i=0; i<32; i++){ + aPanel->Edit[2].Str.Text[i] = *(volatile unsigned char *)(aAddr + i); + } + aPanel->Edit[2].Str.Text[32] = '\0'; + }else{ + aPanel->Edit[2].Str.Clear(); + } + }else{ + aPanel->Edit[2].Str.Clear(); + } + + DrawItem(); + return 0; +} + +int TDisplayPadCfg::FindPrvPadViaAddr() +{ + int i,x,Inx; + unsigned char InxCount; + unsigned char aP0 = Loaded.P0; + unsigned int aAddr; + aP0--; + if(aP0 < dPORT_MAX_COUNT){ + if(Loaded.P0Found){ + Inx = Loaded.Inx; + InxCount = Port[aP0].DisplayPadCount; + if(InxCount > dDISPLAYPAD_MAX_COUNT){ + InxCount = dDISPLAYPAD_MAX_COUNT; + } + for(x=0; xEdit[2].Str.Text[i] = *(volatile unsigned char *)(aAddr + i); + } + aPanel->Edit[2].Str.Text[32] = '\0'; + }else{ + aPanel->Edit[2].Str.Clear(); + } + }else{ + aPanel->Edit[2].Str.Clear(); + } + + DrawItem(); + return 0; +} + +int TDisplayPadCfg::FindNextPadViaAddr() +{ + int i,x,Inx; + unsigned char InxCount; + unsigned char aP0 = Loaded.P0; + unsigned int aAddr; + aP0--; + Loaded.P1Found = 0; + if(aP0 < dPORT_MAX_COUNT){ + if(Loaded.P0Found){ + Inx = Loaded.Inx; + InxCount = Port[aP0].DisplayPadCount; + if(InxCount > dDISPLAYPAD_MAX_COUNT){ + InxCount = dDISPLAYPAD_MAX_COUNT; + } + for(x=0; x= InxCount)Inx = 0; + if(Port[aP0].DisplayPadAddr[Inx]){ + Loaded.Inx = Inx; + Loaded.P1 = Port[aP0].DisplayPadAddr[Inx]; + Loaded.P1Found = 1; + break; + } + } + } + } + + aP0 = Loaded.P0Found -1; + if(Loaded.P0Found && Loaded.P1Found){ + if(aP0 <= dPORT_MAX_COUNT){ + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + ((Loaded.P1-1) * 32); + for(i=0; i<32; i++){ + aPanel->Edit[2].Str.Text[i] = *(volatile unsigned char *)(aAddr + i); + } + aPanel->Edit[2].Str.Text[32] = '\0'; + }else{ + aPanel->Edit[2].Str.Clear(); + } + }else{ + aPanel->Edit[2].Str.Clear(); + } + + DrawItem(); + return 0; +} + +void TDisplayPadCfg::LoadData() +{ + int i; + unsigned char aP0 = Loaded.P0; + aP0--; + if(aP0 < dPORT_MAX_COUNT){ + //AddrAssign[0].CtlNum = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[0].CtlNum; + //AddrAssign[0].Path0 = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[0].P0; + //AddrAssign[0].BeginAddr = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[0].BeginAddr; + //AddrAssign[0].EndAddr = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[0].EndAddr; + //AddrAssign[1].CtlNum = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].CtlNum; + //AddrAssign[1].Path0 = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].P0; + //AddrAssign[1].BeginAddr = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].BeginAddr; + //AddrAssign[1].EndAddr = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].EndAddr; + //AddrAssign[2].CtlNum = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].CtlNum; + //AddrAssign[2].Path0 = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].P0; + //AddrAssign[2].BeginAddr = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].BeginAddr; + //AddrAssign[2].EndAddr = DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].EndAddr; + + aPanel->Edit[11].Str.FromUInt2Dg(AddrAssign[0].CtlNum); + aPanel->Edit[12].Str.FromUInt2Dg(AddrAssign[0].Path0); + aPanel->Edit[13].Str.FromUInt3Dg(AddrAssign[0].BeginAddr); + aPanel->Edit[14].Str.FromUInt3Dg(AddrAssign[0].EndAddr); + + aPanel->Edit[15].Str.FromUInt2Dg(AddrAssign[1].CtlNum); + aPanel->Edit[16].Str.FromUInt2Dg(AddrAssign[1].Path0); + aPanel->Edit[17].Str.FromUInt3Dg(AddrAssign[1].BeginAddr); + aPanel->Edit[18].Str.FromUInt3Dg(AddrAssign[1].EndAddr); + + aPanel->Edit[19].Str.FromUInt2Dg(AddrAssign[2].CtlNum); + aPanel->Edit[20].Str.FromUInt2Dg(AddrAssign[2].Path0); + aPanel->Edit[21].Str.FromUInt3Dg(AddrAssign[2].BeginAddr); + aPanel->Edit[22].Str.FromUInt3Dg(AddrAssign[2].EndAddr); + + for(i=11; i<23; i++){ + aPanel->Edit[i].Show(); + } + } +} + +void TDisplayPadCfg::SaveData() +{ + unsigned char aP0; + aP0 = Loaded.P0; + aP0--; + if(aP0 < dPORT_MAX_COUNT){ + AddrAssign[0].CtlNum = aPanel->Edit[11].Str.ToInteger(); + AddrAssign[0].Path0 = aPanel->Edit[12].Str.ToInteger(); + AddrAssign[0].BeginAddr = aPanel->Edit[13].Str.ToInteger(); + AddrAssign[0].EndAddr = aPanel->Edit[14].Str.ToInteger(); + AddrAssign[1].CtlNum = aPanel->Edit[15].Str.ToInteger(); + AddrAssign[1].Path0 = aPanel->Edit[16].Str.ToInteger(); + AddrAssign[1].BeginAddr = aPanel->Edit[17].Str.ToInteger(); + AddrAssign[1].EndAddr = aPanel->Edit[18].Str.ToInteger(); + AddrAssign[2].CtlNum = aPanel->Edit[19].Str.ToInteger(); + AddrAssign[2].Path0 = aPanel->Edit[20].Str.ToInteger(); + AddrAssign[2].BeginAddr = aPanel->Edit[21].Str.ToInteger(); + AddrAssign[2].EndAddr = aPanel->Edit[22].Str.ToInteger(); + + //DisplayPadRt.Entry[Loaded.P0-1][Loaded.Inx].Spl.UsingPath[0].CtlNum = AddrAssign[0].CtlNum; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[0].P0 = AddrAssign[0].Path0; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[0].BeginAddr = AddrAssign[0].BeginAddr; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[0].EndAddr = AddrAssign[0].EndAddr; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].CtlNum = AddrAssign[1].CtlNum; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].P0 = AddrAssign[1].Path0; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].BeginAddr = AddrAssign[1].BeginAddr; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[1].EndAddr = AddrAssign[1].EndAddr; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].CtlNum = AddrAssign[2].CtlNum; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].P0 = AddrAssign[2].Path0; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].BeginAddr = AddrAssign[2].BeginAddr; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.UsingPath[2].EndAddr = AddrAssign[2].EndAddr; + + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.ThisP0 = Loaded.P0; + //DisplayPadRt.Entry[aP0][Loaded.Inx].Spl.ThisP1 = Loaded.P1; + } +} + +TGuiMsgReturn TDisplayPadCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int uKey; + unsigned char aIndex; + char LastChr; + const char *p; + int i; + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + uKey = 0; + if(VK_LEFT == aKey){ + switch(CtlIndex){ + case 12: + case 13: + case 14: + case 16: + case 17: + case 18: + case 20: + case 21: + case 22: + if(aPanel->Edit[CtlIndex].Pst < 0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + uKey = 1; + } + break; + } + } + if(VK_RIGHT == aKey){ + switch(CtlIndex){ + case 11: + case 12: + case 15: + case 16: + case 19: + case 20: + if(aPanel->Edit[CtlIndex].Pst > 0){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + uKey = 1; + } + break; + case 13: + case 17: + case 21: + if(aPanel->Edit[CtlIndex].Pst > 1){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + uKey = 1; + } + break; + } + } + if(uKey == 0){ + for(i=11; i<23; i++){ + if(aPanel->Edit[i].Selected){ + aPanel->Edit[i].KeyIn(aKey); + aPanel->Edit[i].CorrectPst(); + aPanel->Edit[i].Show(); + } + } + } + break; + case VK_UP: + if(CtlIndex > 14){ + CtlIndex -= 4; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex < 19){ + CtlIndex += 4; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + FindNextPadViaCircuit(); + break; + case dfKEY_SETUP: + FindPrvPadViaAddr(); + break; + case dfKEY_QUERY: + FindNextPadViaAddr(); + break; + case VK_EXECUTE: + if(Loaded.P1Found){ + SaveData(); + Write2Flash(); + Record.ReadDisplayPadSet(); + LoadData(); + ShowSta(1); + } + break; + } + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + + } + + if(aKey != VK_EXECUTE){ + ShowSta(0); + } + + return aMsg; +} + + +void TDisplayPadCfg::Write2Flash() +{ + unsigned int fAddr; + unsigned int i; + unsigned int Piece4K; + volatile unsigned int x, wP0, GetSta; + unsigned char aP0; + + if(Loaded.P0Found && Loaded.P1Found){ + + }else{ + return; + } + + do{ + DelayMs(2); + GetSta = nor_get_busy_state(dFlashDisplayPadSetChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + aP0 = Loaded.P0; + aP0--; + if(aP0 < dPORT_MAX_COUNT){ + wP0 = aP0 & 0xF0; + Piece4K = aP0 / 16; + fAddr = dFlashDisplayPadSet + (Piece4K * 4096); + nor_erase_sector_4k(dFlashDisplayPadSetChip,fAddr); + DelayMs(100); + do{ + DelayMs(10); + GetSta = nor_get_busy_state(dFlashDisplayPadSetChip); + }while(GetSta); + + for(i=0; i<16; i++){ + for(x=0;x<16;x++){ + //ReadWriteData.D32[x*4 + 0] = DisplayPadRt.Entry[wP0 +i][x].D32[0]; + //ReadWriteData.D32[x*4 + 1] = DisplayPadRt.Entry[wP0 +i][x].D32[1]; + //ReadWriteData.D32[x*4 + 2] = DisplayPadRt.Entry[wP0 +i][x].D32[2]; + //ReadWriteData.D32[x*4 + 3] = DisplayPadRt.Entry[wP0 +i][x].D32[3]; + } + fAddr = dFlashDisplayPadSet + (Piece4K * 4096) + (i * 256); + nor_write_page(dFlashDisplayPadSetChip, fAddr, ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashDisplayPadSetChip); + }while(GetSta); + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/DisplayPadCfg.h b/MyCode/Gui/DisplayPadCfg.h new file mode 100644 index 0000000..92a4504 --- /dev/null +++ b/MyCode/Gui/DisplayPadCfg.h @@ -0,0 +1,119 @@ +#ifndef DISPLAYPADCFG_H_ +#define DISPLAYPADCFG_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "EditML.h" +#include "CtlPanel1.h" + +class TDisplayPadCfg{ + public: + TStaticText Caption; + + u32 Color; + + TRect Bound; + TRect Content; + TRect RectPanel; + class TCtlPanel1 *aPanel; + + unsigned char CtlIndex; + + struct{ + unsigned char CtlNum; + unsigned char Path0; + unsigned char BeginAddr; + unsigned char EndAddr; + }AddrAssign[3]; + struct{ + unsigned char P0; + unsigned char P1; + unsigned char P0Found; + unsigned char P1Found; + unsigned char Inx; + }Loaded; + + union{ + unsigned char D8[256]; + unsigned int D32[64]; + }ReadWriteData; + + int Sta; + public: + TDisplayPadCfg(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void RenderBackGround(void); + + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void DrawCaption(void); + void Show(); + void FullRedraw(int Prm); + void DelayMs(unsigned int aMs); + + void ShowSta(); + void ShowSta(int aSta); + + void DrawItem(); + + void LoadData(); + void SaveData(); + + void Check4Selected(); + + void InitPanel(); + int FindNextPadViaCircuit(); + int FindPrvPadViaAddr(); + int FindNextPadViaAddr(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void Write2Flash(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/DisplayPadDescpDownload.cpp b/MyCode/Gui/DisplayPadDescpDownload.cpp new file mode 100644 index 0000000..af0c5be --- /dev/null +++ b/MyCode/Gui/DisplayPadDescpDownload.cpp @@ -0,0 +1,1011 @@ +#include "RuntimeData.h" +#include "DevProperty.h" +#include "DisplayPadDescpDownload.h" +#include "DevMask.h" +#include "server.h" + + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" + #include "fdcan_task.h" + #include "uart_key_drv.h" +} + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +static const short svGrid1X[8] = { + 16, 128, 246, 392, 600, 620, 630, 640 +}; + +void TDisplayPadDescpDownload::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "工程->层显描述下载"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "选择要下载的类型"); + TextRender_string24(Lv.Grid.Left[0] +700, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "后台运行"); + TextRender_string24(svGrid1X[0] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "烟感"); + TextRender_string24(svGrid1X[1] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "温感"); + TextRender_string24(svGrid1X[2] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "手报"); + TextRender_string24(svGrid1X[3] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "输入模块"); + TextRender_string24(svGrid1X[4] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "输入输出模块"); + + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "层显回路号"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "层显地址号"); + + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "注释起始回路"); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "注释起始地址"); + + TextRender_string24(Lv.Grid.Left[3] +16, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "注释结束回路"); + TextRender_string24(Lv.Grid.Left[3] +16, Lv.Grid.Top[3] + 38, clNearWhite, ItemColor, "注释结束地址"); + + if(State == Idle){ + Tag.Inx = 0; + Tag.InxItem = 0; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +16, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, "开始下载", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +154, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, "结束下载", 14, clNearBlack); + }else{ + Tag.Inx = 8; + Tag.InxItem = 0; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +16, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, "开始下载", 14, clSilver); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +154, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, "结束下载", 14, clNearBlack); + } + + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Project->Download Descp To Display Pad"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "Selecte Dev Types"); + TextRender_string24(Lv.Grid.Left[0] +700, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "BackEnd"); + TextRender_string24(svGrid1X[0] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "Smoke"); + TextRender_string24(svGrid1X[1] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "Tempe"); + TextRender_string24(svGrid1X[2] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "Hand Pad"); + TextRender_string24(svGrid1X[3] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "Output Module"); + TextRender_string24(svGrid1X[4] + 32, Lv.Grid.Top[0] + 36, clNearWhite, ItemColor, "In&Out Module"); + + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "Loop Display"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "Addr Display"); + + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "Loop Begin"); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "Addr Begin"); + + TextRender_string24(Lv.Grid.Left[3] +16, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "Loop End"); + TextRender_string24(Lv.Grid.Left[3] +16, Lv.Grid.Top[3] + 38, clNearWhite, ItemColor, "Addr End"); + + if(State == Idle){ + Tag.Inx = 0; + Tag.InxItem = 0; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +16, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, "Download", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +154, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, " Stop ", 14, clNearBlack); + }else{ + Tag.Inx = 8; + Tag.InxItem = 0; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +16, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, "Download", 14, clSilver); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +154, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite," Stop ", 14, clNearBlack); + } + } +} + +void TDisplayPadDescpDownload::Init() +{ + IsPermission =0; + SelectedList.Reset(); + DpPort = 1; + DpAddr = 1; + StartPort =1; + EndPort = 2; + StartAddr = 1; + EndAddr = 250; + State = Idle; + Tag.Inx = 0; + Tag.InxItem = 0; + WriteResult =0; + pPanel = nullptr; +} + +void TDisplayPadDescpDownload::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDisplayPadDescpDownload::DrawSelf(void) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Init(Lv.Grid.Left[1] +174, Lv.Grid.Top[1] + 2, 100,30,0,0,1,clNearBlack); + pPanel->Edit[0].SetMaxLen(2); + pPanel->Edit[0].Str.Clear(); + TMyString::sFrom2Dg(DpPort,Text); + pPanel->Edit[0].SetText(Text, 24); + pPanel->Edit[0].SetPstTail(); + pPanel->Edit[0].Show(); + + pPanel->Edit[1].Init(Lv.Grid.Left[1] +174, Lv.Grid.Top[1] + 38, 100,30,0,0,1,clNearBlack); + pPanel->Edit[1].SetMaxLen(3); + pPanel->Edit[1].Str.Clear(); + TMyString::sFrom3Dg(DpAddr,Text); + pPanel->Edit[1].SetText(Text, 24); + pPanel->Edit[1].Show(); + + pPanel->Edit[2].Init(Lv.Grid.Left[2] +174, Lv.Grid.Top[2] + 2, 100,30,0,0,1,clNearBlack); + pPanel->Edit[2].SetMaxLen(2); + pPanel->Edit[2].Str.Clear(); + TMyString::sFrom2Dg(StartPort,Text); + pPanel->Edit[2].SetText(Text, 24); + pPanel->Edit[2].Show(); + + pPanel->Edit[3].Init(Lv.Grid.Left[1] +174, Lv.Grid.Top[2] + 38, 100,30,0,0,1,clNearBlack); + pPanel->Edit[3].SetMaxLen(3); + pPanel->Edit[3].Str.Clear(); + TMyString::sFrom3Dg(StartAddr,Text); + pPanel->Edit[3].SetText(Text, 24); + pPanel->Edit[3].Show(); + + pPanel->Edit[4].Init(Lv.Grid.Left[2] +174, Lv.Grid.Top[3] + 2, 100,30,0,0,1,clNearBlack); + pPanel->Edit[4].SetMaxLen(2); + pPanel->Edit[4].Str.Clear(); + TMyString::sFrom2Dg(EndPort,Text); + pPanel->Edit[4].SetText(Text, 24); + pPanel->Edit[4].Show(); + + pPanel->Edit[5].Init(Lv.Grid.Left[1] +174, Lv.Grid.Top[3] + 38, 100,30,0,0,1,clNearBlack); + pPanel->Edit[5].SetMaxLen(3); + pPanel->Edit[5].Str.Clear(); + TMyString::sFrom3Dg(EndAddr,Text); + pPanel->Edit[5].SetText(Text, 24); + pPanel->Edit[5].Show(); + + DrawFixText(); + + DrawItemTypeSelected(); + + DrawPadList(); + + if(State == Writing)Tag.Inx =7; + Check4Selected(); + +} + +void TDisplayPadDescpDownload::Show() +{ + IsShow = 1; + DrawSelf(); +} + +void TDisplayPadDescpDownload::FullRedraw(int Prm) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iEdit[0].Show(); + pPanel->Edit[1].Show(); + pPanel->Edit[2].Show(); + pPanel->Edit[3].Show(); + pPanel->Edit[4].Show(); + pPanel->Edit[5].Show(); + + DrawItemTypeSelected(); + + DrawPadList(); + + Check4Selected(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); +} + +void TDisplayPadDescpDownload::PermissionCmdReturnDraw() +{ + RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawWriteResult(); +} + +void TDisplayPadDescpDownload::DrawItemTypeSelected() +{ + if(SelectedList.SenSmoker){ + TRoundSquare::sDrawBySize(svGrid1X[0], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(svGrid1X[0], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + if(SelectedList.SenTemper){ + TRoundSquare::sDrawBySize(svGrid1X[1], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(svGrid1X[1], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + if(SelectedList.HandPadReport){ + TRoundSquare::sDrawBySize(svGrid1X[2], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(svGrid1X[2], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + if(SelectedList.ModuleIn){ + TRoundSquare::sDrawBySize(svGrid1X[3], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(svGrid1X[3], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } + if(SelectedList.ModuleInout){ + TRoundSquare::sDrawBySize(svGrid1X[4], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(svGrid1X[4], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TDisplayPadDescpDownload::DrawWriteResult() +{ + if(IsShow == 0)return; + const int OffSet = 200; + if(LanguageEnCn==0){ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + if(State == Finished){ + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 2, clNearWhite, PanelColor, "传输完成"); + }else + if(State == Writing){ + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 2, clNearWhite, PanelColor, "正在传输"); + }else{ + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 2, clNearWhite, PanelColor, "无传输 "); + } + + TextRender_string24(Lv.Panel.Left +160, Lv.Panel.Top + 2, clNearWhite, PanelColor, "已用时(秒):"); + TextDigitRender8_24(Lv.Panel.Left +292, Lv.Panel.Top + 2, clNearWhite, PanelColor, RunData.WasteTime); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 32, clNearWhite, PanelColor, "总数量:"); + TextDigitRender5_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 32, clNearWhite, PanelColor, RunData.Total); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 62, clNearWhite, PanelColor, "当前写入回路号:"); + TextDigitRender2_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 62, clNearWhite, PanelColor, RunData.WritingPort); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 92, clNearWhite, PanelColor, "当前写入地址号:"); + TextDigitRender3_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 92, clNearWhite, PanelColor, RunData.WritingAddr); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 122, clNearWhite, PanelColor, "已写入数量:"); + TextDigitRender5_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 122, clNearWhite, PanelColor, RunData.WroteCount); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 152, clNearWhite, PanelColor, "写入失败数量:"); + TextDigitRender5_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 152, clRed, PanelColor, RunData.FailCount); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 182, clNearWhite, PanelColor, "重试次数:"); + TextDigitRender6_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 182, clNearWhite, PanelColor, RunData.TotalRetryTimes); + } + }else{ + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + if(State == Finished){ + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 2, clNearWhite, PanelColor, "Completed "); + }else + if(State == Writing){ + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 2, clNearWhite, PanelColor, "Transmiting"); + }else{ + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 2, clNearWhite, PanelColor, "IDLE "); + } + + TextRender_string24(Lv.Panel.Left +160, Lv.Panel.Top + 2, clNearWhite, PanelColor, "Waste Time:"); + TextDigitRender8_24(Lv.Panel.Left +292, Lv.Panel.Top + 2, clNearWhite, PanelColor, RunData.WasteTime); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 32, clNearWhite, PanelColor, "Total:"); + TextDigitRender5_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 32, clNearWhite, PanelColor, RunData.Total); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 62, clNearWhite, PanelColor, "Writing Loop:"); + TextDigitRender2_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 62, clNearWhite, PanelColor, RunData.WritingPort); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 92, clNearWhite, PanelColor, "Writing Addr:"); + TextDigitRender3_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 92, clNearWhite, PanelColor, RunData.WritingAddr); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 122, clNearWhite, PanelColor, "Been Finished:"); + TextDigitRender5_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 122, clNearWhite, PanelColor, RunData.WroteCount); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 152, clNearWhite, PanelColor, "Failed To Write:"); + TextDigitRender5_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 152, clRed, PanelColor, RunData.FailCount); + + TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 182, clNearWhite, PanelColor, "Retey Times:"); + TextDigitRender6_24(Lv.Panel.Left +OffSet, Lv.Panel.Top + 182, clNearWhite, PanelColor, RunData.TotalRetryTimes); + } + } +} + +void TDisplayPadDescpDownload::DrawPadList() +{ + unsigned char tP0, tP1; + int x,y, Cnt; + RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + if(LanguageEnCn==0)TextRender_string24(Lv.PanelSmall.Left + 6, Lv.PanelSmall.Top + 2, clNearWhite, SmallPanelColor, "回路层显地址:"); + else TextRender_string24(Lv.PanelSmall.Left + 6, Lv.PanelSmall.Top + 2, clNearWhite, SmallPanelColor, "List Of Disp:"); + tP0 = DpPort -1; + if(tP0 < dPORT_MAX_COUNT){ + Cnt = 0; + x = Lv.PanelSmall.Left + 6; + y = Lv.PanelSmall.Top + 2 + 32; + if(MainCtl.fData.Split.ExistTablePort[tP0]){ + for(tP1=0; tP1dPORT_MAX_COUNT)return; + if(EndPort>dPORT_MAX_COUNT)return; + if(StartAddr>dEP_MAX_COUNT_PER_PORT)return; + if(EndAddr>dEP_MAX_COUNT_PER_PORT)return; + + tP = StartPort; + tA = StartAddr; + for(;tP<=EndPort;tP++){ + tP0 = tP-1; + for(; tA= EndPort) && (tA >= EndAddr) ){ + return; + } + } + tA = 1; + } +} + +void TDisplayPadDescpDownload::DoTransmiting() +{ + int GoContinue =0; + int GoRetry =0; + int GoSend = 0; + unsigned char tP, tA, tP0, tP1; + if(RpyData.HasSend){ + //Wait + RpyData.WaitTick++; + if(RpyData.RecResult){ + if(RpyData.RecSta == 1){ + RpyData.HasSend =0; + GoContinue =1; + RunData.WroteCount++; + }else{ + if(RunData.RetryTimes < 3){ + RunData.RetryTimes++; + GoRetry =1; + RunData.TotalRetryTimes++; + }else{ + RpyData.HasSend =0; + GoContinue =1; + RunData.FailCount++; + } + } + }else + if(RpyData.WaitTick>10){ + if(RunData.RetryTimes < 3){ + RunData.RetryTimes++; + GoRetry =1; + RunData.TotalRetryTimes++; + }else{ + RpyData.HasSend =0; + GoContinue =1; + RunData.FailCount++; + } + } + }else{ + GoContinue =1; + } + + if(GoRetry){ + SendCmdWriteOnePoint(RunData.WritingPort, RunData.WritingAddr); + RpyData.HasSend =1; + } + + if(GoContinue){ + if( (RunData.WritingPort > EndPort) || ((RunData.WritingPort >= EndPort) && (RunData.WritingAddr > EndAddr)) ) { + State = Finished; + return; + } + RunData.RetryTimes =0; + if(1){ + if( (RunData.WritingPort == 0) || (RunData.WritingAddr ==0) ){ + tP = StartPort; + tA = StartAddr; + }else{ + tP = RunData.WritingPort; + tA = RunData.WritingAddr; + if(tA >= dEP_MAX_COUNT_PER_PORT){ + if(tP >= dPORT_MAX_COUNT){ + State = Finished; + return; + }else{ + tA =1; + tP++; + } + }else{ + tA++; + } + } + for(; tP<=EndPort; tP++){ + tP0 =tP-1; + for(; tA<=dEP_MAX_COUNT_PER_PORT; tA++){ + tP1 =tA-1; + if(SelectedList.SenSmoker){ + if(Port[tP0].dTypeTable[tP1] == dgTYPE_SMOKE_DETECTOR){ + GoSend =1; + } + } + if(SelectedList.SenTemper){ + if(Port[tP0].dTypeTable[tP1] == dgTYPE_TEMPE_DETECTOR){ + GoSend =1; + } + } + if(SelectedList.HandPadReport){ + if(Port[tP0].dTypeTable[tP1] == dgTYPE_HAND_REPORT){ + GoSend =1; + } + } + if(SelectedList.ModuleIn){ + if(Port[tP0].dTypeTable[tP1] == dgTYPE_IN_MODULE){ + GoSend =1; + } + } + if(SelectedList.ModuleInout){ + if( (Port[tP0].dTypeTable[tP1] == dgTYPE_INOUT_MODULE_NonSource) || + (Port[tP0].dTypeTable[tP1] == dgTYPE_INOUT_MODULE_Source) ){ + GoSend =1; + } + } + if(Port[tP0].dTypeTable[tP1] == 0) + GoSend =1; + if(GoSend){ + RunData.WritingPort = tP; + RunData.WritingAddr = tA; + SendCmdWriteOnePoint(RunData.WritingPort, RunData.WritingAddr); + RpyData.HasSend =1; + RpyData.WaitTick =0; + RpyData.RecSta =0; + RpyData.RecResult =0; + goto DoNothingReturnHere; + } + if( (tP > EndPort) || ((tP >= EndPort) && (tA > EndAddr)) ) { + State = Finished; + goto DoNothingReturnHere; + } + } + tA =1; + } + if( (tP > EndPort) || ((tP >= EndPort) && (tA > EndAddr)) ) { + State = Finished; + return; + } + DoNothingReturnHere: + return; + + } + } +} + +void TDisplayPadDescpDownload::ClearSelected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + switch(Tag.InxItem){ + case 0: TRoundSquare::sSelected(svGrid1X[0], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, ItemColor); break; + case 1: TRoundSquare::sSelected(svGrid1X[1], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, ItemColor); break; + case 2: TRoundSquare::sSelected(svGrid1X[2], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, ItemColor); break; + case 3: TRoundSquare::sSelected(svGrid1X[3], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, ItemColor); break; + case 4: TRoundSquare::sSelected(svGrid1X[4], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, ItemColor); break; + case 5: TRoundSquare::sSelected(svGrid1X[5], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, ItemColor); break; + } + break; + case 1: + pPanel->Edit[0].Selected = 0; + pPanel->Edit[0].SetPstTail(); + pPanel->Edit[0].Show(); + break; + case 2: + pPanel->Edit[1].Selected = 0; + pPanel->Edit[1].SetPstTail(); + pPanel->Edit[1].Show(); + break; + case 3: + pPanel->Edit[2].Selected = 0; + pPanel->Edit[2].SetPstTail(); + pPanel->Edit[2].Show(); + break; + case 4: + pPanel->Edit[3].Selected = 0; + pPanel->Edit[3].SetPstTail(); + pPanel->Edit[3].Show(); + break; + case 5: + pPanel->Edit[4].Selected = 0; + pPanel->Edit[4].SetPstTail(); + pPanel->Edit[4].Show(); + break; + case 6: + pPanel->Edit[5].Selected = 0; + pPanel->Edit[5].SetPstTail(); + pPanel->Edit[5].Show(); + break; + case 7: + if(LanguageEnCn==0)tText="开始下载"; else tText="DownLoad"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +16, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + if(LanguageEnCn==0)tText="结束下载"; else tText=" Stop "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +154, Lv.Grid.Top[4] + 8, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +void TDisplayPadDescpDownload::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + switch(Tag.InxItem){ + case 0: TRoundSquare::sSelected(svGrid1X[0], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, clNearWhite); break; + case 1: TRoundSquare::sSelected(svGrid1X[1], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, clNearWhite); break; + case 2: TRoundSquare::sSelected(svGrid1X[2], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, clNearWhite); break; + case 3: TRoundSquare::sSelected(svGrid1X[3], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, clNearWhite); break; + case 4: TRoundSquare::sSelected(svGrid1X[4], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, clNearWhite); break; + case 5: TRoundSquare::sSelected(svGrid1X[5], Lv.Grid.Top[0] + 38, dWWidth, dWHeigh, 4, clNearWhite); break; + } + break; + case 1: + pPanel->Edit[0].Selected = 1; + pPanel->Edit[0].SetPstTail(); + pPanel->Edit[0].Show(); + pPanel->Edit[0].ShowCursor(); + break; + case 2: + pPanel->Edit[1].Selected = 1; + pPanel->Edit[1].SetPstTail(); + pPanel->Edit[1].Show(); + pPanel->Edit[1].ShowCursor(); + break; + case 3: + pPanel->Edit[2].Selected = 1; + pPanel->Edit[2].SetPstTail(); + pPanel->Edit[2].Show(); + pPanel->Edit[2].ShowCursor(); + break; + case 4: + pPanel->Edit[3].Selected = 1; + pPanel->Edit[3].SetPstTail(); + pPanel->Edit[3].Show(); + pPanel->Edit[3].ShowCursor(); + break; + case 5: + pPanel->Edit[4].Selected = 1; + pPanel->Edit[4].SetPstTail(); + pPanel->Edit[4].Show(); + pPanel->Edit[4].ShowCursor(); + break; + case 6: + pPanel->Edit[5].Selected = 1; + pPanel->Edit[5].SetPstTail(); + pPanel->Edit[5].Show(); + pPanel->Edit[5].ShowCursor(); + break; + case 7: + if(LanguageEnCn==0)tText="开始下载"; else tText="DownLoad"; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +16, Lv.Grid.Top[4] + 8, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 8: + if(LanguageEnCn==0)tText="结束下载"; else tText=" Stop "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +154, Lv.Grid.Top[4] + 8, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + } +} + +void TDisplayPadDescpDownload::PushInnerCanData(unsigned char aCmd, unsigned char *pBuf) +{ + if(State == Writing){ + if(aCmd == cmSetDisplayPadPositionInf){ + //Write + if(pBuf[2] == DpPort){ + if(pBuf[3] == DpAddr){ + if(pBuf[5] == dgTYPE_DISPLAY_PAD){ + RpyData.RecSta = pBuf[6]; + RpyData.RecResult =1; + } + } + } + } + } +} + +void TDisplayPadDescpDownload::SendCmdWriteOnePoint(unsigned char aPort, unsigned char aAddr) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + volatile unsigned int tAddr; + unsigned char tP0,tP1; + unsigned int x; + + tP0 = aPort -1; + tP1 = aAddr -1; + if( (tP0 >= dPORT_MAX_COUNT) || (tP1 >= dEP_MAX_COUNT_PER_PORT) )return; + tAddr = dAddrSdRam_Descp + (tP0 * 256 * 32) + (tP1 * 32); + DescpData[0] = MainCtl.fData.Split.MyNum; + DescpData[1] = aPort; + DescpData[2] = aAddr; + for(i=0;i<32;i++){ + DescpData[i+3] = *(volatile unsigned char *)(tAddr +i); + } + DescpData[35]=0; + + aIde.BitF.Cmd = cmSetDisplayPadPositionInf; + for(i=0; i<8; i++){ + Data[i] = 0; + } + Data[0] = 0; + Data[1] = DpPort; + Data[2] = DpAddr; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + x = 0; + for(i=0;i<9;i++){ + Data[3] = i+1; + Data[4]=DescpData[x++]; + Data[5]=DescpData[x++]; + Data[6]=DescpData[x++]; + Data[7]=DescpData[x++]; + InnerCan.Buf4GuiSend.Insert(aIde, Data, (i<8?8:7)); + } +} + +void TDisplayPadDescpDownload::SendCmdWriteAbort(unsigned char aPort, unsigned char aAddr) +{ + +} + +TGuiMsgReturn TDisplayPadDescpDownload::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char tCtlNum, aCc, Ow, Err; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + } + + if(State == Writing){ + switch(aKey){ + case VK_RIGHT: + if(Tag.Inx ==7){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx <8){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + break; + case VK_EXECUTE: + if(Tag.Inx == 8){ + if(State == Writing){ + PermissionCmd = 2; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[1] +320, Lv.Grid.Top[1] + 16, 400, 140, 3); + } + } + } + break; + case VK_RETURN: + IsShow = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Tag.Inx ==0){ + if(aKey == VK_LEFT){ + if(Tag.InxItem >0){ + ClearSelected(); + Tag.InxItem--; + Check4Selected(); + } + }else + if(aKey == VK_RIGHT){ + if(Tag.InxItem <4){ + ClearSelected(); + Tag.InxItem++; + Check4Selected(); + } + } + }else + if(Tag.Inx ==1){ + pPanel->Edit[0].KeyIn(aKey); + aCc = pPanel->Edit[0].Str.ToInteger(); + if( (aCc == 0) || (aCc > dPORT_MAX_COUNT) ){ + pPanel->Edit[0].SelectedColor = clRed; + }else{ + pPanel->Edit[0].SelectedColor = clBlue; + } + DpPort = aCc; + pPanel->Edit[0].Show(); + pPanel->Edit[0].ShowCursor(); + DrawPadList(); + }else + if(Tag.Inx ==2){ + pPanel->Edit[1].KeyIn(aKey); + aCc = pPanel->Edit[1].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + pPanel->Edit[1].SelectedColor = clRed; + }else{ + pPanel->Edit[1].SelectedColor = clBlue; + } + DpAddr = aCc; + pPanel->Edit[1].Show(); + pPanel->Edit[1].ShowCursor(); + }else + + if(Tag.Inx ==3){ + pPanel->Edit[2].KeyIn(aKey); + aCc = pPanel->Edit[2].Str.ToInteger(); + if( (aCc == 0) || (aCc > dPORT_MAX_COUNT) ){ + pPanel->Edit[2].SelectedColor = clRed; + }else{ + pPanel->Edit[2].SelectedColor = clBlue; + } + StartPort = aCc; + pPanel->Edit[2].Show(); + pPanel->Edit[2].ShowCursor(); + }else + if(Tag.Inx ==4){ + pPanel->Edit[3].KeyIn(aKey); + aCc = pPanel->Edit[3].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + pPanel->Edit[3].SelectedColor = clRed; + }else{ + pPanel->Edit[3].SelectedColor = clBlue; + } + StartAddr = aCc; + pPanel->Edit[3].Show(); + pPanel->Edit[3].ShowCursor(); + }else + + if(Tag.Inx ==5){ + pPanel->Edit[4].KeyIn(aKey); + aCc = pPanel->Edit[4].Str.ToInteger(); + if( (aCc == 0) || (aCc > dPORT_MAX_COUNT) ){ + pPanel->Edit[4].SelectedColor = clRed; + }else{ + pPanel->Edit[4].SelectedColor = clBlue; + } + EndPort = aCc; + pPanel->Edit[4].Show(); + pPanel->Edit[4].ShowCursor(); + }else + if(Tag.Inx ==6){ + pPanel->Edit[5].KeyIn(aKey); + aCc = pPanel->Edit[5].Str.ToInteger(); + if( (aCc == 0) || (aCc > dEP_MAX_COUNT_PER_PORT) ){ + pPanel->Edit[5].SelectedColor = clRed; + }else{ + pPanel->Edit[5].SelectedColor = clBlue; + } + EndAddr = aCc; + pPanel->Edit[5].Show(); + pPanel->Edit[5].ShowCursor(); + }else + if(Tag.Inx ==7){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx ==8){ + if(aKey == VK_LEFT){ + if(State != Writing){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + } + } + break; + case VK_UP: + if(Tag.Inx >0){ + if(State != Writing){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + }else{ + if(State != Writing){ + ClearSelected(); + Tag.Inx =8; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(Tag.Inx <8){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + }else{ + if(State != Writing){ + ClearSelected(); + Tag.Inx =0; + Check4Selected(); + } + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + if(Tag.Inx ==0){ + switch(Tag.InxItem){ + case 0: SelectedList.SenSmoker = SelectedList.SenSmoker ? 0 :1; break; + case 1: SelectedList.SenTemper = SelectedList.SenTemper ? 0 :1; break; + case 2: SelectedList.HandPadReport = SelectedList.HandPadReport ? 0 :1; break; + case 3: SelectedList.ModuleIn = SelectedList.ModuleIn ? 0 :1; break; + case 4: SelectedList.ModuleInout = SelectedList.ModuleInout ? 0 :1; break; + } + DrawItemTypeSelected(); + } + break; + case dfKEY_QUERY: + + break; + case VK_EXECUTE: + if(Tag.Inx == 7){ + if(State != Writing){ + if( (DpPort && DpAddr) && (DpPort <= dPORT_MAX_COUNT) && (DpAddr <= dEP_MAX_COUNT_PER_PORT) ){ + if( (StartPort && StartAddr) && (StartPort <= dPORT_MAX_COUNT) && (StartAddr <= dEP_MAX_COUNT_PER_PORT) ){ + if( (EndPort && EndAddr) && (EndPort <= dPORT_MAX_COUNT) && (EndAddr <= dEP_MAX_COUNT_PER_PORT) ){ + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[1] +320, Lv.Grid.Top[1] + 16, 400, 140, 3); + } + } + } + } + } + } + break; + case VK_RETURN: + IsShow = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TDisplayPadDescpDownload::PermissionCmdGO() +{ + if(PermissionCmd == 1){ + InitWriteData(); + RpyData.Reset(); + State = Writing; + }else + if(PermissionCmd == 2){ + SendCmdWriteAbort(DpPort, DpAddr); + State = Idle; + RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + } +} + +void TDisplayPadDescpDownload::Task1000Ms() +{ + if(State != Idle){ + if(RunData.WasteTime < 99999999)RunData.WasteTime++; + DoTransmiting(); + }else{ + return; + } + if(IsShow == 0)return; + if( (State != Idle) && (IsPermission == 0) ){ + DrawWriteResult(); + } + if(State == Finished)State = Idle; +} + +void TDisplayPadDescpDownload::ExtReset() +{ + State = Idle; +} + +int TDisplayPadDescpDownload::ExtRequst(unsigned char Prm) +{ + IsShow = 0; + return 0; +} + diff --git a/MyCode/Gui/DisplayPadDescpDownload.h b/MyCode/Gui/DisplayPadDescpDownload.h new file mode 100644 index 0000000..11983c4 --- /dev/null +++ b/MyCode/Gui/DisplayPadDescpDownload.h @@ -0,0 +1,217 @@ +#ifndef DISPLAYPADDESCPDOWNLOAD_H_ +#define DISPLAYPADDESCPDOWNLOAD_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" + + +class TDisplayPadDescpDownload{ + public: + static constexpr unsigned short hList[12] = {72,72,72,72, 44,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,290,290,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 5, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 220, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1, + + .PanelSmall.Active = 1, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 72, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1 + 72 -1, + }; + static constexpr TPoint TipPoint ={ + .x = 16, + .y = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + 6, + }; + typedef enum{ + Idle =0, + Writing =1, + Finished + }TState; + public: + int Downloading; + unsigned char DpPort; + unsigned char DpAddr; + unsigned char StartPort; + unsigned char EndPort; + unsigned char StartAddr; + unsigned char EndAddr; + unsigned char Dump0; + unsigned char Dump1; + + struct{ + unsigned char SenSmoker; + unsigned char SenTemper; + unsigned char HandPadReport; + unsigned char ModuleIn; + unsigned char ModuleInout; + void Reset(){ + SenSmoker =1; + SenTemper =1; + HandPadReport =1; + ModuleIn =1; + ModuleInout =1; + } + }SelectedList; + + class TCtlPanel1 *pPanel; + + TRect Bound; + TRect Content; + + struct{ + unsigned char Transmiting; + unsigned char RetryTimes; + unsigned char WritingPort; + unsigned char WritingAddr; + unsigned int WroteCount; + unsigned int FailCount; + unsigned int Total; + unsigned int WasteTime; + unsigned int TotalRetryTimes; + void Reset(){ + WritingPort =0; + WritingAddr =0; + WroteCount =0; + FailCount =0; + Total =0; + WasteTime = 0; + TotalRetryTimes = 0; + } + }RunData; + + TState State; + + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + unsigned char InxItem; + void Reset(){ + Inx = 0; + InxMin = 0; + InxMax =2; + InxItem =0; + } + }Tag; + + struct{ + unsigned char HasSend; + unsigned char WaitTick; + unsigned char RecResult; + unsigned char RecSta; + void Reset(){ + HasSend =0; + WaitTick =0; + RecResult = 0; + RecSta = 0; + } + }RpyData; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char IsShow; + unsigned char WriteResult; + + unsigned int fAddr; + + unsigned char Data[12]; + char Text[12]; + unsigned char DescpData[36]; + public: + TDisplayPadDescpDownload(){ + IsShow = 0; + State = Idle; + }; + void Init(); + void RenderBackGround(void); + + void DrawSelf(void); + void Show(); + void FullRedraw(int Prm); + void DrawItemTypeSelected(); + void DrawPadList(); + void DrawFixText(); + + void DrawWriteResult(); + + void DelayMs(unsigned int aMs); + + void CheckScope(); + void DoTransmiting(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void ClearSelected(void); + void Check4Selected(); + + void InitWriteData(); + void PushInnerCanData(unsigned char aCmd, unsigned char *pBuf); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void SendCmdWriteOnePoint(unsigned char aPort, unsigned char aAddr); + void SendCmdWriteAbort(unsigned char aPort, unsigned char aAddr); + + void Task1000Ms(); + void ExtReset(); + int ExtRequst(unsigned char Prm); +}; + + +#endif diff --git a/MyCode/Gui/DuplicateCheck.cpp b/MyCode/Gui/DuplicateCheck.cpp new file mode 100644 index 0000000..b34966a --- /dev/null +++ b/MyCode/Gui/DuplicateCheck.cpp @@ -0,0 +1,797 @@ +#include "RuntimeData.h" +#include "DuplicateCheck.h" + + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +void TDuplicateCheck::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->重码检测"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("本集中机",24); + else if(MainCtl.fData.Split.NetworkMode == 2) + IList->STextCtlType.SetText("本区域机",24); + else + IList->STextCtlType.SetText("本单机 ",24); + IList->STextCtlType.Show(); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "开始检测", 14, clNearBlack); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "分回路检测"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +38, clNearWhite, "回路号"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 72, 120, 30, 7, clNearWhite, "回路检测", 14, clNearBlack); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +10, clNearWhite, "操作"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 38, 76, 30, 7, clNearWhite, "点灯", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Duplicate Addr Detect"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + if(MainCtl.fData.Split.NetworkMode == 1) + IList->STextCtlType.SetText("Local Master ",24); + else if(MainCtl.fData.Split.NetworkMode == 2) + IList->STextCtlType.SetText("Local Regional ",24); + else + IList->STextCtlType.SetText("Local Stand Alone",24); + IList->STextCtlType.Show(); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, " Detect ", 14, clNearBlack); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Single Loop Check"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +38, clNearWhite, "LoopID"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 72, 120, 30, 7, clNearWhite, " Detect ", 14, clNearBlack); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +10, clNearWhite, "Operation"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 38, 76, 30, 7, clNearWhite, "LED ", 14, clNearBlack); + } +} + + +void TDuplicateCheck::Init() +{ + IsShow =0; + IsPermission =0; + IsFastCmd = 0; + Tag.Reset(); + if(MainCtl.fData.Split.NetworkMode == 1){ + Tag.InxMin = 0; + }else{ + Tag.InxMin = 1; + } + Tag.InxMin = 1; + Tag.Inx = Tag.InxMin; + + IsChecking =0; + IsOnNetwork =0; + CheckWhat =0; + CheckTick =0; + IsShowDetail =0; + CtlNum = MainCtl.fData.Split.MyNum; + KeepOnMeJustEnter = nullptr; + KeepUiOnMe = nullptr; + + IsDulAddrChecking = 0; +} + +void TDuplicateCheck::ResetBackEndData() +{ + //dAddrSdRam_DupCheck + int i,x; + volatile unsigned int tAddrCnt; + PortCnt =0; + for(i=1; i<=dPORT_MAX_COUNT; i++){ + tAddrCnt = dAddrSdRam_DupCheck + (i*256); + for(x=0; x<256; x++){ + *(volatile unsigned char *)(tAddrCnt + x) = 0; + } + } +} + +void TDuplicateCheck::SetData(unsigned char aPort, unsigned char aAddr, unsigned char aCnt) +{ + volatile unsigned int tAddrCnt; + tAddrCnt = dAddrSdRam_DupCheck + (static_cast(aPort) * 256) + static_cast(aAddr); + *(volatile unsigned char *)(tAddrCnt) = aCnt; +} + +unsigned char TDuplicateCheck::GetData(unsigned char aPort, unsigned char aAddr) +{ + volatile unsigned int tAddrCnt; + unsigned char tCnt; + tAddrCnt = dAddrSdRam_DupCheck + (static_cast(aPort) * 256) + static_cast(aAddr); + tCnt = *(volatile unsigned char *)(tAddrCnt); + return tCnt; +} + +void TDuplicateCheck::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TDuplicateCheck::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TDuplicateCheck::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + + for(int i=0; i<5; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + IList->EditCtlNum.Init(Lv.Grid.Left[0] + 100, Lv.Grid.Top[0] + 2, 36, 30, 0, 0, 1, clNearWhite); + if(MainCtl.fData.Split.NetworkMode == 1) + IList->EditCtlNum.Enable = 1; + else + IList->EditCtlNum.Enable = 0; + IList->EditCtlNum.Visible =1;; + IList->EditCtlNum.SetMaxLen(2); + IList->EditCtlNum.Str.FromUInt2Dg( MainCtl.fData.Split.MyNum); + IList->EditCtlNum.SelectedColor = clBlue; + IList->EditCtlNum.Enable = 0; + IList->EditCtlNum.Show(); + CtlNum = MainCtl.fData.Split.MyNum; + IList->STextCtlType.Init(Lv.Grid.Left[0] + 146, Lv.Grid.Top[0] + 2, 106, 30, 0, 0, clNearWhite, ItemColor); + IList->EditPortNum.Init(Lv.Grid.Left[1] + 100, Lv.Grid.Top[1] + 34, 36, 30, 0, 0, 1, clNearWhite); + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible =1;; + IList->EditPortNum.SetMaxLen(2); + IList->EditPortNum.Str.FromUInt2Dg( 1); + IList->EditPortNum.SelectedColor = clBlue; + IList->EditPortNum.Show(); + IList->STextLastState.Init(Lv.Grid.Left[2] + 96, Lv.Grid.Top[2] + 6, 180, 30, 0, 0, clNearWhite, ItemColor); + DrawFixText(); + IList->TextOutClear(); + Check4Selected(); + CtlNumAvalble =1; + PortNumAvalble =1; +} + +void TDuplicateCheck::Show(void) +{ + IsShow =1; + RenderBackGround(); + DrawSelf(); +} + +void TDuplicateCheck::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + for(int i=0; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawCommonByExReturn(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TDuplicateCheck::DrawCommonByExReturn() +{ + //0 + DrawFixText(); + IList->EditCtlNum.Show(); + IList->STextCtlType.Show(); + IList->EditPortNum.Show(); + + Check4Selected(); +} + +void TDuplicateCheck::DrawProgress() +{ + //Percent; + if(LanguageEnCn==0){ + RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + TextRender_string24(Lv.PanelSmall.Left +4, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "检测进度:"); + TextDigitRender3_24(Lv.PanelSmall.Left +4+108, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, Percent); + TextRender_string24(Lv.PanelSmall.Left +4+108+36, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "%"); + + if(IsTransmitingFinish){ + TextRender_string24(Lv.PanelSmall.Left +4+200, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "传输完成"); + }else + if(IsTransmiting){ + TextRender_string24(Lv.PanelSmall.Left +4+200, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "正在传输"); + } + }else{ + RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + TextRender_string24(Lv.PanelSmall.Left +4, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "Progress:"); + TextDigitRender3_24(Lv.PanelSmall.Left +4+108, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, Percent); + TextRender_string24(Lv.PanelSmall.Left +4+108+36, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "%"); + + if(IsTransmitingFinish){ + TextRender_string24(Lv.PanelSmall.Left +4+200, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "Completed"); + }else + if(IsTransmiting){ + TextRender_string24(Lv.PanelSmall.Left +4+200, Lv.PanelSmall.Top + 4, clNearWhite, SmallPanelColor, "Transmite"); + } + } +} + +void TDuplicateCheck::DrawDetailOutline() +{ + unsigned int aClr; + if(IsShowDetail){ + aClr = clBlue; + }else{ + aClr = clMedGray; + } + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); +} + +void TDuplicateCheck::CheckResult() +{ + const int tOffsetX = 84+4; + int tP0,tP1; + int Pages, Lines, Pst; + unsigned char Val; + Pages =0; + Lines = 0; + Pst = 0; + for(tP0=1; tP0<=dPORT_MAX_COUNT; tP0++){ + Lines++; + if(Lines>LinesCount){ + Pages++; + Lines =1; + Pst = 0; + } + for(tP1=1;tP1<=dEP_MAX_COUNT_PER_PORT;tP1++){ + Val = GetData(tP0,tP1); + if(Val){ + Pst++; + if(Pst>=5){ + Pst=0; + Lines++; + if(Lines>LinesCount){ + Pages++; + Lines =1; + Pst = 0; + } + } + } + } + } + Details.PagesCount = Pages+1; + Details.PageX = 0; +} + +int TDuplicateCheck::TryDrawDetail() +{ + const int tOffsetX = 84+4; + int tP0,tP1; + int Pages, Lines, Pst, PageHasDraw; + unsigned char Val; + Pages =0; + Lines = 0; + Pst = 0; + PageHasDraw = 0; + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawDetailOutline(); + for(tP0=1; tP0<=dPORT_MAX_COUNT; tP0++){ + Lines++; + if(Lines>LinesCount){ + Pages++; + Lines =1; + Pst = 1; + } + if(Pages == Details.PageX){ + PageHasDraw =1; + if(LanguageEnCn==0)TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 4 + (Lines * 30 -30), clNearWhite, PanelColor, "回路:"); + else TextRender_string24(Lv.Panel.Left +4, Lv.Panel.Top + 4 + (Lines * 30 -30), clNearWhite, PanelColor, "Loop:"); + TextDigitRender2_24(Lv.Panel.Left +4+48, Lv.Panel.Top + 4 + (Lines * 30 -30), clNearWhite, PanelColor, tP0); + TextRender_string24(Lv.Panel.Left +4+48+24, Lv.Panel.Top + 4 + (Lines * 30 -30), clNearWhite, PanelColor, ":"); + } + for(tP1=1;tP1<=dEP_MAX_COUNT_PER_PORT;tP1++){ + Val = GetData(tP0,tP1); + if(Val){ + Pst++; + if(Pst>5){ + Pst=1; + Lines++; + if(Lines>LinesCount){ + Pages++; + Lines =1; + } + } + if(Pages == Details.PageX){ + PageHasDraw = 1; + TextDigitRender3_24(Lv.Panel.Left +tOffsetX + (Pst*72-72), Lv.Panel.Top + 4 + (Lines * 30 -30), clNearWhite, PanelColor, tP1); + Text[0]='x';Text[2]='\0'; Text[3]='\0'; + if(Val<10){ + Text[1]= Val + '0'; + }else{ + Text[1]= 'B'; + } + TextRender_string24(Lv.Panel.Left +tOffsetX + (Pst*72-72) + 36, Lv.Panel.Top + 4 + (Lines * 30 -30), clNearWhite, PanelColor, Text); + } + } + } + } + return PageHasDraw; +} + +void TDuplicateCheck::DrawDetail() +{ + if(TryDrawDetail() == 0){ + Details.PageX = 0; + TryDrawDetail(); + } +} + +//______________________________________________________________________________________________________________________________ +void TDuplicateCheck::ClearSelected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditCtlNum.Selected = 0; + IList->EditCtlNum.Show(); + break; + case 1: + if(LanguageEnCn==0)tText = "开始检测"; else tText = " Detect "; + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 2: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + break; + case 3: + if(LanguageEnCn==0)tText = "回路检测"; else tText = " Detect "; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 72, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 4: + if(LanguageEnCn==0)tText = "点灯"; else tText = "LED"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 38, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + default: + break; + } +} + +void TDuplicateCheck::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditCtlNum.Selected = 1; + IList->EditCtlNum.SetPstTail(); + IList->EditCtlNum.Show(); + IList->EditCtlNum.ShowCursor(); + break; + case 1: + if(LanguageEnCn==0)tText = "开始检测"; else tText = " Detect "; + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +10, Lv.Grid.Top[0] + 36, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 2: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 3: + if(LanguageEnCn==0)tText = "回路检测"; else tText = " Detect "; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 72, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 4: + if(LanguageEnCn==0)tText = "点灯"; else tText = "LED"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 38, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + + default: + + break; + } +} + +void TDuplicateCheck::PermissionCmdReturnDraw() +{ + int x,y; + Check4Selected(); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawDetailOutline(); + if(IsChecking && (Percent == 100)){ + + } +} +//_____________________________________________________________________________________________________________________________ + +void TDuplicateCheck::PermissionCmdGO() +{ + if(PermissionCmd == 0){ + ResetBackEndData(); + IList->RealtimeData.Reset(); + IList->TextOutClear(); + Data[0] = 0; + Data[1] = CtlNum; + Data[2] = 0xFF; + Data[3] = 0; + Data[4] = 0; + Data[5] = 0; + Data[6] = 0; + Data[7] = 1; + InnerCan.OBufInsert(1, cmDuplicateAddrCheckStart, Data, 3); + //IList->STextLastState.SetText("全部回路探测",24); + //IList->STextLastState.Show(); + + IsShowDetail = 0; + IsProgressUpdata =0; + IsDetailUpdata =0; + WastingTime = 0; + + IsChecking =1; + IsTransmiting =0; + IsTransmitingFinish = 0; + if(CtlNum == MainCtl.fData.Split.MyNum){ + IsOnNetwork =0; + CheckWhat =0; + Percent =0; + DrawProgress(); + }else{ + IsOnNetwork =1; + } + IsDulAddrChecking =1; + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + }else + if(PermissionCmd == 1){ + ResetBackEndData(); + IList->RealtimeData.Reset(); + IList->TextOutClear(); + int iVal = IList->EditPortNum.Str.ToInteger(); + if( (iVal) && (iVal<=dPORT_MAX_COUNT)){ + Data[0] = 0; + Data[1] = CtlNum; + Data[2] = iVal; + Data[3] = 0; + Data[4] = 0; + Data[5] = 0; + Data[6] = 0; + Data[7] = 1; + InnerCan.OBufInsert(1, cmDuplicateAddrCheckStart, Data, 3); + //IList->STextLastState.SetText("单回路探测",24); + //IList->STextLastState.Show(); + + IsShowDetail = 0; + IsProgressUpdata =0; + IsDetailUpdata =0; + WastingTime =0; + Percent =0; + + IsChecking =1; + IsTransmiting =0; + IsTransmitingFinish = 0; + if(CtlNum == MainCtl.fData.Split.MyNum){ + IsOnNetwork =0; + CheckWhat =iVal; + iVal--; + DrawProgress(); + }else{ + IsOnNetwork =1; + } + IsDulAddrChecking =1; + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + } + }else + if(PermissionCmd == 2){ + //Light On + TCanHeaderID aIde; + if(CtlNum == MainCtl.fData.Split.MyNum){ + aIde.BitF.Cmd = cmDevLightOn; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + for(int i=4; i<8; i++){ + Data[i] = 0; + } + Data[0] = 0; + Data[1] = 0xFF; + Data[2] = 1; + InnerCan.OBufInsert(1, cmDuplicateAddrEpDeviceLed, Data, 3); + } + } +} + +TGuiMsgReturn TDuplicateCheck::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + } + + if(IsShowDetail){ + switch(aKey){ + case VK_LEFT: + case VK_UP: + if(Details.PageX>0){ + Details.PageX--; + } + + DrawDetail(); + break; + case VK_RIGHT: + case VK_DOWN : + Details.PageX++; + if(Details.PageX>=(Details.PagesCount)){ + Details.PageX =0; + } + DrawDetail(); + break; + case VK_TAB: + if(IsTransmitingFinish){ + IsTransmitingFinish =0; + IsShowDetail = 0; + DrawDetailOutline(); + } + break; + case VK_RETURN: + IsShow = 0; + SendEndCmd(); + aMsg = guiMsgReturn; + break; + } + return aMsg; + } + + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx == 0){ + IList->EditCtlNum.KeyIn(aKey); + int iVal = IList->EditCtlNum.Str.ToInteger(); + if( (iVal > 0) && (iVal <= 16) ){ + IList->EditCtlNum.SelectedColor = clBlue; + CtlNumAvalble = 1; + }else{ + IList->EditCtlNum.SelectedColor = clRed; + CtlNumAvalble = 0; + } + IList->EditCtlNum.Show(); + }else + if(Tag.Inx == 2){ + IList->EditPortNum.KeyIn(aKey); + int iVal = IList->EditPortNum.Str.ToInteger(); + if( (iVal > 0) && (iVal <= dPORT_MAX_COUNT) ){ + IList->EditPortNum.SelectedColor = clBlue; + PortNumAvalble = 1; + }else{ + IList->EditPortNum.SelectedColor = clRed; + PortNumAvalble = 0; + } + IList->EditPortNum.Show(); + } + break; + + case VK_UP: + if(Tag.Inx>Tag.InxMin){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx=4; + Check4Selected(); + } + break; + case VK_DOWN : + if(Tag.Inx<4){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx=Tag.InxMin; + Check4Selected(); + } + break; + case VK_EXECUTE: + if(Tag.Inx == 1){ + if(CtlNumAvalble){ + if(SystemPermission >1){ + PermissionCmd = 0; + PermissionCmdGO(); + }else{ + PermissionCmd = 0; + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + }else + if(Tag.Inx == 3){ + if( (CtlNumAvalble) && (PortNumAvalble) ){ + if(SystemPermission >1){ + PermissionCmd = 1; + PermissionCmdGO(); + }else{ + PermissionCmd = 1; + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + }else + if(Tag.Inx == 4){ + if( 1 ){ + if(SystemPermission >1){ + PermissionCmd = 2; + PermissionCmdGO(); + }else{ + PermissionCmd = 2; + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 2); + } + } + } + break; + case VK_TAB: + //IsShowDetail = 1; + //DrawDetailOutline(); + break; + case VK_RETURN: + IsShow = 0; + SendEndCmd(); + aMsg = guiMsgReturn; + break; + } + return aMsg; +} + +void TDuplicateCheck::InnerCanPushData(unsigned char aCmd, unsigned char *pData) +{ + unsigned int i,x,v, ov, tPortCnt, RecVal, FullVal; + if( aCmd == cmDuplicateAddrCheckPrg ){ + if( (pData[1]) && (pData[1]<=dPORT_MAX_COUNT) ){ + x = pData[1]; + v = pData[2]; + if(v>100)v=100; + IList->RealtimeData.Data[0][x]=v; + if(CheckWhat == 0){ + tPortCnt=0; + for(i=0; i(IList->RealtimeData.Data[0][i]); + } + tPortCnt = RecVal * 100 / FullVal; + Percent = static_cast(tPortCnt % 101); + IsProgressUpdata =1; + } + }else + if(aCmd == cmDuplicateAddrData){ + if( (pData[1]) && (pData[1]<=dPORT_MAX_COUNT) && (pData[2] == 0)){ + x = pData[1]; + if(pData[4] && pData[5]){ + SetData(x,pData[4],pData[5]); + IsDetailUpdata =1; + IsTransmiting =1; + } + if(pData[6] && pData[7]){ + SetData(x,pData[6],pData[7]); + IsDetailUpdata =1; + IsTransmiting =1; + } + } + }else + if(aCmd == cmDuplicateAddrCheckEnd){ + if( (pData[1]) && (pData[1]<=dPORT_MAX_COUNT) ){ + x = pData[1]; + v = pData[2]; + if(1){ + IList->RealtimeData.Data[1][x]=1; + if(CheckWhat == 0){ + tPortCnt=0; + for(i=0; iRealtimeData.Data[1][i]; + } + if(RecVal == tPortCnt){ + IsDetailUpdata = 1; + IsTransmitingFinish = 1; + IsProgressUpdata =1; + } + } + } + } +} + +void TDuplicateCheck::SendEndCmd() +{ + TCanHeaderID aIde; + aIde.BitF.Cmd = cmDuplicateAddrCheckEnd; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + for(int i=0; i<8; i++){ + Data[i] = 0; + } + Data[0] = 0; + Data[1] = CtlNum; + Data[2] = 0xFE; + + InnerCan.Buf4GuiSend.Insert(aIde, Data,6); +} + +void TDuplicateCheck::Task1000Ms() +{ + unsigned int ttProgress, tt100, Val; + if(IsShow == 0){ + IsDulAddrChecking = 0; + return; + } + if(IsChecking == 0)return; + if(WastingTime<360){ + WastingTime++; + if(KeepUiOnMe != nullptr)KeepUiOnMe(); + } + if(IsOnNetwork == 0){ + if(IsProgressUpdata){ + IsProgressUpdata =0; + DrawProgress(); + } + if( IsDetailUpdata ){ + IsShowDetail =1; + IsDetailUpdata = 0; + CheckResult(); + DrawDetailOutline(); + DrawDetail(); + } + }else{ + + } +} + +int TDuplicateCheck::ExtRequst(unsigned char Prm) +{ + IsDulAddrChecking = 0; + IsShow =0; + SendEndCmd(); + return 0; +} + + + diff --git a/MyCode/Gui/DuplicateCheck.h b/MyCode/Gui/DuplicateCheck.h new file mode 100644 index 0000000..dbaa7b9 --- /dev/null +++ b/MyCode/Gui/DuplicateCheck.h @@ -0,0 +1,185 @@ +#ifndef DUPLICATECHECK_H_ +#define DUPLICATECHECK_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TDuplicateCheck{ + public: + static constexpr unsigned short hList[12] = {72,102,72,72, 42,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,290,290,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 5, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 250, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 250 -1, + + .PanelSmall.Active = 1, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 250 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 42, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 250 -1 + 1 + 42 -1, + }; + static constexpr unsigned int MaxCount = 1024; + static constexpr int LinesCount = 8; + public: + class TItemList *IList; + + void (*KeepOnMeJustEnter)(void); + void (*KeepUiOnMe)(void); + u32 Color; + + int IsShow; + + unsigned char CtlNum; + unsigned char PortNum; + unsigned char CtlNumAvalble; + unsigned char PortNumAvalble; + + TRect Bound; + TMyString Str; + + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + void Reset(){ + Inx = 0; + InxMin = 0; + InxMax =11; + } + }Tag; + unsigned char IsPermission; + unsigned char PermissionCmd; + + union{ + unsigned short sVal[4]; + unsigned char cVal[8]; + }RecData; + unsigned short Scaling[4]; + int IsFastCmd; + unsigned char Data[8]; + + unsigned char IsChecking; + unsigned char IsTransmiting; + unsigned char IsTransmitingFinish; + unsigned char IsOnNetwork; + unsigned char CheckWhat; + unsigned char CheckTick; + unsigned char PortCnt; + unsigned char Percent; + unsigned char OldPercent; + unsigned char P0; + unsigned char IsShowDetail; + unsigned char IsProgressUpdata; + unsigned char IsDetailUpdata; + + unsigned int WastingTime; + + struct{ + unsigned char PagesCount; + unsigned char PageX; + }Details; + char Text[4]; + + private: + public: + TDuplicateCheck(){}; + void Init(); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawCommonByExReturn(); + void DrawFixText(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawProgress(); + void DrawDetailOutline(); + int TryDrawDetail(); + void DrawDetail(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + void ClearSelected(void); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void SendCmd(); + void SendFastCmd(); + void SendEndCmd(); + + void CheckResult(); + void ResetBackEndData(); + + void InnerCanPushData(unsigned char aCmd, unsigned char *pData); + + void PermissionCmdGO(); + void SetData(unsigned char aPort, unsigned char aAddr, unsigned char aCnt); + unsigned char GetData(unsigned char aPort, unsigned char aAddr); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm);//{IsShow =0; SendEndCmd(); return 0;} +}; + + + +#endif + + + diff --git a/MyCode/Gui/ECanNetwork.cpp b/MyCode/Gui/ECanNetwork.cpp new file mode 100644 index 0000000..ea2cb1f --- /dev/null +++ b/MyCode/Gui/ECanNetwork.cpp @@ -0,0 +1,332 @@ +#include "ECanNetwork.h" +#include "XBox.h" +#include "Runtime.h" + +void TECanNetwork::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + BoundCaption.SetBySize(Left,Top,Width, CH); + Content.Set(Left, Top+CH, Right, Bottom); + + Color = aColor; + + BoxBoundCfg.Set(Left + 100, Top+56, Right -145, Bottom -60); + + CtlIndex = 0; + TextHasClear =1; + + vtValue[0] = 0; + vtValue[1] = 0; + vtValue[2] = 0; + vtValue[3] = 0; + + #undef CH +} + +void TECanNetwork::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); + + RectFillRender(BoundCaption.Left, BoundCaption.Top, BoundCaption.Right, BoundCaption.Bottom, clMaroon); + TextRender_string24(BoundCaption.Left+6, BoundCaption.Top +3, clNearWhite, clMaroon, "系统设置->组网配置"); + + TextRender_string24(Content.Left+100, Content.Bottom -98, clNearBlack, Color, "1.左右键,数字键,删除键编辑内容"); + TextRender_string24(Content.Left+100, Content.Bottom -64, clNearBlack, Color, "2.上下键, TAB键切换编辑项,选中保存设定按钮按确认键保存"); +} + + +void TECanNetwork::Show(void) +{ + DrawSelf(); +} + +void TECanNetwork::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + aPanel->ReDrawItems(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->ReDrawItems(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +void TECanNetwork::Check4Selected() +{ + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + switch(CtlIndex){ + case 0: aPanel->Edit[0].Selected = 1; break; + case 1: aPanel->Edit[1].Selected = 1; break; + case 2: aPanel->Btn[0].Selected = 1; break; + case 3: aPanel->Btn[1].Selected = 1; break; + default: CtlIndex = 0; aPanel->Edit[0].Selected = 1; break; + } +} + +void TECanNetwork::LoadSysCfg() +{ + vtValue[0] = MainCtl.fData.Split.NetworkMode; + vtValue[1] = MainCtl.fData.Split.MyNum; +} + +void TECanNetwork::DrawAllItems() +{ + if(vtValue[0] == 2){ + aPanel->Edit[0].Str.FromStr("区域机"); + aPanel->Btn[1].Caption.FromStr("向集中机请求日期时间更新"); + aPanel->Btn[1].Enable = 1; + }else + if(vtValue[0] == 1){ + aPanel->Edit[0].Str.FromStr("集中机"); + aPanel->Btn[1].Caption.FromStr(" 同步各区域机日期时间 "); + aPanel->Btn[1].Enable = 1; + }else{ + aPanel->Edit[0].Str.FromStr("单机"); + aPanel->Btn[1].Caption.FromStr(" 同步各区域机日期时间 "); + aPanel->Btn[1].Enable = 0; + } + aPanel->Edit[0].Show(); + aPanel->Btn[1].Show(); + + TMyString::sFrom2Dg(vtValue[1], aPanel->Edit[1].Str.Text); + aPanel->Edit[1].SetPstTail();; + aPanel->Edit[1].Show(); +} + +void TECanNetwork::WriteSysCfg() +{ + int iVal; + ValOk = 1; + iVal = aPanel->Edit[1].Str.ToInteger(); + if( (iVal <1) || (iVal > 64) ){ + ValOk = 0; + }else{ + vtValue[1] = iVal; + } + + if(ValOk){ + //Save To Mem Here + Record.WriteMainSetMainCtl(vtValue[0], vtValue[1]); + } +} + +void TECanNetwork::sRecoverSetDefault() +{ + Record.WriteMainSetMainCtl(0, 1); +} + +void TECanNetwork::CheckClearText() +{ + if(TextHasClear == 0){ + TextHasClear = 1; + TextRender_string24(260, 82, clNearBlack, Color, " "); + } +} + +TGuiMsgReturn TECanNetwork::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned int GoWrite; + unsigned char pNumOld; + + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex == 0){ + if(vtValue[0] == 1){ + vtValue[0] = 2; + aPanel->Edit[0].Str.FromStr("区域机"); + }else + if(vtValue[0] == 2){ + vtValue[0] = 0; + aPanel->Edit[0].Str.FromStr("单机"); + }else{ + vtValue[0] = 1; + aPanel->Edit[0].Str.FromStr("集中机"); + } + DrawAllItems(); + }else + if(CtlIndex == 1){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + } + CheckClearText(); + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + CheckClearText(); + break; + case VK_DOWN: + if(CtlIndex <3){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + CheckClearText(); + break; + case VK_TAB: + if(CtlIndex <3){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + }else{ + CtlIndex = 0; + Check4Selected(); + aPanel->ReDrawItems(); + } + CheckClearText(); + break; + case VK_EXECUTE: + //Save Data Here + if(CtlIndex == 2){ + pNumOld = MainCtl.fData.Split.MyNum; + WriteSysCfg(); + Record.ReadMainSet(); + if( (ValOk) && (vtValue[1] == MainCtl.fData.Split.MyNum) && (vtValue[1] == MainCtl.fData.Split.MyNum) ){ + Record.OperateAdd_SetCanNetwork(MainCtl.fData.Split.NetworkMode, pNumOld); + TextHasClear = 0; + TextRender_string24(260, 82, clNearBlack, Color, " 保存成功 "); + }else{ + TextHasClear = 0; + TextRender_string24(260, 82, clRed, Color, "保存失败,请检查配置内容"); + } + LoadSysCfg(); + DrawAllItems(); + }else + if(CtlIndex == 3){ + if(vtValue[0] ==1){ + //Set DateTime + ProtoC2C.DateTimeSet(); + }else + if(vtValue[0] ==2){ + //Req DateTime + ProtoC2C.DateTimeReq(); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + + return aMsg; +} + + +void TECanNetwork::InitPanel(void) +{ + int x,y, aW,aH,i; + + x = Content.Left; + y = Content.Top; + aW = 400; + aH = 260; + + aPanel->Init(100,10,aW,aH,x,y,Color, bvRaised); + + aPanel->Caption.Init(101,11,aW-3,32,x,y,clFrmFace,Color); + aPanel->Caption.Text[0] = 0; + + x = aPanel->Bound.Left; + y = aPanel->Bound.Top; + + aPanel->SText[0].Init(130,40,60,30,x,y,clNearBlack,Color); + aPanel->SText[1].Init(130,80,60,30,x,y,clNearBlack,Color); + + TMyString::sFromStr("本机模式:", aPanel->SText[0].Text); + TMyString::sFromStr("本机地址:", aPanel->SText[1].Text); + + aPanel->Edit[0].Init(248,40,300,30,x,y,1,clNearWhite); + aPanel->Edit[1].Init(248,80,300,30,x,y,1,clNearWhite); + + for(i=0; i<2;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.Clear(); + } + aPanel->Edit[1].SetMaxLen(2); + + aPanel->Btn[0].Init(248,120,300,38,x,y,1,clFrmFace); + aPanel->Btn[0].Caption.FromStr(" 保存设定"); + aPanel->Btn[0].SelectedColor = clBlue; + aPanel->Btn[0].SetCaptionLeftSpacing(6); + aPanel->Btn[0].Enable = 1; + aPanel->Btn[0].Visible = 1; + + aPanel->Btn[1].Init(248,160,300,38,x,y,1,clFrmFace); + aPanel->Btn[1].Caption.FromStr("xxxxxxxx"); + aPanel->Btn[1].SelectedColor = clBlue; + aPanel->Btn[1].SetCaptionLeftSpacing(6); + aPanel->Btn[1].Enable = 1; + aPanel->Btn[1].Visible = 1; + + //aPanel->Caption.Visible = 1; + + //aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); +} + + + + + diff --git a/MyCode/Gui/ECanNetwork.h b/MyCode/Gui/ECanNetwork.h new file mode 100644 index 0000000..cde5977 --- /dev/null +++ b/MyCode/Gui/ECanNetwork.h @@ -0,0 +1,63 @@ +#ifndef ECANNETWORK_H_ +#define ECANNETWORK_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" +#include "CtlPanel1.h" + +class TECanNetwork{ + public: + TCtlPanel1 *aPanel; + + unsigned int Color; + + TRect Bound; + TRect BoundCaption; + TRect Content; + + TRect BoxBoundCfg; + + unsigned char TextHasClear; + unsigned char CtlIndex; + unsigned char EditIndex; + unsigned char ValOk; + unsigned char vtValue[4]; + + public: + TECanNetwork(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void DrawSelf(); + void DrawGetDescpButton(); + void Show(); + void FullRedraw(int Prm); + void DrawAllItems(); + void CheckClearText(); + + void LoadSysCfg(void); + void WriteSysCfg(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(void); + void Check4Selected(); + void CheckSetting(); + + static void sRecoverSetDefault(); + + int ExtRequst(unsigned char Prm){return 0;} + +}; + + + +#endif + diff --git a/MyCode/Gui/EditML.cpp b/MyCode/Gui/EditML.cpp new file mode 100644 index 0000000..36ee7a8 --- /dev/null +++ b/MyCode/Gui/EditML.cpp @@ -0,0 +1,344 @@ + +#include "gType.h" +#include"GraphLow.h" +#include"EditML.h" + + +void TEditML::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aBorderWidth, u32 aBorderColor) +{ + unsigned short Left,Right,Top,Bottom, aBW; + aBW = aBorderWidth; + aBW = 2; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + OwnerLeftTop.x = OwnerX; + OwnerLeftTop.y = OwnerY; + Border.Width = aBW; + Border.Color = aBorderColor; + + Left = Bound.Left + aBW; + Right = Bound.Right - aBW; + Top = Bound.Top + aBW; + Bottom = Bound.Bottom - aBW; + + Content.Set(Left,Top,Right,Bottom); + Index = 0; + + Color = clNearWhite; + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + SetText("Edit xx", 24); + + Enable = true; + FlickDominance = true; + FlickTick = 0; + Pst = -1; + + MaxLen = 256; + LineSpacing = 4; + SetLineSpacing(LineSpacing); +} + +void TEditML::SetLineSpacing(int aSpacing) +{ + int aN, aS; + LineSpacing = aSpacing; + aN = Content.Width / 12; + aS = Content.Width % 12; + if(aS < 3){ + OneLineTextCount = aN -1; + }else{ + OneLineTextCount = aN; + } + LineNum = Content.Height /24; +} + +void TEditML::SetText(char *p, int aFontSize) +{ + Str.FromStr(p); + FontSize = aFontSize; +} + +void TEditML::SetText(const char *p, int aFontSize) +{ + Str.FromStr(p); + FontSize = aFontSize; +} + +void TEditML::TextClear(void) +{ + Str.Text[0]=0; + Str.Text[1]=0; + Pst = -1; + ReDraw(); +} + +void TEditML::SelfDraw(void) +{ + if (Border.Width>0){ + VertLineRender(Bound.Left, Bound.Top, Bound.Height-1, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width-1, 0xFF808080); + + VertLineRender(Bound.Left+1, Bound.Top+1, Bound.Height-2, 0xFF404040); + HorizLineRender(Bound.Left+1, Bound.Top+1, Bound.Width-2, 0xFF404040); + + VertLineRender(Bound.Right-1, Bound.Top+1, Bound.Height-2, 0xFFD4D0C8); + HorizLineRender(Bound.Left+1, Bound.Bottom-1, Bound.Width-2, 0xFFD4D0C8); + + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFFFFFFFF); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFFFFFFFF); + } + + ReDraw(); +} + +void TEditML::ReDraw(void) +{ + int i,x,y, xCnt, yCnt, Inx, cpPst; + unsigned int tClr, bClr; + TmpChar[0] = 0; + TmpChar[1] = 0; + TmpChar[2] = 0; + TmpChar[3] = 0; + if(Enable){ + if(Selected){ + bClr = SelectedColor; + tClr = SelectedTextColor; + }else{ + bClr = Color; + tClr = TextColor; + } + }else{ + bClr = clFrmFace; + tClr = clGray; + } + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, bClr); + x = Content.Left + 2; + y = Content.Top + 1; + xCnt = 0; + yCnt = 0; + Inx = 0; + if(Pst == -1){ + if(Enable && Selected && IsShowCursor) + VertLineRender(x , y, 24, tClr); + } + for(i=0; i= cpPst){ + xCnt = 0; + yCnt++; + x = Content.Left + 2; + y = y + LineSpacing + 24; + if(yCnt >= LineNum)break; + } + if(Inx >= (dMYLONGSTRING_LENGTH -1))break; + } + } +} + +void TEditML::SetSelect(void) +{ + Selected = 1; + ReDraw(); +} + +void TEditML::SetDeSelect(void) +{ + Selected = 0; + FlickDominance = true; + FlickTick = 0; + Pst = Str.GetEndPst(); + ReDraw(); +} + +void TEditML::Show(void) +{ + SelfDraw(); +} + +void TEditML::KeyIn(unsigned char aKey) +{ + int aEp, aLen; + switch(aKey){ + case VK_DELETE: + aEp = Str.Delete(Pst); + Pst -= aEp; + if(Pst < -1)Pst =-1; + break; + case VK_LEFT: + if(Pst > 0){ + if( (Str.Text[Pst] & 0x80) == 0){ + //this is AscII + Pst--; + }else{ + Pst -=2; + } + }else + if(Pst >-1){ + Pst--; + } + break; + case VK_RIGHT: + aEp = Str.GetEndPst(); + if(Pst < (aEp-1)){ + if( (Str.Text[Pst+1] & 0x80) == 0){ + //this is AscII + Pst++; + }else{ + Pst +=2; + } + }else + if(Pst= VK_0) && (aKey <= VK_9) ){ + if(aKey == VK_0)Str.Insert("0",Pst); + if(aKey == VK_1)Str.Insert("1",Pst); + if(aKey == VK_2)Str.Insert("2",Pst); + if(aKey == VK_3)Str.Insert("3",Pst); + if(aKey == VK_4)Str.Insert("4",Pst); + if(aKey == VK_5)Str.Insert("5",Pst); + if(aKey == VK_6)Str.Insert("6",Pst); + if(aKey == VK_7)Str.Insert("7",Pst); + if(aKey == VK_8)Str.Insert("8",Pst); + if(aKey == VK_9)Str.Insert("9",Pst); + Pst++; + } + if(aKey == ' '){Str.Insert(" ",Pst); Pst++;} + else if(aKey == '='){Str.Insert("=",Pst); Pst++;} + else if(aKey == 'Y'){Str.Insert("Y",Pst); Pst++;} + else if(aKey == '('){Str.Insert("(",Pst); Pst++;} + else if(aKey == ')'){Str.Insert(")",Pst); Pst++;} + else if(aKey == '-'){Str.Insert("-",Pst); Pst++;} + else if(aKey == '+'){Str.Insert("+",Pst); Pst++;} + else if(aKey == '&'){Str.Insert("&",Pst); Pst++;} + else if(aKey == 'S'){Str.Insert("S",Pst); Pst++;} + else if(aKey == '*'){Str.Insert("*",Pst); Pst++;} + else if(aKey == VK_DECIMAL){Str.Insert("*",Pst); Pst++;} + else if(aKey == VK_OEM_2){Str.Insert("#",Pst);Pst++;} + }else + if(InputMethod == CN){ + + }else{ + InputMethod = EN; + } + Str.Text[MaxLen] = 0; + if(Pst >= MaxLen)Pst = MaxLen -1; +} + +void TEditML::OnTime100mS(void) +{ + FlickTick++; + if(FlickTick>4){ + FlickTick = 0; + if(FlickDominance){ + FlickDominance = false; + }else{ + FlickDominance = true; + } + } +} + +void TEditML::SetMaxLen(unsigned int aLen) +{ + if(aLen > (dMYLONGSTRING_LENGTH-2)){ + MaxLen = dMYLONGSTRING_LENGTH-2; + }else{ + MaxLen = aLen; + } +} + +void TEditML::SetInputMaskEn(void) +{ + InputMethod = EN; +} + +void TEditML::SetInputCN(void) +{ + InputMethod = CN; +} + +void TEditML::SetPstTail(void) +{ + Pst = Str.GetEndPst(); +} + +char TEditML::GetLastChar() +{ + int i; + char aChr = 0; + for(i=0; i<(dMYLONGSTRING_LENGTH-2); i++){ + if(Str.Text[i] != 0){ + aChr = Str.Text[i]; + }else{ + return aChr; + } + } + return ' '; +} + +void TEditML::SetLastChar(char aChr) +{ + int i, aPst; + aPst = 0; + for(i=0; i<(dMYLONGSTRING_LENGTH-2); i++){ + if(Str.Text[i] != 0){ + aPst = i; + }else{ + if(aPst < (dMYLONGSTRING_LENGTH-2)){ + Str.Text[aPst] = aChr; + Str.Text[aPst +1] = 0; + }else{ + Str.Text[aPst] = 0; + } + } + } +} + +char TEditML::GetCurrentChar() +{ + return Str.Text[Pst]; +} + +void TEditML::SetCurrentChar(char aChr) +{ + Str.Text[Pst] = aChr; +} + + diff --git a/MyCode/Gui/EditML.h b/MyCode/Gui/EditML.h new file mode 100644 index 0000000..6483fdc --- /dev/null +++ b/MyCode/Gui/EditML.h @@ -0,0 +1,80 @@ +#ifndef EDITML_H_ +#define EDITML_H_ + +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "MyLongString.h" + +class TEditML{ + private: + struct{ + unsigned int Width; + unsigned int Color; + }Border; + char TmpChar[4]; + int OneLineTextCount; + int LineNum; + int LineSpacing; + public: + TMyLongString Str; + bool Enable; + int FontSize; + int DrawMode; //dmRaised=1 dmLowered=-1 dmNone=0 + unsigned int Color; + unsigned int TextColor; + unsigned int Index; + unsigned int Edit; + int TabOrder; + + int Selected; + unsigned int SelectedColor; + unsigned int SelectedTextColor; + + TPoint OwnerLeftTop; //Parrent Left Top; + TRect Bound; + TRect Content; + int Pst; + int MaxLen; + bool FlickDominance; + unsigned int FlickTick; + TInputMethod InputMethod; + unsigned int Visible; + int IsShowCursor; + public: + TEditML(void){}; + TEditML(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aBorderWidth, u32 aBorderColor){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aBorderWidth, aBorderColor); + } + void Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aBorderWidth, u32 aBorderColor); + void SetText(char *p, int aFontSize); + void SetText(const char *p, int aFontSize); + void SelfDraw(void); + void TextClear(void); + + void SetLineSpacing(int aSpacing); + void SetSelect(void); + void SetDeSelect(void); + void ReDraw(void); + void Show(void); + + void KeyIn(unsigned char aKey); + + void OnTime100mS(void); + void SetMaxLen(unsigned int aLen); + + void SetInputMaskEn(void); + void SetInputCN(void); + + void SetPstTail(void); + char GetLastChar(); + void SetLastChar(char aChr); + + char GetCurrentChar(); + void SetCurrentChar(char aChr); +}; + +#endif + diff --git a/MyCode/Gui/EnInput.cpp b/MyCode/Gui/EnInput.cpp new file mode 100644 index 0000000..e69de29 diff --git a/MyCode/Gui/EnInput.h b/MyCode/Gui/EnInput.h new file mode 100644 index 0000000..026793b --- /dev/null +++ b/MyCode/Gui/EnInput.h @@ -0,0 +1,77 @@ +#ifndef ENINPUT_H_ +#define ENINPUT_H_ + +#include "gType.h" + +const char ListPayload[10] = {0,0,3,3,3,3,3,4,3,4}; +const char ListCaseUp[10][4] = { +{' ', ' ', ' ', ' '}, +{' ', ' ', ' ', ' '}, +{'A', 'B', 'C', ' '}, +{'D', 'E', 'F', ' '}, +{'G', 'H', 'I', ' '}, +{'J', 'K', 'L', ' '}, +{'M', 'N', 'O', ' '}, +{'P', 'Q', 'R', 'S'}, +{'T', 'U', 'V', ' '}, +{'W', 'X', 'Y', 'Z'} +}; +const char ListCaseLow[10][4] = { +{' ', ' ', ' ', ' '}, +{' ', ' ', ' ', ' '}, +{'A', 'B', 'C', ' '}, +{'D', 'E', 'F', ' '}, +{'G', 'H', 'I', ' '}, +{'J', 'K', 'L', ' '}, +{'M', 'N', 'O', ' '}, +{'P', 'Q', 'R', 'S'}, +{'T', 'U', 'V', ' '}, +{'W', 'X', 'Y', 'Z'} +}; + +typedef enum{ + EnInputNumber = 0, + EnInputCaseUp = 1, + EnInputCaseLow = 2, + EnInputSymbol +}TEnInputMethrold; + +class TEnInput{ + public: + TEnInputMethrold InMethrold; + unsigned char KeyIndex; + + public: + + public: + TEnInput(){}; + void Init(); + + +}; + + + + + + + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/EpDevState.cpp b/MyCode/Gui/EpDevState.cpp new file mode 100644 index 0000000..6dd2378 --- /dev/null +++ b/MyCode/Gui/EpDevState.cpp @@ -0,0 +1,664 @@ +#include "RuntimeData.h" +#include "EpDevState.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +void TEpDevState::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+358,Top,434, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + RectPanel.Set(100,82,700,428); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("终端调试-本机", Caption.Text); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + CtlIndex = 0; + FastIndex = 0; + + OnActive = 0; + IsFastCmd = 0; +} + +void TEpDevState::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TEpDevState::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TEpDevState::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TEpDevState::DrawCaption2(void) +{ + TMyString::sFromStr("TAB键在快捷命令与定义命令之间切换", SText.Text); + SText.Show(); +} + +void TEpDevState::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); +} + +void TEpDevState::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + aPanel->Show(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + } +} + +void TEpDevState::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ + +void TEpDevState::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<7;i++)aPanel->Btn[i].Selected = 0; + for(i=0; i<10;i++)aPanel->Edit[i].Selected = 0; + if(IsFastCmd == 0){ + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Edit[2].Selected = 1; + break; + case 3: + aPanel->Edit[3].Selected = 1; + break; + case 4: + aPanel->Edit[4].Selected = 1; + break; + case 5: + aPanel->Edit[5].Selected = 1; + break; + case 6: + aPanel->Edit[6].Selected = 1; + break; + case 7: + aPanel->Edit[7].Selected = 1; + break; + case 8: + aPanel->Edit[8].Selected = 1; + break; + case 9: + aPanel->Edit[9].Selected = 1; + break; + + default: + + break; + } + }else{ + switch(FastIndex){ + case 0: + aPanel->Btn[1].Selected = 1; + break; + case 1: + aPanel->Btn[2].Selected = 1; + break; + case 2: + aPanel->Btn[3].Selected = 1; + break; + case 3: + aPanel->Btn[4].Selected = 1; + break; + case 4: + aPanel->Btn[5].Selected = 1; + break; + case 5: + aPanel->Btn[6].Selected = 1; + break; + case 6: + aPanel->Btn[0].Selected = 1; + break; + default: + break; + } + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TEpDevState::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + if(IsFastCmd == 0){ + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(CtlIndex < 10){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].ReDraw(); + } + } + + if(aKey == VK_UP){ + if(CtlIndex >0){ + CtlIndex--; + if(CtlIndex == 5)CtlIndex=4; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + }else{ + CtlIndex = 9; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_DOWN){ + if(CtlIndex <9){ + CtlIndex++; + if(CtlIndex == 5)CtlIndex=6; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + }else{ + CtlIndex = 0; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_TAB){ + IsFastCmd = 1; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + SendCmd(); + } + }else{ + if(aKey == VK_UP){ + if(FastIndex >2){ + FastIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + }else{ + FastIndex =6; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_DOWN){ + if(FastIndex <6){ + FastIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + }else{ + FastIndex =2; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + }else + if(aKey == VK_TAB){ + IsFastCmd = 0; + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + SendFastCmd(); + } + } + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TEpDevState::PanelCanvasOut() +{ + //TXBox::sDrawBoxBorder(RectPanel.Left + 8, RectPanel.Top + 3, RectPanel.Left + 362, RectPanel.Top + 150, "自定义命令", 8, 1, 0, clFrmFace); +} + +void TEpDevState::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[0].Init(26,3,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[1].Init(26,35,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[2].Init(26,67,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[3].Init(26,99,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[4].Init(26,131,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[5].Init(26,163,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[6].Init(26,195,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[7].Init(26,227,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[8].Init(26,259,70,30,x,yt,clNearBlack,clFrmFace); + + aPanel->SText[9].Init(26,294,70,30,x,yt,clNearBlack,clFrmFace); + + aPanel->SText[10].Init(430,3,70,30,x,yt,clNearBlack,clFrmFace); + + TMyString::sFromStr("命令------CMD", aPanel->SText[0].Text); + TMyString::sFromStr("控制字----D-0", aPanel->SText[1].Text); + TMyString::sFromStr("机器-区号-D-1", aPanel->SText[2].Text); + TMyString::sFromStr("回路-状态-D-2", aPanel->SText[3].Text); + TMyString::sFromStr("地址------D-3", aPanel->SText[4].Text); + TMyString::sFromStr("通道------D-4", aPanel->SText[5].Text); + TMyString::sFromStr("类型------D-5", aPanel->SText[6].Text); + TMyString::sFromStr("数值0-----D-6", aPanel->SText[7].Text); + TMyString::sFromStr("数值1-----D-7", aPanel->SText[8].Text); + + TMyString::sFromStr("长度------DLC", aPanel->SText[9].Text); + aPanel->SText[10].SetText(" ", 24); + + for(i=0; i<11;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + + aPanel->Edit[0].Init(330,3,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(330,35,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(330,67,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[3].Init(330,99,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[4].Init(330,131,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[5].Init(330,163,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[6].Init(330,195,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[7].Init(330,227,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[8].Init(330,259,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[9].Init(330,294,70,30,x,yt,clNearBlack,clNearWhite); + + aPanel->Edit[13].Init(220,3,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[14].Init(220,35,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[15].Init(220,67,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[16].Init(220,99,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[17].Init(220,131,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[18].Init(220,163,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[19].Init(220,195,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[20].Init(220,227,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[21].Init(220,259,70,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[22].Init(220,294,70,30,x,yt,clNearBlack,clNearWhite); + + aPanel->Btn[0].Init(430,294,156,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("发送定义内容"); + + aPanel->Btn[1].Init(430,45,156,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[2].Init(430,85,156,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[3].Init(430,125,156,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[4].Init(430,165,156,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[5].Init(430,205,156,36,x,yt,clNearBlack,clFrmFace); + aPanel->Btn[6].Init(430,245,156,36,x,yt,clNearBlack,clFrmFace); + + + aPanel->Btn[1].Caption.FromStr("15 手动启动"); + aPanel->Btn[2].Caption.FromStr("16 手动停止"); + aPanel->Btn[3].Caption.FromStr("18 启动"); + aPanel->Btn[4].Caption.FromStr("19 停止"); + aPanel->Btn[5].Caption.FromStr("25 声光启动"); + aPanel->Btn[6].Caption.FromStr("26 声光停止"); + + + for(i=0; i<7;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + for(i=0; i<9;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + aPanel->Edit[i].Pst = 2; + } + for(i=9; i<10;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(1); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("8"); + aPanel->Edit[i].Pst = 0; + } + for(i=13; i<23;i++){ + aPanel->Edit[i].Enable = 0; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("--"); + aPanel->Edit[i].Pst = 1; + } + + aPanel->Edit[5].Enable = 0; + aPanel->Edit[5].Str.FromStr("0"); + aPanel->Btn[1].Enable = 0; + aPanel->Btn[2].Enable = 0; + + aPanel->Btn[6].SetCaptionLeftSpacing(0); + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + PanelCanvasOut(); +} + +void TEpDevState::SendCmd() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len = aPanel->Edit[9].Str.ToInteger(); + if(Len >8)Len =8; + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aIde.BitF.Cmd = cVal; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + for(i=0; iEdit[i+1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[i] = cVal; + } + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TEpDevState::SendFastCmd() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + unsigned int FullPath; + int iVal; + unsigned char aCtlNum, aP0, aP1, adType; + unsigned int CtlFound; + + if(FastIndex == 0){ + aIde.BitF.Cmd = 18; + Len = 6; + }else + if(FastIndex == 1){ + aIde.BitF.Cmd = 19; + Len = 6; + }else + if(FastIndex == 2){ + aIde.BitF.Cmd = 18; + Len = 6; + }else + if(FastIndex == 3){ + aIde.BitF.Cmd = 19; + Len = 6; + }else + if(FastIndex == 4){ + aIde.BitF.Cmd = 25; + Len = 3; + }else + if(FastIndex == 5){ + aIde.BitF.Cmd = 26; + Len = 2; + }else + if(FastIndex == 6){ + SendCmd(); + } + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + for(i=0; iEdit[i+1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[i] = cVal; + } + + aP0 = Data[3] -1; + aP1 = Data[2] -1; + aCtlNum = Data[1]; + if(aP0 <40){ + adType = Port[aP0].dTypeTable[aP1]; + } + + if(aIde.BitF.Cmd == 18){ + FullPath = Data[4]; + FullPath <<= 8; + FullPath |= Data[3]; + FullPath <<= 8; + FullPath |= Data[2]; + FullPath <<= 8; + FullPath |= Data[1]; + + aP0 = Data[3] -1; + aP1 = Data[2] -1; + if(aP0 < 40){ + Port[aP0].StateTable[aP1] &= ~dEpStateBitFbMiss; + Port[aP0].StateTable[aP1] &= ~dEpStateBitDelayStart; + } + Record.OperateAdd_ManualStart(FullPath, etLinkageStart, 0x01); + RtManualPushStartMsg(adType,1,FullPath); + }else + if(aIde.BitF.Cmd == 19){ + FullPath = Data[4]; + FullPath <<= 8; + FullPath |= Data[3]; + FullPath <<= 8; + FullPath |= Data[2]; + FullPath <<= 8; + FullPath |= Data[1]; + aP0 = Data[3] -1; + aP1 = Data[2] -1; + if(aP0 < 40){ + Port[aP0].StateTable[aP1] &= ~dEpStateBitDelayStart; + } + Record.OperateAdd_ManualStartCancel(FullPath, etLinkageStartCancel, 0x01); + //RtManualPushStartCancelMsg(1,FullPath); + }else + if(aIde.BitF.Cmd == 18){ + FullPath = Data[4]; + FullPath <<= 8; + FullPath |= Data[3]; + FullPath <<= 8; + FullPath |= Data[2]; + FullPath <<= 8; + FullPath |= Data[1]; + + aP0 = Data[3] -1; + aP1 = Data[2] -1; + if(aP0 < 40){ + Port[aP0].StateTable[aP1] &= ~dEpStateBitFbMiss; + } + Record.OperateAdd_ManualStart(FullPath, etLinkageStart, 0x01); + RtManualPushStartMsg(adType,1,FullPath); + }else + if(aIde.BitF.Cmd == 19){ + FullPath = Data[4]; + FullPath <<= 8; + FullPath |= Data[3]; + FullPath <<= 8; + FullPath |= Data[2]; + FullPath <<= 8; + FullPath |= Data[1]; + aP0 = Data[3] -1; + aP1 = Data[2] -1; + if(aP0 < 40){ + Port[aP0].StateTable[aP1] &= ~dEpStateBitDelayStart; + } + Record.OperateAdd_ManualStartCancel(FullPath, etLinkageStartCancel, 0x01); + //RtManualPushStartCancelMsg(1,FullPath); + }else + if(aIde.BitF.Cmd == 25){ + FullPath = Data[4]; + FullPath <<= 8; + FullPath |= Data[3]; + FullPath <<= 8; + FullPath |= Data[2]; + FullPath <<= 8; + FullPath |= Data[1]; + Record.OperateAdd_ManualStart(0x99999999, etLinkageStart, 0x02); + RtManualPushStartMsg(255,2,FullPath); + }else + if(aIde.BitF.Cmd == 26){ + FullPath = Data[4]; + FullPath <<= 8; + FullPath |= Data[3]; + FullPath <<= 8; + FullPath |= Data[2]; + FullPath <<= 8; + FullPath |= Data[1]; + Record.OperateAdd_ManualStartCancel(0x99999999, etLinkageStartCancel, 0x02); + //RtManualPushStartCancelMsg(255,2,FullPath); + } + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + if( aCtlNum == MainCtl.fData.Split.MyNum ){ + //InnerCan.CmdSendCustom(aIde, Data, Len); + InnerCan.OBufFastInsert(1, aIde.BitF.Cmd, Data, Len); + aPanel->SText[10].SetText("发送成功", 24); + }else{ + if(MainCtl.fData.Split.NetworkMode == 1){ + CtlFound = 0; + for(i=0; iSText[10].SetText("发送成功", 24); + }else{ + aPanel->SText[10].SetText("发送失败", 24); + } + }else{ + aPanel->SText[10].SetText("发送失败", 24); + } + } + aPanel->SText[10].Show(); +} + + + + + + + + diff --git a/MyCode/Gui/EpDevState.h b/MyCode/Gui/EpDevState.h new file mode 100644 index 0000000..bca5176 --- /dev/null +++ b/MyCode/Gui/EpDevState.h @@ -0,0 +1,78 @@ +#ifndef EPDEVSTATE_H_ +#define EPDEVSTATE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TEpDevState{ + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect VScrollBarBox; + + TRect Content; + TRect RectPanel; + + TMyString Str; + + unsigned int CtlIndex; + unsigned int FastIndex; + + int IsFastCmd; + unsigned char Data[8]; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TEpDevState(){}; + TEpDevState(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + + void SendCmd(); + void SendFastCmd(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/EpMonitor.cpp b/MyCode/Gui/EpMonitor.cpp new file mode 100644 index 0000000..5c3a5ff --- /dev/null +++ b/MyCode/Gui/EpMonitor.cpp @@ -0,0 +1,400 @@ +#include "RuntimeData.h" +#include "EpMonitor.h" + +#define dfDataLen 0x10000 +#define dfDataPieceLen 0x2000 + +static const unsigned char stCmd[8] = {221,222,223,224,225,226,227,228}; +static const unsigned char stPrm[8] = {0,1,2,3,4,5,6,7}; +static const unsigned char stHexNum[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +void TEpMonitor::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("系统调试->回路设备运行状态", Caption.Text); + + CtlIndex = 0; + IsShowing = 0; +} + +void TEpMonitor::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TEpMonitor::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TEpMonitor::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + +void TEpMonitor::DrawCaption2(void) +{ + +} + +void TEpMonitor::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + IsShowing = 1; + + TextRender_string24(420, 320, clNearBlack, "1.按TAB键切换回路号与地址号编辑"); + TextRender_string24(420, 360, clNearBlack, "2.上下键加减1"); + TextRender_string24(420, 400, clNearBlack, "3.输入回路号地址号后按确认键"); +} + +void TEpMonitor::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + IsShowing = 1; + + TextRender_string24(420, 320, clNearBlack, "1.按TAB键切换回路号与地址号编辑"); + TextRender_string24(420, 360, clNearBlack, "2.上下键加减1"); + TextRender_string24(420, 400, clNearBlack, "3.输入回路号地址号后按确认键"); + + aPanel->ReDrawItems(); + RedrawState(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->ReDrawItems(); + RedrawState(); + } +} + +void TEpMonitor::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ +void TEpMonitor::Check4Selected(void) +{ + unsigned int i; + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + default: + + break; + } +} + +void TEpMonitor::Task1000Ms() +{ + if(IsShowing){ + RedrawState(); + } +} + +void TEpMonitor::CheckPath(void) +{ + int aVal; + aVal = aPanel->Edit[0].Str.ToInteger(); + Path0 = aVal -1; + aVal = aPanel->Edit[1].Str.ToInteger(); + Path1 = aVal -1; +} + +void TEpMonitor::RedrawState(void) +{ + int aP0, aType, aFire, aFault, aMask, HasState, HasWrote; + aFire = 0; + aFault = 0; + aMask = 0; + HasState = 0; + + aPanel->SText[11].TextClear(); + aPanel->SText[12].TextClear(); + aPanel->SText[13].TextClear(); + + if( (Path0>39) || (Path1>249) ){ + aPanel->SText[11].Show(); + aPanel->SText[12].Show(); + aPanel->SText[13].Show(); + return; + } + + if(MainCtl.fData.Split.ExistTablePort[Path0]){ + aType = Port[Path0].dTypeTable[Path1]; + TMyString::sFromStr(StrType[aType],aPanel->SText[11].Text); + + if(Port[Path0].StateTable[Path1] & dEpStateBitFire){ + aFire = 1; + HasState = 1; + } + if(Port[Path0].StateTable[Path1] & dEpStateBitFault){ + aFault = 1; + HasState = 1; + } + if(Port[Path0].StateTable[Path1] & dEpStateBitMask){ + aMask = 1; + HasState = 1; + } + + aPanel->SText[12].TextClear(); + HasWrote = 0; + if(aFire){ + TMyString::sFromStr("报警",aPanel->SText[12].Text); + HasWrote = 1; + } + if(aFault){ + if(HasWrote){ + TMyString::sAddOnStr("\/故障",aPanel->SText[12].Text); + }else{ + TMyString::sFromStr("故障",aPanel->SText[12].Text); + } + } + if(aMask){ + if(HasWrote){ + TMyString::sAddOnStr("\/屏蔽",aPanel->SText[12].Text); + }else{ + TMyString::sFromStr("屏蔽",aPanel->SText[12].Text); + } + } + if(HasState == 0){ + TMyString::sFromStr("正常运行 ",aPanel->SText[12].Text); + } + + //aType = Port[Path0].dTypeTable[Path1]; + //TMyString::sFromStr(StrType[aType],aPanel->SText[11].Text); + } + + aPanel->SText[11].Show(); + aPanel->SText[12].Show(); + aPanel->SText[13].Show(); +} + +void TEpMonitor::TryDec() +{ + int iVal; + if(aPanel->Edit[0].Selected){ + iVal = aPanel->Edit[0].Str.ToInteger(); + iVal --; + if(iVal <1)iVal = 1; + aPanel->Edit[0].Str.FromInt(iVal); + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[0].Show(); + }else + if(aPanel->Edit[1].Selected){ + iVal = aPanel->Edit[1].Str.ToInteger(); + iVal --; + if(iVal <1)iVal = 1; + aPanel->Edit[1].Str.FromInt(iVal); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[1].Show(); + } +} + +void TEpMonitor::TryInc() +{ + int iVal; + if(aPanel->Edit[0].Selected){ + iVal = aPanel->Edit[0].Str.ToInteger(); + iVal ++; + if(iVal > 40)iVal = 40; + aPanel->Edit[0].Str.FromInt(iVal); + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[0].Show(); + }else + if(aPanel->Edit[1].Selected){ + iVal = aPanel->Edit[1].Str.ToInteger(); + iVal ++; + if(iVal >250)iVal = 250; + aPanel->Edit[1].Str.FromInt(iVal); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[1].Show(); + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TEpMonitor::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + int aVal; + Updata = 0; + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].ReDraw(); + }else + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].ReDraw(); + } + CheckPath(); + RedrawState(); + } + + if(aKey == VK_UP){ + TryInc(); + CheckPath(); + RedrawState(); + }else + if(aKey == VK_DOWN){ + TryDec(); + CheckPath(); + RedrawState(); + }else + if(aKey == VK_TAB){ + if(CtlIndex){ + CtlIndex = 0; + }else{ + CtlIndex = 1; + } + Check4Selected(); + aPanel->ReDrawItems(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + Check4Selected(); + aPanel->ReDrawItems(); + }else + if(aKey == VK_RETURN){ + IsShowing = 0; + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TEpMonitor::InitPanel(void) +{ + int x,y, aW,aH,i; + + x = Content.Left; + y = Content.Top; + aW = Content.Width; + aH = 40; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + aPanel->Caption.Text[0] = 0; + + aPanel->SText[0].Init(60,26,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(400,26,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(60,76,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(60,126,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(60,176,60,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路号:", aPanel->SText[0].Text); + TMyString::sFromStr("地址号:", aPanel->SText[1].Text); + TMyString::sFromStr("类型:", aPanel->SText[2].Text); + TMyString::sFromStr("状态:", aPanel->SText[3].Text); + TMyString::sFromStr("位置:", aPanel->SText[4].Text); + + aPanel->SText[11].Init(160,76,400,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[12].Init(160,126,400,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[13].Init(160,176,400,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("未知", aPanel->SText[11].Text); + TMyString::sFromStr("未知", aPanel->SText[12].Text); + TMyString::sFromStr("未知", aPanel->SText[13].Text); + + aPanel->Edit[0].Init(170,26,40,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(500,26,50,30,x,y,clNearBlack,clNearWhite); + + for(i=0; i<2;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.Clear(); + } + aPanel->Edit[0].Str.FromStr("01"); + aPanel->Edit[1].Str.FromStr("001"); + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[1].SetMaxLen(3); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[1].Pst = 2; + + aPanel->Caption.Visible = 1; + + //aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + RedrawState(); +} + +int TEpMonitor::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} + diff --git a/MyCode/Gui/EpMonitor.h b/MyCode/Gui/EpMonitor.h new file mode 100644 index 0000000..f87d69f --- /dev/null +++ b/MyCode/Gui/EpMonitor.h @@ -0,0 +1,78 @@ +#ifndef EPMONITOR_H_ +#define EPMONITOR_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +#include "Record.h" + +class TEpMonitor{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + + u32 Color; + + int TabOrder; + + TRect Bound; + TRect Content; + + unsigned char CtlIndex; + unsigned char Path0; + unsigned char Path1; + + int IsShowing; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TEpMonitor(){}; + TEpMonitor(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + void DrawList(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void CheckPath(); + void RedrawState(); + + void Check4Selected(void); + + void SendCmd(int StartStop); + void ResetData(); + + void Task1000Ms(); + + void TryDec(); + void TryInc(); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + diff --git a/MyCode/Gui/EventShow.cpp b/MyCode/Gui/EventShow.cpp new file mode 100644 index 0000000..e55f3f3 --- /dev/null +++ b/MyCode/Gui/EventShow.cpp @@ -0,0 +1,3791 @@ +#include "EventShow.h" +#include "RuntimeData.h" +#include "server.h" + +#define dsLineCount 4 +#define dlLineCount 10 + +#define MsgX0 14 + +#define clReadOk clTeal +#define clSelectedUnRead clBlue +#define clSelectedRead clDarkBlue //clAqua + +#define dLineMaxLen 62 + +static int cMaxSelLine[5] = {2,2,5,5,5}; + +const char ccFF[8] = " 1st"; +//const char ccMC[8] = "本机"; +//const char ccCC[8] = "回路"; +const char CapStringCn[6][16] = {"火警:", "联动:", "监管:", "故障:", "屏蔽:", " "}; //"总延时:" +const char CapStringEn[6][16] = {"Fire:", "Link:", "SUPV:", "Fail:", "Mask:", " "}; //"TDelay:" +const char CapStringDownCn[4][16] = {"启动:", "反馈:", "延时启动:", "停止:"}; +const char CapStringDownEn[4][16] = {"ACTD:", "FBCK:", "DelayAct:", "STOP:"}; + +const unsigned int clUnRead[5] = {cldRed, cldMaroon, cldOrange, cldYellow, clDarkkGray}; +const unsigned int clTextUnRead[5] = {clNearBlack, clNearBlack, clNearBlack, clNearBlack, clNearWhite}; +const unsigned int clTextHasRead[5] = {clNearWhite, clNearWhite, clNearWhite, clNearWhite, clNearWhite}; + +const static unsigned short stAllTop[10] = { + 96, 130, 164, 198, 232, + 266, 300, 334, 368, 414 +}; + +const static unsigned short stUpTop[4] = { + 96, 130, 164, 198 +}; + +const static unsigned short stDownTop[4] = { + 300, 334, 368, 414 +}; + +const static unsigned short TitleUp = 52; +const static unsigned short TitleDown = 256; + +const static unsigned int stUnFocusColor = clNearBlack; +const static unsigned int stSelectedColor = clBlue; +const static short stScrollBarX0 = 766; + +static void ReadIdfDrawBySize(int ax, int ay, int aW, int aH, int RoundR, u32 aClr, int Active) +{ + TPoint Lt, Lb, Rt, Rb; + Lt.x = ax + RoundR; Lt.y = ay + RoundR; + Lb.x = Lt.x; Lb.y = ay + aH -1 - RoundR; + Rt.x = ax + aW -1 - RoundR; Rt.y = Lt.y; + Rb.x = Rt.x; Rb.y = Lb.y; + + TCircle::sRenderQuadrant(Lt.x, Lt.y, RoundR, 3, aClr, 1); + TCircle::sRenderQuadrant(Rt.x, Rt.y, RoundR, 0, aClr, 1); + TCircle::sRenderQuadrant(Lb.x, Lb.y, RoundR, 2, aClr, 1); + TCircle::sRenderQuadrant(Rb.x, Rb.y, RoundR, 1, aClr, 1); + + BoxRender2D((ax), (ay+RoundR-1), (ax+aW-1), (ay+aH-1-RoundR), aClr); + BoxRender2D((ax+RoundR-1), (ay), (ax+aW-1-RoundR), (ay+RoundR-1), aClr); + BoxRender2D((ax+RoundR-1), (ay+aH-1-RoundR), (ax+aW-1-RoundR), (ay+aH-1), aClr); + + if(Active){ + TPoint Gp; + const int PenWidth = (aW * aH) / 200 ; + const int OffSet0 = (aW * aH) / 120; + const int OffSet1 = OffSet0 * 23 / 10; + Gp.x = ax + (aW * 10 / 45); + Gp.y = ay + (aH / 2); + + LineRender(Gp.x, Gp.y, Gp.x +OffSet0, Gp.y +OffSet0, PenWidth, clNearBlack); + LineRender(Gp.x +OffSet0, Gp.y +OffSet0, Gp.x +OffSet0 + OffSet1, Gp.y +OffSet0 - OffSet1, PenWidth, clNearBlack); + } +} + +void TEventShow::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, int BoderW, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top, Right, Bottom); + ContentUp.Set(Left, Top, Right-20, Bottom - 300); + ContentDown.Set(Left, Top + 300, Right-20, Bottom); + SText.Init (519, Top, 280, CH, 0, 0, clWhite, clMaroon); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + WhatSelected = 0; + + SelectedCol =0; + SelectedUpCol =0; + SelectedDownCol =0; + + FirstFireHadDraw = 0; + NoKeyInTick500mS = 99; + NoNewEventTick500mS = 99; + + MsgList[0].Count =0; + MsgList[1].Count =0; + MsgList[2].Count =0; + MsgList[3].Count =0; + MsgList[4].Count =0; + + MsgList[0].NewCount =0; + MsgList[1].NewCount =0; + MsgList[2].NewCount =0; + MsgList[3].NewCount =0; + MsgList[4].NewCount =0; + + MsgList[0].IsListUpdata = 0; + MsgList[1].IsListUpdata = 0; + MsgList[2].IsListUpdata = 0; + MsgList[3].IsListUpdata = 0; + MsgList[4].IsListUpdata = 0; + MsgList[0].RefrashIndex = 0; + MsgList[1].RefrashIndex = 0; + MsgList[2].RefrashIndex = 0; + MsgList[3].RefrashIndex = 0; + MsgList[4].RefrashIndex = 0; + + MsgList[0].TopIndex =0; + MsgList[1].TopIndex =0; + MsgList[2].TopIndex =0; + MsgList[3].TopIndex =0; + MsgList[4].TopIndex =0; + MsgList[0].ReqTopIndex =0; + MsgList[1].ReqTopIndex =0; + MsgList[2].ReqTopIndex =0; + MsgList[3].ReqTopIndex =0; + MsgList[4].ReqTopIndex =0; + + MsgList[0].TailRemain =0; + MsgList[1].TailRemain =0; + MsgList[2].TailRemain =0; + MsgList[3].TailRemain =0; + MsgList[4].TailRemain =0; + + MsgList[1].StartCount =0; + MsgList[1].FbCount =0; + MsgList[1].DelayCount =0; + + for(i=0; i<10; i++){ + MsgList[0].Body[i].D32[0] =0; + MsgList[0].Body[i].D32[1] =0; + MsgList[0].Body[i].D32[2] =0; + MsgList[0].Body[i].D32[3] =0; + MsgList[0].Body[i].D32[4] =0; + MsgList[0].Body[i].D32[5] =0; + + MsgList[1].Body[i].D32[0] =0; + MsgList[1].Body[i].D32[1] =0; + MsgList[1].Body[i].D32[2] =0; + MsgList[1].Body[i].D32[3] =0; + MsgList[1].Body[i].D32[4] =0; + MsgList[1].Body[i].D32[5] =0; + + MsgList[2].Body[i].D32[0] =0; + MsgList[2].Body[i].D32[1] =0; + MsgList[2].Body[i].D32[2] =0; + MsgList[2].Body[i].D32[3] =0; + MsgList[2].Body[i].D32[4] =0; + MsgList[2].Body[i].D32[5] =0; + + MsgList[3].Body[i].D32[0] =0; + MsgList[3].Body[i].D32[1] =0; + MsgList[3].Body[i].D32[2] =0; + MsgList[3].Body[i].D32[3] =0; + MsgList[3].Body[i].D32[4] =0; + MsgList[3].Body[i].D32[5] =0; + + MsgList[0].Body[i].D32[0] =0; + MsgList[0].Body[i].D32[1] =0; + MsgList[0].Body[i].D32[2] =0; + MsgList[0].Body[i].D32[3] =0; + MsgList[0].Body[i].D32[4] =0; + MsgList[0].Body[i].D32[5] =0; + + MsgBuf[i].D32[0] = 0; + MsgBuf[i].D32[1] = 0; + MsgBuf[i].D32[2] = 0; + MsgBuf[i].D32[3] = 0; + MsgBuf[i].D32[4] = 0; + MsgBuf[i].D32[5] = 0; + } + IsShouldReturn = 0; + this->IsShowing = 0; + LastDrawSplite = 0; + Text[0] = 0; + Text[79] = 0; + + DrawListNotDone[0]=0; + DrawListNotDone[1]=0; + DrawListNotDone[2]=0; + DrawListNotDone[3]=0; + DrawListNotDone[4]=0; + + //StartCountDownList.Count = 0; + //for(i=0; i<1000; i++){ + // StartCountDownList.Path[i] = 0; + // StartCountDownList.TimeSec[i] = 0; + //} + + GolbalDelayValueOnShowing =0; + + IsGoReset = 0; +} + + +void TEventShow::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + //VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + //VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + //VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + //HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + //HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + //HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + //VertLineRender (x, y, h-1, 0xFF808080); + //HorizLineRender (x, y, w-1, 0xFF808080); + + //VertLineRender (x+1, y+1, h-2, 0xFF404040); + //HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + //VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + //HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + //VertLineRender (x2, y, h, 0xFFFFFFFF); + //HorizLineRender (x, y2, w, 0xFFFFFFFF); + RectFillRender(0, Bound.Top, 799, Bound.Bottom, clNearBlack); + //RectFillRender(0, RectTitleBtm.Top, 799, RectTitleBtm.Bottom, clNearBlack); + +}; + +void TEventShow::Show(void) +{ + LastDrawSplite = 0; + DrawSelf(); + DrawList(); + this->IsShowing = 1; + + EventShowOnShowCallBack(); +} + +void TEventShow::Hide() +{ + this->IsShowing = 0; + LastDrawSplite = 0; +} + +void TEventShow::DrawAll(void) +{ + +} + +void TEventShow::CoverDateTimeIllegal(TieMsg Src, TDateTimeBytes *Dst) +{ + unsigned char aValTens, aValOnes, aVal; + if ((Src.Splite.Year / 16) > 9) goto Illegal_Here; + if ((Src.Splite.Year % 16) > 9) goto Illegal_Here; + + aValTens = Src.Splite.Month / 16 *10; + aValOnes = Src.Splite.Month % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) == 0) goto Illegal_Here; + if( (aValTens + aValOnes) > 12) goto Illegal_Here; + + aValTens = Src.Splite.Day / 16 *10; + aValOnes = Src.Splite.Day % 16; + if( aValOnes > 9) goto Illegal_Here; + aVal = aValTens + aValOnes; + if(aVal == 0) goto Illegal_Here; + if(aVal > 31) goto Illegal_Here; + + aValTens = Src.Splite.Hour / 16 *10; + aValOnes = Src.Splite.Hour % 16; + if( aValOnes > 9) goto Illegal_Here; + aVal = aValTens + aValOnes; + if( aVal > 23) goto Illegal_Here; + + aValTens = Src.Splite.Minute / 16 *10; + aValOnes = Src.Splite.Minute % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) > 59) goto Illegal_Here; + + aValTens = Src.Splite.Second / 16 *10; + aValOnes = Src.Splite.Second % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) > 59) goto Illegal_Here; + + Dst->Year = Src.Splite.Year; + Dst->Month = Src.Splite.Month; + Dst->Day = Src.Splite.Day; + Dst->Hour = Src.Splite.Hour; + Dst->Minute = Src.Splite.Minute; + Dst->Second = Src.Splite.Second; + return; + + Illegal_Here: + Dst->Year = 0x22; + Dst->Month = 0x01; + Dst->Day = 0x01; + Dst->Hour = 0x08; + Dst->Minute = 0x10; + Dst->Second = 0x10; +} + +void TEventShow::CoverDateTimeIllegal(TEventMsg Src, TDateTimeBytes *Dst) +{ + unsigned char aValTens, aValOnes, aVal; + if ((Src.Splite.Year / 16) > 9) goto Illegal_Here; + if ((Src.Splite.Year % 16) > 9) goto Illegal_Here; + + aValTens = Src.Splite.Month / 16 *10; + aValOnes = Src.Splite.Month % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) == 0) goto Illegal_Here; + if( (aValTens + aValOnes) > 12) goto Illegal_Here; + + aValTens = Src.Splite.Day / 16 *10; + aValOnes = Src.Splite.Day % 16; + if( aValOnes > 9) goto Illegal_Here; + aVal = aValTens + aValOnes; + if(aVal == 0) goto Illegal_Here; + if(aVal > 31) goto Illegal_Here; + + aValTens = Src.Splite.Hour / 16 *10; + aValOnes = Src.Splite.Hour % 16; + if( aValOnes > 9) goto Illegal_Here; + aVal = aValTens + aValOnes; + if( aVal > 23) goto Illegal_Here; + + aValTens = Src.Splite.Minute / 16 *10; + aValOnes = Src.Splite.Minute % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) > 59) goto Illegal_Here; + + aValTens = Src.Splite.Second / 16 *10; + aValOnes = Src.Splite.Second % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) > 59) goto Illegal_Here; + + Dst->Year = Src.Splite.Year; + Dst->Month = Src.Splite.Month; + Dst->Day = Src.Splite.Day; + Dst->Hour = Src.Splite.Hour; + Dst->Minute = Src.Splite.Minute; + Dst->Second = Src.Splite.Second; + return; + + Illegal_Here: + Dst->Year = 0x22; + Dst->Month = 0x01; + Dst->Day = 0x01; + Dst->Hour = 0x08; + Dst->Minute = 0x10; + Dst->Second = 0x10; +} + +void TEventShow::FillText(unsigned char aWhat, unsigned int aIndex, unsigned int aLineNum) +{ + unsigned int i; + unsigned int d,e; + unsigned int data; + unsigned char aCn; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char P0,P1; + unsigned int DelaySec; + TDMix16 Dmix; + + if(aLineNum > 9)return; + + if(aWhat == 0){ + if(aIndex >= ieMSG_FIRE_MAX_COUNT)return; + }else + if(aWhat == 1){ + if(aIndex >= ieMSG_LINKAGE_MAX_COUNT)return; + }else + if(aWhat == 2){ + if(aIndex >= ieMSG_SV_MAX_COUNT)return; + }else + if(aWhat == 3){ + if(aIndex >= ieMSG_FAULT_MAX_COUNT)return; + }else + if(aWhat == 4){ + if(aIndex >= ieMSG_MASK_MAX_COUNT)return; + } + + NeedShowDescp = 0; + + data = (aIndex +1) % 100000; + + d = data/10000; + e = d % 10; + Text[0] = e + '0'; + + d = data/1000; + e = d % 10; + Text[1] = e + '0'; + + d = data/100; + e = d % 10; + Text[2] = e + '0'; + + d = data/10; + e = d % 10; + Text[3] = e + '0'; + + e = data % 10; + Text[4] = e + '0'; + + Text[5] = ' '; + + this->CoverDateTimeIllegal( MsgList[aWhat].Body[aLineNum], &DateTimeCovered); + Text[6] = DateTimeCovered.Year / 16 % 10 + '0'; + Text[7] = DateTimeCovered.Year % 16 % 10 + '0'; + Text[8] = '/'; + Text[9] = DateTimeCovered.Month / 16 % 10 + '0'; + Text[10] = DateTimeCovered.Month % 16 % 10 + '0'; + Text[11] = '/'; + Text[12] = DateTimeCovered.Day / 16 % 10 + '0'; + Text[13] = DateTimeCovered.Day % 16 % 10 + '0'; + Text[14] = ' '; + Text[15] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text[16] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text[17] = ':'; + Text[18] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text[19] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text[20] = ':'; + Text[21] = DateTimeCovered.Second / 16 % 10 + '0'; + Text[22] = DateTimeCovered.Second % 16 % 10 + '0'; + Text[23] = ' '; + + data = MsgList[aWhat].Body[aLineNum].Splite.PCtlNum; + d = data/10; + e = d % 10; + Text[24] = e + '0'; + e = data % 10; + Text[25] = e + '0'; + Text[26] = '-'; + + data = MsgList[aWhat].Body[aLineNum].Splite.P0; + d = data/10; + e = d % 10; + Text[27] = e + '0'; + e = data % 10; + Text[28] = e + '0'; + Text[29] = '-'; + + Text[30] = '\0'; + + if(aWhat == 3){ + if( (MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xC0){ + Text[26] = ' '; + Text[27] = '\0'; + if( (MsgList[aWhat].Body[aLineNum].Splite.P1 >= dADDR_HANDPAD_START) && (MsgList[aWhat].Body[aLineNum].Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("总线盘 ",Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1 -dADDR_HANDPAD_START +1,Text); + TMyString::sAddOnStr(" 离线",Text); + } + if( (MsgList[aWhat].Body[aLineNum].Splite.P1 >= dADDR_DIRECTPAD_START) && (MsgList[aWhat].Body[aLineNum].Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("多线盘 ",Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1 -dADDR_DIRECTPAD_START +1,Text); + TMyString::sAddOnStr(" 离线",Text); + } + }else + if((MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xD0){ + Text[26] = ' '; + Text[27] = '\0'; + TMyString::sAddOnStr("设备故障 ",Text); + aType = MsgList[aWhat].Body[aLineNum].Splite.Data0; + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultType[aType],Text); + if( (aType == 15) || (aType == 16) ){ + Text[27] = '\0'; + TMyString::sAddOnStr(StrDevFaultType[aType],Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1, Text); + TMyString::sAddOnStr(" 通讯故障",Text); + //if(MsgList[aWhat].Body[aLineNum].Splite.mType > 200){ + // TMyString::sAddOnStr(" 通讯故障条目数:多于200",Text); + //}else{ + // TMyString::sAddOnStr("通讯故障条目数:",Text); + // TMyString::sAddOn3Dg(MsgList[aWhat].Body[aLineNum].Splite.mType, Text); + //} + }else + if( (aType == 19) || (aType == 20) || (aType == 21) || (aType == 23) || (aType == 26) || (aType == 27) ){ + TMyString::sAddOnStr(" ",Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1, Text); + } + }else{ + TMyString::sAddOnStr("未知类型",Text); + } + }else + if((MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xE0){ + //Cir Error + TMyString::sAddOnStr("回路故障",Text); + }else + if((MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + Text[26] = ' '; + Text[27] = '\0'; + TMyString::sAddOnStr("板卡故障 ",Text); + aType = MsgList[aWhat].Body[aLineNum].Splite.Data0; + if( (aType == TBoardFaultType::LoopMotherBoard) || + (aType == TBoardFaultType::RegisteredData) || + (aType == TBoardFaultType::MaskedData) || + (aType == TBoardFaultType::StorageEpDType) || + (aType == TBoardFaultType::StorageEpAuxId) || + (aType == TBoardFaultType::StorageEpArea) || + (aType == TBoardFaultType::StorageEpAssignedType) || + (aType == TBoardFaultType::StorageEpSignalType) || + (aType == TBoardFaultType::StorageDirectPadCfg) || + (aType == TBoardFaultType::StoragePortDpSet) || + (aType == TBoardFaultType::StorageBusPadCfg) ){ + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1,Text); + TMyString::sAddOnStr(" ",Text); + }else + if( (aType == TBoardFaultType::StorageLinkExpressionPart1) || + (aType == TBoardFaultType::StorageLinkExpressionPart2) || + (aType == TBoardFaultType::StorageLinkExpressionPart3) || + (aType == TBoardFaultType::StorageLinkExpressionPart4) || + (aType == TBoardFaultType::StorageLinkExpressionPart5) || + (aType == TBoardFaultType::StorageLinkExpressionPart6) || + (aType == TBoardFaultType::StorageLinkExpressionPart7) || + (aType == TBoardFaultType::StorageLinkExpressionPart8) || + (aType == TBoardFaultType::StorageLinkExpressionPart9) ){ + unsigned short tInx = aType - static_cast(TBoardFaultType::StorageLinkExpressionPart1); + tInx = tInx * 256 + MsgList[aWhat].Body[aLineNum].Splite.P1; + TMyString::sAddOn4Dg(tInx % 10000,Text); + TMyString::sAddOnStr(" ",Text); + } + if(aType < TBoardFaultType::MaxValue){ + TMyString::sAddOnStr(StrBrdFaultType[aType],Text); + }else{ + TMyString::sAddOnStr("未知类型",Text); + } + }else{ + //EpError + data = MsgList[aWhat].Body[aLineNum].Splite.P1; + d = data/100; + e = d % 10; + Text[30] = e + '0'; + d = data/10; + e = d % 10; + Text[31] = e + '0'; + e = data % 10; + Text[32] = e + '0'; + Text[33] = ' '; + + aP0 = MsgList[aWhat].Body[aLineNum].Splite.P0; + aP1 = MsgList[aWhat].Body[aLineNum].Splite.P1; + data = MsgList[aWhat].Body[aLineNum].Splite.UserCode; + d = data/10000000; + e = d % 10; + Text[34] = e + '0'; + d = data/1000000; + e = d % 10; + Text[35] = e + '0'; + d = data/100000; + e = d % 10; + Text[36] = e + '0'; + d = data/10000; + e = d % 10; + Text[37] = e + '0'; + d = data/1000; + e = d % 10; + Text[38] = e + '0'; + d = data/100; + e = d % 10; + Text[39] = e + '0'; + d = data/10; + e = d % 10; + Text[40] = e + '0'; + e = data % 10; + Text[41] = e + '0'; + Text[42] = ' '; + + Text[43] = 0; + + aType = MsgList[aWhat].Body[aLineNum].Splite.Data0; + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultType[aType],Text); + }else{ + TMyString::sAddOnStr("未知故障",Text); + } + + aType = MsgList[aWhat].Body[aLineNum].Splite.dType; + for(i=0; i<6; i++)TextDescp[i] = ' '; + TextDescp[6] = '\0'; + if( (aP0 >0) && (aP0 <= 40) ){ + P0 = aP0-1; + if(aP1 >0){ + NeedShowDescp = 1; + P1 = aP1-1; + if(MsgList[aWhat].Body[aLineNum].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[P0].ExistTable[P1] == 0){ + TMyString::sAddOnStr("未登记",TextDescp); + }else{ + TMyString::sAddOnStr(StrTypeShortName[aType],TextDescp); + } + }else{ + TMyString::sAddOnStr(StrTypeShortName[aType],TextDescp); + } + }else{ + TMyString::sAddOnStr("未登记",TextDescp); + } + TMyString::sFillFixLen(TextDescp,28); + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if( (aP1>0) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + NeedShowDescp = 1; + if(aType){ + TMyString::sAddOnStr(StrTypeShortName[aType],TextDescp); + }else{ + TMyString::sAddOnStr("多线盘节点",TextDescp); + } + } + + TMyString::sFillFixLen(TextDescp,28); + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + TextDescp[28] = '\0'; + } + } + }else{ + aP0 = MsgList[aWhat].Body[aLineNum].Splite.P0; + aP1 = MsgList[aWhat].Body[aLineNum].Splite.P1; + + data = MsgList[aWhat].Body[aLineNum].Splite.P1; + d = data/100; + e = d % 10; + Text[30] = e + '0'; + d = data/10; + e = d % 10; + Text[31] = e + '0'; + e = data % 10; + Text[32] = e + '0'; + Text[33] = ' '; + + data = MsgList[aWhat].Body[aLineNum].Splite.UserCode; + d = data/1000'0000; + e = d % 10; + Text[34] = e + '0'; + d = data/100'0000; + e = d % 10; + Text[35] = e + '0'; + d = data/10'0000; + e = d % 10; + Text[36] = e + '0'; + d = data/10000; + e = d % 10; + Text[37] = e + '0'; + d = data/1000; + e = d % 10; + Text[38] = e + '0'; + d = data/100; + e = d % 10; + Text[39] = e + '0'; + d = data/10; + e = d % 10; + Text[40] = e + '0'; + e = data % 10; + Text[41] = e + '0'; + Text[42] = ' '; + + Text[43] = 0; + aType = MsgList[aWhat].Body[aLineNum].Splite.dType; + if( (aP0 >0) && (aP0 <= 40) ){ + P0 = aP0-1; + if(aP1 >0){ + NeedShowDescp = 1; + P1 = aP1-1; + if(MsgList[aWhat].Body[aLineNum].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[P0].ExistTable[P1] == 0){ + TMyString::sAddOnStr("未登记",Text); + }else{ + TMyString::sAddOnStr(StrTypeShortName[aType],Text); + } + }else{ + TMyString::sAddOnStr(StrTypeShortName[aType],Text); + } + }else{ + TMyString::sAddOnStr("未登记",Text); + } + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + NeedShowDescp = 1; + if(aType){ + TMyString::sAddOnStr(StrTypeShortName[aType],Text); + }else{ + TMyString::sAddOnStr("多线盘节点",Text); + } + if( (aP1>0) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) )NeedShowDescp = 1; + }else{ + TMyString::sAddOnStr("未登记",Text); + } + + if(aWhat == 1){ + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x01){ + TMyString::sAddOnStr("-启动",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x02){ + Text[26] = '\0'; + TMyString::sAddOnStr("声光启动",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x03){ + TMyString::sAddOnStr("-反馈",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x04){ + TMyString::sAddOnStr("-反馈缺失",Text); + }else + + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x05){ + //TMyString::sAddOnStr("-手动启动",Text); + TMyString::sAddOnStr("-启动",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x06){ + Text[26] = ' '; + Text[27] = '\0'; + //TMyString::sAddOnStr("-手动声光启动",Text); + TMyString::sAddOnStr("-声光启动",Text); + return; + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x07){ + Text[26] = ' '; + Text[27] = '\0'; + TMyString::sAddOnStr("-应答消钮",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x09){ + TMyString::sAddOnStr("-已停止",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x0A){ + TMyString::sBrokeFixLen(Text,56); + } + } + + TMyString::sAddOnStr(" ",Text); + } + + if(NeedShowDescp){ + if(aWhat != 3){ + if(aWhat == 0){ + if(MsgList[0].Body[aLineNum].Splite.Data0 == TControlCenter::LinkInputTypeFireSimulate){ + TMyString::sFromStr("模拟",TextDescp); + for(i=4; i<28; i++)TextDescp[i] = ' '; + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + }else + if(aWhat == 1){ + if(MsgList[1].Body[aLineNum].Splite.Data1 == TControlCenter::StartTypeSimulate){ + TMyString::sFromStr("模拟",TextDescp); + for(i=4; i<28; i++)TextDescp[i] = ' '; + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + }else + if(aWhat == 2){ + if(MsgList[2].Body[aLineNum].Splite.Data1 == TControlCenter::StartTypeSimulate){ + TMyString::sFromStr("模拟",TextDescp); + for(i=4; i<28; i++)TextDescp[i] = ' '; + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + TextDescp[28] = '\0'; + } + + aCn = MsgList[aWhat].Body[aLineNum].Splite.PCtlNum; + aP0 = MsgList[aWhat].Body[aLineNum].Splite.P0; + aP1 = MsgList[aWhat].Body[aLineNum].Splite.P1; + + if(MsgList[aWhat].Body[aLineNum].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if( (aP0) && (aP1) ){ + if(aP0 <= dPORT_MAX_COUNT){ + d = aP0-1; + e = aP1-1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + d = aP0 - dADDR_DIRECTPAD_START; + e = d * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + d = 40; + } + data = dAddrSdRam_Descp + (d * 256 * 32) + (e * 32); + for(i=0; i<32; i++){ + TextDescp[i+28] = *(volatile unsigned char *)(data + i); + if( (TextDescp[i+28] == '\0') || (TextDescp[i+28] == 0) ){ + break; + } + } + } + }else{ + if( (aCn) && (aCn <= dNETWORK_MACHINE_COUNT) ){ + aCn --; + if( (aP0) && (aP1) ){ + if(aP0 <= dPORT_MAX_COUNT){ + d = aP0-1; + e = aP1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + d = aP0 - dADDR_DIRECTPAD_START; + e = d * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + d = 40; + } + data = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(d*8192) + (e*32); + for(i=0; i<32; i++){ + TextDescp[i+28] = *(volatile unsigned char *)(data + i); + if( (TextDescp[i+28] == '\0') || (TextDescp[i+28] == 0) ){ + break; + } + } + } + } + } + TMyString::sBrokeFixLen(TextDescp,62); + } + TMyString::sBrokeFixLen(Text,62); +} + + +void TEventShow::FillTextEn(unsigned char aWhat, unsigned int aIndex, unsigned int aLineNum) +{ + unsigned int i; + unsigned int d,e; + unsigned int data; + unsigned char aCn; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char P0,P1; + unsigned int DelaySec; + TDMix16 Dmix; + + if(aLineNum > 9)return; + + if(aWhat == 0){ + if(aIndex >= ieMSG_FIRE_MAX_COUNT)return; + }else + if(aWhat == 1){ + if(aIndex >= ieMSG_LINKAGE_MAX_COUNT)return; + }else + if(aWhat == 2){ + if(aIndex >= ieMSG_SV_MAX_COUNT)return; + }else + if(aWhat == 3){ + if(aIndex >= ieMSG_FAULT_MAX_COUNT)return; + }else + if(aWhat == 4){ + if(aIndex >= ieMSG_MASK_MAX_COUNT)return; + } + + NeedShowDescp = 0; + + data = (aIndex +1) % 100000; + + d = data/10000; + e = d % 10; + Text[0] = e + '0'; + + d = data/1000; + e = d % 10; + Text[1] = e + '0'; + + d = data/100; + e = d % 10; + Text[2] = e + '0'; + + d = data/10; + e = d % 10; + Text[3] = e + '0'; + + e = data % 10; + Text[4] = e + '0'; + + Text[5] = ' '; + this->CoverDateTimeIllegal( MsgList[aWhat].Body[aLineNum], &DateTimeCovered); + Text[6] = DateTimeCovered.Year / 16 % 10 + '0'; + Text[7] = DateTimeCovered.Year % 16 % 10 + '0'; + Text[8] = '/'; + Text[9] = DateTimeCovered.Month / 16 % 10 + '0'; + Text[10] = DateTimeCovered.Month % 16 % 10 + '0'; + Text[11] = '/'; + Text[12] = DateTimeCovered.Day / 16 % 10 + '0'; + Text[13] = DateTimeCovered.Day % 16 % 10 + '0'; + Text[14] = ' '; + Text[15] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text[16] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text[17] = ':'; + Text[18] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text[19] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text[20] = ':'; + Text[21] = DateTimeCovered.Second / 16 % 10 + '0'; + Text[22] = DateTimeCovered.Second % 16 % 10 + '0'; + Text[23] = ' '; + + data = MsgList[aWhat].Body[aLineNum].Splite.PCtlNum; + d = data/10; + e = d % 10; + Text[24] = e + '0'; + e = data % 10; + Text[25] = e + '0'; + Text[26] = '-'; + + data = MsgList[aWhat].Body[aLineNum].Splite.P0; + d = data/10; + e = d % 10; + Text[27] = e + '0'; + e = data % 10; + Text[28] = e + '0'; + Text[29] = '-'; + + Text[30] = '\0'; + + if(aWhat == 3){ + if( (MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xC0){ + Text[26] = ' '; + Text[27] = '\0'; + if( (MsgList[aWhat].Body[aLineNum].Splite.P1 >= dADDR_HANDPAD_START) && (MsgList[aWhat].Body[aLineNum].Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("Bus KeyPad ",Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1 -dADDR_HANDPAD_START +1,Text); + TMyString::sAddOnStr(" Offline",Text); + } + if( (MsgList[aWhat].Body[aLineNum].Splite.P1 >= dADDR_DIRECTPAD_START) && (MsgList[aWhat].Body[aLineNum].Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("Direct KeyPad ",Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1 -dADDR_DIRECTPAD_START +1,Text); + TMyString::sAddOnStr(" Offline",Text); + } + }else + if((MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xD0){ + Text[26] = ' '; + Text[27] = '\0'; + TMyString::sAddOnStr("Dev Fail ",Text); + aType = MsgList[aWhat].Body[aLineNum].Splite.Data0; + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultTypeEn[aType],Text); + if( (aType == 15) || (aType == 16) ){ + Text[27] = '\0'; + TMyString::sAddOnStr(StrDevFaultTypeEn[aType],Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1, Text); + TMyString::sAddOnStr(" Offline",Text); + //if(MsgList[aWhat].Body[aLineNum].Splite.mType > 200){ + // TMyString::sAddOnStr(" 通讯故障条目数:多于200",Text); + //}else{ + // TMyString::sAddOnStr("通讯故障条目数:",Text); + // TMyString::sAddOn3Dg(MsgList[aWhat].Body[aLineNum].Splite.mType, Text); + //} + }else + if( (aType == 19) || (aType == 20) || (aType == 21) || (aType == 23) || (aType == 26) || (aType == 27) ){ + TMyString::sAddOnStr(" ",Text); + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1, Text); + } + }else{ + TMyString::sAddOnStr("Unknown",Text); + } + }else + if((MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xE0){ + //Cir Error + TMyString::sAddOnStr("Loop Fail",Text); + }else + if((MsgList[aWhat].Body[aLineNum].Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + Text[26] = ' '; + Text[27] = '\0'; + TMyString::sAddOnStr("Board Err ",Text); + aType = MsgList[aWhat].Body[aLineNum].Splite.Data0; + if( (aType == TBoardFaultType::LoopMotherBoard) || + (aType == TBoardFaultType::RegisteredData) || + (aType == TBoardFaultType::MaskedData) || + (aType == TBoardFaultType::StorageEpDType) || + (aType == TBoardFaultType::StorageEpAuxId) || + (aType == TBoardFaultType::StorageEpArea) || + (aType == TBoardFaultType::StorageEpAssignedType) || + (aType == TBoardFaultType::StorageEpSignalType) || + (aType == TBoardFaultType::StorageDirectPadCfg) || + (aType == TBoardFaultType::StoragePortDpSet) || + (aType == TBoardFaultType::StorageBusPadCfg) ){ + TMyString::sAddOn2Dg(MsgList[aWhat].Body[aLineNum].Splite.P1,Text); + TMyString::sAddOnStr(" ",Text); + }else + if( (aType == TBoardFaultType::StorageLinkExpressionPart1) || + (aType == TBoardFaultType::StorageLinkExpressionPart2) || + (aType == TBoardFaultType::StorageLinkExpressionPart3) || + (aType == TBoardFaultType::StorageLinkExpressionPart4) || + (aType == TBoardFaultType::StorageLinkExpressionPart5) || + (aType == TBoardFaultType::StorageLinkExpressionPart6) || + (aType == TBoardFaultType::StorageLinkExpressionPart7) || + (aType == TBoardFaultType::StorageLinkExpressionPart8) || + (aType == TBoardFaultType::StorageLinkExpressionPart9) ){ + unsigned short tInx = aType - static_cast(TBoardFaultType::StorageLinkExpressionPart1); + tInx = tInx * 256 + MsgList[aWhat].Body[aLineNum].Splite.P1; + TMyString::sAddOn4Dg(tInx % 10000,Text); + TMyString::sAddOnStr(" ",Text); + } + if(aType < TBoardFaultType::MaxValue){ + TMyString::sAddOnStr(StrBrdFaultTypeEn[aType],Text); + }else{ + TMyString::sAddOnStr("Unknown",Text); + } + }else{ + //EpError + data = MsgList[aWhat].Body[aLineNum].Splite.P1; + d = data/100; + e = d % 10; + Text[30] = e + '0'; + d = data/10; + e = d % 10; + Text[31] = e + '0'; + e = data % 10; + Text[32] = e + '0'; + Text[33] = ' '; + + aP0 = MsgList[aWhat].Body[aLineNum].Splite.P0; + aP1 = MsgList[aWhat].Body[aLineNum].Splite.P1; + data = MsgList[aWhat].Body[aLineNum].Splite.UserCode; + d = data/10000000; + e = d % 10; + Text[34] = e + '0'; + d = data/1000000; + e = d % 10; + Text[35] = e + '0'; + d = data/100000; + e = d % 10; + Text[36] = e + '0'; + d = data/10000; + e = d % 10; + Text[37] = e + '0'; + d = data/1000; + e = d % 10; + Text[38] = e + '0'; + d = data/100; + e = d % 10; + Text[39] = e + '0'; + d = data/10; + e = d % 10; + Text[40] = e + '0'; + e = data % 10; + Text[41] = e + '0'; + Text[42] = ' '; + + Text[43] = 0; + + aType = MsgList[aWhat].Body[aLineNum].Splite.Data0; + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultTypeEn[aType],Text); + }else{ + TMyString::sAddOnStr("Unknown",Text); + } + + aType = MsgList[aWhat].Body[aLineNum].Splite.dType; + for(i=0; i<6; i++)TextDescp[i] = ' '; + TextDescp[6] = '\0'; + if( (aP0 >0) && (aP0 <= 40) ){ + P0 = aP0-1; + if(aP1 >0){ + NeedShowDescp = 1; + P1 = aP1-1; + if(MsgList[aWhat].Body[aLineNum].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[P0].ExistTable[P1] == 0){ + TMyString::sAddOnStr("UnReg",TextDescp); + }else{ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],TextDescp); + } + }else{ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],TextDescp); + } + }else{ + TMyString::sAddOnStr("UnReg",TextDescp); + } + TMyString::sFillFixLen(TextDescp,28); + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if( (aP1>0) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + NeedShowDescp = 1; + if(aType){ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],TextDescp); + }else{ + TMyString::sAddOnStr("DirectPad Node",TextDescp); + } + } + + TMyString::sFillFixLen(TextDescp,28); + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + TextDescp[28] = '\0'; + } + } + }else{ + aP0 = MsgList[aWhat].Body[aLineNum].Splite.P0; + aP1 = MsgList[aWhat].Body[aLineNum].Splite.P1; + + data = MsgList[aWhat].Body[aLineNum].Splite.P1; + d = data/100; + e = d % 10; + Text[30] = e + '0'; + d = data/10; + e = d % 10; + Text[31] = e + '0'; + e = data % 10; + Text[32] = e + '0'; + Text[33] = ' '; + + data = MsgList[aWhat].Body[aLineNum].Splite.UserCode; + d = data/1000'0000; + e = d % 10; + Text[34] = e + '0'; + d = data/100'0000; + e = d % 10; + Text[35] = e + '0'; + d = data/10'0000; + e = d % 10; + Text[36] = e + '0'; + d = data/10000; + e = d % 10; + Text[37] = e + '0'; + d = data/1000; + e = d % 10; + Text[38] = e + '0'; + d = data/100; + e = d % 10; + Text[39] = e + '0'; + d = data/10; + e = d % 10; + Text[40] = e + '0'; + e = data % 10; + Text[41] = e + '0'; + Text[42] = ' '; + + Text[43] = 0; + aType = MsgList[aWhat].Body[aLineNum].Splite.dType; + if( (aP0 >0) && (aP0 <= 40) ){ + P0 = aP0-1; + if(aP1 >0){ + NeedShowDescp = 1; + P1 = aP1-1; + if(MsgList[aWhat].Body[aLineNum].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[P0].ExistTable[P1] == 0){ + TMyString::sAddOnStr("Unreg",Text); + }else{ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text); + } + }else{ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text); + } + }else{ + TMyString::sAddOnStr("Unreg",Text); + } + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + NeedShowDescp = 1; + if(aType){ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text); + }else{ + TMyString::sAddOnStr("Direct Pad Node",Text); + } + if( (aP1>0) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) )NeedShowDescp = 1; + }else{ + TMyString::sAddOnStr("Unreg",Text); + } + + if(aWhat == 1){ + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x01){ + TMyString::sAddOnStr("-Act",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x02){ + Text[26] = '\0'; + TMyString::sAddOnStr("S+L Act",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x03){ + TMyString::sAddOnStr("-FeedBack",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x04){ + TMyString::sAddOnStr("-FB Miss",Text); + }else + + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x05){ + //TMyString::sAddOnStr("-手动启动",Text); + TMyString::sAddOnStr("-Act",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x06){ + Text[26] = ' '; + Text[27] = '\0'; + //TMyString::sAddOnStr("-手动声光启动",Text); + TMyString::sAddOnStr("-S+L Act",Text); + return; + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x07){ + Text[26] = ' '; + Text[27] = '\0'; + TMyString::sAddOnStr("-Hydrant Ack",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x09){ + TMyString::sAddOnStr("-Stop",Text); + }else + if(MsgList[aWhat].Body[aLineNum].Splite.Data0 == 0x0A){ + TMyString::sBrokeFixLen(Text,56); + } + } + + TMyString::sAddOnStr(" ",Text); + } + + if(NeedShowDescp){ + if(aWhat != 3){ + if(aWhat == 0){ + if(MsgList[0].Body[aLineNum].Splite.Data0 == TControlCenter::LinkInputTypeFireSimulate){ + TMyString::sFromStr("SIM",TextDescp); + for(i=4; i<28; i++)TextDescp[i] = ' '; + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + }else + if(aWhat == 1){ + if(MsgList[1].Body[aLineNum].Splite.Data1 == TControlCenter::StartTypeSimulate){ + TMyString::sFromStr("SIM",TextDescp); + for(i=4; i<28; i++)TextDescp[i] = ' '; + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + }else + if(aWhat == 2){ + if(MsgList[2].Body[aLineNum].Splite.Data1 == TControlCenter::StartTypeSimulate){ + TMyString::sFromStr("SIM",TextDescp); + for(i=4; i<28; i++)TextDescp[i] = ' '; + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + }else{ + for(i=0; i<28; i++)TextDescp[i] = ' '; + } + TextDescp[28] = '\0'; + } + + aCn = MsgList[aWhat].Body[aLineNum].Splite.PCtlNum; + aP0 = MsgList[aWhat].Body[aLineNum].Splite.P0; + aP1 = MsgList[aWhat].Body[aLineNum].Splite.P1; + + if(MsgList[aWhat].Body[aLineNum].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if( (aP0) && (aP1) ){ + if(aP0 <= dPORT_MAX_COUNT){ + d = aP0-1; + e = aP1-1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + d = aP0 - dADDR_DIRECTPAD_START; + e = d * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + d = 40; + } + data = dAddrSdRam_Descp + (d * 256 * 32) + (e * 32); + for(i=0; i<32; i++){ + TextDescp[i+28] = *(volatile unsigned char *)(data + i); + if( (TextDescp[i+28] == '\0') || (TextDescp[i+28] == 0) ){ + break; + } + } + } + }else{ + if( (aCn) && (aCn <= dNETWORK_MACHINE_COUNT) ){ + aCn --; + if( (aP0) && (aP1) ){ + if(aP0 <= dPORT_MAX_COUNT){ + d = aP0-1; + e = aP1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + d = aP0 - dADDR_DIRECTPAD_START; + e = d * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + d = 40; + } + data = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(d*8192) + (e*32); + for(i=0; i<32; i++){ + TextDescp[i+28] = *(volatile unsigned char *)(data + i); + if( (TextDescp[i+28] == '\0') || (TextDescp[i+28] == 0) ){ + break; + } + } + } + } + } + TMyString::sBrokeFixLen(TextDescp,62); + } + TMyString::sBrokeFixLen(Text,62); +} + +void TEventShow::FirstFireFillDescp() +{ + unsigned int aAddr, i; + unsigned int aCn, aP0, aP1; + if(LanguageEnCn==0)TMyString::sFromStr( "首警: ", DescpText.Text); + else TMyString::sFromStr( "First Fire: ", DescpText.Text); + if(CtlCenter.MsgReadTmp.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = CtlCenter.MsgReadTmp.Splite.P0; + aP1 = CtlCenter.MsgReadTmp.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=0; i<8; i++){ + DescpText.D32[i+3] = *(volatile unsigned int *)(aAddr + (i *4)); + } + DescpText.Text[44] =0; + } + }else + if( (CtlCenter.MsgReadTmp.Splite.PCtlNum) && (CtlCenter.MsgReadTmp.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = CtlCenter.MsgReadTmp.Splite.PCtlNum-1; + aP0 = CtlCenter.MsgReadTmp.Splite.P0; + aP1 = CtlCenter.MsgReadTmp.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=0; i<8; i++){ + DescpText.D32[i+3] = *(volatile unsigned int *)(aAddr + (i *4)); + } + DescpText.Text[44] =0; + } + } + if(DescpText.Text[12] == '\0'){ + if(LanguageEnCn==0){ + TMyString::sAddOnStr("未定义位置描述信息", DescpText.Text); + }else{ + TMyString::sAddOnStr("No Description Text", DescpText.Text); + } + } +} + +void TEventShow::DrawFirstFire() +{ + unsigned char aP0, aP1, data, aType, F; + CtlCenter.FireGetViaPath(0); + if(CtlCenter.MsgReadTmp.Splite.State != 0){ + FirstFireHadDraw =1; + FirstFireShowDescpInteval ++; + if(FirstFireShowDescpInteval == 1){ + if(LanguageEnCn==0)TMyString::sFromStr("首警:", Text); + else TMyString::sFromStr(" 1st:", Text); + this->CoverDateTimeIllegal(CtlCenter.MsgReadTmp, &DateTimeCovered); + Text[5] = DateTimeCovered.Year / 16 % 10 + '0'; + Text[6] = DateTimeCovered.Year % 16 % 10 + '0'; + Text[7] = '/'; + Text[8] = DateTimeCovered.Month / 16 % 10 + '0'; + Text[9] = DateTimeCovered.Month % 16 % 10 + '0'; + Text[10] = '/'; + Text[11] = DateTimeCovered.Day / 16 % 10 + '0'; + Text[12] = DateTimeCovered.Day % 16 % 10 + '0'; + Text[13] = ' '; + Text[14] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text[15] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text[16] = ':'; + Text[17] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text[18] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text[19] = ':'; + Text[20] = DateTimeCovered.Second / 16 % 10 + '0'; + Text[21] = DateTimeCovered.Second % 16 % 10 + '0'; + Text[22] = ' '; + Text[23] = '\0'; + //TMyString::sAddOnStr("本机", Text); + TMyString::sAddOn2Dg(CtlCenter.MsgReadTmp.Splite.PCtlNum, Text); + aP0 = CtlCenter.MsgReadTmp.Splite.P0; + aP1 = CtlCenter.MsgReadTmp.Splite.P1; + + TMyString::sAddOnStr("-", Text); + TMyString::sAddOn2Dg(aP0, Text); + TMyString::sAddOnStr("-", Text); + TMyString::sAddOn3Dg(aP1, Text); + TMyString::sAddOnStr(" ", Text); + + TMyString::sAddOn8Dg(CtlCenter.MsgReadTmp.Splite.UserCode, Text); + TMyString::sAddOnStr(" ", Text); + + aType = CtlCenter.MsgReadTmp.Splite.dType; + F =0; + if( (aP0) && (aP1) ){ + if(LanguageEnCn==0){ + if(aP0 <= dPORT_MAX_COUNT){ + TMyString::sAddOnStr(StrTypeShortName[aType], Text); + F =1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if(aType){ + TMyString::sAddOnStr(StrTypeShortName[aType], Text); + }else{ + TMyString::sAddOnStr("多线盘节点", Text); + } + F =1; + } + }else{ + if(aP0 <= dPORT_MAX_COUNT){ + TMyString::sAddOnStr(StrTypeShortNameEn[aType], Text); + F =1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if(aType){ + TMyString::sAddOnStr(StrTypeShortNameEn[aType], Text); + }else{ + TMyString::sAddOnStr("Direct-Pad Node", Text); + } + F =1; + } + } + } + if(F ==0){ + data = 0;//DirectCtlBoard[aP0-49].UserCodeList[aP1-1]; + aType = dgTYPE_DIRECT_CTL_CHANNEL; + if(LanguageEnCn==0)TMyString::sAddOnStr(" 未知位置", Text); + else TMyString::sAddOnStr(" Unknown", Text); + TMyString::sAddOn2Dg(aP0 % 100, Text); + TMyString::sAddOnStr(" ", Text); + TMyString::sAddOnStr("XXXXX", Text); + TMyString::sAddOnStr("-", Text); + TMyString::sAddOn3Dg(aP1, Text); + TMyString::sAddOnStr(" ", Text); + if(LanguageEnCn==0)TMyString::sAddOnStr("未知类型", Text); + else TMyString::sAddOnStr(" Unknown", Text); + } + TStaticText::sShow(2, 2, 668, 30, clRed, clFrmFace, Text); + }else + if(FirstFireShowDescpInteval == 4){ + if(LanguageEnCn==0)TMyString::sFromStr("首警:", Text); + else TMyString::sFromStr("First", Text); + FirstFireFillDescp(); + TStaticText::sShow(2, 2, 668, 30, clRed, clFrmFace, DescpText.Text); + }else + if(FirstFireShowDescpInteval >6){ + FirstFireShowDescpInteval = 0; + } + }else{ + if(FirstFireHadDraw){ + FirstFireHadDraw =0; + FirstFireShowDescpInteval = 0; + TStaticText::sDrawDump(2, 2, 668, 30, clFrmFace); + } + } +} + +void TEventShow::DrawListAll(void) +{ + int i, aLen; + int aInx, aCnt; + unsigned int tClr, bClr, Wrote, HadRead; + + this->IsShowing = 1; + Wrote = 0; + + if(WhatSelected <0)return; + if(WhatSelected >4)return; + + if(OutLineType != 0){ + + } + CalcSelectedIndex(WhatSelected); + + aCnt = MsgList[WhatSelected].Count; + aInx = MsgList[WhatSelected].TopIndex; + MsgList[WhatSelected].BlankLine = 10 - (aCnt - aInx) + 1; + if(MsgList[WhatSelected].BlankLine < 0)MsgList[WhatSelected].BlankLine = 0; + MsgList[WhatSelected].ShowRemainCnt = aCnt - aInx - 10; + for(i=0;i<5;i++){ + if(aCnt < 1)break; + if(aInx < 0)break; + HadRead = MsgList[WhatSelected].Body[i].Splite.iByte0; + //if(HadRead){ + // tClr = clTextHasRead[WhatSelected]; + // if(MsgList[WhatSelected].SelectedLine == i){ + // tClr = clNearWhite; + // bClr = clSelectedRead; + // }else{ + // bClr = clReadOk; + // } + //}else{ + tClr = clTextUnRead[WhatSelected]; + if(MsgList[WhatSelected].SelectedLine == i){ + tClr = clNearWhite; + bClr = clSelectedUnRead; + }else{ + bClr = clUnRead[WhatSelected]; + } + //} + if(MsgList[WhatSelected].Body[i].Splite.State != 0){ + if(LanguageEnCn==0) FillText (WhatSelected, MsgList[WhatSelected].TopIndex - i, i); + else FillTextEn (WhatSelected, MsgList[WhatSelected].TopIndex - i, i); + //TStaticText::sShow(5, stAllTop[i], 775, 406, clWhite, clRed, Text); + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stAllTop[i*2], tClr, bClr, Text); + RectFillRender(MsgX0, stAllTop[i*2] + 24, MsgX0 + 743, stAllTop[i*2 +1], bClr); + if(NeedShowDescp){ + TMyString::sFillFixLen(TextDescp, dLineMaxLen); + TextRender_string24(MsgX0, stAllTop[i*2 +1], tClr, bClr, TextDescp); + }else{ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stAllTop[i*2 +1], clWhite, bClr, Text); + } + }else{ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stAllTop[i*2], clWhite, bClr, Text); + RectFillRender(MsgX0, stAllTop[i*2] + 24, MsgX0 + 743, stAllTop[i*2 +1], bClr); + TextRender_string24(MsgX0, stAllTop[i*2 +1], clWhite, bClr, Text); + } + if(HadRead){ + ReadIdfDrawBySize(736, stAllTop[i*2 +1], 20, 20, 4, clDeepGreen, 1); + } + aInx--; + Wrote++; + } + for(i=Wrote; i<5; i++){ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stAllTop[i*2], clWhite, ColorBg, Text); + RectFillRender(MsgX0, stAllTop[i*2] + 24, MsgX0 + 743, stAllTop[i*2 +1], ColorBg); + TextRender_string24(MsgX0, stAllTop[i*2 +1], clWhite, ColorBg, Text); + } + MsgList[WhatSelected].TailRemain = 5 - Wrote; + aInx = MsgList[WhatSelected].Count - MsgList[WhatSelected].TopIndex -1; + + if(aInx <0)aInx = 0; + TVScrollBar::sDrawByPoint(stScrollBarX0, stAllTop[0], stScrollBarX0+19, stAllTop[9]+24, clBlue , clGray , aCnt, 5, aInx); +} + +void TEventShow::DrawFig() +{ + /*unsigned int w0Clr, w1Clr; + if(WhatSelected < 2){ + if(WhatSelected == 0){ + w0Clr = clBlue; + w1Clr = clTeal; + }else{ + w0Clr = clTeal; + w1Clr = clBlue; + } + + RectFillRender(Content.Left +1, Content.Top, Content.Left +4, Content.Top + 190, w0Clr); + RectFillRender(Content.Left +1, Content.Top, Content.Right -1, Content.Top +2, w0Clr); + RectFillRender(Content.Right -4, Content.Top, Content.Right-2, Content.Top + 190, w0Clr); + RectFillRender(Content.Left +1, Content.Top + 190-4, Content.Right -2, Content.Top + 190, w0Clr); + + RectFillRender(Content.Left +1, Content.Top +198, Content.Left +4, Content.Bottom -1, w1Clr); + RectFillRender(Content.Left +1, Content.Top +198, Content.Right -1, Content.Top +198 +3, w1Clr); + RectFillRender(Content.Right -4, Content.Top +198, Content.Right-1, Content.Bottom-1, w1Clr); + RectFillRender(Content.Left +1, Content.Bottom -4, Content.Right -1, Content.Bottom-1, w1Clr); + }else{ + + RectFillRender(Content.Left +1, Content.Top, Content.Left +2 +2, Content.Bottom -1, clBlue); + RectFillRender(Content.Left +1, Content.Top, Content.Right -1, Content.Top +2, clBlue); + RectFillRender(Content.Right -4, Content.Top, Content.Right-1, Content.Bottom -1, clBlue); + RectFillRender(Content.Left +1, Content.Bottom -4, Content.Right -1, Content.Bottom -1, clBlue); + }*/ +} + +void TEventShow::DrawListHeader(void) +{ + int i,x, aLen; + int aInx; + unsigned int tClr; + short aCnt; + int aW = 122; + + //RectFillRender(10, TitleUp -4, 780, TitleUp + 34, Color); + if(LanguageEnCn==0){ + for(i=0; i<6; i++)CapString[i] = CapStringCn[i]; + for(i=0; i<4; i++)CapStringDown[i]=CapStringDownCn[i]; + }else{ + for(i=0; i<6; i++)CapString[i] = CapStringEn[i]; + for(i=0; i<4; i++)CapStringDown[i]=CapStringDownEn[i]; + } + + if(WhatSelected < 2){ + //Show Up And Low. + x = 2; + RectFillRender(RectTitleTop.Left, RectTitleTop.Top, RectTitleTop.Right, RectTitleTop.Bottom, ColorTitle); + if(WhatSelected == 1) + RectFillRender(x + 130 * 0, RectTitleTop.Top, x + 130 * 0 + 130, RectTitleTop.Bottom, ColorTitleFireNotOnSelected); + else + RectFillRender(x + 130 * 0, RectTitleTop.Top, x + 130 * 0 + 130, RectTitleTop.Bottom, clDeepBlue); + + x = 4; + for(i=0; i<5; i++){ + aCnt = MsgList[i].NewCount; + tClr = clNearWhite; + TMyString::sFromStr(CapString[i], cText); + TMyString::sAddOn5Dg(aCnt,cText); + TStaticText::sShow(x, TitleUp, x+aW, TitleUp+30, tClr, cText); + x += (aW + 8); + } + //x+=6; + //TMyString::sFromStr(CapString[5], cText); + //TMyString::sAddOn3Dg(GolbalDelayTick,cText); + //TMyString::sAddOnChar('s', cText); + //TextRender_string24(x+4, TitleUp+2, tClr, ContentColor, cText); + //GolbalDelayValueOnShowing = GolbalDelayTick; + }else{ + //Show All + x=2; + RectFillRender(RectTitleTop.Left, RectTitleTop.Top, RectTitleTop.Right, RectTitleTop.Bottom, ColorTitle); + RectFillRender(x + 130 * WhatSelected, RectTitleTop.Top, x + 130 * WhatSelected + 130, RectTitleTop.Bottom, clDeepBlue); + + x =4; + for(i=0; i<2; i++){ + aCnt = MsgList[i].NewCount; + TMyString::sFromStr(CapString[i], cText); + TMyString::sAddOn5Dg(aCnt,cText); + + tClr = clNearWhite; + + TStaticText::sShow(x, TitleUp, x+aW, TitleUp+30, tClr, cText); + x += (aW + 8); + } + + for(i=2; i<5; i++){ + aCnt = MsgList[i].NewCount; + //if(aCnt>0){ + TMyString::sFromStr(CapString[i], cText); + TMyString::sAddOn5Dg(aCnt,cText); + tClr = clNearWhite; + TStaticText::sShow(x, TitleUp, x+aW, TitleUp+30, tClr, cText); + x += (aW + 8); + //} + } + //x+=6; + //TMyString::sFromStr(CapString[5], cText); + //TMyString::sAddOn3Dg(GolbalDelayTick,cText); + //TMyString::sAddOnChar('s', cText); + //TextRender_string24(x+4, TitleUp+2, tClr, ContentColor, cText); + //GolbalDelayValueOnShowing = GolbalDelayTick; + } + + if( WhatSelected < 2){ + //Show Linkage + aW = 122; + if(WhatSelected == 1){ + RectFillRender(RectTitleBtm.Left, RectTitleBtm.Top, RectTitleBtm.Right, RectTitleBtm.Bottom, clDeepBlue); + }else{ + RectFillRender(RectTitleBtm.Left, RectTitleBtm.Top, RectTitleBtm.Right, RectTitleBtm.Bottom, ColorTitle); + } + x = 10; + aCnt = MsgList[1].StartCount; + TMyString::sFromStr(CapStringDown[0], cText); + TMyString::sAddOn5Dg(aCnt,cText); + TMyString::sAddOnStr(" ",cText); + TMyString::sAddOnStr(CapStringDown[1], cText); + aCnt = MsgList[1].FbCount; + TMyString::sAddOn5Dg(aCnt,cText); + TMyString::sAddOnStr(" ",cText); + TMyString::sAddOnStr(CapStringDown[2], cText); + aCnt = MsgList[1].DelayCount; + TMyString::sAddOn5Dg(aCnt,cText); + TMyString::sAddOnStr(" ",cText); + TMyString::sAddOnStr(CapStringDown[3], cText); + aCnt = MsgList[1].StopCount; + TMyString::sAddOn5Dg(aCnt,cText); + + + tClr = clNearWhite; + + TStaticText::sShow(x, TitleDown, x+572, TitleDown+30, tClr, cText); + + } +} + +void TEventShow::DrawListUp(void) +{ + int i, aLen; + int aInx, aCnt; + int aList; + unsigned int bClr, Wrote, HadRead; + + this->IsShowing = 1; + Wrote = 0; + + aList = 0; + + CalcSelectedIndex(0); + + aCnt = MsgList[aList].Count; + aInx = MsgList[aList].TopIndex; + MsgList[aList].BlankLine = 4 - (aCnt - aInx) + 1; + if(MsgList[aList].BlankLine < 0)MsgList[aList].BlankLine = 0; + MsgList[aList].ShowRemainCnt = aCnt - aInx - 4; + for(i=0;i<2;i++){ + if(aInx < 0)break; + if(aCnt < 1)break; + + if( (aInx ==0) && (aCnt == 0)) break; + HadRead = MsgList[0].Body[i].Splite.iByte0; + //if(HadRead){ + // if( (WhatSelected == 0) && (MsgList[0].SelectedLine == i) ) bClr = clSelectedRead; + // else bClr = clReadOk; + //}else{ + if( (WhatSelected == 0) && (MsgList[0].SelectedLine == i) ) bClr = clSelectedUnRead; + else bClr = clUnRead[aList]; + //} + if(MsgList[aList].Body[i].Splite.State != 0){ + if(LanguageEnCn==0) FillText (aList, MsgList[aList].TopIndex - i, i); + else FillTextEn (aList, MsgList[aList].TopIndex - i, i); + //TStaticText::sShow(5, stAllTop[i], 775, 406, clWhite, clRed, Text); + TMyString::sFillFixLen(Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stUpTop[i*2], clWhite, bClr, Text); + RectFillRender(MsgX0, stUpTop[i*2] + 24, MsgX0 + 743, stUpTop[i*2 +1], bClr); + if(NeedShowDescp){ + TMyString::sFillFixLen(TextDescp, dLineMaxLen); + TextRender_string24(MsgX0, stUpTop[i*2 +1], clWhite, bClr, TextDescp); + }else{ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stUpTop[i*2 +1], clWhite, bClr, Text); + } + }else{ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stUpTop[i*2], clWhite, bClr, Text); + TextRender_string24(MsgX0, stUpTop[i*2 +1], clWhite, bClr, Text); + } + if(HadRead){ + ReadIdfDrawBySize(736, stUpTop[i*2 +1], 20, 20, 4, clDeepGreen, 1); + } + aInx--; + Wrote++; + } + for(i=Wrote; i<2; i++){ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stUpTop[i*2], clWhite, ColorBg, Text); + RectFillRender(MsgX0, stUpTop[i*2] + 24, MsgX0 + 743, stUpTop[i*2 +1], ColorBg); + TextRender_string24(MsgX0, stUpTop[i*2 +1], clWhite, ColorBg, Text); + } + MsgList[aList].TailRemain = 2 - Wrote; + aInx = MsgList[aList].TopIndex; + if(WhatSelected == 0)bClr = clBlue; else bClr = clTeal; + + aInx = MsgList[0].Count - MsgList[0].TopIndex -1; + if(aInx <0)aInx = 0; + TVScrollBar::sDrawByPoint(stScrollBarX0, stUpTop[0], stScrollBarX0+20, stUpTop[3] + 24, bClr , clGray , aCnt, 2, aInx); +} + +void TEventShow::DrawListDown(void) +{ + int i, aLen; + int aInx, aCnt; + unsigned int bClr, Wrote, aTinx, HadRead; + + this->IsShowing = 1; + Wrote = 0; + + CalcSelectedIndex(1); + + aCnt = MsgList[1].Count; + aInx = MsgList[1].TopIndex; + MsgList[1].BlankLine = 4 - (aCnt - aInx) + 1; + if(MsgList[1].BlankLine < 0)MsgList[1].BlankLine = 0; + MsgList[1].ShowRemainCnt = aCnt - aInx - 4; + for(i=0;i<2;i++){ + if(aInx < 0)break; + if( (aInx ==0) && (aCnt == 0)) break; + HadRead = MsgList[1].Body[i].Splite.iByte0; + if(HadRead){ + if( (WhatSelected == 1) && (MsgList[1].SelectedLine == i) ) bClr = clSelectedRead; + else bClr = clReadOk; + }else{ + if( (WhatSelected == 1) && (MsgList[1].SelectedLine == i) ) bClr = clSelectedUnRead; + else bClr = clUnRead[1]; + } + if(MsgList[1].Body[i].Splite.State != 0){ + if(LanguageEnCn==0) FillText (1, MsgList[1].TopIndex - i, i); + else FillTextEn (1, MsgList[1].TopIndex - i, i); + //TStaticText::sShow(5, stAllTop[i], 775, 406, clWhite, clRed, Text); + TMyString::sFillFixLen(Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stDownTop[i*2], clWhite, bClr, Text); + RectFillRender(MsgX0, stDownTop[i*2] + 24, MsgX0 + 743, stDownTop[i*2 +1], bClr); + if(NeedShowDescp){ + TMyString::sFillFixLen(TextDescp, dLineMaxLen); + TextRender_string24(MsgX0, stDownTop[i*2 +1], clWhite, bClr, TextDescp); + }else{ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stDownTop[i*2 +1], clWhite, bClr, Text); + } + LinkDelayLineBClr[i] = bClr; + }else{ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stDownTop[i*2], clWhite, bClr, Text); + TextRender_string24(MsgX0, stDownTop[i*2 +1], clWhite, bClr, Text); + } + aInx--; + Wrote++; + LinkDelayLineBClr[i] = bClr; + } + for(i=Wrote; i<2; i++){ + Text[0] = ' '; + Text[1] = 0; + TMyString::sFillFixLen(Text, dLineMaxLen); + TextRender_string24(MsgX0, stDownTop[i*2], clWhite, ColorBg, Text); + RectFillRender(MsgX0, stDownTop[i*2] + 24, MsgX0 + 743, stDownTop[i*2 +1], ColorBg); + TextRender_string24(MsgX0, stDownTop[i*2 +1], clWhite, ColorBg, Text); + LinkDelayLineBClr[i] = ColorBg; + } + MsgList[1].TailRemain = 2 - Wrote; + aInx = MsgList[1].TopIndex; + if(WhatSelected == 1)bClr = clBlue; else bClr = clTeal; + + aInx = MsgList[1].Count - MsgList[1].TopIndex -1; + if(aInx <0)aInx = 0; + TVScrollBar::sDrawByPoint(stScrollBarX0, stDownTop[0], stScrollBarX0+20, stDownTop[3]+24, bClr , clGray , aCnt, 2, aInx); +} + +void TEventShow::DrawList(void) +{ + unsigned int w0Clr, w1Clr; + this->IsShowing = 1; + if(WhatSelected < 2){ + if(WhatSelected == 0){ + w0Clr = clBlue; + w1Clr = clTeal; + }else{ + w0Clr = clTeal; + w1Clr = clBlue; + } + if(LastDrawSplite != 2){ + //RectFillRender(Content.Left , Content.Top, Content.Right , Content.Bottom, Color); + RectFillRender(0, stUpTop[0], 799, stUpTop[3]+24+1, ColorBg); + RectFillRender(0, stUpTop[3]+24+2, 799, stDownTop[0]-1, clNearBlack); + RectFillRender(0, stDownTop[0], 799, stDownTop[3]+24+1, ColorBg); + } + DrawFig(); + DrawListHeader(); + DrawListUp(); + DrawListDown(); + LastDrawSplite =2; + }else{ + if(LastDrawSplite != 1){ + //RectFillRender(Content.Left , Content.Top, Content.Right , Content.Bottom, Color); + //RectFillRender(RectTitleBtm.Left, RectTitleBtm.Top, RectTitleBtm.Right, RectTitleBtm.Bottom, clNearBlack); + RectFillRender(0, stAllTop[0], 799, stAllTop[9]+24+1, ColorBg); + } + DrawFig(); + DrawListHeader(); + DrawListAll(); + LastDrawSplite = 1; + } +} + +void TEventShow::DrawListFullRedraw(void) +{ + +} + +int TEventShow::TryGetFireData(int GetListMode, int aInx) +{ + int i, x, aTinx, LoadingIndex; + int aCount, aLen, aLineCnt; + int aToGetList = 0; + int ReadSuccess = 0; + int Result = 0; + int TryTimes = 0; + + do{ + TryTimes++; + if(TryTimes > 1000)break; + aLineCnt = 4; + if( (MsgList[0].RefrashIndex != CtlCenter.ieMsgFire.ReflashIndex) || GetListMode ){ + if(CtlCenter.ieMsgFire.Lock == 1){ + continue; + } + CtlCenter.ieMsgFire.RequestRead = 1; + LoadingIndex = CtlCenter.ieMsgFire.ReflashIndex; + aCount = CtlCenter.ieMsgFire.Count; + if(GetListMode == 2) aToGetList = 1; + else if( (GetListMode == 1) && (MsgList[0].RefrashIndex != LoadingIndex) ) aToGetList = 1; + if(aToGetList){ + if(aInx < ieMSG_FIRE_MAX_COUNT){ + aTinx = aInx; + if(aTinx >= aCount) + aTinx = aCount - 1; + }else{ + aTinx = aCount - 1; + } + x = 0; + i = aTinx; + for(; i>-1; i--){ + if(x >= aLineCnt)break; + CtlCenter.FireMsgExtGet(i); + MsgBuf[x].D32[0] = CtlCenter.MsgExtGet.D32[0]; + MsgBuf[x].D32[1] = CtlCenter.MsgExtGet.D32[1]; + MsgBuf[x].D32[2] = CtlCenter.MsgExtGet.D32[2]; + MsgBuf[x].D32[3] = CtlCenter.MsgExtGet.D32[3]; + MsgBuf[x].D32[4] = CtlCenter.MsgExtGet.D32[4]; + x++; + } + aLen = x; + } + if(CtlCenter.ieMsgFire.RequestRead == 0){ + continue; + }else{ + MsgList[0].NewCount = aCount; + if(aToGetList){ + MsgList[0].Count = aCount; + for(i=0; i 1000)break; + + aLineCnt = 4; + if( (MsgList[1].RefrashIndex != CtlCenter.ieMsgLinkage.ReflashIndex) || GetListMode ){ + if(CtlCenter.ieMsgLinkage.Lock == 1){ + continue; + } + CtlCenter.ieMsgLinkage.RequestRead = 1; + LoadingIndex = CtlCenter.ieMsgLinkage.ReflashIndex; + aCount = CtlCenter.ieMsgLinkage.Count; + aStartCount = CtlCenter.ieMsgLinkage.StartCount; + aFbCount = CtlCenter.ieMsgLinkage.FbCount; + if(GetListMode == 2) aToGetList = 1; + else if( (GetListMode == 1) && (MsgList[1].RefrashIndex != LoadingIndex) ) aToGetList = 1; + if(aToGetList){ + if(aInx < ieMSG_LINKAGE_MAX_COUNT){ + aTinx = aInx; + if(aTinx >= aCount) + aTinx = aCount - 1; + }else{ + aTinx = aCount - 1; + } + x = 0; + i = aTinx; + for(; i>-1; i--){ + if(x >= aLineCnt)break; + CtlCenter.LinkageMsgExtGet(i); + MsgBuf[x].D32[0] = CtlCenter.MsgExtGet.D32[0]; + MsgBuf[x].D32[1] = CtlCenter.MsgExtGet.D32[1]; + MsgBuf[x].D32[2] = CtlCenter.MsgExtGet.D32[2]; + MsgBuf[x].D32[3] = CtlCenter.MsgExtGet.D32[3]; + MsgBuf[x].D32[4] = CtlCenter.MsgExtGet.D32[4]; + x++; + } + aLen = x; + } + if(CtlCenter.ieMsgLinkage.RequestRead == 0){ + continue; + }else{ + MsgList[1].NewCount = aCount; + MsgList[1].StartCount = aStartCount; + MsgList[1].FbCount = aFbCount; + MsgList[1].FbCount = aFbCount; + MsgList[1].DelayCount = CtlCenter.ieMsgLinkage.DelayCount; + MsgList[1].StopCount = CtlCenter.ieMsgLinkage.StopCount; + if(aToGetList){ + MsgList[1].Count = aCount; + for(i=0; i 1000)break; + aLineCnt = 10; + if( (MsgList[2].RefrashIndex != CtlCenter.ieMsgSv.ReflashIndex) || GetListMode ){ + if(CtlCenter.ieMsgSv.Lock == 1){ + continue; + } + CtlCenter.ieMsgSv.RequestRead = 1; + LoadingIndex = CtlCenter.ieMsgSv.ReflashIndex; + aCount = CtlCenter.ieMsgSv.Count; + if(GetListMode == 2) aToGetList = 1; + else if( (GetListMode == 1) && (MsgList[2].RefrashIndex != LoadingIndex) ) aToGetList = 1; + if(aToGetList){ + if(aInx < ieMSG_SV_MAX_COUNT){ + aTinx = aInx; + if(aTinx >= aCount) + aTinx = aCount - 1; + }else{ + aTinx = aCount - 1; + } + x = 0; + i = aTinx; + for(; i>-1; i--){ + if(x >= aLineCnt)break; + CtlCenter.SvMsgExtGet(i); + MsgBuf[x].D32[0] = CtlCenter.MsgExtGet.D32[0]; + MsgBuf[x].D32[1] = CtlCenter.MsgExtGet.D32[1]; + MsgBuf[x].D32[2] = CtlCenter.MsgExtGet.D32[2]; + MsgBuf[x].D32[3] = CtlCenter.MsgExtGet.D32[3]; + MsgBuf[x].D32[4] = CtlCenter.MsgExtGet.D32[4]; + x++; + } + aLen = x; + } + if(CtlCenter.ieMsgSv.RequestRead == 0){ + continue; + }else{ + MsgList[2].NewCount = aCount; + if(aToGetList){ + MsgList[2].Count = aCount; + for(i=0; i 1000)break; + aLineCnt = 10; + if( (MsgList[3].RefrashIndex != CtlCenter.ieMsgFault.ReflashIndex) || GetListMode ){ + if(CtlCenter.ieMsgFault.Lock == 1){ + continue; + } + CtlCenter.ieMsgFault.RequestRead = 1; + LoadingIndex = CtlCenter.ieMsgFault.ReflashIndex; + aCount = CtlCenter.ieMsgFault.Count; + if(GetListMode == 2) aToGetList = 1; + else if( (GetListMode == 1) && (MsgList[3].RefrashIndex != LoadingIndex) ) aToGetList = 1; + if(aToGetList){ + if(aInx < ieMSG_FAULT_MAX_COUNT){ + aTinx = aInx; + if(aTinx >= aCount) + aTinx = aCount - 1; + }else{ + aTinx = aCount - 1; + } + x = 0; + i = aTinx; + for(; i>-1; i--){ + if(x >= aLineCnt)break; + CtlCenter.FaultMsgExtGet(i); + MsgBuf[x].D32[0] = CtlCenter.MsgExtGet.D32[0]; + MsgBuf[x].D32[1] = CtlCenter.MsgExtGet.D32[1]; + MsgBuf[x].D32[2] = CtlCenter.MsgExtGet.D32[2]; + MsgBuf[x].D32[3] = CtlCenter.MsgExtGet.D32[3]; + MsgBuf[x].D32[4] = CtlCenter.MsgExtGet.D32[4]; + x++; + } + aLen = x; + } + if(CtlCenter.ieMsgFault.RequestRead == 0){ + continue; + }else{ + MsgList[3].NewCount = aCount; + if(aToGetList){ + MsgList[3].Count = aCount; + for(i=0; i= aCount) + aTinx = aCount - 1; + }else{ + aTinx = aCount - 1; + } + x = 0; + i = aTinx; + for(; i>-1; i--){ + if(x >= aLineCnt)break; + sAddr = dAddrSdRam_MsgMask + i *24; + MsgBuf[x].D32[0] = *(volatile unsigned int *)(sAddr + 0); + MsgBuf[x].D32[1] = *(volatile unsigned int *)(sAddr + 4); + MsgBuf[x].D32[2] = *(volatile unsigned int *)(sAddr + 8); + MsgBuf[x].D32[3] = *(volatile unsigned int *)(sAddr + 12); + MsgBuf[x].D32[4] = *(volatile unsigned int *)(sAddr + 16); + x++; + } + aLen = x; + } + if(CtlCenter.ieMsgMask.RequestRead == 0){ + return 0; + }else{ + MsgList[4].NewCount = aCount; + if(aToGetList){ + MsgList[4].Count = aCount; + for(i=0; iIsShowing == 0){ + if(MsgList[0].Count > 0){ + WhatSelected = 0; + aForceShow = 1; + ToDraw = 1; + }else + if(MsgList[1].Count > 0){ + WhatSelected = 1; + aForceShow = 1; + ToDraw = 1; + }else + if(MsgList[2].Count > 0){ + WhatSelected = 2; + aForceShow = 1; + ToDraw = 1; + }else + if(MsgList[3].Count > 0){ + WhatSelected = 3; + aForceShow = 1; + ToDraw = 1; + }else + if(MsgList[4].Count > 0){ + WhatSelected = 4; + aForceShow = 1; + ToDraw = 1; + } + + if( (ToDraw) && (IsShowTipPopup == 0) ){ + MainMenu.Hide(); + if(aForceShow){ + if(this->IsShowing){ + DrawList(); + }else{ + this->IsShowing = 1; + Show(); + DrawList(); + } + }else{ + if(this->IsShowing){ + DrawList(); + } + } + return 1; + }else{ + return 0; + } + }else{ + if(AutoRollTick > 9){ + AutoRollTick = 0; + if(MsgList[0].Count > 0){ + WhatSelected = 0; + ToDraw = 1; + }else + if(MsgList[1].Count > 0){ + WhatSelected = 1; + ToDraw = 1; + }else + if(MsgList[2].Count > 0){ + WhatSelected = 2; + ToDraw = 1; + }else + if(MsgList[3].Count > 0){ + WhatSelected = 3; + ToDraw = 1; + }else + if(MsgList[4].Count > 0){ + WhatSelected = 4; + ToDraw = 1; + } + if( (ToDraw) && (IsShowTipPopup == 0) ){ + AutoRollShow(); + return 1; + }else{ + return 0; + } + } + return 1; + } +} + +int TEventShow::DoNoOperate() +{ + int i,aState; + int EventUpdata = 0; + unsigned int aUpdata =0; + unsigned int LoadUpdata = 0; + unsigned int aForceShow = 0; + unsigned int ReArray = 0; + unsigned int aWhatFound = 0; + unsigned int ToDraw = 0; + unsigned int ToDrawHead = 0; + int NoEvent = 1; + + //try to Load New Event Load + //Switch to Show Fire + + NoOpaUd[0] = TryGetFireData(0,0); + NoOpaUd[1] = TryGetLinkageData(0,0); + NoOpaUd[2] = TryGetSvData(0,0); + NoOpaUd[3] = TryGetFaultData(0,0); + NoOpaUd[4] = TryGetMaskData(0,0); + + if(NoOpaUd[0] == 2){ + TryGetFireData(2,202404017); + } + if(NoOpaUd[1] == 2){ + TryGetLinkageData(2,202404017); + } + if(NoOpaUd[2] == 2){ + TryGetSvData(2,202404017); + } + if(NoOpaUd[3] == 2){ + TryGetFaultData(2,202404017); + } + if(NoOpaUd[4] == 2){ + TryGetMaskData(2,202404017); + } + + if(WhatSelected == 0){ + if(NoOpaUd[0] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[1] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[2] == 2){ + ToDrawHead = 1; + }else + if(NoOpaUd[3] == 2){ + ToDrawHead = 1; + }else + if(NoOpaUd[4] == 2){ + ToDrawHead = 1; + } + if(ToDraw || ToDrawHead){ + if(MsgList[0].Count > 0){ + + }else + if(MsgList[1].Count >0){ + WhatSelected = 1; + }else + if(MsgList[2].Count >0){ + WhatSelected = 2; + ToDraw = 1; + }else + if(MsgList[3].Count >0){ + WhatSelected = 3; + ToDraw = 1; + }else + if(MsgList[4].Count >0){ + WhatSelected = 4; + ToDraw = 1; + } + } + }else + if(WhatSelected == 1){ + if(NoOpaUd[0] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[1] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[2] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[3] == 2){ + ToDrawHead = 1; + }else + if(NoOpaUd[4] == 2){ + ToDrawHead = 1; + } + if(ToDraw || ToDrawHead){ + if(MsgList[0].Count >0){ + WhatSelected = 0; + ToDraw = 1; + }else + if(MsgList[1].Count >0){ + WhatSelected = 1; + ToDraw = 1; + }else + if(MsgList[2].Count >0){ + WhatSelected = 2; + ToDraw = 1; + }else + if(MsgList[3].Count >0){ + WhatSelected = 3; + ToDraw = 1; + }else + if(MsgList[4].Count >0){ + WhatSelected = 4; + ToDraw = 1; + } + } + }else + if(WhatSelected == 2){ + if(NoOpaUd[0] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[1] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[2] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[3] == 2){ + ToDrawHead = 1; + }else + if(NoOpaUd[4] == 2){ + ToDrawHead = 1; + } + if(ToDraw || ToDrawHead){ + if(MsgList[0].Count >0){ + WhatSelected = 0; + ToDraw = 1; + }else + if(MsgList[1].Count >0){ + WhatSelected = 1; + ToDraw = 1; + }else + if(MsgList[2].Count >0){ + WhatSelected = 2; + ToDraw = 1; + }else + if(MsgList[3].Count >0){ + WhatSelected = 3; + ToDraw = 1; + }else + if(MsgList[4].Count >0){ + WhatSelected = 4; + ToDraw = 1; + } + } + }else + if(WhatSelected == 3){ + if(NoOpaUd[0] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[1] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[2] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[3] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[4] == 2){ + ToDrawHead = 1; + } + if(ToDraw || ToDrawHead){ + if(MsgList[0].Count >0){ + WhatSelected = 0; + ToDraw = 1; + }else + if(MsgList[1].Count >0){ + WhatSelected = 1; + ToDraw = 1; + }else + if(MsgList[2].Count >0){ + WhatSelected = 2; + ToDraw = 1; + }else + if(MsgList[3].Count >0){ + WhatSelected = 3; + ToDraw = 1; + }else + if(MsgList[4].Count >0){ + WhatSelected = 4; + ToDraw = 1; + } + } + }else + if(WhatSelected == 4){ + if(NoOpaUd[0] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[1] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[2] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[3] == 2){ + ToDraw = 1; + }else + if(NoOpaUd[4] == 2){ + ToDraw = 1; + } + if(ToDraw || ToDrawHead){ + if(MsgList[0].Count >0){ + WhatSelected = 0; + ToDraw = 1; + }else + if(MsgList[1].Count >0){ + WhatSelected = 1; + ToDraw = 1; + }else + if(MsgList[2].Count >0){ + WhatSelected = 2; + ToDraw = 1; + }else + if(MsgList[3].Count >0){ + WhatSelected = 3; + ToDraw = 1; + }else + if(MsgList[4].Count >0){ + WhatSelected = 4; + ToDraw = 1; + } + } + } + + if(ToDraw){ + if(this->IsShowing == 0){ + this->IsShowing = 1; + TipPopup.Hide(); + TipPopup.ClearTickOnEventOcc(); + MainMenu.Hide(); + MakeShow(); + }else{ + DrawList(); + } + GeneralDev.LcdBlackLightSetOn(); + }else{ + if(ToDrawHead){ + if(this->IsShowing == 0){ + this->IsShowing = 1; + TipPopup.Hide(); + TipPopup.ClearTickOnEventOcc(); + MainMenu.Hide(); + MakeShow(); + }else{ + DrawListHeader(); + } + GeneralDev.LcdBlackLightSetOn(); + } + } + + if( (MsgList[0].Count == 0) && + (MsgList[1].Count == 0) && + (MsgList[2].Count == 0) && + (MsgList[3].Count == 0) && + (MsgList[4].Count == 0) ){ + IsShouldReturn = 1; + return 0; + } + return 1; +} + +int TEventShow::DoOperate() +{ + int i; + int GoSerach = 1; + int ToDraw = 0; + int ToDrawHeader = 0; + int GotFire; + int GotLinkage; + int GotSv; + int GotFault; + int GotMask; + + GotFire = TryGetFireData(0,0); + GotLinkage = TryGetLinkageData(0,0); + GotSv = TryGetSvData(0,0); + if(IsDulAddrChecking)GotFault =0; + else GotFault = TryGetFaultData(0,0); + GotMask = TryGetMaskData(0,0); + + if(GotFire == 2)TryGetFireData(2,20240417); + if(GotLinkage == 2)TryGetLinkageData(2,20240417); + if(GotSv ==2)TryGetSvData(2,20240417); + if(GotFault == 2)TryGetFaultData(2,20240417); + if(GotMask == 2)TryGetMaskData(2,20240417); + + if(this->IsShowing){ + if(WhatSelected == 0){ + if(GotFire == 2){ + ToDraw = 1; + if(MsgList[0].Count == 0){ + if(MsgList[1].Count>0)WhatSelected = 1; + else if(MsgList[2].Count>0)WhatSelected = 2; + else if(MsgList[3].Count>0)WhatSelected = 3; + else if(MsgList[4].Count>0)WhatSelected = 4; + } + } + if(GotLinkage == 2){ + ToDraw = 1; + } + }else + if(WhatSelected == 1){ + if(GotFire == 2){ + ToDraw = 1; + if(MsgList[0].Count > 0)WhatSelected = 0; + } + if(GotLinkage == 2){ + if(MsgList[1].Count == 0){ + if(MsgList[0].Count > 0)WhatSelected = 0; + else if(MsgList[2].Count>0)WhatSelected = 2; + else if(MsgList[3].Count>0)WhatSelected = 3; + else if(MsgList[4].Count>0)WhatSelected = 4; + } + ToDraw = 1; + } + }else + if(WhatSelected == 2){ + if(GotFire == 2){ + ToDraw = 1; + WhatSelected = 0; + }else + if(GotLinkage == 2){ + ToDraw = 1; + WhatSelected = 1; + } + if(GotSv == 2){ + if(MsgList[2].Count == 0){ + if(MsgList[0].Count > 0)WhatSelected = 0; + else if(MsgList[1].Count > 0)WhatSelected = 1; + else if(MsgList[3].Count > 0)WhatSelected = 3; + else if(MsgList[4].Count > 0)WhatSelected = 4; + } + ToDraw = 1; + } + }else + if(WhatSelected == 3){ + if(GotFire == 2){ + ToDraw = 1; + if(MsgList[0].Count > 0)WhatSelected = 0; + }else + if(GotLinkage == 2){ + ToDraw = 1; + if(MsgList[1].Count > 0)WhatSelected = 1; + }else + if(GotSv == 2){ + ToDraw = 1; + WhatSelected = 2; + } + if(GotFault == 2){ + if(MsgList[3].Count == 0){ + if(MsgList[0].Count > 0)WhatSelected = 0; + else if(MsgList[1].Count > 0)WhatSelected = 1; + else if(MsgList[2].Count > 0)WhatSelected = 2; + else if(MsgList[4].Count > 0)WhatSelected = 4; + } + ToDraw = 1; + } + }else{ + if(GotFire == 2){ + ToDraw = 1; + if(MsgList[0].Count > 0)WhatSelected = 0; + }else + if(GotLinkage == 2){ + ToDraw = 1; + if(MsgList[1].Count > 0)WhatSelected = 1; + }else + if(GotSv == 2){ + ToDraw = 1; + if(MsgList[2].Count > 0)WhatSelected = 2; + }else + if(GotFault == 2){ + ToDraw = 1; + if(MsgList[3].Count > 0)WhatSelected = 3; + }else + if(GotMask == 2){ + ToDraw = 1; + if(MsgList[4].Count == 0){ + WhatSelected = 4; + if(MsgList[0].Count > 0)WhatSelected = 0; + else if(MsgList[1].Count>0)WhatSelected = 1; + else if(MsgList[2].Count>0)WhatSelected = 2; + else if(MsgList[3].Count>0)WhatSelected = 3; + } + } + } + + + if(ToDraw){ + DrawList(); + GeneralDev.LcdBlackLightSetOn(); + return 1; + }else{ + if( (GotFire == 2) || (GotLinkage == 2) || (GotSv == 2) || (GotFault == 2) || (GotMask == 2)){ + DrawListHeader(); + GeneralDev.LcdBlackLightSetOn(); + return 1; + } + } + }else{ + if(GotFire == 2){ + if(MsgList[0].Count>0){ + WhatSelected = 0; + TryGetFireData(2,20240417); + TipPopup.Hide(); + TipPopup.ClearTickOnEventOcc(); + MainMenu.Hide(); + MakeShow(); + GeneralDev.LcdBlackLightSetOn(); + return 1; + } + } + if(GotLinkage == 2){ + if(DevStartStop.IsShow == 0){ + if(MsgList[1].Count>0){ + WhatSelected = 1; + TryGetLinkageData(2,20240417); + MainMenu.Hide(); + TipPopup.Hide(); + TipPopup.ClearTickOnEventOcc(); + MakeShow(); + GeneralDev.LcdBlackLightSetOn(); + return 1; + } + } + } + if(GotSv == 2){ + if(MsgList[2].Count>0){ + WhatSelected = 2; + TryGetSvData(2,20240417); + TipPopup.Hide(); + TipPopup.ClearTickOnEventOcc(); + MainMenu.Hide(); + MakeShow(); + GeneralDev.LcdBlackLightSetOn(); + return 1; + } + } + if(GotFault == 2){ + if(MsgList[3].Count>0){ + WhatSelected = 3; + TryGetFireData(2,20240417); + TipPopup.Hide(); + TipPopup.ClearTickOnEventOcc(); + MainMenu.Hide(); + MakeShow(); + GeneralDev.LcdBlackLightSetOn(); + return 1; + } + } + if(GotMask == 2){ + if(MsgList[4].Count>0){ + WhatSelected = 4; + TryGetMaskData(2,20240417); + TipPopup.Hide(); + TipPopup.ClearTickOnEventOcc(); + MainMenu.Hide(); + MakeShow(); + GeneralDev.LcdBlackLightSetOn(); + return 1; + } + } + } + + if( (MsgList[0].Count == 0) && (MsgList[1].Count == 0) && (MsgList[2].Count == 0) && + (MsgList[3].Count == 0) && (MsgList[4].Count == 0) ){ + return 0; + } + return 1; +} + +int TEventShow::ManageState(void) +{ + if(NoKeyInTick500mS < 100)NoKeyInTick500mS++; + else NoKeyInTick500mS = 100; + if(NoNewEventTick500mS < 100)NoNewEventTick500mS++; + else NoNewEventTick500mS = 100; + + if(NoKeyInTick500mS > 90){ + //Nobody Operating + if(NoNewEventTick500mS > 90){ + //No New event , auto roll Entry + return DoNoEvent(); + }else{ + return DoNoOperate(); + } + }else{ + return DoOperate(); + } +} + +void TEventShow::MakeShow() +{ + int GotCount = 0; + TryGetFireData(2,20240417); + TryGetLinkageData(2,20240417); + TryGetSvData(2,20240417); + TryGetFaultData(2,20240417); + if (EventShow.MsgList[0].Count != 0) {GotCount =1; WhatSelected = 0;} + else if (EventShow.MsgList[1].Count != 0) {GotCount =1;WhatSelected = 1;} + else if (EventShow.MsgList[2].Count != 0) {GotCount =1;WhatSelected = 2;} + else if (EventShow.MsgList[3].Count != 0) {GotCount =1;WhatSelected = 3;} + else if (EventShow.MsgList[4].Count != 0) {GotCount =1;WhatSelected = 4;} + if(GotCount){ + this->IsShowing = 1; + Show(); + DrawList(); + } +} + +void TEventShow::AutoRollShow() +{ + int Lcnt, aInx; + if(this->IsShowing){ + if(WhatSelected < 2){ + Lcnt = 2; + //Roll And Draw That Fire And Linkage + aInx = MsgList[0].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 20240711; + } + TryGetFireData(2,aInx); + + aInx = MsgList[1].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 20240711; + } + TryGetLinkageData(2,aInx); + DrawList(); + }else + if(WhatSelected == 2){ + Lcnt = 5; + aInx = MsgList[2].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 20240711; + } + TryGetSvData(2,aInx); + DrawList(); + }else + if(WhatSelected == 3){ + Lcnt = 5; + aInx = MsgList[3].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 20240711; + } + TryGetFaultData(2,aInx); + DrawList(); + }else + if(WhatSelected == 4){ + Lcnt = 5; + //aInx = MsgList[4].TopIndex; + //aInx = aInx - Lcnt; + //if(aInx < 0){ + // aInx = 20240711; + //} + if(MsgList[4].TopIndex != (CtlCenter.ieMsgMask.Count -1)){ + TryGetMaskData(2,20240711); + DrawList(); + } + } + } +} + +void TEventShow::ShowCountDownTime() +{ + unsigned char P0, P1; + unsigned int DelaySec,i; + if(WhatSelected <2){ + if(MsgList[1].Count >0){ + if(MsgList[1].DelayCount >0){ + for(i=0; i<2; i++){ + if(MsgList[1].Body[i].Splite.Data0 == 0x0A){ + DelaySec = 0; + if(MsgList[1].Body[i].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if( (MsgList[1].Body[i].Splite.P0 >0) && (MsgList[1].Body[i].Splite.P0 <= 40) ){ + P0 = MsgList[1].Body[i].Splite.P0-1; + P1 = MsgList[1].Body[i].Splite.P1-1; + if( Port[P0].DelayTick[P1] > 2){ + DelaySec = Port[P0].DelayTick[P1] -2; + }else{ + DelaySec = 0; + } + }else + if( (MsgList[1].Body[i].Splite.P0 >= dADDR_DIRECTPAD_START) && (MsgList[1].Body[i].Splite.P0 <= dADDR_DIRECTPAD_END) ){ + P0 = MsgList[1].Body[i].Splite.P0-dADDR_DIRECTPAD_START; + P1 = MsgList[1].Body[i].Splite.P1-1; + if(DirectCtlBoard[P0].DelayTick[P1] > 2){ + DelaySec = DirectCtlBoard[P0].DelayTick[P1] -2; + }else{ + DelaySec = 0; + } + } + + }else{ + if(MsgList[1].Body[i].Splite.PCtlNum <= 16){ + if( (MsgList[1].Body[i].Splite.P0 >0) && (MsgList[1].Body[i].Splite.P0 <= dPORT_MAX_COUNT) ){ + P0 = MsgList[1].Body[i].Splite.P0; + P1 = MsgList[1].Body[i].Splite.P1; + DelaySec = ProtoC2C.GetNwDevDelayCountDown(MsgList[1].Body[i].Splite.PCtlNum,P0,P1); + }else + if( (MsgList[1].Body[i].Splite.P0 >= dADDR_DIRECTPAD_START) && (MsgList[1].Body[i].Splite.P0 <= dADDR_DIRECTPAD_END) ){ + P0 = MsgList[1].Body[i].Splite.P0-dADDR_DIRECTPAD_START+1; + P1 = MsgList[1].Body[i].Splite.P1; + DelaySec = ProtoC2C.GetNwDirectPadDelayStartPoint(MsgList[1].Body[i].Splite.PCtlNum,P0,P1); + } + } + } + Text[0] = '\0'; Text[1] = '\0'; + if(DelaySec > 99){ + TMyString::sFrom3Dg(DelaySec,Text); + TMyString::sAddOnStr("s", Text); + }else + if(DelaySec > 9){ + TMyString::sFromStr(" ", Text); + TMyString::sAddOn2Dg(DelaySec,Text); + TMyString::sAddOnStr("s", Text); + }else{ + TMyString::sFromStr(" ", Text); + TMyString::sAddOn1Dg(DelaySec,Text); + TMyString::sAddOnStr("s", Text); + } + + TextRender_string24(MsgX0 + 694, stDownTop[i*2], clWhite, LinkDelayLineBClr[i], Text); + } + } + } + } + } +} + +void TEventShow::MakeDelay180Sec() +{ + int i, NetworkDone; + unsigned char tP0, tP1; + if(CtlCenter.ieMsgLinkage.DelayCount >0){ + NetworkDone =0; + for(i=0; i0) && (MsgBuf4OneDelay.Splite.P0 <= 40) ){ + tP0 = MsgBuf4OneDelay.Splite.P0-1; + tP1 = MsgBuf4OneDelay.Splite.P1-1; + if( Port[tP0].DelayTick[tP1] > 2){ + if(Port[tP0].DelayTick[tP1] < 182) + Port[tP0].DelayTick[tP1] = 182; + } + }else + if( (MsgBuf4OneDelay.Splite.P0 >= dADDR_DIRECTPAD_START) && (MsgBuf4OneDelay.Splite.P0 <= dADDR_DIRECTPAD_END) ){ + tP0 = MsgBuf4OneDelay.Splite.P0-dADDR_DIRECTPAD_START; + tP1 = MsgBuf4OneDelay.Splite.P1-1; + if(DirectCtlBoard[tP0].DelayTick[tP1] > 2){ + if(DirectCtlBoard[tP0].DelayTick[tP1] < 182) + DirectCtlBoard[tP0].DelayTick[tP1] = 182; + } + } + }else{ + if(NetworkDone == 0){ + //Publish Msg Make Delay 180S + + NetworkDone = 1; + } + } + } + } + } +} + +void TEventShow::Task100Ms(void) +{ + +} + +void TEventShow::ShowTask() +{ + if(Tick1000MsRdy){ + Tick1000MsRdy = 0; + } +} + +void TEventShow::CalcSelectedIndex(int aWhat) +{ + int index; + if(aWhat >4)return; + if(MsgList[aWhat].SelectedLine < 0)MsgList[aWhat].SelectedLine =0; + if(MsgList[aWhat].SelectedLine >= cMaxSelLine[aWhat]) MsgList[aWhat].SelectedLine = cMaxSelLine[aWhat] -1; + if(MsgList[aWhat].TopIndex >= MsgList[aWhat].Count)MsgList[aWhat].TopIndex = MsgList[aWhat].Count -1; + if(MsgList[aWhat].TopIndex < 0)MsgList[aWhat].TopIndex = 0; + + index = MsgList[aWhat].TopIndex - MsgList[aWhat].SelectedLine; + if(index > -1){ + MsgList[aWhat].SelectedIndex = index; + }else{ + MsgList[aWhat].SelectedLine = 0; + MsgList[aWhat].SelectedIndex = MsgList[aWhat].TopIndex; + } +} + +void TEventShow::TryFireGetNext(int IsForce) +{ + int aInx, GoForce; + int Lcnt =2; + GoForce =1; + if(MsgList[0].SelectedLine <(Lcnt -1)){ + if( (MsgList[0].TopIndex - MsgList[0].SelectedLine) > 0){ + MsgList[0].SelectedLine ++; + if(IsForce){ + TryGetFireData(2,MsgList[0].TopIndex); + } + DrawList(); + GoForce = 0; + } + }else{ + aInx = MsgList[0].TopIndex; + if( (aInx - Lcnt ) > -1 ){ + aInx = aInx - 1; + TryGetFireData(2,aInx); + DrawList(); + GoForce =0; + } + } + if(IsForce && GoForce){ + TryGetFireData(2,MsgList[0].TopIndex); + DrawList(); + } +} + +void TEventShow::TryLinkageGetNext(int IsForce) +{ + int aInx, GoForce; + int Lcnt =2; + GoForce = 1; + if(MsgList[1].SelectedLine <(Lcnt -1)){ + if( (MsgList[1].TopIndex - MsgList[1].SelectedLine) > 0){ + MsgList[1].SelectedLine ++; + if(IsForce){ + TryGetLinkageData(2,MsgList[1].TopIndex); + } + DrawList(); + GoForce = 0; + } + }else{ + aInx = MsgList[1].TopIndex; + if( (aInx - Lcnt ) > -1 ){ + aInx = aInx - 1; + TryGetLinkageData(2,aInx); + DrawList(); + GoForce = 0; + } + } + if(IsForce && GoForce){ + TryGetLinkageData(2,MsgList[1].TopIndex); + DrawList(); + } +} + +void TEventShow::TrySvGetNext(int IsForce) +{ + int aInx, GoForce; + int Lcnt; + Lcnt = 5; + GoForce = 1; + if(MsgList[2].SelectedLine <(Lcnt -1)){ + if( (MsgList[2].TopIndex - MsgList[2].SelectedLine) > 0){ + MsgList[2].SelectedLine ++; + if(IsForce){ + TryGetSvData(2,MsgList[2].TopIndex); + } + DrawList(); + GoForce = 0; + } + }else{ + aInx = MsgList[2].TopIndex; + if( (aInx - Lcnt ) > -1 ){ + aInx = aInx - 1; + TryGetSvData(2,aInx); + DrawList(); + GoForce = 0; + } + } + if(IsForce && GoForce){ + TryGetSvData(2,MsgList[2].TopIndex); + DrawList(); + } +} +void TEventShow::TryFaultGetNext(int IsForce) +{ + int aInx, GoForce; + int Lcnt; + Lcnt = 5; + GoForce = 1; + if(MsgList[3].SelectedLine <(Lcnt -1)){ + if( (MsgList[3].TopIndex - MsgList[3].SelectedLine) > 0){ + MsgList[3].SelectedLine ++; + if(IsForce){ + TryGetFaultData(2,MsgList[3].TopIndex); + } + DrawList(); + GoForce = 0; + } + }else{ + aInx = MsgList[3].TopIndex; + if( (aInx - Lcnt ) > -1 ){ + aInx = aInx - 1; + TryGetFaultData(2,aInx); + DrawList(); + GoForce = 0; + } + } + if(IsForce && GoForce){ + TryGetFaultData(2,MsgList[3].TopIndex); + DrawList(); + } +} +void TEventShow::TryMaskGetNext(int IsForce) +{ + int aInx, GoForce; + int Lcnt; + Lcnt = 5; + GoForce = 1; + if(MsgList[4].SelectedLine <(Lcnt -1)){ + if( (MsgList[4].TopIndex - MsgList[4].SelectedLine) > 0){ + MsgList[4].SelectedLine ++; + if(IsForce){ + TryGetMaskData(2,MsgList[4].TopIndex); + } + DrawList(); + GoForce = 0; + } + }else{ + aInx = MsgList[4].TopIndex; + if( (aInx - Lcnt ) > -1 ){ + aInx = aInx - 1; + TryGetMaskData(2,aInx); + DrawList(); + GoForce = 0; + } + } + if(IsForce && GoForce){ + TryGetMaskData(2,MsgList[4].TopIndex); + DrawList(); + } +} + +TGuiMsgReturn TEventShow::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int aWhat, c, Lcnt; + int aInx; + int aState; + int IsFaultDescp; + unsigned char dType, fType; + unsigned int tUc; + + NoKeyInTick500mS = 0; + + if(aKey == VK_LEFT){ + //Page Up + if(WhatSelected == 0){ + Lcnt = 2; + aInx = MsgList[0].TopIndex; + aInx = aInx + Lcnt; + if(aInx >= MsgList[0].Count){ + aInx = MsgList[0].Count-1; + } + aState = TryGetFireData(2,aInx); + CalcSelectedIndex(0); + DrawList(); + }else + if(WhatSelected == 1){ + Lcnt = 2; + aInx = MsgList[1].TopIndex; + aInx = aInx + Lcnt; + if(aInx >= MsgList[1].Count){ + aInx = MsgList[1].Count-1; + } + aState = TryGetLinkageData(2,aInx); + CalcSelectedIndex(1); + DrawList(); + }else + if(WhatSelected == 2){ + Lcnt = 5; + aInx = MsgList[2].TopIndex; + aInx = aInx + Lcnt; + if(aInx >= MsgList[2].Count){ + aInx = MsgList[2].Count-1; + } + aState = TryGetSvData(2,aInx); + CalcSelectedIndex(2); + DrawList(); + }else + if(WhatSelected == 3){ + Lcnt = 5; + aInx = MsgList[3].TopIndex; + aInx = aInx + Lcnt; + if(aInx >= MsgList[3].Count){ + aInx = MsgList[3].Count-1; + } + aState = TryGetFaultData(2,aInx); + CalcSelectedIndex(3); + DrawList(); + }else + if(WhatSelected == 4){ + Lcnt = 5; + aInx = MsgList[4].TopIndex; + aInx = aInx + Lcnt; + if(aInx >= MsgList[4].Count){ + aInx = MsgList[4].Count-1; + } + aState = TryGetMaskData(2,aInx); + CalcSelectedIndex(4); + DrawList(); + } + }else + if(aKey == VK_RIGHT){ + //Page Down + if(WhatSelected == 0){ + Lcnt = 2; + aInx = MsgList[0].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 0; + } + aState = TryGetFireData(2,aInx); + CalcSelectedIndex(0); + DrawList(); + }else + if(WhatSelected == 1){ + Lcnt = 2; + aInx = MsgList[1].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 0; + } + aState = TryGetLinkageData(2,aInx); + CalcSelectedIndex(1); + DrawList(); + }else + if(WhatSelected == 2){ + Lcnt = 5; + aInx = MsgList[2].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 0; + } + aState = TryGetSvData(2,aInx); + CalcSelectedIndex(2); + DrawList(); + }else + if(WhatSelected == 3){ + Lcnt = 5; + aInx = MsgList[3].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 0; + } + aState = TryGetFaultData(2,aInx); + CalcSelectedIndex(3); + DrawList(); + }else + if(WhatSelected == 4){ + Lcnt = 5; + aInx = MsgList[4].TopIndex; + aInx = aInx - Lcnt; + if(aInx < 0){ + aInx = 0; + } + aState = TryGetMaskData(2,aInx); + CalcSelectedIndex(4); + DrawList(); + } + }else + if(aKey == VK_UP){ + //Index Up + if(WhatSelected == 0){ + Lcnt = 2; + if(MsgList[0].SelectedLine >0){ + MsgList[0].SelectedLine --; + DrawList(); + }else{ + aInx = MsgList[0].TopIndex; + aInx = aInx + 1; + if(aInx >= MsgList[0].Count){ + aInx = MsgList[0].Count-1; + } + aState = TryGetFireData(2,aInx); + DrawList(); + } + }else + if(WhatSelected == 1){ + Lcnt = 2; + if(MsgList[1].SelectedLine >0){ + MsgList[1].SelectedLine --; + DrawList(); + }else{ + aInx = MsgList[1].TopIndex; + aInx = aInx + 1; + if(aInx >= MsgList[1].Count){ + aInx = MsgList[1].Count-1; + } + aState = TryGetLinkageData(2,aInx); + DrawList(); + } + }else + if(WhatSelected == 2){ + Lcnt = 5; + if(MsgList[2].SelectedLine >0){ + MsgList[2].SelectedLine --; + CalcSelectedIndex(2); + DrawList(); + }else{ + aInx = MsgList[2].TopIndex; + aInx = aInx + 1; + if(aInx >= MsgList[2].Count){ + aInx = MsgList[2].Count-1; + } + aState = TryGetSvData(2,aInx); + DrawList(); + } + }else + if(WhatSelected == 3){ + Lcnt = 5; + if(MsgList[3].SelectedLine >0){ + MsgList[3].SelectedLine --; + CalcSelectedIndex(3); + DrawList(); + }else{ + aInx = MsgList[3].TopIndex; + aInx = aInx + 1; + if(aInx >= MsgList[3].Count){ + aInx = MsgList[3].Count-1; + } + aState = TryGetFaultData(2,aInx); + DrawList(); + } + }else + if(WhatSelected == 4){ + Lcnt = 5; + if(MsgList[4].SelectedLine >0){ + MsgList[4].SelectedLine --; + CalcSelectedIndex(4); + DrawList(); + }else{ + aInx = MsgList[4].TopIndex; + aInx = aInx +1; + if(aInx >= MsgList[4].Count){ + aInx = MsgList[4].Count-1; + } + aState = TryGetMaskData(2,aInx); + DrawList(); + } + } + }else + if(aKey == VK_DOWN){ + //Index Down + if(WhatSelected == 0){ + TryFireGetNext(0); + }else + if(WhatSelected == 1){ + TryLinkageGetNext(0); + }else + if(WhatSelected == 2){ + TrySvGetNext(0); + }else + if(WhatSelected == 3){ + TryFaultGetNext(0); + }else + if(WhatSelected == 4){ + TryMaskGetNext(0); + } + }else + if(aKey == HOTKEY_INF_CONF){ + switch(WhatSelected){ + case 0: + aInx = MsgList[0].SelectedLine; + if( (aInx > -1) && (aInx <2) ){ + if(MsgList[0].Body[aInx].Splite.iByte0 == 0){ + if(CtlCenter.ieMsgFire.Count == 1){ + //Make Delay 180 second; + //if(aInx == 0){ + //MakeDelay180Sec(); + //if(CtlCenter.ieMsgLinkage.DelayCount){ + // GolbalDelayTick = 180; + //}else{ + // GolbalDelayTick = 0; + //} + //EventShow.GolbalDelayValueOnShowing = 181; + //} + } + CtlCenter.ieFireMsgConfAddr(MsgList[0].Body[aInx].D32[2]); + tUc = MsgList[0].Body[aInx].Splite.UserCode; + if(MainCtl.fData.Split.NetworkMode == 1){ + if(MsgList[0].Body[aInx].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + Record.OperateAdd_FireConfirm(MsgList[0].Body[aInx].Splite.PCtlNum, MsgList[0].Body[aInx].Splite.P0, MsgList[0].Body[aInx].Splite.P1, MsgList[0].Body[aInx].Splite.dType, tUc, MsgList[0].Body[aInx].Splite.Data0); + }else{ + Record.OperateAdd_FireConfirm(MsgList[0].Body[aInx].Splite.PCtlNum, MsgList[0].Body[aInx].Splite.P0, MsgList[0].Body[aInx].Splite.P1, MsgList[0].Body[aInx].Splite.dType, tUc, MsgList[0].Body[aInx].Splite.Data0); + Record.OperatePublic_FireRemoteConfirm(MsgList[0].Body[aInx].Splite.PCtlNum, MsgList[0].Body[aInx].Splite.P0, MsgList[0].Body[aInx].Splite.P1, MsgList[0].Body[aInx].Splite.dType, MsgList[0].Body[aInx].Splite.Data0); + } + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + Record.OperateAdd_FireConfirm(MsgList[0].Body[aInx].Splite.PCtlNum, MsgList[0].Body[aInx].Splite.P0, MsgList[0].Body[aInx].Splite.P1, MsgList[0].Body[aInx].Splite.dType, tUc, MsgList[0].Body[aInx].Splite.Data0); + Record.OperatePublic_FireRemoteConfirm(MsgList[0].Body[aInx].Splite.PCtlNum, MsgList[0].Body[aInx].Splite.P0, MsgList[0].Body[aInx].Splite.P1, MsgList[0].Body[aInx].Splite.dType, MsgList[0].Body[aInx].Splite.Data0); + }else{ + Record.OperateAdd_FireConfirm(MsgList[0].Body[aInx].Splite.PCtlNum, MsgList[0].Body[aInx].Splite.P0, MsgList[0].Body[aInx].Splite.P1, MsgList[0].Body[aInx].Splite.dType, tUc, MsgList[0].Body[aInx].Splite.Data0); + } + TryFireGetNext(1); + } + } + break; + /*case 1: + aInx = MsgList[1].SelectedLine; + if( (aInx > -1) && (aInx <4) ){ + if(MsgList[1].Body[aInx].Splite.mType == etLinkageStart){ + CtlCenter.ieLinkageMsgStartConfAddr( MsgList[1].Body[aInx].D32[2]); + }else + if(MsgList[1].Body[aInx].Splite.mType == etLinkageFeedBack){ + CtlCenter.ieLinkageMsgFbConfAddr( MsgList[1].Body[aInx].D32[2]); + } + TryLinkageGetNext(1); + } + break;*/ + case 2: + + break; + case 3: + aInx = MsgList[3].SelectedLine; + if( (aInx > -1) && (aInx <5) ){ + if(MsgList[3].Body[aInx].Splite.iByte0 == 0){ + CtlCenter.ieFaultMsgFaultConfAddr(MsgList[3].Body[aInx].D32[2]); + dType = MsgList[3].Body[aInx].Splite.dType; + fType = MsgList[3].Body[aInx].Splite.P2; + IsFaultDescp = MsgList[3].Body[aInx].Splite.Data1; + tUc = MsgList[3].Body[aInx].Splite.UserCode; + if(MainCtl.fData.Split.NetworkMode == 1){ + if(MsgList[3].Body[aInx].Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + Record.OperateAdd_FaultConfirm(MsgList[3].Body[aInx].Splite.PCtlNum, MsgList[3].Body[aInx].Splite.P0, MsgList[3].Body[aInx].Splite.P1, dType, fType, IsFaultDescp, tUc); + }else{ + Record.OperateAdd_FaultConfirm(MsgList[3].Body[aInx].Splite.PCtlNum, MsgList[3].Body[aInx].Splite.P0, MsgList[3].Body[aInx].Splite.P1, dType, fType, IsFaultDescp, tUc); + Record.OperatePublic_FaultRemoteConfirm(MsgList[3].Body[aInx].Splite.PCtlNum, MsgList[3].Body[aInx].Splite.P0, MsgList[3].Body[aInx].Splite.P1, dType, fType, IsFaultDescp); + } + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + Record.OperateAdd_FaultConfirm(MsgList[3].Body[aInx].Splite.PCtlNum, MsgList[3].Body[aInx].Splite.P0, MsgList[3].Body[aInx].Splite.P1, dType, fType, IsFaultDescp, tUc); + Record.OperatePublic_FaultRemoteConfirm(MsgList[3].Body[aInx].Splite.PCtlNum, MsgList[3].Body[aInx].Splite.P0, MsgList[3].Body[aInx].Splite.P1, dType, fType, IsFaultDescp); + }else{ + Record.OperateAdd_FaultConfirm(MsgList[3].Body[aInx].Splite.PCtlNum, MsgList[3].Body[aInx].Splite.P0, MsgList[3].Body[aInx].Splite.P1, dType, fType, IsFaultDescp, tUc); + } + TryFaultGetNext(1); + } + } + break; + /*case 4: + aInx = MsgList[4].SelectedLine; + if( (aInx > -1) && (aInx <10) ){ + c = MsgList[4].TopIndex - aInx; + if( (c>-1)&&(c<1000) ){ + //CtlCenter.ieMsgMask.Body[c].Splite.iByte0 = 1; + } + TryMaskGetNext(1); + } + break;*/ + default:break; + } + }else + if(aKey == VK_TAB){ + aWhat = WhatSelected; + for(c=0; c<5; c++){ + aWhat--; + if(aWhat < 0){ + aWhat = 4; + } + if(MsgList[aWhat].Count > 0){ + WhatSelected = aWhat; + break; + } + } + if(WhatSelected == 0)TryGetFireData(2,MsgList[0].TopIndex); + else if(WhatSelected == 1)TryGetLinkageData(2,MsgList[1].TopIndex); + else if(WhatSelected == 2)TryGetSvData(2,MsgList[2].TopIndex); + else if(WhatSelected == 3)TryGetFaultData(2,MsgList[3].TopIndex); + else if(WhatSelected == 4)TryGetMaskData(2,MsgList[4].TopIndex); + DrawList(); + }else + if(aKey == dfKEY_ENCN){ + aWhat = WhatSelected; + for(c=0; c<5; c++){ + aWhat++; + if(aWhat > 4){ + aWhat = 0; + } + if(MsgList[aWhat].Count > 0){ + WhatSelected = aWhat; + break; + } + } + if(WhatSelected == 0)TryGetFireData(2,MsgList[0].TopIndex); + else if(WhatSelected == 1)TryGetLinkageData(2,MsgList[1].TopIndex); + else if(WhatSelected == 2)TryGetSvData(2,MsgList[2].TopIndex); + else if(WhatSelected == 3)TryGetFaultData(2,MsgList[3].TopIndex); + else if(WhatSelected == 4)TryGetMaskData(2,MsgList[4].TopIndex); + DrawList(); + }else + if(aKey == VK_F2){ + if(WhatSelected == 0){ + Lcnt = 2; + aInx = MsgList[0].TopIndex; + aInx = (aInx / Lcnt +1) * Lcnt; + if(aInx < (MsgList[0].Count)){ + aState = TryGetFireData(2,aInx); + } + DrawList(); + }else + if(WhatSelected == 1){ + Lcnt = 2; + aInx = MsgList[1].TopIndex; + aInx = (aInx / Lcnt +1) * Lcnt; + if(aInx < (MsgList[1].Count)){ + aState = TryGetLinkageData(2,aInx); + } + DrawList(); + }else + if(WhatSelected == 2){ + Lcnt = 5; + aInx = MsgList[2].TopIndex; + aInx = (aInx / Lcnt +1) * Lcnt; + if(aInx < (MsgList[2].Count)){ + aState = TryGetSvData(2,aInx); + } + DrawList(); + }else + if(WhatSelected == 3){ + Lcnt = 5; + aInx = MsgList[3].TopIndex; + aInx = (aInx / Lcnt +1) * Lcnt; + if(aInx < (MsgList[3].Count)){ + aState = TryGetFaultData(2,aInx); + } + DrawList(); + }else + if(WhatSelected == 4){ + Lcnt = 5; + aInx = MsgList[4].TopIndex; + aInx = (aInx / Lcnt +1) * Lcnt; + if(aInx < (MsgList[4].Count)){ + aState = TryGetMaskData(2,aInx); + } + DrawList(); + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + return aMsg; +} + +void TEventShow::KeyJab() +{ + NoKeyInTick500mS = 0; +} + +int TEventShow::MakeFastCheck() +{ + NoKeyInTick500mS = 60; + return 0; +} + +void TEventShow::MsgReset() +{ + int i; + MsgList[0].Count = 0; + MsgList[1].Count = 0; + MsgList[2].Count = 0; + MsgList[3].Count = 0; + MsgList[4].Count = 0; + + MsgList[0].NewCount = 0; + MsgList[1].NewCount = 0; + MsgList[2].NewCount = 0; + MsgList[3].NewCount = 0; + MsgList[4].NewCount = 0; + + MsgList[1].StartCount =0; + MsgList[1].FbCount =0; + + //StartCountDownList.Count = 0; + //for(i=0; i<1000; i++){ + // StartCountDownList.Path[i] = 0; + // StartCountDownList.TimeSec[i] =0; + //} + + DrawSelf(); + DrawFirstFire(); +} +/* +void TEventShow::MsgStartAddCountDownItem(unsigned int Path) +{ + int i, Cnt; + if(StartCountDownList.Count > 950){ + IsEventAddBlock =1; + return; + } + Cnt = 0; + for(i=0; i<1000; i++){ + if(StartCountDownList.Path[i] != 0){ + TmpPath[i] = StartCountDownList.Path[i]; + TmpTimeSec[i] = StartCountDownList.TimeSec[i]; + Cnt++; + } + } + for(i=0; i 950){ + IsEventAddBlock =1; + return; + } + StartCountDownList.Path[Cnt] = Path; + StartCountDownList.TimeSec[Cnt] = 0; + Cnt++; + for(; Cnt<1000; Cnt++){ + StartCountDownList.Path[Cnt] = 0; + StartCountDownList.TimeSec[Cnt] = 0; + } + StartCountDownList.Count++; +} +*/ +void TEventShow::StartToResetPrc() +{ + IsGoReset = 1; + GoResetTick =0; + + RectFillRender(Bound.Left, Bound.Top, Bound.Right, Bound.Bottom, Color); + if(LanguageEnCn==0)TextRender_string24(300, 190, clNearBlack, "开始复位..."); + else TextRender_string24(300, 190, clNearBlack, "Resetting"); +} + +void TEventShow::ShowGolbalDelayTime() +{ + if(GolbalDelayTick != GolbalDelayValueOnShowing){ + TMyString::sFrom3Dg(GolbalDelayTick,cText); + TextRender_string24(744+4, TitleUp+2, clNearWhite, ContentColor, cText); + GolbalDelayValueOnShowing = GolbalDelayTick; + } +} + +int TEventShow::Task1000Ms() +{ + int rst; + if( IsGoReset == 0 ){ + //if( ((Register.IsOnShow == 0) && (Register.IsOnGo == 0)) && (LiteSelfCheck.IsShowing == 0) )return 0; + if(CheckIsFrozeScreen()== 0) { + DrawFirstFire(); + rst = 2; + if(PmsIntervene.IsShow == 0){ + rst = ManageState(); + Tick1000MsRdy = 1; + AutoRollTick++; + } + if(this->IsShowing){ + //ShowGolbalDelayTime(); + ShowCountDownTime(); + } + return rst; + }else{ + return 2; + } + }else{ + GoResetTick++; + if(MainCtl.fData.Split.NetworkMode == 1){ + if(GoResetTick == 2){ + if(LanguageEnCn==0)TextRender_string24(300, 220, clDeepGreen, "复位完成"); + else TextRender_string24(300, 220, clDeepGreen, "Reset Completed"); + }else + if(GoResetTick > 3){ + ResetAfterCallBack(); + IsGoReset = 0; + IsShowingMsgReset = 0; + return -1; + } + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + if(GoResetTick == 6){ + if(LanguageEnCn==0)TextRender_string24(300, 220, clDeepGreen, "复位完成"); + else TextRender_string24(300, 220, clDeepGreen, "Reset Completed"); + }else + if(GoResetTick > 7){ + ResetAfterCallBack(); + IsGoReset = 0; + IsShowingMsgReset = 0; + ProtoC2C.SlaveDoUploadMaskList(); + return -1; + } + }else{ + if(GoResetTick == 6){ + if(LanguageEnCn==0)TextRender_string24(300, 220, clDeepGreen, "复位完成"); + else TextRender_string24(300, 220, clDeepGreen, "Reset Completed"); + }else + if(GoResetTick > 7){ + ResetAfterCallBack(); + IsGoReset = 0; + IsShowingMsgReset = 0; + return -1; + } + } + return -2; + } +} + +int TEventShow::ExtRequst(unsigned char Prm) +{ + return 0; +} diff --git a/MyCode/Gui/EventShow.h b/MyCode/Gui/EventShow.h new file mode 100644 index 0000000..28152f8 --- /dev/null +++ b/MyCode/Gui/EventShow.h @@ -0,0 +1,356 @@ +#ifndef EVENTSHOW_H_ +#define EVENTSHOW_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "MainCtl.h" + +#include "Runtime.h" +//#include "ControlCenter.h" + +typedef union{ + unsigned int D32[6]; + unsigned char D8[24]; + struct { + unsigned int LD32; + unsigned short HD16; + unsigned short Rsv0; + unsigned short Rsv1; + unsigned short Rsv2; + }DateTime; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char iByte0; + unsigned char State; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char mType; + unsigned char dType; + unsigned char Data0; + unsigned char Data1; + + unsigned int UserCode; + unsigned short AreaNum; + unsigned short DumpShort; + }Splite; +}TieMsg; + +typedef struct{ + short Left; + short Top; + short Width; + short Height; + short Right; + short Bottom; +}TRectEvTitleTop, TRectEvTitleBottom, TRectVertScrrolBar; + +typedef struct{ + short Left[5]; + short Top[5]; + short Width[5]; + short Height[5]; + short Right[5]; + short Bottom[5]; +}TRectEvEntry; + +typedef struct{ + short Left[2]; + short Top[2]; + short Width[2]; + short Height[2]; + short Right[2]; + short Bottom[2]; +}TRectEvEntryTop, TRectEvEntryBottom; + +class TEventShow{ + public: + static constexpr unsigned int ColorTitle = 0xFFA3918F; + static constexpr unsigned int ColorTitleInSelected = clDeepBlue; + static constexpr unsigned int ColorTitleFireNotOnSelected = 0xFF783030; + static constexpr unsigned int ColorTitleText = clNearWhite; + static constexpr unsigned int ColorBg = clDarkkGray; + static constexpr TRectEvTitleTop RectTitleTop ={ + .Left = 2, + .Top = 46, + .Width = 652, + .Height = 40, + .Right = 2 + 652 -1, + .Bottom = 46 + 40 -1, + }; + static constexpr TRectEvTitleBottom RectTitleBtm ={ + .Left = 2, + .Top = 248, + .Width = 710, + .Height = 40, + .Right = 2 + 710 -1, + .Bottom = 248 + 40 -1, + }; + static constexpr TRectVertScrrolBar RectVertScrrolBar ={ + .Left = 776, + .Top = 80, + .Width = 20, + .Height = 360, + .Right = 776 + 20 -1, + .Bottom = 80 + 360 -1, + }; + static constexpr TRectEvEntry RectEvEntryList = { + .Left[0] =10, + .Left[1] =10, + .Left[2] =10, + .Left[3] =10, + .Left[4] =10, + .Top[0] = 90 + 50 * 0, + .Top[1] = 90 + 50 * 1, + .Top[2] = 90 + 50 * 2, + .Top[3] = 90 + 50 * 3, + .Top[4] = 90 + 50 * 4, + .Width[0] = 760, + .Width[1] = 760, + .Width[2] = 760, + .Width[3] = 760, + .Width[4] = 760, + .Height[0] = 40, + .Height[1] = 40, + .Height[2] = 40, + .Height[3] = 40, + .Height[4] = 40, + .Right[0] = 10 + 760 -1, + .Right[1] = 10 + 760 -1, + .Right[2] = 10 + 760 -1, + .Right[3] = 10 + 760 -1, + .Right[4] = 10 + 760 -1, + .Bottom[0] = 90 + 50 * 0 + 40 -1, + .Bottom[1] = 90 + 50 * 1 + 40 -1, + .Bottom[2] = 90 + 50 * 2 + 40 -1, + .Bottom[3] = 90 + 50 * 3 + 40 -1, + .Bottom[4] = 90 + 50 * 4 + 40 -1, + }; + static constexpr TRectEvEntryTop RectEvEntryTopList = { + .Left[0] =10, + .Left[1] =10, + .Top[0] = 90 + 50 * 0, + .Top[1] = 90 + 50 * 1, + .Width[0] = 760, + .Width[1] = 760, + .Height[0] = 40, + .Height[1] = 40, + .Right[0] = 10 + 760 -1, + .Right[1] = 10 + 760 -1, + .Bottom[0] = 90 + 50 * 0 + 40 -1, + .Bottom[1] = 90 + 50 * 1 + 40 -1, + }; + static constexpr TRectEvEntryBottom RectEvEntryBtmList = { + .Left[0] =10, + .Left[1] =10, + .Top[0] = 280 + 50 * 0, + .Top[1] = 280 + 50 * 1, + .Width[0] = 760, + .Width[1] = 760, + .Height[0] = 40, + .Height[1] = 40, + .Right[0] = 10 + 760 -1, + .Right[1] = 10 + 760 -1, + .Bottom[0] = 280 + 50 * 0 + 40 -1, + .Bottom[1] = 280 + 50 * 1 + 40 -1, + }; + + public: + + unsigned int IsShowing; + TStaticText Caption, SText; + TRect Bound; + TRect Content; + TRect ContentUp; + TRect ContentDown; + + short SelectedCol; + short SelectedUpCol; + short SelectedDownCol; + + unsigned int Color; + + unsigned int LinkDelayLineBClr[2]; + struct{ + int RefrashIndex; + int ShowingIndex; + int IsListUpdata; + int StartCount; + int FbCount; + int DelayCount; + int StopCount; + int Count; + int NewCount; + int TopIndex; + int ReqTopIndex; + int BlankLine; + int ShowRemainCnt; + int TailRemain; + int SelectedLine; + int SelectedIndex; + TieMsg Body[10]; + }MsgList[5]; + TieMsg MsgBuf[10]; + TieMsg MsgBuf4OneDelay; + short WhatSelected; + unsigned char IsUpdata; + unsigned char LastDrawSplite; + unsigned char NoKeyInTick500mS; + unsigned char NoNewEventTick500mS; + + unsigned char FirstFireHadDraw; + unsigned char OutLineType; + unsigned char IsOutlineChange; + unsigned char Tick1000MsRdy; + + //struct{ + // int Count; + // unsigned int Path[1000]; + // unsigned char TimeSec[1000]; + //}StartCountDownList; + + //unsigned int TmpPath[1000]; + //unsigned char TmpTimeSec[1000]; + + char Text[128]; + int NeedShowDescp; + char TextDescp[128]; + char cText[128]; + int AutoRollTick; + int IsShouldReturn; + unsigned int DrawListNotDone[5]; + + struct{ + unsigned int ManualType; + unsigned int mType; + unsigned int SubType; + unsigned int aPath; + }ConfirmMsg; + + unsigned char IsGoReset; + unsigned char GoResetTick; + int NoOpaUd[5]; + int FirstFireShowDescpInteval; + union{ + unsigned int D32[16]; + char Text[64]; + }DescpText; + unsigned int GolbalDelayValueOnShowing; + private: + const char *CapString[8]; + const char *CapStringDown[8]; + TDateTimeBytes DateTimeCovered; + public: + TEventShow(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, int BoderW, u32 aColor); + + void DrawSelf(); + void FillText(unsigned char aWhat, unsigned int aIndex, unsigned int aLineNum); + void FillTextEn(unsigned char aWhat, unsigned int aIndex, unsigned int aLineNum); + void Show(); + void Hide(); + + void CoverDateTimeIllegal(TieMsg Src, TDateTimeBytes *Dst); + void CoverDateTimeIllegal(TEventMsg Src, TDateTimeBytes *Dst); + + void DrawOutLineAll(); + void DrawOutLineUpDown(); + void DrawAll(); + void DrawUp(); + void DrawDown(); + + void DrawListUp(); + void DrawListDown(); + void DrawListAll(); + void DrawFirstFire(); + + void DrawFig(); + void DrawListHeader(); + void DrawList(); + void DrawListFullRedraw(void); + void AutoRollShow(); + void ShowCountDownTime(); + + void MsgReset(); + + int TryGetFireData(int GetListMode, int aInx); + int TryGetFaultData(int GetListMode, int aInx); + int TryGetSvData(int GetListMode, int aInx); + int TryGetLinkageData(int GetListMode, int aInx); + int TryGetMaskData(int GetListMode, int aInx); + + void Task100Ms(void); + int Task1000Ms(void); + + void TryFireGetNext(int IsForce); + void TryLinkageGetNext(int IsForce); + void TrySvGetNext(int IsForce); + void TryFaultGetNext(int IsForce); + void TryMaskGetNext(int IsForce); + + TGuiMsgReturn KeyIn(unsigned char aKey); + void KeyJab(); + + void CalcSelectedIndex(int aWhat); + + void ReNewTopIndex(short aIdx); + int ManageState(); + + int MakeFastCheck(); + + void MakeShow(); + void ShowTask(); + + int DoNoEvent(); + int DoNoOperate(); + int DoOperate(); + void CheckReturn(); + + void MsgStartAddCountDownItem(unsigned int Path); + void ManageStartCountDown(); + + void StartToResetPrc(); + + void FirstFireFillDescp(); + + void MakeDelay180Sec(); + + void ShowGolbalDelayTime(); + + int ExtRequst(unsigned char Prm); +}; + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/FloorDisplay.cpp b/MyCode/Gui/FloorDisplay.cpp new file mode 100644 index 0000000..b32ef98 --- /dev/null +++ b/MyCode/Gui/FloorDisplay.cpp @@ -0,0 +1,1217 @@ +#include "RuntimeData.h" +#include "FloorDisplay.h" +#include "DevMask.h" + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" +} + +#define dfAddrLineNum 6 +#define dfDescpLineNum 4 +#define dfDescpMax 250 + +#define dAddr_DescpBuf dAddrSdRam_Commom + +const short AddrLeft[8] = {10,60,170,420,480,788,788,788}; +const short AddrTop[8] = {42,84,126,168,210,252,296,338}; +const short AddrTextLeft[8] = {12,62,172,422,482,790,790,790}; +const short AddrTextTop[8] = {50,92,134,176,218,260,304,346}; + +const short DescpLeft[4] = {10,120,788,420}; +const short DescpTop[8] = {42,84,126,168,210,252,296,338}; +const short DescpTextLeft[4] = {12,122,172,422}; +const short DescpTextTop[8] = {50,92,134,176,218,260,304,346}; + +void TFloorDisplay::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+450,Top,340, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + + RectPanel.Set(Left + 420,Top + CH, Right - 4, Top + CH + 6 + 284); + Color = aColor; + #undef CH + + CtlIndex =0; + SubCtlIndex =0; + IsUsing = 0; + WhatSet = 0; + + Caption.Border.Color = clGray; + + Lv.DevCount = 0; + Lv.SelectedLineNum = 0; + Lv.SelectedIndex = 0; + Lv.TopIndex = 0; +} + +void TFloorDisplay::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TFloorDisplay::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TFloorDisplay::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TFloorDisplay::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TFloorDisplay::DrawCaption(void) +{ + TMyString::sFromStr("通用设置->楼层显示", Caption.Text); + Caption.Show(); +} + +void TFloorDisplay::DrawCaption2(void) +{ + TMyString::sFromStr(" ", SText.Text); + SText.Show(); +} + +void TFloorDisplay::DrawCaption24Addr(void) +{ + //TMyString::sFromStr("按TAB键切换至保存或重新读取", SText.Text); + //SText.Show(); +} + +void TFloorDisplay::DrawCaption24Descp(void) +{ + //TMyString::sFromStr("按TAB键切换至保存或重新读取", SText.Text); + //SText.Show(); +} + +void TFloorDisplay::Show() +{ + DrawSelf(); + DrawCaption(); + TextRender_string24(250, 300 ,clNearBlack, "1.上下键切换选择项目; "); + TextRender_string24(250, 340 ,clNearBlack, "2.确定键进入"); +} + +void FullRedraw() +{ + +} + +void TFloorDisplay::Check4Selected(void) +{ + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[2].Selected = 0; + switch(CtlIndex){ + case 0: + aPanel->Btn[0].Selected = 1; + break; + case 1: + aPanel->Btn[1].Selected = 1; + break; + case 2: + aPanel->Btn[2].Selected = 1; + break; + default: + CtlIndex = 0; + aPanel->Btn[0].Selected = 1; + break; + } +} + +void TFloorDisplay::Check4Selected4Global(void) +{ + aPanel->Edit[0].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Btn[0].Selected = 1; + break; + case 2: + aPanel->Btn[1].Selected = 1; + break; + default: + CtlIndex = 0; + aPanel->Edit[0].Selected = 1; + break; + } +} + +void TFloorDisplay::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + + RectPanel.Set(250,150, 550, 290); + + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + + aPanel->Btn[0].Init(40,5,220,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[1].Init(40,45,220,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[2].Init(40,85,220,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[0].Caption.FromStr(" 全局参数设置 "); + aPanel->Btn[1].Caption.FromStr("层显设备地址分配"); + aPanel->Btn[2].Caption.FromStr("层(区)描述字设置"); + for(i=0; i<3;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(10); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); +} + + +void TFloorDisplay::InitPanel4Global(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + + RectPanel.Set(250,150, 550, 290); + + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->Edit[0].Init(50,5,200,34,x,yt,clNearBlack,clNearWhite); + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + } + aPanel->Edit[0].SetMaxLen(15); + aPanel->Edit[0].SetInputMaskEn(); + aPanel->Edit[0].Str.FromStr("----未知详情----"); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[0].IsShowCursor = 0; + + aPanel->Btn[0].Init(40,45,220,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[1].Init(40,85,220,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[0].Caption.FromStr(" 读取参数 "); + aPanel->Btn[1].Caption.FromStr(" 保存参数 "); + for(i=0; i<2;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(10); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected4Global(); + aPanel->ReDrawItems(); +} + + +void TFloorDisplay::InitPanel4SetAddr(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + + RectPanel.Set(6,76, 794, 434); + + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[0].Init(0,0,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[1].Init(416,0,70,30,x,yt,clNearBlack,clFrmFace); + + TMyString::sFromStr("序号 设备列表 设备描述", aPanel->SText[0].Text); + TMyString::sFromStr("显址 楼层描述", aPanel->SText[1].Text); + for(i=0; i<2;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + + aPanel->Edit[0].Init(AddrLeft[3] + 1,AddrTop[0] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(AddrLeft[3] + 1,AddrTop[1] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(AddrLeft[3] + 1,AddrTop[2] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[3].Init(AddrLeft[3] + 1,AddrTop[3] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[4].Init(AddrLeft[3] + 1,AddrTop[4] + 1,48,30,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[5].Init(AddrLeft[3] + 1,AddrTop[5] + 1,48,30,x,yt,clNearBlack,clNearWhite); + + for(i=0; i<6;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + aPanel->Edit[i].Pst = 2; + aPanel->Edit[i].Selected = 0; + } + + aPanel->Btn[0].Init(420,300,168,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[1].Init(600,300,168,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[0].Caption.FromStr("重新读取设定"); + aPanel->Btn[1].Caption.FromStr("保存所有设定"); + for(i=0; i<2;i++){ + aPanel->Btn[i].Selected = 0; + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(10); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + x = RectPanel.Left; + y = RectPanel.Top; + for(i=0; i<6; i++){ + VertLineRender(AddrLeft[i], y + AddrTop[0], 252, clGray); + } + for(i=0; i<7; i++){ + HorizLineRender(AddrLeft[0], y + AddrTop[i], 776, clGray); + } +} + +void TFloorDisplay::DescpBufInit() +{ + int i,x; + unsigned int aAddr; + aAddr = dAddr_DescpBuf; + for(i=0; i<256; i++){ + for(x=0; x<32; x++){ + *(volatile unsigned char *)(aAddr + (i*32) + x) = 0; + } + } +} + +void TFloorDisplay::LoadDescpFromSys() +{ + ReadFromFlash(); +} + +void TFloorDisplay::InitPanel4SetDescp(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + + RectPanel.Set(6,76, 794, 336); + + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[0].Init(6,0,70,30,x,yt,clNearBlack,clFrmFace); + aPanel->SText[1].Init(12,264,700,30,x,yt,clNearBlack,Color); + aPanel->SText[2].Init(12,290,700,30,x,yt,clNearBlack,Color); + + TMyString::sFromStr("楼层区域 楼层区域描述", aPanel->SText[0].Text); + TMyString::sFromStr("1.中/英健切换输入法,上下键切换选中条目", aPanel->SText[1].Text); + TMyString::sFromStr("2.TAB键在编辑与读取保存按钮之间切换切换", aPanel->SText[2].Text); + + aPanel->Edit[0].Init(DescpLeft[1] + 2,DescpTop[0],400,32,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(DescpLeft[1] + 2,DescpTop[1],400,32,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(DescpLeft[1] + 2,DescpTop[2],400,33,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[3].Init(DescpLeft[1] + 2,DescpTop[3],400,34,x,yt,clNearBlack,clNearWhite); + + for(i=0; i<4;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + aPanel->Edit[i].Pst = 2; + aPanel->Edit[i].Selected = 0; + } + + aPanel->SText[11].Init(176,212,70,30,x,yt,clNearBlack,clFrmFace); + TMyString::sFromStr("跳到此索引号:", aPanel->SText[11].Text); + aPanel->Edit[11].Init(340,212,60,34,x,yt,clNearBlack,clNearWhite); + aPanel->Edit[11].Enable = 0; + aPanel->Edit[11].Visible = 1; + aPanel->Edit[11].SetMaxLen(3); + aPanel->Edit[11].SetInputMaskEn(); + aPanel->Edit[11].Str.FromStr("001"); + aPanel->Edit[11].Pst = 2; + aPanel->Edit[11].Selected = 0; + + aPanel->Btn[0].Init(420,212,168,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[1].Init(600,212,168,34,x,yt,clNearBlack,clNearWhite); + aPanel->Btn[0].Caption.FromStr("重新读取设定"); + aPanel->Btn[1].Caption.FromStr("保存所有设定"); + for(i=0; i<2;i++){ + aPanel->Btn[i].Selected = 0; + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(10); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + x = RectPanel.Left; + y = RectPanel.Top; + for(i=0; i<3; i++){ + VertLineRender(DescpLeft[i], y + DescpTop[0], 170, clGray); + } + for(i=0; i<5; i++){ + HorizLineRender(DescpLeft[0], y + DescpTop[i], 776, clGray); + } +} + +void TFloorDisplay::LoadDev() +{ + int i,a, inx; + inx = 0; + Lv.DevCount = 0; + for(i=0; i<256; i++){ + AddrAssign[i].Path0 = 0; + AddrAssign[i].Path1 = 0; + AddrAssign[i].aAssign = 0; + } + for(i=0; i -1) { + inx = Lv.SelectedLineNum + Lv.TopIndex; + if(inx < Lv.DevCount){ + if(Lv.SelectedLineNum < 10){ + RestoreIndex = inx; + RestoreEditIndex = Lv.SelectedLineNum; + aPanel->Edit[Lv.SelectedLineNum].Str.FromUInt3Dg(AddrAssign[inx].aAssign); + aPanel->Edit[Lv.SelectedLineNum].Selected = 1; + aPanel->Edit[Lv.SelectedLineNum].Show(); + } + } + } +} + +void TFloorDisplay::RestoreEditAddr() +{ + int eIndex; + if(RestoreIndex < Lv.DevCount){ + AddrAssign[RestoreIndex].aAssign = aPanel->Edit[RestoreEditIndex].Str.ToInteger(); + } +} + +void TFloorDisplay::DrawAddrList() +{ + int i, inx, x, y; + inx = Lv.TopIndex; + for(i=0; i<6; i++){ + if(inx < Lv.DevCount){ + y = RectPanel.Top + AddrTextTop[i]; + TMyString::sFrom3Dg(Lv.TopIndex +i + 1, Text.Body); + TextRender_string24(AddrTextLeft[0], y ,clNearBlack, clFrmFace, Text.Body); + TMyString::sClear(Text.Body); + TMyString::sAddOn2Dg(AddrAssign[inx].Path0, Text.Body); + TMyString::sAddOnStr("-", Text.Body); + TMyString::sAddOn3Dg(AddrAssign[inx].Path1, Text.Body); + TextRender_string24(AddrTextLeft[1] +3, y ,clNearBlack, clFrmFace, Text.Body); + //TMyString::sFillFixLen(Text.Body, 20); + //TextRender_string24(AddrTextLeft[2], AddrTextTop[i] ,clNearBlack, clFrmFace, Text.Body); + aPanel->Edit[i].Str.FromUInt3Dg(AddrAssign[inx].aAssign); + aPanel->Edit[i].Pst =2; + aPanel->Edit[i].Show(); + //TMyString::sFillFixLen(Text.Body, 20); + //TextRender_string24(AddrTextLeft[2], AddrTextTop[i] ,clNearBlack, clFrmFace, Text.Body); + inx++; + }else{ + y = RectPanel.Top + AddrTextTop[i]; + TextRender_string24(AddrTextLeft[0] +3, y ,clNearBlack, clFrmFace, " "); + TextRender_string24(AddrTextLeft[1] +3, y ,clNearBlack, clFrmFace, " "); + TextRender_string24(AddrTextLeft[2] +3, y ,clNearBlack, clFrmFace, " "); + RectFillRender(aPanel->Edit[i].Bound.Left, aPanel->Edit[i].Bound.Top, aPanel->Edit[i].Bound.Right, aPanel->Edit[i].Bound.Bottom, clFrmFace); + TextRender_string24(AddrTextLeft[4] +3, y ,clNearBlack, clFrmFace, " "); + inx++; + } + } +} + +void TFloorDisplay::DrawDescpList() +{ + int i, inx, x, y, m; + unsigned int aAddr; + aAddr = dAddr_DescpBuf; + + inx = Lv.TopIndex; + for(i=0; iEdit[i].Str.Text); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Show(); + inx++; + }else{ + y = RectPanel.Top + AddrTextTop[i]; + TextRender_string24(AddrTextLeft[0] +3, y ,clNearBlack, clFrmFace, " "); + RectFillRender(aPanel->Edit[i].Bound.Left, aPanel->Edit[i].Bound.Top, aPanel->Edit[i].Bound.Right, aPanel->Edit[i].Bound.Bottom, clFrmFace); + inx++; + } + } +} + +void TFloorDisplay::RestoreDescpFromEdits() +{ + int i, inx, x, y, m; + unsigned int aAddr; + aAddr = dAddr_DescpBuf; + + inx = Lv.TopIndex; + for(i=0; iEdit[i].Str.Text); + inx++; + }else{ + y = RectPanel.Top + AddrTextTop[i]; + TextRender_string24(AddrTextLeft[0] +3, y ,clNearBlack, clFrmFace, " "); + RectFillRender(aPanel->Edit[i].Bound.Left, aPanel->Edit[i].Bound.Top, aPanel->Edit[i].Bound.Right, aPanel->Edit[i].Bound.Bottom, clFrmFace); + inx++; + } + } +} + +void TFloorDisplay::LoadDescp(int aInx, char *p) +{ + unsigned int aAddr, i; + aAddr = dAddr_DescpBuf; + for(i=0; i<32; i++){ + *p = *(volatile unsigned char *)(aAddr + aInx * 32 + i); + p++; + } + *p = '\0'; +} + +void TFloorDisplay::RestoreDescp(int aInx, char *p) +{ + unsigned int aAddr, i; + aAddr = dAddr_DescpBuf; + for(i=0; i<32; i++){ + *(volatile unsigned char *)(aAddr + aInx * 32 + i) = *p; + p++; + } + *p = '\0'; +} + +TGuiMsgReturn TFloorDisplay::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aIndex; + char LastChr; + const char *p; + int i; + if(WhatSet == 0){ + switch(aKey){ + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <2){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + WhatSet = 1; + CtlIndex = 0; + Lv.SelectedLineNum = 0; + Lv.SelectedIndex = 0; + Lv.TopIndex = 0; + RenderContent(); + InitPanel4Global(); + }else + if(CtlIndex == 1){ + WhatSet = 2; + CtlIndex = 0; + Lv.SelectedLineNum = 0; + Lv.SelectedIndex = 0; + Lv.TopIndex = 0; + //RenderContent(); + DrawCaption24Addr(); + LoadDev(); + InitPanel4SetAddr(); + DrawAddrList(); + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + }else + if(CtlIndex == 2){ + WhatSet = 3; + CtlIndex = 0; + Lv.SelectedLineNum = 0; + Lv.SelectedIndex = 0; + Lv.TopIndex = 0; + RenderContent(); + InitPanel4SetDescp(); + aPanel->Edit[0].Selected = 1; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + DrawDescpList(); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + }else + if(WhatSet == 1){ + switch(aKey){ + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex == 0){ + GlobalPrm++; + if(GlobalPrm > 2)GlobalPrm = 0; + if(GlobalPrm == 0){ + aPanel->Edit[0].Str.FromStr(" 全部显示 "); + }else + if(GlobalPrm == 1){ + aPanel->Edit[0].Str.FromStr("按照用户编码显示"); + }else + if(GlobalPrm == 2){ + aPanel->Edit[0].Str.FromStr("相邻楼层编码显示"); + } + aPanel->Edit[0].Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected4Global(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <2){ + CtlIndex++; + Check4Selected4Global(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + GlobalPrm++; + if(GlobalPrm > 2)GlobalPrm = 0; + if(GlobalPrm == 0){ + aPanel->Edit[0].Str.FromStr(" 全部显示 "); + }else + if(GlobalPrm == 1){ + aPanel->Edit[0].Str.FromStr("按照用户编码显示"); + }else + if(GlobalPrm == 2){ + aPanel->Edit[0].Str.FromStr("相邻楼层编码显示"); + } + aPanel->Edit[0].Show(); + }else + if(CtlIndex == 1){ + //Read Here + + }else + if(CtlIndex == 2){ + //Write Here + + } + break; + case VK_RETURN: + WhatSet = 0; + Show(); + InitPanel(); + break; + } + }else + if(WhatSet == 2){ + if(CtlIndex == 0){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + for(i=0; i<6; i++){ + if(aPanel->Edit[i].Selected){ + aPanel->Edit[i].KeyIn(aKey); + aPanel->Edit[i].Show(); + } + } + break; + case VK_UP: + if(Lv.SelectedLineNum > 0){ + AddrAssign[Lv.SelectedIndex].aAssign = aPanel->Edit[Lv.SelectedLineNum].Str.ToInteger(); + aPanel->Edit[Lv.SelectedLineNum].Selected = 0; + aPanel->Edit[Lv.SelectedLineNum].Show(); + Lv.SelectedLineNum--; + Lv.SelectedIndex--; + aPanel->Edit[Lv.SelectedLineNum].Str.FromUInt3Dg(AddrAssign[Lv.SelectedIndex].aAssign); + aPanel->Edit[Lv.SelectedLineNum].Pst = 2; + aPanel->Edit[Lv.SelectedLineNum].Selected = 1; + aPanel->Edit[Lv.SelectedLineNum].Show(); + }else{ + if(Lv.TopIndex > 0){ + Lv.TopIndex -- ; + Lv.SelectedIndex--; + aPanel->Edit[0].Selected = 1; + DrawAddrList(); + } + } + break; + case VK_DOWN: + if(Lv.SelectedLineNum < (dfAddrLineNum-1)){ + if(Lv.SelectedIndex < (Lv.DevCount-1)){ + AddrAssign[Lv.SelectedIndex].aAssign = aPanel->Edit[Lv.SelectedLineNum].Str.ToInteger(); + aPanel->Edit[Lv.SelectedLineNum].Selected = 0; + aPanel->Edit[Lv.SelectedLineNum].Show(); + Lv.SelectedLineNum++; + Lv.SelectedIndex++; + aPanel->Edit[Lv.SelectedLineNum].Str.FromUInt3Dg(AddrAssign[Lv.SelectedIndex].aAssign); + aPanel->Edit[Lv.SelectedLineNum].Pst = 2; + aPanel->Edit[Lv.SelectedLineNum].Selected = 1; + aPanel->Edit[Lv.SelectedLineNum].Show(); + } + }else{ + if(Lv.SelectedIndex < (Lv.DevCount-1)){ + Lv.TopIndex ++; + Lv.SelectedIndex++; + DrawAddrList(); + } + } + break; + case VK_TAB: + //Show Save + CtlIndex = 1; + SubCtlIndex = 1; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 1; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + aPanel->Edit[Lv.SelectedLineNum].Selected = 0; + aPanel->Edit[Lv.SelectedLineNum].Show(); + break; + + } + }else + if(CtlIndex ==1){ + switch(aKey){ + case VK_LEFT: + SubCtlIndex = 0; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + break; + case VK_RIGHT: + SubCtlIndex = 1; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 1; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + break; + case VK_EXECUTE: + if(SubCtlIndex == 0){ + //Reload + }else + if(SubCtlIndex == 1){ + //Save + }else{ + SubCtlIndex = 0; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + } + break; + case VK_TAB: + //Show Save + CtlIndex = 0; + SubCtlIndex = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + aPanel->Edit[Lv.SelectedLineNum].Selected = 1; + aPanel->Edit[Lv.SelectedLineNum].Show(); + break; + } + } + if(aKey == VK_RETURN){ + WhatSet = 0; + Show(); + DrawCaption2(); + InitPanel(); + } + }else + if(WhatSet == 3){ + if(IsExtInput){ + if(aKey == VK_UP){ + IsExtInput = 0; + CnInput.OverPrint(Color); + aPanel->SText[1].Show(); + aPanel->SText[2].Show(); + }else + if(aKey == VK_DOWN){ + IsExtInput = 0; + CnInput.OverPrint(Color); + aPanel->SText[1].Show(); + aPanel->SText[2].Show(); + }else + if(aKey == VK_TAB){ + IsExtInput = 0; + CnInput.OverPrint(Color); + aPanel->SText[1].Show(); + aPanel->SText[2].Show(); + }else + if(aKey == dfKEY_ENCN){ + CnInput.KeyIn(aKey); + if(CnInput.InputMode == 0){ + IsExtInput = 0; + CnInput.OverPrint(Color); + aPanel->SText[1].Show(); + aPanel->SText[2].Show(); + } + }else + if(aKey == VK_RETURN){ + IsExtInput = 0; + CnInput.OverPrint(Color); + aPanel->SText[1].Show(); + aPanel->SText[2].Show(); + }else{ + p = CnInput.KeyIn(aKey); + if(p != nullptr){ + if(pEdit != nullptr){ + if(CnInput.GotChar[0] != '\0'){ + pEdit->Pst = pEdit->Str.Insert(CnInput.GotChar, pEdit->Pst); + pEdit->Str.BrokeFixLen(32); + pEdit->CorrectPst(); + pEdit->Show(); + } + } + } + } + }else{ + if(CtlIndex == 0){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + for(i=0; i<4; i++){ + if(aPanel->Edit[i].Selected){ + aPanel->Edit[i].KeyIn(aKey); + aPanel->Edit[i].Str.BrokeFixLen(32); + aPanel->Edit[i].CorrectPst(); + aPanel->Edit[i].Show(); + } + } + break; + case VK_UP: + RestoreDescpFromEdits(); + if(Lv.SelectedLineNum > 0){ + aPanel->Edit[Lv.SelectedLineNum].Selected = 0; + aPanel->Edit[Lv.SelectedLineNum].SetPstTail(); + aPanel->Edit[Lv.SelectedLineNum].Show(); + Lv.SelectedLineNum--; + Lv.SelectedIndex--; + aPanel->Edit[Lv.SelectedLineNum].Pst = 2; + aPanel->Edit[Lv.SelectedLineNum].Selected = 1; + aPanel->Edit[Lv.SelectedLineNum].SetPstTail(); + aPanel->Edit[Lv.SelectedLineNum].Show(); + }else{ + if(Lv.TopIndex > 0){ + Lv.TopIndex -- ; + Lv.SelectedIndex--; + aPanel->Edit[0].Selected = 1; + DrawDescpList(); + } + } + break; + case VK_DOWN: + RestoreDescpFromEdits(); + if(Lv.SelectedLineNum < (dfDescpLineNum-1)){ + if(Lv.SelectedIndex < (dfDescpMax-1)){ + aPanel->Edit[Lv.SelectedLineNum].Selected = 0; + aPanel->Edit[Lv.SelectedLineNum].SetPstTail(); + aPanel->Edit[Lv.SelectedLineNum].Show(); + Lv.SelectedLineNum++; + Lv.SelectedIndex++; + aPanel->Edit[Lv.SelectedLineNum].Pst = 2; + aPanel->Edit[Lv.SelectedLineNum].Selected = 1; + aPanel->Edit[Lv.SelectedLineNum].SetPstTail(); + aPanel->Edit[Lv.SelectedLineNum].Show(); + } + }else{ + if(Lv.SelectedIndex < (dfDescpMax-1)){ + Lv.TopIndex ++; + Lv.SelectedIndex++; + DrawDescpList(); + } + } + break; + case VK_TAB: + //Show Save + RestoreDescpFromEdits(); + CtlIndex = 1; + SubCtlIndex = 1; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + aPanel->Edit[Lv.SelectedLineNum].Selected = 0; + aPanel->Edit[Lv.SelectedLineNum].Show(); + break; + case dfKEY_ENCN: + IsExtInput = 1; + pEdit = &aPanel->Edit[Lv.SelectedLineNum]; + CnInput.Init(20, 346, 760, 90, 0, 0, clFrmFace); + CnInput.Show(); + break; + + } + }else + if(CtlIndex ==1){ + switch(aKey){ + case VK_LEFT: + if(SubCtlIndex > 1){ + SubCtlIndex--; + aPanel->Edit[11].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + if(SubCtlIndex == 0){ + aPanel->Edit[11].Selected = 1; + aPanel->Edit[11].Show(); + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + }else + if(SubCtlIndex == 1){ + aPanel->Btn[0].Selected = 1; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + } + } + break; + case VK_RIGHT: + if(SubCtlIndex < 2){ + SubCtlIndex++; + aPanel->Edit[11].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + if(SubCtlIndex == 1){ + aPanel->Btn[0].Selected = 1; + aPanel->Edit[11].Show(); + aPanel->Btn[0].Show(); + }else + if(SubCtlIndex == 2){ + aPanel->Btn[1].Selected = 1; + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + } + } + break; + case VK_EXECUTE: + if(SubCtlIndex == 0){ + + }else + if(SubCtlIndex == 1){ + //Reload + ReadFromFlash(); + }else{ + //Save + RestoreDescpFromEdits(); + Write2Flash(); + } + break; + case VK_TAB: + //Show Save + CtlIndex = 0; + SubCtlIndex = 0; + aPanel->Edit[11].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Edit[11].Show(); + aPanel->Btn[0].Show(); + aPanel->Btn[1].Show(); + aPanel->Edit[Lv.SelectedLineNum].Selected = 1; + aPanel->Edit[Lv.SelectedLineNum].Show(); + break; + } + } + if(aKey == VK_RETURN){ + WhatSet = 0; + Show(); + DrawCaption2(); + InitPanel(); + } + } + } + return aMsg; +} + + +void TFloorDisplay::Write2Flash() +{ + unsigned int fAddr, sdAddr; + unsigned int i; + volatile unsigned int aWait, x, wP1; + + wP1 =1; + while(wP1){ + for(aWait=0; aWait<1000000;aWait++); + wP1 = nor_get_busy_state(0); + } + + //Erase 1 * 64K Blocks + fAddr = dFlashAddrFloorDescp; + nor_erase_sector_64k(0,fAddr); + for(aWait=0; aWait<10000000;aWait++); + wP1 =1; + while(wP1){ + for(aWait=0; aWait<1000000;aWait++); + wP1 = nor_get_busy_state(0); + } + + for(x=0; x<32; x++){ + fAddr = dFlashAddrFloorDescp + (x * 256); + sdAddr = dAddr_DescpBuf + (x * 256); + for(i=0; i<64;i++){ + ReadWriteData.D32[i] = *(volatile unsigned int *)(sdAddr + i *4); + } + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + nor_write_page(0, fAddr, ReadWriteData.D8); + for(aWait=0; aWait<2000000; aWait++); + wP1 =1; + while(wP1){ + for(aWait=0; aWait<100000; aWait++); + wP1 = nor_get_busy_state(0); + } + } + + ReadFromFlash(); +} + +void TFloorDisplay::ReadFromFlash() +{ + unsigned int fAddr, sdAddr; + unsigned int x,i; + unsigned int wP1; + volatile unsigned int aWait; + + for(x=0; x<32; x++){ + fAddr = dFlashAddrFloorDescp + + (x * 256); + nor_read_page(0, fAddr, ReadWriteData.D8); + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + sdAddr = dAddr_DescpBuf + (x * 256); + for(i=0; i<64;i++){ + *(volatile unsigned int *)(sdAddr + i*4) = ReadWriteData.D32[i]; + } + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + sdAddr = dAddrSdRam_DescpFloor + (x * 256); + for(i=0; i<64;i++){ + *(volatile unsigned int *)(sdAddr + i*4) = ReadWriteData.D32[i]; + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/FloorDisplay.h b/MyCode/Gui/FloorDisplay.h new file mode 100644 index 0000000..197c7da --- /dev/null +++ b/MyCode/Gui/FloorDisplay.h @@ -0,0 +1,149 @@ +#ifndef FLOORDISPLAY_H_ +#define FLOORDISPLAY_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "EditML.h" +#include "CtlPanel1.h" + +class TFloorDisplay{ + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + + TRect Bound; + TRect Content; + TRect RectPanel; + class TCtlPanel1 *aPanel; + + unsigned char CtlIndex; + unsigned char SubCtlIndex; + unsigned char WhatSet; + + unsigned char PadNum; + unsigned char KeyNum; + unsigned char IsUsing; + unsigned char Type; + unsigned char Ferture; + unsigned char Fon; + + unsigned char GlobalPrm; + + struct{ + unsigned char CtlNum; + unsigned char Path0; + unsigned char Path1; + unsigned char aAssign; + }AddrAssign[256]; + struct{ + short TopIndex; + short SelectedLineNum; + short SelectedIndex; + short DevCount; + }Lv; + short RestoreIndex; + short RestoreEditIndex; + + union{ + unsigned int D32[16]; + char Body[64]; + }Text; + + TEdit *pEdit; + + unsigned char IsExtInput; + + union{ + unsigned char D8[256]; + unsigned int D32[64]; + }ReadWriteData; + public: + TFloorDisplay(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void RenderBackGround(void); + + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void DrawCaption(void); + void DrawCaption2(void); + void DrawCaption24Addr(void); + void DrawCaption24Descp(void); + void Show(); + + void Check4Selected(); + void Check4Selected4Global(); + void Check4Selected4SetAddr(); + void Check4Selected4SetDescp(); + void InitPanel(); + void InitPanel4Global(void); + void InitPanel4SetAddr(); + void InitPanel4SetDescp(); + + void DrawAddrList(); + void DrawDescpList(); + void RestoreDescpFromEdits(); + + void SetEditAddrStart(); + void RestoreEditAddr(); + + void LoadDescp(int aInx, char *p); + void RestoreDescp(int aInx, char *p); + + void LoadDev(); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void DescpBufInit(); + void LoadDescpFromSys(); + + void Write2Flash(); + void ReadFromFlash(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/FwUpgrade.cpp b/MyCode/Gui/FwUpgrade.cpp new file mode 100644 index 0000000..275057f --- /dev/null +++ b/MyCode/Gui/FwUpgrade.cpp @@ -0,0 +1,453 @@ +#include "RuntimeData.h" +#include "FwUpgrade.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const int xFirst = 10; +const int xSec = 160; +const int xThi = 310; +const int xFourth = 460; +const int xFifth = 610; + +void TFwUpgrade::Init() +{ + CtlIndex = 0; + IsShowing = 0; + IsOnGoing = 0; + ReadWrite =0; + + State.Connection =0; + State.Rsv0 =0; + State.Rsv0 =1; + State.Rsv0 =2; + + IsPermission =0; +} + +void TFwUpgrade::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick固件升级"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "USB"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "升级部位"); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 40, 128, 30, 7, clNearWhite, " 连接 ", 4, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[0] + 40, 128, 30, 7, clNearWhite, " 断开 ", 4, clNearBlack); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " 全部 ", 4, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " 主板 ", 4, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " 按键 ", 4, clNearBlack); + TRoundRect::sDrawBySize(xFourth, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " 多线盘 ", 4, clNearBlack); + TRoundRect::sDrawBySize(xFifth, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " 总线盘 ", 4, clNearBlack); + + //TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, " 全部 ", 12, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, " 回路母板 ", 4, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, " 回路卡 ", 4, clNearBlack); + TRoundRect::sDrawBySize(xFourth, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, "联网接口卡", 4, clNearBlack); + TRoundRect::sDrawBySize(xFifth, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, " 存储单元 ", 4, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Data Transmission->Firmware Upgrade"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "USB"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Part Choice"); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 40, 128, 30, 7, clNearWhite, " Connect ", 4, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[0] + 40, 128, 30, 7, clNearWhite, "Disconnect", 4, clNearBlack); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " All ", 4, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, "Main Board", 4, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " Keyboard ", 4, clNearBlack); + TRoundRect::sDrawBySize(xFourth, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, "Direct Pad", 4, clNearBlack); + TRoundRect::sDrawBySize(xFifth, Lv.Grid.Top[1] + 40, 128, 30, 7, clNearWhite, " Bus Pad ", 4, clNearBlack); + + //TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, " 全部 ", 12, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, "Mother Brd", 4, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, " Loop ", 4, clNearBlack); + TRoundRect::sDrawBySize(xFourth, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, "interface ", 4, clNearBlack); + TRoundRect::sDrawBySize(xFifth, Lv.Grid.Top[1] + 80, 128, 30, 7, clNearWhite, "Ext Memory", 4, clNearBlack); + } +} + +void TFwUpgrade::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i6){ + ClearSelected(); + CtlIndex -=4; + Check4Selected(); + }else + if(CtlIndex >3){ + ClearSelected(); + CtlIndex =1; + Check4Selected(); + }else + if(CtlIndex >1){ + ClearSelected(); + CtlIndex -=2; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex <2){ + ClearSelected(); + CtlIndex +=2; + Check4Selected(); + }else + if(CtlIndex <3){ + ClearSelected(); + CtlIndex =7; + Check4Selected(); + }else + if(CtlIndex <7){ + ClearSelected(); + CtlIndex +=4; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + //Active + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Panel.Top + 12, 600 , 120, 3); + } + }else + if(CtlIndex == 1){ + PermissionCmd = 2; + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Panel.Top + 12, 600 , 120, 2); + } + }else + if(CtlIndex == 2){ + //All + }else + if(CtlIndex == 3){ + //Ctl + }else + if(CtlIndex == 4){ + //Key Pad + }else + if(CtlIndex == 5){ + //DirectCtlBoard + }else + if(CtlIndex == 6){ + //HandCtlBoard + }else + if(CtlIndex == 7){ + //MotherBoard + }else + if(CtlIndex == 8){ + //Port[0..39] + }else + if(CtlIndex == 9){ + //Network Board + }else + if(CtlIndex == 10){ + //Stroge Card + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TFwUpgrade::Task1000Ms() +{ + if(IsShowing){ + /*if(IsRunCmd){ + RunTick++; + + } + if( (StartShowWarning == 0) && (IsSelfChecking == 0) ){ + if(ShowingWarning){ + TextRender_string24(120, 88, clNearBlack, Color, " "); + ShowingWarning = 0; + }else{ + TextRender_string24(120, 88, clNearBlack, Color, "升级期间不要关闭电源"); + ShowingWarning =1; + } + }*/ + } +} + +int TFwUpgrade::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} + + diff --git a/MyCode/Gui/FwUpgrade.h b/MyCode/Gui/FwUpgrade.h new file mode 100644 index 0000000..9c67be3 --- /dev/null +++ b/MyCode/Gui/FwUpgrade.h @@ -0,0 +1,128 @@ +#ifndef FWUPGRADE_H_ +#define FWUPGRADE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TFwUpgrade{ + public: + static constexpr unsigned short hList[12] = {80,126,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 2, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + hList[1] +4, + .Panel.Width = 796, + .Panel.Heigh = 156, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + hList[1] +4 + 156 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + char Text[68]; + + + unsigned char ReadWrite; + unsigned char IsOnGoing; + + struct{ + unsigned char Connection; + unsigned char Rsv0; + unsigned char Rsv1; + unsigned char Rsv2; + }State; + public: + TFwUpgrade(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DelayMs(unsigned int aMs); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + void DrawConnState(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + +#endif + + diff --git a/MyCode/Gui/GraiphDevCfg.cpp b/MyCode/Gui/GraiphDevCfg.cpp new file mode 100644 index 0000000..06c163d --- /dev/null +++ b/MyCode/Gui/GraiphDevCfg.cpp @@ -0,0 +1,682 @@ +#include "RuntimeData.h" +#include "GraphDevCfg.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const int xRs485 = 20; +const int xCan = 160; +const int xActive = 20; +const int xClose = 160; + +void TGraphDevCfg::Init() +{ + IsShowing = 0; + CtlIndex = 0; + OpaState = 0; + + IsPermission =0; + + this->CrtNum = GraphAddr; + if( (this->CrtNum >0) && (this->CrtNum <65) ) { + CrtNumValid = 1; + }else{ + CrtNumValid = 0; + } +} + +void TGraphDevCfg::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick消防控制室图形显示装置"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "接口选择"); + TextRender_string24(Lv.Grid.Left[0] + 210, Lv.Grid.Top[0] +6, clNearWhite, "本机号:"); + TextRender_string24(xRs485 + 30, Lv.Grid.Top[0] + 40, clNearWhite, "RS485"); + TextRender_string24(xCan + 30, Lv.Grid.Top[0] + 40, clNearWhite, "CAN"); + + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "图显地址号"); + TextRender_string24(Lv.Grid.Left[1] + 63, Lv.Grid.Top[1] +40, clNearWhite, "选中后按确定键保存"); + TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "开启", 26, clNearBlack); + TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "关闭", 26, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Local Network->Fire Alram Graphic Display"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Port Type Choice"); + TextRender_string24(Lv.Grid.Left[0] + 210, Lv.Grid.Top[0] +6, clNearWhite, "Local"); + TextRender_string24(xRs485 + 30, Lv.Grid.Top[0] + 40, clNearWhite, "RS485"); + TextRender_string24(xCan + 30, Lv.Grid.Top[0] + 40, clNearWhite, "CAN"); + + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Graphic-ID "); + TextRender_string24(Lv.Grid.Left[1] + 63, Lv.Grid.Top[1] +40, clNearWhite, "Press Key OK To Save"); + TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "Enable", 14, clNearBlack); + TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "Disable", 14, clNearBlack); + } +} + +void TGraphDevCfg::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; iEditCtlNum.Init(Lv.Grid.Left[1] +20, Lv.Grid.Top[1] +36, 36, 32, 0,0, 1, clNearWhite); + IList->EditCtlNum.SetMaxLen(2); + IList->EditCtlNum.TextClear(); + IList->EditCtlNum.Str.FromUInt2Dg(GraphAddr); + IList->EditCtlNum.SetPstTail(); + this->CrtNum = GraphAddr; + if( (this->CrtNum >1) && (this->CrtNum <64) ) { + CrtNumValid = 1; + IList->EditCtlNum.SelectedColor = clBlue; + }else{ + CrtNumValid = 0; + this->CrtNum =0; + IList->EditCtlNum.SelectedColor = clRed; + } + IList->EditCtlNum.Str.FromUInt2Dg(this->CrtNum); + DrawLineType(); + IList->EditCtlNum.Show(); + Check4Selected(); + + ShowSysState(); +} + +void TGraphDevCfg::Show(void) +{ + RenderBackGround(); + DrawSelf(); +} + +void TGraphDevCfg::ShowSysState() +{ + if(LanguageEnCn==0){ + if(GraphUsing){ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] +6, clNearWhite, ItemColor, "目前图显开启"); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] +6, clSilver, ItemColor, "目前图显关闭"); + } + }else{ + if(GraphUsing){ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] +6, clNearWhite, ItemColor, "Graphic Displayer Enabled"); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] +6, clSilver, ItemColor, "Graphic Displayer Disabled"); + } + } +} + +void TGraphDevCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; iEditCtlNum.Init(Lv.Grid.Left[1] +20, Lv.Grid.Top[1] +36, 36, 32, 0,0, 1, clNearWhite); + IList->EditCtlNum.SetMaxLen(2); + IList->EditCtlNum.TextClear(); + IList->EditCtlNum.Str.FromUInt2Dg(GraphAddr); + IList->EditCtlNum.SetPstTail(); + this->CrtNum = GraphAddr; + if( (this->CrtNum >1) && (this->CrtNum <64) ) { + CrtNumValid = 1; + IList->EditCtlNum.SelectedColor = clBlue; + }else{ + CrtNumValid = 0; + this->CrtNum =0; + IList->EditCtlNum.SelectedColor = clRed; + } + IList->EditCtlNum.Str.FromUInt2Dg(this->CrtNum); + DrawLineType(); + IList->EditCtlNum.Show(); + + if(IsPermission){ + PmsIntervene4Gui.ReDraw4GuiRecall(); + }else{ + Check4Selected(); + } + } + ShowSysState(); +} + +void TGraphDevCfg::DrawLineType() +{ + if( GraphLineType == 0){ + TRoundSquare::sDrawBySize(xRs485, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(xCan, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + TRoundSquare::sDrawBySize(xRs485, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(xCan, Lv.Grid.Top[0] + 40, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + } +} + +//______________________________________________________________________________________________________________________________ +void TGraphDevCfg::ClearSelected(void) +{ + switch(CtlIndex){ + case 0: + TRoundSquare::sSelected(xRs485, Lv.Grid.Top[0]+40, dWWidth, dWHeigh, 4, ItemColor); + break; + case 1: + TRoundSquare::sSelected(xCan, Lv.Grid.Top[0]+40, dWWidth, dWHeigh, 4, ItemColor); + break; + case 2: + IList->EditCtlNum.Selected = 0; + IList->EditCtlNum.Show(); + break; + case 3: + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "开启", 26, clNearBlack); + else TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "Enable", 14, clNearBlack); + break; + case 4: + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "关闭", 26, clNearBlack); + else TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[1] + 80, 112, 30, 7, clNearWhite, "Disable", 14, clNearBlack); + break; + default: + + break; + } +} + +void TGraphDevCfg::Check4Selected(void) +{ + switch(CtlIndex){ + case 0: + TRoundSquare::sSelected(xRs485, Lv.Grid.Top[0]+40, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 1: + TRoundSquare::sSelected(xCan, Lv.Grid.Top[0]+40, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 2: + IList->EditCtlNum.Selected = 1; + IList->EditCtlNum.SetPstTail(); + IList->EditCtlNum.Show(); + break; + case 3: + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[1] + 80, 112, 30, 7, clBlue, "开启", 26, clNearWhite); + else TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[1] + 80, 112, 30, 7, clBlue, "Enable", 14, clNearWhite); + break; + case 4: + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[1] + 80, 112, 30, 7, clBlue, "关闭", 26, clNearWhite); + else TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[1] + 80, 112, 30, 7, clBlue, "Disable", 14, clNearWhite); + break; + default: + + break; + } +} + +void TGraphDevCfg::PermissionCmdReturnDraw() +{ + RectFillRender(90, Lv.Grid.Bottom[1] +8, 706, Lv.Grid.Bottom[1] +28 + 140, ContentColor); + Check4Selected(); +} + +void TGraphDevCfg::ShowSta() +{ + if(LanguageEnCn==0){ + if(OpaState ==0){ + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +8, clNearWhite, ContentColor, " "); + }else + if(OpaState ==1){ + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +8, clNearWhite, ContentColor, "配置成功"); + }else + if(OpaState ==2){ + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +8, clNearWhite, ContentColor, "配置失败"); + } + }else{ + if(OpaState ==0){ + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +8, clNearWhite, ContentColor, " "); + }else + if(OpaState ==1){ + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +8, clNearWhite, ContentColor, "Configured OK "); + }else + if(OpaState ==2){ + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +8, clNearWhite, ContentColor, "Failed To Configure"); + } + } +} + +void TGraphDevCfg::ShowSta(unsigned char aSta) +{ + OpaState = aSta; + ShowSta(); +} + +void TGraphDevCfg::PermissionCmdGO() +{ + int i =0; + unsigned char tCrtNum = GraphAddr; + unsigned char tLineType = GraphLineType; + unsigned char tActive = GraphUsing; + if(PermissionCmd == 1){ + //Go Active + WriteCrtCfg(GraphLineType, GraphAddr, 1); + ReadCrtCfg(); + i=1; + }else + if(PermissionCmd == 2){ + //Do Close + WriteCrtCfg(GraphLineType, GraphAddr, 0); + ReadCrtCfg(); + i=2; + }else + if(PermissionCmd == 11){ + //Set Rs485 + WriteCrtCfg(0, GraphAddr, GraphUsing); + ReadCrtCfg(); + i=3; + }else + if(PermissionCmd == 12){ + //Set CAN + WriteCrtCfg(1, GraphAddr, GraphUsing); + ReadCrtCfg(); + i=4; + }else + if(PermissionCmd == 13){ + //Set Crt Num + WriteCrtCfg(GraphLineType, this->CrtNum, GraphUsing); + ReadCrtCfg(); + i=5; + } + if(i){ + if(i == 1){ + if( (tCrtNum == GraphAddr) && (tLineType == GraphLineType) && (1 == GraphUsing) ){ + ShowSta(1); + }else{ + ShowSta(2); + } + ShowSysState(); + }else + if(i == 2){ + if( (tCrtNum == GraphAddr) && (tLineType == GraphLineType) && (0 == GraphUsing) ){ + ShowSta(1); + }else{ + ShowSta(2); + } + ShowSysState(); + }else + if(i == 3){ + if( (tCrtNum == GraphAddr) && (0 == GraphLineType) && (0 == GraphUsing) ){ + ShowSta(1); + }else{ + ShowSta(2); + } + }else + if(i == 4){ + if( (tCrtNum == GraphAddr) && (1 == GraphLineType) && (0 == GraphUsing) ){ + ShowSta(1); + }else{ + ShowSta(2); + } + }else + if(i == 5){ + if( (this->CrtNum == GraphAddr) && (tLineType == GraphLineType) && (tActive == GraphUsing) ){ + ShowSta(1); + }else{ + ShowSta(2); + } + } + + DrawLineType(); + this->CrtNum = GraphAddr; + if( (this->CrtNum >0) && (this->CrtNum <65) ) { + CrtNumValid = 1; + IList->EditCtlNum.SelectedColor = clBlue; + }else{ + CrtNumValid = 0; + this->CrtNum =0; + IList->EditCtlNum.SelectedColor = clRed; + } + IList->EditCtlNum.Str.FromUInt2Dg(this->CrtNum); + DrawLineType(); + IList->EditCtlNum.Show(); + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TGraphDevCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + unsigned int aAddr, HadPrc; + TDMix aFullPath; + int NoOpa =1; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + HadPrc =0; + if( (aKey == VK_LEFT) || (aKey == VK_RIGHT) ){ + if(CtlIndex == 0){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 1){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 3){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 4){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + } + } + if(HadPrc == 0){ + if(CtlIndex == 2){ + IList->EditCtlNum.KeyIn(aKey); + int iVal; + iVal = IList->EditCtlNum.Str.ToInteger(); + if( (iVal <2) || (iVal > 63) ){ + IList->EditCtlNum.SelectedColor = clRed; + CrtNumValid = 0; + this->CrtNum = 99; + }else{ + IList->EditCtlNum.SelectedColor = clBlue; + CrtNumValid = 1; + this->CrtNum = iVal; + } + IList->EditCtlNum.Show(); + } + } + break; + case VK_UP: + if(CtlIndex >0){ + if(CtlIndex == 2){ + if(CrtNumValid){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex--; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex=4; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex <4){ + if(CtlIndex == 2){ + if(CrtNumValid){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + if(CtlIndex == 0){ + PermissionCmd = 11; + if(SystemPermission > 2){ + PermissionCmdGO(); + NoOpa =0; + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[1] + 20, 600 , 140, 3); + NoOpa =0; + } + }else + if(CtlIndex == 1){ + PermissionCmd = 12; + if(SystemPermission > 2){ + PermissionCmdGO(); + NoOpa =0; + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[1] + 20, 600 , 140, 3); + NoOpa =0; + } + } + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + PermissionCmd = 11; + if(SystemPermission > 2){ + PermissionCmdGO(); + NoOpa =0; + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[1] + 20, 600 , 140, 3); + NoOpa =0; + } + }else + if(CtlIndex == 1){ + PermissionCmd = 12; + if(SystemPermission > 2){ + PermissionCmdGO(); + NoOpa =0; + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[1] + 20, 600 , 140, 3); + NoOpa =0; + } + }else + if(CtlIndex == 2){ + if(this->CrtNumValid){ + PermissionCmd = 13; + if(SystemPermission > 2){ + PermissionCmdGO(); + NoOpa =0; + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[1] + 20, 600 , 140, 3); + NoOpa =0; + } + } + }else + if(CtlIndex == 3){ + //Active + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + NoOpa =0; + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[1] + 20, 600 , 140, 3); + NoOpa =0; + } + }else + if(CtlIndex == 4){ + //Close + PermissionCmd = 2; + if(SystemPermission > 2){ + PermissionCmdGO(); + NoOpa =0; + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[1] + 20, 600 , 140, 3); + NoOpa =0; + } + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + if(NoOpa){ + ShowSta(0); + } + } + + return aMsg; +} + +int TGraphDevCfg::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} + +void TGraphDevCfg::WriteCrtCfg(unsigned char aLineType, unsigned char aCrtNum, unsigned char aActive) +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char tData[4]; + int i; + //Read ExistTable + tData[0] = aActive; + tData[1] = aCrtNum; + tData[2] = aLineType; + tData[3] = 0; + aAddr = dEepAddrCrtCfg + 0; + sDelayMs(10); + eeprom_write_byte_via_page(0, aAddr, tData, 4); + sDelayMs(10); +} + +void TGraphDevCfg::ReadCrtCfg() +{ + unsigned int aAddr; + int i; + unsigned char tData[4]; + //Read ExistTable + aAddr = dEepAddrCrtCfg; + sDelayMs(10); + eeprom_read_byte(0, aAddr, tData, 4); + + GraphUsing = tData[0]; + GraphAddr = tData[1]; + GraphLineType = tData[2]; +} + +void TGraphDevCfg::sRecoverSetDefault() +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char tData[4]; + int i; + //Read ExistTable + tData[0] = 0; + tData[1] = 2; + tData[2] = 0; + tData[3] = 0; + aAddr = dEepAddrCrtCfg + 0; + sDelayMs(10); + eeprom_write_byte_via_page(0, aAddr, tData, 4); + sDelayMs(10); + + //Read ExistTable + sDelayMs(10); + eeprom_read_byte(0, aAddr, tData, 4); + + GraphUsing = tData[0]; + GraphAddr = tData[1]; + GraphLineType = tData[2]; +} + + + + + + + + diff --git a/MyCode/Gui/GraphBase.cpp b/MyCode/Gui/GraphBase.cpp new file mode 100644 index 0000000..c89b1f1 --- /dev/null +++ b/MyCode/Gui/GraphBase.cpp @@ -0,0 +1,1065 @@ +#include "ImageData.h" +#include "GraphBase.h" +#include "GraphLow.h" + +void TRect::Set(int aLeft, int aTop, int aRight, int aBottom) +{ + Left=aLeft; + Top=aTop; + Right=aRight; + Bottom=aBottom; + Width=Right-Left+1; + Height=Bottom-Top+1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetBySize(int aLeft, int aTop, int aWidth, int aHeight) +{ + Left=aLeft; + Top=aTop; + Width=aWidth; + Height=aHeight; + Right=Left+Width-1; + Bottom=Top+Height-1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetBy2Point(TPoint aPLT, TPoint aPRB) +{ + Left=aPLT.x; + Top=aPLT.y; + Right=aPRB.x; + Bottom=aPRB.y; + Width=Right-Left+1; + Height=Bottom-Top+1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetLeftTop(int aL, int aT) +{ + SetLeft(aL); + SetTop(aT); + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetLeft(int aL) +{ + Left=aL; + Right=Left+Width-1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetTop(int aT) +{ + Top=aT; + Bottom=Top+Height-1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + + +void TRect::SetRight(int aR) +{ + Right=aR; + Left=Right-Width+1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetBottom(int aB) +{ + Bottom=aB; + Top=Bottom-Height+1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetWidth(int aW) +{ + Width=aW; + Right=Left+Width-1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + +void TRect::SetHeight(int aH) +{ + Height=aH; + Bottom=Top+Height-1; + CenterPoint.x=(Left+Right)/2; + CenterPoint.y=(Top+Bottom)/2; +} + + +void TCircle::Plot4Points(int x, int y) +{ + PixelRender((Center.x + x), (Center.y + y), PenWidth, PenColor); + if (x != 0) PixelRender((Center.x - x), (Center.y + y), PenWidth, PenColor); + if (y != 0) PixelRender((Center.x + x), (Center.y - y), PenWidth, PenColor); + if (x != 0 && y != 0) PixelRender((Center.x - x), (Center.y - y), PenWidth, PenColor); +} + +void TCircle::Plot4PointsFill(int x, int y) +{ + BoxRender2D((Center.x-x), (Center.y+y), (Center.x+x), (Center.y+y), PenColor); + BoxRender2D((Center.x-x), (Center.y-y), (Center.x+x), (Center.y-y), PenColor); +} + + +void TCircle::Plot8Points(int x, int y) +{ + if(BrushStyle) { + Plot4PointsFill(x, y); + if (x != y) Plot4PointsFill(y, x); + }else{ + Plot4Points( x, y); + if (x != y) Plot4Points(y, x); + } +} + +void TCircle::Render(void) //draw circle +{ + int tmp = static_cast(Radius); + int error = (-1 * tmp); + unsigned int x = Radius; + unsigned int y = 0; + + // The following while loop may altered to 'while (x > y)' for a + // performance benefit, as long as a call to 'plot4points' follows + // the body of the loop. This allows for the elimination of the + // '(x != y') test in 'plot8points', providing a further benefit. + // + // For the sake of clarity, this is not shown here. + while (x >= y){ + Plot8Points(x, y); + + error += y; + ++y; + error += y; + + // The following test may be implemented in assembly language in + // most machines by testing the carry flag after adding 'y' to + // the value of 'error' in the previous step, since 'error' + // nominally has a negative value. + if (error >= 0){ + --x; + error -= x; + error -= x; + } + } +} + +//在指定位置画一个指定大小的圆 +//(x,y):中心点 +//r :半径 +void TCircle::Render2(void) +{ + int a,b; + int di; + a=0;b=Radius; + di=3-(Radius<<1); //判断下个点位置的标志 + while(a<=b) + { + PixelRender(Center.x+a,Center.y-b,PenColor); //5 + PixelRender(Center.x+b,Center.y-a,PenColor); //0 + PixelRender(Center.x+b,Center.y+a,PenColor); //4 + PixelRender(Center.x+a,Center.y+b,PenColor); //6 + PixelRender(Center.x-a,Center.y+b,PenColor); //1 + PixelRender(Center.x-b,Center.y+a,PenColor); + PixelRender(Center.x-a,Center.y-b,PenColor); //2 + PixelRender(Center.x-b,Center.y-a,PenColor); //7 + a++; + //Bresenham algorithm + if(di<0)di +=4*a+6; + else + { + di+=10+4*(a-b); + b--; + } + } +} + +void TCircle::sPlot4Points(int cx, int cy, int x, int y, unsigned int aClr) +{ + PixelRender((cx + x), (cy + y), 1, aClr); + if (x != 0) PixelRender((cx - x), (cy + y), 1, aClr); + if (y != 0) PixelRender((cx + x), (cy - y), 1, aClr); + if (x != 0 && y != 0) PixelRender((cx - x), (cy - y), 1, aClr); +} + +void TCircle::sPlot4PointsFill(int cx, int cy, int x, int y, unsigned int aClr) +{ + BoxRender2D((cx-x), (cy+y), (cx+x), (cy+y), aClr); + BoxRender2D((cx-x), (cy-y), (cx+x), (cy-y), aClr); +} + +void TCircle::sPlot8Points(int cx, int cy, int x, int y, unsigned int aClr, int IsFill) +{ + if(IsFill) { + sPlot4PointsFill(cx, cy, x, y, aClr); + if (x != y) sPlot4PointsFill(cx, cy, y, x, aClr); + }else{ + sPlot4Points(cx, cy, x, y, aClr); + if (x != y) sPlot4Points(cx, cy, y, x, aClr); + } +} + +void TCircle::sRender(int ax, int ay, int aR, unsigned int aClr, int IsFill) +{ + int tmp = static_cast(aR); + int error = (-1 * tmp); + unsigned int x = aR; + unsigned int y = 0; + + // The following while loop may altered to 'while (x > y)' for a + // performance benefit, as long as a call to 'plot4points' follows + // the body of the loop. This allows for the elimination of the + // '(x != y') test in 'plot8points', providing a further benefit. + // + // For the sake of clarity, this is not shown here. + while (x >= y){ + sPlot8Points(ax, ay, x, y, aClr, IsFill); + + error += y; + ++y; + error += y; + + // The following test may be implemented in assembly language in + // most machines by testing the carry flag after adding 'y' to + // the value of 'error' in the previous step, since 'error' + // nominally has a negative value. + if (error >= 0){ + --x; + error -= x; + error -= x; + } + } +} + +//在指定位置画一个指定大小的圆 +//(x,y):中心点 +//r :半径 +void TCircle::sRender2(int x, int y, int aR, unsigned int aClr) +{ + int a,b; + int di; + a=0;b=aR; + di=3-(aR<<1); //判断下个点位置的标志 + while(a<=b) + { + PixelRender(x+a,y-b,aClr); //5 + PixelRender(x+b,y-a,aClr); //0 + PixelRender(x+b,y+a,aClr); //4 + PixelRender(x+a,y+b,aClr); //6 + PixelRender(x-a,y+b,aClr); //1 + PixelRender(x-b,y+a,aClr); + PixelRender(x-a,y-b,aClr); //2 + PixelRender(x-b,y-a,aClr); //7 + a++; + //Bresenham algorithm + if(di<0)di +=4*a+6; + else + { + di+=10+4*(a-b); + b--; + } + } +} + + + +void TCircle::Plot4PointsQuadrant(int x, int y, int quadrant) +{ + switch(quadrant) + { + case 0: + if (y != 0) PixelRender((Center.x + x), (Center.y - y), PenWidth, PenColor); + break; + case 1: + PixelRender((Center.x + x), (Center.y + y), PenWidth, PenColor); + break; + case 2: + if (x != 0) PixelRender((Center.x - x), (Center.y + y), PenWidth, PenColor); + break; + case 3: + if (x != 0 && y != 0) PixelRender((Center.x - x),(Center.y - y), PenWidth, PenColor); + break; + } +} + +void TCircle::Plot4PointsFillQuadrant(int x, int y,int quadrant) +{ + switch(quadrant) + { + case 0: + BoxRender2D((Center.x), (Center.y-y), (Center.x+x), (Center.y-y), BrushColor); + break; + case 1: + BoxRender2D((Center.x),(Center.y+y), (Center.x+x), (Center.y+y), BrushColor); + break; + case 2: + BoxRender2D((Center.x-x),(Center.y+y), (Center.x), (Center.y+y), BrushColor); + break; + case 3: + BoxRender2D((Center.x-x),(Center.y-y), (Center.x), (Center.y-y), BrushColor); + break; + } +} + + +void TCircle::Plot8PointsQuadrant(int x, int y, int quadrant) +{ + if(BrushStyle) { + Plot4PointsFillQuadrant(x, y, quadrant); + if (x != y) Plot4PointsFillQuadrant(y, x, quadrant); + }else{ + Plot4PointsFillQuadrant(x, y, quadrant); + if (x != y) Plot4PointsFillQuadrant(y, x, quadrant); + } +} + +void TCircle::RenderQuadrant(int quadrant) //draw circle +{ + int tmp = Radius; + signed int error = (-1 * tmp); + unsigned int x = Radius; + unsigned int y = 0; + + if(!Radius) + { + PixelRender(Center.x, Center.y, PenWidth, PenColor); + return; + } + + // The following while loop may altered to 'while (x > y)' for a + // performance benefit, as long as a call to 'plot4points' follows + // the body of the loop. This allows for the elimination of the + // '(x != y') test in 'plot8points', providing a further benefit. + // + // For the sake of clarity, this is not shown here. + while (x >= y) + { + Plot8PointsQuadrant(x, y, quadrant); + + error += y; + ++y; + error += y; + + // The following test may be implemented in assembly language in + // most machines by testing the carry flag after adding 'y' to + // the value of 'error' in the previous step, since 'error' + // nominally has a negative value. + if (error >= 0) + { + --x; + error -= x; + error -= x; + } + } +} + +void TCircle::sPlot4PointsFillQuadrant(int ax, int ay, int x, int y, int quadrant, u32 aClr) +{ + switch(quadrant) + { + case 0: + BoxRender2D((ax), (ay-y), (ax+x), (ay-y), aClr); + break; + case 1: + BoxRender2D((ax),(ay+y), (ax+x), (ay+y), aClr); + break; + case 2: + BoxRender2D((ax-x),(ay+y), (ax), (ay+y), aClr); + break; + case 3: + BoxRender2D((ax-x),(ay-y), (ax), (ay-y), aClr); + break; + } +} + + +void TCircle::sPlot8PointsQuadrant(int ax, int ay, int x, int y, int quadrant,u32 aClr) +{ + sPlot4PointsFillQuadrant(ax,ay,x, y, quadrant,aClr); + if (x != y) sPlot4PointsFillQuadrant(ax,ay,y, x, quadrant,aClr); +} + +void TCircle::sPlot8PointsFillQuadrant(int ax, int ay, int x, int y, int quadrant, u32 aClr) +{ + sPlot4PointsFillQuadrant(ax,ay,x, y, quadrant,aClr); + if (x != y) sPlot4PointsFillQuadrant(ax,ay,y, x, quadrant,aClr); +} + +void TCircle::sRenderQuadrant(int ax, int ay, int aR, int quadrant, u32 aClr, int IsFill) //draw circle +{ + int tmp = aR; + signed int error = (-1 * tmp); + unsigned int x = aR; + unsigned int y = 0; + + if(!aR) + { + PixelRender(ax, ay, 1, aClr); + return; + } + + // The following while loop may altered to 'while (x > y)' for a + // performance benefit, as long as a call to 'plot4points' follows + // the body of the loop. This allows for the elimination of the + // '(x != y') test in 'plot8points', providing a further benefit. + // + // For the sake of clarity, this is not shown here. + while (x >= y) + { + if(IsFill) + sPlot8PointsFillQuadrant(ax,ay,x, y, quadrant,aClr); + else + sPlot8PointsQuadrant(ax,ay,x, y, quadrant,aClr); + + error += y; + ++y; + error += y; + + // The following test may be implemented in assembly language in + // most machines by testing the carry flag after adding 'y' to + // the value of 'error' in the previous step, since 'error' + // nominally has a negative value. + if (error >= 0) + { + --x; + error -= x; + error -= x; + } + } +} + +void TImageList::SetData(unsigned int aSize, unsigned int aIndex) +{ + unsigned int i,j; + if(aSize == 16){ + + }else + if(aSize == 24){ + + }else + if(aSize == 32){ + + } +} + +void TImageList::LoadFromFlash(unsigned int aSize, unsigned int aIndex) +{ + /* + unsigned int i,j; + if(aSize == 16){ + if(aIndex < dICON16_COUNT){ + for(i=0; i<16; i++){ + for(j=0; j<16; j++){ + Size16[aIndex].HV[i][j] = 0; + } + } + } + }else + if(aSize == 24){ + + }else + if(aSize == 32){ + + }*/ +} + +void TImageList::LoadFromFlash(void) +{ + /* + unsigned int i; + for(i=0;i= yLimit)break; + axL = aLeft; + for(x=0;x<16;x++){ + if(axL >= xLimit){ + z = z + 16 - x; + Ram_addr += 4 * (16-x); + break; + } + if(TranparrentColor != (*(volatile unsigned int *)(z)) ) + *(volatile unsigned int *)(Ram_addr) = (*(volatile unsigned int *)(z)); + z += 4; + Ram_addr += 4; + axL++; + } + Ram_addr += (800 - 16) *4 ; + ayL++; + } + } + }else + if(aSize == 22){ + if(aIndex < dICON16_COUNT){ + + } + }else + if(aSize == 24){ + if(aIndex < dICON24_COUNT){ + z = FLASH_USER_PIC_24X24 + aIndex * FLASH_USER_PIC_24X24_UINT; + TranparrentColor = *(volatile unsigned int *)(z); + Ram_addr = ((aTop - 1) * 800 + aLeft) *4 + LcdBaseAddr; + ayL = aTop; + for(y=0; y<24; y++){ + if(ayL >= yLimit)break; + axL = aLeft; + for(x=0;x<24;x++){ + if(axL >= xLimit){ + z = z + 24 - x; + Ram_addr += 4 * (24-x); + break; + } + if(TranparrentColor != (*(volatile unsigned int *)(z)) ) + *(volatile unsigned int *)(Ram_addr) = (*(volatile unsigned int *)(z)); + z += 4; + Ram_addr += 4; + axL++; + } + Ram_addr += (800 - 24) *4 ; + ayL++; + } + } + }else + if(aSize == 32){ + if(aIndex < dICON32_COUNT){ + z = FLASH_USER_PIC_32X32 + aIndex * FLASH_USER_PIC_32X32_UINT; + TranparrentColor = *(volatile unsigned int *)(z); + Ram_addr = ((aTop - 1) * 800 + aLeft) *4 + LcdBaseAddr; + ayL = aTop; + for(y=0; y<32; y++){ + if(ayL >= yLimit)break; + axL = aLeft; + for(x=0;x<32;x++){ + if(axL >= xLimit){ + z = z + 32 - x; + Ram_addr += 4 * (32-x); + break; + } + if(TranparrentColor != (*(volatile unsigned int *)(z))) + *(volatile unsigned int *)(Ram_addr) = (*(volatile unsigned int *)(z)); + z+=4; + Ram_addr += 4; + axL++; + } + Ram_addr += (800 - 32) *4 ; + ayL++; + } + } + } +} + +unsigned int TImageList::GetSize16Count(void) +{ + return dICON16_COUNT; +} + +unsigned int TImageList::GetSize24Count(void) +{ + return dICON24_COUNT; +} + +unsigned int TImageList::GetSize32Count(void) +{ + return dICON32_COUNT; +} + +void TVScrollBar::sDrawByPoint(int x, int y, int Right, int Bottom, u32 aClr, u32 aBClr, int aItemsCount, int aLineCount, int aTopIndex) +{ + int aW, aH; + int RibbonHeight; + int RibbonBottom; + int RibbonTop; + float f1,f2,f3,f4,f5; + + int CenterPoint; + + if(aItemsCount <1){ + RectFillRender(x, y, Right, Bottom, aBClr); + return; + } + + aW = Right - x +1; + aH = Bottom - y +1; + + VertLineRender(x, y, aH, 0xFF808080); + VertLineRender(Right, y , aH, 0xFF808080); + HorizLineRender(x , y, aW, 0xFF808080); + HorizLineRender(x, Bottom, aW, 0xFF808080); + + if(aItemsCount <= aLineCount){ + RibbonTop = y+1; + RibbonBottom = Bottom - 1; + RibbonHeight = aH - 2; + }else{ + f1 = static_cast(aTopIndex); + f2 = static_cast(aLineCount); + f3 = static_cast(aItemsCount); + f4 = static_cast(aH-2); + f5 = (f1 + (f2/2.0)) / f3 * f4; + CenterPoint = (static_cast(f5)) + y +1; + RibbonHeight = static_cast(f2 / f3 * f4); + if(RibbonHeight < 10)RibbonHeight =10; + if(RibbonHeight > (aH-2) )RibbonHeight = aH-2; + RibbonTop = CenterPoint - RibbonHeight /2 +1; + RibbonBottom = CenterPoint + RibbonHeight /2 +1; + if(RibbonTop <= y){ + RibbonTop = y+1; + RibbonBottom = RibbonTop + RibbonHeight; + if(RibbonBottom > (Bottom-1)){ + RibbonBottom = Bottom-1; + } + } + if(RibbonBottom > (Bottom-1)){ + RibbonBottom = Bottom-1; + RibbonTop = RibbonBottom - RibbonHeight; + if(RibbonTop <= y){ + RibbonTop = y+1; + } + } + } + + //Draw Vert ScrollBar BackGround + RectFillRender(x, y, Right, Bottom, aBClr); + //Draw Vert ScrollBar Ribbon + RectFillRender(x, RibbonTop, Right, RibbonBottom, aClr); + //RectFillRender(x, 90, Right, 160, aClr); +} + +void TVScrollBar::sDrawBySize(int x, int y, int aW, int aH, u32 aClr, u32 aBClr, int aItemsCount, int aLineCount, int aTopIndex) +{ + int Right, Bottom; + + Right = x + aW -1; + Bottom = y + aH -1; + + sDrawByPoint(x, y, Right, Bottom, aClr, aBClr, aItemsCount, aLineCount, aTopIndex); +} + +void TProgressBar::sDrawByPoint(int x, int y, int Right, int Bottom, int aPercent, int aMax, u32 aClr, u32 aBClr, u32 aTClr) +{ + int aW, aH, x1,y1,x2,y2; + float f1,f2,f3,f4; + + aW = Right - x +1; + aH = Bottom - y +1; + + VertLineRender(x, y, aH, 0xFF808080); + VertLineRender(Right, y , aH, 0xFF808080); + HorizLineRender(x , y, aW, 0xFF808080); + HorizLineRender(x, Bottom, aW, 0xFF808080); + + aW = aW-2; + if(aW < 1)aW = 1; + x1 = x+1; + y1 = y+1; + x2 = Right - 1; + y2 = Bottom -1; + f1 = static_cast(aPercent); + f2 = static_cast(aMax); + f3 = static_cast(aW); + f4 = f1 / f2 * f3; + aW = static_cast(f4); + x2 = x1 + aW; + RectFillRender(x1, y1, x2, y2, aClr); + x2 = Right - 1; + x1 = x2 +1; + if(x1 < (Right-1)) + RectFillRender(x1, y1, x2, y2, aBClr); + + x1 = x + (aW / 2) - 18; + y1 = y + ((aH -24) /2); + //TextDigitRender2Right24(x1,y1 ,aTClr, aPercent); + +} + +void TProgressBar::sDrawBySize(int x, int y, int aW, int aH, int aPercent, int aMax, u32 aClr, u32 aBClr, u32 aTClr) +{ + int W, x1,y1,x2,y2; + int Right, Bottom; + + float f1,f2,f3,f4; + + Right = x + aW -1; + Bottom = y + aH -1; + + VertLineRender(x, y, aH, 0xFF808080); + VertLineRender(Right, y , aH, 0xFF808080); + HorizLineRender(x , y, aW, 0xFF808080); + HorizLineRender(x, Bottom, aW, 0xFF808080); + + W = aW-2; + if(W < 1)W = 1; + x1 = x+1; + y1 = y+1; + x2 = Right - 1; + y2 = Bottom -1; + if(aPercent < 1){ + RectFillRender(x1, y1, x2, y2, aBClr); + return; + } + f1 = static_cast(aPercent); + f2 = static_cast(aMax); + f3 = static_cast(W); + f4 = f1 / f2 * f3; + W = static_cast(f4); + x2 = x1 + W; + RectFillRender(x1, y1, x2, y2, aClr); + x2 = Right - 1; + x1 = x2 +1; + if(x1 < (Right-1)) + RectFillRender(x1, y1, x2, y2, aBClr); + + x1 = x + (aW / 2) - 18; + y1 = y + ((aH -24) /2); + //TextDigitRender3Right24(x1,y1 ,aTClr, aPercent); +} + +void TImage::Render(unsigned int xLimit, unsigned int yLimit) +{ + unsigned int x,y,z; + unsigned int Ram_addr; + unsigned int i,j,axL,ayL; + + if(Width > 300)Width = 300; + if(Height == 24){ + z = FLASH_USER_PIC_LOGO24; + TranparrentColor = 0xFF000000; + Ram_addr = ((Top - 1) * 800 + Left) *4 + LcdBaseAddr; + ayL = Top; + for(y=0; y<24; y++){ + if(ayL >= yLimit)break; + axL = Left; + for(x=0;x= xLimit){ + z = z + 24 - x; + Ram_addr += 4 * (24-x); + break; + } + if(TranparrentColor != (*(volatile unsigned int *)(z)) ) + *(volatile unsigned int *)(Ram_addr) = (*(volatile unsigned int *)(z)); + z += 4; + Ram_addr += 4; + axL++; + } + Ram_addr += (800 - Width) *4 ; + ayL++; + } + }else + if(Height == 32){ + z = FLASH_USER_PIC_LOGO32; + TranparrentColor = 0xFF000000; + Ram_addr = ((Top - 1) * 800 + Left) *4 + LcdBaseAddr; + ayL = Top; + for(y=0; y<32; y++){ + if(ayL >= yLimit)break; + axL = Left; + for(x=0;x= xLimit){ + z = z + 32 - x; + Ram_addr += 4 * (32-x); + break; + } + if(TranparrentColor != (*(volatile unsigned int *)(z))) + *(volatile unsigned int *)(Ram_addr) = (*(volatile unsigned int *)(z)); + z+=4; + Ram_addr += 4; + axL++; + } + Ram_addr += (800 - Width) *4 ; + ayL++; + } + } +} + +void TRoundSquare::sDrawBySize(int ax, int ay, int aW, int aH, int RoundR, u32 aClr, int Active) +{ + TPoint Lt, Lb, Rt, Rb; + Lt.x = ax + RoundR; Lt.y = ay + RoundR; + Lb.x = Lt.x; Lb.y = ay + aH -1 - RoundR; + Rt.x = ax + aW -1 - RoundR; Rt.y = Lt.y; + Rb.x = Rt.x; Rb.y = Lb.y; + + TCircle::sRenderQuadrant(Lt.x, Lt.y, RoundR, 3, aClr, 1); + TCircle::sRenderQuadrant(Rt.x, Rt.y, RoundR, 0, aClr, 1); + TCircle::sRenderQuadrant(Lb.x, Lb.y, RoundR, 2, aClr, 1); + TCircle::sRenderQuadrant(Rb.x, Rb.y, RoundR, 1, aClr, 1); + + BoxRender2D((ax), (ay+RoundR-1), (ax+aW-1), (ay+aH-1-RoundR), aClr); + BoxRender2D((ax+RoundR-1), (ay), (ax+aW-1-RoundR), (ay+RoundR-1), aClr); + BoxRender2D((ax+RoundR-1), (ay+aH-1-RoundR), (ax+aW-1-RoundR), (ay+aH-1), aClr); + + if(Active){ + TPoint Gp; + const int PenWidth = (aW * aH) / 200 ; + const int OffSet0 = (aW * aH) / 120; + const int OffSet1 = OffSet0 * 23 / 10; + Gp.x = ax + (aW * 10 / 45); + Gp.y = ay + (aH / 2); + + LineRender(Gp.x, Gp.y, Gp.x +OffSet0, Gp.y +OffSet0, PenWidth, clNearBlack); + LineRender(Gp.x +OffSet0, Gp.y +OffSet0, Gp.x +OffSet0 + OffSet1, Gp.y +OffSet0 - OffSet1, PenWidth, clNearBlack); + } +} + +void TRoundSquare::sSelected(int ax, int ay, int aW, int aH, int aThick, u32 aColor) +{ + int x,y; + const int Thick = aThick; + TPoint rP[4]; + rP[0].x = ax - Thick; rP[0].y = ay -Thick; //Left Top + rP[1].x = ax +aW -1 +1; rP[1].y = rP[0].y; //Right Top + rP[2].x = rP[0].x; rP[2].y = ay + aH -1; //Left Bottom + rP[3].x = rP[1].x; rP[3].y = rP[2].y; //Right Bottom + + for(int i=0; i<4; i++){ + for(x=0; x=StartH; h-=2){ + VertLineRender(x2, y2, h, aClr); + x2++; + y2++; + WidthHasDarw ++; + } + return WidthHasDarw; +} + +int TTriangleLeftRight::sDrawLeftByHight(int x, int y, int aH, unsigned int aClr) +{ + int x2,y2,IsOdd; + int WidthHasDarw; + int StartH; + if(aH & 0x00000001){ + StartH =1; + IsOdd = 1; + y2 = y + (aH/2); + }else{ + StartH =2; + IsOdd = 0; + y2 = y + (aH/2) -1; + } + WidthHasDarw = 0; + + x2 = x; + for(int h=StartH; h<=aH; h+=2){ + VertLineRender(x2, y2, h, aClr); + y2--; + x2++; + WidthHasDarw ++; + } + + WidthHasDarw += aH /5; + return WidthHasDarw; +} + +int TTriangleLeftRight::sDrawRightByHight(int x, int y, int aH, unsigned int aClr) +{ + int x2,y2,IsOdd; + int WidthHasDarw; + int StartH; + if(aH & 0x00000001){ + StartH =1; + IsOdd = 1; + y2 = y + (aH/2); + }else{ + StartH =2; + IsOdd = 0; + y2 = y + (aH/2) -1; + } + WidthHasDarw = 0; + + x2 = x; + y2 = y; + for(int h=aH; h>=StartH; h-=2){ + VertLineRender(x2, y2, h, aClr); + x2++; + y2++; + WidthHasDarw ++; + } + return WidthHasDarw; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/GraphBase.h b/MyCode/Gui/GraphBase.h new file mode 100644 index 0000000..21c7637 --- /dev/null +++ b/MyCode/Gui/GraphBase.h @@ -0,0 +1,197 @@ +#ifndef GRAPHBASE_H_ +#define GRAPHBASE_H_ + +#include "gType.h" +#include "GraphLow.h" + +#define dmClear 0 +#define dmSolid 1 + +#define dICON16_COUNT 32 +#define dICON24_COUNT 24 +#define dICON32_COUNT 4 + +typedef enum +{ + CENTER = 0x01, // Center mode + RIGHT = 0x02, // Right mode + LEFT = 0x03 // Left mode +}Tdraw_string_aline_mode; + +typedef struct{ + int x; + int y; +}TPoint; + +typedef struct{ + float x; + float y; +}T2DPoint; + +typedef enum{ + bvNone = 0, + bvLowered, + bvRaised, + bvSpace +}TBvStyle; + +class TRect{ + public: + int Left; + int Top; + int Right; + int Bottom; + int Width; + int Height; + TPoint CenterPoint; + + public: + void Set(int aLeft, int aTop, int aRight, int aBottom); + void SetBySize(int aLeft, int aTop, int aWidth, int aHeight); + void SetBy2Point(TPoint aPLT, TPoint aPRB); + void SetLeftTop(int aL, int aT); + void SetLeft(int aL); + void SetTop(int aT); + void SetRight(int aR); + void SetBottom(int aB); + void SetWidth(int aW); + void SetHeight(int aH); +}; + +class TCircle{ + public: + TPoint Center; + u32 Radius; + + int PenWidth; + u32 PenColor; + int BrushStyle; //fsSolid=1; fsClear=0; + u32 BrushColor; + + private: + void Plot4Points(int x, int y); + void Plot4PointsFill(int x, int y); + void Plot8Points(int x, int y); + void Plot4PointsQuadrant(int x, int y, int quadrant); + void Plot4PointsFillQuadrant(int x, int y, int quadrant); + void Plot8PointsQuadrant(int x, int y, int quadrant); + public: + void Set(TPoint aCenter, s16 aRadius); + void SetBySize(int aLeft, int aTop, int aWidth, int aHeight); + + void Render(void); + void Render2(void); + void RenderQuadrant (int quadrant); + + static void sPlot4Points(int cx, int cy, int x, int y, unsigned int aClr); + static void sPlot4PointsFill(int cx, int cy, int x, int y, unsigned int aClr); + static void sPlot8Points(int cx, int cy, int x, int y, unsigned int aClr, int IsFill); + static void sRender(int x, int y, int aR, unsigned int aClr, int IsFill); + static void sRender2(int x, int y, int aR, unsigned int aClr); + + static void sPlot4PointsFillQuadrant(int ax, int ay, int x, int y,int quadrant, u32 aClr); + static void sPlot8PointsFillQuadrant(int ax, int ay, int x, int y, int quadrant, u32 aClr); + static void sPlot8PointsQuadrant(int ax, int ay, int x, int y, int quadrant,u32 aClr); + static void sRenderQuadrant(int ax, int ay, int aR, int quadrant, u32 aClr, int IsFill); //draw circle +}; + +class TImageList{ + public: + unsigned int AddrInFlash; + unsigned int AllDataSize; // N * 4K Bytes + unsigned int DrawMode; // 0 = Clear 1 = Solid + unsigned int TranparrentColor; + + public: + TImageList(void){ + AllDataSize = 102400; + DrawMode = dmClear; + TranparrentColor = 0xFFFFFFFF; + } + void SetData(unsigned int aSize, unsigned int aIndex); + void LoadFromFlash(unsigned int aSize, unsigned int aIndex); + void LoadFromFlash(void); + void ClearAllFlash(void); + void WriteToFlash(unsigned int Index); + + void Render(unsigned int aSize, unsigned int aIndex, unsigned int aLeft, unsigned int aTop); + void Render(unsigned int aSize, unsigned int aIndex, unsigned int aLeft, unsigned int aTop, unsigned int xLimit, unsigned int yLimit); + + unsigned int GetSize16Count(void); + unsigned int GetSize24Count(void); + unsigned int GetSize32Count(void); +}; + +class TImage{ + public: + unsigned int AddrInFlash; + unsigned int AllDataSize; // N * 4K Bytes + unsigned int DrawMode; // 0 = Clear 1 = Solid + unsigned int TranparrentColor; + unsigned int Width; + unsigned int Height; + int Left; + int Top; + public: + TImage(void){ + AllDataSize = 102400; + DrawMode = dmClear; + TranparrentColor = 0xFFFFFFFF; + } + void Init(int x, int y, unsigned int aA, unsigned int aW, unsigned int aH){ + Left = x; + Top = y; + AddrInFlash = aA; + Width = aW; + Height = aH; + } + void Render(unsigned int xLimit, unsigned int yLimit); +}; + + +class TVScrollBar{ + public: + static void sDrawByPoint(int x, int y, int Right, int Bottom, u32 aClr, u32 aBClr, int aItemsCount, int aLineCount, int aTopIndex); + static void sDrawBySize(int x, int y, int aW, int aH, u32 aClr, u32 aBClr, int aItemsCount, int aLineCount, int aTopIndex); +}; + +class TBevel{ + public: + static void DrawRaised(int x, int y, int Right, int Bottom, u32 aClr, u32 aBClr, int aItemsCount, int aLineCount, int aTopIndex); + static void DrawLowered(int x, int y, int Right, int Bottom, u32 aClr, u32 aBClr, int aItemsCount, int aLineCount, int aTopIndex); +}; + +class TRoundBox{ + +}; + +class TCanvas{ + +}; + +class TProgressBar{ + public: + static void sDrawByPoint(int x, int y, int Right, int Bottom, int aPercent, int aMax, u32 aClr, u32 aBClr, u32 aTClr); + static void sDrawBySize(int x, int y, int aW, int aH, int aPercent, int aMax, u32 aClr, u32 aBClr, u32 aTClr); +}; + +class TRoundSquare{ + public: + static void sDrawBySize(int x, int y, int aW, int aH, int RoundR, u32 aClr, int Active); + static void sSelected(int ax, int ay, int aW, int aH, int aThick, u32 aColor); +}; + +class TRoundRect{ + public: + static void sDrawBySize(int x, int y, int aW, int aH, int RoundR, u32 aClr, char *Text, int LeftSpace, u32 TextClr); +}; + +class TTriangleLeftRight{ + public: + static int sDrawByHight(int x, int y, int aH, unsigned int aClr); + static int sDrawLeftByHight(int x, int y, int aH, unsigned int aClr); + static int sDrawRightByHight(int x, int y, int aH, unsigned int aClr); +}; + + +#endif diff --git a/MyCode/Gui/GraphDevCfg.h b/MyCode/Gui/GraphDevCfg.h new file mode 100644 index 0000000..9a094d7 --- /dev/null +++ b/MyCode/Gui/GraphDevCfg.h @@ -0,0 +1,130 @@ +#ifndef GRAPHDEVCFG_H_ +#define GRAPHDEVCFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TGraphDevCfg{ + public: + static constexpr unsigned short hList[12] = {76,116,110,72, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2, + .Panel.Width = 796, + .Panel.Heigh = 174, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2 + 174 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + class TItemList *IList; + unsigned char CtlIndex; + unsigned char OpaState; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char CrtNum; + unsigned char CrtNumValid; + + char Text[68]; + public: + TGraphDevCfg(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + static void sDelayMs(unsigned int aMs); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + void ShowSysState(); + void DrawLineType(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void WriteCrtCfg(unsigned char aLineType, unsigned char aCrtNum, unsigned char aActive); + void ReadCrtCfg(); + + void ShowSta(); + void ShowSta(unsigned char aSta); + + static void sRecoverSetDefault(); + + int ExtRequst(unsigned char Prm); + +}; + + + +#endif + + diff --git a/MyCode/Gui/GraphLow.cpp b/MyCode/Gui/GraphLow.cpp new file mode 100644 index 0000000..73eee23 --- /dev/null +++ b/MyCode/Gui/GraphLow.cpp @@ -0,0 +1,2310 @@ + +#include "stm32h743xx.h" +#include "GraphLow.h" +#include "font.h" +#include "my_font.h" + + +extern "C"{ +#include "extern_C_Include.h" +} + +const char ppp[8] = "测试"; + +const unsigned char *HeadOfLocation; + +typedef unsigned short u16; +typedef unsigned int u32; + +#define dLCD_HORIZ_SIZE 800 +#define dLCD_VERT_SIZE 480 + +static unsigned char text_buf[76]; +volatile static unsigned int FixColor; +volatile static unsigned int *pFixColor; + +const unsigned int LcdBaseAddr = 0xC0000000; +const unsigned int LcdTopAddr = 0XC0177000; +Tltdc_dev LtdcDev; + +void LcdTopFill(unsigned int aClr) +{ + unsigned int i; + unsigned int addr = LcdTopAddr; + for(i=0; i<384000;i++){ + *(volatile unsigned int*)(addr) = aClr; + addr += 4; + } +} + +unsigned int Abs32(signed int num) { + if(num < 0) + num = num * -1; + return num; +} + +void SwapCoord(int *c1, int *c2) +{ + int tmp; + tmp = *c1; + *c1 = *c2; + *c2 = tmp; +} + +int GetFontWidth(int FS) +{ + switch(FS){ + case 7: return 7; + case 11: return 11; + case 14: return 14; + case 17: return 17; + + case 16: return 16; + case 24: return 24; + case 32: return 32; + + default: return 16; + } +} + +int GetFontHeight(int FS) +{ + switch(FS){ + case 7: return 12; + case 11: return 16; + case 14: return 20; + case 17: return 24; + + case 16: return 16; + case 24: return 24; + case 32: return 32; + + default: return 16; + } +} + +void PixelRender(int x, int y, unsigned int aColor) +{ + unsigned int addr; + addr = ((y * 800) + x) *4 + LcdBaseAddr; + *(volatile unsigned int*)(addr) = aColor; +} + + void BoxRender2D(int x1, int y1, int x2, int y2, unsigned int color) +{ + LTDC_Fill(x1,y1,x2,y2, color); + +} + +void PixelRender(int x, int y, int PenWidth, unsigned int PenColor) +{ + unsigned int addr; + if(PenWidth ==1){ + addr = ((y * 800) + x) *4 + LcdBaseAddr; + *(volatile unsigned int*)(addr) = PenColor; + }else{ + int aW, aH; + for(aW=0; aW 1 ) + { + if(x1 > x2) + { + SwapCoord(&x1, &x2); + } + + if(y1 > y2) + { + SwapCoord(&y1, &y2); + } + + x2++; + y2++; + } + + BoxRender2D(x1 ,y1 ,x2 , y2, PenColor); + + return; + } +*/ + if(x1 == x2){ + VertLineRender(x1, y1, y2-y1+1, PenColor); + return; + }else + if(y1 == y2){ + HorizLineRender(x1, y2, x2-x1+1, PenColor); + return; + } + + delta_x = static_cast(Abs32((x2 - x1)) << 1); + delta_y = static_cast(Abs32((y2 - y1)) << 1); + + // if x1 == x2 or y1 == y2, then it does not matter what we set here + ix = ((x2 > x1)?1:-1); + iy = ((y2 > y1)?1:-1); + + PixelRender( x1, y1, PenWidth, PenColor); + + if (delta_x >= delta_y) + { + // error may go below zero + int error = delta_y - (delta_x >> 1); + + while (x1 != x2) + { + if (error >= 0) + { + if (error || (ix > 0)) + { + y1 += iy; + error -= delta_x; + } + // else do nothing + } + // else do nothing + + x1 += ix; + error += delta_y; + + PixelRender( x1, y1, PenWidth, PenColor); + } + } + else + { + // error may go below zero + int error = delta_x - (delta_y >> 1); + + while (y1 != y2) + { + if (error >= 0) + { + if (error || (iy > 0)) + { + x1 += ix; + error -= delta_y; + } + // else do nothing + } + // else do nothing + + y1 += iy; + error += delta_x; + + PixelRender( x1, y1, PenWidth, PenColor); + } + } + + } + +void HorizLineRender(int xpos, int ypos, int length, unsigned int clr) +{ + unsigned short i; + unsigned int ram_addr; + + ram_addr = LcdBaseAddr + ((ypos * 800) + xpos) * 4; + for(i=0; iAHB1ENR|=1<<23; //使能DM2D时钟 + DMA2D->CR=3<<16; //寄存器到存储器模式 + DMA2D->BGPFCCR = 0x00; + DMA2D->FGPFCCR = 0x00; + DMA2D->OPFCCR=0x00; //LCD_PIXFORMAT; //设置颜色格式 LCD_PIXEL_FORMAT_ARGB8888 0X00 + DMA2D->OOR=offline; //设置行偏移 + DMA2D->CR&=~(1<<0); //先停止DMA2D + DMA2D->OMAR=addr; //输出存储器地址 + DMA2D->NLR=(pey-psy)|((pex-psx)<<16); //设定行数寄存器 + DMA2D->OCOLR=FixColor; //设定输出颜色寄存器 + DMA2D->CR|=1<<0; //启动DMA2D + while((DMA2D->ISR&(1<<1))==0) //等待传输完成 + { + timeout++; + if(timeout>0X2FFFFFF)break; //超时退出 + } + DMA2D->IFCR|=1<<1; //清除传输完成标志 + */ + + int x,y,aW,aH; + volatile unsigned int ram_addr; + + if(x1 > x2){ + ram_addr = ((y2 ) * 800 + x2) *4 + LcdBaseAddr; + aW = x1 -x2 + 1; + aH = y1 - y2 + 1; + }else{ + ram_addr = ((y1 ) * 800 + x1) *4 + LcdBaseAddr; + aW = x2 -x1 + 1; + aH = y2 - y1 + 1; + } + + + for(y=0; y LCD_X_SIZE){ + //beyond screen width + // state |= 1; + //} + //if((ypos+16) > LCD_V_SIZE){ + //beyond screen height + // state |= 2; + //} + //if(stete){ + // return state; + //} + + ram_addr = ((ypos - 1) * dLCD_HORIZ_SIZE + xpos) * 4; + + data_x = static_cast((cr - ' ' ) * 8 * 2); + for(y=0;y<16;y++){ + c = 0x80; + for(x=0;x<8;x++){ + if(ascii_8x16[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + c >>=1; + } + c = 0x80; + data_x++; + ram_addr += (dLCD_HORIZ_SIZE - 8) *4 ; + } + return state; +} + +unsigned int lcd_draw_char_8x16(unsigned int xpos, unsigned int ypos, unsigned int clr, unsigned int bClr, char cr) +{ + unsigned int ram_addr; + unsigned int data_x; + unsigned int x,y; + unsigned char c; + unsigned int state = 0; + + //if((xpos+11) > LCD_X_SIZE){ + //beyond screen width + // state |= 1; + //} + //if((ypos+16) > LCD_V_SIZE){ + //beyond screen height + // state |= 2; + //} + //if(stete){ + // return state; + //} + + ram_addr = ((ypos - 1) * dLCD_HORIZ_SIZE + xpos) * 4; + + data_x = static_cast((cr - ' ' ) * 8 * 2); + for(y=0;y<16;y++){ + c = 0x80; + for(x=0;x<8;x++){ + if(ascii_8x16[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; + } + ram_addr += 4; + c >>=1; + } + c = 0x80; + data_x++; + ram_addr += (dLCD_HORIZ_SIZE - 8) *4 ; + } + return state; +} + +void lcd_draw_str_8x16(unsigned int xpos,unsigned int ypos,unsigned int clr, char *pc) +{ + unsigned int text_size = 0; + const char *p_text; + unsigned int xp; + unsigned int i; + + //get text size + p_text = pc; + while (*p_text++) text_size ++ ; + xp = xpos; + if(text_size>1024)return; + for(i=0; i LCD_X_SIZE){ + //beyond screen width + // state |= 1; + //} + //if((ypos+16) > LCD_V_SIZE){ + //beyond screen height + // state |= 2; + //} + //if(stete){ + // return state; + //} + + ram_addr = ((ypos - 1) * dLCD_HORIZ_SIZE + xpos) * 4; + + data_x = static_cast((cr - ' ' ) * 16 * 2); + for(y=0;y<16;y++){ + c = 0x80; + for(x=0;x<8;x++){ + if(ascii_11x16_table[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + c >>=1; + } + c = 0x80; + data_x++; + for(x=0;x<3;x++){ + if(ascii_11x16_table[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + c >>=1; + } + data_x++; + ram_addr += (dLCD_HORIZ_SIZE - 11) *4 ; + } + return state; +} + +void lcd_draw_str_11x16(unsigned int xpos,unsigned int ypos,unsigned int clr,const char *pc) +{ + unsigned int text_size = 0; + const char *p_text; + unsigned int xp; + unsigned int i; + + //get text size + p_text = pc; + while (*p_text++) text_size ++ ; + xp = xpos; + if(text_size>1024)return; + for(i=0; i1024)return; + for(i=0; i LCD_X_SIZE){ + //beyond screen width + // state |= 1; + //} + //if((ypos+20) > LCD_V_SIZE){ + //beyond screen height + // state |= 2; + //} + //if(stete){ + // return state; + //} + + ram_addr = ((ypos - 1) * dLCD_HORIZ_SIZE + xpos) * 4; + + data_x = (unsigned int)((cr - ' ' ) * 20 * 2); + for(y=0;y<20;y++){ + c = 0x80; + for(x=0;x<8;x++){ + if(ascii_14x20_table[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + c >>=1; + } + c = 0x80; + data_x++; + for(x=0;x<6;x++){ + if(ascii_14x20_table[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + c >>=1; + } + data_x++; + ram_addr += (dLCD_HORIZ_SIZE - 14) *4 ; + } + return state; +} + +void lcd_draw_str_14x20(unsigned int xpos,unsigned int ypos, unsigned int clr, const char *pc) +{ + unsigned int text_size = 0; + const char *p_text; + unsigned int xp; + unsigned int i; + + //get text size + p_text = pc; + while (*p_text++) text_size ++ ; + xp = xpos; + if(text_size > 1024)return; + for(i=0; i 1024)return; + for(i=0; i LCD_X_SIZE){ + //beyond screen width + // state |= 1; + //} + //if((ypos+24) > LCD_V_SIZE){ + //beyond screen height + // state |= 2; + //} + //if(stete){ + // return state; + //} + + ram_addr = ((ypos - 1) * dLCD_HORIZ_SIZE + xpos) * 4; + + data_x = static_cast((cr - ' ' ) * 24 * 3); + for(y=0;y<24;y++){ + c = 0x80; + for(x=0;x<8;x++){ + if(ascii_17x24_table[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + //add lint here + c >>=1; + } + c = 0x80; + data_x++; + for(x=0;x<8;x++){ //ascii_17x24_table + if(ascii_17x24_table[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + //add lint here + c >>=1; + } + c = 0x80; + data_x++; + if(1){ + if(ascii_17x24_table[data_x] & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = clr; + }else{ + //ram_x = ~clr; + } + ram_addr += 4; + //add lint here + c >>=1; + } + data_x++; + ram_addr += (dLCD_HORIZ_SIZE - 17) *4 ; + } + return state; +} + +void lcd_draw_str_17x24(unsigned int xpos,unsigned int ypos, unsigned int clr, unsigned char *pc) +{ + unsigned int text_size = 0; + unsigned char *p_text; + unsigned int xp; + unsigned int i; + + //get text size + p_text = pc; + while (*p_text++) text_size ++ ; + xp = xpos; + if(text_size > 1024)return; + for(i=0; i>=1; + } + pbuf++; + c = 0x80; + for(x=0;x<8;x++){ //ascii_17x24_table + if(*pbuf & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; + }else{ + //ram_x = ~clr; + } + ram_addr += 3200; + //add lint here + c >>=1; + } + pbuf++; + c = 0x80; + for(x=0;x<8;x++){ + if(*pbuf & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; + }else{ + //ram_x = ~clr; + } + ram_addr += 3200; + //add lint here + c >>=1; + } + pbuf++; + x1++; + } +} + + +void gui_write_EN2412(unsigned short x1, unsigned short y1, unsigned int CharColor, unsigned int bClr, unsigned char num) +{ + const unsigned char* pbuf; + unsigned int x, y; + unsigned short ix, iy; + unsigned int offset = 0; + + unsigned int ram_addr; + unsigned char c; + + x = x1; + y = y1; + + //num=num-' ';//得到偏移后的值（ASCII字库是从空格开始取模，所以-' '就是对应字符的字库） + offset = (num-' '); + pbuf = &asc2_2412[offset][0]; + + + for(y=0;y<12;y++){ + ram_addr = (y1 * dLCD_HORIZ_SIZE + x1) * 4; + c = 0x80; + for(x=0;x<8;x++){ + if(*pbuf & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; + } + ram_addr += 3200; + //add lint here + c >>=1; + } + pbuf++; + c = 0x80; + for(x=0;x<8;x++){ //ascii_17x24_table + if(*pbuf & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; + } + ram_addr += 3200; + //add lint here + c >>=1; + } + pbuf++; + c = 0x80; + for(x=0;x<8;x++){ + if(*pbuf & c){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; + } + ram_addr += 3200; + //add lint here + c >>=1; + } + pbuf++; + x1++; + } +} + +static unsigned int get_chinese_code24(const char *p) +{ + u32 address; + address=72UL*( ((*p)-15-0xa1)*94 + ((*(p+1))-0xa1) ); + //sFLASH_ReadBuffer(dot, address, 72); + return address; +} + +static unsigned int get_chinese_code24(char *p) +{ + u32 address; + address=72UL*( ((*p)-15-0xa1)*94 + ((*(p+1))-0xa1) ); + //sFLASH_ReadBuffer(dot, address, 72); + return address; +} + +static unsigned int get_chinese_code24(unsigned char *p) +{ + u32 address; + address=72UL*( ((*p)-15-0xa1)*94 + ((*(p+1))-0xa1) ); + //sFLASH_ReadBuffer(dot, address, 72); + return address; +} + +static unsigned int get_C_code24(const char *p) +{ + u32 address; + if((*(p+1)) < 0x7F){ + address=72UL*( ((*p)-0x81)*190 + ((*(p+1))-0x40) ); + }else{ + address=72UL*( ((*p)-0x81)*190 + ((*(p+1))-0x41) ); + } + //sFLASH_ReadBuffer(dot, address, 72); + return address; +} + +static unsigned int get_C_code24(char *p) +{ + u32 address; + if((*(p+1)) < 0x7F){ + address=72UL*( ((*p)-0x81)*190 + ((*(p+1))-0x40) ); + }else{ + address=72UL*( ((*p)-0x81)*190 + ((*(p+1))-0x41) ); + } + //sFLASH_ReadBuffer(dot, address, 72); + return address; +} + +static unsigned int get_C_code24(unsigned char *p) +{ + u32 address; + if((*(p+1)) < 0x7F){ + address=72UL*( ((*p)-0x81)*190 + ((*(p+1))-0x40) ); + }else{ + address=72UL*( ((*p)-0x81)*190 + ((*(p+1))-0x41) ); + } + //sFLASH_ReadBuffer(dot, address, 72); + return address; +} + +void TextRender_1CN24(int x, int y, unsigned int CharColor, const char *p) +{ + const unsigned char* pbuf; + unsigned short ix, iy; + unsigned int ram_addr; + static unsigned int offset = 0; + unsigned char c; + + //if((*p<0xA1) || (*(p+1)< 0xA1)){ + if(1){ + offset = get_C_code24(p); + + HeadOfLocation = (const unsigned char *)Gbk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(iy=0; iy<24; iy++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+8, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++) + { + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+16, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + y++; + } + }else{ + offset = get_chinese_code24( p); + + //______________________________fill location + //HeadOfLocation = Hzk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(ix=0; ix<24; ix++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+8, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+16, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + x++; + } + } +} + +void TextRender_1CN24(int x, int y, unsigned int CharColor, char *p) +{ + const unsigned char* pbuf; + unsigned short ix, iy; + unsigned int ram_addr; + unsigned int offset = 0; + unsigned char c; + + //if((*p<0xA1) || (*(p+1)< 0xA1)){ + if(1){ + offset = get_C_code24(p); + + HeadOfLocation = (const unsigned char *)Gbk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(iy=0; iy<24; iy++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+8, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++) + { + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+16, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + y++; + } + }else{ + offset = get_chinese_code24( p); + + //______________________________fill location + //HeadOfLocation = Hzk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(ix=0; ix<24; ix++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+8, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+16, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + x++; + } + } +} + + +void TextRender_1CN24(int x, int y, unsigned int CharColor, unsigned char *p) +{ + const unsigned char* pbuf; + unsigned short ix, iy; + unsigned int ram_addr; + unsigned int offset = 0; + unsigned char c; + + //if((*p<0xA1) || (*(p+1)< 0xA1)){ + if(1){ + offset = get_C_code24(p); + + HeadOfLocation = (const unsigned char *)Gbk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(iy=0; iy<24; iy++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+8, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++) + { + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+16, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + y++; + } + }else{ + offset = get_chinese_code24( p); + + //______________________________fill location + //HeadOfLocation = Hzk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(ix=0; ix<24; ix++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+8, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + //gui_put_pixel(x, y+iy+16, 0, BackColor); //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + x++; + } + } +} + + + +void TextRender_1CN24(int x, int y, unsigned int CharColor, unsigned int bClr, const char *p) +{ + const unsigned char* pbuf; + unsigned short ix, iy; + unsigned int ram_addr; + unsigned int offset = 0; + unsigned char c; + + //if((*p<0xA1) || (*(p+1)< 0xA1)){ + if(1){ + offset = get_C_code24(p); + + HeadOfLocation = (const unsigned char *)Gbk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(iy=0; iy<24; iy++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++){ + if( (*pbuf & c)==0 ){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + c = 0x80; + for(ix=0; ix<8; ix++) + { + if( (*pbuf & c)==0 ){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 4; + c >>=1; + } + + pbuf++; + y++; + } + }else{ + offset = get_chinese_code24( p); + + //______________________________fill location + //HeadOfLocation = Hzk_24_data; + pbuf = &HeadOfLocation[offset]; + + for(ix=0; ix<24; ix++){ + ram_addr = (y * dLCD_HORIZ_SIZE + x) * 4; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + c = 0x80; + for(iy=0; iy<8; iy++){ + if( (*pbuf & c)==0 ){ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = bClr; //______________________________put pixel here + }else{ + *(volatile unsigned int *)(LcdBaseAddr+ ram_addr) = CharColor; //______________________________put pixel here + } + ram_addr += 3200; + c >>=1; + } + + pbuf++; + x++; + } + } +} + + +void TextRender_string24(int x, int y, unsigned int CharColor, unsigned char* pC) +{ + unsigned char dat; + unsigned char *p; + + p = pC; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN2412(x, y, CharColor, dat); + x+=12; + //gui_write_EN2417(x, y, CharColor, BackColor, dat); + //x+=17; + } + + else//?? + { + TextRender_1CN24(x, y, CharColor, p); + x+=24; + p++; + } + } +} + + +void TextRender_string24(int x, int y, unsigned int CharColor, unsigned int aBClr, unsigned char* pC) +{ + unsigned char dat; + unsigned char *p; + + p = pC; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN2412(x, y, CharColor, aBClr, dat); + x+=12; + //gui_write_EN2417(x, y, CharColor, BackColor, dat); + //x+=17; + } + + else//?? + { + TextRender_1CN24(x, y, CharColor, aBClr, (const char *)(p)); + x+=24; + p++; + } + } +} + +void TextRender_string24(int x, int y, unsigned int CharColor, const char* pC) +{ + unsigned char dat; + const char *p; + + p = pC; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN2412(x, y, CharColor, dat); + x+=12; + //gui_write_EN2417(x, y, CharColor, BackColor, dat); + //x+=17; + } + + else//?? + { + TextRender_1CN24(x, y, CharColor, p); + x+=24; + p++; + } + } +} + +void TextRender_string24(int x, int y, unsigned int CharColor, char* pC) +{ + unsigned char dat; + const char *p; + + p = pC; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN2412(x, y, CharColor, dat); + x+=12; + //gui_write_EN2417(x, y, CharColor, BackColor, dat); + //x+=17; + } + + else//?? + { + TextRender_1CN24(x, y, CharColor, p); + x+=24; + p++; + } + } +} + +void TextRender_string24(int x, int y, unsigned int CharColor, unsigned int bClr, char* pC) +{ + unsigned char dat; + const char *p; + + p = pC; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN2412(x, y, CharColor, bClr, dat); + x+=12; + //gui_write_EN2417(x, y, CharColor, BackColor, dat); + //x+=17; + } + + else//?? + { + TextRender_1CN24(x, y, CharColor, bClr, p); + x+=24; + p++; + } + } +} + +void TextRender_string24(int x, int y, unsigned int CharColor, unsigned int bClr, const char* pC) +{ + unsigned char dat; + const char *p; + + p = pC; + + for(; *p!=0; p++) + { + if(( (unsigned char)*p&0x80)==0)//?? + { + if(*p=='\r')//?? + { + //x=START_X; + continue; + } + else if(*p=='\n')//?? + { + //y+=24; + //if(y > RECT_YMAX-24) + // y=START_Y; + continue; + } + else if(*p=='\1') //?????.? + dat='~'-' '+1; + else if(*p=='\2') //?????.? + dat='~'-' '+2; + else if(*p=='\3') //?????.? + dat='~'-' '+3; + else if(*p=='\4') //?????.? + dat='~'-' '+4; +// else if(*p=='\\') //????? +// { +// p++; +// if(*p=='U') //?????.? +// dat='~'-' '+1; +// else if(*p=='D') //?????.? +// dat='~'-' '+2; +// else if(*p=='L') //?????.? +// dat='~'-' '+3; +// else// if(*p=='R') //?????.? +// dat='~'-' '+4; +// } + else //?????? + dat=*p-0x20; + + dat=*p; + gui_write_EN2412(x, y, CharColor, bClr, dat); + x+=12; + //gui_write_EN2417(x, y, CharColor, BackColor, dat); + //x+=17; + } + + else//?? + { + TextRender_1CN24(x, y, CharColor, bClr, p); + x+=24; + p++; + } + } +} + +void TextDigitRender1Right24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int da; + da = dig % 10; + gui_write_EN2412(x, y, CharColor, da + '0'); +} + +void TextDigitRender1Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int da; + da = dig % 10; + gui_write_EN2412(x, y, CharColor, bClr, da + '0'); +} + +void TextDigitRenderLeft24_1t3(int x, int y, unsigned int CharColor, unsigned int dig) +{ + if(dig > 999)return; + if(dig < 10){ + gui_write_EN2412(x, y, CharColor, dig + '0'); + }else + if(dig < 100){ + TextDigitRender2Right24(x,y,CharColor,dig); + }else{ + TextDigitRender3Right24(x,y,CharColor,dig); + } +} + +void TextDigitRenderLeft24_1t3(int x, int y, unsigned int CharColor, unsigned int BackClr, unsigned int dig) +{ + if(dig > 999)return; + if(dig < 10){ + gui_write_EN2412(x, y, CharColor, BackClr, dig + '0'); + }else + if(dig < 100){ + TextDigitRender2Right24(x,y,CharColor,BackClr,dig); + }else{ + TextDigitRender3Right24(x,y,CharColor,BackClr,dig); + } +} + +void TextDigitRender2_24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 10; + da = dig; + for(i=0; i<2; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender2_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 10; + da = dig; + for(i=0; i<2; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender2Right24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 12; + gui_write_EN2412(x2, y, CharColor, '0'); + } + x2 = x; + Found = 0; + aRatio = 10; + da = dig; + for(i=0; i<2; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + }else{ + if(Le == 0){ + if(i == 1)gui_write_EN2412(x2, y, CharColor, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender2Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 12; + gui_write_EN2412(x2, y, CharColor, '0'); + } + x2 = x; + Found = 0; + aRatio = 10; + da = dig; + for(i=0; i<2; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + }else{ + if(Le == 0){ + gui_write_EN2412(x2, y, CharColor, bClr, ' '); + if(i == 1)gui_write_EN2412(x2, y, CharColor, bClr, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender3_24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 100; + da = dig; + for(i=0; i<3; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender3_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 100; + da = dig; + for(i=0; i<3; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender4_24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 1000; + da = dig; + for(i=0; i<4; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender4_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 1000; + da = dig; + for(i=0; i<4; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender5_24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 10000; + da = dig; + for(i=0; i<5; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender5_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 10000; + da = dig; + for(i=0; i<5; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender6_24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 100000; + da = dig; + for(i=0; i<6; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender6_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 100000; + da = dig; + for(i=0; i<6; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender8_24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 10000000; + da = dig; + for(i=0; i<8; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender8_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + x2 = x; + aRatio = 10000000; + da = dig; + for(i=0; i<8; i++){ + Le = da / aRatio; + da = da % aRatio; + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender3Right24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 24; + gui_write_EN2412(x2, y, CharColor, '0'); + } + x2 = x; + Found = 0; + aRatio = 100; + da = dig; + for(i=0; i<3; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + }else{ + if(Le == 0){ + //if(Found)gui_write_EN2412(x2, y, CharColor, ' '); + if(i == 2)gui_write_EN2412(x2, y, CharColor, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender3Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 0; + gui_write_EN2412(x2, y, CharColor, bClr, ' '); + x2 = x + 12; + gui_write_EN2412(x2, y, CharColor, bClr, ' '); + x2 = x + 24; + gui_write_EN2412(x2, y, CharColor, bClr, '0'); + } + x2 = x; + Found = 0; + aRatio = 100; + da = dig; + for(i=0; i<3; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + }else{ + if(Le == 0){ + gui_write_EN2412(x2, y, CharColor, bClr, ' '); + if(i == 2)gui_write_EN2412(x2, y, CharColor, bClr, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender4Right24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 36; + gui_write_EN2412(x2, y, CharColor, '0'); + return; + } + x2 = x; + Found = 0; + aRatio = 1000; + da = dig; + for(i=0; i<4; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + }else{ + if(Le == 0){ + //if(Found)gui_write_EN2412(x2, y, CharColor, ' '); + if(i == 3)gui_write_EN2412(x2, y, CharColor, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender4Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 36; + gui_write_EN2412(x2, y, CharColor, bClr, '0'); + return; + } + x2 = x; + Found = 0; + aRatio = 1000; + da = dig; + for(i=0; i<4; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + }else{ + if(Le == 0){ + if(i == 3)gui_write_EN2412(x2, y, CharColor, bClr, '0'); + else gui_write_EN2412(x2, y, CharColor, bClr, ' '); + }else{ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender5Right24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 48; + gui_write_EN2412(x2, y, CharColor, '0'); + return; + } + x2 = x; + Found = 0; + aRatio = 10000; + da = dig; + for(i=0; i<5; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + }else{ + if(Le == 0){ + //if(Found)gui_write_EN2412(x2, y, CharColor, ' '); + if(i == 4)gui_write_EN2412(x2, y, CharColor, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender5Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 48; + gui_write_EN2412(x2, y, CharColor, bClr, '0'); + return; + } + x2 = x; + Found = 0; + aRatio = 10000; + da = dig; + for(i=0; i<5; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + }else{ + if(Le == 0){ + if(i == 4)gui_write_EN2412(x2, y, CharColor, bClr, '0'); + else gui_write_EN2412(x2, y, CharColor, bClr, ' '); + }else{ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender6Right24(int x, int y, unsigned int CharColor, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 60; + gui_write_EN2412(x2, y, CharColor, '0'); + return; + } + x2 = x; + Found = 0; + aRatio = 100000; + da = dig; + for(i=0; i<6; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + }else{ + if(Le == 0){ + //if(Found)gui_write_EN2412(x2, y, CharColor, ' '); + if(i == 5)gui_write_EN2412(x2, y, CharColor, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + +void TextDigitRender6Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x + 60; + gui_write_EN2412(x2, y, CharColor, bClr, '0'); + return; + } + x2 = x; + Found = 0; + aRatio = 100000; + da = dig; + for(i=0; i<6; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + }else{ + if(Le == 0){ + if(i == 5)gui_write_EN2412(x2, y, CharColor, bClr, '0'); + else gui_write_EN2412(x2, y, CharColor, bClr, ' '); + }else{ + gui_write_EN2412(x2, y, CharColor, bClr, Le + '0'); + Found = 1; + } + } + aRatio = aRatio / 10; + x2 += 12; + } +} + + +void TextDigitRender5Left24(int x, int y, unsigned int CharColor, unsigned int BackClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x; + gui_write_EN2412(x2, y, CharColor, BackClr, '0'); + x2 += 12; + for(Found=1; Found<5; Found++){ + gui_write_EN2412(x2, y, CharColor, BackClr, ' '); + x2 += 12; + } + return; + } + x2 = x; + Found = 0; + aRatio = 10000; + da = dig; + for(i=0; i<5; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, BackClr, Le + '0'); + Found++; + }else{ + if(Le == 0){ + //if(Found)gui_write_EN2412(x2, y, BackClr, ' '); + if(i == 5)gui_write_EN2412(x2, y, CharColor, BackClr, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, BackClr, Le + '0'); + Found =1; + } + } + aRatio = aRatio / 10; + if(Found)x2 += 12; + } + if(Found <5){ + for(; Found<5; Found++){ + gui_write_EN2412(x2, y, CharColor, BackClr, ' '); + x2 += 12; + } + } +} + + +void TextDigitRender6Left24(int x, int y, unsigned int CharColor, unsigned int BackClr, unsigned int dig) +{ + unsigned int i, da, Le, Ta, x2, aRatio, Found; + if(dig == 0){ + x2 = x; + gui_write_EN2412(x2, y, CharColor, BackClr, '0'); + x2 += 12; + for(Found=1; Found<6; Found++){ + gui_write_EN2412(x2, y, CharColor, BackClr, ' '); + x2 += 12; + } + return; + } + x2 = x; + Found = 0; + aRatio = 100000; + da = dig; + for(i=0; i<6; i++){ + Le = da / aRatio; + da = da % aRatio; + if(Found){ + gui_write_EN2412(x2, y, CharColor, BackClr, Le + '0'); + Found++; + }else{ + if(Le == 0){ + //if(Found)gui_write_EN2412(x2, y, BackClr, ' '); + if(i == 5)gui_write_EN2412(x2, y, CharColor, BackClr, '0'); + }else{ + gui_write_EN2412(x2, y, CharColor, BackClr, Le + '0'); + Found =1; + } + } + aRatio = aRatio / 10; + if(Found)x2 += 12; + } + if(Found <6){ + for(; Found<6; Found++){ + gui_write_EN2412(x2, y, CharColor, BackClr, ' '); + x2 += 12; + } + } +} + +void TextRender(int x1, int y1, const char *p, unsigned int aColor, int aFontSize) +{ + +} + +void TextRenderAscii_20(unsigned int x,unsigned int y, unsigned int clr,const char *pc) +{ + lcd_draw_str_14x20(x,y, clr,pc); +} + +void TextRenderAscii_20(unsigned int x,unsigned int y, unsigned int clr, char *pc) +{ + lcd_draw_str_14x20(x,y, clr,pc); +} + +void TextRenderAscii_16(unsigned int x,unsigned int y, unsigned int clr, const char *pc) +{ + lcd_draw_str_11x16(x,y,clr,pc); +} + +void TextRenderAscii_16(unsigned int x,unsigned int y, unsigned int clr, char *pc) +{ + lcd_draw_str_11x16(x,y,clr,pc); +} + + + + + + diff --git a/MyCode/Gui/GraphLow.h b/MyCode/Gui/GraphLow.h new file mode 100644 index 0000000..b3d77a9 --- /dev/null +++ b/MyCode/Gui/GraphLow.h @@ -0,0 +1,118 @@ +#ifndef GRAPHLOW_H_ +#define GRAPHLOW_H_ + +extern "C"{ + #include "main.h" + #include "internal_flash.h" +} + +//#define Hzk_24_data ((const unsigned char *)(FLASH_USER_FONT_24X24)) +//#define Hzk_24_data ((const unsigned char *)(ADDR_FLASH_SECTOR_0_BANK2)) + +#define Gbk_24_data ((const unsigned char *)(0xC0600000)) + +typedef struct +{ + unsigned int pwidth; //LCD面板的宽度,固定参数,不随显示方向改变,如果为0,说明没有任何RGB屏接入 + unsigned int pheight; //LCD面板的高度,固定参数,不随显示方向改变 + unsigned short hsw; //水平同步宽度 + unsigned short vsw; //垂直同步宽度 + unsigned short hbp; //水平后廊 + unsigned short vbp; //垂直后廊 + unsigned short hfp; //水平前廊 + unsigned short vfp; //垂直前廊 + unsigned char activelayer; //当前层编号:0/1 + unsigned char dir; //0,竖屏;1,横屏; + unsigned short width; //LCD宽度 + unsigned short height; //LCD高度 + unsigned int pixsize; //每个像素所占字节数 +}Tltdc_dev; + +extern const unsigned int LcdBaseAddr; +extern const unsigned int LcdTopAddr; + +extern void LcdTopFill(unsigned int aClr); + +extern unsigned int Abs32(signed int num) ; +extern void SwapCoord(int *c1, int *c2); +extern void PixelRender(int x, int y, unsigned int aColor); +extern void PixelRender(int x, int y, int PenWidth, unsigned int Color); +extern void BoxRender2D(int x1, int y1, int x2, int y2, unsigned int color); +extern void LineRender (int x1,int y1, int x2, int y2, int PenWidth, unsigned int PenColor); //draw line - bresenham algorithm +extern void HorizLineRender(int xpos, int ypos, int length, unsigned int clr); +extern void VertLineRender(int xpos, int ypos, int length, unsigned int clr); +extern void RectRender(int x1, int y1, int x2, int y2,int line_type, unsigned int color); //draw rectangle +extern void RectFillRender(int x1, int y1, int x2, int y2, unsigned int color); + +extern unsigned int lcd_draw_char_8x16(unsigned int xpos, unsigned int ypos, unsigned int clr, unsigned int bClr, char cr); + +extern void gui_write_EN2412(unsigned short x1, unsigned short y1, unsigned int CharColor, unsigned char num); +extern void gui_write_EN2412(unsigned short x1, unsigned short y1, unsigned int CharColor, unsigned int bClr, unsigned char num); +extern void TextRender_1CN24(int x, int y, unsigned int CharColor, const char *p); +extern void TextRender_1CN24(int x, int y, unsigned int CharColor, char *p); +extern void TextRender_1CN24(int x, int y, unsigned int CharColor, unsigned int bClr, const char *p); + +extern void TextRender (int x1, int y1, const char *p, unsigned int aColor, int aFontSize); +extern void TextRender_string24(int x, int y, unsigned int CharColor, char* p); +extern void TextRender_string24(int x, int y, unsigned int CharColor, unsigned char* p); +extern void TextRender_string24(int x, int y, unsigned int CharColor, const char* p); +extern void TextRender_string24(int x, int y, unsigned int CharColor, unsigned int bClr, char* pC); +extern void TextRender_string24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned char* pC); +extern void TextRender_string24(int x, int y, unsigned int CharColor, unsigned int bClr, const char* pC); +extern void TextRenderAscii_20(unsigned int x,unsigned int y, unsigned int clr, char *pc); +extern void TextRenderAscii_20(unsigned int x,unsigned int y, unsigned int clr, const char *pc); +extern void TextRenderAscii_16(unsigned int x,unsigned int y, unsigned int clr, char *pc); +extern void TextRenderAscii_16(unsigned int x,unsigned int y, unsigned int clr, const char *pc); + +extern void TextDigitRenderLeft24_1t3(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRenderLeft24_1t3(int x, int y, unsigned int CharColor, unsigned int BackClr, unsigned int dig); +extern void TextDigitRender1Right24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender1Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender2_24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender2_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender3_24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender3_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender4_24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender4_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender5_24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender5_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender6_24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender6_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender8_24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender8_24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender2Right24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender3Right24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender4Right24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender4Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender5Right24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender5Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender6Right24(int x, int y, unsigned int CharColor, unsigned int dig); +extern void TextDigitRender6Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender2Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender3Right24(int x, int y, unsigned int CharColor, unsigned int bClr, unsigned int dig); +extern void TextDigitRender5Left24(int x, int y, unsigned int CharColor, unsigned int BackClr, unsigned int dig); +extern void TextDigitRender6Left24(int x, int y, unsigned int CharColor, unsigned int BackClr, unsigned int dig); + +extern int GetFontWidth(int FS); +extern int GetFontHeight(int FS); + +extern unsigned int lcd_draw_char_8x16(unsigned int xpos, unsigned int ypos, unsigned int clr, char cr); +extern void lcd_draw_str_8x16(unsigned int xpos,unsigned int ypos,unsigned int clr, char *pc); + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/Gui.cpp b/MyCode/Gui/Gui.cpp new file mode 100644 index 0000000..5cf3c90 --- /dev/null +++ b/MyCode/Gui/Gui.cpp @@ -0,0 +1,520 @@ +#include "Gui.h" + +class TImageList ImageList; +class TItemList ItemList; + +class TMenu MainMenu; + +//Screen Top Panel ____________________________________________________________________________________ +class TPanel PanelOnTop; +class TStaticText STextCaption; +class TIcon IconTop; +class TStaticText STextNewMsg; + +//Screen Bottom Panel __________________________________________________________________________________ +class TPanel PanelOnBottom; +class TStaticText STextAdjust; +class TStaticText STextAllowAuto; +class TStaticText STextMaintain; +class TStaticText STextTimeShow; + +class TIcon IconAdjust; +class TIcon IconAllowAuto; +class TIcon IconMaintain; +//______________________________________________________________________________________________________ + +class TCtlPanel1 CommonPanel; +class TCtlPanelLite CtlPanelLite; + +//______________________________________________________________________________________________________ + +class TListBoxForm ListBoxForm ; +class TListViewDevice ListViewDevice; +class TDevProperty DevProperty; + +class TLiteIconOverView LiteIconOverViewDev; +class TLiteListViewMask LiteListViewMask; +class TRegister Register; +class TRegisterManual RegisterManual; +class TDesignPrmSet DesignPrmSet; +//class TRegisterAdd RegisterAdd; +//class TRegisterAddRemove RegisterAddRemove; +//class TIoPadDefine IoPadDefine; +class TQueryMsg QueryMsg; +class TQueryMessageFire QueryMessageFire; +class TQueryMsgLinkage QueryMsgLinkage; +class TQueryMsgSv QueryMsgSv; +class TQueryMsgFault QueryMsgFault; +class TQueryMsgOperate QueryMsgOperate; +class TDevMask DevMask; +class TXBox aRadioGroup; +class TXBox aRadioGroup2; +class TPrinterSet PrinterSet; +//class TUserSet UserSet; + +class TEventShow EventShow; +class TPageIdle PageIdle; +class TPermissionSet PermissionSet; +class TPrintInf PrintInf; +class TDateTimeCfg DateTimeCfg; +//class TECanNetwork ECanNetwork; +//class TQueryCfg QueryCfg; +class TPasswdChange PasswdChange; +class TCircuitState CircuitState; +class TRootDevVoltage RootDevVoltage; +class TMessageBox MessageBox; +//class TDetectorCurve DetectorCurve; +class TCircuitCfg CircuitCfg; +//class TEpMonitor EpMonitor; +class TDuplicateCheck DuplicateCheck; +//class TAddrAssign AddrAssign; +class TLiteSelfCheck LiteSelfCheck; +class TProjectSet ProjectSet; +class TBusPadLnk BusPadLnk; +class TLinkageProgram LinkageProgram; +class TDirectPadCfg DirectPadCfg; +//class TDisplayPadCfg DisplayPadCfg; +class TfNetworkReg fNetworkReg; +//class TfNetworkRegManual fNetworkRegManual; +//class TfNetworkRegRemove fNetworkRegRemove; +class TuInportExport uInportExport; +class TOnlineCtrl OnlineCtrl; +class TGraphDevCfg GraphDevCfg; +class THwInf HwInf; +class TFwUpgrade FwUpgrade; +class TDevAuthorize DevAuthorize; +class TAuthorizeState AuthorizeState; +class TaBefore aBefore; +class TMaintain Maintain; +class TAllow Allow; +class TBroadcastCfg BroadcastCfg; +class TScreenSaveCfg ScreenSaveCfg; +class TCleanUp CleanUp; +class TAboutUs AboutUs; +class TCheckNormal CheckNormal; +class TDescpWrite DescpWrite; +class TPmsIntervene PmsIntervene; +class TPmsIntervene PmsIntervene4Gui; +class TDevStartStop DevStartStop; +//class TPowerSuplyCfg PowerSuplyCfg; +class TPowerSuplyInf PowerSuplyInf; +class TDeviceSetup DeviceSetup; +class TLanguageCfg LanguageCfg; + +class TRunModeCfg RunModeCfg; +class TPadInf PadInf; +class TLinkageList LinkageList; +class TLnkFecBusCfg LnkFecBusCfg; +class TAreaCfg AreaCfg; +class TUserCodeSet UserCodeSet; +class TUserCodeSetByArea UserCodeSetByArea; +class TCanNetworkInf CanNetworkInf; +class TCanNetworkRegister CanNetworkRegister; +class TCanNetworkMask CanNetworkMask; +class TBlueTooth BlueTooth; +class TWifiConn WifiConn; +class TTransmiteDev TransmiteDev; +class TClearRegistedInf ClearRegistedInf; +class TClearLinkageCfg ClearLinkageCfg; +class TClearDescp ClearDescp; +class TRecoverAll RecoverAll; +//class TSlaveRegByRemote SlaveRegByRemote; +class TDevCount DevCount; +class TTipPopup TipPopup; +class TDevOutputCfg DevOutputCfg; +class TDevSensitiveCfg DevSensitiveCfg; +class TDevVaCfg DevVaCfg; +class TDisplayPadDescpDownload DisplayPadDescpDownload; + +class TDialogStartup DialogStartup; + +class TCnInput CnInput; + + +class TEdit Edit1; +class TButton Button1; + +class THistoryMsg HistoryMsg; + +class TImage ImageLogo24; +class TImage ImageLogo32; + +int IsSelfChecking =0; + +static char TextPwrBat[36]; + +const unsigned int ContentColor = clNearBlack; +const unsigned int CaptionColor = clDarkBlue; +const unsigned int ItemColor = clDarkkGray; +const unsigned int PanelColor = clGray; +const unsigned int SmallPanelColor = clDarkkGray; +const TContentGeometry ContentGeometry = { + .Left = 0, + .Top = 36, + .Width = 800, + .Heigh = 408, + .Right = 800 - 0 -1, + .Bottom = 408 + 36 -1, +}; + +void StateBarReflash(void) +{ + if(RunState == TRunModeCfg::RunModeAdjust){ + if(LanguageEnCn==0)STextAdjust.SetText("调试",24); + else STextAdjust.SetText("TEST",24); + //STextAdjust.Color = clMedOrange; + STextAdjust.TextColor = clRed; + }else + if(RunState == TRunModeCfg::RunModeRun){ + if(LanguageEnCn==0)STextAdjust.SetText("运行",24); + else STextAdjust.SetText("RUN ",24); + //STextAdjust.Color = clFrmFace; + STextAdjust.TextColor = clNearBlack; + }else{ + RunState = TRunModeCfg::RunModeRun; + if(LanguageEnCn==0)STextAdjust.SetText("运行",24); + else STextAdjust.SetText("RUN ",24); + STextAdjust.TextColor = clNearBlack; + //STextAdjust.SetText(" ?? ",24); + //STextAdjust.Color = clFrmFace; + //STextAdjust.TextColor = clMedOrange; + } + IconAdjust.Show(); + STextAdjust.Show(); + + if(AllowAuto){ + if(LanguageEnCn==0)STextAllowAuto.SetText("自动",24); + else STextAllowAuto.SetText("AUTO",24); + STextAllowAuto.TextColor = clNearBlack; + IconAllowAuto.SetActive(); + }else{ + if(LanguageEnCn==0)STextAllowAuto.SetText("自动",24); + else STextAllowAuto.SetText("AUTO",24); + STextAllowAuto.TextColor = clWhiteGray; + IconAllowAuto.SetDeActive(); + } + STextAllowAuto.Show(); + IconAllowAuto.Show(); + + StateBarReflashMaintain(); +} + +void StateBarReflashMaintain(void) +{ + if(IsMaintainTip){ + if(LanguageEnCn==0)STextMaintain.SetText("维保",24); + else STextMaintain.SetText("Maint",24); + STextMaintain.TextColor = clRed; + }else{ + STextMaintain.SetText(" ",24); + STextMaintain.TextColor = clNearBlack; + } + STextMaintain.Show(); + LastMaintainTip = IsMaintainTip; +} + +void StateBarUpDateBatIfForce(int IsForce) +{ + int x, dInt,dDec; + + if( (LiteSelfCheck.IsShowing == 0) || (IsForce) ){ + x = 284; + if(PsBatDataAva){ + if(LanguageEnCn==0)TMyString::sFromStr("备电:", TextPwrBat); + else TMyString::sFromStr("Batt:", TextPwrBat); + dInt = PsBatData.Body.BatVoltage1.D16 / 1000; + dDec = PsBatData.Body.BatVoltage1.D16 / 100 % 10; + TMyString::sAddOn2Dg(dInt, TextPwrBat); + TMyString::sAddOnChar('.', TextPwrBat); + TMyString::sAddOn1Dg(dDec, TextPwrBat); + TMyString::sAddOnStr("V " , TextPwrBat); + + dInt = PsBatData.Body.BatVoltage2.D16 / 1000; + dDec = PsBatData.Body.BatVoltage2.D16 / 100 % 10; + TMyString::sAddOn2Dg(dInt, TextPwrBat); + TMyString::sAddOnChar('.', TextPwrBat); + TMyString::sAddOn1Dg(dDec, TextPwrBat); + TMyString::sAddOnStr("V " , TextPwrBat); + + TMyString::sAddOn3Dg(PsBatData.Body.BatEnerger1, TextPwrBat); + TMyString::sAddOnStr("% ", TextPwrBat); + + TextRender_string24(x,450,clNearBlack, clFrmFace, TextPwrBat ); + }else{ + if(LanguageEnCn==0) TMyString::sFromStr("备电: 无数据 ", TextPwrBat); + else TMyString::sFromStr("Batt: No Data ", TextPwrBat); + TextRender_string24(x,450,clNearBlack, clFrmFace, TextPwrBat ); + } + } +} + +void ShowSelfCheckCtlNum() +{ + unsigned int i, cnt, x; + char Text[8]; + x = 284; + if(LanguageEnCn==0) TMyString::sFromStr("自检区域机 ", TextPwrBat); + else TMyString::sFromStr("Self-Check ", TextPwrBat); + cnt = 0; + for(i=0; i<17; i++){ + if(NwSelfCheckTick[i] ){ + if(cnt <2){ + cnt++; + Text[0] = (i / 10) + '0'; + Text[1] = (i % 10) + '0'; + Text[2] = ' '; + Text[3] = '\0'; + TMyString::sAddOnStr(Text, TextPwrBat); + }else{ + TMyString::sAddOnStr("...", TextPwrBat); + break; + } + } + } + TMyString::sFillFixLen(TextPwrBat,22); + TextRender_string24(x,450,clNearBlack, clFrmFace, TextPwrBat ); +} + +void StateBar_Pwr_SelfCheck() +{ + static unsigned int ShowWhat =0; + static unsigned int itv =0; + if(MainCtl.fData.Split.NetworkMode == 1){ + if(NwIsSelfCheck){ + if(itv>1){ + if(ShowWhat == 0){ + ShowWhat = 1; + ShowSelfCheckCtlNum(); + }else{ + ShowWhat = 0; + StateBarUpDateBatIfForce(0); + } + itv =0; + } + }else{ + if(itv>1){ + itv = 0; + if(ShowWhat){ + ShowWhat = 0; + StateBarUpDateBatIfForce(1); + }else{ + if(PsBatDataHasUpdate){ + PsBatDataHasUpdate = 0; + StateBarUpDateBatIfForce(0); + } + } + } + } + }else{ + ShowWhat = 0; + if(itv>1){ + itv = 0; + if(PsBatDataHasUpdate){ + PsBatDataHasUpdate = 0; + StateBarUpDateBatIfForce(0); + } + } + } + itv++; +} + +void StateBarUpDateBat(int Ava) +{ + PsBatDataHasUpdate = 1; + PsBatDataAva = Ava; + //StateBarUpDateBatIfForce(0); +} + +void StateBarShow(void) +{ + PanelOnBottom.Show(); + StateBarReflash(); +} + +void GuiTopPanel_init(void) +{ + PanelOnTop.Init ( 0, 0, 800, 36, 0, 0, clFrmFace, bvRaised); + IconTop.Init ( 650, 1, 32, 32, 0, 0, 24, clFrmFace); + STextCaption.Init ( 682, 2, 120, 32, 0, 0, clNearBlack, clFrmFace); + STextNewMsg.Init ( 300, 1, 499, 33, 0, 0, clNearBlack, clFrmFace); + + IconTop.IconList = &ImageList; + IconTop.iSize = 24; + IconTop.ActiveImageIndex = 16; + IconTop.DeActiveImageIndex = 16; + IconTop.SetActive(); + + ImageLogo24.Init(705, 6, FLASH_USER_PIC_LOGO24,90,24); + ImageLogo32.Init(675, 2, FLASH_USER_PIC_LOGO32,122,32); +} + +void GuiBottomPanel_init(void) +{ + //Screen Bottom Panel __________________________________________________________ + PanelOnBottom.Init ( 0, 443, 800, 37, 0, 0, clFrmFace, bvRaised); + IconAdjust.Init ( 1, 6, 28, 28, 0, 443, 24, clFrmFace); + STextAdjust.Init ( 25, 3, 56, 33, 0, 443, clNearBlack, clFrmFace); + + IconAllowAuto.Init ( 84, 6, 28, 28, 0, 443, 24, clFrmFace); + STextAllowAuto.Init (112, 3, 56, 31, 0, 443, clNearBlack, clFrmFace); + + //IconAllowManual.Init (168, 6, 28, 28, 0, 443, 24, clFrmFace); + STextMaintain.Init (196, 3, 56, 31, 0, 443, clNearBlack, clFrmFace); + + STextTimeShow.Init (564, 3, 235, 31, 0, 443, clNearBlack, clFrmFace); + + IconAdjust.IconList = &ImageList; + IconAdjust.iSize = 24; + IconAdjust.ActiveImageIndex = 3; + IconAdjust.DeActiveImageIndex = 11; + IconAdjust.SetActive(); + + IconAllowAuto.IconList = &ImageList; + IconAllowAuto.iSize = 24; + IconAllowAuto.ActiveImageIndex = dIcon24_Allow; + IconAllowAuto.DeActiveImageIndex = dIcon24_NotAllow; + IconAllowAuto.SetActive(); + + //IconAllowManual.IconList = &ImageList; + //IconAllowManual.iSize = 24; + //IconAllowManual.ActiveImageIndex = dIcon24_Allow; + //IconAllowManual.DeActiveImageIndex = dIcon24_NotAllow; + //IconAllowManual.SetActive(); + //______________________________________________________________________________ + +} + +void GuiStart(void) +{ + //Init____________________________________________________________________________________________________________________________ + //DescpBuf.Init(); + + //Screen Top Panel _____________________________________________________________ + GuiTopPanel_init(); + //Screen Bottom Panel _____________________________________________________________ + GuiBottomPanel_init(); + + //Menu__________________________________________________________________________ + MainMenu.Init(0,36,799,442); + MainMenu.IconList = &ImageList; + MainMenu.LoadPermission(3); + + + ListViewDevice.Init() ; + + LiteIconOverViewDev.Init(0, 36, 800, 406, 0, 0, clNearWhite); + + //IoPadDefine.Init(0, 36, 800, 406, 0, 0, clNearWhite); + + PageIdle.Init(0, 36, 800, 406, 0, 0, clMedGray); + QueryMsg.Init(0, 36, 800, 406, 0, 0, clMoneyGreen); + + //_____________________________________________________________________________ + ListBoxForm.Init(0, 36, 800, 406, 0, 0, 1, clMoneyGreen) ; + + EventShow.Init(0, 36, 800, 406, 0, 0, 1, clMoneyGreen) ; + EventShow.TryGetMaskData(2,2024); + + Edit1.Init(6,6, 120,30, 0,0,1,clMoneyGreen); + Button1.Init(6,200, 120,30,0,0, 2,clMoneyGreen); + //________________________________________________________________________________________________________________________________ + //Screen Top + PanelOnTop.Show(); + ImageLogo32.Render(800,480); + + PanelOnBottom.Show(); + + StateBarReflash(); + IconAdjust.SetDeActive(); + IconAdjust.Show(); + IconAllowAuto.Show(); + //IconAllowManual.Show(); + + STextAdjust.Show(); + STextAllowAuto.Show(); + STextMaintain.Show(); + + TipPopup.Init(); + TipPopup.ClearTickOnKeyPress(); + + DisplayPadDescpDownload.Init(); +} + +void EventShowOnShowCallBack() +{ + CheckNormal.Hide(); +} + +void GuiRedrawBase() +{ + //________________________________________________________________________________________________________________________________ + //Screen Top + PanelOnTop.Show(); + ImageLogo32.Render(800,480); + + PanelOnBottom.Show(); + StateBarReflash(); + StateBarUpDateBatIfForce(1); +} + +void GuiRedraw(int Prm) +{ + if(TipPopup.IsShow){ + TipPopup.Hide(); + TipPopup.ClearTickOnKeyPress(); + EventShow.MakeFastCheck(); + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + GuiState = guiShowEvent; + PageIdle.Hide(); + EventShow.MakeShow(); + }else{ + GuiState = guiIdle; + EventShow.Hide(); + PageIdle.Show(); + } + }else + if(CheckNormal.IsShowing){ + CheckNormal.ReDraw(); + }else + if(EventShow.IsShowing){ + GuiState = guiShowEvent; + EventShow.MakeShow(); + }else + if(MainMenu.OnAction){ + if(MainMenu.ActiveLevel < 2){ + MainMenu.FullRedraw(); + }else{ + MainMenu.FullRedrawFrm(Prm); + } + }else + if(MainMenu.Active){ + MainMenu.FullRedraw(); + }else + if(PageIdle.IsShowing){ + PageIdle.Show(); + } +} + +int CheckIsRemoteRegFeasible() +{ + if(Register.IsOnGo)return 0; + if(ClearRegistedInf.Eraser.OnGo)return 0; + if(ClearLinkageCfg.Eraser.OnGo)return 0; + if(ClearDescp.Eraser.OnGo)return 0; + if(ProtoC2C.RemoteReq.Reg.IsRequsting)return -1; + return 1; +} + +void SlaveDoRemoteReg() +{ + SlaveInRemoteCtl = 0xB6B6B6B6; + GeneralDev.LcdBlackLightSetOn(); + Register.Init(); + Register.Show4Slave(); + Register.Nw.CtlNum = MainCtl.fData.Split.MyNum; + //Trige to Start Register + Register.SlaveReplyStartState(1); + Register.SlaveRegInit(ProtoC2C.RemoteReq.Reg.RegPath); +} + diff --git a/MyCode/Gui/Gui.h b/MyCode/Gui/Gui.h new file mode 100644 index 0000000..a4879ac --- /dev/null +++ b/MyCode/Gui/Gui.h @@ -0,0 +1,288 @@ +#ifndef GUI_H_ +#define GUI_H_ + +#include "gType.h" +#include "GuiDef.h" +#include "Icon.h" +#include "gvalue.h" +#include "Panel.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "CtlPanelLite.h" +#include "ItemList.h" +#include "TMenu.h" +#include "ListViewDevice.h" +#include "ListBox.h" +#include "HistoryMsg.h" +#include "DevProperty.h" +#include "DeviceDymPrm.h" +#include "LiteIconOverView.h" +#include "LiteListViewMask.h" +#include "Register.h" +#include "RegisterManual.h" +#include "DesignPrmSet.h" +//#include "IoPadDefine.h" +#include "PageIdle.h" +#include "QueryMessage.h" +//#include "QueryMessageFire.h" +//#include "QueryMsgLinkage.h" +//#include "QueryMsgSv.h" +//#include "QueryMsgFault.h" +//#include "QueryMsgOperate.h" +#include "DevMask.h" +#include "XBox.h" +#include "PrinterSet.h" +//#include "UserSet.h" +#include "EventShow.h" +#include "PermissionSet.h" +#include "PrintInf.h" +#include "DateTimeSet.h" +#include "ECanNetwork.h" +#include "QueryCfg.h" +#include "PasswdChange.h" +#include "CircuitState.h" +#include "RootDevVoltage.h" +#include "MessageBox.h" +#include "EpDevState.h" +#include "DetectorCurve.h" +#include "RealTimeData.h" +#include "CircuitCfg.h" +#include "EpMonitor.h" +#include "DuplicateCheck.h" +#include "AddrAssign.h" +#include "LiteSelfCheck.h" +#include "ProjectSet.h" +#include "BusPadLnk.h" +#include "LinkageProgram.h" +#include "DirectPadCfg.h" +#include "DisplayPadCfg.h" +#include "fNetworkReg.h" +#include "fNetworkRegManual.h" +#include "fNetworkRegRemove.h" +#include "uInportExport.h" +#include "OnlineCtrl.h" +#include "GraphDevCfg.h" +#include "SimRun.h" +#include "HwInf.h" +#include "FwUpgrade.h" +#include "DevAuthorize.h" +#include "TAuthorizeState.h" +#include "aBefore.h" +#include "Maintain.h" +#include "Allow.h" +#include "BroadcastCfg.h" +#include "ScreenSaveCfg.h" +#include "CleanUp.h" +#include "AboutUs.h" +#include "CnInput.h" +#include "CheckNormal.h" +#include "DescpWrite.h" +#include "PmsIntervene.h" +#include "DevStartStop.h" +//#include "PowerSuplyCfg.h" +#include "PowerSuplyInf.h" +#include "DeviceSetup.h" +#include "LanguageCfg.h" +#include "RunModeCfg.h" +#include "PadInf.h" +#include "LinkageList.h" +#include "LnkFecBus.h" +#include "AreaCfg.h" +#include "UserCodeSet.h" +#include "UserCodeSetByArea.h" +#include "CanNetworkInf.h" +#include "CanNetworkRegister.h" +#include "CanNetworkMask.h" +#include "BlueTooth.h" +#include "WifiConn.h" +#include "TransmiteDeviceCfg.h" +#include "ClearRegistedInf.h" +#include "ClearLinkageCfg.h" +#include "ClearDescp.h" +#include "RecoverAll.h" +//#include "SlaveRegByRemote.h" +#include "DevCount.h" +#include "TipPopup.h" +#include "DevOutputCfg.h" +#include "DevSensitiveCfg.h" +#include "DialogStartup.h" +#include "DisplayPadDescpDownload.h" +#include "DevVaCfg.h" + +#define dIcon24_Allow 14 +#define dIcon24_NotAllow 5 + +#define GCaptionColor clDeepBlue +#define GCaptionTextColor clNearWhite + + +extern const unsigned int ContentColor; +extern const unsigned int CaptionColor; +extern const unsigned int ItemColor; +extern const unsigned int PanelColor; +extern const unsigned int SmallPanelColor; +extern const TContentGeometry ContentGeometry; + + +extern TImageList ImageList; +extern class TItemList ItemList; + +//GUI___________________________________________________________________________________________________________ +extern class TMenu MainMenu; + + +//Screen Top Panel _________________ +extern class TPanel PanelOnTop; +extern class TStaticText STextCaption; +extern class TIcon IconTop; +//extern class TStaticText STextNewMsg; + +//Screen Bottom Panel ______________ +extern class TPanel PanelOnBottom; +extern class TStaticText STextAdjust; +extern class TStaticText STextAllowAuto; +extern class TStaticText STextAllowAllAuto; +//extern class TStaticText STextAllowManual; +extern class TStaticText STextAllowSplash; +extern class TStaticText STextAllowPrint; +extern class TStaticText STextTimeShow; + +extern class TIcon IconAdjust; +extern class TIcon IconAllowAuto; +extern class TIcon IconAllowAllAuto; +//extern class TIcon IconAllowManual; +extern class TIcon IconAllowSplash; +extern class TIcon IconAllowPrint; + +//_____________________________________ + +extern class TCtlPanel1 CommonPanel; +extern class TCtlPanelLite CtlPanelLite; + +//Property Frm +extern class TLiteIconOverView LiteIconOverViewDev; +extern class TLiteListViewMask LiteListViewMask; +extern class TRegister Register; +extern class TRegisterManual RegisterManual; +extern class TDesignPrmSet DesignPrmSet; +//extern class TIoPadDefine IoPadDefine; +extern class TPageIdle PageIdle; +extern class TQueryMsg QueryMsg; +extern class TQueryMessageFire QueryMessageFire; +extern class TQueryMsgLinkage QueryMsgLinkage; +extern class TQueryMsgSv QueryMsgSv; +extern class TQueryMsgFault QueryMsgFault; +extern class TQueryMsgOperate QueryMsgOperate; +extern class TDevMask DevMask; +extern class TXBox aRadioGroup; +extern class TXBox aRadioGroup2; +extern class TPrinterSet PrinterSet; +//extern class TUserSet UserSet; +extern class TEventShow EventShow; +extern class TPermissionSet PermissionSet; +extern class TPrintInf PrintInf; +extern class TDateTimeCfg DateTimeCfg; +//extern class TECanNetwork ECanNetwork; +//extern class TQueryCfg QueryCfg; +extern class TPasswdChange PasswdChange; +extern class TCircuitState CircuitState; +extern class TRootDevVoltage RootDevVoltage; +extern class TMessageBox MessageBox; +//extern class TDetectorCurve DetectorCurve; +extern class TCircuitCfg CircuitCfg; +//extern class TEpMonitor EpMonitor; +extern class TDuplicateCheck DuplicateCheck; +//extern class TAddrAssign AddrAssign; +extern class TLiteSelfCheck LiteSelfCheck; +extern class TProjectSet ProjectSet; +extern class TBusPadLnk BusPadLnk; +extern class TLinkageProgram LinkageProgram; +extern class TDirectPadCfg DirectPadCfg; +//extern class TDisplayPadCfg DisplayPadCfg; +extern class TfNetworkReg fNetworkReg; +//extern class TfNetworkRegManual fNetworkRegManual; +//extern class TfNetworkRegRemove fNetworkRegRemove; +extern class TuInportExport uInportExport; +extern class TOnlineCtrl OnlineCtrl; +extern class TGraphDevCfg GraphDevCfg; +extern class THwInf HwInf; +extern class TFwUpgrade FwUpgrade; +extern class TDevAuthorize DevAuthorize; +extern class TAuthorizeState AuthorizeState; +extern class TaBefore aBefore; +extern class TMaintain Maintain; +extern class TAllow Allow; +extern class TBroadcastCfg BroadcastCfg; +extern class TScreenSaveCfg ScreenSaveCfg; +extern class TCleanUp CleanUp; +extern class TAboutUs AboutUs; +extern class TCheckNormal CheckNormal; +extern class TDescpWrite DescpWrite; +extern class TPmsIntervene PmsIntervene; +extern class TPmsIntervene PmsIntervene4Gui; +extern class TDevStartStop DevStartStop; +//extern class TPowerSuplyCfg PowerSuplyCfg; +extern class TPowerSuplyInf PowerSuplyInf; +extern class TDeviceSetup DeviceSetup; +extern class TLanguageCfg LanguageCfg; +extern class TRunModeCfg RunModeCfg; +extern class TPadInf PadInf; +extern class TLinkageList LinkageList; +extern class TLnkFecBusCfg LnkFecBusCfg; +extern class TAreaCfg AreaCfg; +extern class TUserCodeSet UserCodeSet; +extern class TUserCodeSetByArea UserCodeSetByArea; +extern class TCanNetworkInf CanNetworkInf; +extern class TCanNetworkRegister CanNetworkRegister; +extern class TCanNetworkMask CanNetworkMask; +extern class TBlueTooth BlueTooth; +extern class TWifiConn WifiConn; +extern class TTransmiteDev TransmiteDev; +extern class TClearRegistedInf ClearRegistedInf; +extern class TClearLinkageCfg ClearLinkageCfg; +extern class TClearDescp ClearDescp; +extern class TRecoverAll RecoverAll; +//extern class TSlaveRegByRemote SlaveRegByRemote; +extern class TDevCount DevCount; +extern class TTipPopup TipPopup; +extern class TDevOutputCfg DevOutputCfg; +extern class TDevSensitiveCfg DevSensitiveCfg; +extern class TDialogStartup DialogStartup; +extern class TDevVaCfg DevVaCfg; +extern class TDisplayPadDescpDownload DisplayPadDescpDownload; + +extern class TCnInput CnInput; + +extern class TImage ImageLogo24; +extern class TImage ImageLogo32; + +extern int IsSelfChecking; + + +//______________________________________________________________________________________________________ + +extern class TListBoxForm ListBoxForm ; +extern class TListViewDevice ListViewDevice; +extern class TDevProperty DevProperty; +extern class THistoryMsg HistoryMsg; + + +extern class TEdit Edit1; +extern class TButton Button1; + +extern void GuiStart(void); +extern void GuiRedrawBase(); +extern void GuiRedraw(int Prm); + +extern void StateBarUpDateBat(int Ava); +extern void StateBar_Pwr_SelfCheck(); + +extern void EventShowOnShowCallBack(); +extern int CheckIsRemoteRegFeasible(); + +extern void SlaveDoRemoteReg(); + +extern void StateBarReflashMaintain(void); + +#endif + diff --git a/MyCode/Gui/GuiDef.h b/MyCode/Gui/GuiDef.h new file mode 100644 index 0000000..dae85cf --- /dev/null +++ b/MyCode/Gui/GuiDef.h @@ -0,0 +1,16 @@ +#ifndef GUIDEF_H_ +#define GUIDEF_H_ + +#define dIcon24_Allow1 13 +#define dIcon24_NotAllow1 12 +#define dIcon24_Allow2 13 +#define dIcon24_NotAllow2 12 + +#define dIcon24_Input_En 16 +#define dIcon24_Input_EnUpCase 17 +#define dIcon24_Input_EnLowCase 18 +#define dIcon24_Input_EnSymbol 19 +#define dIcon24_Input_Cn 20 + +#endif + diff --git a/MyCode/Gui/HwInf.cpp b/MyCode/Gui/HwInf.cpp new file mode 100644 index 0000000..52efd50 --- /dev/null +++ b/MyCode/Gui/HwInf.cpp @@ -0,0 +1,1193 @@ +#include "HwInf.h" + +#define dLineTypeMainCtl 1 +#define dLineTypeMotherBrd 2 +#define dLineTypePort 3 +#define dLineTypeDirectPad 4 +#define dLineTypeBusPad 5 +#define dLineTypeEthNetwork 6 +#define dLineTypeWifi 7 +#define dLineTypeCanNetwork 8 +#define dLineTypePrinter 9 +#define dLineTypeCommBrd 10 + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" +} + +static const short svGridX[4] = {20, 220, 400, 540}; +static const int HwTypeDescpTextLen = 14; +static const int PartNumTextLen = 34; +static const int CountTextLen = 40; +static const int VersionTextLen = 62; +static constexpr char PartNum[16] = "FC7011\0\0"; +static constexpr char Version[16] = "260402ACN\0\0"; + +void THwInf::Init() +{ + IsShow = 0; + Update =0; + StrList.LineSize =256; + StrList.SelectedLine =-1; +} + +void THwInf::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void THwInf::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void THwInf::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn==0) + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "本机->本机信息"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Local->Hardware Info"); + for(int i=0; i= StrList.ItemsCount){ + StrList.DrawTopItem =0; + } + Inx =2; + for(i=StrList.DrawTopItem; iStr[x] = *(volatile unsigned char *)(StrList.Addr4Items + (i * StrList.LineSize) + x); + if(IList->Str[x] == '\0'){ + break; + } + } + IList->Str[67] = '\0'; + + x = Lv.Grid.Left[Inx] + 8; + y = Lv.Grid.Top[Inx] +6; + TextRender_string24(x,y,clNearWhite, ItemColor, IList->Str); + Inx++; + if(Inx >10)break; + } +} + +void THwInf::ClearSelected() +{ + if( (StrList.SelectedLine > -1) && (StrList.SelectedLine < 9) ){ + int Inx = StrList.SelectedLine +2; + RectFillRender(Lv.Grid.Left[Inx], Lv.Grid.Top[Inx], Lv.Grid.Left[Inx] + Lv.Grid.Right[Inx], Lv.Grid.Top[Inx] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[Inx], Lv.Grid.Top[Inx], Lv.Grid.Left[Inx] + 3, Lv.Grid.Bottom[Inx], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[Inx] -3, Lv.Grid.Top[Inx], Lv.Grid.Right[Inx], Lv.Grid.Bottom[Inx], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[Inx], Lv.Grid.Bottom[Inx] -3, Lv.Grid.Right[Inx], Lv.Grid.Bottom[Inx], ItemColor); //draw rectangle + } +} + +void THwInf::DrawSelected() +{ + if( (StrList.SelectedLine > -1) && (StrList.SelectedLine < 9) ){ + int Inx = StrList.SelectedLine +2; + RectFillRender(Lv.Grid.Left[Inx], Lv.Grid.Top[Inx], Lv.Grid.Left[Inx] + Lv.Grid.Right[Inx], Lv.Grid.Top[Inx] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[Inx], Lv.Grid.Top[Inx], Lv.Grid.Left[Inx] + 3, Lv.Grid.Bottom[Inx], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[Inx] -3, Lv.Grid.Top[Inx], Lv.Grid.Right[Inx], Lv.Grid.Bottom[Inx], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[Inx], Lv.Grid.Bottom[Inx] -3, Lv.Grid.Right[Inx], Lv.Grid.Bottom[Inx], clBlue); //draw rectangle + } +} + +void THwInf::LoadData() +{ + Update =1; + QueryPartNum(); + QueryVersion(0xFe,0xFe); + QueryPnAndVer(); +} + +void THwInf::Show(void) +{ + IsShow =1; + RenderBackGround(); + IList->RealtimeData.Reset(); + IList->ReadWriteData.Reset(); + IList->TextOutClear(); + DrawSelf(); + Analy(); + StrList.SelectedLine =0; + StrList.DrawTopItem =0; + DrawText(); + DrawSelected(); + LoadData(); +} + +void THwInf::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + ReDrawInf(); + DrawText(); + DrawSelected(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + DrawSelf(); + DrawText(); + DrawSelected(); + } +} + +//______________________________________________________________________________________________________________________________ + +void THwInf::ReDrawInf() +{ + +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn THwInf::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + + switch(aKey){ + case VK_UP: + if(StrList.ItemsCount >0){ + if(StrList.SelectedLine >0){ + ClearSelected(); + StrList.SelectedLine --; + DrawSelected(); + }else + if(StrList.DrawTopItem > 0){ + StrList.DrawTopItem--; + DrawText(); + DrawSelected(); + } + } + break; + case VK_DOWN: + if(StrList.ItemsCount >0){ + if(StrList.SelectedLine <0){ + StrList.DrawTopItem =0; + StrList.SelectedLine =0; + DrawSelected(); + } + if(StrList.SelectedLine <8){ + if( (StrList.DrawTopItem + StrList.SelectedLine +1) < StrList.ItemsCount){ + ClearSelected(); + StrList.SelectedLine ++; + DrawSelected(); + } + }else{ + if( (StrList.DrawTopItem + 8 +1) < StrList.ItemsCount){ + StrList.DrawTopItem++; + DrawText(); + DrawSelected(); + } + } + } + break; + case VK_RETURN: + IsShow = 0; + aMsg = guiMsgReturn; + break; + } + + return aMsg; +} + +void THwInf::QueryPartNum() +{ + //Inner CAN + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + Len =4; + + for(i=0; i<8; i++){ + TxData[i] = 0; + } + + aIde.BitF.Cmd = cmQueryBoardModel; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, TxData, Len); + + //KeyPadUart + //CommBrdUart + //ExtMemUart + //PrinterUart +} + +void THwInf::QueryVersion(unsigned char aType, unsigned char aInx) +{ + //Query 1.Port 2.MotherBoard 3.BusPad 4.DirectPad + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aPx; + + Len =4; + + for(i=0; i<8; i++){ + TxData[i] = 0; + } + + TxData[1] = aType; + TxData[2] = aInx; + + aIde.BitF.Cmd = cmQueryVer; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, TxData, Len); +} + +void THwInf::QueryPnAndVer() +{ + //KeyPadUart + sys_get_power_ver(0); + sys_get_power_ver(1); + sys_get_power_ver(2); + sys_get_sw_brd_ver(); + sys_get_sw_brd_descp(); + + //CommBrdUart + get_commbrd_ver_modle(); + + //ExtMemUart + ExRecord.GetVerFlag = 1; + ExRecord.GetModleFlag = 1; + //PrinterUart +} + + + +void THwInf::InnerCanPushData(unsigned char aCmd, unsigned char *pData) +{ + unsigned char tHwType, tNum, tInx; + int i,x; + if(IsShow == 0)return; + tHwType = pData[1]; + tNum = pData[2]; + if(aCmd == cmQueryBoardModel){ + tInx = pData[3]; + switch(tHwType){ + case btDirectPad: + if(tInx == 0){ + if(tNum && (tNum<=dDIRECTCTL_MAX_COUNT) ){ + tNum--; + IList->DirectPadOk[tNum] |= 1; + } + }else + if(tInx <5){ + if(tNum && (tNum<=dDIRECTCTL_MAX_COUNT) ){ + tNum--; + tInx--; + for(i=0;i<4;i++) IList->RealtimeData.PnVerDirectPad[tNum][(tInx*4) + i]=pData[i+4]; + } + } + break; + case btBusPad: + if(tInx == 0){ + if(tNum && (tNum<=dDIRECTCTL_MAX_COUNT) ){ + tNum--; + IList->BusPadOk[tNum] |= 1; + } + }else + if(tInx <5){ + if(tNum && (tNum<=dHANDCTL_MAX_COUNT)){ + tNum--; + tInx--; + for(i=0;i<4;i++) IList->RealtimeData.PnVerBusPad[tNum][(tInx*4) + i]=pData[i+4]; + } + } + break; + case btMotherBoard: + if(tInx == 0){ + if(tNum && (tNum<=5) ){ + tNum--; + IList->MotherBrdOk[tNum] |= 1; + } + }else + if(tInx <5){ + if(tNum && (tNum<=5)){ + tNum--; + tInx--; + for(i=0;i<4;i++) IList->PnVerMotherBoard[tNum][(tInx*4) + i]=pData[i+4]; + } + } + break; + case btPort: + if(tInx == 0){ + if(tNum && (tNum<=dPORT_MAX_COUNT) ){ + tNum--; + IList->PortOk[tNum] |= 1; + } + }else + if(tInx <5){ + if(tNum && (tNum<=dPORT_MAX_COUNT)){ + tNum--; + tInx--; + for(i=0;i<4;i++) IList->RealtimeData.PnVerPort[tNum][(tInx*4) + i]=pData[i+4]; + } + } + break; + default:break; + } + Update =1; + }else + if(aCmd == cmQueryVer){ + switch(tHwType){ + case btDirectPad: + if(tNum && (tNum<=dDIRECTCTL_MAX_COUNT)){ + tNum--; + for(i=0;i<5;i++) IList->RealtimeData.PnVerDirectPad[tNum][i+16]=pData[i+3]; + IList->DirectPadOk[tNum] |= 2; + } + break; + case btBusPad: + if(tNum && (tNum<=dHANDCTL_MAX_COUNT)){ + tNum--; + for(i=0;i<5;i++) IList->RealtimeData.PnVerBusPad[tNum][i+16]=pData[i+3]; + IList->BusPadOk[tNum] |= 2; + } + break; + case btMotherBoard: + if(tNum && (tNum<=5)){ + tNum--; + for(i=0;i<5;i++) IList->PnVerMotherBoard[tNum][i+16]=pData[i+3]; + IList->MotherBrdOk[tNum] |= 2; + } + break; + case btPort: + if(tNum && (tNum<=dPORT_MAX_COUNT)){ + tNum--; + for(i=0;i<5;i++) IList->RealtimeData.PnVerPort[tNum][i+16]=pData[i+3]; + IList->PortOk[tNum] |= 2; + } + break; + default:break; + } + Update =1; + } +} + +void THwInf::KeyPadUartPushData(unsigned char aCmd, unsigned char *pData) +{ + unsigned char tHwType, tNum, tLen; + int i,x; + + if(IsShow == 0)return; + tHwType = pData[0]; + tNum = pData[1]; + tLen = pData[2]; + if(aCmd == cmQueryBoardModel){ + switch(tHwType){ + case btKeyPad: + for(i=0;(iPnVerKeyPad[i]=pData[i+3]; + IList->KeyPadOk |= 1; + break; + case btPowerSuply: + + break; + default:break; + } + Update =1; + }else + if(aCmd == cmQueryVer){ + switch(tHwType){ + case btKeyPad: + for(i=0;i<5;i++) IList->PnVerKeyPad[i+16]=pData[i+3]; + IList->KeyPadOk |= 2; + break; + case btPowerSuply: + if( tNum <4 ){ + IList->PnVerPowerSpy[tNum][0] = 'P'; + IList->PnVerPowerSpy[tNum][1] = 'o'; + IList->PnVerPowerSpy[tNum][2] = 'w'; + IList->PnVerPowerSpy[tNum][3] = 'e'; + IList->PnVerPowerSpy[tNum][4] = 'r'; + IList->PnVerPowerSpy[tNum][5] = 'S'; + IList->PnVerPowerSpy[tNum][6] = 'u'; + IList->PnVerPowerSpy[tNum][7] = 'p'; + IList->PnVerPowerSpy[tNum][8] = 'p'; + IList->PnVerPowerSpy[tNum][9] = 'l'; + IList->PnVerPowerSpy[tNum][10] = 'y'; + IList->PnVerPowerSpy[tNum][11] = '\0'; + for(i=0;i<5;i++) IList->PnVerPowerSpy[tNum][i+16]=pData[i+3]; + IList->PowerSpyOk[tNum] =3; + } + break; + default:break; + } + Update =1; + } +} + +void THwInf::CommBrdUartPushData(unsigned char aCmd, unsigned char *pData) +{ + unsigned char tHwType, tNum, tLen; + int i,x; + + if(IsShow == 0)return; + tHwType = pData[0]; + tNum = pData[1]; + tLen = pData[2]; + if(aCmd == cmQueryBoardModel){ + switch(tHwType){ + case btCommPort: + for(i=0;(iPnVerCommBoard[i]=pData[i+3]; + IList->CommBoardOk |= 1; + break; + default:break; + } + Update =1; + }else + if(aCmd == cmQueryVer){ + switch(tHwType){ + case btCommPort: + for(i=0;i<5;i++) IList->PnVerCommBoard[i+16]=pData[i+3]; + IList->CommBoardOk |= 2; + break; + default:break; + } + Update =1; + } +} + +void THwInf::ExtMemUartPushData(unsigned char aCmd, unsigned char *pData) +{ + unsigned char tHwType, tNum, tLen; + int i,x; + if(IsShow == 0)return; + tHwType = pData[0]; + tNum = pData[1]; + tLen = pData[2]; + if(aCmd == cmQueryBoardModel){ + switch(tHwType){ + case btExMem: + for(i=0;(iPnVerExtMem[i]=pData[i+3]; + IList->ExtMemOk |= 1; + break; + default:break; + } + Update =1; + }else + if(aCmd == cmQueryVer){ + switch(tHwType){ + case btExMem: + for(i=0;i<5;i++) IList->PnVerExtMem[i+16]=pData[i+3]; + IList->ExtMemOk |= 2; + break; + default:break; + } + Update =1; + } +} + +void THwInf::PrinterUartPushData(unsigned char aCmd, unsigned char *pData) +{ + if(IsShow == 0)return; + +} + +int THwInf::GetVerText(char *pSource, char *pText) +{ + int i,x; + unsigned char c; + x =0; + for(i=0; i<5;i++){ + c = pSource[i] >> 4; + if(c<10){ + pText[x] = c +'0'; + }else + if(c<11){ + pText[x] = '.'; + }else{ + pText[x] = '\0'; + return x; + } + x++; + c = pSource[i] & 0x0F; + if(c<10){ + pText[x] = c +'0'; + }else + if(c<11){ + pText[x] = '.'; + }else{ + pText[x] = '\0'; + return x; + } + x++; + } + return 10; +} + +void THwInf::Analy() +{ + //dAddrSdRam_HwInf + unsigned int Addr, PnLen, VerLen, PnLenInRam, VerLenInRam; + int i,x,z,IsEq; + int CmpStartLine, MatchLine; + + StrList.LineSize = 256; + StrList.Addr4LinesType = dAddrSdRam_HwInf; + StrList.Addr4ItemsCount = dAddrSdRam_HwInf + (128*4); + StrList.Addr4Items = dAddrSdRam_HwInf + (StrList.LineSize*4); + + for(i=0; i<16384; i++){ + *(volatile unsigned int *)(dAddrSdRam_HwInf + i*4) = 0; + } + + //Clear Lines Type + Addr = dAddrSdRam_HwInf; + for(i=0; i<128; i++){ + *(volatile unsigned int *)(Addr + i*4) = 0; + } + + StrList.ItemsCount =0; + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btDisplay; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr("主控板",IList->Str); + else TMyString::sAddOnStr("Main Board",IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(PartNum, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(Version, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + + //Mother Board + CmpStartLine = StrList.ItemsCount; + for(i=0; i<5; i++){ + if(IList->MotherBrdOk[i] == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerMotherBoard[i][z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerMotherBoard[i][16], IList->StrVer); + MatchLine = -1; + for(x=CmpStartLine; xStrPnInRam[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPnInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + HwTypeDescpTextLen) + z); + if(IList->StrPnInRam[z] == 0)break; + if(IList->StrPnInRam[z] == ' ')break; + } + PnLenInRam = z; + IList->StrVerInRam[10] = '\0'; + for(z=0; z<10; z++){ + IList->StrVerInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + CountTextLen) + z); + if(IList->StrVerInRam[z] == 0)break; + if(IList->StrVerInRam[z] == ' ')break; + } + VerLenInRam = z; + if( (PnLen == PnLenInRam) && (VerLen == VerLenInRam) ){ + IsEq =1; + for(z=0; zStrPnInRam[z] != IList->StrPn[z]){ + IsEq =0; + break; + } + } + if(IsEq){ + for(z=0; zStrVerInRam[z] != IList->StrVer[z]){ + IsEq =0; + break; + } + } + + } + }else{ + IsEq =0; + } + if(IsEq){ + MatchLine = x; + break; + } + } + if(MatchLine > -1){ + z = *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) +1; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) = z; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +0) = z/10%10 + '0'; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +1) = z%10 + '0'; + }else{ + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btMotherBoard; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0) + TMyString::sAddOnStr("回路母板", IList->Str); + else + TMyString::sAddOnStr("Mother Brd", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + } + } + + //Port + CmpStartLine = StrList.ItemsCount; + for(i=0; i<40; i++){ + if(IList->PortOk[i] == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->RealtimeData.PnVerPort[i][z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->RealtimeData.PnVerPort[i][16], IList->StrVer); + MatchLine = -1; + for(x=CmpStartLine; xStrPnInRam[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPnInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + HwTypeDescpTextLen) + z); + if(IList->StrPnInRam[z] == 0)break; + if(IList->StrPnInRam[z] == ' ')break; + } + PnLenInRam = z; + IList->StrVerInRam[10] = '\0'; + for(z=0; z<10; z++){ + IList->StrVerInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + CountTextLen) + z); + if(IList->StrVerInRam[z] == 0)break; + if(IList->StrVerInRam[z] == ' ')break; + } + VerLenInRam = z; + + if( (PnLen == PnLenInRam) && (VerLen == VerLenInRam) ){ + IsEq =1; + for(z=0; zStrPnInRam[z] != IList->StrPn[z]){ + IsEq =0; + break; + } + } + if(IsEq){ + for(z=0; zStrVerInRam[z] != IList->StrVer[z]){ + IsEq =0; + break; + } + } + + } + }else{ + IsEq =0; + } + if(IsEq){ + MatchLine = x; + break; + } + } + if(MatchLine > -1){ + z = *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) +1; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) = z; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +0) = z/10%10 + '0'; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +1) = z%10 + '0'; + }else{ + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btPort; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0) + TMyString::sAddOnStr( "回路卡", IList->Str); + else + TMyString::sAddOnStr( "Loop Board", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + } + } + + //Direct Pad + CmpStartLine = StrList.ItemsCount; + for(i=0; i<20; i++){ + if(IList->DirectPadOk[i] == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->RealtimeData.PnVerDirectPad[i][z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->RealtimeData.PnVerDirectPad[i][16], IList->StrVer); + MatchLine = -1; + for(x=CmpStartLine; xStrPnInRam[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPnInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + HwTypeDescpTextLen) + z); + if(IList->StrPnInRam[z] == 0)break; + if(IList->StrPnInRam[z] == ' ')break; + } + PnLenInRam = z; + IList->StrVerInRam[10] = '\0'; + for(z=0; z<10; z++){ + IList->StrVerInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + CountTextLen) + z); + if(IList->StrVerInRam[z] == 0)break; + if(IList->StrVerInRam[z] == ' ')break; + } + VerLenInRam = z; + + if( (PnLen == PnLenInRam) && (VerLen == VerLenInRam) ){ + IsEq =1; + for(z=0; zStrPnInRam[z] != IList->StrPn[z]){ + IsEq =0; + break; + } + } + if(IsEq){ + for(z=0; zStrVerInRam[z] != IList->StrVer[z]){ + IsEq =0; + break; + } + } + + } + }else{ + IsEq =0; + } + if(IsEq){ + MatchLine = x; + break; + } + } + if(MatchLine > -1){ + z = *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) +1; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) = z; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +0) = z/10%10 + '0'; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +1) = z%10 + '0'; + }else{ + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btDirectPad; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0) + TMyString::sAddOnStr( "多线盘", IList->Str); + else + TMyString::sAddOnStr( "Direct Ctrl", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + } + } + + //Bus Pad + CmpStartLine = StrList.ItemsCount; + for(i=0; i<20; i++){ + if(IList->BusPadOk[i] == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->RealtimeData.PnVerBusPad[i][z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->RealtimeData.PnVerBusPad[i][16], IList->StrVer); + MatchLine = -1; + for(x=CmpStartLine; xStrPnInRam[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPnInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + HwTypeDescpTextLen) + z); + if(IList->StrPnInRam[z] == 0)break; + if(IList->StrPnInRam[z] == ' ')break; + } + PnLenInRam = z; + IList->StrVerInRam[10] = '\0'; + for(z=0; z<10; z++){ + IList->StrVerInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + CountTextLen) + z); + if(IList->StrVerInRam[z] == 0)break; + if(IList->StrVerInRam[z] == ' ')break; + } + VerLenInRam = z; + + + if( (PnLen == PnLenInRam) && (VerLen == VerLenInRam) ){ + IsEq =1; + for(z=0; zStrPnInRam[z] != IList->StrPn[z]){ + IsEq =0; + break; + } + } + if(IsEq){ + for(z=0; zStrVerInRam[z] != IList->StrVer[z]){ + IsEq =0; + break; + } + } + + } + }else{ + IsEq =0; + } + if(IsEq){ + MatchLine = x; + break; + } + } + if(MatchLine > -1){ + z = *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) +1; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) = z; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +0) = z/10%10 + '0'; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +1) = z%10 + '0'; + }else{ + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btBusPad; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "总线盘", IList->Str); + else TMyString::sAddOnStr( "Bus Pads", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + } + } + + //EthNetwork Not NowCmpStartLine = StrList.ItemsCount; + if(IList->EthNetworkOk == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerEth[z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerEth[16], IList->StrVer); + + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btEthNet; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "以太网卡", IList->Str); + else TMyString::sAddOnStr( "Ethernet", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + + //Wifi Not Now btWireless + if(IList->WirelessOk == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerWireless[z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerWireless[16], IList->StrVer); + + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btWireless; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "无线通讯卡", IList->Str); + else TMyString::sAddOnStr( "Wifi Brd", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + + //Can Network + CmpStartLine = StrList.ItemsCount; + if(IList->CommBoardOk == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerCommBoard[z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerCommBoard[16], IList->StrVer); + + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btCommPort; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "联网接口卡", IList->Str); + else TMyString::sAddOnStr( "Network Brd", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + + //Printer + CmpStartLine = StrList.ItemsCount; + if(IList->PrinterOk == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerPrinter[z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerPrinter[16], IList->StrVer); + + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btPrinter; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "打印机", IList->Str); + else TMyString::sAddOnStr( "Printer", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + + //Power suply + CmpStartLine = StrList.ItemsCount; + for(i=0; i<4; i++){ + if(IList->PowerSpyOk[i] == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerPowerSpy[i][z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerPowerSpy[i][16], IList->StrVer); + MatchLine = -1; + for(x=CmpStartLine; xStrPnInRam[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPnInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + HwTypeDescpTextLen) + z); + if(IList->StrPnInRam[z] == 0)break; + if(IList->StrPnInRam[z] == ' ')break; + } + PnLenInRam = z; + IList->StrVerInRam[10] = '\0'; + for(z=0; z<10; z++){ + IList->StrVerInRam[z] = *(volatile unsigned char *)(StrList.Addr4Items + (x * StrList.LineSize + CountTextLen) + z); + if(IList->StrVerInRam[z] == 0)break; + if(IList->StrVerInRam[z] == ' ')break; + } + VerLenInRam = z; + + + if( (PnLen == PnLenInRam) && (VerLen == VerLenInRam) ){ + IsEq =1; + for(z=0; zStrPnInRam[z] != IList->StrPn[z]){ + IsEq =0; + break; + } + } + if(IsEq){ + for(z=0; zStrVerInRam[z] != IList->StrVer[z]){ + IsEq =0; + break; + } + } + + } + }else{ + IsEq =0; + } + if(IsEq){ + MatchLine = x; + break; + } + } + if(MatchLine > -1){ + z = *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) +1; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + MatchLine*4 ) = z; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +0) = z/10%10 + '0'; + *(volatile unsigned char *)(StrList.Addr4Items + (MatchLine * StrList.LineSize) +PartNumTextLen +1) = z%10 + '0'; + }else{ + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btPowerSuply; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "电源", IList->Str); + else TMyString::sAddOnStr( "Power Supply", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + } + } + + //Key Pad + CmpStartLine = StrList.ItemsCount; + if(IList->KeyPadOk == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerKeyPad[z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerKeyPad[16], IList->StrVer); + + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btKeyPad; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "按键板", IList->Str); + else TMyString::sAddOnStr( "User KeyBoard", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } + + //Ex Mem Card + CmpStartLine = StrList.ItemsCount; + if(IList->ExtMemOk == 3) { + IList->StrPn[16] = '\0'; + for(z=0; z<16; z++){ + IList->StrPn[z] = IList->PnVerExtMem[z]; + if(IList->StrPn[z] == 0)break; + } + PnLen = z; + VerLen = GetVerText(&IList->PnVerExtMem[16], IList->StrVer); + + *(volatile unsigned int *)(StrList.Addr4LinesType + (StrList.ItemsCount)*4) = btExMem; + *(volatile unsigned int *)(StrList.Addr4ItemsCount + (StrList.ItemsCount)*4) = 1; + TMyString::sClear(IList->Str); + if(LanguageEnCn==0)TMyString::sAddOnStr( "存储单元", IList->Str); + else TMyString::sAddOnStr( "Memory Unit", IList->Str); + TMyString::sFillFixLen(IList->Str, HwTypeDescpTextLen); + TMyString::sAddOnStr(IList->StrPn, IList->Str); + TMyString::sFillFixLen(IList->Str, PartNumTextLen); + TMyString::sAddOn2Dg(1, IList->Str); + TMyString::sFillFixLen(IList->Str, CountTextLen); + TMyString::sAddOnStr(IList->StrVer, IList->Str); + TMyString::sFillFixLen(IList->Str, VersionTextLen); + for(z=0; zStr[z]; + } + *(volatile unsigned char *)(StrList.Addr4Items + (StrList.ItemsCount * StrList.LineSize) +VersionTextLen) = '\0'; + StrList.ItemsCount++; + } +} + +void THwInf::Task1000Ms() +{ + if(IsShow == 0)return; + if(Update){ + Analy(); + DrawText(); + Update =0; + } +} + diff --git a/MyCode/Gui/HwInf.h b/MyCode/Gui/HwInf.h new file mode 100644 index 0000000..f34a84e --- /dev/null +++ b/MyCode/Gui/HwInf.h @@ -0,0 +1,133 @@ +#ifndef HWINF_H_ +#define HWINF_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" +#include "Gui.h" + +typedef enum{ + btNotDefine =0, + btDisplay = 1, + btKeyPad = 2, // + btExMem =3, // + btDirectPad =4, // + btBusPad, // + btMotherBoard, // + btPort, // + btPowerSuply, // + btPrinter, // + btCommPort, + btEthNet, + btWireless, +}TInnerBoardType; + + +class THwInf{ + public: + static constexpr unsigned short hList[12] = {32,32,32,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 11, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + class TItemList *IList; + unsigned int IsShow; + unsigned int Update; + + TStaticText TextDraw; + unsigned char RxData[16]; + unsigned char TxData[8]; + struct{ + unsigned int Addr4LinesType; + unsigned int Addr4ItemsCount; + unsigned int Addr4Items; + unsigned int ItemsCount; + unsigned int LineSize; + int DrawTopItem; + int SelectedLine; + }StrList; + public: + THwInf(){ + IsShow = 0; + } + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawText(); + void ClearSelected(); + void DrawSelected(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void QueryPartNum(); + void QueryPnAndVer(); + void QueryVersion(unsigned char aType, unsigned char aInx=0); + void InnerCanPushData(unsigned char aCmd, unsigned char *pData); + void KeyPadUartPushData(unsigned char aCmd, unsigned char *pData); + void CommBrdUartPushData(unsigned char aCmd, unsigned char *pData); + void ExtMemUartPushData(unsigned char aCmd, unsigned char *pData); + void PrinterUartPushData(unsigned char aCmd, unsigned char *pData); + void Task1000Ms(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + int GetVerText(char *pSource, char *pText); + void LoadData(); + void ReDrawInf(); + void Analy(); + + int ExtRequst(unsigned char Prm){IsShow =0; return 0;} +}; + + +#endif + diff --git a/MyCode/Gui/Icon.cpp b/MyCode/Gui/Icon.cpp new file mode 100644 index 0000000..fbfdae8 --- /dev/null +++ b/MyCode/Gui/Icon.cpp @@ -0,0 +1,72 @@ +#include "Icon.h" + + +void TIcon::Init(u16 aX, u16 aY, u16 aW, u16 aH, u16 OwnerX, u16 OwnerY, u32 aSize, u32 aColor) +{ + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + Content.SetBySize(aX+OwnerX+1,aY+OwnerY+1,aW-2,aH-2); + + OwnerLeftTop.x = OwnerX; + OwnerLeftTop.y = OwnerY; + + iSize = aSize; + Color = aColor; + BorderColor = clFrmFace; + + Dx = (Bound.Width - aSize)/2 + Bound.Left; + Dy = (Bound.Height - aSize)/2 + Bound.Top; + Active = true; +} + +void TIcon::SetActive(void) +{ + Active = 1; +} + +void TIcon::SetDeActive(void) +{ + Active = 0; +} + +void TIcon::SetActiveIndex(unsigned int aIndex) +{ + ActiveImageIndex = aIndex; +} + +void TIcon::SetDeActiveIndex(unsigned int aIndex) +{ + DeActiveImageIndex = aIndex; +} + +void TIcon::DrawBorder(void) +{ + VertLineRender(Bound.Left, Bound.Top, Bound.Height, BorderColor); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, BorderColor); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width , BorderColor); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width , BorderColor); +} + +void TIcon::DrawContent(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TIcon::DrawIcon(void) +{ + if(IconList != nullptr) { + if(Active) + IconList->Render(iSize, ActiveImageIndex, Dx, Dy); + else + IconList->Render(iSize, DeActiveImageIndex, Dx, Dy); + } +} + +void TIcon::Show(void) +{ + DrawBorder(); + DrawContent(); + DrawIcon(); +} + + + diff --git a/MyCode/Gui/Icon.h b/MyCode/Gui/Icon.h new file mode 100644 index 0000000..4e22e54 --- /dev/null +++ b/MyCode/Gui/Icon.h @@ -0,0 +1,57 @@ +#ifndef ICON_H_ +#define ICON_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" + +class TIcon{ + public: + class TImageList *IconList; + bool Active; + unsigned int iSize; + unsigned int Color; + unsigned int ActiveImageIndex; + unsigned int DeActiveImageIndex; + int TabOrder; + + unsigned short Dx,Dy; + + TPoint OwnerLeftTop; //Parrent Left Top; + TRect Bound; + TRect Content; + unsigned int BorderColor; + + public: + TIcon(void){}; + TIcon(u16 aX, u16 aY, u16 aW, u16 aH, u16 OwnerX, u16 OwnerY, u32 aSize, u32 aColor){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aSize, aColor); + } + void Init(u16 aX, u16 aY, u16 aW, u16 aH, u16 OwnerX, u16 OwnerY, u32 aSize, u32 aColor); + + void SetActive(void); + void SetDeActive(void); + + void DrawBorder(void); + void DrawContent(void); + void DrawIcon(void); + void Show(void); + + void SetActiveIndex(unsigned int aIndex); + void SetDeActiveIndex(unsigned int aIndex); + +}; + + + + + +#endif + + + + diff --git a/MyCode/Gui/ImageData.cpp b/MyCode/Gui/ImageData.cpp new file mode 100644 index 0000000..6f65751 --- /dev/null +++ b/MyCode/Gui/ImageData.cpp @@ -0,0 +1,30 @@ +#include "ImageData.h" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/ImageData.h b/MyCode/Gui/ImageData.h new file mode 100644 index 0000000..0683e26 --- /dev/null +++ b/MyCode/Gui/ImageData.h @@ -0,0 +1,9 @@ +#ifndef IMAGEDATA_H_ +#define IMAGEDATA_H_ + + + + + +#endif + diff --git a/MyCode/Gui/IoPadDefine.cpp b/MyCode/Gui/IoPadDefine.cpp new file mode 100644 index 0000000..4dbd379 --- /dev/null +++ b/MyCode/Gui/IoPadDefine.cpp @@ -0,0 +1,2389 @@ +#include "IoPadDefine.h" +#include "Register.h" +#include "Runtime.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 54 +#define ipdWidth1 40 +#define ipdWidth2 30 +#define ipdWidth3 40 +#define ipdWidth4 30 + +void TIoPadDefine::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left, Top, Width, CH, 0, 0, clWhite, clMaroon); + SText.Init (319, Top, 480, CH, 0, 0, clWhite, clMaroon); + + Content0.Set(Left, Top+CH, Left + ipdWidth0 -1, Bottom); + Left = Left + ipdWidth0 ; + Content1.Set(Left, Top+CH, Left + ipdWidth1 + ipdWidth2 -1, Bottom); + Left = Left + ipdWidth1 + ipdWidth2 ; + Content2.Set(Left, Top+CH, Left + ipdWidth3 + ipdWidth4 -1, Bottom); + Left = Left + ipdWidth3 + ipdWidth4 ; + Content3.Set(Left, Top+CH, Left + 599 -1, Bottom); + + VScrollBarBox.Set(Right -20 +1, Top + CH, Right, Bottom); + Color = aColor; + #undef CH + + ActiveLineNum=0; + + ListView.ColHeight = 33; + ListView.RowCount = 9; + ListView.FixColTop = Content0.Top; + ListView.FixColBottom = ListView.FixColTop + ListView.ColHeight; + ListView.ColTop[0] = ListView.FixColBottom + 1; + ListView.ColBottom[0] = ListView.ColTop[0] + ListView.ColHeight -1; + ListView.ColLeft[0] = 1; + ListView.ColRight[0] = ListView.ColWidth[0] +1; + for(i=1; i<12; i++){ + ListView.ColTop[i] = ListView.ColTop[i -1] + ListView.ColHeight; + ListView.ColBottom[i] = ListView.ColBottom[i-1] + ListView.ColHeight; + } + for(i=1;i aRect.Bottom)y2 = aRect.Bottom; + if(x == aSelCol){ + if(Index == 0){ + if( (CtlLevel == 0) && (IsEditing ==0) )aSelClr = clBlue; + else aSelClr = clGray; + }else + if(Index == 1){ + if( (CtlLevel == 1) && (IsEditing ==0) )aSelClr = clBlue; + else aSelClr = clGray; + } + if(Index == 2){ + if( (CtlLevel == 2) && (IsEditing ==0) )aSelClr = clBlue; + else aSelClr = clGray; + } + RectFillRender(aRect.Left, y, aRect.Right, y2, aSelClr); + }else{ + if(x & 1){ + RectFillRender(aRect.Left, y, aRect.Right, y2, OddColor); + }else{ + RectFillRender(aRect.Left, y, aRect.Right, y2, Color); + } + } + y = y2 + 1; + if(y>aRect.Bottom)break; + } +} + +void TIoPadDefine::RenderContent0(unsigned int aClr) +{ + RenderContent(Content0, clMoneyGreen,0); +} + +void TIoPadDefine::RenderContent1(unsigned int aClr) +{ + RenderContent(Content1, clNearWhite,1); +} + +void TIoPadDefine::RenderContent2(unsigned int aClr) +{ + RenderContent(Content2, clMoneyGreen,2); +} + +void TIoPadDefine::RenderContent3(unsigned int aClr) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y; + unsigned int aRow; + RectFillRender(Content3.Left, ListView.FixColTop, Content3.Right, ListView.FixColBottom, FixColColor); + for(x=5; x<10; x++){ + aRow = x -5; + for(y=0; y= Loaded1.Count)break; + if(i == Level1.SelectedCol)aClr = clNearWhite; else aClr = clNearBlack; + aIndex = Loaded1.ItemsPath[x]; + if(aIndex < 1)return; + + aTop = ListView.ColTop[i] + TextTopOffSet; + TextDigitRender3Right24(ListView.ColLeft[1], aTop, aClr, aIndex); + + aType = Loaded1.Type[x]; + if(aType > 30)aType = 30; + ImageList.Render(24, aType, ListView.ColLeft[2], aTop); + + aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[3], aTop, aClr, 1); + x++; + } +} + +void TIoPadDefine::RenderHandCtlChannelPrm(void) +{ + int aTop, i, aIdx, aCount, aType; + unsigned int aClr; + + RenderContent3(0xFF000000); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 指派类型" ); + TextRender_string24(ListView.ColLeft[6],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[7],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[8],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[9],aTop,TextColor, "区域" ); + + aCount = Loaded1.Count; + aIdx = Level1.TopIndex; + aClr = clNearBlack; + if(1){ + for(i=0; i= aCount)return; + if(1){ + if((IsEditing) && (PrmEdit.SelectedCol == i) ){ + aTop = ListView.ColTop[i] + TextTopOffSet; + + if(PrmEdit.SelectedRow == 0) aClr = clNearWhite; + else aClr = clNearBlack; + aType = ValueList[aIdx][0].eType; + if(aType >30)aType =30; + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_oType[aType]); + + if(PrmEdit.SelectedRow == 1) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[6],aTop,aClr, ValueList[aIdx][0].Group0 ); + + if(PrmEdit.SelectedRow == 2) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[7],aTop,aClr, ValueList[aIdx][0].Group1); + + if(PrmEdit.SelectedRow == 3) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[8],aTop,aClr, ValueList[aIdx][0].Group2 ); + + if(PrmEdit.SelectedRow == 4) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[9],aTop,aClr, ValueList[aIdx][0].Group3 ); + + }else{ + aTop = ListView.ColTop[i] + TextTopOffSet; + aType = ValueList[aIdx][0].eType; + if(aType >30)aType =30; + TextRender_string24(ListView.ColLeft[5],aTop,clNearBlack, StrAssign_oType[aType]); + TextDigitRender3Right24(ListView.ColLeft[6],aTop,clNearBlack, ValueList[aIdx][0].Group0 ); + TextDigitRender3Right24(ListView.ColLeft[7],aTop,clNearBlack, ValueList[aIdx][0].Group1 ); + TextDigitRender3Right24(ListView.ColLeft[8],aTop,clNearBlack, ValueList[aIdx][0].Group2); + TextDigitRender3Right24(ListView.ColLeft[9],aTop,clNearBlack, ValueList[aIdx][0].Group3); + } + } + aIdx++; + } + } +} + +TGuiMsgReturn TIoPadDefine::HandCtlKeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + if(aKey == VK_LEFT){ + if(IsEditing){ + if(PrmEdit.SelectedRow>0){ + PrmEdit.SelectedRow--; + RenderHandCtlChannelPrm(); + }else{ + IsEditing = 0; + IsModifing = 0; + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + }else{ + if(CtlLevel >0){ + if(CtlLevel == 1){ + CtlLevel = 0; + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + IsWarningSave =1; + RenderWarningSave(); + }else{ + CtlLevel--; + if(CtlLevel == 0){ + + }else + if(CtlLevel == 1){ + LoadHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + }else{ + CtlLevel =0; + LoadHandCtl(); + LoadHandCtlChannel(); + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + } + } + }else + if(aKey == VK_RIGHT){ + if(IsEditing){ + if(PrmEdit.SelectedRow<4){ + PrmEdit.SelectedRow++; + RenderHandCtlChannelPrm(); + } + }else{ + if(CtlLevel == 0){ + CtlLevel++; + LoadHandCtlChannel(); + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + }else + if(CtlLevel == 1){ + IsEditing = 1; + PrmEdit.SelectedCol = Level1.SelectedCol; + PrmEdit.SelectedRow = 0; + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + }else + if(aKey == VK_UP){ + if(IsEditing){ + if(IsModifing){ + aCh = 0; + if(CtlLevel == 1){ + y = Level1.SelectedIndex; + } + x = PrmEdit.SelectedRow; + if(x==0){ + if(ValueList[y][aCh].eType < 30)ValueList[y][aCh].eType++; + }else + if(x==1){ + ValueList[y][aCh].Group0++; + }else + if(x==2){ + ValueList[y][aCh].Group1++; + }else + if(x==3){ + ValueList[y][aCh].Group2++; + }else + if(x==4){ + ValueList[y][aCh].Group3++; + } + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + }else{ + if(CtlLevel ==1){ + if(Level1.SelectedCol >0){ + Level1.SelectedCol--; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + }else{ + if(Level1.TopIndex >0){ + Level1.TopIndex --; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + } + }else{ + if(CtlLevel == 0){ + //ListLineCnt + if(Level0.SelectedCol >0){ + Level0.SelectedCol--; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadHandCtl(); + LoadHandCtlChannel(); + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + + }else{ + if(Level0.TopIndex >0){ + Level0.TopIndex --; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadHandCtl(); + LoadHandCtlChannel(); + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + }else + if(CtlLevel == 1){ + if(Level1.SelectedCol >0){ + Level1.SelectedCol--; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + }else{ + if(Level1.TopIndex >0){ + Level1.TopIndex --; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + } + }else + if(aKey == VK_DOWN){ + if(IsEditing){ + if(IsModifing){ + aCh = 0; + y = Level1.SelectedIndex; + x = PrmEdit.SelectedRow; + if(x==0){ + if(ValueList[y][aCh].eType >0)ValueList[y][aCh].eType--; + }else + if(x==1){ + ValueList[y][aCh].Group0--; + }else + if(x==2){ + ValueList[y][aCh].Group1--; + }else + if(x==3){ + ValueList[y][aCh].Group2--; + }else + if(x==4){ + ValueList[y][aCh].Group3--; + } + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + }else{ + if(CtlLevel == 1){ + if(Level1.SelectedCol < (ListLineCnt-1)){ + if( (Level1.TopIndex + Level1.SelectedCol) < (Loaded1.Count -1) ){ + Level1.SelectedCol++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + }else{ + if( (Level1.TopIndex + ListLineCnt) < Loaded1.Count){ + Level1.TopIndex ++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + } + }else{ + if(CtlLevel == 0){ + //ListLineCnt + if(Level0.SelectedCol < (ListLineCnt-1)){ + if( (Level0.TopIndex + Level0.SelectedCol) < (Loaded0.Count -1) ){ + Level0.SelectedCol++; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadHandCtl(); + LoadHandCtlChannel(); + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + }else{ + if( (Level0.TopIndex + ListLineCnt) < Loaded0.Count){ + Level0.TopIndex ++; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadHandCtl(); + LoadHandCtlChannel(); + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + }else + if(CtlLevel == 1){ + if(Level1.SelectedCol < (ListLineCnt-1)){ + if( (Level1.TopIndex + Level1.SelectedCol) < (Loaded1.Count -1) ){ + Level1.SelectedCol++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + }else{ + if( (Level1.TopIndex + ListLineCnt) < Loaded1.Count){ + Level1.TopIndex ++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + } + }else + if(aKey == VK_F1){ + //Go Modify + if(IsEditing){ + if(IsModifing)IsModifing =0; else IsModifing = 1; + RenderHandCtlChannelPrm(); + } + }else + if(aKey == VK_TAB){ + if(IsWarningSave){ + //User Not Save Here + IsWarningSave = 0; + CtlLevel = 0; + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + if(aKey == VK_EXECUTE){ + //Save Data Here + if(IsWarningSave){ + //Save Here + if(IsReqReturn){ + //Save and Return + + aMsg = guiMsgReturn; + }else{ + IsWarningSave = 0; + RenderHandCtl(); + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + }else{ + //ask if Save Here + IsWarningSave = 1; + RenderWarningSave(); + } + }else + if(aKey == VK_RETURN){ + if(IsWarningSave ==0){ + IsWarningSave = 1; + RenderWarningSave(); + IsReqReturn = 1; + }else{ + IsWarningSave = 0; + if(IsReqReturn){ + aMsg = guiMsgReturn; + }else{ + RenderHandCtlChannel(); + RenderHandCtlChannelPrm(); + } + } + } + return aMsg; +} + +//_________________________________________________________________________________________________________________________________________ +void TIoPadDefine::SetDirectCtl(void) +{ + ParentType = 1; +} + +void TIoPadDefine::LoadDirectCtl(void) +{ + int i; + Loaded0.Count = 0; + for(i=0; i<256;i++){ + Loaded0.ItemsPath[i] =0; + } + for(i=0; i= Loaded1.Count)break; + if(i == Level1.SelectedCol)aClr = clNearWhite; else aClr = clNearBlack; + aIndex = Loaded1.ItemsPath[x]; + if(aIndex < 1)return; + + aTop = ListView.ColTop[i] + TextTopOffSet; + TextDigitRender3Right24(ListView.ColLeft[1], aTop, aClr, aIndex); + + aType = Loaded1.Type[x]; + if(aType > 30)aType = 30; + ImageList.Render(24, aType, ListView.ColLeft[2], aTop); + + aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[3], aTop, aClr, 1); + x++; + } +} + +void TIoPadDefine::RenderDirectCtlChannelPrm(void) +{ + int aTop, i, aIdx, aCount, aType; + unsigned int aClr; + + RenderContent3(0xFF000000); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 指派类型" ); + TextRender_string24(ListView.ColLeft[6],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[7],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[8],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[9],aTop,TextColor, "区域" ); + + aCount = Loaded1.Count; + aIdx = Level1.TopIndex; + aClr = clNearBlack; + if(1){ + for(i=0; i= aCount)return; + if(1){ + if((IsEditing) && (PrmEdit.SelectedCol == i) ){ + aTop = ListView.ColTop[i] + TextTopOffSet; + + if(PrmEdit.SelectedRow == 0) aClr = clNearWhite; + else aClr = clNearBlack; + aType = ValueList[aIdx][0].eType; + if(aType >30)aType =30; + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_oType[aType]); + + if(PrmEdit.SelectedRow == 1) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[6],aTop,aClr, ValueList[aIdx][0].Group0 ); + + if(PrmEdit.SelectedRow == 2) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[7],aTop,aClr, ValueList[aIdx][0].Group1); + + if(PrmEdit.SelectedRow == 3) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[8],aTop,aClr, ValueList[aIdx][0].Group2 ); + + if(PrmEdit.SelectedRow == 4) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[9],aTop,aClr, ValueList[aIdx][0].Group3 ); + + }else{ + aTop = ListView.ColTop[i] + TextTopOffSet; + aType = ValueList[aIdx][0].eType; + if(aType >30)aType =30; + TextRender_string24(ListView.ColLeft[5],aTop,clNearBlack, StrAssign_oType[aType]); + TextDigitRender3Right24(ListView.ColLeft[6],aTop,clNearBlack, ValueList[aIdx][0].Group0 ); + TextDigitRender3Right24(ListView.ColLeft[7],aTop,clNearBlack, ValueList[aIdx][0].Group1 ); + TextDigitRender3Right24(ListView.ColLeft[8],aTop,clNearBlack, ValueList[aIdx][0].Group2); + TextDigitRender3Right24(ListView.ColLeft[9],aTop,clNearBlack, ValueList[aIdx][0].Group3); + } + } + aIdx++; + } + } +} + +TGuiMsgReturn TIoPadDefine::DirectCtlKeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + if(aKey == VK_LEFT){ + if(IsEditing){ + if(PrmEdit.SelectedRow>0){ + PrmEdit.SelectedRow--; + RenderDirectCtlChannelPrm(); + }else{ + IsEditing = 0; + IsModifing = 0; + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + }else{ + if(CtlLevel >0){ + if(CtlLevel == 1){ + CtlLevel = 0; + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + IsWarningSave =1; + RenderWarningSave(); + }else{ + CtlLevel--; + if(CtlLevel == 0){ + + }else + if(CtlLevel == 1){ + LoadDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + }else{ + CtlLevel =0; + LoadDirectCtl(); + LoadDirectCtlChannel(); + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + } + } + }else + if(aKey == VK_RIGHT){ + if(IsEditing){ + if(PrmEdit.SelectedRow<4){ + PrmEdit.SelectedRow++; + RenderDirectCtlChannelPrm(); + } + }else{ + if(CtlLevel == 0){ + CtlLevel++; + LoadDirectCtlChannel(); + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + }else + if(CtlLevel == 1){ + IsEditing = 1; + PrmEdit.SelectedCol = Level1.SelectedCol; + PrmEdit.SelectedRow = 0; + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + }else + if(aKey == VK_UP){ + if(IsEditing){ + if(IsModifing){ + aCh = 0; + if(CtlLevel == 1){ + y = Level1.SelectedIndex; + } + x = PrmEdit.SelectedRow; + if(x==0){ + if(ValueList[y][aCh].eType < 30)ValueList[y][aCh].eType++; + }else + if(x==1){ + ValueList[y][aCh].Group0++; + }else + if(x==2){ + ValueList[y][aCh].Group1++; + }else + if(x==3){ + ValueList[y][aCh].Group2++; + }else + if(x==4){ + ValueList[y][aCh].Group3++; + } + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + }else{ + if(CtlLevel ==1){ + if(Level1.SelectedCol >0){ + Level1.SelectedCol--; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + }else{ + if(Level1.TopIndex >0){ + Level1.TopIndex --; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + } + }else{ + if(CtlLevel == 0){ + //ListLineCnt + if(Level0.SelectedCol >0){ + Level0.SelectedCol--; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadDirectCtl(); + LoadDirectCtlChannel(); + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + + }else{ + if(Level0.TopIndex >0){ + Level0.TopIndex --; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadDirectCtl(); + LoadDirectCtlChannel(); + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + }else + if(CtlLevel == 1){ + if(Level1.SelectedCol >0){ + Level1.SelectedCol--; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + }else{ + if(Level1.TopIndex >0){ + Level1.TopIndex --; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + } + }else + if(aKey == VK_DOWN){ + if(IsEditing){ + if(IsModifing){ + aCh = 0; + y = Level1.SelectedIndex; + x = PrmEdit.SelectedRow; + if(x==0){ + if(ValueList[y][aCh].eType >0)ValueList[y][aCh].eType--; + }else + if(x==1){ + ValueList[y][aCh].Group0--; + }else + if(x==2){ + ValueList[y][aCh].Group1--; + }else + if(x==3){ + ValueList[y][aCh].Group2--; + }else + if(x==4){ + ValueList[y][aCh].Group3--; + } + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + }else{ + if(CtlLevel == 1){ + if(Level1.SelectedCol < (ListLineCnt-1)){ + if( (Level1.TopIndex + Level1.SelectedCol) < (Loaded1.Count -1) ){ + Level1.SelectedCol++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + }else{ + if( (Level1.TopIndex + ListLineCnt) < Loaded1.Count){ + Level1.TopIndex ++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + } + }else{ + if(CtlLevel == 0){ + //ListLineCnt + if(Level0.SelectedCol < (ListLineCnt-1)){ + if( (Level0.TopIndex + Level0.SelectedCol) < (Loaded0.Count -1) ){ + Level0.SelectedCol++; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadDirectCtl(); + LoadDirectCtlChannel(); + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + }else{ + if( (Level0.TopIndex + ListLineCnt) < Loaded0.Count){ + Level0.TopIndex ++; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadDirectCtl(); + LoadDirectCtlChannel(); + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + }else + if(CtlLevel == 1){ + if(Level1.SelectedCol < (ListLineCnt-1)){ + if( (Level1.TopIndex + Level1.SelectedCol) < (Loaded1.Count -1) ){ + Level1.SelectedCol++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + }else{ + if( (Level1.TopIndex + ListLineCnt) < Loaded1.Count){ + Level1.TopIndex ++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + } + }else + if(aKey == VK_F1){ + //Go Modify + if(IsEditing){ + if(IsModifing)IsModifing =0; else IsModifing = 1; + RenderDirectCtlChannelPrm(); + } + }else + if(aKey == VK_TAB){ + if(IsWarningSave){ + //User Not Save Here + IsWarningSave = 0; + CtlLevel = 0; + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + if(aKey == VK_EXECUTE){ + //Save Data Here + if(IsWarningSave){ + //Save Here + if(IsReqReturn){ + //Save and Return + + aMsg = guiMsgReturn; + }else{ + IsWarningSave = 0; + RenderDirectCtl(); + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + }else{ + //ask if Save Here + IsWarningSave = 1; + RenderWarningSave(); + } + }else + if(aKey == VK_RETURN){ + if(IsWarningSave ==0){ + IsWarningSave = 1; + RenderWarningSave(); + IsReqReturn = 1; + }else{ + IsWarningSave = 0; + if(IsReqReturn){ + aMsg = guiMsgReturn; + }else{ + RenderDirectCtlChannel(); + RenderDirectCtlChannelPrm(); + } + } + } + return aMsg; +} + +//________________________________________________________________________________________________________________________________________ +//________________________________________________________________________________________________________________________________________ +void TIoPadDefine::SetPort(void) +{ + ParentType = 2; +} + +void TIoPadDefine::LoadPort(void) +{ + int i; + Loaded0.Count = 0; + for(i=0; i<256;i++){ + Loaded0.ItemsPath[i] =0; + } + for(i=0; i= Loaded1.Count)break; + if(i == Level1.SelectedCol)aClr = clNearWhite; else aClr = clNearBlack; + aIndex = Loaded1.ItemsPath[x]; + if(aIndex < 1)return; + + aTop = ListView.ColTop[i] + TextTopOffSet; + TextDigitRender3Right24(ListView.ColLeft[1], aTop, aClr, aIndex); + + aType = Loaded1.Type[x]; + if(aType > 30)aType = 30; + ImageList.Render(24, aType, ListView.ColLeft[2], aTop); + + aClr = clNearBlack; + if(Loaded1.ChannelCount[x] > 1){ + TextDigitRender3Right24(ListView.ColLeft[3], aTop, aClr, Loaded1.ChannelInCount[x]); + }else{ + TextDigitRender3Right24(ListView.ColLeft[3], aTop, aClr, Loaded1.ChannelCount[x]); + } + + x++; + } +} + + +void TIoPadDefine::RenderEpChannel(void) +{ + int i, x, aIndex, BGClr, TextClr, aTop; + unsigned int aClr; + unsigned char aType; + unsigned char aP0; + + RenderContent2(0xFF000000); + aTop = ListView.FixColTop + TextTopOffSet; + + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路" ); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, " 地址" ); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, " 通道" ); + + x = Level2.TopIndex; + for(i=0; i= Loaded2.Count)break; + if(i == Level2.SelectedCol)aClr = clNearWhite; else aClr = clNearBlack; + aIndex = Loaded2.ItemsPath[x]; + if(aIndex < 1)return; + + aTop = ListView.ColTop[i] + TextTopOffSet; + TextDigitRender3Right24(ListView.ColLeft[3], aTop, aClr, aIndex); + + x++; + } +} + +void TIoPadDefine::RenderEpPrm(void) +{ + int aTop, i, x, aIdx, aCount; + unsigned int aClr; + + RenderContent3(clMoneyGreen); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 指派类型" ); + TextRender_string24(ListView.ColLeft[6],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[7],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[8],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[9],aTop,TextColor, "区域" ); + + aCount = Loaded1.Count; + aIdx = Level1.TopIndex; + aClr = clNearBlack; + if(1){ + for(i=0; i= aCount)return; + if(Loaded1.ChannelCount[aIdx] == 1){ + if((IsEditing) && (PrmEdit.SelectedCol == i) ){ + aTop = ListView.ColTop[i] + TextTopOffSet; + + if(PrmEdit.SelectedRow == 0) aClr = clNearWhite; + else aClr = clNearBlack; + if(Loaded1.ChannelInCount) + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_iType[ValueList[aIdx][0].eType]); + else + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_oType[ValueList[aIdx][0].eType]); + + if(PrmEdit.SelectedRow == 1) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[6],aTop,aClr, ValueList[aIdx][0].Group0 ); + + if(PrmEdit.SelectedRow == 2) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[7],aTop,aClr, ValueList[aIdx][0].Group1); + + if(PrmEdit.SelectedRow == 3) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[8],aTop,aClr, ValueList[aIdx][0].Group2 ); + + if(PrmEdit.SelectedRow == 4) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[9],aTop,aClr, ValueList[aIdx][0].Group3 ); + + }else{ + aTop = ListView.ColTop[i] + TextTopOffSet; + if(Loaded1.ChannelInCount) + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_iType[ValueList[aIdx][0].eType]); + else + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_oType[ValueList[aIdx][0].eType]); + TextDigitRender3Right24(ListView.ColLeft[6],aTop,clNearBlack, ValueList[aIdx][0].Group0 ); + TextDigitRender3Right24(ListView.ColLeft[7],aTop,clNearBlack, ValueList[aIdx][0].Group1 ); + TextDigitRender3Right24(ListView.ColLeft[8],aTop,clNearBlack, ValueList[aIdx][0].Group2); + TextDigitRender3Right24(ListView.ColLeft[9],aTop,clNearBlack, ValueList[aIdx][0].Group3); + } + } + aIdx++; + } + } +} + +void TIoPadDefine::RenderEpChannelPrm() +{ + int aTop, i, x, aIdx, aCount, aType; + unsigned int aClr; + unsigned int sColClr, sRowClr; + unsigned int sColTextClr, sRowTextClr; + unsigned char aCh; + + RenderContent3(clMoneyGreen); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 指派类型" ); + TextRender_string24(ListView.ColLeft[6],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[7],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[8],aTop,TextColor, "区域" ); + TextRender_string24(ListView.ColLeft[9],aTop,TextColor, "区域" ); + + aCount = Loaded2.Count; + aIdx = Level1.SelectedIndex; + aCh = Level2.TopIndex; + if(1){ + for(i=0; i= aCount)return; + if(1){ + if((IsEditing) && (PrmEdit.SelectedCol == i) ){ + aTop = ListView.ColTop[i] + TextTopOffSet; + + if(PrmEdit.SelectedRow == 0) aClr = clNearWhite; + else aClr = clNearBlack; + aType = ValueList[aIdx][aCh].eType; + if(aType >30)aType =30; + if(Loaded1.ChannelInCount) + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_iType[aType]); + else + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_oType[aType]); + + if(PrmEdit.SelectedRow == 1) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[6],aTop,aClr, ValueList[aIdx][aCh].Group0 ); + + if(PrmEdit.SelectedRow == 2) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[7],aTop,aClr, ValueList[aIdx][aCh].Group1); + + if(PrmEdit.SelectedRow == 3) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[8],aTop,aClr, ValueList[aIdx][aCh].Group2 ); + + if(PrmEdit.SelectedRow == 4) aClr = clNearWhite; + else aClr = clNearBlack; + TextDigitRender3Right24(ListView.ColLeft[9],aTop,aClr, ValueList[aIdx][aCh].Group3 ); + + }else{ + aTop = ListView.ColTop[i] + TextTopOffSet; + if(Loaded1.ChannelInCount) + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_iType[ValueList[aIdx][aCh].eType]); + else + TextRender_string24(ListView.ColLeft[5],aTop,aClr, StrAssign_oType[ValueList[aIdx][aCh].eType]); + TextDigitRender3Right24(ListView.ColLeft[6],aTop,clNearBlack, ValueList[aIdx][aCh].Group0 ); + TextDigitRender3Right24(ListView.ColLeft[7],aTop,clNearBlack, ValueList[aIdx][aCh].Group1 ); + TextDigitRender3Right24(ListView.ColLeft[8],aTop,clNearBlack, ValueList[aIdx][aCh].Group2); + TextDigitRender3Right24(ListView.ColLeft[9],aTop,clNearBlack, ValueList[aIdx][aCh].Group3); + } + } + aCh++; + } + } +} +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TIoPadDefine::EpKeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + if(aKey == VK_LEFT){ + if(IsEditing){ + if(PrmEdit.SelectedRow>0){ + PrmEdit.SelectedRow--; + if(CtlLevel == 1){ + RenderEpPrm(); + }else + if(CtlLevel == 2){ + RenderEpChannelPrm(); + } + }else{ + IsEditing = 0; + IsModifing = 0; + if(CtlLevel == 1){ + RenderEp(); + RenderEpPrm(); + }else + if(CtlLevel == 2){ + RenderEpChannel(); + RenderEpChannelPrm(); + } + } + }else{ + if(CtlLevel >0){ + if(CtlLevel == 1){ + CtlLevel = 0; + RenderPort(); + RenderEp(); + RenderEpChannel(); + RenderEpChannelPrm(); + IsWarningSave =1; + RenderWarningSave(); + }else{ + CtlLevel--; + if(CtlLevel == 0){ + + }else + if(CtlLevel == 1){ + LoadEp(); + RenderEp(); + RenderEpPrm(); + }else + if(CtlLevel == 2){ + RenderEpChannel(); + RenderEpChannelPrm(); + }else{ + CtlLevel =0; + LoadPort(); + RenderPort(); + RenderEp(); + RenderEpChannel(); + RenderEpChannelPrm(); + } + } + } + } + }else + if(aKey == VK_RIGHT){ + if(IsEditing){ + if(PrmEdit.SelectedRow<4){ + PrmEdit.SelectedRow++; + if(CtlLevel == 1){ + RenderEp(); + RenderEpPrm(); + }else + if(CtlLevel == 2){ + RenderEpChannel(); + RenderEpChannelPrm(); + } + } + }else{ + if(CtlLevel == 0){ + CtlLevel++; + LoadEp(); + LoadEpChannel(); + RenderPort(); + RenderEp(); + RenderEpPrm(); + }else + if(CtlLevel == 1){ + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + if(aP0 && aP1 ){ + aP0--; + aP1--; + Level1.CurrentType = EpDev[aP0][aP1].fData.Split.dType; + if( Loaded1.ChannelCount[Level1.SelectedIndex] >1 ){ + CtlLevel ++; + LoadEpChannel(); + RenderEp(); + Level2.TopIndex = 0; + Level2.SelectedIndex = 0; + Level2.SelectedCol = 0; + RenderEpChannel(); + RenderEpChannelPrm(); + }else{ + IsEditing = 1; + PrmEdit.SelectedCol = Level1.SelectedCol; + PrmEdit.SelectedRow = 0; + RenderEp(); + RenderEpPrm(); + } + } + }else + if(CtlLevel == 2){ + IsEditing = 1; + PrmEdit.SelectedCol = Level2.SelectedCol; + PrmEdit.SelectedRow = 0; + RenderEp(); + RenderEpChannel(); + RenderEpChannelPrm(); + } + } + }else + if(aKey == VK_UP){ + if(IsEditing){ + if(IsModifing){ + if(CtlLevel == 1){ + y = Level1.SelectedIndex; + aCh = 0; + }else + if(CtlLevel == 2){ + y = Level1.SelectedIndex; + aCh = Level2.SelectedIndex; + } + x = PrmEdit.SelectedRow; + if(x==0){ + if(ValueList[y][aCh].eType < 30)ValueList[y][aCh].eType++; + }else + if(x==1){ + ValueList[y][aCh].Group0++; + }else + if(x==2){ + ValueList[y][aCh].Group1++; + }else + if(x==3){ + ValueList[y][aCh].Group2++; + }else + if(x==4){ + ValueList[y][aCh].Group3++; + } + if(CtlLevel == 1){ + RenderEpPrm(); + }else + if(CtlLevel == 2){ + RenderEpChannelPrm(); + } + }else{ + if(CtlLevel ==1){ + if(Level1.SelectedCol >0){ + Level1.SelectedCol--; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + }else{ + if(Level1.TopIndex >0){ + Level1.TopIndex --; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderEp(); + RenderEpPrm(); + } + }else + if(CtlLevel ==2){ + if(Level2.SelectedCol >0){ + Level2.SelectedCol--; + Level2.SelectedIndex--; + RenderEpChannel(); + PrmEdit.SelectedCol = Level2.SelectedCol; + PrmEdit.SelectedIndex = Level2.SelectedIndex; + RenderEpChannelPrm(); + } + } + } + }else{ + if(CtlLevel == 0){ + //ListLineCnt + if(Level0.SelectedCol >0){ + Level0.SelectedCol--; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadEp(); + LoadEpChannel(); + RenderPort(); + RenderEp(); + RenderEpPrm(); + + }else{ + if(Level0.TopIndex >0){ + Level0.TopIndex --; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadEp(); + LoadEpChannel(); + RenderPort(); + RenderEp(); + RenderEpPrm(); + } + } + }else + if(CtlLevel == 1){ + if(Level1.SelectedCol >0){ + Level1.SelectedCol--; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + }else{ + if(Level1.TopIndex >0){ + Level1.TopIndex --; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderEp(); + RenderEpPrm(); + } + }else + if(CtlLevel == 2){ + if(Level2.SelectedCol >0){ + Level2.SelectedCol--; + Level2.SelectedIndex--; + RenderEpChannel(); + } + } + } + }else + if(aKey == VK_DOWN){ + if(IsEditing){ + if(IsModifing){ + if(CtlLevel == 1){ + y = Level1.SelectedIndex; + aCh = 0; + }else + if(CtlLevel == 2){ + y = Level1.SelectedIndex; + aCh = Level2.SelectedIndex; + } + x = PrmEdit.SelectedRow; + if(x==0){ + if(ValueList[y][aCh].eType >0)ValueList[y][aCh].eType--; + }else + if(x==1){ + ValueList[y][aCh].Group0--; + }else + if(x==2){ + ValueList[y][aCh].Group1--; + }else + if(x==3){ + ValueList[y][aCh].Group2--; + }else + if(x==4){ + ValueList[y][aCh].Group3--; + } + if(CtlLevel == 1){ + RenderEpPrm(); + }else + if(CtlLevel == 2){ + RenderEpChannelPrm(); + } + }else{ + if(CtlLevel == 1){ + if(Level1.SelectedCol < (ListLineCnt-1)){ + if( (Level1.TopIndex + Level1.SelectedCol) < (Loaded1.Count -1) ){ + Level1.SelectedCol++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + }else{ + if( (Level1.TopIndex + ListLineCnt) < Loaded1.Count){ + Level1.TopIndex ++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + PrmEdit.TopIndex = Level1.TopIndex; + PrmEdit.SelectedIndex = Level1.SelectedIndex; + PrmEdit.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderEp(); + RenderEpPrm(); + } + }else + if(CtlLevel == 2){ + if( (Level2.SelectedCol < (Loaded2.Count-1)) && (Level2.SelectedCol < 3) ){ + Level2.SelectedCol++; + Level2.SelectedIndex++; + RenderEpChannel(); + PrmEdit.SelectedCol = Level2.SelectedCol; + PrmEdit.SelectedIndex = Level2.SelectedIndex; + RenderEpChannelPrm(); + } + } + } + }else{ + if(CtlLevel == 0){ + //ListLineCnt + if(Level0.SelectedCol < (ListLineCnt-1)){ + if( (Level0.TopIndex + Level0.SelectedCol) < (Loaded0.Count -1) ){ + Level0.SelectedCol++; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadEp(); + RenderPort(); + RenderEp(); + RenderEpPrm(); + } + }else{ + if( (Level0.TopIndex + ListLineCnt) < Loaded0.Count){ + Level0.TopIndex ++; + Level0.SelectedIndex = Level0.TopIndex + Level0.SelectedCol; + Level1.SelectedCol =0; + Level1.SelectedIndex = 0; + Level1.SelectedIndex = 0; + Level2.SelectedCol =0; + Level2.SelectedIndex = 0; + Level2.SelectedIndex = 0; + LoadEp(); + RenderPort(); + RenderEp(); + RenderEpPrm(); + } + } + }else + if(CtlLevel == 1){ + if(Level1.SelectedCol < (ListLineCnt-1)){ + if( (Level1.TopIndex + Level1.SelectedCol) < (Loaded1.Count -1) ){ + Level1.SelectedCol++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + }else{ + if( (Level1.TopIndex + ListLineCnt) < Loaded1.Count){ + Level1.TopIndex ++; + Level1.SelectedIndex = Level1.TopIndex + Level1.SelectedCol; + Level2.TopIndex = Level1.TopIndex; + Level2.SelectedIndex = Level1.SelectedIndex; + Level2.SelectedCol = Level1.SelectedCol; + aP0 = Loaded0.ItemsPath[Level0.SelectedIndex]; + aP1 = Loaded1.ItemsPath[Level1.SelectedIndex]; + Updata = 1; + } + } + if(Updata){ + RenderEp(); + RenderEpPrm(); + } + } + if(CtlLevel == 2){ + if( (Level2.SelectedCol < (Loaded2.Count-1)) && (Level2.SelectedCol < 3) ){ + Level2.SelectedCol++; + Level2.SelectedIndex++; + RenderEpChannel(); + } + } + } + }else + if(aKey == VK_F1){ + //Go Modify + if(IsEditing){ + if(IsModifing)IsModifing =0; else IsModifing = 1; + if(CtlLevel == 1){ + RenderEpPrm(); + }else + if(CtlLevel == 2){ + RenderEpChannelPrm(); + } + } + }else + if(aKey == VK_TAB){ + if(IsWarningSave){ + //User Not Save Here + IsWarningSave = 0; + CtlLevel = 0; + RenderPort(); + RenderEp(); + } + } + if(aKey == VK_EXECUTE){ + //Save Data Here + if(IsWarningSave){ + //Save Here + if(IsReqReturn){ + //Save and Return + + aMsg = guiMsgReturn; + }else{ + IsWarningSave = 0; + CtlLevel = 0; + RenderPort(); + RenderEp(); + if(CtlLevel == 2){ + RenderEpChannel(); + RenderEpChannelPrm(); + }else{ + RenderEpPrm(); + } + } + }else{ + //Ask if Save Here + IsWarningSave = 1; + RenderWarningSave(); + } + }else + if(aKey == VK_RETURN){ + if(IsWarningSave == 0){ + IsWarningSave = 1; + RenderWarningSave(); + IsReqReturn = 1; + }else{ + IsWarningSave = 0; + if(IsReqReturn){ + aMsg = guiMsgReturn; + }else{ + if(CtlLevel == 2){ + RenderEpChannel(); + RenderEpChannelPrm(); + }else{ + RenderEp(); + RenderEpPrm(); + } + } + } + } + return aMsg; +} + +TGuiMsgReturn TIoPadDefine::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if(ParentType == 0){ + //dgTYPE_HAND_CTL + aMsg = HandCtlKeyIn(aKey); + }else + if(ParentType == 1){ + //dgTYPE_DIRECT_CTL + aMsg = DirectCtlKeyIn(aKey); + }else + if(ParentType == 2){ + //EpDev + aMsg = EpKeyIn(aKey); + } + + if(aKey == VK_EXECUTE){ + //Open path Device + + }else + if(aKey == VK_F2){ + + }else + if(aKey == VK_RETURN){ + + } + + return aMsg; +} + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/IoPadDefine.h b/MyCode/Gui/IoPadDefine.h new file mode 100644 index 0000000..7f4c76e --- /dev/null +++ b/MyCode/Gui/IoPadDefine.h @@ -0,0 +1,189 @@ +#ifndef IOPADDEFINE_H_ +#define IOPADDEFINE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "MainCtl.h" +#include "Runtime.h" + +class TIoPadDefine{ + public: + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + struct{ + unsigned short RowCount; + unsigned short ColTop[12]; + unsigned short ColBottom[12]; + unsigned short ColHeight; + unsigned short ColWidth[12]; + unsigned short ColLeft[12]; + unsigned short ColRight[12]; + unsigned short FixColTop; + unsigned short FixColBottom; + }ListView; + public: + TStaticText Caption; + TStaticText SText; + int ActiveLineNum; + int LineCount; + int LineHeight; + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + + TRect Content0; + TRect Content1; + TRect Content2; + TRect Content3; + + TMyString Str; + + unsigned char State; + unsigned char CtlIndex; + unsigned char NewRegCompleted; + + unsigned char ParentType; + struct{ + unsigned char iType; + unsigned char Path0; + unsigned char Path1; + unsigned char Path2; + }Selected; + + struct{ + int TopIndex; + int SelectedCol; + int SelectedIndex; + unsigned char CurrentType; + }Level0, Level1, Level2; + + struct{ + unsigned char Count; + unsigned char Type[40]; + unsigned char ItemsPath[40]; + }Loaded0; + struct{ + unsigned char Count; + unsigned char Type[256]; + unsigned char ItemsPath[256]; + unsigned char ChannelCount[256]; + unsigned char ChannelInCount[256]; + }Loaded1; + struct{ + unsigned char Count; + unsigned char Type[4]; + unsigned char IsOut[4]; + unsigned char ItemsPath[4]; + }Loaded2; + + + struct{ + int TopIndex; + int SelectedCol; + int SelectedRow; + int SelectedIndex; + unsigned char CurrentType; + }PrmEdit; + struct { + unsigned char eType; + unsigned char Group0; + unsigned char Group1; + unsigned char Group2; + unsigned char Group3; + }ValueList[256][4]; + unsigned char IsEditing; + unsigned char IsModifing; + unsigned char IsWarningSave; + unsigned char IsReqReturn; + + unsigned char CtlLevel; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TIoPadDefine(){}; + TIoPadDefine(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderContent(TRect aRect, unsigned int aClr, unsigned int Index); + void RenderContent0(unsigned int aClr); + void RenderContent1(unsigned int aClr); + void RenderContent2(unsigned int aClr); + void RenderContent3(unsigned int aClr); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawVertScrollBar0(void); + void DrawVertScrollBar1(void); + + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + + void RenderWarningSave(void); + + void FullRedraw(int Prm); + //_________________________________________________ + void SetHandCtl(void); + void LoadHandCtl(void); + void LoadHandCtlChannel(); + void RenderHandCtl(void); + void RenderHandCtlChannel(void); + void RenderHandCtlChannelPrm(void); + //_________________________________________________ + void SetDirectCtl(void); + void LoadDirectCtl(void); + void LoadDirectCtlChannel(); + void RenderDirectCtl(void); + void RenderDirectCtlChannel(void); + void RenderDirectCtlChannelPrm(void); + //_________________________________________________ + void SetPort(void); + void LoadPort(void); + void LoadEp(void); + void LoadEpChannel(void); + void RenderPort(void); + void RenderEp(void); + void RenderEpChannel(void); + void RenderEpPrm(void); + void RenderEpChannelPrm(void); + //_________________________________________________ + void HandCtlList(void); + + TGuiMsgReturn HandCtlKeyIn(unsigned char aKey); + TGuiMsgReturn DirectCtlKeyIn(unsigned char aKey); + TGuiMsgReturn EpKeyIn(unsigned char aKey); + TGuiMsgReturn KeyIn(unsigned char aKey); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/ItemList.cpp b/MyCode/Gui/ItemList.cpp new file mode 100644 index 0000000..e69de29 diff --git a/MyCode/Gui/ItemList.h b/MyCode/Gui/ItemList.h new file mode 100644 index 0000000..429ea8c --- /dev/null +++ b/MyCode/Gui/ItemList.h @@ -0,0 +1,119 @@ +#ifndef ITEMLIST_H_ +#define ITEMLIST_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "DevProperty.h" + +class TItemList{ + public: + static constexpr int RtDataMaxLen = 512; + public: + TStaticText Caption; + TStaticText STextCtlType; + TStaticText STextState; + TStaticText STextDType; + TStaticText STextRegisted; + TStaticText STextCtlNum; + TStaticText STextModuleInDefineType; + TStaticText STextLastState; + TEdit EditCtlNum; + TEdit EditPortNum; + TEdit EditAddrNum; + TEdit EditDescpShow; + TEdit EditUserCode; + TEdit EditAreaAssign; + + TEdit Edit[4]; + union{ + char TextOut[8][100]; + struct{ + char PnVerMotherBoard[5][24]; //120 + char PnVerKeyPad[24]; //144 + char PnVerPrinter[24]; //168 + char PnVerExtMem[24]; //192 + char PnVerCommBoard[24]; //216 + char PnVerPowerSpy[4][24]; //312 + char PnVerEth[24]; // + char PnVerWireless[24]; //360 + + char Str[72]; //568 + char StrPn[20]; // + char StrVer[20]; // + char StrPnInRam[20]; + char StrVerInRam[20]; //648 + + char MotherBrdOk[8]; // + char PortOk[40]; + char BusPadOk[20]; + char DirectPadOk[20]; + char PowerSpyOk[4]; + char KeyPadOk; + char PrinterOk; + char ExtMemOk; + char EthNetworkOk; + char WirelessOk; + char CommBoardOk; + }; + }; + union{ + char Text[128][16]; + struct{ + char PnVerPort[40][24]; + char PnVerBusPad[20][24]; + char PnVerDirectPad[20][24]; + }; + unsigned char Data[4][512]; + void Reset(){ + for(int i=0; i<512; i++){ + Data[0][i] =0; + Data[1][i] =0; + Data[2][i] =0; + Data[3][i] =0; + } + } + }RealtimeData; + + union{ + char Str[256]; + unsigned char D8[256]; + unsigned short D16[128]; + unsigned int D32[64]; + void Reset(){ + for(int i=0; i<64; i++){ + D32[i] = 0; + } + } + }ReadWriteData; + void TextOutClear(){ + for(int i=0; i<8; i++){ + for(int x=0; x<100; x++)TextOut[i][x] = 0; + } + } +}; + + + + + + + + + + + + + + + + + + +#endif + diff --git a/MyCode/Gui/LanguageCfg.cpp b/MyCode/Gui/LanguageCfg.cpp new file mode 100644 index 0000000..516dbf4 --- /dev/null +++ b/MyCode/Gui/LanguageCfg.cpp @@ -0,0 +1,328 @@ +#include "RuntimeData.h" +#include "LanguageCfg.h" +#include "DevMask.h" + +#define dInteval 88 + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +static constexpr short svGridX[10] = { +6, +6 + (dInteval * 1) , +6 + (dInteval * 2) , +6 + (dInteval * 3) , +6 + (dInteval * 4) , +6 + (dInteval * 5) , +6 + (dInteval * 6) , +6 + (dInteval * 7) , +6 + (dInteval * 8) , +6 + (dInteval * 9) +}; + +void TLanguageCfg::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "本机->语言/Language"); + TextRender_string24(svGridX[0], Lv.Grid.Top[0] +10, clNearWhite, "语言/Language"); + TextRender_string24(svGridX[0] +30, Lv.Grid.Top[0] +46, clNearWhite, "中文"); + TextRender_string24(svGridX[1] +30, Lv.Grid.Top[0] +46, clNearWhite, "英文/Language"); + TRoundRect::sDrawBySize(svGridX[0] +6, Lv.Grid.Top[1] + 14, 76, 36, 7, clNearWhite, "保存", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Local->Language/语言"); + TextRender_string24(svGridX[0], Lv.Grid.Top[0] +10, clNearWhite, "Language/语言"); + TextRender_string24(svGridX[0] +30, Lv.Grid.Top[0] +46, clNearWhite, "CN"); + TextRender_string24(svGridX[1] +30, Lv.Grid.Top[0] +46, clNearWhite, "English/英文"); + TRoundRect::sDrawBySize(svGridX[0] +6, Lv.Grid.Top[1] + 14, 76, 36, 7, clNearWhite, "Save", 14, clNearBlack); + } +} + +void TLanguageCfg::Init() +{ + Tag.Group = 0; + Tag.Inx0 = 0; + Tag.Inx1 = 0; + IsPermission =0; + + SettingEnCn = 0; + + SaveResult = 0; +} + +void TLanguageCfg::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TLanguageCfg::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TLanguageCfg::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TLanguageCfg::DrawEnCn() +{ + if(SettingEnCn == 0){ + TRoundSquare::sDrawBySize(svGridX[0] +2, Lv.Grid.Top[0] + 46, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + TRoundSquare::sDrawBySize(svGridX[1] +2, Lv.Grid.Top[0] + 46, dWWidth, dWHeigh, dRoundR, dWdDisabelClr, 0); + }else{ + TRoundSquare::sDrawBySize(svGridX[0] +2, Lv.Grid.Top[0] + 46, dWWidth, dWHeigh, dRoundR, dWdDisabelClr, 0); + TRoundSquare::sDrawBySize(svGridX[1] +2, Lv.Grid.Top[0] + 46, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + } +} + +void TLanguageCfg::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; i0){ + DrawSelected(0); + Tag.Inx0 --; + DrawSelected(1); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 >0){ + DrawSelected(0); + Tag.Inx1 --; + DrawSelected(1); + } + } + }else + if(aKey == VK_RIGHT){ + if(Tag.Group == 0){ + if(Tag.Inx0 <1){ + DrawSelected(0); + Tag.Inx0 ++; + DrawSelected(1); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 <7){ + DrawSelected(0); + Tag.Inx1 ++; + DrawSelected(1); + } + } + }else + if(aKey == VK_UP){ + if(Tag.Group == 0){ + + }else + if(Tag.Group == 1){ + DrawSelected(0); + Tag.Group = 0; + if(Tag.Inx0 >1)Tag.Inx0 = 1; + DrawSelected(1); + } + }else + if(aKey == VK_DOWN){ + if(Tag.Group == 0){ + DrawSelected(0); + Tag.Group = 1; + if(Tag.Inx1 >7)Tag.Inx1 =7; + DrawSelected(1); + }else + if(Tag.Group == 1){ + } + }else + if(aKey == VK_F1){ + ChangeValue(); + DrawEnCn(); + }else + if(aKey == VK_EXECUTE){ + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 40, 400, 140, 2); + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + if( (aKey != VK_EXECUTE) && (aKey != VK_RETURN) ){ + if(SaveResult != 0)ShowSaveResult(0); + } + } + return aMsg; +} + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/LanguageCfg.h b/MyCode/Gui/LanguageCfg.h new file mode 100644 index 0000000..cfd6422 --- /dev/null +++ b/MyCode/Gui/LanguageCfg.h @@ -0,0 +1,138 @@ +#ifndef LANGUAGECFG_H_ +#define LANGUAGECFG_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" + +class TLanguageCfg{ + public: + static constexpr unsigned short hList[12] = {80,60,32,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint TipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 20, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 80, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 20, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 10, + }; + + int SettingEnCn; + + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Dump0; + void Reset(); + }Tag; + + int SaveResult; + unsigned char IsPermission; + public: + TLanguageCfg(){}; + void Init(); + void RenderBackGround(void); + + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void Show(); + void DrawTip(); + void FullRedraw(int Prm); + void DrawFixText(); + + void DrawSelected(int IsSelected); + + void DrawEnCn(); + + void ChangeValue(); + + void ShowSaveResult(); + void ShowSaveResult(int aSaveResult); + + void LoadSysCfg(); + void SetDefault(); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void SetProperty(); + void SetEventType(); + + void ShowSta(int aGroup, int aInx); + void ShowStaAll(); + int GoResult(); + + static void sRecoverSetDefault(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + int ExtRequst(unsigned char Prm){return 0;} + +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/LinkageList.cpp b/MyCode/Gui/LinkageList.cpp new file mode 100644 index 0000000..c9a95bc --- /dev/null +++ b/MyCode/Gui/LinkageList.cpp @@ -0,0 +1,320 @@ +#include "LinkageList.h" + +static const short svGridX[8] = {20, 44, 92, 140, 164, 212, 400, 600}; +static const short xExist = 260; + +void TLinkageList::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "联动->编程查询"); + TextRender_string24(svGridX[0], Lv.Grid.Top[0] +4, clNearWhite, "第"); + TextRender_string24(svGridX[2], Lv.Grid.Top[0] +4, clNearWhite, "条"); + TextRender_string24(svGridX[3], Lv.Grid.Top[0] +4, clNearWhite, "共"); + TextRender_string24(svGridX[5], Lv.Grid.Top[0] +4, clNearWhite, "条"); + TextRender_string24(xExist, Lv.Grid.Top[0] +4, clNearWhite, "有效"); + TextRender_string24(xExist+48+48, Lv.Grid.Top[0] +4, clNearWhite, "条"); + + TextRender_string24(svGridX[6], Lv.Grid.Top[0] +4, clNearWhite, "执行情况"); + TextRender_string24(svGridX[7], Lv.Grid.Top[0] +4, clNearWhite, "正常/屏蔽"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Linkage->Expression Overview"); + TextRender_string24(svGridX[0], Lv.Grid.Top[0] +4, clNearWhite, "Index"); + //TextRender_string24(svGridX[2], Lv.Grid.Top[0] +4, clNearWhite, "条"); + TextRender_string24(svGridX[3]-36, Lv.Grid.Top[0] +4, clNearWhite, "Total"); + //TextRender_string24(svGridX[5], Lv.Grid.Top[0] +4, clNearWhite, "条"); + TextRender_string24(xExist-12, Lv.Grid.Top[0] +4, clNearWhite, "Valid"); + //TextRender_string24(xExist+48+48, Lv.Grid.Top[0] +4, clNearWhite, "条"); + + TextRender_string24(svGridX[6]+20, Lv.Grid.Top[0] +4, clNearWhite, "Executed"); + TextRender_string24(svGridX[7]+20, Lv.Grid.Top[0] +4, clNearWhite, "Blocking"); + } +} + +void TLinkageList::Init() +{ + IsShow = 0; + ShowEntry = 0; + Tag.Inx =0; + Tag.TopInx = 0; + Items.Inx = 0; + Items.TopInx = 0; +} + +void TLinkageList::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TLinkageList::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TLinkageList::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; i 10)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle +} + +void TLinkageList::Check4Selected(void) +{ + int iT; + iT = Tag.Inx + 1; + if(iT == 0)return; + if(iT > 10)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TLinkageList::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone, SubReturn; + + if(ShowEntry){ + SubReturn = LinkageProgram.KeyIn(aKey); + if(SubReturn == guiMsgReturn){ + ShowEntry = 0; + RenderBackGround(); + DrawSelf(); + LoadList(); + DrawList(); + Check4Selected(); + } + }else{ + switch(aKey){ + case VK_UP: + if(Tag.Inx>0){ + ClearSelected(); + Tag.Inx--; + Items.Inx--; + Check4Selected(); + }else{ + if(Items.Inx>0){ + ClearSelected(); + Tag.Inx =0; + Items.Inx--; + Items.TopInx =Items.Inx; + DrawList(); + Check4Selected(); + } + } + if(LanguageEnCn==0)TextDigitRender4_24(svGridX[0] + 24, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, Items.Inx+1); + break; + case VK_DOWN: + if(Tag.Inx<9){ + if(Items.Inx<(dLINKAGE_MAX_COUNT-1)){ + ClearSelected(); + Tag.Inx++; + Items.Inx++; + Check4Selected(); + } + }else{ + Tag.Inx =9; + if(Items.Inx<(dLINKAGE_MAX_COUNT-1)){ + ClearSelected(); + Items.Inx++; + Items.TopInx =Items.Inx-9; + DrawList(); + Check4Selected(); + } + } + if(LanguageEnCn==0)TextDigitRender4_24(svGridX[0] + 24, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, Items.Inx+1); + break; + case VK_LEFT: + int GoLeft; + if(Items.Inx <1){ + ClearSelected(); + Items.Inx =2040; + Items.TopInx =2040; + Tag.Inx = 0; + DrawList(); + Check4Selected(); + }else{ + GoLeft = (Items.Inx / 10 -1) * 10; + if(GoLeft < 0){ + GoLeft = 0; + } + ClearSelected(); + Items.Inx =GoLeft; + Items.TopInx =GoLeft; + Tag.Inx = 0; + DrawList(); + Check4Selected(); + } + if(LanguageEnCn==0)TextDigitRender4_24(svGridX[0] + 24, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, Items.Inx+1); + break; + case VK_RIGHT: + int GoInx; + if(Items.Inx >= 2040){ + ClearSelected(); + Items.Inx =0; + Items.TopInx =0; + Tag.Inx = 0; + DrawList(); + Check4Selected(); + }else{ + GoInx = (Items.Inx / 10 +1) * 10; + if(GoInx >= dLINKAGE_MAX_COUNT){ + GoInx = dLINKAGE_MAX_COUNT-10; + if(GoInx <0)GoInx = 0; + } + ClearSelected(); + Items.Inx =GoInx; + Items.TopInx =GoInx; + Tag.Inx = 0; + DrawList(); + Check4Selected(); + } + if(LanguageEnCn==0)TextDigitRender4_24(svGridX[0] + 24, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, Items.Inx+1); + break; + case VK_EXECUTE: + ShowEntry = 1; + LinkageProgram.Init(); + LinkageProgram.EnterMethod = 1; + LinkageProgram.Show(); + LinkageProgram.InitPanel(); + LinkageProgram.Skip2Entry(Items.Inx+1); + break; + case VK_RETURN: + IsShow =0; + aMsg = guiMsgReturn; + break; + } + } + return aMsg; +} + +int TLinkageList::ExtRequst(unsigned char Prm) +{ + if(ShowEntry){ + LinkageProgram.ExtRequst(Prm); + } + IsShow = 0; return 0; +} + diff --git a/MyCode/Gui/LinkageList.h b/MyCode/Gui/LinkageList.h new file mode 100644 index 0000000..089f4af --- /dev/null +++ b/MyCode/Gui/LinkageList.h @@ -0,0 +1,108 @@ +#ifndef LINKAGELIST_H_ +#define LINKAGELIST_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" +#include "Gui.h" + +#pragma pack(push, 1) +class TLinkageList{ + public: + static constexpr unsigned short hList[12] = {32,32,32,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 11, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + unsigned int IsShow; + TStaticText TextDraw; + struct{ + short Inx; + short TopInx; + short Count; + }Items; + struct{ + short Inx; + short TopInx; + }Tag; + unsigned char ShowEntry; + public: + TLinkageList(){ + IsShow = 0; + } + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixText(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void DrawList(); + void ClearSelected(void); + void Check4Selected(void); + + void LoadList(); + int GetLnkMask(unsigned int aExp); + + int ExtRequst(unsigned char Prm); +}; + +#pragma pack(pop) + + +#endif + + + diff --git a/MyCode/Gui/LinkageProgram.cpp b/MyCode/Gui/LinkageProgram.cpp new file mode 100644 index 0000000..03e029f --- /dev/null +++ b/MyCode/Gui/LinkageProgram.cpp @@ -0,0 +1,2658 @@ +#include "RuntimeData.h" +#include "LinkageProgram.h" +#include "InterLink.h" +#include "DevMask.h" +#include "Runtime.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "HW_config.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +#define dAddrSdRam_LinkageInput (dAddrSdRam_Commom + 0xF0000) + +static const int GridX [5] = {4, 202, 400, 598, 796}; +static const int GridTop [12] = {143, 173, 202, 231, 260, 294, 323, 352, 381, 410, 439, 468}; +static const int GridBottom [12] = {172, 201, 230, 259, 288, 322, 351, 380, 409, 438, 467, 470}; + +//static const unsigned int clInput = clShallowGreen; +//static const unsigned int clOutput = clShallowRed; + +const char NumText[10][4] = {"0", "1", "2", "3", "4", "5", "6", "7", "8", "9"}; + +static const int xCount = 10; +static const int xEntry = 214; +static const int xActiveBy = 300; +static const int xMask = 450; +static const int xSave = 560; +static const int xDelete = 640; +static const int xNew = 720; +static const int xSelfActive = 560; + +static const int xEntryState = xEntry; +static const int xOperatState = 450; + +void TLinkageProgram::Init() +{ + IsShow = 0; + IsPermission =0; + PermissionCmd =0; + EnterMethod =0; + + ItemsIndex =0; + EditIndex =0; + OnEditing =0; + IsInputSymbol = 0; + IsViewList = 0; + IsNew = 0; + + ActX =0; + Inx =0; + eX =0; + eY =0; + eWhat = 0; + + ShouldBeClear = 0; + ShouldBeLoad = 0; + + CurrentPath0 = 0; + IsWhowingTip = 0; + +} + +void TLinkageProgram::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TLinkageProgram::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TLinkageProgram::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; +} + +void TLinkageProgram::DrawFixText() +{ + if(LanguageEnCn==0){ + if(EnterMethod){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "联动->编程查询->编程输入 "); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "联动->编程输入 "); + } + TextRender_string24(Lv.Grid.Left[0] + 60, Lv.Grid.Top[0] +6, clNearWhite, "/"); + TextRender_string24(Lv.Grid.Left[0] + 150, Lv.Grid.Top[0] +6, clNearWhite, "序号:"); + TextRender_string24(Lv.Grid.Left[0] + xActiveBy, Lv.Grid.Top[0] +6, clNearWhite, "执行:"); + TextRender_string24(Lv.Grid.Left[0] + xMask + 28, Lv.Grid.Top[0] +6, clNearWhite, "屏蔽"); + TextRender_string24(Lv.Grid.Left[0] + xSelfActive + 28, Lv.Grid.Top[0] +6, clNearWhite, "强制自动执行"); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +xSave, Lv.Grid.Top[1] + 4, 60, 30, 3, clNearWhite, "保存", 8, ItemColor); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +xDelete, Lv.Grid.Top[1] + 4, 60, 30, 3, clNearWhite, "删除", 8, ItemColor); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +xNew, Lv.Grid.Top[1] + 4, 60, 30, 3, clNearWhite, "新建", 8, ItemColor); + }else{ + if(EnterMethod){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Linkage->Overview->Expression Edit"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Linkage->Expression Edit"); + } + TextRender_string24(Lv.Grid.Left[0] + 60, Lv.Grid.Top[0] +6, clNearWhite, "/"); + TextRender_string24(Lv.Grid.Left[0] + 150, Lv.Grid.Top[0] +6, clNearWhite, "Index"); + TextRender_string24(Lv.Grid.Left[0] + xActiveBy, Lv.Grid.Top[0] +6, clNearWhite, "Mode"); + TextRender_string24(Lv.Grid.Left[0] + xMask + 28, Lv.Grid.Top[0] +6, clNearWhite, "Mask"); + TextRender_string24(Lv.Grid.Left[0] + xSelfActive + 28, Lv.Grid.Top[0] +6, clNearWhite, "Force Auto Run"); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +xSave, Lv.Grid.Top[1] + 4, 60, 30, 3, clNearWhite, "Save", 8, ItemColor); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +xDelete, Lv.Grid.Top[1] + 4, 60, 30, 3, clNearWhite, "Del ", 8, ItemColor); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +xNew, Lv.Grid.Top[1] + 4, 60, 30, 3, clNearWhite, "New ", 8, ItemColor); + } +} + +void TLinkageProgram::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; i= 10)break; + } + i = InputPageIndex * 10; + TVScrollBar::sDrawByPoint(206, 116, 215, 428, aClr, clGray, InputCount, 10, i); +} + + +int TLinkageProgram::SearchPort(unsigned char aP0) +{ + int y; + unsigned int aAddr; + unsigned char aType; + unsigned char P0; + unsigned char iCount = 0; + + P0 = aP0-1; + if(MainCtl.fData.Split.PortCount == 0){ + return iCount; + } + if(MainCtl.fData.Split.ExistTablePort[P0] == 0xA5){ + for(y=0 ;y<256; y++){ + if(Port[P0].ExistTable[y]){ + aType = Port[P0].dTypeTable[y]; + aAddr = dAddrSdRam_LinkageInput + (iCount * 4) ; + *(volatile unsigned char *)(aAddr + 0) = 0; + *(volatile unsigned char *)(aAddr + 1) = P0 +1; + *(volatile unsigned char *)(aAddr + 2) = y +1; + *(volatile unsigned char *)(aAddr + 3) = aType; + iCount ++; + } + } + return iCount; + } + return iCount; +} + +int TLinkageProgram::TrySearchStartPort() +{ + int i; + for(i=1; i<(dPORT_MAX_COUNT+1); i++){ + if(SearchPort(i)){ + LoadInputList(i); + CurrentPath0 = i; + return i; + } + } + return 0; +} + +int TLinkageProgram::TrySearchPrePort() +{ + unsigned char P0; + int i; + P0 = CurrentPath0-1; + for(i=0; i= dPORT_MAX_COUNT){ + P0 = dPORT_MAX_COUNT-1;; + }else{ + P0--; + } + if(MainCtl.fData.Split.ExistTablePort[P0] == 0xA5){ + return P0+1; + } + } + return 0; +} + +int TLinkageProgram::TrySearchNextPort() +{ + unsigned char P0; + int i; + P0 = CurrentPath0-1; + for(i=0; i= dPORT_MAX_COUNT){ + P0 = 0; + }else{ + P0++; + } + if(MainCtl.fData.Split.ExistTablePort[P0] == 0xA5){ + return P0+1; + } + } + return 0; +} + +void TLinkageProgram::TryDecValue(int IsForce) +{ + int aVal,i; + unsigned int index; + unsigned int Found; + Found = 0; + ShouldBeClear = 0; + ShouldBeLoad = 0; + if( (Inx == 0) || (IsForce) ){ + if(ExpCount){ + aVal = EEntry.Str.ToInteger(); + if( (aVal > dLINKAGE_MAX_COUNT) || (aVal < 1) ){ + aVal = 1; + } + index = aVal; + for(i=0; i dLINKAGE_MAX_COUNT) || (aVal < 1) ){ + aVal = 1; + } + index = aVal; + for(i=0; i dLINKAGE_MAX_COUNT)index=1; + if(ExistTabel[index -1]){ + //RestoreFromEdit(EditingLinkageIndex); + EditingLinkageIndex = index -1; + EEntry.Str.FromUInt4Dg(EditingLinkageIndex +1); + EEntry.SetPstTail(); + EEntry.Show(); + //EditML.Enable = 1; + //SetEditStart(EditingLinkageIndex); + EntryState = 1; + Found = 1; + ShouldBeLoad = 1; + break; + } + } + } + if(Found == 0){ + ExpCount = 0; + EntryState = 2; + EditingLinkageIndex = 0; + TextDigitRender4_24(Lv.Grid.Left[0] + xCount, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, ExpCount); + EEntry.Str.FromStr("0001"); + EEntry.SetPstTail(); + EEntry.Show(); + ShouldBeClear = 1; + //EditML.Enable = 0; + //EditML.Str.Clear(); + //EditML.Show(); + } + } + ShowEntryState(); +} + +void TLinkageProgram::FindNextExp() +{ + int aVal,i; + unsigned int index; + unsigned int Found; + Found = 0; + ShouldBeClear = 0; + ShouldBeLoad = 0; + if(ExpCount){ + aVal = EEntry.Str.ToInteger(); + if( (aVal > dLINKAGE_MAX_COUNT) || (aVal < 1) ){ + aVal = 1; + } + index = aVal; + for(i=0; i dLINKAGE_MAX_COUNT)index=1; + if(ExistTabel[index -1]){ + //RestoreFromEdit(EditingLinkageIndex); + EditingLinkageIndex = index -1; + EEntry.Str.FromUInt4Dg(EditingLinkageIndex +1); + EEntry.SetPstTail(); + EEntry.Show(); + EntryState = 1; + Found = 1; + ShouldBeLoad = 1; + break; + } + } + } + if(Found == 0){ + ExpCount = 0; + EntryState = 2; + EditingLinkageIndex = 0; + TextDigitRender4_24(Lv.Grid.Left[0] + xCount, Lv.Grid.Top[0] +6, clNearWhite, ItemColor, ExpCount); + EEntry.Str.FromStr("----"); + EEntry.SetPstTail(); + EEntry.Show(); + ShouldBeClear = 1; + } +} + +void TLinkageProgram::LoadExpCountFromRam() +{ + unsigned int i,x; + char Cz; + unsigned int SysLinkAddr; + TDMix Idf; + ExpCount = 0; + for(i=0; i= '0') && (EuCode.Str.Text[i] <= '9') ) || (EuCode.Str.Text[i] == '*') || (EuCode.Str.Text[i] == '#') ) { + + }else{ + EuCode.Str.Text[i] = '\0'; + EuCode.Str.Text[i+1] = '\0'; + break; + } + } + EuCode.Str.Text[8] = '\0'; + EuCode.Str.Text[9] = '\0'; + for(i=0; i<3; i++){ + EdType.Str.Text[i] = tEntry[eY][eX][i + 8]; + } + for(i=0; i<3; i++){ + if( (EdType.Str.Text[i] != '*') && ((EdType.Str.Text[i] < '0') || (EdType.Str.Text[i] > '9')) ){ + EdType.Str.Text[i] = '\0'; + EdType.Str.Text[i +1] = '\0'; + } + } + EdType.Str.Text[3] = '\0'; + EdType.Str.Text[4] = '\0'; + + if(eY < 4){ + IsInput = 1; + + if( (tEntry[eY][eX][11] >= '1') && (tEntry[eY][eX][11] <= '9') ){ + EInnerCount.Str.Text[0] = tEntry[eY][eX][11]; + EInnerCount.Str.Text[1] = '\0'; + }else{ + EInnerCount.Str.Text[0] = '\0'; + EInnerCount.Str.Text[1] = '\0'; + } + EInnerCount.SetPstTail(); + if(tEntry[eY][eX][12] == 'X'){ + tLogic = 'X'; + ELogic.Str.FromStr("与"); + }else + if(tEntry[eY][eX][12] == '+'){ + tLogic = '+'; + ELogic.Str.FromStr("或"); + }else{ + tLogic = ' '; + ELogic.Str.FromStr("xx"); + } + if( (tEntry[eY][eX][13] >= '1') && (tEntry[eY][eX][13] <= '9') ){ + EInCount.Str.Text[0] = tEntry[eY][eX][13]; + EInCount.Str.Text[1] = '\0'; + }else{ + EInCount.Str.Text[0] = '\0'; + EInCount.Str.Text[1] = '\0'; + } + EInCount.SetPstTail(); + }else + if(eY < 8){ + IsInput = 0; + EDelay.Str.Text[0] = tEntry[eY][eX][11]; + EDelay.Str.Text[1] = tEntry[eY][eX][12]; + EDelay.Str.Text[2] = tEntry[eY][eX][13]; + for(i=0; i<3; i++){ + if( (EDelay.Str.Text[i] < '0') || (EDelay.Str.Text[i] > '9') ){ + EDelay.Str.Text[i] = '\0'; + EDelay.Str.Text[i +1] = '\0'; + } + } + EDelay.Str.Text[3] = '\0'; + EDelay.Str.Text[4] = '\0'; + } +} + +int TLinkageProgram::TryRestoreFromEdit() +{ + //EntryChar + unsigned int i; + for(i=0; i<8; i++){ + if( ( (EuCode.Str.Text[i] < '0') || (EuCode.Str.Text[i] > '9') ) && (EuCode.Str.Text[i] != '*') ){ + return 1; + } + } + if (EuCode.Str.Text[8] != 0){ + return 1; + } + + if(IsInput){ + for(i=0; i<3; i++){ + if( (EdType.Str.Text[i] < '0') || (EdType.Str.Text[i] > '9') ){ + return 1; + } + } + } + if (EdType.Str.Text[3] != 0){ + return 1; + } + if(IsInput){ + + }else{ + if(EuCode.Str.Text[0] != '*'){ + i = TMyString::sToInteger(EdType.Str.Text); + if( (i <0) || ( i > 254) ){ + return 1; + } + } + } + + if(IsInput){ + if( (EInnerCount.Str.Text[0] < '1') || (EInnerCount.Str.Text[0] > '9') || (EInnerCount.Str.Text[1] != 0 )){ + return 1; + } + if( (tLogic != 'X') && (tLogic != '+') ){ + return 1; + } + if(tLogic == 'X'){ + if( (EInCount.Str.Text[0] < '1') || (EInCount.Str.Text[0] > '9') ){ + return 1; + } + } + }else{ + if(EDelay.Str.Text[0] != 0){ + if( (EDelay.Str.Text[0] < '0') || (EDelay.Str.Text[0] > '9') ){ + return 1; + } + if(EDelay.Str.Text[1] != 0){ + if( (EDelay.Str.Text[1] < '0') || (EDelay.Str.Text[1] > '9') ){ + return 1; + } + if(EDelay.Str.Text[2] != 0){ + if( (EDelay.Str.Text[2] < '0') || (EDelay.Str.Text[2] > '9') ){ + return 1; + } + } + } + i = TMyString::sToInteger(EDelay.Str.Text); + if( (i < 0) || ( i > 600 ) ){ + return 1; + } + } + + } + return 0; +} + +void TLinkageProgram::RestoreFromEdit() +{ + unsigned int i,x,y, NotUse, NewParCnt; + ParCntHasChanged = 0; + for(i=0; i<18; i++)tEntry[eY][eX][i] = '\0'; + for(i=0; i<8; i++){ + tEntry[eY][eX][i] = EuCode.Str.Text[i]; + } + TMyString::sFillFixLen(tEntry[eY][eX], 8); + for(i=0; i<3; i++){ + tEntry[eY][eX][i + 8] = EdType.Str.Text[i]; + } + TMyString::sFillFixLen(tEntry[eY][eX], 11); + if(eY<4){ + if( (EInnerCount.Str.Text[0] >= '1') && ((EInnerCount.Str.Text[0] <= '9')) ){ + tEntry[eY][eX][11] = EInnerCount.Str.Text[0]; + }else{ + tEntry[eY][eX][11] = ' '; + } + + if(tLogic == 'X'){ + tEntry[eY][eX][12] = 'X'; + }else + if(tLogic == '+'){ + tEntry[eY][eX][12] = '+'; + }else{ + tEntry[eY][eX][12] = ' '; + } + + if(tLogic == 'X'){ + if( (EInCount.Str.Text[0] >= '1') && ((EInCount.Str.Text[0] <= '9')) ){ + tEntry[eY][eX][13] = EInCount.Str.Text[0]; + NewParCnt = EInCount.Str.Text[0] -'0'; + }else{ + tEntry[eY][eX][13] = ' '; + NewParCnt = 1; + } + if(NewParCnt != ParCnt){ + ParCnt = NewParCnt; + ParCntHasChanged = 1; + } + }else{ + tEntry[eY][eX][13] = ' '; + } + + if( (tEntry[eY][eX][0] != '*') && (tEntry[eY][eX][0] != '#') ){ + if( (tEntry[eY][eX][0] < '0') || (tEntry[eY][eX][0] > '9') ){ + tEntry[eY][eX][11] = ' '; + tEntry[eY][eX][12] = ' '; + tEntry[eY][eX][13] = ' '; + } + } + + TMyString::sFillFixLen(tEntry[eY][eX], 14); + tEntry[eY][eX][14] = '\0'; + tEntry[eY][eX][15] = '\0'; + }else + if(eY<8){ + tEntry[eY][eX][11] = EDelay.Str.Text[0]; + tEntry[eY][eX][12] = EDelay.Str.Text[1]; + tEntry[eY][eX][13] = EDelay.Str.Text[2]; + TMyString::sFillFixLen(tEntry[eY][eX], 14); + tEntry[eY][eX][14] = '\0'; + tEntry[eY][eX][15] = '\0'; + } +} + +void TLinkageProgram::RedrawParCnt() +{ + unsigned int y, x; + if(ParCntHasChanged == 0)return; + for(y=0; y<4; y++){ + for(x=0; x<4; x++){ + if( ( (tEntry[y][x][0] >= '0') && (tEntry[y][x][0] <= '9') ) || (tEntry[y][x][0] == '*') || (tEntry[y][x][0] == '#') ) { + if(tEntry[y][x][12] == 'X'){ + if((ParCnt > 0) && (ParCnt < 10)){ + tEntry[y][x][13] = ParCnt + '0'; + }else{ + tEntry[y][x][13] = ' '; + } + ShowOneGrid(x,y); + } + } + } + } +} + +void TLinkageProgram::ClearGridSelected() +{ + unsigned int x, y, aClr; + int tWidth, tHeigth, InxY; + if(eY < 4){ + aClr = ItemColor; + InxY = eY +1; + }else{ + aClr = ItemColor; + InxY = eY +2; + } + x = GridX[eX] + 1; + y = GridTop[InxY] +1; + tWidth = GridX[eX+1] -GridX[eX] -2; + tHeigth = GridBottom[InxY] - GridTop[InxY] -1; + + VertLineRender (x, y, tHeigth, aClr); + VertLineRender (x+1, y, tHeigth, aClr); + VertLineRender (x + tWidth -3, y, tHeigth, aClr); + VertLineRender (x + tWidth -2, y, tHeigth, aClr); + + HorizLineRender (x, GridTop[InxY]+1, tWidth, aClr); + HorizLineRender (x, GridTop[InxY]+2, tWidth, aClr); + HorizLineRender (x, GridBottom[InxY]-1, tWidth, aClr); + HorizLineRender (x, GridBottom[InxY]-0, tWidth, aClr); +} + +void TLinkageProgram::DrawSelectedGrid(unsigned int oldX, unsigned int oldY, unsigned int NewX, unsigned int NewY) +{ + unsigned int x, y, aClr; + int tWidth, tHeigth, InxY; + x = GridX[oldX] + 1; + if(oldY < 4){ + aClr = ItemColor; + InxY = oldY +1; + }else{ + aClr = ItemColor; + InxY = oldY +2; + } + x = GridX[oldX] + 1; + y = GridTop[InxY] +1; + tWidth = GridX[oldX+1] -GridX[oldX] -2; + tHeigth = GridBottom[InxY] - GridTop[InxY] -1; + + VertLineRender (x, y, tHeigth, aClr); + VertLineRender (x+1, y, tHeigth, aClr); + VertLineRender (x + tWidth -3, y, tHeigth, aClr); + VertLineRender (x + tWidth -2, y, tHeigth, aClr); + + HorizLineRender (x, GridTop[InxY]+1, tWidth, aClr); + HorizLineRender (x, GridTop[InxY]+2, tWidth, aClr); + HorizLineRender (x, GridBottom[InxY]-1, tWidth, aClr); + HorizLineRender (x, GridBottom[InxY]-0, tWidth, aClr); + + x = GridX[NewX] + 1; + if(NewY < 4){ + InxY = NewY +1; + }else{ + InxY = NewY +2; + } + x = GridX[NewX] + 1; + y = GridTop[InxY] +1; + tWidth = GridX[NewX+1] -GridX[NewX] -2; + tHeigth = GridBottom[InxY] - GridTop[InxY] -1; + aClr = clBlue; + VertLineRender (x, y, tHeigth, aClr); + VertLineRender (x+1, y, tHeigth, aClr); + VertLineRender (x + tWidth -3, y, tHeigth, aClr); + VertLineRender (x + tWidth -2, y, tHeigth, aClr); + + HorizLineRender (x, GridTop[InxY]+1, tWidth, aClr); + HorizLineRender (x, GridTop[InxY]+2, tWidth, aClr); + HorizLineRender (x, GridBottom[InxY]-1, tWidth, aClr); + HorizLineRender (x, GridBottom[InxY]-0, tWidth, aClr); +} + +void TLinkageProgram::ShowOneGrid(unsigned int x, unsigned int y) +{ + unsigned int pX, pY, i; + int InxY; + if(y<4){ + InxY = y+1; + }else{ + InxY = y+2; + } + pX = GridX[x] + 4; + pY = GridTop[InxY] + 2; + for(i=0; i<18; i++)PathText[i] = '\0'; + for(i=0; i<8; i++){ + PathText[i] = tEntry[y][x][i]; + } + TMyString::sFillFixLen(PathText, 8); + PathText[8] = ' '; + for(i=0; i<3; i++){ + PathText[i+9] = tEntry[y][x][i+8]; + } + TMyString::sFillFixLen(PathText, 12); + if(y<4){ + PathText[12] = ' '; + PathText[13] = tEntry[y][x][11]; + PathText[14] = tEntry[y][x][12]; + PathText[15] = tEntry[y][x][13]; + TMyString::sFillFixLen(PathText, 16); + PathText[16] = '\0'; + PathText[17] = '\0'; + }else + if(y<8){ + PathText[12] = ' '; + PathText[13] = tEntry[y][x][11]; + PathText[14] = tEntry[y][x][12]; + PathText[15] = tEntry[y][x][13]; + PathText[16] = '\0'; + PathText[17] = '\0'; + } + + TMyString::sFillFixLen(PathText, 16); + PathText[16] = '\0'; + PathText[17] = '\0'; + + TextRender_string24(pX, pY ,clNearWhite, ItemColor, PathText); +} + +void TLinkageProgram::ShowAllGrid() +{ + unsigned int x, y; + for(y=0; y<8; y++)for (x=0; x<4; x++)ShowOneGrid(x,y); +} + +void TLinkageProgram::ShowEntryState() +{ + if( EntryState == 0){ + if(LanguageEnCn==0)TextRender_string24(xEntryState, Lv.Grid.Top[1] +2, clNearWhite, ItemColor, "编号超限 "); + else TextRender_string24(xEntryState, Lv.Grid.Top[1] +2, clNearWhite, ItemColor, "Index Exceeds "); + }else + if( EntryState == 1){ + if(LanguageEnCn==0)TextRender_string24(xEntryState, Lv.Grid.Top[1] +2, clNearWhite, ItemColor, "已配置联动"); + else TextRender_string24(xEntryState, Lv.Grid.Top[1] +2, clNearWhite, ItemColor, "Valid Expression"); + }else + if( EntryState == 2){ + if(LanguageEnCn==0)TextRender_string24(xEntryState, Lv.Grid.Top[1] +2, clNearWhite, ItemColor, "新联动 "); + else TextRender_string24(xEntryState, Lv.Grid.Top[1] +2, clNearWhite, ItemColor, "New Expression "); + } +} + +int TLinkageProgram::NewEntry() +{ + int i, FoundEmpty; + FoundEmpty = 0; + for(i=0; i '9') ){ + Uniquely = 0; + break; + } + } + Got = 0; + iVal = EuCode.Str.ToInteger(); + if(Uniquely && (iVal>0) ){ + for(tP0=0; tP0= Port[tP0].UserCodeMin) && (iVal<= Port[tP0].UserCodeMax) ){ + for(tP1=0; tP1<250; tP1++){ + if(iVal == Port[tP0].UcList[tP1].Full){ + if(Port[tP0].AssignType[tP1] != 0){ + tType = Port[tP0].AssignType[tP1]; + }else{ + tType = Port[tP0].dTypeTable[tP1]; + } + Got = 1; + } + } + } + } + if( (Got == 0) && (aIsInput == 0) ){ + for(tP0=0; tP0 dLINKAGE_MAX_COUNT)return;; + EditingLinkageIndex = aEntry -1; + EEntry.Str.FromUInt4Dg(aEntry); + EEntry.SetPstTail(); + EEntry.Show(); + + if(ExistTabel[EditingLinkageIndex]){ + EntryState = 1; + LoadExp(EditingLinkageIndex); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + }else{ + ShouldBeClear = 1; + EntryState = 2; + LoadExpVoid(); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + ActX = 1; + ClearPanelSelected(); + DrawSelectedGrid(eX, eY, eX, eY); + ShowEntryState(); +} + +int TLinkageProgram::CheckUserCodeOk() +{ + int iVal, IncludeAst; + if(EuCode.Str.GetLength() != 8){ + return 0; + } + for(int i=0;i<8;i++){ + if( ((EuCode.Str.Text[i] < '0') || (EuCode.Str.Text[i] >'9')) && (EuCode.Str.Text[i] != '*') )return 0; + } + IncludeAst = 0; + for(int i=0;i<8;i++){ + if(EuCode.Str.Text[i] == '*')IncludeAst =1; + } + if(IncludeAst == 0){ + iVal = EuCode.Str.ToInteger(); + if(iVal == 0)return 0; + } + return 1; +} + +int TLinkageProgram::CheckTypeOk() +{ + int iVal; + if(EdType.Str.GetLength() != 3)return 0; + if(IsInput){ + if( (EdType.Str.Text[0]=='*') or (EdType.Str.Text[1]=='*') or (EdType.Str.Text[2]=='*') )return 0; + iVal = EdType.Str.ToInteger(); + if( iVal>0 and iVal<256){ + return 1; + } + }else{ + if( (EdType.Str.Text[0]=='*') and (EdType.Str.Text[1]=='*') and (EdType.Str.Text[2]=='*'))return 1; + if((EdType.Str.Text[0]=='*') or (EdType.Str.Text[1]=='*') or (EdType.Str.Text[2]=='*'))return 0; + iVal = EdType.Str.ToInteger(); + if(iVal>0 && iVal<256){ + return 1; + } + } + return 0; +} + +TGuiMsgReturn TLinkageProgram::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone, PmsRtnMsg; + int iVal; + unsigned char NewPath0; + unsigned char LoadKey; + unsigned char tType; + char LastChr; + + if(IsWhowingTip){ + if(aKey == VK_EXECUTE){ + Inx = 0; + RenderGridBack(); + InitPanel(); + IsWhowingTip = 0; + if(ShouldBeClear){ + LoadExpVoid(); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + if(ShouldBeLoad){ + LoadExp(EditingLinkageIndex); + ShowAllGrid(); + } + }else + if(aKey == VK_RETURN){ + return guiMsgReturn; + } + }else + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + if(ActX >2){ + ActX = 0; + } + if(ActX == 0){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Inx == 0){ + if(aKey == VK_RIGHT){ + if( EEntry.Str.GetEndPst() <= EEntry.Pst){ + ClearSelected(); + Inx =1; + Check4Selected(); + } + } + if(Inx == 0){ + EEntry.KeyIn(aKey); + EEntry.ReDraw(); + iVal = EEntry.Str.ToInteger(); + + if(iVal > dLINKAGE_MAX_COUNT){ + EntryState = 0; + }else + if(iVal <1 ){ + EntryState = 0; + }else{ + EditingLinkageIndex = iVal -1; + if(ExistTabel[EditingLinkageIndex]){ + ShouldBeLoad = 1; + EntryState = 1; + LoadExp(EditingLinkageIndex); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + }else{ + ShouldBeClear = 1; + EntryState = 2; + LoadExpVoid(); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + } + ShowEntryState(); + } + }else{ + if(aKey == VK_LEFT){ + if( (Inx > 0) && (Inx<4) ){ + ClearSelected(); + Inx --; + Check4Selected(); + }else + if( (Inx == 5) || ( Inx == 6) ){ + ClearSelected(); + Inx --; + Check4Selected(); + } + }else + if(aKey == VK_RIGHT){ + if( (Inx==1) || (Inx==2) || (Inx==4) || (Inx==5) ){ + ClearSelected(); + Inx ++; + Check4Selected(); + } + } + } + break; + case VK_UP: + if(Inx == 0){ + TryIncValue(0); + if(EntryState == 2){ + LoadExpVoid(); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + if(EntryState == 1){ + LoadExp(EditingLinkageIndex); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + }else + if(Inx > 3){ + ClearSelected(); + Inx =3; + Check4Selected(); + } + break; + case VK_DOWN: + if(Inx==0){ + TryDecValue(0); + if(EntryState == 2){ + LoadExpVoid(); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + }else + if(EntryState == 1){ + LoadExp(EditingLinkageIndex); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + }else + if( (Inx==4) || (Inx==5) || (Inx==6) ){ + ActX = 1; + ClearSelected(); + DrawSelectedGrid(eX, eY, eX, eY); + }else + if( (Inx==1) || (Inx==2) || (Inx==3)){ + ClearSelected(); + Inx =4; + Check4Selected(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + if(Inx == 0){ + TryDecValue(0); + if(EntryState == 2){ + LoadExpVoid(); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + }else + if(EntryState == 1){ + LoadExp(EditingLinkageIndex); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + }else + if(Inx == 1){ + if(DoStop){ + DoStop = 0; + }else{ + DoStop = 1; + } + DrawActiveByStartStop(); + }else + if(Inx == 2){ + if(IsMask){ + IsMask = 0; + }else{ + IsMask = 1; + } + DrawIsMask(); + }else + if(Inx == 3){ + if(IsSelfActive){ + IsSelfActive = 0; + }else{ + IsSelfActive = 1; + } + DrawIsSelfActive(); + } + break; + case dfKEY_QUERY: //0x71 // Key value for QUERY + if(Inx == 0){ + ClearSelected(); + Inx =1; + Check4Selected(); + } + break; + case VK_TAB: + ActX = 1; + ClearSelected(); + DrawSelectedGrid(eX, eY, eX, eY); + break; + case VK_EXECUTE: + if(Inx == 1){ + if(DoStop){ + DoStop = 0; + }else{ + DoStop = 1; + } + DrawActiveByStartStop(); + }else + if(Inx == 2){ + if(IsMask){ + IsMask = 0; + }else{ + IsMask = 1; + } + DrawIsMask(); + }else + if(Inx == 3){ + if(IsSelfActive){ + IsSelfActive = 0; + }else{ + IsSelfActive = 1; + } + DrawIsSelfActive(); + }else + if(Inx == 4){ + //Save + if(EntryState){ + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 16, 400, 140, 3); + } + } + }else + if(Inx == 5){ + //Delete + if( EntryState ==1 ){ + PermissionCmd = 0; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 16, 400, 140, 3); + } + }else + if(EntryState == 2){ + LoadExpVoid(); + DrawIsMask(); + DrawActiveByStartStop(); + DrawIsSelfActive(); + ShowAllGrid(); + } + }else + if(Inx == 6){ + //New + if(NewEntry() == 0){ + EntryState = 2; + ActX = 1; + ClearPanelSelected(); + DrawSelectedGrid(eX, eY, eX, eY); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + }else + if(ActX == 1){ + switch(aKey){ + case VK_LEFT: + if (eX >0){ + eX--; + DrawSelectedGrid(eX+1, eY, eX, eY); + } + break; + case VK_RIGHT: + if (eX <3){ + eX++; + DrawSelectedGrid(eX-1, eY, eX, eY); + } + break; + case VK_UP: + if( eY >0){ + eY--; + DrawSelectedGrid(eX, eY+1, eX, eY); + }else{ + ActX = 0; + Inx = 4; + ClearGridSelected(); + Check4Selected(); + } + break; + case VK_DOWN: + if( eY <7){ + eY++; + DrawSelectedGrid(eX, eY-1, eX, eY); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + //Save Here + + break; + case VK_TAB: + ActX = 0; + Inx = 4; + ClearGridSelected(); + Check4Selected(); + break; + case VK_DELETE: + EntryClear(); + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DECIMAL: + case VK_OEM_2: + case VK_EXECUTE: + ActX = 2; + eWhat = 0; + ShowItemEdit(); + CheckEWhatWhoActive(); + RedrawEEdit(); + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + }else + if(ActX == 2){ + if(IsInput){ + switch(aKey){ + case dfKEY_ENCN: + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + case VK_DECIMAL: + case VK_OEM_2: + if(eWhat == 0){ + EuCode.KeyIn(aKey); + EuCode.Show(); + CheckUserCodeUniquely(1); + }else + if(eWhat == 1){ + if( (aKey != VK_DECIMAL) && (aKey != VK_OEM_2)){ + EdType.KeyIn(aKey); + CheckShowDevType(); + } + }else + if(eWhat == 2){ + if( (aKey != VK_DECIMAL) && (aKey != VK_OEM_2) ) { + EInnerCount.KeyIn(aKey); + EInnerCount.Show(); + } + }else + if(eWhat == 3){ + if(tLogic == '+')tLogic = 'X'; + else tLogic = '+'; + if(tLogic == '+')if(LanguageEnCn==0)ELogic.Str.FromStr("或"); else ELogic.Str.FromStr("or"); + else if (tLogic == 'X')if(LanguageEnCn==0)ELogic.Str.FromStr("与"); else ELogic.Str.FromStr("And"); + else ELogic.Str.FromStr(" "); + ELogic.Show(); + }else + if(eWhat == 4){ + if( (aKey != VK_DECIMAL) && (aKey != VK_OEM_2) ) { + EInCount.KeyIn(aKey); + EInCount.Show(); + } + } + break; + case VK_UP: + if(eWhat >0){ + eWhat--; + CheckEWhatWhoActive(); + RedrawEEdit(); + } + break; + case VK_DOWN: + if(eWhat <4){ + eWhat++; + CheckEWhatWhoActive(); + RedrawEEdit(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + + break; + case dfKEY_QUERY: //0x71 // Key value for QUERY + break; + case VK_EXECUTE: + if(TryRestoreFromEdit() == 0){ + RestoreFromEdit(); + RedrawParCnt(); + } + ActX = 1; + RenderGridBack(); + DrawGridLine(); + ShowAllGrid(); + DrawSelectedGrid(eX, eY, eX, eY); + break; + case VK_RETURN: + ActX = 1; + RenderGridBack(); + DrawGridLine(); + ShowAllGrid(); + DrawSelectedGrid(eX, eY, eX, eY); + break; + } + }else{ + switch(aKey){ + case dfKEY_ENCN: + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + case VK_DECIMAL: + case VK_OEM_2: + if(eWhat == 0){ + EuCode.KeyIn(aKey); + EuCode.Show(); + CheckUserCodeUniquely(0); + }else + if(eWhat == 1){ + if(aKey != VK_OEM_2){ + EdType.KeyIn(aKey); + CheckShowDevType(); + } + }else{ + if( (aKey != VK_DECIMAL) && (aKey != VK_OEM_2) ){ + EDelay.KeyIn(aKey); + EDelay.Show(); + } + } + break; + case VK_UP: + if(eWhat >0){ + eWhat--; + CheckEWhatWhoActive(); + RedrawEEdit(); + } + break; + case VK_DOWN: + if(eWhat <2){ + eWhat++; + CheckEWhatWhoActive(); + RedrawEEdit(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + + break; + case dfKEY_QUERY: //0x71 // Key value for QUERY + break; + case VK_EXECUTE: + if(CheckUserCodeOk() && CheckTypeOk()){ + if(TryRestoreFromEdit() == 0){ + RestoreFromEdit(); + } + ActX = 1; + RenderGridBack(); + DrawGridLine(); + ShowAllGrid(); + DrawSelectedGrid(eX, eY, eX, eY); + }else{ + + } + break; + case VK_RETURN: + ActX = 1; + RenderGridBack(); + DrawGridLine(); + ShowAllGrid(); + DrawSelectedGrid(eX, eY, eX, eY); + break; + } + } + } + } + return aMsg; +} + +void TLinkageProgram::CheckShowDevType() +{ + int iVal; + if(EdType.Str.GetLength() != 3){ + EdType.SelectedColor = clRed; + if(LanguageEnCn==0)STextDType.SetText("输入不完整",24); + else STextDType.SetText("Dev Invalid",24); + }else{ + if(IsInput){ + iVal = EdType.Str.ToInteger(); + if( (iVal > 0) && (iVal < 256)){ + EdType.SelectedColor = clBlue; + if(LanguageEnCn==0){ + STextDType.SetText(StrTypeShortName[iVal],24); + }else{ + STextDType.SetText(StrTypeShortNameEn[iVal],24); + } + }else{ + EdType.SelectedColor = clRed; + if(LanguageEnCn==0)STextDType.SetText( "类型超出范围",24); + else STextDType.SetText( "Dev Type Invalid",24); + } + }else{ + if(EdType.Str.Text[0] == '*' and EdType.Str.Text[1]=='*' and EdType.Str.Text[2]=='*' and EdType.Str.Text[3]=='\0'){ + EdType.SelectedColor = clBlue; + if(LanguageEnCn==0){ + STextDType.SetText("所有输出类型",24); + }else{ + STextDType.SetText("All Out Type",24); + } + }else + if(EdType.Str.Text[0]=='*' or EdType.Str.Text[1]=='*' or EdType.Str.Text[2]=='*'){ + EdType.SelectedColor = clRed; + if(LanguageEnCn==0)STextDType.SetText( "类型超出范围",24); + else STextDType.SetText( "Dev Type Invalid",24); + }else{ + iVal = EdType.Str.ToInteger(); + if( (iVal > -1) && (iVal < 256)){ + EdType.SelectedColor = clBlue; + if(LanguageEnCn==0){ + if(iVal == 0){ + EdType.SelectedColor = clRed; + STextDType.SetText("无效类型",24); + }else{ + STextDType.SetText(StrTypeShortName[iVal],24); + } + }else{ + if(iVal == 0){ + EdType.SelectedColor = clRed; + STextDType.SetText("Invalid Type",24); + }else{ + STextDType.SetText(StrTypeShortNameEn[iVal],24); + } + } + }else{ + EdType.SelectedColor = clRed; + if(LanguageEnCn==0)STextDType.SetText( "类型超出范围",24); + else STextDType.SetText( "Dev Type Invalid",24); + } + } + } + } + EdType.Show(); + STextDType.Show(); +} + +void TLinkageProgram::ShowItemEdit() +{ + + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int clr; + unsigned int x, y, x2, y2, w, h; + int iVal; + + if(eY <4)IsInput =1; else IsInput = 0; + + if(IsInput){ + x = 200; + x2 = 600; + y = 150; + y2 = 430; + w = 400; + h = 280; + }else{ + x = 200; + x2 = 600; + y = 150; + y2 = 350; + w = 400; + h = 200; + } + + VertLineRender(x, y, h -1, 0xFFFFFFFF); + VertLineRender(x2 -1, y +1, h -2, 0xFF808080); + VertLineRender(x2, y, h, 0xFF404040); + + HorizLineRender(x, y, w - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, w- 2, 0xFF808080); + HorizLineRender(x, y2, w, 0xFF404040); + + RectFillRender(x+1, y+2, x2-3, y+37, clNavy); + RectFillRender(x+1, y+38, x2-3, y2-2, clFrmFace); + if(LanguageEnCn==0){ + if (IsInput) + TextRender_string24(x +8, y + 6,clNearWhite, "编辑条目细节-输入"); + else + TextRender_string24(x +8, y + 6,clNearWhite, "编辑条目细节-输出"); + TextRender_string24(x +8, y + 48,clNearBlack, "设备编码:"); + TextRender_string24(x +8, y + 88,clNearBlack, "设备类型:"); + + if (IsInput){ + TextRender_string24(x +8, y +168,clNearBlack, "逻辑关系:"); + }else{ + TextRender_string24(x +8, y +128,clNearBlack, "延时时间:"); + } + }else{ + if (IsInput) + TextRender_string24(x +8, y + 6,clNearWhite, "Edit-Input"); + else + TextRender_string24(x +8, y + 6,clNearWhite, "Edit-Output"); + TextRender_string24(x +8, y + 48,clNearBlack, "AuxID:"); + TextRender_string24(x +8, y + 88,clNearBlack, "Dev Type:"); + + if (IsInput){ + TextRender_string24(x +8, y +168,clNearBlack, "Logical:"); + }else{ + TextRender_string24(x +8, y +128,clNearBlack, "Delay Sec:"); + } + } + + EuCode.Init(x+120,y+ 48,120,30,0,0,clNearBlack,clNearWhite); + EuCode.SetMaxLen(8); + EuCode.Str.FromStr("xxxxxxxx"); + EuCode.Pst = 7; + EdType.Init(x+120,y+ 88,46,30,0,0,clNearBlack,clNearWhite); + EdType.SetMaxLen(3); + EdType.Str.FromStr("xxx"); + EdType.Pst = 2; + + EInnerCount.Init(x+120,y+128,46,30,0,0,clNearBlack,clNearWhite); + + if(IsInput){ + ELogic.Init(x+120,y+168,46,30,0,0,clNearBlack,clNearWhite); + ELogic.SetMaxLen(2); + if(LanguageEnCn==0)ELogic.Str.FromStr("或"); + else ELogic.Str.FromStr("or"); + ELogic.IsShowCursor = 0; + ELogic.Pst = 1; + }else{ + EDelay.Init(x+120,y+128,46,30,0,0,clNearBlack,clNearWhite); + EDelay.SetMaxLen(3); + EDelay.Str.FromStr("600"); + EDelay.IsShowCursor = 1; + EDelay.Pst = 2; + } + + EInCount.Init(x+120,y+208,46,30,0,0,clNearBlack,clNearWhite); + + SetEditStart(); + EuCode.SetPstTail(); + EdType.SetPstTail(); + EuCode.Show(); + EdType.Show(); + if(IsInput){ + ELogic.SetPstTail(); + ELogic.Show(); + EInnerCount.SetMaxLen(1); + EInCount.SetMaxLen(1); + EInnerCount.SetPstTail(); + EInCount.SetPstTail(); + + EInnerCount.Show(); + EInCount.Show(); + }else{ + EDelay.SetPstTail(); + EDelay.Show(); + } + + STextDType.Init(x + 170, y+ 88, 200, 30,0,0,clNearBlack,clFrmFace); + CheckShowDevType(); + + if(LanguageEnCn==0){ + if(IsInput){ + TextRender_string24(x +8, y +128,clNearBlack, "内部数量:"); TextRender_string24(x +168, y +128,clNearBlack, "范围:1~9"); + TextRender_string24(x +8, y +208,clNearBlack, "输入数量:"); TextRender_string24(x +168, y +208,clNearBlack, "范围:1~9"); + TextRender_string24(x +22, y +248,clNearBlack, "确认键执行修改,返回键放弃修改"); + }else{ + TextRender_string24(x +22, y +168,clNearBlack, "确认键执行修改,返回键放弃修改"); + } + }else{ + if(IsInput){ + TextRender_string24(x +8, y +128,clNearBlack, "Internal:"); + TextRender_string24(x +168, y +128,clNearBlack, "Scope:1..9"); + TextRender_string24(x +8, y +208,clNearBlack, "And Num:"); + TextRender_string24(x +168, y +208,clNearBlack, "Scope:1..9"); + TextRender_string24(x +22, y +248,clNearBlack, "Key OK Modify, Or Return"); + }else{ + TextRender_string24(x +22, y +168,clNearBlack, "Key OK Modify, Or Return"); + } + } + + if(IsInput){ + x2 = x + 170; + y2 = y + 168 + 6; + y2 += 9; + h =3; + for(w=0; w<10; w++){ + VertLineRender(x2, y2, h, clNearBlack); + y2--; + h += 2; + x2++; + } + + x2 = x + 170 + 14; + y2 = y + 168 + 6; + y2 += 0; + h =21; + for(w=0; w<10; w++){ + VertLineRender(x2, y2, h, clNearBlack); + x2++; + h -= 2; + y2++; + } + } +} + +void TLinkageProgram::RedrawEEdit() +{ + EuCode.Show(); + EdType.Show(); + if(IsInput){ + EInnerCount.Show(); + ELogic.Show(); + EInCount.Show(); + }else{ + EDelay.Show(); + } +} + +void TLinkageProgram::CheckEWhatWhoActive() +{ + EuCode.Selected = 0; + EdType.Selected = 0; + EInnerCount.Selected = 0; + ELogic.Selected = 0; + EInCount.Selected = 0; + EDelay.Selected = 0; + if(eWhat == 0) EuCode.Selected = 1; + else if(eWhat == 1) EdType.Selected = 1; + else{ + if(IsInput){ + if(eWhat == 2)EInnerCount.Selected = 1; + else if(eWhat == 3)ELogic.Selected = 1; + else if(eWhat == 4)EInCount.Selected = 1; + }else{ + EDelay.Selected = 1; + } + } +} + +void TLinkageProgram::RedrawItemEdit() +{ + +} + +void TLinkageProgram::LoadExp(unsigned int aExp) +{ + unsigned int x,y,i; + unsigned int SysLinkAddr; + unsigned int aAddr4Char; + unsigned int aAddr4Int; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + + if(*(volatile unsigned char *)(SysLinkAddr + 4) == 'M')IsMask =1; else IsMask=0; + if(*(volatile unsigned char *)(SysLinkAddr + 5) == 'S')DoStop =1; else DoStop=0; + if(*(volatile unsigned char *)(SysLinkAddr + 6) == 'F')IsSelfActive =1; else IsSelfActive=0; + for(y=0; y<8; y++){ + for(x=0; x<4; x++){ + aAddr4Char = SysLinkAddr + (y * 4 * 16) + (x * 16) + 16; + for(i=0; i<16; i++){ + tEntry[y][x][i] = *(volatile unsigned char *)(aAddr4Char++); + } + tEntry[y][x][16] = '\0'; + tEntry[y][x][17] = '\0'; + } + } +} + +void TLinkageProgram::LoadExpVoid() +{ + unsigned int x,y,i; + for(y=0; y<8; y++){ + for(x=0; x<4; x++){ + for(i=0; i<16; i++){ + tEntry[y][x][i] = '\0'; + } + tEntry[y][x][16] = '\0'; + tEntry[y][x][17] = '\0'; + } + } + IsMask = 0; + DoStop = 0; + IsSelfActive = 0; +} + +void TLinkageProgram::RestoreExp(unsigned int aExp) +{ + unsigned int x,y,i; + unsigned int SysLinkAddr; + unsigned int aAddr4Char; + unsigned int aAddr4Int; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + + aAddr4Char = SysLinkAddr; + *(volatile unsigned char *)(aAddr4Char++) = 'T'; + *(volatile unsigned char *)(aAddr4Char++) = 'R'; + *(volatile unsigned char *)(aAddr4Char++) = 'U'; + *(volatile unsigned char *)(aAddr4Char++) = 'E'; + + SetLnkMask(aExp); + SetLnkDoStop(aExp); + SetLnkSelfActive(aExp); + + for(y=0; y<8; y++){ + for(x=0; x<4; x++){ + aAddr4Char = SysLinkAddr + (y * 4 * 16) + (x * 16) + 16; + for(i=0; i<16; i++){ + *(volatile unsigned char *)(aAddr4Char++) = tEntry[y][x][i]; + } + } + } +} + +void TLinkageProgram::GetLnkMask(unsigned int aExp) +{ + unsigned int SysLinkAddr; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + if(*(volatile unsigned char *)(SysLinkAddr + 4) == 'M'){ + IsMask = 1; + }else{ + IsMask = 0; + } +} + +void TLinkageProgram::SetLnkMask(unsigned int aExp) +{ + unsigned int SysLinkAddr; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + if(IsMask){ + *(volatile unsigned char *)(SysLinkAddr + 4) = 'M'; + }else{ + *(volatile unsigned char *)(SysLinkAddr + 4) = ' '; + } +} + +void TLinkageProgram::GetLnkDoStop(unsigned int aExp) +{ + unsigned int SysLinkAddr; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + if(*(volatile unsigned char *)(SysLinkAddr + 5) == 'S'){ + DoStop = 1; + }else{ + DoStop = 0; + } +} + +void TLinkageProgram::GetLnkSelfActive(unsigned int aExp) +{ + unsigned int SysLinkAddr; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + if(*(volatile unsigned char *)(SysLinkAddr + 6) == 'F'){ + IsSelfActive = 1; + }else{ + IsSelfActive = 0; + } +} + +void TLinkageProgram::SetLnkDoStop(unsigned int aExp) +{ + unsigned int SysLinkAddr; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + if(DoStop){ + *(volatile unsigned char *)(SysLinkAddr + 5) = 'S'; + }else{ + *(volatile unsigned char *)(SysLinkAddr + 5) = ' '; + } +} + +void TLinkageProgram::SetLnkSelfActive(unsigned int aExp) +{ + unsigned int SysLinkAddr; + SysLinkAddr = dSdAddrLinkageExp + (aExp * 1024); + if(IsSelfActive){ + *(volatile unsigned char *)(SysLinkAddr + 6) = 'F'; + }else{ + *(volatile unsigned char *)(SysLinkAddr + 6) = ' '; + } +} + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/LinkageProgram.h b/MyCode/Gui/LinkageProgram.h new file mode 100644 index 0000000..1881831 --- /dev/null +++ b/MyCode/Gui/LinkageProgram.h @@ -0,0 +1,278 @@ +#ifndef LINKAGEPROGRAM_H_ +#define LINKAGEPROGRAM_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "EditML.h" +#include "CtlPanel1.h" + + + /* int64 nHeaderBytes; // header bytes of the original + int64 nDataBytes; // data bytes of the original + int64 nTotalBytes; // total bytes of the original + int64 nTotalBytes; // total bytes of the file + int64 nTotalBlocks; // the total number blocks + int nLengthMS; // the length in milliseconds + int nAverageBitrate; // the kbps (i.e. 637 kpbs) + int nDecompressedBitrate; // the kbps of the decompressed audio (i.e. 1440 kpbs) + int nJunkHeaderBytes; // used for, etc. + int nSeekTableElements; // the number of elements in the seek table(s) + int nMD5Invalid; // whether the is valid*/ + +class TLinkageProgram{ + public: + static constexpr unsigned short hList[12] = {36,32,300,150, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + int IsShow; + unsigned char IsPermission; + unsigned char PermissionCmd; + + class TEdit EEntry; + + class TEdit EuCode; + class TEdit EdType; + class TEdit ELogic; + class TEdit EDelay; + class TEdit EInnerCount; + class TEdit EInCount; + + TStaticText STextDType; + + unsigned char IsSaveEn; + unsigned char IsDeleteEn; + unsigned char EnterMethod; + unsigned char ShouldBeLoad; + unsigned char ShouldBeClear; + unsigned char ParCntHasChanged; + unsigned char tAvalible; + unsigned char tLogic; + unsigned char IsInput; + unsigned char IsMask; + unsigned char IsSelfActive; + unsigned char ParCnt; + unsigned char DoStop; + unsigned char InCount; + char tEntry[12][4][24]; + char EntryChar[24]; + + u32 Color; + + unsigned char ItemsIndex; + unsigned char EditIndex; + unsigned char OnEditing; + unsigned char CharIndex; + unsigned char IsInputSymbol; + unsigned char IsProgram; + + char PathText[64]; + unsigned char CtlNum; + unsigned char Path0; + unsigned char Path1; + + unsigned char IsViewList; + int InputCount; + int InputPageCount; + int InputPageIndex; + unsigned char CurrentPath0; + + int EditingLinkageIndex; + int ExpCount; + int IsNew; + unsigned char ExistTabel[dLINKAGE_MAX_COUNT]; + + union{ + unsigned char D8[256]; + unsigned int D32[64]; + }ReadWriteData; + unsigned char ActX; + unsigned char Inx; + unsigned char eX, eY; + unsigned char eWhat; + unsigned char IsWhowingTip; + unsigned char EntryState; + public: + TLinkageProgram(){}; + void Init(); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void DrawCaption(void); + void DrawCaption2(); + void Show(); + void FullRedraw(int Prm); + void DelayUs(unsigned int aUs); + void DelayMs(unsigned int aMs); + void PaintExp(); + void DrawInputListXX(); + void ShowTip(int aTip); + void ShowOneGrid(unsigned int x, unsigned int y); + void ShowAllGrid(); + void RedrawEEdit(); + void RenderGridBack(); + void DrawSelectedGrid(unsigned int oldX, unsigned int oldY, unsigned int NewX, unsigned int NewY); + void DrawFixText(); + + void TryDecValue(int IsForce); + void TryIncValue(int IsForce); + void ClearSelected(void); + void Check4Selected(); + void CheckEWhatWhoActive(); + void InitPanel(); + void DrawGridLine(); + void DrawInputTip(); + void DrawTip(); + unsigned char LoadInputList(unsigned char Path0); + int TrySearchStartPort(); + int SearchPort(unsigned char aP0); + int TrySearchPrePort(); + int TrySearchNextPort(); + + void LoadCfg(); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void LoadExpression(); + void SetEditStart(); + int TryRestoreFromEdit(); + void RestoreFromEdit(); + + void LoadInputList(); + + void IdfButtonEn(); + + void ShowEntryState(); + void FindNextExp(); + int NewEntry(); + void WriteEntry(); + void ReScanExpViaRam(); + void WaitChipIdle(unsigned int aCnt); + void LoadExpCountFromRam(); + void LoadExpression2Ram(); + void LoadExpression2Ram(unsigned int aInx); + void LoadExpression2RamFor4K(unsigned int aInx); + void LoadExpression2Edit(unsigned int aInx); + void Erase4Index(unsigned int aInx); + void Write4Index(unsigned int aInx); + void DeleteEntry(); + + void ShowItemEdit(); + void RedrawItemEdit(); + void RedrawParCnt(); + void ClearPanelSelected(); + void ClearGridSelected(); + + void LoadExpVoid(); + void LoadExp(unsigned int aExp); + void RestoreExp(unsigned int aExp); + + void GetLnkMask(unsigned int aExp); + void SetLnkMask(unsigned int aExp); + void GetLnkSelfActive(unsigned int aExp); + void GetLnkDoStop(unsigned int aExp); + void SetLnkDoStop(unsigned int aExp); + void SetLnkSelfActive(unsigned int aExp); + + void CheckUserCodeUniquely(int IsInput); + + void DrawActiveByStartStop(); + void DrawIsMask(); + void DrawIsSelfActive(); + + void PermissionCmdGO(); + void PermissionCmdReturnDraw(); + + void Skip2Entry(unsigned int aEntry); + void EntryClear(); + int CheckUserCodeOk(); + int CheckTypeOk(); + void CheckShowDevType(); + + + int ExtRequst(unsigned char Prm){IsShow =0; return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/ListBox.cpp b/MyCode/Gui/ListBox.cpp new file mode 100644 index 0000000..db8d978 --- /dev/null +++ b/MyCode/Gui/ListBox.cpp @@ -0,0 +1,210 @@ +#include"gType.h" +#include"GraphLow.h" +#include"ListBox.h" + +#define VCNT 10 + +void TListBoxForm::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u16 aBorderWidth, u32 aBorderColor){ + unsigned short Left,Right,Top,Bottom, aBW,i; + aBW = aBorderWidth; + aBW = 2; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + OwnerLeftTop.x = OwnerX; + OwnerLeftTop.y = OwnerY; + Border.Width = aBW; + Border.Color = aBorderColor; + Left = Bound.Left + aBW; + Right = Bound.Right - aBW; + Top = Bound.Top + aBW; + Bottom = Bound.Bottom - aBW; + VScrollBarBox.Set(Right-20,Top,Right,Bottom); + Content.Set(Left,Top,Right-20,Bottom); + + SetFontSize(24); + + Color = clNearWhite; + TextColor = clNearBlack; + SelectedColor = clAqua; + SelectedTextColor = clNearWhite; + VScrollBar.Color = 0xFFFF7777; + VScrollBar.RibbonColor = 0xFF007777; +} + +void TListBoxForm::SetFontSize(int size) +{ + FontSize = size; + FontHeight = GetFontHeight(FontSize); + LineHeight = FontHeight + 4; +} + +void TListBoxForm::DrawSelf(void) +{ + //Draw Border + if (Border.Width>0){ + VertLineRender(Bound.Left, Bound.Top, Bound.Height-1, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width-1, 0xFF808080); + + VertLineRender(Bound.Left+1, Bound.Top+1, Bound.Height-2, 0xFF404040); + HorizLineRender(Bound.Left+1, Bound.Top+1, Bound.Width-2, 0xFF404040); + + VertLineRender(Bound.Right-1, Bound.Top+1, Bound.Height-2, 0xFFD4D0C8); + HorizLineRender(Bound.Left+1, Bound.Bottom-1, Bound.Width-2, 0xFFD4D0C8); + + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFFFFFFFF); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFFFFFFFF); + } + //Fill Rect Box + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TListBoxForm::DrawVertScrollBar(void) +{ + int RibbonHeight; + int RibbonBottom; + int RibbonTop; + int UpRemain; + int DownRemain; + float f1,f2,f3,f4; + + if(Items.Count <= VCNT){ + RibbonTop = VScrollBarBox.Top+1; + RibbonBottom = VScrollBarBox.Bottom - 1; + RibbonHeight = VScrollBarBox.Height - 2; + }else{ + //get RibbonHeight + f1 = static_cast(VCNT); + f2 = static_cast(Items.Count); + f3 = static_cast(VScrollBarBox.Height); + f4 = f1/f2*f3; + RibbonHeight = static_cast(f4) ; + if(RibbonHeight > VScrollBarBox.Height) RibbonHeight = VScrollBarBox.Height; + if(RibbonHeight < 10) RibbonHeight = 10; + f2 = f4/f1; //Get One Item Height + + //get RibbonCenter + UpRemain = Items.TopIndex; + DownRemain = Items.Count - Items.TopIndex - VCNT; + if(UpRemain < DownRemain){ + f1 = UpRemain; + RibbonTop = static_cast(f1*f2) + VScrollBarBox.Top + 1; + RibbonBottom = RibbonTop + RibbonHeight; + if( RibbonBottom > (VScrollBarBox.Bottom -1) )RibbonBottom = VScrollBarBox.Bottom - 1; + }else{ + f1 = DownRemain; + RibbonBottom = VScrollBarBox.Bottom - static_cast(f1*f2); + RibbonTop = RibbonBottom - RibbonHeight; + if( RibbonTop < (VScrollBarBox.Top +1) )RibbonTop = VScrollBarBox.Top +1; + } + } + + //Draw Vert ScrollBar BackGround + RectFillRender(VScrollBarBox.Left, VScrollBarBox.Top, VScrollBarBox.Right, VScrollBarBox.Bottom, VScrollBar.Color); + //Draw Vert ScrollBar Ribbon + RectFillRender(VScrollBarBox.Left, RibbonTop, VScrollBarBox.Right, RibbonBottom, VScrollBar.RibbonColor); +} + +void TListBoxForm::DrawList(void) +{ + int i,index; + for(i=0; i0){ + Items.SelectedIndex--; + if(Items.SelectedIndex VCNT){ + Items.TopIndex = Items.SelectedIndex - VCNT +1; + } + } + }else + + //Page up or Down____________________________ + if(VK_PRIOR == step){ + //roll up one page + Items.TopIndex = Items.TopIndex - VCNT; + if(Items.TopIndex < 0){ + Items.TopIndex = 0; + Items.SelectedIndex = 0; + }else{ + Items.SelectedIndex = Items.SelectedIndex - VCNT; + if(Items.SelectedIndex < 0)Items.SelectedIndex = 0; + } + }else + if(VK_NEXT == step){ + //roll Down one page + ind = Items.TopIndex + VCNT; + if (ind < Items.Count){ + Items.TopIndex = ind; + ind = Items.SelectedIndex + VCNT; + if(ind >= Items.Count) + Items.SelectedIndex = Items.Count - 1; + } + }else + + //roll to Top or Bottom + if(VK_HOME == step){ + //roll up to 0 Index + Items.TopIndex = 0; + Items.SelectedIndex = 0; + }else + if(VK_END == step){ + //roll down to Tail + Items.TopIndex = Items.Count - VCNT + 1; + if(Items.TopIndex < 0) + Items.TopIndex = 0; + Items.SelectedIndex = Items.TopIndex; + } +} + +int TListBoxForm::GetTopIndex(void) +{ + return Items.TopIndex; +} + +int TListBoxForm::GetSelectedItemIndex(void) +{ + return Items.SelectedIndex; +} + +void TListBoxForm::SetTextMount(unsigned char *pTextMount, u32 Ind) +{ + if(IndDevProperty = nullptr; + Tag.Reset(); + Items[0].Reset(); + Items[1].Reset(); + Items[2].Reset(); + IsShow = 0; +} + +void TListViewDevice::SetFontSize(int size) +{ + FontSize = size; + FontHeight = GetFontHeight(FontSize); + LineCount =Content.Height / FontHeight; +} + +void TListViewDevice::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8) +{ + unsigned int i; + ListView.ColWidth[0] = w0; + ListView.ColWidth[1] = w1; + ListView.ColWidth[2] = w2; + ListView.ColWidth[3] = w3; + ListView.ColWidth[4] = w4; + ListView.ColWidth[5] = w5; + ListView.ColWidth[6] = w6; + ListView.ColWidth[7] = w7; + ListView.ColWidth[8] = w8; + + ListView.ColRight[0] = ListView.ColLeft[0] + w0; + for(i=1; i<9; i++){ + ListView.ColLeft[i] = ListView.ColRight[i-1] +1; + ListView.ColRight[i] = ListView.ColLeft[i] + ListView.ColWidth[i]; + } +} + +void TListViewDevice::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TListViewDevice::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TListViewDevice::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TListViewDevice::DrawSelfLevel0(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn == 0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->注册信息"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Registered Information"); + } + + for(int i=0; i注册信息->单回路查询 "); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Circuit->Registered Information"); + } + + for(int i=0; i注册信息->单回路查询->部件数据"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Registered Information->Single Loop->Device"); + } + + for(int i=0; i HLineTextRight ){ + DrawY = DrawY + HSpace; + DrawX = Content.Left +6; + } +} + +void TListViewDevice::ShowTypeList(unsigned char aP0, unsigned char Type1, unsigned char Type2, int Is2Type, char *p, int tLen) +{ + + int i,ToDraw, Addr, DrawText ,Path,ThisLen, aFrom, Found, NewLine; + + if(aP0 == 0)return; + if(aP0 >40) return; + + LastDrawX = -1; + LastDrawY = -1; + Path = aP0 -1; + ToDraw = 0; + DrawText =0; + Found = 0; + for(i=0; i<251; i++){ + if(Is2Type){ + if( (Port[Path].ExistTable[i] == 0xA5) && (( Port[Path].dTypeTable[i] == Type1) || (Port[Path].dTypeTable[i] == Type2) )){ + Addr = i + 1; + if(Found == 0){ + aFrom = i + 1; + Found = 1; + } + }else{ + if(Found){ + if(aFrom == Addr){ + //Show One Addr + ToDraw = 1; + }else{ + //Show Multi Addr + ToDraw = 2; + } + } + Found = 0; + } + }else{ + if( (Port[Path].ExistTable[i] == 0xA5) && ( Port[Path].dTypeTable[i] == Type1 )){ + Addr = i + 1; + if(Found == 0){ + aFrom = i + 1; + Found = 1; + } + }else{ + if(Found){ + if(aFrom == Addr){ + //Show One Addr + ToDraw = 1; + }else{ + //Show Multi Addr + ToDraw = 2; + } + } + Found = 0; + } + } + + + if(i == 250){ + if(Found){ + if(aFrom == Addr){ + //Show One Addr + ToDraw = 1; + }else{ + //Show Multi Addr + ToDraw = 2; + } + } + Found = 0; + } + + if(ToDraw){ + if(DrawText == 0){ + CheckNewLine(tLen); + TextRender_string24(DrawX,DrawY,clNearBlack, p); + DrawX = DrawX + tLen; + DrawText = 1; + } + + if(ToDraw == 1){ + if(Addr > 99){ + ThisLen = 3 * 12; + }else + if(Addr >9){ + ThisLen = 2 * 12; + }else{ + ThisLen = 1 * 12; + } + CheckNewLine(ThisLen); + TextDigitRenderLeft24_1t3(DrawX,DrawY,clNearBlack,Addr); + DrawX = DrawX + ThisLen; + + ThisLen = 1 *12; + CheckNewLine(ThisLen); + TextRender_string24(DrawX,DrawY,clNearBlack, ","); + LastDrawX = DrawX; + LastDrawY = DrawY; + DrawX = DrawX + ThisLen; + }else + if(ToDraw == 2){ + if(aFrom > 99){ + ThisLen = 3 * 12; + }else + if(aFrom >9){ + ThisLen = 2 * 12; + }else{ + ThisLen = 1 * 12; + } + CheckNewLine(ThisLen); + TextDigitRenderLeft24_1t3(DrawX,DrawY,clNearBlack,aFrom); + DrawX = DrawX + ThisLen; + //_________________________ + ThisLen = 1 *12; + + CheckNewLine(ThisLen); + TextRender_string24(DrawX,DrawY,clNearBlack, "~"); + DrawX = DrawX + ThisLen; + //_________________________ + + if(Addr > 99){ + ThisLen = 3 * 12; + }else + if(Addr >9){ + ThisLen = 2 * 12; + }else{ + ThisLen = 1 * 12; + } + CheckNewLine(ThisLen); + TextDigitRenderLeft24_1t3(DrawX,DrawY,clNearBlack,Addr); + DrawX = DrawX + ThisLen; + + ThisLen = 1 *12; + CheckNewLine(ThisLen); + TextRender_string24(DrawX,DrawY,clNearBlack, ","); + LastDrawX = DrawX; + LastDrawY = DrawY; + DrawX = DrawX + ThisLen; + } + ToDraw = 0; + } + } + if(DrawText){ + if(LastDrawX >0){ + TextRender_string24(LastDrawX,LastDrawY,clNearBlack, Color, " "); + if( (LastDrawX + 36) < HLineTextRight){ + TextRender_string24(LastDrawX,LastDrawY,clNearBlack, Color, " "); + DrawX = DrawX + 32; + }else{ + DrawY = DrawY + HSpace; + DrawX = Content.Left +6; + } + } + TypeCharHasShow = 1; + } +} + + +void TListViewDevice::ClearSpliteCount() +{ + Count.Smoke =0; + Count.Tempe =0; + Count.HandReport =0; + Count.HydKp =0; + Count.ModuleInput =0; + Count.ModuleInOut =0; + Count.ModuleOutput =0; + Count.Va =0; + Count.FDisplay =0; + Count.cOther =0; + Count.SmokeTempe = 0; + Count.Tt = 0; +} + + +void TListViewDevice::GetSpliteCount(unsigned char aP0) +{ + unsigned int sPath0,sPath1,aType0,aType1; + int i, j; + unsigned int aIndex, aCount; + unsigned char aType; + + + ClearSpliteCount(); + + if(aP0 == 0) return; + if(aP0 > dPORT_MAX_COUNT)return; + i = aP0-1; + if(MainCtl.fData.Split.ExistTablePort[i] == 0xA5){ + for(j=0; j<250; j++){ + if(Port[i].ExistTable[j] == 0xA5){ + aType = Port[i].dTypeTable[j]; + //if( (Port[i].StateTable[j] & (dEpStateBitFault + dEpStateBitMask)) == 0) { + if(1){ + if(aType == 0){ + //Count.cOther++; + //Count.Tt++; + }else + if( (aType == dgTYPE_SMOKE_DETECTOR) ){ + Count.Smoke++; + Count.Tt++; + }else + if( aType == dgTYPE_TEMPE_DETECTOR ){ + Count.Tempe++; + Count.Tt++; + }else + if( (aType == dgTYPE_HAND_REPORT ) ){ + Count.HandReport++; + Count.Tt++; + }else + if( (aType == dgTYPE_FIRE_HydrantKp ) ){ + Count.HydKp++; + Count.Tt++; + }else + if( (aType == dgTYPE_IN_MODULE ) ){ + Count.ModuleInput++; + Count.Tt++; + }else + if( (aType == dgTYPE_INOUT_MODULE_NonSource) || + (aType == dgTYPE_INOUT_MODULE_Source) ){ + Count.ModuleInOut++; + Count.Tt++; + }else + if( (aType == dgTYPE_OUT_MODULE) ){ + Count.ModuleOutput++; + Count.Tt++; + }else + if( (aType == dgType_VAALRAM ) ){ + Count.Va++; + Count.Tt++; + }else + if( aType == dgTYPE_DISPLAY_PAD ){ + Count.FDisplay++; + Count.Tt++; + }else + if(aType == dgTYPE_SMOKE_TEMPE_DETECTOR ){ + Count.SmokeTempe++; + Count.Tt++; + }else{ + Count.cOther++; + Count.Tt++; + } + } + } + } + } +} + +void TListViewDevice::ShowFig(unsigned char aP0) +{ + + RectFillRender(Content.Left, Content.Top+42, Content.Right, Content.Bottom, Color); + + TextRender_string24(Content.Left+20, Content.Top+42 + 0*32 , clNearBlack, "烟感:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 1*32 , clNearBlack, "温感:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 2*32 , clNearBlack, "输入模块:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 3*32 , clNearBlack, "输出模块:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 4*32 , clNearBlack, "手报:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 5*32 , clNearBlack, "消钮:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 6*32 , clNearBlack, "输入输出模块:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 7*32 , clNearBlack, "层显:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 8*32 , clNearBlack, "声光警报器:" ); + TextRender_string24(Content.Left+20, Content.Top+42 + 9*32 , clNearBlack, "其他:" ); + + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 0*32 ,clNearBlack, Count.Smoke); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 1*32 ,clNearBlack, Count.Tempe); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 2*32 ,clNearBlack, Count.ModuleInput); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 3*32 ,clNearBlack, Count.ModuleOutput); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 4*32 ,clNearBlack, Count.HandReport); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 5*32 ,clNearBlack, Count.HydKp); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 6*32 ,clNearBlack, Count.ModuleInOut); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 7*32 ,clNearBlack, Count.FDisplay); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 8*32 ,clNearBlack, Count.Va); + TextDigitRender3Right24(Content.Left+200, Content.Top+42 + 9*32 ,clNearBlack, Count.cOther); + + TextRender_string24(Content.Left+420, Content.Top+42 + 0*32 , clNearBlack, "烟温一体:" ); + TextDigitRender3Right24(Content.Left+600, Content.Top+42 + 0*32 ,clNearBlack, Count.SmokeTempe); +} + +void TListViewDevice::ShowCount(unsigned char aP0) +{ + DrawX = Content.Left +6; + DrawY = Content.Top + 42; + + //dgTYPE_SMOKE_DETECTOR, + //dgTYPE_TEMPE_DETECTOR, + //dgTYPE_HAND_REPORT, + //dgTYPE_FIRE_hydrant_Kp, + //dgTYPE_IN_MODULE, + //dgTYPE_OUT_MODULE, + //dgTYPE_INOUT_MODULE_NonSource, + //dgTYPE_INOUT_MODULE_Source, + //dgType_VAALRAM, + //dgTYPE_DISPLAY_PAD + RectFillRender(Content.Left, Content.Top+42, Content.Right, Content.Bottom, Color); + + TypeCharHasShow = 0; + if(MainCtl.fData.Split.ExistTablePort[aP0-1] == 0xA5){ + ShowTypeList(aP0, dgTYPE_SMOKE_DETECTOR, 0, 0, "烟感:", 5*12); + ShowTypeList(aP0, dgTYPE_TEMPE_DETECTOR, 0, 0, "温感:", 5*12); + ShowTypeList(aP0, dgTYPE_IN_MODULE, 0, 0, "输入模块:", 9*12); + ShowTypeList(aP0, dgTYPE_OUT_MODULE, 0, 0, "输出模块:", 9*12); + ShowTypeList(aP0, dgTYPE_HAND_REPORT, 0, 0, "手报:", 5*12); + ShowTypeList(aP0, dgTYPE_FIRE_HydrantKp, 0, 0, "消钮:", 5*12); + ShowTypeList(aP0, dgTYPE_INOUT_MODULE_NonSource, dgTYPE_INOUT_MODULE_Source, 1, "输入输出模块:", 13*12); + ShowTypeList(aP0, dgTYPE_DISPLAY_PAD, 0, 0, "层显:", 5*12); + ShowTypeList(aP0, dgType_VAALRAM, 0, 0, "声光警报器:", 11*12); + ShowTypeList(aP0, dgTYPE_SMOKE_TEMPE_DETECTOR, 0, 0, "烟温一体:", 5*12); + } + if(TypeCharHasShow == 0){ + TextRender_string24(Content.Left, Content.Top+42, clNearBlack, "本回路未挂载终端设备" ); + } +} + +void TListViewDevice::DrawList(void) +{ + int i,t,x,y; + unsigned int tAddr; + unsigned int ExistCnt, cnt, aP0, aP1, dType; + if(Tag.ViewingLevel == 0){ + for(i=0, t=Items[0].TopInx; (i<8) && (tFullRedraw(Prm); + } + } + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + Caption.Enable = 1; + if(Tag.ViewingLevel == 0){ + DrawSelfLevel0(); + DrawList(); + Check4SelectedLv0(); + }else + if(Tag.ViewingLevel == 1){ + DrawSelfLevel1(); + DrawList(); + Check4SelectedLv1(); + }else + if(Tag.ViewingLevel == 2){ + if(DevProperty != nullptr){ + DevProperty->FullRedraw(Prm); + } + } + } +} + +void TListViewDevice::ShowCircuitDet() +{ + if(IsPath0Found){ + TextRender_string24(Content.Left + 200,Content.Top + 4,clNearBlack, Color, " " ); + TextRender_string24(Content.Left + 260,Content.Top + 4,clNearBlack, Color, "设备数量: " ); + TextDigitRender3Right24(Content.Left + 368,Content.Top + 4,clNearBlack, Count.Tt); + TextRender_string24(Content.Left + 540,Content.Top + 4,clNearBlack, "左右键切换显示内容" ); + }else{ + TextRender_string24(Content.Left + 200,Content.Top + 4,clNearBlack, Color, "此回路未登记 " ); + TextRender_string24(Content.Left + 540,Content.Top + 4,clNearBlack, Color, " " ); + } +} + +void TListViewDevice::CalcIconDrawPrm(void) +{ + +} + +TGuiMsgReturn TListViewDevice::QueryKeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg; + aMsg = DevProperty->KeyIn(aKey); + + if(aMsg == guiMsgReturn){ + return guiMsgReturn; + } + return guiMsgNone; +} + +TGuiMsgReturn TListViewDevice::EditKeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg; + //editting + return guiMsgNone; +} + +void TListViewDevice::ClearSelectedLv0(void) +{ + int iT; + iT = Tag.Level[0].Inx + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle +} + +void TListViewDevice::Check4SelectedLv0(void) +{ + int iT; + iT = Tag.Level[0].Inx + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle +} + +void TListViewDevice::ClearSelectedLv1(void) +{ + int iT; + iT = Tag.Level[1].Inx + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle +} + +void TListViewDevice::Check4SelectedLv1(void) +{ + int iT; + iT = Tag.Level[1].Inx + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle +} + +TGuiMsgReturn TListViewDevice::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex, Found; + unsigned char aP0; + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn aMsg2Rtn = guiMsgNone; + //Up or Down One Index___________________ + + if(Tag.ViewingLevel == 0){ + if(VK_LEFT ==aKey){ + + }else + if(VK_RIGHT == aKey){ + + }else + if(VK_UP == aKey){ + if(Tag.Level[0].Inx >0){ + ClearSelectedLv0(); + Tag.Level[0].Inx--; + Items[0].Inx--; + Items[0].Path = Items[0].Item[Items[0].Inx]; + Check4SelectedLv0(); + }else{ + if(Items[0].Inx >0){ + Items[0].Inx--; + Items[0].Path = Items[0].Item[Items[0].Inx]; + Items[0].TopInx = Items[0].Inx; + DrawList(); + } + } + }else + if(VK_DOWN == aKey){ + if(Tag.Level[0].Inx < 7){ + if(Items[0].Inx < (Items[0].Count-1)){ + ClearSelectedLv0(); + Tag.Level[0].Inx++; + Items[0].Inx++; + Items[0].Path = Items[0].Item[Items[0].Inx]; + Check4SelectedLv0(); + } + }else{ + Tag.Level[0].Inx = 7; + if(Items[0].Inx < (Items[0].Count-1)){ + Items[0].Inx++; + Items[0].Path = Items[0].Item[Items[0].Inx]; + Items[0].TopInx++; + if(Items[0].TopInx <0)Items[0].TopInx =0; + DrawList(); + } + } + }else + if(aKey == VK_TAB){ + + }else + if(aKey == VK_EXECUTE){ + //Open path Device + if(Items[0].Count > 0){ + if(Items[0].Inx < Items[0].Count){ + if(Items[0].Path < dPORT_MAX_COUNT){ + Tag.ViewingLevel = 1; + Tag.Level[1].Inx = 0; + Items[1].TopInx = 0; + Items[1].Inx = 0; + Items[1].Path = Items[1].Inx; + RenderBackGround(); + DrawSelfLevel1(); + DrawList(); + Check4SelectedLv1(); + } + } + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + }else{ + + } + }else + if(Tag.ViewingLevel == 1){ + if(VK_LEFT ==aKey){ + int GoInx; + if(Items[1].TopInx <1){ + GoInx = 248; + Items[1].Inx = GoInx; + Items[1].TopInx = GoInx; + }else{ + GoInx = (Items[1].Inx / 8 -1) * 8; + if(GoInx <0)GoInx = 0; + Items[1].Inx = GoInx; + Items[1].TopInx = GoInx; + } + Items[1].Path = Items[1].Inx; + DrawList(); + ClearSelectedLv1(); + Tag.Level[1].Inx = 0; + Check4SelectedLv1(); + }else + if(VK_RIGHT == aKey){ + int GoInx; + GoInx = (Items[1].Inx / 8 +1) * 8; + if(GoInx > 248)GoInx = 0; + Items[1].Inx = GoInx; + Items[1].TopInx = GoInx; + Items[1].Path = Items[1].Inx; + DrawList(); + ClearSelectedLv1(); + Tag.Level[1].Inx = 0; + Check4SelectedLv1(); + }else + if(VK_UP == aKey){ + if(Tag.Level[1].Inx >0){ + ClearSelectedLv1(); + Tag.Level[1].Inx--; + Items[1].Inx--; + Items[1].Path = Items[1].Inx; + Check4SelectedLv1(); + }else{ + if(Items[1].Inx >0){ + Items[1].Inx--; + Items[1].TopInx = Items[1].Inx; + Items[1].Path = Items[1].Inx; + DrawList(); + } + } + }else + if(VK_DOWN == aKey){ + if(Tag.Level[1].Inx < 7){ + if(Items[1].Inx < (dEP_MAX_COUNT_PER_PORT-1)){ + ClearSelectedLv1(); + Tag.Level[1].Inx++; + Items[1].Inx++; + Items[1].Path = Items[1].Inx; + Check4SelectedLv1(); + } + }else{ + Tag.Level[1].Inx = 7; + if(Items[1].Inx < (dEP_MAX_COUNT_PER_PORT-1)){ + Items[1].TopInx++; + Items[1].Inx++; + Items[1].Path = Items[1].Inx; + DrawList(); + } + } + }else + if(aKey == VK_TAB){ + + }else + if(aKey == VK_EXECUTE){ + this->DevProperty->Init(TDevProperty::htNoType, 1); + this->DevProperty->aPanel = this->aPanel; + this->DevProperty->IList = this->IList; + this->DevProperty->IList->RealtimeData.Reset(); + this->DevProperty->IList->TextOutClear(); + this->DevProperty->SetPath(MainCtl.fData.Split.MyNum, Items[0].Path+1, Items[1].Path+1); + this->DevProperty->Show(); + this->DevProperty->Init4DType(); + this->DevProperty->DrawCommonInfTitle(); + this->DevProperty->RenewCommonInf(); + Tag.ViewingLevel = 2; + }else + if(aKey == VK_RETURN){ + Tag.ViewingLevel = 0; + DrawSelfLevel0(); + DrawList(); + Check4SelectedLv0(); + }else{ + + } + }else + if(Tag.ViewingLevel == 2){ + aMsg2Rtn = this->DevProperty->KeyIn(aKey); + if(aMsg2Rtn == guiMsgReturn){ + Tag.ViewingLevel = 1; + RenderBackGround(); + DrawSelfLevel1(); + DrawList(); + Check4SelectedLv1(); + } + } + //____________________________________________________________________<- List View + + return aMsg; + +} + +void TListViewDevice::ClearPath(void) +{ + ListView.TopIndex = 0; + +} + +void TListViewDevice::ClearPath1(void) +{ + ListView.TopIndex = 0; +} + +void TListViewDevice::LoadPath0Item() +{ + for(int i=0; i40){ + return; + } + aP0--; + + theRDev = &Port[aP0]; + if(theRDev->fData.Common.dType == dgTYPE_PORT){ + px = theRDev->fData.Port.Id; + if(px){ + ItemEnter.Path0 = px; + px--; + thePort = (TPort *)theRDev; + ClearPath1(); + for(i=0; i< dEP_MAX_COUNT_PER_PORT; i++){ + if(Port[px].ExistTable[i] == 0xA5) + LoadPath1Item(&EpDev[px][i]); + } + } + } + + ListView.SelectedCol = 0; + ListView.TopIndex = 0; +} + +void TListViewDevice::SetEditMode(unsigned int aMode) +{ + EditMode = aMode; +} + + + + + + + diff --git a/MyCode/Gui/ListViewDevice.h b/MyCode/Gui/ListViewDevice.h new file mode 100644 index 0000000..bd6b7c6 --- /dev/null +++ b/MyCode/Gui/ListViewDevice.h @@ -0,0 +1,280 @@ +#ifndef LISTVIEWDEVICE_H_ +#define LISTVIEWDEVICE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "Icon.h" + +#define dLISTVIEW_TYPE_DUMP 0 +#define dLISTVIEW_TYPE_SYS 1 +#define dLISTVIEW_TYPE_EP 2 +#define dLISTVIEW_TYPE_PORT 3 +#define dLISTVIEW_TYPE_HANDCTL 4 +#define dLISTVIEW_TYPE_DIRECTCTL 5 + +#define dLISTVIEW_STYLE_LIST 0 +#define dLISTVIEW_STYLE_ICON 1 +#define dLISTVIEW_VSCOLLBAR_WIDTH 20 + +//For Device View or Edit +class TListViewDevice{ + public: + static constexpr unsigned short hList[12] = {34,34,34,34, 34,34,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]) +4, + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1] +4, + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 10, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + class TCtlPanel1 *aPanel; + class TItemList *IList; + int FontSize; + int FontHeight; + int EditMode; + int Editing; + int Quering; + class TEdit Edit; + struct{ + int TopIndex; + unsigned short RowCount; + unsigned short ColTop[12]; + unsigned short ColBottom[12]; + unsigned short ColHeight; + unsigned short ColWidth[12]; + unsigned short ColLeft[12]; + unsigned short ColRight[12]; + unsigned short FixColTop; + unsigned short FixColBottom; + unsigned int TransparrentColor; + int SelectedCol; + }ListView; + struct{ + struct{ + int SelectedIndex; + int ListTopIndex; + int IconLeftTopIndex; + }Path0; + struct{ + int SelectedIndex; + int ListTopIndex; + int IconLeftTopIndex; + }Path1; + }Bk; + struct{ + int Count; + int Inx; + int TopInx; + int Path; + unsigned char Item[256]; + void Reset(){ + Inx = 0; + TopInx = 0; + Path = 0; + } + }Items[3]; + unsigned char SelectedType; + struct{ + unsigned short Path0; + unsigned short Path1; + TRootDevice *RootDev; + TEpDevice *EpDev; + }ItemEnter; + unsigned char TypeAndCount[256]; + unsigned char TypeCount; + unsigned char TypeCountIndex; + unsigned char TypeCountPageIndex; + unsigned char TypeCountPageCount; + unsigned char TypeCharHasShow; + + char Text[80]; + unsigned char TextInputIndex; + + int DrawX,DrawY; + int LastDrawX,LastDrawY; + + int CircuitShowFig; + struct{ + unsigned int Smoke; + unsigned int Tempe; + unsigned int HandReport; + unsigned int HydKp; + unsigned int ModuleInput; + unsigned int ModuleInOut; + unsigned int ModuleOutput; + unsigned int Va; + unsigned int FDisplay; + unsigned int SmokeTempe; + unsigned int cOther; + + unsigned int Tt; + }Count; + int IsPath0Found; + unsigned char Path0; + struct{ + int ViewingLevel; + struct{ + int Inx; + }Level[3]; + void Reset(){ + ViewingLevel =0; + Level[0].Inx = 0; + Level[1].Inx = 0; + Level[2].Inx = 0; + } + }Tag; + public: + TIcon Icon; + TStaticText Caption; + TStaticText SText; + unsigned int ViewPath; + unsigned int ViewStyle; + int ActiveLineNum; + int LineCount; + int LineHeight; + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + int IsShow; + + TDevProperty *DevProperty; + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TListViewDevice(){}; + void Init(); + void LoadPath0Item(); + void SetFontSize(int size); + unsigned int ItemGetIcon(unsigned int aIndex); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelfLevel0(void); + void DrawSelfLevel1(void); + void DrawSelfLevel2(void); + void DrawLevel1Detail(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + void RenderContent(void); + void ClearSpliteCount(); + void GetSpliteCount(unsigned char aP0); + void ShowFig(unsigned char aP0); + void ShowCount(); + void ShowCircuitDet(); + void FullRedraw(int Prm); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearPath(void); + void ClearPath1(void); + void LoadPath0(void); + void LoadPath1(unsigned char aP0); + void GetTypeAndCount(); + int FindStartPoint(); + void SetEditMode(unsigned int aMode); + + void CheckNewLine(int aLen); + void ShowTypeList(unsigned char aP0, unsigned char Type1, unsigned char Type2, int Is2Type, char *p, int tLen); + void ShowCount(unsigned char aP0); + + void FullRePaint(void); + void RePaint(void); + + void DevPropertyInit(void); + + void ClearSelectedLv0(void); + void Check4SelectedLv0(void); + void ClearSelectedLv1(void); + void Check4SelectedLv1(void); + + int ExtRequst(unsigned char Prm){ + if(this->DevProperty != nullptr) + this->DevProperty->ExtRequst(Prm); + IsShow = 0; + return 0; + } +}; + + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/LiteIconOverView.cpp b/MyCode/Gui/LiteIconOverView.cpp new file mode 100644 index 0000000..8882af6 --- /dev/null +++ b/MyCode/Gui/LiteIconOverView.cpp @@ -0,0 +1,873 @@ +#include "LiteIconOverView.h" +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" + +#define Hcnt0 10 +#define Vcnt0 7 +#define Hcnt1 20 +#define Vcnt1 13 + +#define dfColor_Normal clMedGreen +#define dfColor_Fire clRed +#define dfColor_Fault clMedOrange +#define dfColor_Start clDeepBlue +#define dfColor_Fb clTeal +#define dfColor_StartFb clAqua +#define dfColor_Mask clNearBlack + +#define dfLine1_Top 100 +#define dfLine2_Top 299 +#define dfLine3_Top 349 + +static const short svGridX[10] = {40, 116, 192, 268, 344, 420, 496, 572, 648, 724}; +static const short svGridY[6] = {105, 155, 205, 255, 305, 355}; +static const short svGridX2[10] = {100, 176, 252, 328, 404, 480, 556, 632, 708, 784}; +static const short svGridY2[6] = {145, 195, 245, 295, 345, 395}; + +static const short svGrid1X[20] = { + 13, 52, 91, 130, 169, 208, 247, 286, 325, 364, 403, 442, 481, 520, 559, 598, 637, 676, 715, 754 +}; +static const short svGrid1X2[20] = { + 48, 87, 126, 165, 204, 243, 282, 321, 360, 399, 438, 477, 516, 555, 594, 633, 672, 711, 750, 789 +}; + +void TLiteIconOverView::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + View1.ItemsCount =0; + View1.SelectedIndex =0; + + ViewPath = 0; + + Caption.Border.Color = clGray; + + cx =0; + cy =0; + + RootCircuitCount = 0; +} + +void TLiteIconOverView::SetIconPosition(void) +{ + unsigned int i, aLeft, aTop; + aLeft = Content.Left + 10; + aTop = Content.Top + 32; + + aLeft = Content.Left + 10; + aTop = Content.Top + 34; + //for(i=0; i设备状态概览 ", Caption.Text); + else TMyString::sFromStr(" Loop->Dev Status Overview ", Caption.Text); + Caption.Show(); +} + +void TLiteIconOverView::DrawStateIdf_0(void) +{ + //正常 离线 报警 故障 屏蔽 重码 污染 输入开 输出开 + #define GS 24 + #define TS 60 + + unsigned int aLeft, aTop, aTopR; + aLeft = Content.Left + 170; + aTop = Content.Top +4; + aTopR = Content.Top +6; + if(LanguageEnCn==0){ + TMyString::sFromStr(" 主机挂载回路 ", Text); + TMyString::sAddOn2Dg(RootCircuitCount, Text); + TextRender_string24(Content.Left + 6,120,clNearBlack, "回"); + TextRender_string24(Content.Left + 6,150,clNearBlack, "路"); + }else{ + TMyString::sFromStr(" Mounted Loop(s) ", Text); + TMyString::sAddOn2Dg(RootCircuitCount, Text); + TextRender_string24(Content.Left + 6,aTop,clNearBlack, "Loop"); + } + TextRender_string24(Caption.Bound.Left + 400,Caption.Bound.Top+4,clNearWhite, Text); + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Normal); + aLeft += GS; + if(LanguageEnCn==0){ + TextRender_string24(aLeft,aTop,clNearBlack, "正常"); + }else{ + TextRender_string24(aLeft,aTop,clNearBlack, "IDLE"); + } + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Fire); + aLeft += GS; + if(LanguageEnCn==0){ + TextRender_string24(aLeft,aTop,clNearBlack, "报警"); + }else{ + TextRender_string24(aLeft,aTop,clNearBlack, "FIRE"); + } + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Fault); + aLeft += GS; + if(LanguageEnCn==0){ + TextRender_string24(aLeft,aTop,clNearBlack, "故障"); + }else{ + TextRender_string24(aLeft,aTop,clNearBlack, "Fault"); + aLeft+=12; + } + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Start); + aLeft += GS; + if(LanguageEnCn==0){ + TextRender_string24(aLeft,aTop,clNearBlack, "启动"); + }else{ + TextRender_string24(aLeft,aTop,clNearBlack, "Actived"); + } + aLeft += (TS + 40); + if(LanguageEnCn==0){ + TextRender_string24(aLeft,aTop,clNearBlack, "(子部件状态)"); + }else{ + //Sub component status + TextRender_string24(aLeft,aTop,clNearBlack, "(Component Status)"); + } + + //TextRender_string24(Content.Left + 6,svGridY[4] + 10,clNearBlack, "总线盘"); + //TextRender_string24(Content.Left + 6,svGridY[5] + 10,clNearBlack, "多线盘"); + + #undef GS + #undef TS +} + + + +void TLiteIconOverView::DrawStateIdf_1(void) +{ + //正常 离线 报警 故障 屏蔽 重码 污染 输入开 输出开 + #define GS 24 + #define TS 60 + + unsigned int aLeft, aTop, aTopR; + aLeft = Content.Left +90; + aTop = Content.Top +4; + aTopR = Content.Top +6; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Normal); + aLeft += GS; + if(LanguageEnCn==0){TextRender_string24(aLeft,aTop,clNearBlack, "正常");} + else {TextRender_string24(aLeft,aTop,clNearBlack, "IDLE");} + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Fire); + aLeft += GS; + if(LanguageEnCn==0){TextRender_string24(aLeft,aTop,clNearBlack, "报警");} + else {TextRender_string24(aLeft,aTop,clNearBlack, "Fire");} + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Fault); + aLeft += GS; + if(LanguageEnCn==0){TextRender_string24(aLeft,aTop,clNearBlack, "故障");} + else {TextRender_string24(aLeft,aTop,clNearBlack, "Fault");aLeft += 12;} + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Start); + aLeft += GS; + if(LanguageEnCn==0){TextRender_string24(aLeft,aTop,clNearBlack, "启动");} + else {TextRender_string24(aLeft,aTop,clNearBlack, "Act");} + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Fb); + aLeft += GS; + if(LanguageEnCn==0){TextRender_string24(aLeft,aTop,clNearBlack, "反馈");} + else {TextRender_string24(aLeft,aTop,clNearBlack, "FB");} + aLeft += TS; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_StartFb); + aLeft += GS; + if(LanguageEnCn==0){TextRender_string24(aLeft,aTop,clNearBlack, "启动+反馈");} + else {TextRender_string24(aLeft,aTop,clNearBlack, "Act & FB");} + aLeft += TS + 64; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, dfColor_Mask); + aLeft += GS; + if(LanguageEnCn==0){TextRender_string24(aLeft,aTop,clNearBlack, "屏蔽");} + else {TextRender_string24(aLeft,aTop,clNearBlack, "Blocking");} + aLeft += TS; + + /* + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clTeal); + aLeft += GS; + TextRender_string24(aLeft,aTop,clNearBlack, "输入开"); + aLeft += TS + 24; + + RectFillRender( aLeft, aTopR, aLeft + 20, aTopR + 18, clOlive); + aLeft += GS; + TextRender_string24(aLeft,aTop,clNearBlack, "输出开"); + aLeft += TS; + */ + #undef GS + #undef TS + + LoadPath1(); +} + +void TLiteIconOverView::DrawRootItemsCount() +{ + + TMyString::sFromStr(" 主机挂载", Caption.Text); + TMyString::sAddOn2Dg(ItemsP0Count, Caption.Text); + TMyString::sAddOnStr(" 回路", Caption.Text); + TMyString::sAddOn2Dg(RootCircuitCount, Caption.Text); + + Caption.Show(); +} + +void TLiteIconOverView::DrawSel() +{ + int x,y, aV; + int SelX, SelY; + if(SelPath0 == 0)return; + + + + if(SelPath0 < 41){ + aV = SelPath0 -1; + SelX = aV % 10; + SelY = aV / 10; + }else + if(SelPath0 < 49){ + aV = SelPath0 -1; + SelX = aV % 10 +2; + SelY = 4; + }else + if(SelPath0 < 57){ + aV = SelPath0 -1 +2; + SelX = aV % 10 +2; + SelY = 5; + } + + for(y=0; y<4; y++){ + for(x=0; x<10; x++){ + if( (y == SelY) && (x == SelX) ){ + RectRender(svGridX[x], svGridY[y], svGridX2[x], svGridY2[y], 4,clBlue); + }else{ + RectRender(svGridX[x], svGridY[y], svGridX2[x], svGridY2[y], 4,Color); + } + } + } + for(y=4; y<6; y++){ + for(x=2; x<10; x++){ + if( (y == SelY) && (x == SelX) ){ + RectRender(svGridX[x], svGridY[y], svGridX2[x], svGridY2[y], 4,clBlue); + }else{ + RectRender(svGridX[x], svGridY[y], svGridX2[x], svGridY2[y], 4,Color); + } + } + } +} + +void TLiteIconOverView::DrawList(void) +{ + int i,j; + unsigned int idx, iz; + unsigned int x,y, aP0; + unsigned int aClr; + unsigned char aState; + + if(1){ + DrawCaption(); + RectFillRender(Content.Left,Content.Top,Content.Right,Content.Bottom, Color); + if(ViewPath == 0){ + //if(View0.ItemsCount < 1)return; + DrawStateIdf_0(); + LineRender(10, dfLine1_Top, 788, dfLine1_Top, 1, clGray); + LineRender(10, dfLine2_Top, 788, dfLine2_Top, 1, clGray); + LineRender(10, dfLine3_Top, 788, dfLine3_Top, 1, clGray); + for(i=0; i0){ + aCy = cy-1; + while(aCy > -1){ + aCx = cx; + while(aCx > -1){ + if(ExistTab[aCy][aCx]){ + cy = aCy; + cx = aCx; + Found = 1; + CalcSelPath0(); + break; + } + aCx--; + } + if(Found == 0){ + aCx = cx; + while(aCx <10){ + if(ExistTab[aCy][aCx]){ + cy = aCy; + cx = aCx; + Found = 1; + CalcSelPath0(); + break; + } + aCx++; + } + } + if(Found)break; + aCy--; + } + } + if(Found){ + DrawSel(); + } + } + }else + if(VK_DOWN == aKey){ + if(ViewPath ==0){ + if(cy<5){ + aCy = cy+1; + while(aCy <6){ + aCx = cx; + while(aCx > -1){ + if(ExistTab[aCy][aCx]){ + cy = aCy; + cx = aCx; + Found = 1; + CalcSelPath0(); + break; + } + aCx--; + } + if(Found == 0){ + aCx = cx; + while(aCx <10){ + if(ExistTab[aCy][aCx]){ + cy = aCy; + cx = aCx; + Found = 1; + CalcSelPath0(); + break; + } + aCx++; + } + } + if(Found)break; + aCy++; + } + } + if(Found){ + DrawSel(); + } + } + }else + if(VK_LEFT == aKey){ + if(ViewPath ==0){ + if(cx > -1){ + aCy = cy; + aCx = cx-1; + while(aCx > -1){ + if(ExistTab[aCy][aCx]){ + cx = aCx; + Found = 1; + CalcSelPath0(); + break; + } + aCx--; + } + } + if(Found){ + DrawSel(); + } + } + }else + if(VK_RIGHT == aKey){ + if(ViewPath ==0){ + if(cx < 10){ + aCy = cy; + aCx = cx+1; + while(aCx < 10){ + if(ExistTab[aCy][aCx]){ + cx = aCx; + Found = 1; + CalcSelPath0(); + break; + } + aCx++; + } + } + if(Found){ + DrawSel(); + } + } + } + } + + if(aKey == VK_EXECUTE){ + //Open path Device + if(ViewPath == 0){ + ClearPath1(); + ViewPath = 1; + DrawList(); + } + }else + if(aKey == VK_F2){ + + }else + if(aKey == VK_RETURN){ + if(ViewPath == 0){ + ClearPath(); + aMsg = guiMsgReturn; + }else + if(ViewPath == 1){ + //ClearPath(); + //LoadPath0(); + ViewPath = 0; + ReDraw(); + }else + if(ViewPath > 1){ + ClearPath(); + LoadPath0(); + ViewPath = 0; + ReDraw(); + } + } + return aMsg; +} + + + + + + diff --git a/MyCode/Gui/LiteIconOverView.h b/MyCode/Gui/LiteIconOverView.h new file mode 100644 index 0000000..bfb124b --- /dev/null +++ b/MyCode/Gui/LiteIconOverView.h @@ -0,0 +1,120 @@ +#ifndef LITEICONOVERVIEW_H_ +#define LITEICONOVERVIEW_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" + +#define dLISTVIEW_TYPE_DUMP 0 +#define dLISTVIEW_TYPE_SYS 1 +#define dLISTVIEW_TYPE_EP 2 +#define dLISTVIEW_TYPE_PORT 3 +#define dLISTVIEW_TYPE_HANDCTL 4 +#define dLISTVIEW_TYPE_DIRECTCTL 5 + +#define dLISTVIEW_STYLE_LIST 0 +#define dLISTVIEW_STYLE_ICON 1 +#define dLISTVIEW_VSCOLLBAR_WIDTH 20 + +//For Device View or Edit +class TLiteIconOverView{ + public: + struct{ + unsigned int ItemsCount; + int SelectedIndex; + int SelectedCol; + int SelectedRow; + //unsigned short x1List[20]; + unsigned short y1List[20]; + //unsigned short x2List[20]; + unsigned short y2List[20]; + }View1; + char Text[68]; + unsigned char ExistTab[6][10]; + short cx,cy; + + TStaticText Caption; + unsigned int ViewPath; + u32 Color; + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + + struct{ + unsigned char Path; + unsigned char iType; + }ItemsP0[128]; + + unsigned char ItemsP0Count; + unsigned char SelPath0; + unsigned char SelRootType; + + unsigned char RootCircuitCount; + private: + void LoadPath0Item(TRootDevice *pItem); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TLiteIconOverView(){}; + TLiteIconOverView(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void SetIconPosition(void); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void RenderContent(void); + void DrawStateIdf_0(void); + void DrawStateIdf_1(void); + void DrawSel(); + void DrawRootItemsCount(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearPath(void); + void ClearPath1(void); + void LoadPath0(void); + void LoadPath1(void); + + void FindNearP0(); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + void CalcSelPath0(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/LiteListViewMask.cpp b/MyCode/Gui/LiteListViewMask.cpp new file mode 100644 index 0000000..5e27183 --- /dev/null +++ b/MyCode/Gui/LiteListViewMask.cpp @@ -0,0 +1,594 @@ +#include "LiteListViewMask.h" +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +void TLiteListViewMask::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right-20, Bottom); + VScrollBarBox.Set(Right-20 +1, Top+CH + 33, Right, Bottom); + Color = aColor; + #undef CH + + ActiveLineNum=0; + + ListView.ColHeight = 33; + ListView.TopIndex=0; + ListView.RowCount = 9; + ListView.FixColTop = Content.Top; + ListView.FixColBottom = ListView.FixColTop + ListView.ColHeight; + ListView.ColTop[0] = ListView.FixColBottom + 1; + ListView.ColBottom[0] = ListView.ColTop[0] + ListView.ColHeight -1; + ListView.ColLeft[0] = 1; + ListView.ColRight[0] = ListView.ColWidth[0] +1; + for(i=1; i<12; i++){ + ListView.ColTop[i] = ListView.ColTop[i -1] + ListView.ColHeight; + ListView.ColBottom[i] = ListView.ColBottom[i-1] + ListView.ColHeight; + } + for(i=1;i Content.Bottom)y2 = Content.Bottom; + if(x == ListView.SelectedCol){ + RectFillRender(Content.Left, y, Content.Right, y2, SelectedColor); + }else{ + if(x & 1){ + RectFillRender(Content.Left, y, Content.Right, y2, OddColor); + }else{ + RectFillRender(Content.Left, y, Content.Right, y2, Color); + } + } + y = y2 + 1; + if(y>Content.Bottom)break; + } +} + +void TLiteListViewMask::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TLiteListViewMask::DrawCaption(void) +{ + Caption.Show(); +} + +void TLiteListViewMask::DrawVertScrollBar(void) +{ + TVScrollBar::sDrawBySize(VScrollBarBox.Left, VScrollBarBox.Top, + VScrollBarBox.Width, VScrollBarBox.Height, + clMedGray, clGray, + EntryCount, 10, ListView.TopIndex); +} + +void TLiteListViewMask::DrawList(void) +{ + int i, index, BGClr, TextClr, aTop; + unsigned int aClr, aAddr, aP0,aP1;; + if(EntryCount < 1)return; + + RenderContent(); + aTop = ListView.FixColTop + TextTopOffSet; + + SetListColWidth(30,90,100,150,100,100,1,1,1); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, " 序号" ); + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, " 路径"); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, "设备类型"); + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, " 描述 "); + + for(i=0; i-1; j--){ + if(Port[i].ExistTable[j] == 0xA5){ + if(Port[i].StateTable[j] & (dEpStateBitMask)){ + EntryFound.Path0 = i + dADDR_OFFSET_PORT; + EntryFound.Path1 = j +1; + EntryFound.iType0 = dgTYPE_PORT; + EntryFound.iType1 = EpDev[i][j].fData.Split.dType; + FoundNew = 1; + break; + } + } + } + } + //is Port; Find All Next Port Sub Items + if(FoundNew)break; + i = sPath0 -1 -1; + for(; i>-1; i--){ + if(MainCtl.fData.Split.ExistTablePort[i] == 0xA5){ + j = dEP_MAX_COUNT_PER_PORT -1; + for(; j>-1; j--){ + if(Port[i].ExistTable[j] == 0xA5){ + if(Port[i].StateTable[j] & (dEpStateBitMask)){ + EntryFound.Path0 = i + dADDR_OFFSET_PORT; + EntryFound.Path1 = j +1; + EntryFound.iType0 = dgTYPE_PORT; + EntryFound.iType1 = EpDev[i][j].fData.Split.dType; + FoundNew = 1; + break; + } + } + } + if(FoundNew)break; + } + } + } + }while(0); + + if(FoundNew){ + for(i=9; i>0; i--){ + Entry[i].Path0 = Entry[i-1].Path0; + Entry[i].Path1 = Entry[i-1].Path1; + Entry[i].iType0 = Entry[i-1].iType0; + Entry[i].iType1 = Entry[i-1].iType1; + Entry[i].Loaded = Entry[i-1].Loaded; + } + Entry[point].Path0 = EntryFound.Path0; + Entry[point].Path1 = EntryFound.Path1; + Entry[point].iType0 = EntryFound.iType0; + Entry[point].iType1 = EntryFound.iType1; + Entry[point].Loaded = 1; + + ListView.TopIndex--; + } +} + +void TLiteListViewMask::EntryTotalize(void) +{ + unsigned int i,j; + EntryCount = 0; + for(i=0; i已屏蔽设备", Caption.Text); +} + +TGuiMsgReturn TLiteListViewMask::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if(aKey == VK_TAB){ + + } + if(1){ + if(VK_UP == aKey){ + if(ListView.SelectedCol >0){ + ListView.SelectedCol--; + DrawList(); + }else{ + if(ListView.TopIndex >0){ + EntryLoadBackward(); + DrawList(); + } + } + }else + if(VK_DOWN == aKey){ + if((ListView.TopIndex + ListView.SelectedCol) < (EntryCount-1) ){ + if( ListView.SelectedCol < (ListLineCnt -1) ){ + ListView.SelectedCol++; + DrawList(); + }else{ + if( (ListView.TopIndex + ListLineCnt) < EntryCount ){ + EntryLoadForward(); + DrawList(); + } + } + } + } + } + + if(aKey == VK_EXECUTE){ + //Open path Device + }else + if(aKey == VK_F2){ + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + return aMsg; +} + + + + diff --git a/MyCode/Gui/LiteListViewMask.h b/MyCode/Gui/LiteListViewMask.h new file mode 100644 index 0000000..4d37da0 --- /dev/null +++ b/MyCode/Gui/LiteListViewMask.h @@ -0,0 +1,121 @@ +#ifndef LITELISTVIEWMASK_H_ +#define LITELISTVIEWMASK_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" + +//For Device View or Edit +class TLiteListViewMask{ + public: + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + struct{ + int TopIndex; + int SelectedCol; + unsigned short RowCount; + unsigned short ColTop[12]; + unsigned short ColBottom[12]; + unsigned short ColHeight; + unsigned short ColWidth[12]; + unsigned short ColLeft[12]; + unsigned short ColRight[12]; + unsigned short FixColTop; + unsigned short FixColBottom; + }ListView; + public: + TStaticText Caption; + int ActiveLineNum; + int LineCount; + int LineHeight; + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + int SelectedIndex; + int EntryCount; + + struct{ + unsigned char Path0; + unsigned char Path1; + unsigned char iType0; + unsigned char iType1; + unsigned int Loaded; + }Entry[10],EntryFound; + + TMyString Str; + + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TLiteListViewMask(){}; + TLiteListViewMask(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + unsigned int ItemGetIcon(unsigned int aIndex); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void RenderContent(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void EntryClear(); + void EntryLoadForward(void); + void EntryLoadBackward(void); + void EntryTotalize(void); + void EntryFindByIndex(unsigned int aIndex); + void EntryLoad(void); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/LiteSelfCheck.cpp b/MyCode/Gui/LiteSelfCheck.cpp new file mode 100644 index 0000000..d2ca30d --- /dev/null +++ b/MyCode/Gui/LiteSelfCheck.cpp @@ -0,0 +1,671 @@ +#include "RuntimeData.h" +#include "LiteSelfCheck.h" + +void TLiteSelfCheck::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left, Top, Width, CH, 0, 0, clWhite, clMaroon); + SText.Init (429, Top, 370, CH, 0, 0, clWhite, clMaroon); + + Content.Set(Left, Top+CH, Right, Bottom); + + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + + IsShowing = 0; + CtlIndex = 0; + IsCheckWhat =0; + Seq =0; + AlramCountDown =0; + + IsGo = 0; + + CheckCmdHasSend = 0; + +} + +void TLiteSelfCheck::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TLiteSelfCheck::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TLiteSelfCheck::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderBackGround(); +} + + +void TLiteSelfCheck::DrawCaption2(void) +{ + //TMyString::sFromStr("TAB键在编辑与类型列表之间切换", SText.Text); + //SText.Show(); +} + +void TLiteSelfCheck::Show(void) +{ + IsShowing = 1; + RenderBackGround(); + DrawSelf(); + if(LanguageEnCn==0)TMyString::sFromStr("自检-本机", Caption.Text); + else TMyString::sFromStr("Local Self-Check", Caption.Text); + Caption.Show(); + + Tick = 0; + Seq =0; + CheckCmdHasSend = 0; + IsGo =1; + IsSelfChecking = 1; +} + +void TLiteSelfCheck::ShowCaption() +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); + Caption.Show(); +} + +//______________________________________________________________________________________________________________________________ +void TLiteSelfCheck::Check4Selected(void) +{ + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + + if(CtlIndex == 0){ + aPanel->Btn[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Btn[1].Selected = 1; + } +} + +void TLiteSelfCheck::ShowMsg(int p) +{ + if(LanguageEnCn==0){ + if(p==0){ + TMyString::sFromStr("自检开始", Text); + }else{ + TMyString::sFromStr("自检完成", Text); + } + }else{ + if(p==0){ + TMyString::sFromStr("Self-Check Begins", Text); + }else{ + TMyString::sFromStr("Self-Check Completed", Text); + } + } + RectFillRender(4, 34, 796, 436, clNearWhite); + TextRender_string24(360, 140, clNearBlack, clNearWhite, Text); +} + +//_____________________________________________________________________________________________________________________________ + +void TLiteSelfCheck::ClearOutText() +{ + TMyString::sClear(aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP0_LcdRed() +{ + TMyString::sFromStr(" LCD红色 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP1_LcdGreen() +{ + TMyString::sFromStr(" LCD绿色 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP2_LcdBlue() +{ + TMyString::sFromStr(" LCD蓝色 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP3_PanelLedAllDarking() +{ + TMyString::sFromStr(" 面板指示灯全部熄灭 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP4_PanelLedAllLighting() +{ + TMyString::sFromStr(" 面板指示灯全部点亮 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP5_PanelLedSeq() +{ + TMyString::sFromStr(" 面板指示灯依次点亮 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP6_BusPadLedDarkAll() +{ + TMyString::sFromStr("多线盘指示灯全部熄灭", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP7_BusPadLedLightAll() +{ + TMyString::sFromStr("总线盘指示灯全部点亮", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + + +void TLiteSelfCheck::CheckCP8_DirectPadLedDarkAll() +{ + TMyString::sFromStr("多线盘指示灯全部熄灭", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP9_DirectPadLedLightAll() +{ + TMyString::sFromStr("多线盘指示灯全部点亮", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckCP10_Speaker() +{ + TMyString::sFromStr(" 扬声器发声 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::CheckFireAlram() +{ + TMyString::sFromStr(" 警报声 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::ForceStopAll() +{ + TMyString::sFromStr(" 全部停止 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::DoneAll() +{ + TMyString::sFromStr(" 完成 ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TLiteSelfCheck::iRun() +{ + unsigned int m; + m = Tick % 5; + switch(m){ + case 0: + RectFillRender(0, 0, 799, 479, clRed); + break; + case 1: + RectFillRender(0, 0, 799, 479, clGreen); + break; + case 2: + RectFillRender(0, 0, 799, 479, clBlue); + break; + case 3: + RectFillRender(0, 0, 799, 479, clBlack); + break; + case 4: + RectFillRender(0, 0, 799, 479, clWhite); + break; + case 5: + RectFillRender(0, 0, 799, 479, clRed); + break; + case 6: + RectFillRender(0, 0, 799, 479, clGreen); + break; + case 7: + RectFillRender(0, 0, 799, 479, clBlue); + break; + case 8: + RectFillRender(0, 0, 799, 479, clBlack); + break; + case 9: + RectFillRender(0, 0, 799, 479, clWhite); + break; + case 10: + RectFillRender(0, 0, 799, 479, clAqua); + break; + case 11: + RectFillRender(0, 0, 799, 479, clAqua); + break; + case 12: + RectFillRender(0, 0, 799, 479, clWhite); + break; + } +} + +void TLiteSelfCheck::Task1000Ms() +{ + if(IsShowing){ + if(IsGo){ + if(CheckCmdHasSend == 0){ + if(SelfCheckSendCmd(1) == 0){ + CheckCmdHasSend = 1; + CtlCenter.IsSendSelfCheckToPad =1; + } + } + if(CheckCmdHasSend){ + iRun(); + Tick++; + if(Tick > 12){ + GuiRedrawBase(); + GuiRedraw(0); + IsGo = 0; + IsShowing = 0; + IsSelfChecking = 0; + FinishCallBack(); + } + } + }else{ + IsShowing = 0; + FinishCallBack(); + } + } + return; + + + if(IsShowing){ + if(IsCheckWhat == 1){ + switch(Seq){ + case 0: + CheckCP0_LcdRed(); + Seq++; + break; + case 1: + CheckCP0_LcdRed(); + Seq++; + break; + case 2: + CheckCP1_LcdGreen(); + Seq++; + break; + case 3: + CheckCP2_LcdBlue(); + Seq++; + break; + case 4: + CheckCP3_PanelLedAllDarking(); + Seq++; + break; + case 5: + CheckCP4_PanelLedAllLighting(); + Seq++; + break; + case 6: + CheckCP3_PanelLedAllDarking(); + Seq++; + break; + case 7: + CheckCP5_PanelLedSeq(); + switch(Tick){ + case 0: break; + case 1: break; + case 2: break; + case 3: break; + case 4: break; + case 5: break; + case 6: break; + case 7: break; + case 8: break; + case 9: break; + case 10: break; + case 11: break; + case 12: break; + case 13: break; + case 14: break; + case 15: break; + case 16: break; + case 17: break; + case 18: break; + case 19: break; + case 20: break; + case 21: break; + case 22: break; + case 23: break; + } + Tick++; + if(Tick > 6){ + Seq++; + } + break; + case 8: + CheckCP6_BusPadLedDarkAll(); + Seq++; + break; + case 9: + CheckCP7_BusPadLedLightAll(); + Seq++; + break; + case 10: + CheckCP8_DirectPadLedDarkAll(); + Seq++; + break; + case 11: + CheckCP9_DirectPadLedLightAll(); + Seq++; + break; + case 12: + CheckCP10_Speaker(); + Seq++; + break; + case 13: + Seq++; + break; + case 14: + Seq++; + break; + case 15: + DoneAll(); + IsCheckWhat =0; + FinishCallBack(); + break; + default: + DoneAll(); + IsCheckWhat =0; + FinishCallBack(); + break; + + } + }else + if(IsCheckWhat == 2){ + if(AlramCountDown){ + AlramCountDown--; + TextDigitRender2Right24(260, 245 ,clNearBlack, clFrmFace, AlramCountDown); + }else{ + DoneAll(); + RectFillRender(260, 245, 283, 268, clFrmFace); + IsCheckWhat = 0; + FinishCallBack(); + } + } + } +} + +TGuiMsgReturn TLiteSelfCheck::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + TDMix aFullPath; + + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + + break; + case VK_LEFT: + + break; + case VK_RIGHT: + + break; + case VK_UP: + if(IsCheckWhat == 0){ + //ClearOutText(); + if(CtlIndex >0){ + CtlIndex--; + // Check4Selected(); + // aPanel->ReDrawItems(); + } + } + break; + case VK_DOWN: + if(IsCheckWhat == 0){ + //ClearOutText(); + if(CtlIndex <1){ + CtlIndex++; + // Check4Selected(); + // aPanel->ReDrawItems(); + } + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + + break; + case dfKEY_QUERY: + + break; + case VK_EXECUTE: + //Do Check Here + if(IsCheckWhat == 0){ + if(CtlIndex == 0){ + // ClearOutText(); + IsCheckWhat =1; + Seq =0; + Tick = 0; + }else + if(CtlIndex == 1){ + // ClearOutText(); + IsCheckWhat =2; + AlramCountDown =10; + } + } + break; + case VK_RETURN: + if(IsGo){ + CheckCancel = 1; + }else{ + IsGo =0; + IsShowing = 0; + IsSelfChecking = 0; + //ForceStopAll(); + aMsg = guiMsgReturn; + } + break; + } + + return aMsg; +} + +void TLiteSelfCheck::SendCmdClearAll() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearAllRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = 0xFe; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TLiteSelfCheck::SendCmdClearOnePort(unsigned char aCc) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearSinglePortRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TLiteSelfCheck::SendCmdClearMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr, unsigned char aType) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearSinglePortRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + Data[3] = sAddr; + Data[4] = eAddr; + Data[5] = aType; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TLiteSelfCheck::SendCmdClearOneAddr(unsigned char aCc, unsigned char aAddr, unsigned char aType) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearSinglePortAddrRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + Data[3] = aAddr; + Data[4] = aAddr; + Data[5] = aType; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +int TLiteSelfCheck::SelfCheckSendCmd(unsigned char SatrtStop) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =2; + + aIde.BitF.Cmd = cmSelfCheck; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = SatrtStop; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + return InnerCan.CmdSendCustomWithReturn(aIde, Data, Len); +} + +int TLiteSelfCheck::ExtRequst(unsigned char Prm) +{ + IsCheckWhat = 0; + IsGo = 0; + IsShowing = 0; + IsSelfChecking = 0; + return 0; +} + + diff --git a/MyCode/Gui/LiteSelfCheck.h b/MyCode/Gui/LiteSelfCheck.h new file mode 100644 index 0000000..668ffa3 --- /dev/null +++ b/MyCode/Gui/LiteSelfCheck.h @@ -0,0 +1,99 @@ +#ifndef LITESELFCHECK_H_ +#define LITESELFCHECK_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TLiteSelfCheck{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + u32 Color; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + TMyString Str; + + int IsShowing; + unsigned char CtlIndex; + unsigned char IsCheckWhat; + unsigned char Seq; + unsigned char Tick; + unsigned char AlramCountDown; + int IsGo; + int CheckCmdHasSend; + int CheckCancel; + unsigned char Data[8]; + char Text[64]; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TLiteSelfCheck(){}; + TLiteSelfCheck(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void ClearOutText(); + + void CheckCP0_LcdRed(); + void CheckCP1_LcdGreen(); + void CheckCP2_LcdBlue(); + void CheckCP3_PanelLedAllDarking(); + void CheckCP4_PanelLedAllLighting(); + void CheckCP5_PanelLedSeq(); + void CheckCP6_BusPadLedDarkAll(); + void CheckCP7_BusPadLedLightAll(); + void CheckCP8_DirectPadLedDarkAll(); + void CheckCP9_DirectPadLedLightAll(); + void CheckCP10_Speaker(); + void CheckFireAlram(); + void ForceStopAll(); + void DoneAll(); + void iRun(); + void ShowMsg(int p); + + void Show(void); + void ShowCaption(); + void ReDraw(void); + void DrawCaption2(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void Check4Selected(void); + + void SendCmdClearAll(); + + void SendCmdClearOnePort(unsigned char aCc); + void SendCmdClearMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr, unsigned char aType); + void SendCmdClearOneAddr(unsigned char aCc, unsigned char aAddr, unsigned char aType); + void SendCmdClear(); + int SelfCheckSendCmd(unsigned char SatrtStop); + + void (*FinishCallBack)(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + +#endif + diff --git a/MyCode/Gui/LnkFecBus.cpp b/MyCode/Gui/LnkFecBus.cpp new file mode 100644 index 0000000..3e2ace4 --- /dev/null +++ b/MyCode/Gui/LnkFecBus.cpp @@ -0,0 +1,367 @@ +#include "LnkFecBus.h" +#include "Runtime.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TLnkFecBusCfg::Init() +{ + CtlIndex = 0; + IsShow = 0; + + IsPermission =0; + + Sta =0; +} + +void TLnkFecBusCfg::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick联动设备控制总线FECBUS"); + + for(int i=0; i联动设备控制总线FECBUS"); + + for(int i=0; i0){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex <2){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + if( CtlIndex==0 ){ + EnBus = EnBus ? 0 : 1; + }else + if( CtlIndex==1 ){ + EnTx = EnTx ? 0 : 1; + }else + if( CtlIndex==2 ){ + EnRx = EnRx ? 0 : 1; + } + ShowCfg(); + break; + case VK_EXECUTE: + //Save Data Here + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 16, 400, 140, 3); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default : + break; + } + + if(VK_EXECUTE != aKey){ + ShowSta(0); + } + } + + return aMsg; +} + +void TLnkFecBusCfg::InitPanel(void) +{ + LoadData(); + Check4Selected(); + ShowCfg(); +} + +void TLnkFecBusCfg::LoadData() +{ + EnBus = FecBusCfg.BusEN; + EnTx = FecBusCfg.TxEN; + EnRx = FecBusCfg.RxEN; + + ShowCfg(); +} + +void TLnkFecBusCfg::RestoreData() +{ + FecBusCfg.BusEN =EnBus; + FecBusCfg.TxEN =EnTx; + FecBusCfg.RxEN =EnRx ; +} + +void TLnkFecBusCfg::ReadSetting() +{ + unsigned int tAddr; + unsigned char tData[4]; + //Read ExistTable + tAddr = dEepAddrFecBusSetting +0; + sDelayMs(10); + eeprom_read_byte(0, tAddr, tData, 4); + + FecBusCfg.BusEN = tData[0]; + FecBusCfg.TxEN = tData[1]; + FecBusCfg.RxEN = tData[2]; + + if(FecBusCfg.BusEN == 0xFF)FecBusCfg.BusEN =0; + if(FecBusCfg.TxEN == 0xFF)FecBusCfg.TxEN =0; + if(FecBusCfg.RxEN == 0xFF)FecBusCfg.RxEN = 0; +} + +void TLnkFecBusCfg::WriteSetting() +{ + unsigned int tAddr; + unsigned char tData[4]; + + tData[0] = FecBusCfg.BusEN; + tData[1] = FecBusCfg.TxEN; + tData[2] = FecBusCfg.RxEN; + tData[3] = 0 ; + + tAddr = dEepAddrFecBusSetting + 0; + sDelayMs(10); + eeprom_write_byte_via_page(0, tAddr, tData, 4); + sDelayMs(10); +} + +void TLnkFecBusCfg::sRecoverSetDefault() +{ + unsigned int tAddr; + unsigned char tData[4]; + + tData[0] = 0; + tData[1] = 0; + tData[2] = 0; + tData[3] = 0 ; + + tAddr = dEepAddrFecBusSetting + 0; + sDelayMs(10); + eeprom_write_byte_via_page(0, tAddr, tData, 4); + sDelayMs(10); + + ReadSetting(); +} + + diff --git a/MyCode/Gui/LnkFecBus.h b/MyCode/Gui/LnkFecBus.h new file mode 100644 index 0000000..70f4a90 --- /dev/null +++ b/MyCode/Gui/LnkFecBus.h @@ -0,0 +1,130 @@ +#ifndef LNKFECBUSCFG_H_ +#define LNKFECBUSCFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +#pragma pack(push, 1) + +class TLnkFecBusCfg{ + public: + static constexpr unsigned short hList[12] = {82,82,82,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[0] + 650, + .y = Lv.Grid.Top[0] + 6, + }; + public: + int IsShow; + class TItemList *IList; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned int CtlIndex; + + int Sta; + + unsigned char EnBus; + unsigned char EnTx; + unsigned char EnRx; + public: + TLnkFecBusCfg(){}; + void Init(); + static void sDelayMs(unsigned int aMs); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void ShowCfg(); + void ShowSta(); + void ShowSta(int aSta); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + void ClearSelected(void); + void Check4Selected(void); + + void LoadData(); + void RestoreData(); + + void PermissionCmdGO(); + void PermissionCmdReturnDraw(); + + static void ReadSetting(); + static void WriteSetting(); + + static void sRecoverSetDefault(); + + int ExtRequst(unsigned char Prm){IsShow =0; return 0;} + +}; + + + + + + + + + + + + + + + + + + + + + + + + + +#pragma pack(pop) + + + +#endif + diff --git a/MyCode/Gui/Maintain.cpp b/MyCode/Gui/Maintain.cpp new file mode 100644 index 0000000..921425f --- /dev/null +++ b/MyCode/Gui/Maintain.cpp @@ -0,0 +1,763 @@ +#include "Maintain.h" +#include "Runtime.h" + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const char cWeek[7][8] = { + "星期一", + "星期二", + "星期三", + "星期四", + "星期五", + "星期六", + "星期天", +}; + +void TMaintain::Init() +{ + Tag.Reset(); + SaveSta = 0; + IsPermission =0; +} + +void TMaintain::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TMaintain::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TMaintain::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; i维保提醒"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "工程名称"); + TextRender_string24(Lv.Grid.Left[0] + 520, Lv.Grid.Top[0] +8, clNearWhite, "运行时长:"); + TextRender_string24(Lv.Grid.Left[0] + 698, Lv.Grid.Top[0] +8, clNearWhite, "天"); + TextRender_string24(Lv.Grid.Left[0] + 746, Lv.Grid.Top[0] +8, clNearWhite, "小时"); + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +10, clNearWhite, "维保提醒"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +50, clNearWhite, "维保间隔时间"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +90, clNearWhite, "定时维保"); + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] +90, clNearWhite, "月"); + TextRender_string24(Lv.Grid.Left[1] + 260, Lv.Grid.Top[1] +90, clNearWhite, "日"); + TextRender_string24(Lv.Grid.Left[1] + 350, Lv.Grid.Top[1] +90, clNearWhite, "月"); + TextRender_string24(Lv.Grid.Left[1] + 410, Lv.Grid.Top[1] +90, clNearWhite, "日"); + TextRender_string24(Lv.Grid.Left[1] + 500, Lv.Grid.Top[1] +90, clNearWhite, "月"); + TextRender_string24(Lv.Grid.Left[1] + 560, Lv.Grid.Top[1] +90, clNearWhite, "日"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 6, 120, 30, 7, clNearWhite, "完成维保", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Project->Maintenance Reminder"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "PrjName"); + TextRender_string24(Lv.Grid.Left[0] + 520, Lv.Grid.Top[0] +8, clNearWhite, "Duration:"); + TextRender_string24(Lv.Grid.Left[0] + 698, Lv.Grid.Top[0] +8, clNearWhite, "D"); + TextRender_string24(Lv.Grid.Left[0] + 746, Lv.Grid.Top[0] +8, clNearWhite, "Hour"); + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +10, clNearWhite, "Reminder"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +50, clNearWhite, "TimeInterval"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +90, clNearWhite, "On Time "); + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] +90, clNearWhite, "M"); + TextRender_string24(Lv.Grid.Left[1] + 260, Lv.Grid.Top[1] +90, clNearWhite, "D"); + TextRender_string24(Lv.Grid.Left[1] + 350, Lv.Grid.Top[1] +90, clNearWhite, "M"); + TextRender_string24(Lv.Grid.Left[1] + 410, Lv.Grid.Top[1] +90, clNearWhite, "D"); + TextRender_string24(Lv.Grid.Left[1] + 500, Lv.Grid.Top[1] +90, clNearWhite, "M"); + TextRender_string24(Lv.Grid.Left[1] + 560, Lv.Grid.Top[1] +90, clNearWhite, "D"); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 6, 120, 30, 7, clNearWhite, "Complete", 14, clNearBlack); + } + TextDigitRender5Right24(Lv.Grid.Left[0] + 636, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun / 24); + TextDigitRender2Right24(Lv.Grid.Left[0] + 722, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun % 24); + TTriangleLeftRight::sDrawRightByHight(Lv.Grid.Left[1] + 252, Lv.Grid.Top[1] +52, 20, clNearWhite); + + ShowLastMaintain(); + aPanel->ReDrawItems(); + ShowIfCustomTime(); +} + +void TMaintain::Show(void) +{ + RenderBackGround(); + DrawSelf(); +} + +void TMaintain::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + }else + if(Prm == 1){ + //RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + RectFillRender(Lv.Grid.Left[3] +200 -10, Lv.Grid.Top[3] +16 -10, Lv.Grid.Left[3] +200 -10 + 420, Lv.Grid.Top[3] +16 -10 + 150, ContentColor); + DrawSelf(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +//______________________________________________________________________________________________________________________________ +void TMaintain::ClearSelected(void) +{ + unsigned int i; + for(i=1; i<8;i++)aPanel->Edit[i].Selected = 0; + if(Tag.Group == 0){ + switch(Tag.Inx0){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, 4, ItemColor); + break; + case 1: + aPanel->Edit[1].Show(); + break; + default: + + break; + } + }else + if(Tag.Group == 1){ + switch(Tag.Inx1){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, 4, ItemColor); + break; + case 1: + aPanel->Edit[2].Show(); + break; + case 2: + aPanel->Edit[3].Show(); + break; + case 3: + aPanel->Edit[4].Show(); + break; + case 4: + aPanel->Edit[5].Show(); + break; + case 5: + aPanel->Edit[6].Show(); + break; + case 6: + aPanel->Edit[7].Show(); + break; + } + }else + if(Tag.Group == 2){ + if(LanguageEnCn==0)TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 6, 120, 30, 7, clNearWhite, "完成维保", 14, clNearBlack); + else TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 6, 120, 30, 7, clNearWhite, "Complete", 14, clNearBlack); + } +} + + +void TMaintain::Check4Selected(void) +{ + unsigned int i; + for(i=1; i<8;i++)aPanel->Edit[i].Selected = 0; + if(Tag.Group == 0){ + switch(Tag.Inx0){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 1: + aPanel->Edit[1].Selected = 1; + if(LanguageEnCn==0){ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("半年"); + else aPanel->Edit[1].Str.FromStr("一年"); + }else{ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("Half"); + else aPanel->Edit[1].Str.FromStr("Year"); + } + aPanel->Edit[1].Show(); + break; + default: + + break; + } + }else + if(Tag.Group == 1){ + switch(Tag.Inx1){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 1: + aPanel->Edit[2].Selected = 1; + aPanel->Edit[2].SetPstTail(); + aPanel->Edit[2].Show(); + break; + case 2: + aPanel->Edit[3].Selected = 1; + aPanel->Edit[3].SetPstTail(); + aPanel->Edit[3].Show(); + break; + case 3: + aPanel->Edit[4].Selected = 1; + aPanel->Edit[4].SetPstTail(); + aPanel->Edit[4].Show(); + break; + case 4: + aPanel->Edit[5].Selected = 1; + aPanel->Edit[5].SetPstTail(); + aPanel->Edit[5].Show(); + break; + case 5: + aPanel->Edit[6].Selected = 1; + aPanel->Edit[6].SetPstTail(); + aPanel->Edit[6].Show(); + break; + case 6: + + aPanel->Edit[7].Selected = 1; + aPanel->Edit[7].SetPstTail(); + aPanel->Edit[7].Show(); + break; + } + }else + if(Tag.Group == 2){ + if(LanguageEnCn==0)TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 6, 120, 30, 7, clBlue, "完成维保", 14, clNearWhite); + else TRoundRect::sDrawBySize(Lv.Grid.Left[2] +60, Lv.Grid.Top[2] + 6, 120, 30, 7, clBlue, "Complete", 14, clNearWhite); + } +} + +void TMaintain::ShowIfCustomTime() +{ + if(Setting.IsCustomTime){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, dRoundR, dWdDisabelClr, 0); + } +} + +void TMaintain::ShowMth() +{ + unsigned char x; + auto show = [&x]() { + x =0; + }; + show(); +} + +void TMaintain::ShowVision() +{ + +} + +void TMaintain::ShowSound() +{ + +} + +void TMaintain::DecIndex() +{ + +} + +void TMaintain::IncIndex() +{ + +} + +void TMaintain::PermissionCmdReturnDraw() +{ + Check4Selected(); + RectFillRender(Lv.Grid.Left[3] +200 -10, Lv.Grid.Top[3] +16 -10, Lv.Grid.Left[3] +200 -10 + 420, Lv.Grid.Top[3] +16 -10 + 150, ContentColor); +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TMaintain::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + int iVal; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + }else{ + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Group == 0){ + if(Tag.Inx0 == 0){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx0 = 1; + Check4Selected(); + }else{ + if(Setting.IsCustomTime) Setting.IsCustomTime = 0; else Setting.IsCustomTime = 1; + ShowIfCustomTime(); + } + }else + if(Tag.Inx0 == 1){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx0 = 0; + Check4Selected(); + }else{ + if(Setting.IsHalfYear)Setting.IsHalfYear = 0; else Setting.IsHalfYear =1; + if(LanguageEnCn==0){ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("半年"); + else aPanel->Edit[1].Str.FromStr("一年"); + }else{ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("Half"); + else aPanel->Edit[1].Str.FromStr("Year"); + } + aPanel->Edit[1].Show(); + } + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 == 0){ + if(VK_RIGHT == aKey){ + ClearSelected(); + Tag.Inx1 = 1; + Check4Selected(); + }else{ + if(Setting.IsCustomTime) Setting.IsCustomTime = 0; else Setting.IsCustomTime = 1; + ShowIfCustomTime(); + } + }else{ + if(Tag.Inx1 == 1){ + if(VK_LEFT == aKey){ + if(aPanel->Edit[2].Pst < 0){ + ClearSelected(); + Tag.Inx1 = 0; + Check4Selected(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + aPanel->Edit[2].ShowCursor(); + } + }else + if(VK_RIGHT == aKey){ + if(aPanel->Edit[2].Pst > 0){ + ClearSelected(); + Tag.Inx1 = 2; + Check4Selected(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + aPanel->Edit[2].ShowCursor(); + } + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + aPanel->Edit[2].ShowCursor(); + } + }else + if(Tag.Inx1 < 7){ + if(VK_LEFT == aKey){ + if(aPanel->Edit[Tag.Inx1 +1].Pst < 0){ + ClearSelected(); + Tag.Inx1 --; + Check4Selected(); + }else{ + aPanel->Edit[Tag.Inx1 +1].KeyIn(aKey); + aPanel->Edit[Tag.Inx1 +1].Show(); + aPanel->Edit[Tag.Inx1 +1].ShowCursor(); + } + }else + if(VK_RIGHT == aKey){ + if( (aPanel->Edit[Tag.Inx1 +1].Pst > 0) && (Tag.Inx1 < 6) ){ + ClearSelected(); + Tag.Inx1 ++; + Check4Selected(); + }else{ + aPanel->Edit[Tag.Inx1 +1].KeyIn(aKey); + aPanel->Edit[Tag.Inx1 +1].Show(); + aPanel->Edit[Tag.Inx1 +1].ShowCursor(); + } + }else{ + aPanel->Edit[Tag.Inx1 +1].KeyIn(aKey); + aPanel->Edit[Tag.Inx1 +1].Show(); + aPanel->Edit[Tag.Inx1 +1].ShowCursor(); + } + } + } + } + break; + case VK_UP: + if(Tag.Group == 1){ + ClearSelected(); + Tag.Group =0; + Check4Selected(); + }else + if(Tag.Group == 2){ + ClearSelected(); + Tag.Group =1; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Group == 0){ + ClearSelected(); + Tag.Group =1; + Check4Selected(); + }else + if(Tag.Group == 1){ + ClearSelected(); + Tag.Group =2; + Check4Selected(); + } + break; + case VK_F1: + if(Tag.Group == 0){ + if(Tag.Inx0 == 0){ + if(Setting.IsCustomTime) Setting.IsCustomTime = 0; else Setting.IsCustomTime = 1; + ShowIfCustomTime(); + }else + if(Tag.Inx0 == 1){ + if(Setting.IsHalfYear)Setting.IsHalfYear = 0; else Setting.IsHalfYear =1; + if(LanguageEnCn==0){ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("半年"); + else aPanel->Edit[1].Str.FromStr("一年"); + }else{ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("Half"); + else aPanel->Edit[1].Str.FromStr("Year"); + } + aPanel->Edit[1].Show(); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 == 0){ + if(Setting.IsCustomTime) Setting.IsCustomTime = 0; else Setting.IsCustomTime = 1; + ShowIfCustomTime(); + } + } + break; + case VK_EXECUTE: + //Save Data Here + if(Tag.Group < 2){ + if(SystemPermission >1){ + PermissionCmd = 0; + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = 0; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[3] +200, Lv.Grid.Top[3] +16, 400, 130, 2); + } + }else + if(Tag.Group == 2){ + if(SystemPermission >1){ + PermissionCmd = 1; + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[3] +200, Lv.Grid.Top[3] +16, 400, 130, 2); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + if( (aKey != VK_EXECUTE) && (aKey != VK_RETURN) ){ + ShowSta(0); + } + } + + return aMsg; +} + +void TMaintain::InitPanel(void) +{ + int i; + aPanel->Init(400,400,10,10,0,0,clFrmFace, bvRaised); + + aPanel->Edit[0].Init(Lv.Grid.Left[0] +104, Lv.Grid.Top[0] + 2, 400, 32, 0,0, 1,ItemColor); + + aPanel->Edit[1].Init(Lv.Grid.Left[1] +194, Lv.Grid.Top[1] + 46,54, 30, 0,0, 1,ItemColor); + + aPanel->Edit[2].Init(Lv.Grid.Left[1] +164,Lv.Grid.Top[1] + 86,32,30,0,0,1,ItemColor); + aPanel->Edit[3].Init(Lv.Grid.Left[1] +224,Lv.Grid.Top[1] + 86,32,30,0,0,1,ItemColor); + aPanel->Edit[4].Init(Lv.Grid.Left[1] +314,Lv.Grid.Top[1] + 86,32,30,0,0,1,ItemColor); + aPanel->Edit[5].Init(Lv.Grid.Left[1] +374,Lv.Grid.Top[1] + 86,32,30,0,0,1,ItemColor); + aPanel->Edit[6].Init(Lv.Grid.Left[1] +464,Lv.Grid.Top[1] + 86,32,30,0,0,1,ItemColor); + aPanel->Edit[7].Init(Lv.Grid.Left[1] +524,Lv.Grid.Top[1] + 86,32,30,0,0,1,ItemColor); + + for(i=0; i<1; i++){ + aPanel->Edit[i].IsShowCursor = 0; + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + } + for(i=1; i<2; i++){ + aPanel->Edit[i].IsShowCursor = 0; + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + } + for(i=2; i<8; i++){ + aPanel->Edit[i].IsShowCursor = 1; + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + } + for(i=1; i<8;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(2); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("20"); + aPanel->Edit[2].SetPstTail(); + } +} + +void TMaintain::ExtLoadData() +{ + ExtLoadSetting.IsCustomTime = MaintainData.fDa.IsCustomTime; + ExtLoadSetting.IsHalfYear = MaintainData.fDa.IsHalfYear; + ExtLoadSetting.Month[0] = MaintainData.fDa.Month0; + ExtLoadSetting.Month[1] = MaintainData.fDa.Month1; + ExtLoadSetting.Month[2] = MaintainData.fDa.Month2; + ExtLoadSetting.Month[3] = MaintainData.fDa.Month3; + ExtLoadSetting.Day[0] = MaintainData.fDa.Day0; + ExtLoadSetting.Day[1] = MaintainData.fDa.Day1; + ExtLoadSetting.Day[2] = MaintainData.fDa.Day2; + ExtLoadSetting.Day[3] = MaintainData.fDa.Day3; +} + +void TMaintain::LoadData() +{ + Setting.IsCustomTime = MaintainData.fDa.IsCustomTime; + Setting.IsHalfYear = MaintainData.fDa.IsHalfYear; + Setting.Month[0] = MaintainData.fDa.Month0; + Setting.Month[1] = MaintainData.fDa.Month1; + Setting.Month[2] = MaintainData.fDa.Month2; + Setting.Month[3] = MaintainData.fDa.Month3; + Setting.Day[0] = MaintainData.fDa.Day0; + Setting.Day[1] = MaintainData.fDa.Day1; + Setting.Day[2] = MaintainData.fDa.Day2; + Setting.Day[3] = MaintainData.fDa.Day3; + + for(int i=0; i<32; i++){ + aPanel->Edit[0].Str.Text[i] = PrjName[i]; + } + aPanel->Edit[0].Str.Text[32] = '\0'; + aPanel->Edit[0].Str.Text[33] = '\0'; + + if(LanguageEnCn==0){ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("半年"); + else aPanel->Edit[1].Str.FromStr("一年"); + }else{ + if(Setting.IsHalfYear)aPanel->Edit[1].Str.FromStr("Half"); + else aPanel->Edit[1].Str.FromStr("Year"); + } + + aPanel->Edit[2].Str.FromUInt2Dg(Setting.Month[0]); + aPanel->Edit[4].Str.FromUInt2Dg(Setting.Month[1]); + aPanel->Edit[6].Str.FromUInt2Dg(Setting.Month[2]); + + aPanel->Edit[3].Str.FromUInt2Dg(Setting.Day[0]); + aPanel->Edit[5].Str.FromUInt2Dg(Setting.Day[1]); + aPanel->Edit[7].Str.FromUInt2Dg(Setting.Day[2]); + + ShowIfCustomTime(); + aPanel->ReDrawItems(); + + Check4Selected(); +} + +void TMaintain::WriteData() +{ + Setting.Month[0] = aPanel->Edit[2].Str.ToInteger(); + Setting.Month[1] = aPanel->Edit[4].Str.ToInteger(); + Setting.Month[2] = aPanel->Edit[6].Str.ToInteger(); + Setting.Day[0] = aPanel->Edit[3].Str.ToInteger(); + Setting.Day[1] = aPanel->Edit[5].Str.ToInteger(); + Setting.Day[2] = aPanel->Edit[7].Str.ToInteger(); + + Setting.Month[3] = 2; + Setting.Day[3] = 2; + + ToWriteBytes[0] = Setting.IsCustomTime; + ToWriteBytes[1] = Setting.IsHalfYear; + ToWriteBytes[2] = 1; + ToWriteBytes[3] = 1; + ToWriteBytes[4] = Setting.Month[0]; + ToWriteBytes[5] = Setting.Day[0]; + ToWriteBytes[6] = Setting.Month[1]; + ToWriteBytes[7] = Setting.Day[1]; + ToWriteBytes[8] = Setting.Month[2]; + ToWriteBytes[9] = Setting.Day[2]; + ToWriteBytes[10] = Setting.Month[3]; + ToWriteBytes[11] = Setting.Day[3]; + + Record.WriteMaintain(ToWriteBytes); + Record.ReadMaintain(); + + int WriteOk = 1; + for(int i=0; i<12; i++){ + if(MaintainData.D8[i] != ToWriteBytes[i]){ + WriteOk = 0; + break; + } + } + + if(WriteOk){ + ShowSta(1); + }else{ + ShowSta(-1); + } +} + +void TMaintain::sRecoverSetDefault() +{ + unsigned char tWb[20]; + tWb[0] = 0; //Setting.IsCustomTime; + tWb[1] = 1; //Setting.IsHalfYear; + tWb[2] = 1; + tWb[3] = 1; + tWb[4] = 1; //Setting.Month[0]; + tWb[5] = 1; //Setting.Day[0]; + tWb[6] = 1; // Setting.Month[1]; + tWb[7] = 1; //Setting.Day[1]; + tWb[8] = 1; //Setting.Month[2]; + tWb[9] = 1; //Setting.Day[2]; + tWb[10] = 1; //Setting.Month[3]; + tWb[11] = 1; //Setting.Day[3]; + tWb[12] = 0; + tWb[13] = 0; + tWb[14] = 0; + tWb[15] = 0; + tWb[16] = 0; + tWb[17] = 0; + + Record.WriteMaintain(tWb); + Record.ReadMaintain(); + + LastMaintain.Day = 0x01; + LastMaintain.Month = 0x01; + LastMaintain.Year = 0x20; + LastMaintain.Cent = 0x20; + (void)Record.WriteLastMaintainTime(); + + Check4MaintainToShow(); + if(IsSelfChecking == 0) + StateBarReflashMaintain(); +} + +void TMaintain::ShowLastMaintain() +{ + if(LanguageEnCn==0)TextRender_string24(Lv.Grid.Left[2] +280, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "上次维保时间:"); + else TextRender_string24(Lv.Grid.Left[2] +280, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, " Last Time:"); + + ToWriteBytes[0] = 2 + '0'; + ToWriteBytes[1] = 0 + '0'; + ToWriteBytes[2] = LastMaintain.Year / 16 % 10 + '0'; + ToWriteBytes[3] = LastMaintain.Year % 16 % 10 + '0'; + ToWriteBytes[4] = '/'; + ToWriteBytes[5] = LastMaintain.Month / 16 % 10 + '0'; + ToWriteBytes[6] = LastMaintain.Month % 16 % 10 + '0'; + ToWriteBytes[7] = '/'; + ToWriteBytes[8] = LastMaintain.Day / 16 % 10 + '0'; + ToWriteBytes[9] = LastMaintain.Day % 16 % 10 + '0'; + ToWriteBytes[10] = ' '; + ToWriteBytes[11] = '\0'; + ToWriteBytes[12] = '\0'; + + TextRender_string24(Lv.Grid.Left[2] +280 + 156, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, ToWriteBytes); + + if(LanguageEnCn!=0){ + TextRender_string24(Lv.Grid.Left[2] +580, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "(Year/Month/Day)"); + } +} + +int TMaintain::WriteLastDate() +{ + LastMaintain.Day = DateTime.Date.Split.Day; + LastMaintain.Month = DateTime.Date.Split.Month; + LastMaintain.Year = static_cast(DateTime.Date.Split.Year & 0x00FF); + LastMaintain.Cent = 0x20; + + if(0 == Record.WriteLastMaintainTime()){ + return 0; + }else{ + //error here + return -1; + } +} + +void TMaintain::ShowSta() +{ + if(SaveSta == 0){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, " "); + }else + if(SaveSta == 1){ + if(LanguageEnCn==0)TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "保存成功 "); + else TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "Save OK "); + }else + if(SaveSta == -1){ + if(LanguageEnCn==0)TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "保存失败 "); + else TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "Failed To Save"); + } +} + +void TMaintain::ShowSta(int aSta) +{ + SaveSta = aSta; + ShowSta(); +} + +void TMaintain::StartUpInit() +{ + Seconeds =0; +} + +void TMaintain::DoCheckPerSec() +{ + +} + + +void TMaintain::PermissionCmdGO() +{ + int aVal; + unsigned char aBits; + switch(PermissionCmd){ + case 0: + WriteData(); + break; + case 1: + if(0 == WriteLastDate()){ + ShowLastMaintain(); + IsMaintainTip = 0; + StateBarReflashMaintain(); + }else{ + ShowLastMaintain(); + } + break; + } +} + + + + + + diff --git a/MyCode/Gui/Maintain.h b/MyCode/Gui/Maintain.h new file mode 100644 index 0000000..9a293b1 --- /dev/null +++ b/MyCode/Gui/Maintain.h @@ -0,0 +1,137 @@ +#ifndef MAINTAIN_H_ +#define MAINTAIN_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TMaintain{ + public: + static constexpr unsigned short hList[12] = {36,126,40,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 3, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[2] + 340, + .y = Lv.Grid.Top[2] + 132, + }; + static constexpr TPoint ResultSavePoint = { + .x = Lv.Grid.Left[3] + 40, + .y = Lv.Grid.Top[3] + 12, + }; + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + int IsPermission; + int PermissionCmd; + public: + TStaticText Caption; + + u32 Color; + + + TRect Bound; + TRect Content; + + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Dump0; + void Reset(){ + Group = 0; + Inx0 = 0; + Inx1 = 0; + } + }Tag; + struct{ + unsigned char IsCustomTime; + unsigned char IsHalfYear; + unsigned char Dump0; + unsigned char Dump1; + unsigned char Month[8]; + unsigned char Day[8]; + }Setting, ExtLoadSetting; + unsigned char ToWriteBytes[20]; + int SaveSta; + int Seconeds; + public: + TMaintain(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void FullRedraw(int Prm); + void ReDraw(void); + void ShowMth(); + void ShowVision(); + void ShowSound(); + void ShowIfCustomTime(); + + void ClearSelected(void); + void Check4Selected(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + + void DecIndex(); + void IncIndex(); + void InitPanel(); + + void ExtLoadData(); + void LoadData(); + void WriteData(); + static void sRecoverSetDefault(); + + void ShowSta(); + void ShowSta(int aSta); + + void StartUpInit(); + void DoCheckPerSec(); + + void ShowLastMaintain(); + int WriteLastDate(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/MessageBox.cpp b/MyCode/Gui/MessageBox.cpp new file mode 100644 index 0000000..d3ae36b --- /dev/null +++ b/MyCode/Gui/MessageBox.cpp @@ -0,0 +1,418 @@ +#include"MessageBox.h" + +#define CH 30 //Caption Height + +void TMessageBox::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + BoxBound.Set(Left+200,Top+CH+50, Right-200, Bottom-180); + SText.Init(60,24,BoxBound.Width - 60 - 7, CH, BoxBound.Left, BoxBound.Top, clNearBlack, clFrmFace); + + Caption.Border.Color = clGray; + + Color = aColor; + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + BoxColor = clFrmFace; + + sIndex = 2; + + DoWhatDone = 0; + ReturnVal[0] = guiMsgReturn; + ReturnVal[1] = guiMsgReturn; + ReturnVal[2] = guiMsgReturn; + ReturnVal[3] = guiMsgReturn; + + Btn[0].Init(0,0,90,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[1].Init(200,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[2].Init(310,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[3].Init(310,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + + Caption.TextClear(); + SText.TextClear(); + Btn[0].Caption.Clear(); + Btn[1].Caption.Clear(); + Btn[2].Caption.Clear(); + Btn[3].Caption.Clear(); +} + +void TMessageBox::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TMessageBox::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TMessageBox::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + +void TMessageBox::SetBtnOkCancel() +{ + sIndex = 2; + + Btn[0].Visible = 0; + Btn[1].Visible = 0; + Btn[2].Visible = 0; + + Btn[0].Init(0,0,90,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[1].Init(200,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[2].Init(310,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + + Btn[1].Enable = 0; + Btn[1].Visible = 1; + Btn[1].SetCaptionLeftSpacing(6); + Btn[1].SelectedColor = clBlue; + Btn[2].Enable = 1; + Btn[2].Visible = 1; + Btn[2].SetCaptionLeftSpacing(6); + Btn[2].SelectedColor = clBlue; + + Btn[1].Caption.FromStr("确定"); + Btn[2].Caption.FromStr("返回"); +} + +void TMessageBox::SetBtnOk1Ok2Cancel() +{ + sIndex = 2; + + Btn[0].Visible = 0; + Btn[1].Visible = 0; + Btn[2].Visible = 0; + Btn[3].Visible = 0; + + + Btn[0].Init(90, 90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[1].Init(200,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[2].Init(310,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[3].Init(310,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + + Btn[0].Enable = 0; + Btn[0].Visible = 1; + Btn[0].SetCaptionLeftSpacing(6); + Btn[0].SelectedColor = clBlue; + Btn[1].Enable = 0; + Btn[1].Visible = 1; + Btn[1].SetCaptionLeftSpacing(6); + Btn[1].SelectedColor = clBlue; + Btn[2].Enable = 1; + Btn[2].Visible = 1; + Btn[2].SetCaptionLeftSpacing(6); + Btn[2].SelectedColor = clBlue; +} + +void TMessageBox::DrawBox(void) +{ + RectFillRender(BoxBound.Left, BoxBound.Top, BoxBound.Right, BoxBound.Bottom, BoxColor); + + VertLineRender(BoxBound.Left, BoxBound.Top, BoxBound.Height -1, 0xFFFFFFFF); + VertLineRender(BoxBound.Right -1, BoxBound.Top +1, BoxBound.Height -2, 0xFF808080); + VertLineRender(BoxBound.Right, BoxBound.Top, BoxBound.Height, 0xFF404040); + + HorizLineRender(BoxBound.Left, BoxBound.Top, BoxBound.Width - 1, 0xFFFFFFFF); + HorizLineRender(BoxBound.Left +1, BoxBound.Bottom -1, BoxBound.Width - 2, 0xFF808080); + HorizLineRender(BoxBound.Left, BoxBound.Bottom, BoxBound.Width, 0xFF404040); +} + +void TMessageBox::DrawBtn() +{ + if(Btn[0].Visible){ + Btn[0].Show(); + } + if(Btn[1].Visible){ + Btn[1].Show(); + } + if(Btn[2].Visible){ + Btn[2].Show(); + } + if(Btn[3].Visible){ + Btn[3].Show(); + } +} + +void TMessageBox::SetBoxColor(unsigned int aClr) +{ + BoxColor = aClr; +} + +void TMessageBox::CheckSelect() +{ + Btn[0].Selected=0; + Btn[1].Selected=0; + Btn[2].Selected=0; + Btn[3].Selected=0; + if(sIndex == 0){ + Btn[0].Selected = 1; + }else + if(sIndex == 1){ + Btn[1].Selected = 1; + } + if(sIndex == 2){ + Btn[2].Selected = 1; + }else + if(sIndex == 3){ + Btn[3].Selected = 1; + } +} + +void TMessageBox::DrawMessage() +{ + SText.Show(); +} + +void TMessageBox::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawBox(); + DrawMessage(); + CheckSelect(); + DrawBtn(); +} + +int TMessageBox::FindNextBtn(int aLR) +{ + int i, aInx; + aInx = sIndex; + if(DoWhatDone){ + if(aLR <0){ + for(i=0; i<4; i++){ + aInx--; + if(aInx < 0)aInx = 3; + if(Btn[aInx].Enable){ + sIndex = aInx; + return 1; + } + } + }else + if(aLR >0){ + for(i=0; i<4; i++){ + aInx++; + if(aInx >3)aInx = 0; + if(Btn[aInx].Enable){ + sIndex = aInx; + return 1; + } + } + } + } + return 0; +} + +TGuiMsgReturn TMessageBox::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aCh; + + if(aKey == VK_LEFT){ + if(DoWhatDone){ + if(FindNextBtn(-1)){ + CheckSelect(); + DrawBtn(); + } + } + }else + if(aKey == VK_RIGHT){ + if(FindNextBtn(1)){ + CheckSelect(); + DrawBtn(); + } + } + + if(aKey == VK_EXECUTE){ + //Save Data Here + if(DoWhatDone){ + aMsg = ReturnVal[sIndex]; + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + return aMsg; +} + + +void TMessageBox::SetReturnValue(TGuiMsgReturn aV0, TGuiMsgReturn aV1, TGuiMsgReturn aV2, TGuiMsgReturn aV3) +{ + ReturnVal[0] = aV0; + ReturnVal[1] = aV1; + ReturnVal[2] = aV2; + ReturnVal[3] = aV3; +} + +void TMessageBox::DoWait4ExitLogin() +{ + volatile unsigned int i; + SText.Init(100,24,BoxBound.Width - 40 -7, CH, BoxBound.Left, BoxBound.Top, clNearBlack, clFrmFace); + SText.SetText("确认退出登录", 24); + SText.TextColor = clRed; + Btn[1].Visible = 1; + Btn[2].Visible = 1; + DrawMessage(); + DoWhatDone = 1; + Btn[1].Enable = 1; + DrawBtn(); +} + +void TMessageBox::DoWait4RunMode() +{ + volatile unsigned int i; + Btn[0].Visible = 0; + Btn[1].Visible = 0; + Btn[2].Visible = 0; + Btn[3].Visible = 0; + + + Btn[0].Init(70, 90,110,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[1].Init(190,90,110,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[2].Init(310,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + Btn[3].Init(310,90,70,36, BoxBound.Left,BoxBound.Top,clNearBlack,clFrmFace); + + Btn[0].Enable = 0; + Btn[0].Visible = 1; + Btn[0].SetCaptionLeftSpacing(6); + Btn[0].SelectedColor = clBlue; + Btn[1].Enable = 0; + Btn[1].Visible = 1; + Btn[1].SetCaptionLeftSpacing(6); + Btn[1].SelectedColor = clBlue; + Btn[2].Enable = 1; + Btn[2].Visible = 1; + Btn[2].SetCaptionLeftSpacing(6); + Btn[2].SelectedColor = clBlue; + + SText.Init(25,24,300, CH, BoxBound.Left, BoxBound.Top, clNearBlack, clFrmFace); + SText.SetText("选择要运行的状态,按确定执行", 24); + SText.TextColor = clRed; + Btn[0].Visible = 1; + Btn[1].Visible = 1; + Btn[2].Visible = 1; + Btn[0].Caption.FromStr("正常运行"); + Btn[1].Caption.FromStr("调试运行"); + Btn[2].Caption.FromStr("返回"); + Btn[0].Enable = 1; + Btn[1].Enable = 1; + SText.TextColor = clNearBlack; + + DoWhatDone = 1; +} + +void TMessageBox::DoWait4EnterSelfCheck() +{ + volatile unsigned int i; + SText.Init(60,24,BoxBound.Width - 60 -7, CH, BoxBound.Left, BoxBound.Top, clNearBlack, clFrmFace); + SText.SetText("按确定键开始系统自检", 24); + SText.TextColor = clRed; + Btn[1].Visible = 1; + Btn[2].Visible = 1; + DrawMessage(); + for(i=0; i< 40000000; i++); + DoWhatDone = 1; + Btn[1].Enable = 1; + SText.TextColor = clNearBlack; + DrawBtn(); +} + +void TMessageBox::DoWait4SaveCurrent() +{ + volatile unsigned int i; + SText.Init(40,24,BoxBound.Width - 40 -7, CH, BoxBound.Left, BoxBound.Top, clNearBlack, clFrmFace); + SText.SetText("按确定键保存,按返回键返回", 24); + SText.TextColor = clRed; + Btn[1].Visible = 1; + Btn[2].Visible = 1; + DrawMessage(); + for(i=0; i< 40000000; i++); + DoWhatDone = 1; + Btn[1].Enable = 1; + SText.TextColor = clNearBlack; + DrawBtn(); +} + +void TMessageBox::DoReadWriteBusPad() +{ + volatile unsigned int i; + SText.Init(25,24,BoxBound.Width - 25 -7, CH, BoxBound.Left, BoxBound.Top, clNearBlack, clFrmFace); + SText.SetText("选择要运行的状态,按确定执行", 24); + SText.TextColor = clRed; + Btn[0].Visible = 1; + Btn[1].Visible = 1; + Btn[2].Visible = 1; + Btn[0].Caption.FromStr("读取编程"); + Btn[1].Caption.FromStr("保存编程"); + Btn[2].Caption.FromStr("返回"); + DrawMessage(); + for(i=0; i< 40; i++); + DoWhatDone = 1; + Btn[0].Enable = 1; + Btn[1].Enable = 1; + SText.TextColor = clNearBlack; + DrawMessage(); + DrawBtn(); +} + +void TMessageBox::ReqAdjMode() +{ + volatile unsigned int i; + SText.Init(100,24,200, CH, BoxBound.Left, BoxBound.Top, clNearBlack, clFrmFace); + SText.SetText("进入调试状态", 24); + SText.TextColor = clRed; + Btn[1].Visible = 1; + Btn[2].Visible = 1; + DrawMessage(); + DoWhatDone = 1; + Btn[1].Enable = 1; + DrawBtn(); +} + + + + + + + + + diff --git a/MyCode/Gui/MessageBox.h b/MyCode/Gui/MessageBox.h new file mode 100644 index 0000000..3272737 --- /dev/null +++ b/MyCode/Gui/MessageBox.h @@ -0,0 +1,77 @@ +#ifndef TMESSAGEBOX_H_ +#define TMESSAGEBOX_H_ + +#include "gType.h" +#include "gValue.h" +#include "GraphBase.h" +#include "TEdit.h" +#include "TButton.h" +#include "StaticText.h" + +class TMessageBox{ + public: + TStaticText Caption; + + TStaticText SText; + + TRect Bound; + TRect Content; + TRect BoxBound; + + TButton Btn[4]; + + u32 Color; + u32 BoxColor; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + unsigned char sIndex; + unsigned char BtnNum; + + unsigned char DoWhatDone; + TGuiMsgReturn ReturnVal[4]; + + public: + TMessageBox(){}; + TMessageBox(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + }; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void Show(); + + void SetBox(int x, int y, int x2, int y2, unsigned int aClr); + void SetBoxColor(unsigned int aClr); + void DrawBox(); + void SetBtn(); + + void CheckSelect(); + void DrawMessage(); + void DrawBtn(); + + void InitItems(); + int FindNextBtn(int aLR); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void SetBtnOkCancel(); + void SetBtnOk1Ok2Cancel(); + + void DoWait4ExitLogin(); + void DoWait4EnterAdj(); + void DoWait4ExitAdj(); + void DoWait4RunMode(); + void DoWait4EnterSelfCheck(); + void DoWait4SaveCurrent(); + void DoReadWriteBusPad(); + void ReqAdjMode(); + + void SetReturnValue(TGuiMsgReturn aV0, TGuiMsgReturn aV1, TGuiMsgReturn aV2, TGuiMsgReturn aV3); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + +#endif diff --git a/MyCode/Gui/MyLongString.cpp b/MyCode/Gui/MyLongString.cpp new file mode 100644 index 0000000..2d201df --- /dev/null +++ b/MyCode/Gui/MyLongString.cpp @@ -0,0 +1,953 @@ +#include "math.h" +#include "my_font.h" +#include "MyLongString.h" + +static void reverse(char *str, int n) +{ + int p = 0, q = n-1; + char t; + while (p < q) { + t = str[p]; + str[p] = str[q]; + str[q] = t; + p++; + q--; + } +} + +void TMyLongString::Clear(void) +{ + Text[0] = 0; + Text[1] = 0; + Text[2] = 0; +} + +void TMyLongString::Insert(const char *source, int Pst) +{ + //dMYSTRING_LENGTH + int i,x; + unsigned int ilen, len; + unsigned int sp; + const char *aP = source; + + x = GetEndPst(); + if(x <= Pst){ + AddOnStr(source); + return; + } + + for(i=0; i0){ + e = d % 10; + TmpChar[i] = e + '0'; + i++; + d /= 10; + } + if(sig){ + d = i; + while(i>0){ + Text[d-i] = TmpChar[i-1]; + i--; + } + Text[d] = 0; + }else{ + d = i; + while(i>0){ + Text[d-i+1] = TmpChar[i-1]; + i--; + } + Text[0] = '-'; + Text[d+1] = 0; + } + } +} + +void TMyLongString::FromUInt4Dg(unsigned int data) +{ + unsigned int d,e; + + d = data/1000; + e = d % 10; + Text[0] = e + '0'; + + d = data/100; + e = d % 10; + Text[1] = e + '0'; + + d = data/10; + e = d % 10; + Text[2] = e + '0'; + + e = data % 10; + Text[3] = e + '0'; + + Text[4] = 0; +} + +void TMyLongString::FromUInt6Dg(unsigned int data) +{ + unsigned int d,e; + + d = data/100000; + e = d % 10; + Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text[4] = e + '0'; + + e = data % 10; + Text[5] = e + '0'; + + Text[6] = 0; +} + + +void TMyLongString::AddOnDgMax6(unsigned int data) +{ + unsigned int d,e,i,pst, IsFound; + pst = GetEndPst() +1; + if(pst > (dMYLONGSTRING_LENGTH - 8))return; + + IsFound = 0; + + d = data/100000; + e = d % 10; + if(e>0){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10000; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/1000; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/100; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + e = data % 10; + Text[pst++] = e + '0'; + + Text[pst++] = 0; + Text[pst++] = 0; +} + +void TMyLongString::AddOn6Dg(unsigned int data) +{ + unsigned int d,e,i,pst; + pst = GetEndPst() +1; + if(pst > (dMYLONGSTRING_LENGTH - 8))return; + + d = data/100000; + e = d % 10; + Text[pst] = e + '0'; + + d = data/10000; + e = d % 10; + Text[pst+1] = e + '0'; + + d = data/1000; + e = d % 10; + Text[pst+2] = e + '0'; + + d = data/100; + e = d % 10; + Text[pst+3] = e + '0'; + + d = data/10; + e = d % 10; + Text[pst+4] = e + '0'; + + e = data % 10; + Text[pst+5] = e + '0'; + + Text[pst+6] = 0; +} + +void TMyLongString::AddOn4Dg(unsigned int data) +{ + unsigned int d,e,i,pst; + pst = GetEndPst() +1; + if(pst > (dMYLONGSTRING_LENGTH - 6))return; + + d = data/1000; + e = d % 10; + Text[pst] = e + '0'; + + d = data/100; + e = d % 10; + Text[pst+1] = e + '0'; + + d = data/10; + e = d % 10; + Text[pst+2] = e + '0'; + + e = data % 10; + Text[pst+3] = e + '0'; + + Text[pst+4] = 0; +} + +void TMyLongString::FromUInt3Dg(unsigned int data) +{ + unsigned int i; + unsigned int d,e; + + d = data/100; + e = d % 10; + Text[0] = e + '0'; + + d = data/10; + e = d % 10; + Text[1] = e + '0'; + + e = data % 10; + Text[2] = e + '0'; + + Text[3] = 0; + Text[4] = 0; +} + +void TMyLongString::AddOn3Dg(unsigned int data) +{ + unsigned int i,pst; + unsigned int d,e; + + pst = GetEndPst() +1; + if(pst > (dMYLONGSTRING_LENGTH - 5))return; + + d = data/100; + e = d % 10; + Text[pst] = e + '0'; + + d = data/10; + e = d % 10; + Text[pst+1] = e + '0'; + + e = data % 10; + Text[pst+2] = e + '0'; + + Text[pst+3] = 0; + Text[pst+4] = 0; +} + +void TMyLongString::FromUInt2Dg(unsigned int data) +{ + unsigned int i; + unsigned int d,e; + + d = data/10; + Text[0] = d + '0'; + + e = data % 10; + Text[1] = e + '0'; + + Text[2] = 0; + Text[3] = 0; +} + +void TMyLongString::AddOn2Dg(unsigned int data) +{ + unsigned int i,pst; + unsigned int d,e; + + pst = GetEndPst() +1; + if(pst > (dMYLONGSTRING_LENGTH - 4))return; + + d = data/10; + Text[pst] = d + '0'; + + e = data % 10; + Text[pst+1] = e + '0'; + + Text[pst+2] = 0; + Text[pst+3] = 0; +} + +void TMyLongString::FormFloat(float fd) +{ + //unsigned int ava_bit = 0; + float f = fd; + unsigned int sig; + signed int i = 0; + signed int n = (int)f; + + if(f < 0){ + sig = 0; + f *= -1; + }else{ + sig = 1; + } + n = (unsigned int)f; + f -= n; + i = 0; + do{ + Text[i++] = n % 10 + '0'; + n /= 10; + }while(n > 0); + if(0 == sig) Text[i++] = '-'; + + reverse(Text , i); + Text[i++] = '.'; + n = 0; + do{ + int t = (int)(f * 10); + Text[i++] = t + '0'; + f = f * 10 - t; + n++; + }while(f > 0 && n < 9); + Text[i] = '\0'; +} + +int TMyLongString::ToInteger(void) +{ + signed int Result; + unsigned int i; + unsigned int sig; + + if(Text[0] == '-'){ + sig = 0; + i = 1; + }else{ + sig = 1; + i = 0; + } + Result = 0; + while(1){ + if(Text[i] < '0' || Text[i] > '9'){ + if(Text[i] == 0) break; + Result = 0; + break; + }else{ + Result *= 10; + Result += Text[i] - '0'; + } + i++; + } + if(sig == 0) Result = 0 - Result; + return Result; + +} + +float TMyLongString::ToFloat(void) +{ + float Result; + + float f; + unsigned int i; + unsigned int sig; + unsigned int dot_found = 0; + signed int Decimal_counts = 0; + unsigned int valid_char_counts = 0; + if(Text[0] == '-'){ + sig = 0; + i = 1; + }else{ + sig = 1; + i = 0; + } + Result = 0; + dot_found = 0; + Decimal_counts = 0; + while(1){ + if((Text[i] < '0' || Text[i] > '9') && (Text[i] != '.')){ + if(Text[i] != 0){ + Result = 0; + break; + }else{ + break; + } + }else{ + if(Text[i] == '.'){ + dot_found++; + }else{ + if(Text[i] == '0'){ + if(valid_char_counts)valid_char_counts++; + }else{ + valid_char_counts++; + } + + if(dot_found == 0){ + Result *= 10; + Result += Text[i] - '0'; + }else if(dot_found == 1){ + Decimal_counts -=1; + if(valid_char_counts > 12)break; +// f = (Text[i] - '0') * pow(10,Decimal_counts); + Result += f; + }else{ + // error '0.0.' more then one dot found + Result = 0; + break; + } + } + } + i++; + } + if(sig == 0) Result *= -1; + return Result; + +} + + +//Static function----------------> +void TMyLongString::sFromStr(char *source, char *dest) +{ + unsigned int i; + unsigned int len; + len = dMYLONGSTRING_LENGTH -1; + for(i=0; i (dMYLONGSTRING_LENGTH - 8))return; + + IsFound = 0; + + d = data/100000; + e = d % 10; + if(e>0){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10000; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/1000; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/100; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + e = data % 10; + dest[pst++] = e + '0'; + + dest[pst++] = 0; + dest[pst++] = 0; +} + + +void TMyLongString::sAddOn5Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYLONGSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYLONGSTRING_LENGTH - 7))return; + + d = data/10000; + e = d % 10; + dest[pst] = e + '0'; + + d = data/1000; + e = d % 10; + dest[pst+1] = e + '0'; + + d = data/100; + e = d % 10; + dest[pst+2] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+3] = e + '0'; + + e = data % 10; + dest[pst+4] = e + '0'; + + dest[pst+5] = 0; +} + + +void TMyLongString::sAddOn4Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYLONGSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYLONGSTRING_LENGTH - 7))return; + + d = data/1000; + e = d % 10; + dest[pst] = e + '0'; + + d = data/100; + e = d % 10; + dest[pst+1] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+2] = e + '0'; + + e = data % 10; + dest[pst+3] = e + '0'; + + dest[pst+4] = 0; +} + + +void TMyLongString::sAddOn3Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYLONGSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYLONGSTRING_LENGTH - 5))return; + + d = data/100; + e = d % 10; + dest[pst] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+1] = e + '0'; + + e = data % 10; + dest[pst+2] = e + '0'; + + dest[pst+3] = 0; +} + +void TMyLongString::sAddOn1Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYLONGSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYLONGSTRING_LENGTH - 5))return; + + e = data % 10; + dest[pst] = e + '0'; + + dest[pst+1] = 0; +} + +void TMyLongString::sAddOn2Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYLONGSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYLONGSTRING_LENGTH - 5))return; + + d = data/10; + e = d % 10; + dest[pst] = e + '0'; + + e = data % 10; + dest[pst+1] = e + '0'; + + dest[pst+2] = 0; +} + +int TMyLongString::sGetLen(char *source) +{ + int i,aLen; + aLen = 0; + for(i=0; i<1024; i++){ + if(*source !=0 ){ + aLen++; + }else{ + break; + } + source++; + } + return aLen; +} + +void TMyLongString::sFillFixLen(char *source, unsigned int aLen) +{ + unsigned int len, i; + len = sGetLen(source); + for(i=len; i< aLen; i++){ + source[i] = ' '; + } + source[aLen] = 0; +} + +void TMyLongString::sClear(char *dest) +{ + dest[0] = 0; + dest[1] = 0; + dest[2] = 0; + dest[3] = 0; +} + +int TMyLongString::sToInteger(char *Src) +{ + signed int Result; + unsigned int i; + unsigned int sig; + + if(Src[0] == '-'){ + sig = 0; + i = 1; + }else{ + sig = 1; + i = 0; + } + Result = 0; + while(1){ + if(Src[i] < '0' || Src[i] > '9'){ + if(Src[i] == 0) break; + Result = 0; + break; + }else{ + Result *= 10; + Result += Src[i] - '0'; + } + i++; + } + if(sig == 0) Result = 0 - Result; + return Result; + +} + + + + + + + + + diff --git a/MyCode/Gui/MyLongString.h b/MyCode/Gui/MyLongString.h new file mode 100644 index 0000000..5043b71 --- /dev/null +++ b/MyCode/Gui/MyLongString.h @@ -0,0 +1,71 @@ +#ifndef MYLONGSTRING_H_ +#define MYLONGSTRING_H_ + +#include"GraphBase.h" + +#define dMYLONGSTRING_LENGTH 260 + +class TMyLongString{ + private: + char TmpChar[dMYLONGSTRING_LENGTH]; + public: + char Text[dMYLONGSTRING_LENGTH]; + public: + void Clear(void); + + void FromInt(int d); + + void FromUInt6Dg(unsigned int data); + void FromUInt4Dg(unsigned int data); + void FromUInt3Dg(unsigned int data); + void FromUInt2Dg(unsigned int data); + + int GetLength(void); + int GetEndPst(void); + void AddOnDgMax6(unsigned int data); + void AddOn6Dg(unsigned int data); + void AddOn4Dg(unsigned int data); + void AddOn3Dg(unsigned int data); + void AddOn2Dg(unsigned int data); + + void FormFloat(float fd); + int ToInteger(void); + float ToFloat(void); + + void FromStr(const char *source); + void FromStr( char *source); + void AddOnStr(const char *source); + void AddOnStr( char *source); + void ToStr(char *Dest, unsigned int len); + void Insert(const char *source, int Pst); + void Insert(char *source, int Pst); + unsigned int Delete(int Pst); + + static void sClear(char *dest); + static void sFromStr(char *source, char *dest); + static void sFromStr(const char *source, char *dest); + static void sFrom3Dg(unsigned int d, char *dest); + static void sFrom4Dg(unsigned int d, char *dest); + static void sAddOnStr(const char *source, char *dest); + static void sAddOnDgMax6(unsigned int data, char *dest); + static void sAddOn5Dg(unsigned int d, char *dest); + static void sAddOn4Dg(unsigned int d, char *dest); + static void sAddOn3Dg(unsigned int d, char *dest); + static void sAddOn2Dg(unsigned int d, char *dest); + static void sAddOn1Dg(unsigned int d, char *dest); + static int sGetLen(char *source); + static void sFillFixLen(char *source, unsigned int aLen); + static int sToInteger(char *Src); +}; + + +#endif + + + + + + + + + diff --git a/MyCode/Gui/NewRegister.cpp b/MyCode/Gui/NewRegister.cpp new file mode 100644 index 0000000..fbfacc0 --- /dev/null +++ b/MyCode/Gui/NewRegister.cpp @@ -0,0 +1,901 @@ +#include "NewReGister.h" +#include "MainCtl.h" + +#define nrdNoneColor clMedGray + + +#define TextTopOffSet 6 +#define ListLineCnt 10 + + +static const char *StrWaitForReply = "等待接收到新数据"; +static const char *StrGotNewReg = "已接收一个注册包"; + +void TNewRegister::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right-20, Bottom); + VScrollBarBox.Set(Right-20 +1, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + ActiveLineNum=0; + + ListView.ColHeight = 33; + ListView.TopIndex=0; + ListView.RowCount = 9; + ListView.FixColTop = Content.Top; + ListView.FixColBottom = ListView.FixColTop + ListView.ColHeight; + ListView.ColTop[0] = ListView.FixColBottom + 1; + ListView.ColBottom[0] = ListView.ColTop[0] + ListView.ColHeight -1; + ListView.ColLeft[0] = 1; + ListView.ColRight[0] = ListView.ColWidth[0] +1; + for(i=1; i<12; i++){ + ListView.ColTop[i] = ListView.ColTop[i -1] + ListView.ColHeight; + ListView.ColBottom[i] = ListView.ColBottom[i-1] + ListView.ColHeight; + } + for(i=1;i Content.Bottom)y2 = Content.Bottom; + if(x == ListView.SelectedCol){ + RectFillRender(Content.Left, y, Content.Right, y2, SelectedColor); + }else{ + if(x & 1){ + RectFillRender(Content.Left, y, Content.Right, y2, OddColor); + }else{ + RectFillRender(Content.Left, y, Content.Right, y2, Color); + } + } + y = y2 + 1; + if(y>Content.Bottom)break; + } +} + +void TNewRegister::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TNewRegister::DrawCaption(void) +{ + Caption.Show(); +} + +void TNewRegister::DrawVertScrollBar(void) +{ + TVScrollBar::sDrawBySize(VScrollBarBox.Left, VScrollBarBox.Top, + VScrollBarBox.Width, VScrollBarBox.Height, + VScrollBar.RibbonColor, VScrollBar.Color, + 10, 10, ListView.TopIndex); +} + +void TNewRegister::DrawBtn(unsigned int x, unsigned int y, unsigned int x2, unsigned int y2, unsigned int aClr) +{ + RectFillRender(x, y, x2, y2, aClr); + + VertLineRender(x, y, y2-y+1-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y +1, y2-y+1-2, 0xFF808080); + VertLineRender(x2, y, y2-y+1-2, 0xFF404040); + + HorizLineRender(x, y, x2-x+1-1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, x2-x+1 - 2, 0xFF808080); + HorizLineRender(x, y2, x2-x+1, 0xFF404040); +} + +void TNewRegister::DrawCtlItem() +{ + unsigned int x, y, x2, y2, aClr, aClrText; + + TMyString::sFromStr("注册设备-本机", Caption.Text); + DrawCaption(); + + Content.SetWidth(Bound.Width -7); + RenderBackGround(clMoneyGreen); + + x =100; y =100; x2 =420; y2 = y+36; //0 + if(CtlIndex == 0){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+30,y+6, aClrText, "读取显示本机原注册信息"); + + x =100; y =160; x2 =420; y2 = y+36; //1 + if(CtlIndex == 1){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+30,y+6, aClrText, "开始重新注册"); + + x =100; y =220; x2 =420; y2 = y+36; //2 + if(CtlIndex == 2){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + if(NewRegCompleted) + TextRender_string24(x+30,y+6, aClrText, "显示新注册概览"); + else + TextRender_string24(x+30,y+6, clSilver, "显示新注册概览"); + + x =100; y =280; x2 =420; y2 = y+36; //3 + if(CtlIndex == 3){aClr = clRed; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + if(NewRegCompleted) + TextRender_string24(x+30,y+6, aClrText, "保存到本机 !"); + else + TextRender_string24(x+30,y+6, clSilver, "保存到本机 !"); + + x =100; y =340; x2 =420; y2 = y+36; //3 + if(CtlIndex == 4){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+30,y+6, aClrText, "停止注册并退出"); +} + +void TNewRegister::DrawList(void) +{ + int i, index, BGClr, TextClr, aTop; + unsigned int aClr; + //if(EntryCount < 1)return; + + RenderContent(); + aTop = ListView.FixColTop + TextTopOffSet; + + SetListColWidth(30,90,100,130,100,100,1,1,1); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, " 序号" ); + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, " 路径"); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, "设备类型"); + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "棣属于"); + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, "棣属于"); + + for(i=0; iCountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountAllDevice); + + aTop = ListView.ColTop[1] + TextTopOffSet; + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountRootDev); + + aTop = ListView.ColTop[2] + TextTopOffSet; + if(aP->CountRootDev)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountPort); + + aTop = ListView.ColTop[3] + TextTopOffSet; + if(aP->CountHandCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtl); + + aTop = ListView.ColTop[4] + TextTopOffSet; + if(aP->CountDirectCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtl); + + aTop = ListView.ColTop[5] + TextTopOffSet; + if(aP->CountMotherBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountMotherBoard); + + aTop = ListView.ColTop[6] + TextTopOffSet; + if(aP->CountCommBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountCommBoard); + + aTop = ListView.ColTop[7] + TextTopOffSet; + if(aP->CountEpAll)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountEpAll); + + aTop = ListView.ColTop[8] + TextTopOffSet; + if(aP->CountHandCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtlPad); + + aTop = ListView.ColTop[9] + TextTopOffSet; + if(aP->CountDirectCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtlPad); + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + + aTop = ListView.ColTop[0] + TextTopOffSet; + if(aP->CountEp.Smoker)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Smoker); + + aTop = ListView.ColTop[1] + TextTopOffSet; + if(aP->CountEp.Tempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Tempe); + + aTop = ListView.ColTop[2] + TextTopOffSet; + if(aP->CountEp.SmokeTempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.SmokeTempe); + + aTop = ListView.ColTop[3] + TextTopOffSet; + if(aP->CountEp.HandReport)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.HandReport); + + aTop = ListView.ColTop[4] + TextTopOffSet; + if(aP->CountEp.Input)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Input); + + aTop = ListView.ColTop[5] + TextTopOffSet; + if(aP->CountEp.Output)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Output); + + aTop = ListView.ColTop[6] + TextTopOffSet; + if(aP->CountEp.InOut)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.InOut); + + aTop = ListView.ColTop[7] + TextTopOffSet; + if(aP->CountEp.VaAlram)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.VaAlram); + + aTop = ListView.ColTop[8] + TextTopOffSet; + if(aP->CountEp.BusBroke)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.BusBroke); + + aTop = ListView.ColTop[9] + TextTopOffSet; + if(aP->CountEp.DisplayPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.DisplayPad); + + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + + aTop = ListView.ColTop[0] + TextTopOffSet; + if(aP->CountEp.UnDefine)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.UnDefine); + + aTop = ListView.ColTop[1] + TextTopOffSet; + if(aP->CountEp.Unknown)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.Unknown); +} + +void TNewRegister::DrawOverViewAllHost() +{ + TThisMainCtl *aP = &MainCtl; + if(aP == nullptr)return; +} + +void TNewRegister::DrawOverViewHost() +{ + int i; + unsigned int aTop, aClr; + TThisMainCtl *aP = &MainCtl; + //Line0,ALl + //Line1,CountRootDev + //Line2,CountPort + //Line3,CountHandCtl + //Line4,CountDirectCtl + //Line5,CountMotherBoard + //Line6,CountCommBoard + //Line7,CountEpAll + //Line8,CountHandCtlPad + //Line9,CountDirectCtlPad + if(aP == nullptr)return; + + Content.SetWidth(Bound.Width -7); + RenderBackGround(clMoneyGreen); + + TMyString::sFromStr("注册信息详情", Caption.Text); + DrawCaption(); + + SetListColWidth(120,160,130,150,120,120,1,1,1); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, " 条目" ); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, "总数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "所有设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountAllDevice); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "根设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountRootDev); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路" ); + if(aP->CountRootDev)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountPort); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘" ); + if(aP->CountHandCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtl); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘" ); + if(aP->CountDirectCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtl); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路母板" ); + if(aP->CountMotherBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountMotherBoard); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "通讯板" ); + if(aP->CountCommBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountCommBoard); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "终端设备" ); + if(aP->CountEpAll)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountEpAll); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘按钮" ); + if(aP->CountHandCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtlPad); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘按钮" ); + if(aP->CountDirectCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtlPad); + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型烟感" ); + if(aP->CountEp.Smoker)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Smoker); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型温感" ); + if(aP->CountEp.Tempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Tempe); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "烟温一体" ); + if(aP->CountEp.SmokeTempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.SmokeTempe); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "手报" ); + if(aP->CountEp.HandReport)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.HandReport); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入模块" ); + if(aP->CountEp.Input)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Input); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输出模块" ); + if(aP->CountEp.Output)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Output); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入输出模块" ); + if(aP->CountEp.InOut)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.InOut); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "声光报警" ); + if(aP->CountEp.VaAlram)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.VaAlram); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "断路器" ); + if(aP->CountEp.BusBroke)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.BusBroke); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "显示盘" ); + if(aP->CountEp.DisplayPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.DisplayPad); + + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未定义设备" ); + if(aP->CountEp.UnDefine)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.UnDefine); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未知设备" ); + if(aP->CountEp.Unknown)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.Unknown); +} + +void TNewRegister::DrawOverViewReg() +{ + int i; + unsigned int aTop, aClr; + TThisMainCtl *aP = &MainCtlReg; + //Line0,ALl + //Line1,CountRootDev + //Line2,CountPort + //Line3,CountHandCtl + //Line4,CountDirectCtl + //Line5,CountMotherBoard + //Line6,CountCommBoard + //Line7,CountEpAll + //Line8,CountHandCtlPad + //Line9,CountDirectCtlPad + if(aP == nullptr)return; + + Content.SetWidth(Bound.Width -7); + RenderBackGround(clMoneyGreen); + + TMyString::sFromStr("注册信息详情", Caption.Text); + DrawCaption(); + + SetListColWidth(120,160,130,150,120,120,1,1,1); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, " 条目" ); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, "总数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "所有设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountAllDevice); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "根设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountRootDev); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路" ); + if(aP->CountRootDev)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountPort); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘" ); + if(aP->CountHandCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtl); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘" ); + if(aP->CountDirectCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtl); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路母板" ); + if(aP->CountMotherBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountMotherBoard); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "通讯板" ); + if(aP->CountCommBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountCommBoard); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "终端设备" ); + if(aP->CountEpAll)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountEpAll); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘按钮" ); + if(aP->CountHandCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtlPad); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘按钮" ); + if(aP->CountDirectCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtlPad); + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型烟感" ); + if(aP->CountEp.Smoker)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Smoker); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型温感" ); + if(aP->CountEp.Tempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Tempe); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "烟温一体" ); + if(aP->CountEp.SmokeTempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.SmokeTempe); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "手报" ); + if(aP->CountEp.HandReport)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.HandReport); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入模块" ); + if(aP->CountEp.Input)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Input); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输出模块" ); + if(aP->CountEp.Output)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Output); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入输出模块" ); + if(aP->CountEp.InOut)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.InOut); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "声光报警" ); + if(aP->CountEp.VaAlram)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.VaAlram); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "断路器" ); + if(aP->CountEp.BusBroke)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.BusBroke); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "显示盘" ); + if(aP->CountEp.DisplayPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.DisplayPad); + + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未定义设备" ); + if(aP->CountEp.UnDefine)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.UnDefine); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未知设备" ); + if(aP->CountEp.Unknown)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.Unknown); +} + + +TGuiMsgReturn TNewRegister::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if(aKey == VK_TAB){ + + } + if(1){ + if(VK_UP == aKey){ + if(State == nrCtl){ + if(CtlIndex >0){ + CtlIndex--; + if( (CtlIndex == 2) || (CtlIndex == 3) ){ + CtlIndex =1; + } + DrawCtlItem(); + } + } + if(ListView.SelectedCol >0){ + + }else{ + if(ListView.TopIndex >0){ + ReDraw(); + } + } + }else + if(VK_DOWN == aKey){ + if(State == nrCtl){ + if(CtlIndex < 4){ + CtlIndex++; + if( (CtlIndex == 2) || (CtlIndex == 3) ){ + CtlIndex =4; + } + DrawCtlItem(); + } + } + if( ListView.SelectedCol < (ListLineCnt -1) ){ + + }else{ + + } + } + } + + if(aKey == VK_EXECUTE){ + //Open path Device + if(State == nrCtl){ + if(CtlIndex ==0){ + MainCtl.LoadVisioInf(); + DrawOverViewHost(); + State = nrShowDetails; + }else + if(CtlIndex ==1){ + NewRegCompleted = 0; + }else + if(CtlIndex ==2){ + if(NewRegCompleted){ + MainCtlReg.LoadVisioInf(); + DrawOverViewReg(); + State = nrShowDetails; + } + }else + if(CtlIndex ==3){ + if(NewRegCompleted){ + + } + }else + if(CtlIndex ==4){ + //do something before return + aMsg = guiMsgReturn; + } + }else + if(State == nrShowDetails){ + State = nrCtl; + DrawCtlItem(); + } + }else + if(aKey == VK_F2){ + + }else + if(aKey == VK_RETURN){ + if(State == nrShowDetails){ + State = nrCtl; + DrawCtlItem(); + } + } + + return aMsg; +} + diff --git a/MyCode/Gui/NewRegister.h b/MyCode/Gui/NewRegister.h new file mode 100644 index 0000000..102ab4d --- /dev/null +++ b/MyCode/Gui/NewRegister.h @@ -0,0 +1,122 @@ +#ifndef NEWREGISTER_H_ +#define NEWREGISTER_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "StaticText.h" +#include "Device.h" +#include "EpDevice.h" + +#define nrCtl 0 +#define nrShowDetails 1 + +class TNewRegister{ + public: + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + struct{ + int TopIndex; + int SelectedCol; + unsigned short RowCount; + unsigned short ColTop[12]; + unsigned short ColBottom[12]; + unsigned short ColHeight; + unsigned short ColWidth[12]; + unsigned short ColLeft[12]; + unsigned short ColRight[12]; + unsigned short FixColTop; + unsigned short FixColBottom; + }ListView; + public: + TStaticText Caption; + int ActiveLineNum; + int LineCount; + int LineHeight; + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + int SelectedIndex; + + TMyString Str; + + unsigned char State; + unsigned char CtlIndex; + unsigned char NewRegCompleted; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TNewRegister(){}; + TNewRegister(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawVertScrollBar(void); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void RenderContent(void); + + void DrawBtn(unsigned int x, unsigned int y, unsigned int x2, unsigned int y2, unsigned int aClr); + void DrawCtlItem(void); + void ShowCtl(void); + void DrawOverViewName(void); + + void DrawOverViewCountHost(void); + void DrawOverViewAllHost(void); + void DrawOverViewHost(void); + + void DrawOverViewReg(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void Read(); + void Clear(); + void Save(void); + void Search(void); + + void ShowAllInf(); + + void FullRePaint(void); + void RePaint(void); +}; + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/OnTimeCheck.cpp b/MyCode/Gui/OnTimeCheck.cpp new file mode 100644 index 0000000..2d4c51a --- /dev/null +++ b/MyCode/Gui/OnTimeCheck.cpp @@ -0,0 +1,276 @@ +#include "RuntimeData.h" +#include "OnTimeCheck.h" +#include "DevMask.h" + +extern "C"{ + //#include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +void TOnTimeCheck::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + + RectPanel.Set(Left + 420,Top + CH, Right - 4, Top + CH + 6 + 284); + Color = aColor; + #undef CH + + CtlIndex =0; + IsProgram = 0; + + Caption.Border.Color = clGray; +} + +void TOnTimeCheck::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TOnTimeCheck::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TOnTimeCheck::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TOnTimeCheck::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TOnTimeCheck::DrawCaption(void) +{ + TMyString::sFromStr("->", Caption.Text); + Caption.Show(); +} + +void TOnTimeCheck::Show() +{ + DrawSelf(); + DrawCaption(); + TextRender_string24(80, 354 ,clNearBlack, "1."); + TextRender_string24(80, 384 ,clNearBlack, "2."); + TextRender_string24(80, 414 ,clNearBlack, "3."); +} + +void TOnTimeCheck::FullRedraw(int Prm) +{ + int i, x, y; + if(Prm == 0){ + Show(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + } + aPanel->Show(); + aPanel->ReDrawItems(); + ShowPath(); +} + +void TOnTimeCheck::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickEdit[i].Selected = 0; + } + if( (CtlIndex > -1) && (CtlIndex < 12) ){ + aPanel->Edit[CtlIndex].Selected = 1; + } +} + +void TOnTimeCheck::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i, yt; + + RectPanel.Set(80,76, 720, 350); + + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + yt = y+6; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + + aPanel->SText[0].Init(6,4,70,36,x,0,clNearBlack,clFrmFace); + TMyString::sFromStr("总线盘号: 按键数量: 按键号:", aPanel->SText[0].Text); + aPanel->SText[17].Init(20,0,300,30,x,yt,clNearBlack,clFrmFace); + + aPanel->SText[0].Enable = 0; + aPanel->SText[4].Enable = 0; + + + aPanel->Edit[ 0].Init(0,0,48,30,x,yt,clNearBlack,clNearWhite); + + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].Str.FromStr("000"); + aPanel->Edit[i].Pst = 2; + aPanel->Edit[i].Selected = 0; + } + + Check4Selected(); + aPanel->ReDrawItems(); +} + +void TOnTimeCheck::ShowPath() +{ + //TextDigitRender2Right24(212, 124, clNearBlack, clFrmFace, Loaded.P0 +1); + //TextDigitRender2Right24(360, 124, clNearBlack, clFrmFace, Loaded.Key +1); +} + + +void TOnTimeCheck::SaveData() +{ + +} + +TGuiMsgReturn TOnTimeCheck::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int uKey; + unsigned char aIndex; + char LastChr; + const char *p; + int i; + if(1){ + switch(aKey){ + case VK_DELETE: + + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + + break; + case VK_UP: + break; + case VK_DOWN: + break; + case VK_LEFT: + break; + case VK_RIGHT: + break; + case VK_TAB: + break; + case dfKEY_ENCN: + break; + case dfKEY_SETUP: + break; + case dfKEY_QUERY: + break; + case VK_EXECUTE: + break; + } + } + + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + + } + return aMsg; +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/OnTimeCheck.h b/MyCode/Gui/OnTimeCheck.h new file mode 100644 index 0000000..ff7fe17 --- /dev/null +++ b/MyCode/Gui/OnTimeCheck.h @@ -0,0 +1,91 @@ +#ifndef ONTIMECHECK_H_ +#define ONTIMECHECK_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "EditML.h" +#include "CtlPanel1.h" + +class TOnTimeCheck{ + public: + TStaticText Caption; + + u32 Color; + + TRect Bound; + TRect Content; + TRect RectPanel; + class TCtlPanel1 *aPanel; + unsigned char CtlIndexTab; + unsigned char CtlIndex; + unsigned char IsProgram; + unsigned char KeyCount; + public: + TOnTimeCheck(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void RenderBackGround(void); + void DelayMs(unsigned int aMs); + + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void DrawCaption(void); + void Show(); + void FullRedraw(int Prm); + + void ShowPath(); + void LoadData(); + void SaveData(); + + void Check4Selected(); + + void InitPanel(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/OnlineCtrl.cpp b/MyCode/Gui/OnlineCtrl.cpp new file mode 100644 index 0000000..ef33d41 --- /dev/null +++ b/MyCode/Gui/OnlineCtrl.cpp @@ -0,0 +1,452 @@ +#include "OnlineCtrl.h" +#include "XBox.h" +#include "Runtime.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const int xUsb = 20; +const int xRs485 = 160; +const int xCan = 300; +const int xReadOnly = 20; +const int xReadWrite = 160; +const int xActive = 20; +const int xClose = 160; + +void TOnlineCtrl::Init() +{ + CtlIndex = 0; + IsShowing = 0; + IsOnGoing = 0; + LineType =0; + ReadWrite =0; + + IsPermission =0; +} + +void TOnlineCtrl::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick在线调试"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "调试接口选择"); + TextRender_string24(xUsb + 30, Lv.Grid.Top[0] + 40, clNearWhite, "USB"); + TextRender_string24(xRs485 + 30, Lv.Grid.Top[0] + 40, clNearWhite, "UART"); + TextRender_string24(xCan + 30, Lv.Grid.Top[0] + 40, clNearWhite, "内CAN"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "模式选择"); + TextRender_string24(xReadOnly + 30, Lv.Grid.Top[1] +40, clNearWhite, "只读"); + TextRender_string24(xReadWrite + 30, Lv.Grid.Top[1] +40, clNearWhite, "读写"); + TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[2] + 4, 112, 30, 7, clNearWhite, "开启", 26, clNearBlack); + TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[2] + 4, 112, 30, 7, clNearWhite, "关闭", 26, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Data Transmission->Online configuration"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Port Choice"); + TextRender_string24(xUsb + 30, Lv.Grid.Top[0] + 40, clNearWhite, "USB"); + TextRender_string24(xRs485 + 30, Lv.Grid.Top[0] + 40, clNearWhite, "UART"); + TextRender_string24(xCan + 30, Lv.Grid.Top[0] + 40, clNearWhite, "Inner-CAN"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Mode"); + TextRender_string24(xReadOnly + 30, Lv.Grid.Top[1] +40, clNearWhite, "ReadOnly"); + TextRender_string24(xReadWrite + 30, Lv.Grid.Top[1] +40, clNearWhite, "Read Write"); + TRoundRect::sDrawBySize(xActive, Lv.Grid.Top[2] + 4, 112, 30, 7, clNearWhite, "Enable", 14, clNearBlack); + TRoundRect::sDrawBySize(xClose, Lv.Grid.Top[2] + 4, 112, 30, 7, clNearWhite, "Disable", 14, clNearBlack); + } +} + +void TOnlineCtrl::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i0){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + }else{ + ClearSelected(); + CtlIndex=6; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex <6){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + break; + case VK_TAB: + + break; + case dfKEY_SETUP: + if(CtlIndex == 0){ + LineType = 0; + DrawLineType(); + }else + if(CtlIndex == 1){ + LineType = 1; + DrawLineType(); + }else + if(CtlIndex == 2){ + LineType = 2; + DrawLineType(); + }else + if(CtlIndex == 3){ + ReadWrite = 0; + DrawReadWrite(); + }else + if(CtlIndex == 4){ + ReadWrite = 1; + DrawReadWrite(); + } + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + LineType = 0; + DrawLineType(); + }else + if(CtlIndex == 1){ + LineType = 1; + DrawLineType(); + }else + if(CtlIndex == 2){ + LineType = 2; + DrawLineType(); + }else + if(CtlIndex == 3){ + ReadWrite = 0; + DrawReadWrite(); + }else + if(CtlIndex == 4){ + ReadWrite = 1; + DrawReadWrite(); + }else + if(CtlIndex == 5){ + //Active + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[2] + 20, 600 , 140, 3); + } + }else + if(CtlIndex == 6){ + //Close + PermissionCmd = 2; + PermissionCmdGO(); + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +int TOnlineCtrl::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} + +void TOnlineCtrl::Task1000Ms() +{ + +} + + + diff --git a/MyCode/Gui/OnlineCtrl.h b/MyCode/Gui/OnlineCtrl.h new file mode 100644 index 0000000..3f2a43c --- /dev/null +++ b/MyCode/Gui/OnlineCtrl.h @@ -0,0 +1,126 @@ +#ifndef ONLINECTRL_H_ +#define ONLINECTRL_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TOnlineCtrl{ + public: + static constexpr unsigned short hList[12] = {76,76,36,72, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 3, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2, + .Panel.Width = 796, + .Panel.Heigh = 170, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 36 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +2 + 170 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char CrtNum; + unsigned char CrtNumValid; + + char Text[68]; + + unsigned char LineType; + unsigned char ReadWrite; + unsigned char IsOnGoing; + public: + TOnlineCtrl(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DelayMs(unsigned int aMs); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + void DrawLineType(); + void DrawReadWrite(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + +#endif + diff --git a/MyCode/Gui/PadInf.cpp b/MyCode/Gui/PadInf.cpp new file mode 100644 index 0000000..4c8c1bf --- /dev/null +++ b/MyCode/Gui/PadInf.cpp @@ -0,0 +1,577 @@ +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "PadInf.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 +#define IconVcnt 5 +#define IconHcnt 10 + +#define HLineTextRight 780 +#define HSpace 33 + +#define clOdd clMoneyGreen +#define clEven clWhiteBlue + + +const int LeftTitlePoint[8] ={ + 20, 100, 200, 320, 420, 520, 620, 700 +}; + +const int LeftTextPoint[8] ={ + 20, 100, 200, 320, 420, 520, 620, 720 +}; + + +void TPadInf::Init() +{ + Tag.Reset(); + Items.Reset(); + IsShow = 0; + ViewingLevel = 0; +} + +void TPadInf::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TPadInf::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TPadInf::DrawSelf() +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn==0) + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "手动控制盘->信息"); + else + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Manual Control Unit->Information"); + + for(int i=0; i=3)return; + } + if(Items.Type[t] == 0){ + aP0 = Items.Num[t]; + UsingKeyCnt = HandCtlBoard[aP0].KeyCount; + if(HandCtlBoard[aP0].PadIsProhibit == 0)tClr = clNearWhite; else tClr = clWhiteGray; + //Draw Pad Type + if(LanguageEnCn==0) + TextRender_string24(LeftTextPoint[0], Lv.Grid.Top[i+2] + 4, tClr, ItemColor, "总线"); + else + TextRender_string24(LeftTextPoint[0], Lv.Grid.Top[i+2] + 4, tClr, ItemColor, "Bus"); + //Draw Pad Num + TextDigitRender2Right24(LeftTextPoint[1], Lv.Grid.Top[i+2] + 4, tClr, ItemColor, Items.Num[t]+1); + if( (UsingKeyCnt != 48) && (UsingKeyCnt != 64) && (UsingKeyCnt != 128) ) { + UsingKeyCnt = 48; + } + ExistCnt = 0; + for(x=0; xBusPad->KeyIn(aKey); + }else + if(LoadedPad.Type == 1){ + aMsg = this->DirectPad->KeyIn(aKey); + } + + if(aMsg == guiMsgReturn){ + return guiMsgReturn; + } + return guiMsgNone; +} + +TGuiMsgReturn TPadInf::EditKeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg; + //editting + return guiMsgNone; +} + +void TPadInf::ClearSelected(void) +{ + int iT; + iT = Tag.Inx + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], ItemColor); //draw rectangle +} + +void TPadInf::Check4Selected(void) +{ + int iT; + iT = Tag.Inx + 2; + if(iT > 9)return; + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + Lv.Grid.Right[iT], Lv.Grid.Top[iT] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Top[iT], Lv.Grid.Left[iT] + 3, Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[iT] -3, Lv.Grid.Top[iT], Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[iT], Lv.Grid.Bottom[iT] -3, Lv.Grid.Right[iT], Lv.Grid.Bottom[iT], clBlue); //draw rectangle +} + + +TGuiMsgReturn TPadInf::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex, Found; + unsigned char aP0; + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn aMsg2Rtn = guiMsgNone; + //Up or Down One Index___________________ + + if(ViewingLevel == 0){ + if(VK_LEFT ==aKey){ + + }else + if(VK_RIGHT == aKey){ + + }else + if(VK_UP == aKey){ + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Items.Inx--; + Check4Selected(); + }else{ + if(Items.Inx >0){ + Items.Inx--; + Items.TopInx--; + DrawList(); + } + } + }else + if(VK_DOWN == aKey){ + if(Tag.Inx < 7){ + if(Items.Inx < (Items.Count-1)){ + ClearSelected(); + Tag.Inx++; + Items.Inx++; + Check4Selected(); + } + }else{ + Tag.Inx = 7; + if(Items.Inx < (Items.Count-1)){ + Items.Inx++; + Items.TopInx++; + DrawList(); + } + } + }else + if(aKey == VK_TAB){ + + }else + if(aKey == VK_EXECUTE){ + //Open path Device + if(Items.Count > 0){ + if(Items.Inx < Items.Count){ + if(Items.Type[Items.Inx] == 0){ + LoadedPad.Type = 0; + LoadedPad.Num = Items.Num[Items.Inx]; + //设置总线盘联动编程 + BusPadLnk.Init(1); + BusPadLnk.aPanel = &CommonPanel; + BusPadLnk.IList = &ItemList; + BusPadLnk.Show(); + BusPadLnk.SetPath(0,LoadedPad.Num+1,1); + ViewingLevel = 1; + }else + if(Items.Type[Items.Inx] == 1){ + LoadedPad.Type = 1; + LoadedPad.Num = Items.Num[Items.Inx]; + //设置多线盘 + DirectPadCfg.Init(1); + DirectPadCfg.aPanel = &CommonPanel; + DirectPadCfg.IList = &ItemList; + DirectPadCfg.Show(); + DirectPadCfg.SetPath(0,LoadedPad.Num+1,1); + ViewingLevel = 1; + } + } + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + }else{ + + } + }else + if(ViewingLevel == 1){ + if(LoadedPad.Type == 0){ + if(this->BusPad == nullptr){ + aMsg2Rtn = guiMsgReturn; + }else{ + aMsg2Rtn = this->BusPad->KeyIn(aKey); + } + }else{ + if(this->DirectPad == nullptr){ + aMsg2Rtn = guiMsgReturn; + }else{ + aMsg2Rtn = this->DirectPad->KeyIn(aKey); + } + } + if(aMsg2Rtn == guiMsgReturn){ + ViewingLevel = 0; + RenderBackGround(); + DrawSelf(); + DrawTitle(); + DrawDirectPadInf(); + DrawBusPadInf(); + DrawList(); + Check4Selected(); + } + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TPadInf::LoadItem(void) +{ + int i; + Items.Count = 0; + for(i=0; i= Items.Count){ + Items.Inx = Items.Count-1; + } +} + +void TPadInf::ClearItem(void) +{ + Items.Count = 0; +} + + + + + + + + + diff --git a/MyCode/Gui/PadInf.h b/MyCode/Gui/PadInf.h new file mode 100644 index 0000000..b57fcb9 --- /dev/null +++ b/MyCode/Gui/PadInf.h @@ -0,0 +1,201 @@ +#ifndef PADINF_H_ +#define PADINF_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "my_string.h" +#include "Device.h" +#include "BusPadLnk.h" +#include "DirectPadCfg.h" + +#define dLISTVIEW_TYPE_DUMP 0 +#define dLISTVIEW_TYPE_SYS 1 +#define dLISTVIEW_TYPE_EP 2 +#define dLISTVIEW_TYPE_PORT 3 +#define dLISTVIEW_TYPE_HANDCTL 4 +#define dLISTVIEW_TYPE_DIRECTCTL 5 + +#define dLISTVIEW_STYLE_LIST 0 +#define dLISTVIEW_STYLE_ICON 1 +#define dLISTVIEW_VSCOLLBAR_WIDTH 20 + +//For Device View or Edit +class TPadInf{ + public: + static constexpr unsigned short hList[12] = {60,32,32,32, 32,32,32,32, 32,32,32,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]) +2, + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1] +2, + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 10, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + class TBusPadLnk *BusPad; + class TDirectPadCfg *DirectPad; + unsigned char ViewingLevel; + struct{ + int Count; + int Inx; + int TopInx; + unsigned char Type[40]; + unsigned char Num[40]; + void Reset(){ + Inx = 0; + TopInx = 0; + } + }Items; + struct{ + unsigned char Type; + unsigned char Num; + unsigned char Node; + }LoadedPad; + struct{ + unsigned short Path0; + unsigned short Path1; + TRootDevice *RootDev; + TEpDevice *EpDev; + }ItemEnter; + unsigned char TypeAndCount[256]; + unsigned char TypeCount; + unsigned char TypeCountIndex; + unsigned char TypeCountPageIndex; + unsigned char TypeCountPageCount; + unsigned char TypeCharHasShow; + + char Text[80]; + unsigned char TextInputIndex; + + int DrawX,DrawY; + int LastDrawX,LastDrawY; + + int CircuitShowFig; + struct{ + unsigned int Smoke; + unsigned int Tempe; + unsigned int HandReport; + unsigned int HydKp; + unsigned int ModuleInput; + unsigned int ModuleInOut; + unsigned int ModuleOutput; + unsigned int Va; + unsigned int FDisplay; + unsigned int Sv; + unsigned int cOther; + + unsigned int Tt; + }Count; + struct{ + int Inx; + void Reset(){ + Inx = 0; + } + }Tag; + public: + TStaticText SText; + + int IsShow; + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TPadInf(){}; + void Init(); + void LoadItem(); + void ReLoadItem(void); + void ClearItem(); + unsigned int ItemGetIcon(unsigned int aIndex); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + + void DrawSelf(); + void DrawBusPadInf(); + void DrawDirectPadInf(); + void DrawTitle(); + void DrawList(int aIsNotFull =0); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void GetTypeAndCount(); + int FindStartPoint(); + void SetEditMode(unsigned int aMode); + + void CheckNewLine(int aLen); + void ShowCount(unsigned char aP0); + + void FullRePaint(void); + void RePaint(void); + + void ClearSelected(void); + void Check4Selected(void); + + int ExtRequst(unsigned char Prm){ + if(this->BusPad != nullptr) + this->BusPad->ExtRequst(Prm); + if(this->DirectPad != nullptr) + this->DirectPad->ExtRequst(Prm); + IsShow = 0; + return 0; + } +}; + + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/PageIdle.cpp b/MyCode/Gui/PageIdle.cpp new file mode 100644 index 0000000..3c769d1 --- /dev/null +++ b/MyCode/Gui/PageIdle.cpp @@ -0,0 +1,721 @@ +#include "PageIdle.h" +#include "XBox.h" + +//https://www.zhetao.com/fontarray.html +//?°?μí3?y3￡??DD?±￡?384x64￡?×?ì?64x64 +static const char my_font_sys_bitmap_bytes[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +const char cYear[] = "年"; +const char cMonth[] = "月"; +const char cDay[] = "日"; + +const char cWeek[] = "星期"; +const char cWeekX[8][4] = { + "xx", + "一", + "二", + "三", + "四", + "五", + "六", + "天", +}; +const char cWeekXEn[8][12] = { + "xx", + "Mon", + "Tue", + "Wed", + "Thu", + "Fri", + "Sat", + "Sun", +}; + + +void TPageIdle::DrawNormalText(int centre_x, int centre_y, unsigned int cClr, unsigned int bClr) +{ + const char* p; + int start_x; + int start_y; + int ix = 0; + int iy = 0; + unsigned int i; + + if(centre_x > (64*3))start_x = centre_x - 64*3; + else start_x = 0; + + if(centre_y > (64/2))start_y = centre_y - 64/2; + else start_y = 0; + + if(LanguageEnCn==0)p = my_font_sys_bitmap_bytes; + else p = my_font_sys_bitmap_bytes_EN; + + while(iy<64){ + for(i=0;i<8;i++){ + if((*p)&(0x80>>i)){ + PixelRender(start_x+ix, start_y+iy, cClr); + }else{ + PixelRender(start_x+ix, start_y+iy, bClr); + } + ix++; + if(ix>=(64*6)){ + ix=0; + iy++; + } + } + p++; + } +} + +void TPageIdle::sDrawDebugText(int centre_x, int centre_y, unsigned int cClr, unsigned int bClr) +{ + const char* p; + int start_x; + int start_y; + int ix = 0; + int iy = 0; + unsigned int i; + + if(centre_x > (64*3))start_x = centre_x - 64*3; + else start_x = 0; + + if(centre_y > (64/2))start_y = centre_y - 64/2; + else start_y = 0; + + if(LanguageEnCn==0)p = my_font_sys_debug_bitmap_bytes; + else p = my_font_sys_debug_bitmap_bytes_EN; + + while(iy<64){ + for(i=0;i<8;i++){ + if((*p)&(0x80>>i)){ + PixelRender(start_x+ix, start_y+iy, cClr); + }else{ + PixelRender(start_x+ix, start_y+iy, bClr); + } + ix++; + if(ix>=(64*6)){ + ix=0; + iy++; + } + } + p++; + } +} + +void TPageIdle::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, aColor); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = aColor; +} + +void TPageIdle::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TPageIdle::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); + +} + +void TPageIdle::DrawCaption(void) +{ + //TMyString::sFromStr("火灾警报系统正在运行", Caption.Text); + Caption.TextClear(); + Caption.Show(); +} + +void TPageIdle::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + IsShowing = 1; + + ShowPrjName(); + //ShowBuildDateTime(); + HorizLineRender(Content.Left + 50, Content.Top + 36, Bound.Width -100, clNearBlack); + + if(RunState == TRunModeCfg::RunModeAdjust){ + sDrawDebugText(400, 188, clDeepBlue, clRed); + }else{ + DrawNormalText(400, 188, clDeepBlue, Color); + } + + //VertLineRender(460, 280, 110, clNearBlack); + //VertLineRender(720, 280, 110, clNearBlack); + //HorizLineRender(460, 280, 260, clNearBlack); + //HorizLineRender(460, 390, 260, clNearBlack); + + //TextRender_string24(460, 400, clRed, "距离试用期到期还剩"); + //TextRender_string24(716, 400, clRed, "天"); +} + +void TPageIdle::DrawCountDownDay() +{ + //class TDateTime TrialEndDateTime; + //int TrialCountDownDay; + //int TrialEndDay; + //unsigned int i; + //i = TrialCountDownDay; + //if(i >999) i=999; + //TextDigitRender3Right24(678, 400, clRed, Color, i); +} + +void TPageIdle::Hide() +{ + IsShowing = 0; +} + +void TPageIdle::ShowPrjName() +{ + TextRender_string24(Content.Left + 50, Content.Top + 6, clNearBlack, PrjName); +} + +void TPageIdle::ShowBuildDateTime() +{ + #define stRadix 16 + + unsigned int d,e; + + Text[0] = '2'; + Text[1] = '0'; + + d = PrjBuildDateTime.Date.Split.Year /stRadix % 10; + e = PrjBuildDateTime.Date.Split.Year % stRadix; + Text[2] = d + '0'; + Text[3] = e + '0'; + + Text[4] = cYear[0]; + Text[5] = cYear[1]; + + d = PrjBuildDateTime.Date.Split.Month /stRadix % 10; + e = PrjBuildDateTime.Date.Split.Month % stRadix; + Text[6] = d + '0'; + Text[7] = e + '0'; + + Text[8] = cMonth[0]; + Text[9] = cMonth[1]; + + + d = PrjBuildDateTime.Date.Split.Day /stRadix % 10; + e = PrjBuildDateTime.Date.Split.Day % stRadix; + Text[10] = d + '0'; + Text[11] = e + '0'; + + Text[12] = cDay[0]; + Text[13] = cDay[1]; + + Text[14] = '\0'; + TextRender_string24(600, Content.Top + 6, clNearBlack, Text); + +} + +void TPageIdle::ShowRunDateTime() +{ + #define stRadix 16 + + unsigned int d,e; + + Text[0] = '2'; + Text[1] = '0'; + + d = DateTime.Date.Split.Year /stRadix % 10; + e = DateTime.Date.Split.Year % stRadix; + Text[2] = d + '0'; + Text[3] = e + '0'; + + Text[4] = cYear[0]; + Text[5] = cYear[1]; + + d = DateTime.Date.Split.Month /stRadix % 10; + e = DateTime.Date.Split.Month % stRadix; + Text[6] = d + '0'; + Text[7] = e + '0'; + + Text[8] = cMonth[0]; + Text[9] = cMonth[1]; + + + d = DateTime.Date.Split.Day /stRadix % 10; + e = DateTime.Date.Split.Day % stRadix; + Text[10] = d + '0'; + Text[11] = e + '0'; + + Text[12] = cDay[0]; + Text[13] = cDay[1]; + + Text[14] = ' '; + + Text[15] = cWeek[0]; + Text[16] = cWeek[1]; + Text[17] = cWeek[2]; + Text[18] = cWeek[3]; + + d = DateTime.GetWeek(); + if(d > 7) d=0; + Text[19] = cWeekX[d][0]; + Text[20] = cWeekX[d][1]; + + Text[21] = ' '; + + d = DateTime.Time.Split.Hour /stRadix % 10; + e = DateTime.Time.Split.Hour % stRadix; + Text[22] = d + '0'; + Text[23] = e + '0'; + Text[24] = ':'; + + d = DateTime.Time.Split.Minute /stRadix % 10; + e = DateTime.Time.Split.Minute % stRadix; + Text[25] = d + '0'; + Text[26] = e + '0'; + Text[27] = ':'; + + d = DateTime.Time.Split.Second /stRadix % 10; + e = DateTime.Time.Split.Second % stRadix; + Text[28] = d + '0'; + Text[29] = e + '0'; + Text[30] = '\0'; + Text[31] = '\0'; + + TextRender_string24(213, 222, clNearBlack, Color, Text); +} + +void TPageIdle::ShowRunDateTimeEn() +{ + #define stRadix 16 + + unsigned int d,e; + + Text[0] ='Y'; + Text[1] ='/'; + Text[2] ='M'; + Text[3] ='/'; + Text[4] ='D'; + Text[5] =':'; + + Text[6] = '2'; + Text[7] = '0'; + + d = DateTime.Date.Split.Year /stRadix % 10; + e = DateTime.Date.Split.Year % stRadix; + Text[8] = d + '0'; + Text[9] = e + '0'; + + Text[10] = '/'; + + d = DateTime.Date.Split.Month /stRadix % 10; + e = DateTime.Date.Split.Month % stRadix; + Text[11] = d + '0'; + Text[12] = e + '0'; + + Text[13] = '/'; + + d = DateTime.Date.Split.Day /stRadix % 10; + e = DateTime.Date.Split.Day % stRadix; + Text[14] = d + '0'; + Text[15] = e + '0'; + + Text[16] = ' '; + Text[17] = ' '; + + + d = DateTime.GetWeek(); + if(d > 7) d=0; + Text[18] = cWeekXEn[d][0]; + Text[19] = cWeekXEn[d][1]; + Text[20] = cWeekXEn[d][2]; + + Text[21] = ' '; + + d = DateTime.Time.Split.Hour /stRadix % 10; + e = DateTime.Time.Split.Hour % stRadix; + Text[22] = d + '0'; + Text[23] = e + '0'; + Text[24] = ':'; + + d = DateTime.Time.Split.Minute /stRadix % 10; + e = DateTime.Time.Split.Minute % stRadix; + Text[25] = d + '0'; + Text[26] = e + '0'; + Text[27] = ':'; + + d = DateTime.Time.Split.Second /stRadix % 10; + e = DateTime.Time.Split.Second % stRadix; + Text[28] = d + '0'; + Text[29] = e + '0'; + Text[30] = '\0'; + Text[31] = '\0'; + + TextRender_string24(213, 222, clNearBlack, Color, Text); +} + +TGuiMsgReturn TPageIdle::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if(aKey == VK_TAB){ + + } + if(1){ + if(VK_UP == aKey){ + + }else + if(VK_DOWN == aKey){ + + }else + if(VK_LEFT == aKey){ + + }else + if(VK_RIGHT == aKey){ + + } + } + + if(aKey == VK_EXECUTE){ + + }else + if(aKey == VK_F2){ + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + return aMsg; +} + + +void TPageIdle::TaskBySecCall() +{ + if(IsShowing){ + if( (IsShowingMsgReset == 0) &&(IsShowTipPopup == 0) ){ + //if( ((Register.IsOnShow == 0) && (Register.IsOnGo == 0)) && (LiteSelfCheck.IsShowing == 0) )return 0; + if( (CheckIsFrozeScreen()== 0) && (PmsIntervene.IsShow == 0) && (EventShow.IsShowing == 0) ){ + if(LanguageEnCn==0)ShowRunDateTime(); + else ShowRunDateTimeEn(); + DrawCountDownDay(); + } + } + } +} + + + diff --git a/MyCode/Gui/PageIdle.h b/MyCode/Gui/PageIdle.h new file mode 100644 index 0000000..8438a82 --- /dev/null +++ b/MyCode/Gui/PageIdle.h @@ -0,0 +1,67 @@ +#ifndef PAGEIDLE_H_ +#define PAGEIDLE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" + +//For Idle View or Edit +class TPageIdle{ + public: + + public: + TStaticText Caption; + u32 Color; + int IsShowing; + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + char Text[64]; + + public: + TPageIdle(){}; + TPageIdle(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void DrawNormalText(int centre_x, int centre_y, unsigned int cClr, unsigned int bClr); + static void sDrawDebugText(int centre_x, int centre_y, unsigned int cClr, unsigned int bClr); + void DrawSelf(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void RenderContent(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void Hide(); + + void ShowPrjName(); + void ShowBuildDateTime(); + void ShowRunDateTime(); + void ShowRunDateTimeEn(); + void DrawCountDownDay(); + + void TaskBySecCall(); + + int ExtRequst(unsigned char Prm){IsShowing =0; return 0;} +}; + + + + + +#endif + + + + + diff --git a/MyCode/Gui/Panel.cpp b/MyCode/Gui/Panel.cpp new file mode 100644 index 0000000..deb4034 --- /dev/null +++ b/MyCode/Gui/Panel.cpp @@ -0,0 +1,97 @@ +#include "Panel.h" + +void TPanel::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + unsigned short Left,Right,Top,Bottom; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + OwnerLeftTop.x = OwnerX; + OwnerLeftTop.y = OwnerY; + BorderWidth = 2; + Color = aColor; + BevelOuter = aBevelOuter; + if(BevelOuter == bvRaised){ + Left = Bound.Left + 1; + Right = Bound.Right - 2; + Top = Bound.Top + 1; + Bottom = Bound.Bottom - 2; + }else{ + Left = Bound.Left + 2; + Right = Bound.Right - 2; + Top = Bound.Top + 2; + Bottom = Bound.Bottom - 2; + } + + Content.Set(Left,Top,Right,Bottom); +} + +void TPanel::DrawSelf(void) +{ + + /*unsigned int r,g,b, h,l; + h = Color & 0x00FFFFFF; + + r = h / 0x10000; + g = (h / 256) % 256; + b = h % 256; + + h = r * 3 / 2; if(h > 255)h=255; r = h; + h = g * 3 / 2; if(h > 255)h=255; g = h; + h = b * 3 / 2; if(h > 255)h=255; b = h; + h = (r<<16) + (g<<8) + b; + l = r * 2 / 3; r = l; + l = g * 2 / 3; g = l; + l = b * 2 / 3; b = l; + l = (r<<16) + (g<<8) + b; + + + //Draw Border + g = Bound.Right; + b = Bound.Bottom; + + //Draw Right & Bottom + for(r=0; r0) && (MainCtl.fData.Split.MyNum < 65) ){ + Machine[MainCtl.fData.Split.MyNum-1].Exist = 1; + } +} + +TGuiMsgReturn TPanelSelfCheck::KeyIn(unsigned char aKey) +{ + int ind, i, F; + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn MBoxMsg = guiMsgNone; + //Up or Down One Index___________________ + if(AskingEnter){ + MBoxMsg = MessageBox.KeyIn(aKey); + if(MBoxMsg == guiMsgOkAndReturn){ + AskingEnter = 0; + Checking = 1; + Show(); + return guiMsgNone; + } + if(MBoxMsg == guiMsgReturn){ + return guiMsgReturn; + }else{ + return guiMsgNone; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + break; + case VK_UP: + F = 0; + ind = vEdit.Str.ToInteger(); + for(i=0; i 64)ind = 1; + if(Machine[ind-1].Exist){ + vEdit.Str.FromInt(ind); + F = 1; + break; + } + } + if(F){ + vEdit.Show(); + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + break; + } + } + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TPanelSelfCheck::ShowAskingEnter() +{ + MessageBox.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + MessageBox.SetBtnOkCancel(); + MessageBox.SetReturnValue(guiMsgNone, guiMsgOkAndReturn, guiMsgReturn, guiMsgNone); + MessageBox.Show(); + MessageBox.DoWait4EnterSelfCheck(); + AskingEnter = 1; +} + +void TPanelSelfCheck::DoSequence() +{ + if(Checking == 1){ + //if(ccTip) + } +} + +void TPanelSelfCheck::Task1000Ms() +{ + +} + diff --git a/MyCode/Gui/PanelSelfCheck.h b/MyCode/Gui/PanelSelfCheck.h new file mode 100644 index 0000000..678fc10 --- /dev/null +++ b/MyCode/Gui/PanelSelfCheck.h @@ -0,0 +1,175 @@ +#ifndef PANELSELFCHECK_H_ +#define PANELSELFCHECK_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "MainCtl.h" +#include "Runtime.h" +#include "RuntimeData2.h" + +#define dLISTVIEW_VSCOLLBAR_WIDTH 20 + +//For Device View or Edit +class TPanelSelfCheck{ + public: + class TEdit vEdit; + struct{ + struct{ + unsigned char Bat; + unsigned char Mem; + unsigned char CommBoardCount; + unsigned char CircultCount; + + unsigned char HandCtlCount; + unsigned char DirectCtlCount; + unsigned char MotherBoardCount; + unsigned char ExLinkBoardCount; + + unsigned char Dump0; + unsigned char Dump1; + unsigned short EpDevCount; + + }Registed; + struct{ + unsigned char Bat; + unsigned char Mem; + unsigned char CommBoardCount; + unsigned char CircultCount; + + unsigned char HandCtlCount; + unsigned char DirectCtlCount; + unsigned char MotherBoardCount; + unsigned char ExLinkBoardCount; + + unsigned char Dump0; + unsigned char Dump1; + unsigned short EpDevCount; + }Offline; + struct{ + unsigned char Bat; + unsigned char Mem; + unsigned char CommBoardCount; + unsigned char CircultCount; + + unsigned char HandCtlCount; + unsigned char DirectCtlCount; + unsigned char MotherBoardCount; + unsigned char ExLinkBoardCount; + + unsigned char Dump0; + unsigned char Dump1; + unsigned short EpDevCount; + }Fault; + unsigned char CheckState; + unsigned char Dump; + unsigned char CheckOk; + unsigned char Exist; + }Machine[dNETWORK_MACHINE_COUNT]; + public: + TStaticText Caption; + TStaticText SText; + TStaticText STextTip; + + u32 Color; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + + TRect RectMaster; + TRect RectSlave; + char Text[32]; + unsigned char DoIndex; + unsigned char AskingEnter; + unsigned char CheckDone; + unsigned char ViewIndex; + int Checking; + + public: + TPanelSelfCheck(){ + AskingEnter = 1; + DoIndex = 0; + } + TPanelSelfCheck(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + unsigned int ItemGetIcon(unsigned int aIndex); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawSel(); + void DrawList(void); + void TipOut(); + void Show(void); + void ReDraw(void); + void ShowAskingEnter(); + void DrawCaption(void); + void DrawCaption1(void); + void RenderContent(void); + + void DrawStateIdf_0(void); + void DrawOngoGrid(); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void LoadData(void); + + void FullRePaint(void); + void RePaint(void); + void ShowIfSave(); + + void DoSequence(); + + void Task1000Ms(); +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif + diff --git a/MyCode/Gui/PasswdChange.cpp b/MyCode/Gui/PasswdChange.cpp new file mode 100644 index 0000000..58ec020 --- /dev/null +++ b/MyCode/Gui/PasswdChange.cpp @@ -0,0 +1,610 @@ +#include "RuntimeData.h" +#include "PasswdChange.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +void TPasswdChange::Init() +{ + StaII = 0; + StaIII = 0; + + Tag.Reset(); +} + +void TPasswdChange::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TPasswdChange::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + +void TPasswdChange::InitPanel(void) +{ + aPanel->Init(400,400,10,10,0,0,clFrmFace, bvRaised); + + aPanel->Edit[0].Init(Lv.Grid.Left[0] +242, Lv.Grid.Top[0] +10 -4, 210, 32, 0,0, 1, clTeal); + aPanel->Edit[1].Init(Lv.Grid.Left[0] +242, Lv.Grid.Top[0] +46 -4, 210, 32, 0,0, 1, clTeal); + aPanel->Edit[2].Init(Lv.Grid.Left[0] +242, Lv.Grid.Top[0] +82 -4, 210, 32, 0,0, 1, clTeal); + + aPanel->Edit[3].Init(Lv.Grid.Left[0] +242, Lv.Grid.Top[1] +10 -4, 210, 32, 0,0, 1, clTeal); + aPanel->Edit[4].Init(Lv.Grid.Left[0] +242, Lv.Grid.Top[1] +46 -4, 210, 32, 0,0, 1, clTeal); + aPanel->Edit[5].Init(Lv.Grid.Left[0] +242, Lv.Grid.Top[1] +82 -4, 210, 32, 0,0, 1, clTeal); + + for(int i=0; i<6; i++){ + aPanel->Edit[i].Str.Clear(); + aPanel->Edit[i].MaxLen = 16; + aPanel->Edit[i].IsShowCursor = 1; + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].Pst = -1; + aPanel->Edit[i].SetTextShowMaskByAsterisk(); + } + +} + +void TPasswdChange::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; i修改密码"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +10, clNearWhite, "二级权限"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +10, clNearWhite, "三级权限"); + + TextRender_string24(Lv.Grid.Left[0] +142, Lv.Grid.Top[0] +10, clNearWhite, "原密码"); + TextRender_string24(Lv.Grid.Left[0] +142, Lv.Grid.Top[0] +46, clNearWhite, "新密码"); + TextRender_string24(Lv.Grid.Left[0] +142, Lv.Grid.Top[0] +82, clNearWhite, "新密码"); + + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[0] + 166, 100, 40, 7, clDeepBlue, "保存", 14, clNearWhite); + + + TextRender_string24(Lv.Grid.Left[1] +142, Lv.Grid.Top[1] +10, clNearWhite, "原密码"); + TextRender_string24(Lv.Grid.Left[1] +142, Lv.Grid.Top[1] +46, clNearWhite, "新密码"); + TextRender_string24(Lv.Grid.Left[1] +142, Lv.Grid.Top[1] +82, clNearWhite, "新密码"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Local->Change Password"); + + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +10, clNearWhite, "II Key "); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +10, clNearWhite, "III Key "); + + TextRender_string24(Lv.Grid.Left[0] +142, Lv.Grid.Top[0] +10, clNearWhite, "Original"); + TextRender_string24(Lv.Grid.Left[0] +142, Lv.Grid.Top[0] +46, clNearWhite, "New"); + TextRender_string24(Lv.Grid.Left[0] +142, Lv.Grid.Top[0] +82, clNearWhite, "confirm"); + + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[0] + 166, 100, 40, 7, clDeepBlue, "保存", 14, clNearWhite); + + + TextRender_string24(Lv.Grid.Left[1] +142, Lv.Grid.Top[1] +10, clNearWhite, "Original"); + TextRender_string24(Lv.Grid.Left[1] +142, Lv.Grid.Top[1] +46, clNearWhite, "New"); + TextRender_string24(Lv.Grid.Left[1] +142, Lv.Grid.Top[1] +82, clNearWhite, "confirm"); + } + + //TRoundRect::sDrawBySize(Lv.Grid.Left[2] +10, Lv.Grid.Top[1] + 166, 100, 40, 7, clDeepBlue, "保存", 14, clNearWhite); + ShowSave_II(); + ShowSave_III(); + + Check4Selected(); + aPanel->ReDrawItems(); +} + +void TPasswdChange::ShowSave_II() +{ + char *tText; + if(LanguageEnCn==0)tText="保存"; else tText = "Save"; + if( (Tag.Group == 0) && (Tag.Inx0 == 3) ){ + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +242, Lv.Grid.Top[0] + 126, 76, 36, 7, clDeepBlue, tText, 14, clNearWhite); + }else{ + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +242, Lv.Grid.Top[0] + 126, 76, 36, 7, clNearWhite, tText, 14, clNearBlack); + } +} + +void TPasswdChange::ShowSave_III() +{ + char *tText; + if(LanguageEnCn==0)tText="保存"; else tText = "Save"; + if( (Tag.Group == 1) && (Tag.Inx1 == 3) ){ + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +242, Lv.Grid.Top[1] + 126, 76, 36, 7, clDeepBlue, tText, 14, clNearWhite); + }else{ + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +242, Lv.Grid.Top[1] + 126, 76, 36, 7, clNearWhite, tText, 14, clNearBlack); + } +} + +void TPasswdChange::Show(void) +{ + RenderBackGround(); + DrawSelf(); +} + +void TPasswdChange::ShowStaII() +{ + if(LanguageEnCn==0){ + if(StaII == 0){ + TMyString::sFromStr(" ", Str.Text); + }else + if(StaII == 1){ + TMyString::sFromStr("更改成功\0", Str.Text); + }else + if(StaII == -1){ + TMyString::sFromStr("密码至少6位\0", Str.Text); + }else + if(StaII == -2){ + TMyString::sFromStr("密码至多12位\0", Str.Text); + }else + if(StaII == -3){ + TMyString::sFromStr("密码不等\0", Str.Text); + }else + if(StaII == -4){ + TMyString::sFromStr("记忆出错\0", Str.Text); + }else + if(StaII == -5){ + TMyString::sFromStr("输入内容出错\0", Str.Text); + }else + if(StaII == -6){ + TMyString::sFromStr("原密码不符", Str.Text); + } + }else{ + if(StaII == 0){ + TMyString::sFromStr(" ", Str.Text); + }else + if(StaII == 1){ + TMyString::sFromStr("Changed OK ", Str.Text); + }else + if(StaII == -1){ + TMyString::sFromStr("Error less 6 ", Str.Text); + }else + if(StaII == -2){ + TMyString::sFromStr("Error More 12 ", Str.Text); + }else + if(StaII == -3){ + TMyString::sFromStr("Error confirm ", Str.Text); + }else + if(StaII == -4){ + TMyString::sFromStr("Error Memory ", Str.Text); + }else + if(StaII == -5){ + TMyString::sFromStr("Error Enter ", Str.Text); + }else + if(StaII == -6){ + TMyString::sFromStr("Error Original", Str.Text); + } + } + TextRender_string24(ResultTipPoint_II.x, ResultTipPoint_II.y, clNearWhite, ItemColor, Str.Text); +} + +void TPasswdChange::ShowStaII(int aSta) +{ + StaII = aSta; + ShowStaII(); +} + +void TPasswdChange::ShowStaIII() +{ + if(LanguageEnCn==0){ + if(StaIII == 0){ + TMyString::sFromStr(" ", Str.Text); + }else + if(StaIII == 1){ + TMyString::sFromStr("更改成功", Str.Text); + }else + if(StaIII == -1){ + TMyString::sFromStr("密码至少6位", Str.Text); + }else + if(StaIII == -2){ + TMyString::sFromStr("密码至多12位", Str.Text); + }else + if(StaIII == -3){ + TMyString::sFromStr("密码不等", Str.Text); + }else + if(StaIII == -4){ + TMyString::sFromStr("记忆出错", Str.Text); + }else + if(StaIII == -5){ + TMyString::sFromStr("输入内容出错", Str.Text); + }else + if(StaIII == -6){ + TMyString::sFromStr("原密码不符", Str.Text); + } + }else{ + if(StaIII == 0){ + TMyString::sFromStr(" ", Str.Text); + }else + if(StaIII == 1){ + TMyString::sFromStr("Changed OK ", Str.Text); + }else + if(StaIII == -1){ + TMyString::sFromStr("Error less 6 ", Str.Text); + }else + if(StaIII == -2){ + TMyString::sFromStr("Error More 12 ", Str.Text); + }else + if(StaIII == -3){ + TMyString::sFromStr("Error confirm ", Str.Text); + }else + if(StaIII == -4){ + TMyString::sFromStr("Error Memory ", Str.Text); + }else + if(StaIII == -5){ + TMyString::sFromStr("Error Enter ", Str.Text); + }else + if(StaIII == -6){ + TMyString::sFromStr("Error Original", Str.Text); + } + } + TextRender_string24(ResultTipPoint_III.x, ResultTipPoint_III.y, clNearWhite, ItemColor, Str.Text); +} + +void TPasswdChange::ShowStaIII(int aSta) +{ + StaIII = aSta; + ShowStaIII(); +} + +void TPasswdChange::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + RenderBackGround(); + DrawSelf(); + } +} + +//______________________________________________________________________________________________________________________________ + +void TPasswdChange::Check4Selected(void) +{ + for(int i=0; i<6; i++) + aPanel->Edit[i].Selected = 0; + + if(Tag.Group == 0){ + switch(Tag.Inx0){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Edit[2].Selected = 1; + break; + } + }else + if(Tag.Group == 1){ + switch(Tag.Inx1){ + case 0: + aPanel->Edit[3].Selected = 1; + break; + case 1: + aPanel->Edit[4].Selected = 1; + break; + case 2: + aPanel->Edit[5].Selected = 1; + break; + } + } +} + +int TPasswdChange::CheckPrvPasswdOk_II() +{ + unsigned int Len,i, Cok, Cing; + Len = aPanel->Edit[0].Str.GetLength(); + if(Len <6){ ShowStaII(-6); return -1;} + if(Len >12){ ShowStaII(-6); return -1;} + Cok = 0; + Cing = 1; + if(Len == CtlCenter.PassWordII.Len){ + for(i=0; iEdit[0].Str.Text[i] != CtlCenter.PassWordII.Content[i]){ + Cing = 0; + } + } + if(Cing){ + Cok = 1; + SystemPermission = 2; + } + } + + if(Cok)return 0; + ShowStaII(-6); return -1; +} + +int TPasswdChange::CheckPrvPasswdOk_III() +{ + unsigned int Len,i, Cok, Cing; + Len = aPanel->Edit[3].Str.GetLength(); + if(Len <6){ ShowStaIII(-6); return -1;} + if(Len >12){ ShowStaIII(-6); return -1;} + Cok = 0; + Cing = 1; + if(Len == CtlCenter.PassWordIII.Len){ + for(i=0; iEdit[3].Str.Text[i] != CtlCenter.PassWordIII.Content[i]){ + Cing = 0; + } + } + if(Cing){ + Cok = 1; + SystemPermission = 3; + SystemPermissionTick = 0; + } + } + if(Cok)return 0; + ShowStaIII(-6); return -1; +} + +void TPasswdChange::CheckPasswordII() +{ + int Len0, Len1, i, IsEq, Wok, Rok; + Len0 = aPanel->Edit[1].Str.GetLength(); + Len1 = aPanel->Edit[2].Str.GetLength(); + + Wok = 0; + Rok = 0; + if(Len0 == Len1){ + if(Len0 <6){ + ShowStaII(-1); + return; + }else + if(Len0 > 12){ + ShowStaII(-2); + return; + } + IsEq = 1; + for(i=0; iEdit[1].Str.Text[i] != aPanel->Edit[2].Str.Text[i]){ + IsEq = 0; + } + } + if(IsEq){ + for(i=0; i<16; i++)PassWord.Content[i] = '\0'; + for(i=0; iEdit[1].Str.Text[i] ; + } + Wok = CtlCenter.PassWordII_ReadWrite(0, &PassWord); + if(Wok == 1){ + Rok = CtlCenter.PassWordII_ReadWrite(1, nullptr); + if(Rok){ + ShowStaII(1); + Record.OperateAdd_PassWdModify(2); + }else{ + ShowStaII(-4); + Record.OperateAdd_PassWdModify(12); + } + }else + if(Wok == -1){ + ShowStaII(-4); + Record.OperateAdd_PassWdModify(12); + }else{ + ShowStaII(-5); + Record.OperateAdd_PassWdModify(12); + } + }else{ + ShowStaII(-3); + } + }else{ + ShowStaII(-3); + } +} + +void TPasswdChange::CheckPasswordIII() +{ + int Len0, Len1, i, IsEq, Wok, Rok; + Len0 = aPanel->Edit[4].Str.GetLength(); + Len1 = aPanel->Edit[5].Str.GetLength(); + + Wok = 0; + Rok = 0; + if(Len0 == Len1){ + if(Len0 <6){ + ShowStaIII(-1); + return; + }else + if(Len0 > 12){ + ShowStaIII(-2); + return; + } + IsEq = 1; + for(i=0; iEdit[4].Str.Text[i] != aPanel->Edit[5].Str.Text[i]){ + IsEq = 0; + } + } + if(IsEq){ + for(i=0; i<16; i++)PassWord.Content[i] = '\0'; + for(i=0; iEdit[4].Str.Text[i] ; + } + Wok = CtlCenter.PassWordIII_ReadWrite(0, &PassWord); + if(Wok == 1){ + Rok = CtlCenter.PassWordIII_ReadWrite(1, nullptr); + if(Rok == 1){ + ShowStaIII(1); + Record.OperateAdd_PassWdModify(3); + }else{ + ShowStaIII(-4); + Record.OperateAdd_PassWdModify(13); + } + }else + if(Wok == -1){ + ShowStaIII(-4); + Record.OperateAdd_PassWdModify(13); + }else{ + ShowStaIII(-5); + Record.OperateAdd_PassWdModify(13); + } + }else{ + ShowStaIII(-3); + } + }else{ + ShowStaIII(-3); + } +} + +void TPasswdChange::sRecoverSetDefault() +{ + TPassWord tPw; + int Wok, RetryTime, i; + for(i=0; i<16; i++)tPw.Content[i] = '\0'; + for(i=0; i<6; i++){ + tPw.Content[i] = '1' + i; + } + Wok = CtlCenter.PassWordII_ReadWrite(0, &tPw); + for(RetryTime =0; RetryTime <6; RetryTime++){ + if(Wok != 1){ + Wok = CtlCenter.PassWordII_ReadWrite(0, &tPw); + } + } + + for(i=0; i<16; i++)tPw.Content[i] = '\0'; + for(i=0; i<6; i++){ + tPw.Content[i] = '1' + i; + } + Wok = CtlCenter.PassWordIII_ReadWrite(0, &tPw); + for(RetryTime =0; RetryTime <6; RetryTime++){ + if(Wok != 1){ + Wok = CtlCenter.PassWordII_ReadWrite(0, &tPw); + } + } + + CtlCenter.PassWordII_ReadWrite(1,nullptr); + CtlCenter.PassWordIII_ReadWrite(1,nullptr); +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TPasswdChange::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) + ){ + for(int i=0; i<6; i++){ + if(aPanel->Edit[i].Selected){ + aPanel->Edit[i].KeyIn(aKey); + aPanel->Edit[i].ReDraw(); + } + } + } + + if(aKey == VK_UP){ + if(Tag.Group == 0){ + if(Tag.Inx0 >0){ + Tag.Inx0--; + Check4Selected(); + aPanel->ReDrawItems(); + ShowSave_II(); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 >0){ + Tag.Inx1--; + Check4Selected(); + aPanel->ReDrawItems(); + ShowSave_III(); + }else{ + Tag.Group = 0; + Tag.Inx0 = 3; + Tag.Inx1--; + Check4Selected(); + aPanel->ReDrawItems(); + ShowSave_II(); + } + } + }else + if(aKey == VK_DOWN){ + if(Tag.Group == 0){ + if(Tag.Inx0 <3){ + Tag.Inx0++; + Check4Selected(); + aPanel->ReDrawItems(); + ShowSave_II(); + }else{ + Tag.Group = 1; + Tag.Inx1 = 0; + Check4Selected(); + aPanel->ReDrawItems(); + ShowSave_II(); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 <3){ + Tag.Inx1++; + Check4Selected(); + aPanel->ReDrawItems(); + ShowSave_III(); + } + } + }else + if(aKey == VK_EXECUTE){ + //Save Data Here + if(Tag.Group == 0){ + if(Tag.Inx0 == 3){ + //if(SystemPermission > 1){ + // CheckPasswordII(); + //}else{ + if(CheckPrvPasswdOk_II() == 0)CheckPasswordII(); + //} + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 == 3){ + //if(SystemPermission >2){ + // CheckPasswordIII(); + //}else{ + if(CheckPrvPasswdOk_III() == 0)CheckPasswordIII(); + //} + } + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + if( (aKey != VK_EXECUTE) && (aKey != VK_EXECUTE) ){ + ShowStaII(0); + ShowStaIII(0); + } + + return aMsg; +} + + + + + + + + + + + + + + diff --git a/MyCode/Gui/PasswdChange.h b/MyCode/Gui/PasswdChange.h new file mode 100644 index 0000000..8f6aaaa --- /dev/null +++ b/MyCode/Gui/PasswdChange.h @@ -0,0 +1,119 @@ +#ifndef PASSWDCHANGE_H_ +#define PASSWDCHANGE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ControlCenter.h" + +class TPasswdChange{ + public: + static constexpr unsigned short hList[12] = {176,176,60,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint_II = { + .x = Lv.Grid.Left[0] + 340, + .y = Lv.Grid.Top[0] + 132, + }; + static constexpr TPoint ResultTipPoint_III = { + .x = Lv.Grid.Left[1] + 340, + .y = Lv.Grid.Top[1] + 132, + }; + public: + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Inx2; + void Reset(){ + Group =0; + Inx0 =0; + Inx1 =0; + Inx2 =0; + } + }Tag; + + class TCtlPanel1 *aPanel; + + TMyString Str; + + int StaII; + int StaIII; + + TPassWord PassWord; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TPasswdChange(){}; + void Init(); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void FullRedraw(int Prm); + void ReDraw(void); + void PanelCanvasOut(); + void DrawCaption2(void); + + int CheckPrvPasswdOk_II(); + int CheckPrvPasswdOk_III(); + + void ShowSave_II(); + void ShowSave_III(); + + void ShowStaII(); + void ShowStaII(int aSta); + void ShowStaIII(); + void ShowStaIII(int aSta); + + void CheckPasswordII(); + void CheckPasswordIII(); + static void sRecoverSetDefault(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/PermissionSet.cpp b/MyCode/Gui/PermissionSet.cpp new file mode 100644 index 0000000..bb98f37 --- /dev/null +++ b/MyCode/Gui/PermissionSet.cpp @@ -0,0 +1,349 @@ +#include "PermissionSet.h" +#include "XBox.h" +#include "Runtime.h" + + +void TPermissionSet::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + BoundCaption.SetBySize(Left,Top,Width, CH); + Content.Set(Left, Top+CH, Right, Bottom); + + BoxBound.Set(Left + 200, Top+70, Right -200, Bottom -70); + + + #undef CH +} + +void TPermissionSet::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clFrmFace); + + RectFillRender(BoundCaption.Left, BoundCaption.Top, BoundCaption.Right, BoundCaption.Bottom, clMaroon); + TextRender_string24(BoundCaption.Left+6, BoundCaption.Top +3, clNearWhite, clMaroon, "II III 级权限允许项设定 按确定键保存并退出"); +} + + +void TPermissionSet::Show(void) +{ + DrawSelf(); + DrawBox(); + ReDrawItems(); + DrawWidget(); +} + +void TPermissionSet::ReDrawItems() +{ + int x,y; + unsigned int aClr; + x = BoxBound.Left + 24 + 20; + y = BoxBound.Top + 36 ; + + TextRender_string24(x, y, clNearBlack, clFrmFace, "I 查询信息"); + y = y + 36; + TextRender_string24(x, y, clNearBlack, clFrmFace, "I 消除控制器的声信号"); + y = y + 36; + TextRender_string24(x, y, clNearBlack, clFrmFace, "I 检查"); + y = y + 36; + TextRender_string24(x, y, clNearBlack, clFrmFace, "I 信息确认"); + y = y + 36; + TextRender_string24(x, y, clNearBlack, clFrmFace, "I 联动启动"); + + if(SystemPermission < 3)aClr = clSilver; + else if(SystemPermission == 3)aClr = clNearBlack; + y = y + 36; + TextRender_string24(x, y, aClr, clFrmFace, "II 屏蔽和解除屏蔽"); + +} + +void TPermissionSet::DrawWidget() +{ + int x,y,R; + x = BoxBound.Left + 24; + y = BoxBound.Top + 36 +12; + R = 10; + + #define CLR_SEL clBlue + #define CLR_ACT clGreen + + if(FocusIndex == 0){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(eValue[0]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 1){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(eValue[1]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 2){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(eValue[2]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 3){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(eValue[3]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 4){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(eValue[4]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 5){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(eValue[5]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } +} + +void TPermissionSet::DrawBox(void) +{ + int aLen, aW; + aLen = 10; + aW = aLen * 12 +12; + + RectFillRender(BoxBound.Left, BoxBound.Top, BoxBound.Right, BoxBound.Bottom, clFrmFace); + + VertLineRender(BoxBound.Left, BoxBound.Top+12, BoxBound.Height-12, clGray); + VertLineRender(BoxBound.Left+1, BoxBound.Top+12, BoxBound.Height-12, clGray); + VertLineRender(BoxBound.Right, BoxBound.Top+12, BoxBound.Height-12, clGray); + VertLineRender(BoxBound.Right-1, BoxBound.Top+12, BoxBound.Height-12, clGray); + + HorizLineRender(BoxBound.Left, BoxBound.Top+12, 6, clGray); + HorizLineRender(BoxBound.Left, BoxBound.Top+12+1, 6, clGray); + HorizLineRender(BoxBound.Left, BoxBound.Bottom, BoxBound.Width, clGray); + HorizLineRender(BoxBound.Left, BoxBound.Bottom -1, BoxBound.Width, clGray); + + HorizLineRender(BoxBound.Left + aW +6, BoxBound.Top+12, BoxBound.Width -6 -aW, clGray); + HorizLineRender(BoxBound.Left + aW +6, BoxBound.Top+12+1, BoxBound.Width -6 -aW, clGray); + + TextRender_string24(BoxBound.Left + 8, BoxBound.Top, clNearBlack, clFrmFace, "允许项设定"); + + ReDrawItems(); +} + +void TPermissionSet::ChangeWg(void) +{ + switch(FocusIndex){ + case 0: if(eValue[0]){ + eValue[0] = 0; + }else{ + eValue[0] = 0xA5; + } + break; + case 1: if(eValue[1]){ + eValue[1] = 0; + }else{ + eValue[1] = 0xA5; + } + break; + case 2: if(eValue[2]){ + eValue[2] = 0; + }else{ + eValue[2] = 0xA5; + } + break; + case 3: if(eValue[3]){ + eValue[3] = 0; + }else{ + eValue[3] = 0xA5; + } + break; + case 4: if(eValue[4]){ + eValue[4] = 0; + }else{ + eValue[4] = 0xA5; + } + break; + case 5: if(eValue[5]){ + eValue[5]= 0; + }else{ + eValue[5] = 0xA5; + } + break; + } +} + +void TPermissionSet::LoadSysCfg() +{ + eValue[0] = PermissionDt.QueryInf; + eValue[1] = PermissionDt.ClearCtlVoice; + eValue[2] = PermissionDt.Check; + eValue[3] = PermissionDt.InfReadConfirm; + eValue[4] = PermissionDt.LinkageActive; + eValue[5] = PermissionDt.MaskAndUnMask; +} + +TGuiMsgReturn TPermissionSet::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aPa; + + if(aKey == VK_LEFT){ + ChangeWg(); + DrawWidget(); + }else + if(aKey == VK_RIGHT){ + ChangeWg(); + DrawWidget(); + }else + if(aKey == VK_UP){ + if(FocusIndex >0){ + FocusIndex--; + DrawWidget(); + } + }else + if(aKey == VK_DOWN){ + if(SystemPermission == 2){ + if(FocusIndex <4){ + FocusIndex++; + DrawWidget(); + } + }else + if(SystemPermission == 3){ + if(FocusIndex <5){ + FocusIndex++; + DrawWidget(); + } + } + }else + if(aKey == VK_EXECUTE){ + PermissionDt.QueryInf = eValue[0]; + PermissionDt.ClearCtlVoice = eValue[1]; + PermissionDt.Check = eValue[2]; + PermissionDt.InfReadConfirm = eValue[3]; + PermissionDt.LinkageActive = eValue[4]; + PermissionDt.MaskAndUnMask = eValue[5]; + + aPa = 0; + if(eValue[0])aPa |= 0x01; + if(eValue[1])aPa |= 0x02; + if(eValue[2])aPa |= 0x04; + if(eValue[3])aPa |= 0x08; + if(eValue[4])aPa |= 0x10; + if(eValue[5])aPa |= 0x20; + Record.OperateAdd_CfgPermissionAllow(aPa); + + aMsg = guiMsgReturn; + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + return aMsg; +} + + + + + + + + diff --git a/MyCode/Gui/PermissionSet.h b/MyCode/Gui/PermissionSet.h new file mode 100644 index 0000000..b03e882 --- /dev/null +++ b/MyCode/Gui/PermissionSet.h @@ -0,0 +1,75 @@ +#ifndef PERMISSIONSET_H_ +#define PERMISSIONSET_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" + +class TPermissionSet{ + public: + int FocusIndex; + + TRect Bound; + TRect BoundCaption; + TRect Content; + + TRect BoxBound; + + unsigned char eValue[8]; + + public: + TPermissionSet(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void ChangeWg(); + void DrawWidget(); + void ReDrawItems(); + void DrawSelf(); + void DrawBox(void); + void Show(); + + void LoadSysCfg(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/PmsIntervene.cpp b/MyCode/Gui/PmsIntervene.cpp new file mode 100644 index 0000000..1d5c2e1 --- /dev/null +++ b/MyCode/Gui/PmsIntervene.cpp @@ -0,0 +1,525 @@ +#include "PmsIntervene.h" +#include "Runtime.h" +#include "server.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + + +static const unsigned char SavePassWord[32] = "9910232250266023\0"; + + +void TPmsIntervene::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + unsigned short Left,Right,Top,Bottom,i; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + Color = aColor; + BevelOuter = aBevelOuter; + if(BevelOuter == bvRaised){ + Left = Bound.Left + 1; + Right = Bound.Right - 2; + Top = Bound.Top + 1; + Bottom = Bound.Bottom - 2; + }else{ + Left = Bound.Left + 2; + Right = Bound.Right - 2; + Top = Bound.Top + 2; + Bottom = Bound.Bottom - 2; + } + + Caption.Init(Left, Top, Right-Left+1, 32, 0, 0, clNearWhite, clMedBlue); + Content.Set(Left,Top+32,Right,Bottom); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Caption.Visible = 0; + + + Edit.Visible = 0; + Edit.SetMaxLen(16); + Edit.SetTextShowMaskByAsterisk(); + + STextDown.Visible = 1; + + CountDownTick =0; +} + +void TPmsIntervene::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick16)return; + Cok = 0; + Cing = 1; + if(Len == CtlCenter.PassWordII.Len){ + for(i=0; i16)return; + Cok = 0; + Cing = 1; + if(Len == CtlCenter.PassWordIII.Len){ + for(i=0; i1){ + HotKeyResetCallBack(); + IsShow = 0; + aMsg = guiMsgReturn; + }else{ + if(LanguageEnCn==0)STextDown.SetText("密码错误 !", 24); + else STextDown.SetText("Incorrect Password", 24); + STextDown.TextColor = clRed; + STextDown.Show(); + CountDownTick = 15; + } + }else + if(GoWhat == 2){ + CheckEnterLvl(); + if(SystemPermission >1){ + RedrawScreen(); + HotKeyAlramCallBack(); + IsShow = 0; + aMsg = guiMsgReturn; + }else{ + if(LanguageEnCn==0)STextDown.SetText("密码错误 !", 24); + else STextDown.SetText("Incorrect Password", 24); + STextDown.TextColor = clRed; + STextDown.Show(); + CountDownTick = 15; + } + }else + if(GoWhat == 3){ + CheckEnterLvl(); + if(SystemPermission >1){ + HotKeySelfCheckCallBack(); + IsShow = 0; + aMsg = guiMsgReturn; + }else{ + if(LanguageEnCn==0)STextDown.SetText("密码错误 !", 24); + else STextDown.SetText("Incorrect Password", 24); + STextDown.TextColor = clRed; + STextDown.Show(); + CountDownTick = 15; + } + }else + if(GoWhat == 4){ + if(ReqLevel == 2){ + CheckEnterLvl(); + if(SystemPermission >1){ + IsShow = 0; + aMsg = guiMsgOkAndReturn; + }else{ + if(LanguageEnCn==0)STextDown.SetText("密码错误 !", 24); + else STextDown.SetText("Incorrect Password", 24); + STextDown.TextColor = clRed; + STextDown.Show(); + CountDownTick = 15; + } + }else + if(ReqLevel == 3){ + CheckEnterLv2(); + if(SystemPermission >2){ + IsShow = 0; + aMsg = guiMsgOkAndReturn; + }else{ + if(LanguageEnCn==0)STextDown.SetText("密码错误 !", 24); + else STextDown.SetText("Incorrect Password", 24); + STextDown.TextColor = clRed; + STextDown.Show(); + CountDownTick = 15; + } + } + } + }else + if(aKey == VK_RETURN){ + IsShow = 0; + if(GoWhat < 4) + RedrawScreen(); + aMsg = guiMsgReturn; + } + if( (aMsg == guiMsgReturn) || (aMsg == guiMsgOkAndReturn) ){ + IsHotKeyCheckingPermission = 0; + } + return aMsg; +} + +void TPmsIntervene::BackScreen() +{ + volatile unsigned int aAddrs, aAddrt; + int x,y; + aAddrs = LcdBaseAddr; + aAddrt = dAddrSdRam_BackScreen; + for(y=100; y<260; y++){ + for(x=170; x<630; x++){ + PxData[x-170] = *(volatile unsigned int *)(aAddrs + ((y*800 + x) *4)); + } + for(x=170; x<630; x++){ + *(volatile unsigned int *)aAddrt = PxData[x-170]; + aAddrt+=4; + } + } +} + +void TPmsIntervene::RedrawScreen() +{ + volatile unsigned int aAddr; + int x,y; + + GuiRedraw(1); + return; + + aAddr = dAddrSdRam_BackScreen; + for(y=100; y<260; y++){ + for(x=170; x<630; x++){ + PxData[x-170] = *(volatile unsigned int *)aAddr; + aAddr+=4; + } + for(x=170; x<630; x++){ + *(volatile unsigned int *)(LcdBaseAddr + ((y*800 + x) *4)) = PxData[x-170]; + } + } +} + +void TPmsIntervene::DrawTip() +{ + unsigned int aClr; + if(CountDownTick & 0x01){ + aClr = clNearWhite; + }else{ + aClr = clNearBlack; + } + RectFillRender(Bound.Left-6, Bound.Top-8, Bound.Left-1, Bound.Bottom+6, aClr); + RectFillRender(Bound.Left-6, Bound.Top-8, Bound.Right+6, Bound.Top-1, aClr); + RectFillRender(Bound.Right+1, Bound.Top-8, Bound.Right+6, Bound.Bottom+6, aClr); + RectFillRender(Bound.Left-6, Bound.Bottom+1, Bound.Right+6, Bound.Bottom+6, aClr); + if(CountDownTick < 10) + TextDigitRender2_24(STextDown.Bound.Left+ 360, STextDown.Bound.Top+2, clNearBlack, clFrmFace, CountDownTick); + else + TextRender_string24(STextDown.Bound.Left+ 360, STextDown.Bound.Top+2, clNearBlack, clFrmFace, " "); +} + +void TPmsIntervene::Task1000Ms() +{ + if(IsShow == 0)return; + if(CountDownTick){ + CountDownTick--; + if(CountDownTick){ + DrawTip(); + }else{ + IsShow = 0; + GoWhat = 0; + RedrawScreen(); + } + } +} + +int TPmsIntervene::ExtRequst(unsigned char Prm) +{ + IsShow = 0; + IsHotKeyCheckingPermission =0; + return 0; +} + + + + + + + + + + + diff --git a/MyCode/Gui/PmsIntervene.h b/MyCode/Gui/PmsIntervene.h new file mode 100644 index 0000000..4e7fa73 --- /dev/null +++ b/MyCode/Gui/PmsIntervene.h @@ -0,0 +1,101 @@ +#ifndef PMSINTERVENE_H_ +#define PMSINTERVENE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TButton.h" +#include "TEdit.h" + +//aPanel with Caption, StaticText, Btn, Edit, +class TPmsIntervene{ + private: + int FontSize; + int FontHeight; + int EditMode; + TBvStyle BevelOuter; + struct{ + u16 Width; + unsigned int Color; + }Border; + public: + TStaticText Caption; + TStaticText STextDown; + TEdit Edit; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + int ReqLevel; + + TRect Bound; + TRect Content; + + int GoWhat; + int IsShow; + + unsigned int PxData[800]; + unsigned int CountDownTick; + + private: + + public: + TPmsIntervene(){}; + TPmsIntervene(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aColor, aBevelOuter); + } + void Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aColor, TBvStyle aBevelOuter); + void DrawSelf(void); + void DrawVertScrollBar(void); + + void Show4Reset(void); + void Show4Alram(); + void Show4SelfCheck(void); + void Show4Gui(int aX, int aY, int aW, int aH, int aReqLevel); + void ReDraw4GuiRecall(); + + + void ReDrawItems(void); + void ReDrawEdit(void); + + void Show(); + void DrawTip(); + void DelayMs(unsigned int aMs); + + void SetEditMode(unsigned int aMode); + + void Clear(void); + void FullRePaint(void); + void RePaint(void); + + void GuiLoginIIShow(); + void GuiLoginIIIShow(); + void CheckEnterLvl(); + void CheckEnterLv2(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void BackScreen(); + void RedrawScreen(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + + + +#endif + + diff --git a/MyCode/Gui/PowerSuplyCfg.cpp b/MyCode/Gui/PowerSuplyCfg.cpp new file mode 100644 index 0000000..e384e15 --- /dev/null +++ b/MyCode/Gui/PowerSuplyCfg.cpp @@ -0,0 +1,292 @@ +#include "PowerSuplyCfg.h" +#include "Runtime.h" + +void TPowerSuplyCfg::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("安装->电源数量配置", Caption.Text); + Caption.Visible = 1; + + CtlIndex = 0; + OnActive = 0; + + Sta = 0; +} + +void TPowerSuplyCfg::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TPowerSuplyCfg::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TPowerSuplyCfg::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + +void TPowerSuplyCfg::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + + TextRender_string24(66, 180, clNearBlack, "1.上下键切换编辑项目"); + TextRender_string24(66, 220, clNearBlack, "2.左右键编辑或更改设定"); +} + +void TPowerSuplyCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + Show(); + aPanel->Show(); + ShowSta(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + ShowSta(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +//______________________________________________________________________________________________________________________________ + +void TPowerSuplyCfg::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<4;i++)aPanel->Edit[i].Selected = 0; + for(i=0; i<1;i++)aPanel->Btn[i].Selected = 0; + if(1){ + switch(CtlIndex){ + case 0: + aPanel->Edit[1].Selected = 1; + break; + //case 1: + // aPanel->Edit[1].Selected = 1; + // break; + //case 2: + // aPanel->Edit[2].Selected = 1; + // break; + case 1: + aPanel->Btn[0].Selected = 1; + break; + default: + + break; + } + } +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TPowerSuplyCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn MBoxMsg = guiMsgNone; + int iVal; + + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex == 0){ + if(WroteSubCount == 0)WroteSubCount = 1; + else if(WroteSubCount == 1)WroteSubCount = 2; + else WroteSubCount = 0; + aPanel->Edit[1].Str.FromUInt2Dg(WroteSubCount); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[1].Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <1){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + break; + case VK_EXECUTE: + //Save Data Here + if(CtlIndex == 1){ + Record.WritePowerSuplyCount(WroteMianCount, WroteSubCount); + Record.ReadPowerSuplyCount(); + //if( (WroteMianCount == PowerPrmValue.MainCount) && (WroteSubCount == PowerPrmValue.SubCount) ){ + // ShowSta(1); + // KeyPad.IsSendPowerSuplyCount = 1; + //}else{ + // ShowSta(0); + //} + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default: + break; + } + + if(VK_EXECUTE != aKey){ + ShowSta(0); + } + + return aMsg; +} + +void TPowerSuplyCfg::ShowSta() +{ + if(Sta == 0){ + TextRender_string24(66, 96, clNearBlack, Color, " "); + }else + if(Sta == 1){ + TextRender_string24(66, 96, clNearBlack, Color, "保存成功 "); + } +} + +void TPowerSuplyCfg::ShowSta(int aSta) +{ + Sta = aSta; + ShowSta(); + +} + +void TPowerSuplyCfg::InitPanel(void) +{ + int x,y,x2,y2,i; + + y = y+10; + + aPanel->Init(350,100,424,220,0,0,clFrmFace, bvRaised); + aPanel->Caption.Init(351,101, 424-3 ,32,0,0,clFrmFace,clFrmFace); + + x = aPanel->Bound.Left; + y = aPanel->Bound.Top; + + aPanel->SText[0].Init(10,7,102,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(10,39,102,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[2].Init(10,71,102,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[3].Init(10,103,102,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("主电数量", aPanel->SText[0].Text); + TMyString::sFromStr("副电源数量", aPanel->SText[1].Text); + TMyString::sFromStr("--", aPanel->SText[2].Text); + TMyString::sFromStr("--", aPanel->SText[3].Text); + + aPanel->Edit[0].Init(260,7,148,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(260,39,148,30,x,y,clNearBlack,clNearWhite); + //aPanel->Edit[2].Init(260,71,148,30,x,y,clNearBlack,clNearWhite); + //aPanel->Edit[3].Init(260,103,148,30,x,y,clNearBlack,clNearWhite); + + aPanel->Edit[0].IsShowCursor = 0; + aPanel->Edit[0].Enable = 0; + aPanel->Edit[0].Visible = 1; + aPanel->Edit[1].IsShowCursor = 0; + aPanel->Edit[1].Enable = 0; + aPanel->Edit[1].Visible = 1; + for(i=1; i<2;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(3); + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("20"); + aPanel->Edit[i].SetPstTail(); + } + + aPanel->Btn[0].Init(260,150,148,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr(" 保存设置"); + + for(i=0; i<1;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + LoadData(); + Check4Selected(); + aPanel->ReDrawItems(); +} + +void TPowerSuplyCfg::LoadData() +{ + WroteMianCount = PowerPrmValue.MainCount; + //WroteSubCount = PowerPrmValue.SubCount; + + aPanel->Edit[0].Str.FromUInt2Dg(WroteMianCount); + aPanel->Edit[1].Str.FromUInt2Dg(WroteSubCount); + + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[1].SetPstTail(); +} + + + + + diff --git a/MyCode/Gui/PowerSuplyCfg.h b/MyCode/Gui/PowerSuplyCfg.h new file mode 100644 index 0000000..1f832a3 --- /dev/null +++ b/MyCode/Gui/PowerSuplyCfg.h @@ -0,0 +1,76 @@ +#ifndef POWERSUPLYCFG_H_ +#define POWERSUPLYCFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TPowerSuplyCfg{ + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + + u32 Color; + + int TabOrder; + + TRect Bound; + TRect Content; + + unsigned int CtlIndex; + + struct{ + unsigned char SaveOn; + unsigned char SaveTime; + unsigned char IsKeyLock; + unsigned char Dump; + }aData; + + int Sta; + + unsigned char WroteMianCount; + unsigned char WroteSubCount; + public: + TPowerSuplyCfg(){}; + TPowerSuplyCfg(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void ShowSaveOnOff(); + void ShowKeyLockOnOff(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + void Check4Selected(void); + + void LoadData(); + void SaveData(); + void ShowSta(); + void ShowSta(int aSta); + + int ExtRequst(unsigned char Prm){return 0;} + +}; + + + +#endif + diff --git a/MyCode/Gui/PowerSuplyInf.cpp b/MyCode/Gui/PowerSuplyInf.cpp new file mode 100644 index 0000000..7c6e61c --- /dev/null +++ b/MyCode/Gui/PowerSuplyInf.cpp @@ -0,0 +1,416 @@ +#include "PowerSuplyInf.h" +#include "runtime.h" + +//#define clOdd clMoneyGreen +//#define clEven clWhiteBlue + +extern "C"{ + #include "uart_key_drv.h" +} + +static const short svGridX [9] = {5, 96, 202, 318, 396, 476, 560, 638, 720}; + + +void TPowerSuplyInf::Init() +{ + #define CH 30 //Caption Height + PermissionCmd =0; + IsPermission =0; + IsAskingPowerCount =0; + Result4Asking = 0; +} + +void TPowerSuplyInf::RenderContent(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TPowerSuplyInf::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn==0)TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "本机->电源信息"); + else TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Local->Power Supply Info"); + + for(int i=0; i 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Top[5] + 40, 600 , 120, 3); + } + }else + if(aKey == VK_EXECUTE){ + Hide(); + aMsg = guiMsgReturn; + }else + if(aKey == dfKEY_QUERY){ + if(IsShowing) + Show(); + }else + if(aKey == VK_RETURN){ + Hide(); + aMsg = guiMsgReturn; + } + } + return aMsg; +} + +void TPowerSuplyInf::DrawData() +{ + int x,y; + int Inx; + Inx = 1; + + for(int i=1; i0){ + y = Lv.Grid.Top[Inx] +3; + + x = svGridX[0]; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "主电源"); + else TextRender_string24(x, y, clNearWhite, "PS-main"); + + x = svGridX[1] +24; + if(PowerSuplyState || PowerSuplyComm || PowerSuplyOutput){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "故障"); //主电 + else TextRender_string24(x, y, clNearWhite, "Fault"); + }else{ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "正常"); + else TextRender_string24(x, y, clNearWhite, "Work"); + } + + x = svGridX[2] +24; + if(PowerBkState || BatState || Bat1UnderVoltage || Bat2UnderVoltage){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "故障"); //备电 + else TextRender_string24(x, y, clNearWhite, "Fault"); //备电 + }else{ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "正常"); + else TextRender_string24(x, y, clNearWhite, "Work"); + } + + x = svGridX[3]; + TextDigitRender2Right24(x, y, clNearWhite, PsBatData.Body.PsVoltageCh1.D16 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, PsBatData.Body.PsVoltageCh1.D16 / 100 % 10); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[4]; + TextDigitRender2Right24(x, y, clNearWhite, PsBatData.Body.PsVoltageCh2.D16 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, PsBatData.Body.PsVoltageCh2.D16 / 100 % 10); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[5]; + TextRender_string24(x+18, y, clNearWhite, "--"); + + x = svGridX[6]; + TextDigitRender2Right24(x, y, clNearWhite, PsBatData.Body.BatVoltage1.D16 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, PsBatData.Body.BatVoltage1.D16 / 100 % 10); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[7]; + TextDigitRender2Right24(x, y, clNearWhite, PsBatData.Body.BatVoltage2.D16 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, PsBatData.Body.BatVoltage2.D16 / 100 % 10); + TextRender_string24(x+48, y, clNearWhite, "V"); + + unsigned int tEng = (PsBatData.Body.BatEnerger1);/// + PsBatData.Body.BatEnerger2); + x = svGridX[8]; + TextDigitRender3Right24(x, y, clNearWhite, tEng % 1000); + TextRender_string24(x+36, y, clNearWhite, "%"); + + Inx++; + } + + if(PowerPrmValue.SubExist[0]){ + y = Lv.Grid.Top[Inx] +3; + + x = svGridX[0]; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "副电源1"); + else TextRender_string24(x, y, clNearWhite, "PS-Aux1"); + + x = svGridX[1] +24; + if(PowerPrmValue.Sub1.Body.PowerLineFault || PowerPrmValue.Sub1.Body.OfflineFault || PowerPrmValue.Sub1.Body.OutputFault){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "故障"); //主电 + else TextRender_string24(x, y, clNearWhite, "Fault"); //主电 + }else{ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "正常"); + else TextRender_string24(x, y, clNearWhite, "Work"); + } + + x = svGridX[2] +24; + if(PowerPrmValue.Sub1.Body.BatFault || PowerPrmValue.Sub1.Body.Bat1VoltageLow || PowerPrmValue.Sub1.Body.Bat2VoltageLow){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "故障"); //备电 + else TextRender_string24(x, y, clNearWhite, "Fault"); //备电 + }else{ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "正常"); + else TextRender_string24(x, y, clNearWhite, "Work"); + } + + x = svGridX[3]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub1.Body.vChannel1 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub1.Body.vChannel1 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[4]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub1.Body.vChannel2 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub1.Body.vChannel2 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[5]; + TextRender_string24(x+18, y, clNearWhite, "--"); + + x = svGridX[6]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub1.Body.vBat1 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub1.Body.vBat1 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[7]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub1.Body.vBat2 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub1.Body.vBat2 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + unsigned int tEng = (PowerPrmValue.Sub1.Body.PercentBat1 + PowerPrmValue.Sub1.Body.PercentBat2) / 2; + x = svGridX[8]; + TextDigitRender3Right24(x, y, clNearWhite, tEng % 1000); + TextRender_string24(x+36, y, clNearWhite, "%"); + + Inx++; + } + if(PowerPrmValue.SubExist[1]){ + y = Lv.Grid.Top[Inx] +3; + + x = svGridX[0]; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "副电源2"); + else TextRender_string24(x, y, clNearWhite, "PS-Aux2"); + + x = svGridX[1] +24; + if(PowerPrmValue.Sub2.Body.PowerLineFault || PowerPrmValue.Sub2.Body.OfflineFault || PowerPrmValue.Sub2.Body.OutputFault){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "故障"); //主电 + else TextRender_string24(x, y, clNearWhite, "Fault"); + }else{ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "正常"); + else TextRender_string24(x, y, clNearWhite, "Work"); + } + + x = svGridX[2] +24; + if(PowerPrmValue.Sub2.Body.BatFault || PowerPrmValue.Sub2.Body.Bat1VoltageLow || PowerPrmValue.Sub2.Body.Bat2VoltageLow){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "故障"); //备电 + else TextRender_string24(x, y, clNearWhite, "Fault"); + }else{ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "正常"); + else TextRender_string24(x, y, clNearWhite, "Work"); + } + + x = svGridX[3]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub2.Body.vChannel1 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub2.Body.vChannel1 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[4]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub2.Body.vChannel2 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub2.Body.vChannel2 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[5]; + TextRender_string24(x+18, y, clNearWhite, "--"); + + x = svGridX[6]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub2.Body.vBat1 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub2.Body.vBat1 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + x = svGridX[7]; + TextDigitRender2Right24(x, y, clNearWhite, PowerPrmValue.Sub2.Body.vBat2 / 1000 % 100); + TextRender_string24(x+24, y, clNearWhite, "."); + TextDigitRender1Right24(x+36, y, clNearWhite, (PowerPrmValue.Sub2.Body.vBat2 % 1000)/100); + TextRender_string24(x+48, y, clNearWhite, "V"); + + unsigned int tEng = (PowerPrmValue.Sub2.Body.PercentBat1 + PowerPrmValue.Sub2.Body.PercentBat2) / 2; + x = svGridX[8]; + TextDigitRender3Right24(x, y, clNearWhite, tEng % 1000); + TextRender_string24(x+36, y, clNearWhite, "%"); + + Inx++; + } + + y = Lv.Grid.Top[10] +3; + x = svGridX[0]; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "设置键更新副电源数量"); + else TextRender_string24(x, y, clNearWhite, "Key Set To Updata Aux Power Supply"); +} + +void TPowerSuplyInf::DrawGetSta() +{ + int x,y; + x = 10; y= Lv.Grid.Top[4]+6; + if(LanguageEnCn==0){ + if(Result4Asking == 0){ + TextRender_string24(x, y, clNearWhite, ContentColor, " "); + }else + if(Result4Asking == 1){ + TextRender_string24(x, y, clNearWhite, ContentColor, "正在读取副电源数量 "); + }else + if(Result4Asking == 2){ + TextRender_string24(x, y, clNearWhite, ContentColor, "读取副电源数量成功 "); + }else{ + TextRender_string24(x, y, clNearWhite, ContentColor, "写入电源配置失败 "); + } + }else{ + if(Result4Asking == 0){ + TextRender_string24(x, y, clNearWhite, ContentColor, " "); + }else + if(Result4Asking == 1){ + TextRender_string24(x, y, clNearWhite, ContentColor, "Reading Sub Power Suppy "); + }else + if(Result4Asking == 2){ + TextRender_string24(x, y, clNearWhite, ContentColor, "Read Sub Power Suppy OK "); + }else{ + TextRender_string24(x, y, clNearWhite, ContentColor, "Wrote Config Error "); + } + } +} + +void TPowerSuplyInf::DrawGetSta(unsigned char aSta) +{ + Result4Asking = aSta; + DrawGetSta(); +} + +void TPowerSuplyInf::AskPowerCount() +{ + sys_get_power_Count(); +} + +void TPowerSuplyInf::SavePwrCount(unsigned char aExistMain, unsigned char aExistSub1, unsigned char aEsixtSub2) +{ + if(IsAskingPowerCount){ + IsAskingPowerCount =0; + Record.WritePowerSuplyCount(aExistSub1, aEsixtSub2); + Record.ReadPowerSuplyCount(); + if(IsShowing){ + if( (IsPermission == 0) && (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ){ + DrawData(); + if( (PowerPrmValue.SubExist[0] == aExistSub1) && (PowerPrmValue.SubExist[1] == aEsixtSub2) )DrawGetSta(2); + else DrawGetSta(3); + }else{ + if( (PowerPrmValue.SubExist[0] == aExistSub1) && (PowerPrmValue.SubExist[1] == aEsixtSub2) )Result4Asking = 2; + else Result4Asking = 3; + } + } + } +} + +int TPowerSuplyInf::ExtRequst(unsigned char Prm) +{ + IsAskingPowerCount =0; + if(IsShowing){ + IsShowing =0; + } + return 0; +} + diff --git a/MyCode/Gui/PowerSuplyInf.h b/MyCode/Gui/PowerSuplyInf.h new file mode 100644 index 0000000..4a1a3b4 --- /dev/null +++ b/MyCode/Gui/PowerSuplyInf.h @@ -0,0 +1,115 @@ +#ifndef POWERSUPLYINF_H_ +#define POWERSUPLYINF_H_ + +#include "gvalue.h" +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "StaticText.h" + + +//For Idle View or Edit +class TPowerSuplyInf{ + public: + static constexpr unsigned short hList[12] = {32,32,32,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 4, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + public: + //TMyString Str[10]; + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + int IsShowing; + unsigned char PermissionCmd; + unsigned char IsPermission; + unsigned char IsAskingPowerCount; + unsigned char Result4Asking; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + + char Text[64]; + public: + TPowerSuplyInf(){IsShowing = 0;} + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void Show(void); + void PermissionCmdReturnDraw(); + void ShowInf(); + void RenderContent(void); + + void DrawData(); + void DrawGetSta(); + void DrawGetSta(unsigned char aSta); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void Hide(); + + void FullRedraw(int Prm); + void AskPowerCount(); + void PermissionCmdGO(); + void SavePwrCount(unsigned char aExistMain, unsigned char aExistSub1, unsigned char aEsixtSub2); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + + + + + diff --git a/MyCode/Gui/PrintInf.cpp b/MyCode/Gui/PrintInf.cpp new file mode 100644 index 0000000..b69114d --- /dev/null +++ b/MyCode/Gui/PrintInf.cpp @@ -0,0 +1,1061 @@ +#include "PrintInf.h" +#include "XBox.h" +#include "Runtime.h" + +void TPrintInf::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + BoundCaption.SetBySize(Left,Top,Width, CH); + Content.Set(Left, Top+CH, Right, Bottom); + + BoxBound.Set(Left + 100, Top+70, Right -400, Bottom -70); + BoxBoundTime.Set(Left + 400, Top+70, Right -60, Bottom -70); + + WhatSel = 0; + SelectedFromOrEnd = 0; + SelectedIndex =0; + IsEditing = 0; + + InfList[0] = 0xA5; + InfList[1] = 0xA5; + InfList[2] = 0xA5; + InfList[3] = 0xA5; + InfList[4] = 0xA5; + + vtValueFrom[0] = 0; + vtValueFrom[1] = 0; + vtValueFrom[2] = 0; + vtValueFrom[3] = 0; + vtValueFrom[4] = 0; + vtValueFrom[5] = 0; + vtValueTo[0] = 0; + vtValueTo[1] = 0; + vtValueTo[2] = 0; + vtValueTo[3] = 0; + vtValueTo[4] = 0; + vtValueTo[5] = 0; + + IsPermission =0; + + #undef CH +} + +void TPrintInf::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clFrmFace); + + RectFillRender(BoundCaption.Left, BoundCaption.Top, BoundCaption.Right, BoundCaption.Bottom, clMaroon); + if(LanguageEnCn==0)TextRender_string24(BoundCaption.Left+6, BoundCaption.Top +3, clNearWhite, clMaroon, "历史信息->打印 按TAB键切换选定框"); + else TextRender_string24(BoundCaption.Left+6, BoundCaption.Top +3, clNearWhite, clMaroon, "Recorded Information->Print"); +} + + +void TPrintInf::Show(void) +{ + DrawSelf(); + DrawBoxItems(); + ReDrawItems(); + DrawWidget(); + + DrawBoxTime(); + DrawBoxTimeString(); + DrawSaveButton(); +} + +void TPrintInf::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + DrawBoxItems(); + ReDrawItems(); + DrawWidget(); + + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + DrawBoxTimeOutLine(); + DrawTimeEntryNoUpdate(); + DrawBoxTimeString(); + DrawSaveButton(); + if(WhatSel == 1){ + SetEditStart(); + } + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], clFrmFace); + DrawBoxItems(); + ReDrawItems(); + DrawWidget(); + + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + DrawBoxTimeOutLine(); + DrawTimeEntryNoUpdate(); + DrawBoxTimeString(); + DrawSaveButton(); + if(WhatSel == 1){ + SetEditStart(); + } + if(WhatSel == 3)ShowDetial(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + + } +} + +void TPrintInf::PermissionCmdReturnDraw() +{ + RectFillRender(200-10, 86-10, 600+20, 220, clFrmFace); + DrawBoxItems(); + ReDrawItems(); + DrawWidget(); + + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + DrawBoxTimeOutLine(); + DrawTimeEntryNoUpdate(); + DrawBoxTimeString(); + DrawSaveButton(); + if(WhatSel == 1){ + SetEditStart(); + } + ShowDetial(); +} + +void TPrintInf::GetStartStopTime() +{ + int i; + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextFrom[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextFrom[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StartTime = alt.D64; + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextTo[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextTo[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StopTime = alt.D64; +} + +void TPrintInf::PermissionCmdGO() +{ + GoPrint(); +} + +void TPrintInf::ShowDetial() +{ + int x,y,x2,y2,aW,aH; + unsigned int tClr; + char *tText; + x = Bound.Left + 196; + y = Bound.Top + 60 ; + aW = 400; + aH = 260; + x2 = x + aW -1; + y2 = y + aH -1; + + RectFillRender(x, y, x2, y2, clFrmFace); + + VertLineRender(x, y, aH -1, 0xFFFFFFFF); + VertLineRender(x2 -1, y +1, aH -2, 0xFF808080); + VertLineRender(x2, y, aH, 0xFF404040); + + HorizLineRender(x, y, aW - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, aW - 2, 0xFF808080); + HorizLineRender(x, y2, aW, 0xFF404040); + + if(LanguageEnCn==0)tText="按确定键打印, 按返回键返回"; + else tText= "Press 'OK' Key To Print, Or Return"; + TStaticText::sShow(x+2, y+2, x2-2, y+32, clNearWhite, clBlue, tText); + + x = x +60; + y = y + 50; + tClr = InfList[0] ? clNearBlack : clSilver; + if(LanguageEnCn==0)tText="火警信息"; else tText="Fire Alram"; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + TextDigitRender6Right24(x +180, y, tClr, this->CountFire); + y = y + 32; + tClr = InfList[1] ? clNearBlack : clSilver; + if(LanguageEnCn==0)tText="联动信息"; else tText="Linkage "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + TextDigitRender6Right24(x +180, y, tClr, this->CountLinkage); + y = y + 32; + tClr = InfList[2] ? clNearBlack : clSilver; + if(LanguageEnCn==0)tText="监管信息"; else tText="Supv "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + TextDigitRender6Right24(x +180, y, tClr, this->CountSv); + y = y + 32; + tClr = InfList[3] ? clNearBlack : clSilver; + if(LanguageEnCn==0)tText="故障信息"; else tText="Fault "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + TextDigitRender6Right24(x +180, y, tClr, this->CountFault); + y = y + 32; + tClr = InfList[4] ? clNearBlack : clSilver; + if(LanguageEnCn==0)tText="操作信息"; else tText="Operating "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + TextDigitRender6Right24(x +180, y, tClr, this->CountOperate); + y = y + 32; + TextRender_string24(x, y, clNearBlack, clFrmFace, "Total Records"); + TextDigitRender6Right24(x +180, y, clNearBlack, this->Count2Print); +} + +void TPrintInf::ReDrawItems() +{ + int x,y; + unsigned int aClr; + char *tText; + x = BoxBound.Left + 24 + 20; + y = BoxBound.Top + 36 ; + + if(LanguageEnCn==0)tText="火警信息"; else tText="Fire Alram"; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + y = y + 36; + if(LanguageEnCn==0)tText="联动信息"; else tText="Linkage "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + y = y + 36; + if(LanguageEnCn==0)tText="监管信息"; else tText="Supv "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + y = y + 36; + if(LanguageEnCn==0)tText="故障信息"; else tText="Fault "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); + y = y + 36; + if(LanguageEnCn==0)tText="操作信息"; else tText="Operating "; + TextRender_string24(x, y, clNearBlack, clFrmFace, tText); +} + +void TPrintInf::DrawWidget() +{ + int x,y,R; + x = BoxBound.Left + 24; + y = BoxBound.Top + 36 +12; + R = 10; + + #define CLR_SEL clBlue + #define CLR_ACT clGreen + + if(FocusIndex == 0){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(InfList[0]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 1){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(InfList[1]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 2){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(InfList[2]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 3){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(InfList[3]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } + + y = y+36; + if(FocusIndex == 4){ + TCircle::sRender(x, y, R+2, CLR_SEL, 0); + TCircle::sRender(x, y, R+3, CLR_SEL, 0); + TCircle::sRender(x, y, R+4, CLR_SEL, 0); + }else{ + TCircle::sRender(x, y, R+2, clFrmFace, 0); + TCircle::sRender(x, y, R+3, clFrmFace, 0); + TCircle::sRender(x, y, R+4, clFrmFace, 0); + } + TCircle::sRender(x, y, R, clGray, 0); + if(InfList[4]){ + TCircle::sRender(x, y, R-1, CLR_ACT, 1); + }else{ + TCircle::sRender(x, y, R-1, clFrmFace, 1); + } +} + +void TPrintInf::DrawBoxItemsOutLine(void) +{ + int aLen, aW; + unsigned int aClr, aTClr; + aLen = 4; + aW = aLen * 12 +12; + + if(WhatSel == 0){ + aClr = clBlue; + aTClr = clBlue; + }else{ + aClr = clGray; + aTClr = clNearBlack; + } + + VertLineRender(BoxBound.Left, BoxBound.Top+12, BoxBound.Height-12, aClr); + VertLineRender(BoxBound.Left+1, BoxBound.Top+12, BoxBound.Height-12, aClr); + VertLineRender(BoxBound.Right, BoxBound.Top+12, BoxBound.Height-12, aClr); + VertLineRender(BoxBound.Right-1, BoxBound.Top+12, BoxBound.Height-12, aClr); + + HorizLineRender(BoxBound.Left, BoxBound.Top+12, 6, aClr); + HorizLineRender(BoxBound.Left, BoxBound.Top+12+1, 6, aClr); + HorizLineRender(BoxBound.Left, BoxBound.Bottom, BoxBound.Width, aClr); + HorizLineRender(BoxBound.Left, BoxBound.Bottom -1, BoxBound.Width, aClr); + + HorizLineRender(BoxBound.Left + aW +6, BoxBound.Top+12, BoxBound.Width -6 -aW, aClr); + HorizLineRender(BoxBound.Left + aW +6, BoxBound.Top+12+1, BoxBound.Width -6 -aW, aClr); + + char *tText; + if(LanguageEnCn==0)tText="选定内容"; else tText="Selecte "; + TextRender_string24(BoxBound.Left + 8, BoxBound.Top, aTClr, clFrmFace, tText); +} + +void TPrintInf::DrawBoxItems(void) +{ + RectFillRender(BoxBound.Left, BoxBound.Top, BoxBound.Right, BoxBound.Bottom, clFrmFace); + DrawBoxItemsOutLine(); + ReDrawItems(); +} + +void TPrintInf::DrawBoxTimeOutLine() +{ + int aLen, aW; + unsigned int aClr,aTClr; + aLen = 4; + aW = aLen * 12 +12; + + if(WhatSel == 1){ + aClr = clBlue; + aTClr = clBlue; + }else{ + aClr = clGray; + aTClr = clNearBlack; + } + + VertLineRender(BoxBoundTime.Left, BoxBoundTime.Top+12, BoxBoundTime.Height-12, aClr); + VertLineRender(BoxBoundTime.Left+1, BoxBoundTime.Top+12, BoxBoundTime.Height-12, aClr); + VertLineRender(BoxBoundTime.Right, BoxBoundTime.Top+12, BoxBoundTime.Height-12, aClr); + VertLineRender(BoxBoundTime.Right-1,BoxBoundTime.Top+12, BoxBoundTime.Height-12, aClr); + + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top+12, 6, aClr); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top+12+1, 6, aClr); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom, BoxBoundTime.Width, aClr); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom -1, BoxBoundTime.Width, aClr); + + HorizLineRender(BoxBoundTime.Left + aW +6, BoxBoundTime.Top+12, BoxBoundTime.Width -6 -aW, aClr); + HorizLineRender(BoxBoundTime.Left + aW +6, BoxBoundTime.Top+12+1, BoxBoundTime.Width -6 -aW, aClr); + + if(LanguageEnCn==0)TextRender_string24(BoxBoundTime.Left + 8, BoxBoundTime.Top, aTClr, clFrmFace, "日期时间"); + else TextRender_string24(BoxBoundTime.Left + 8, BoxBoundTime.Top, aTClr, clFrmFace, "DateTime"); +} + +void TPrintInf::DrawTimeEntry(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + w = 36; + h = 32; + + vtValueFrom[0] = DateTime.Date.Split.Year; + vtValueFrom[1] = DateTime.Date.Split.Month; + vtValueFrom[2] = DateTime.Date.Split.Day; + + vtValueFrom[3] = DateTime.Time.Split.Hour; + vtValueFrom[4] = DateTime.Time.Split.Minute; + vtValueFrom[5] = DateTime.Time.Split.Second; + + vtValueTo[0] =vtValueFrom[0]; + vtValueTo[1] =vtValueFrom[1]; + vtValueTo[2] =vtValueFrom[2]; + vtValueTo[3] =vtValueFrom[3]; + vtValueTo[4] =vtValueFrom[4]; + vtValueTo[5] =vtValueFrom[5]; + + + for(i=0; i<6; i++){ + x = 438 + (i * 48); + y = 210 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = 438 + (i * 48); + y = 210 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[i]); + } +} + +void TPrintInf::DrawTimeEntryNoUpdate(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + w = 36; + h = 32; + + for(i=0; i<6; i++){ + x = 438 + (i * 48); + y = 210 + (0 * 112); + + //aHex0 = vtValueFrom[i] / 16 % 10; + //aHex1 = vtValueFrom[i] % 16; + //vtTextFrom[i][0] = aHex0 + '0'; + //vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = 438 + (i * 48); + y = 210 + (1 * 112); + + //aHex0 = vtValueTo[i] / 16 % 10; + //aHex1 = vtValueTo[i] % 16; + //vtTextTo[i][0] = aHex0 + '0'; + //vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[i]); + } +} + +void TPrintInf::DrawBoxTime(void) +{ + unsigned int i; + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + DrawBoxTimeOutLine(); + + DrawTimeEntry(); + +} + +void TPrintInf::DrawBoxTimeString(void) +{ + if(LanguageEnCn==0){ + TextRender_string24(BoxBoundTime.Left + 12, BoxBoundTime.Top + 34, clNearBlack, "开始时间"); + TextRender_string24(BoxBoundTime.Left + 42, BoxBoundTime.Top + 68, clNearBlack, "年 月 日 时 分 秒"); + TextRender_string24(BoxBoundTime.Left + 12, BoxBoundTime.Top + 147, clNearBlack, "结束时间"); + TextRender_string24(BoxBoundTime.Left + 42, BoxBoundTime.Top + 179, clNearBlack, "年 月 日 时 分 秒"); + }else{ + TextRender_string24(BoxBoundTime.Left + 12, BoxBoundTime.Top + 34, clNearBlack, "Begin"); + TextRender_string24(BoxBoundTime.Left + 42, BoxBoundTime.Top + 68, clNearBlack, " Y M D H M S"); + TextRender_string24(BoxBoundTime.Left + 12, BoxBoundTime.Top + 147, clNearBlack, "End"); + TextRender_string24(BoxBoundTime.Left + 42, BoxBoundTime.Top + 179, clNearBlack, " Y M D H M S"); + } +} + +void TPrintInf::DrawSaveButton(void) +{ + unsigned int aClr, aTClr; + int x,y,x2,y2; + + x = 590; + y = 372; + x2 = 736; + y2 = 416; + + if(WhatSel == 2){ + aClr = clBlue; + aTClr = clNearWhite; + }else{ + aClr = clFrmFace; + aTClr = clNearBlack; + } + + RectFillRender(x, y, x2, y2, aClr); + VertLineRender(x, y, y2-y+1-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y +1, y2-y+1-2, 0xFF808080); + VertLineRender(x2, y, y2-y+1-2, 0xFF404040); + HorizLineRender(x, y, x2-x+1-1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, x2-x+1 - 2, 0xFF808080); + HorizLineRender(x, y2, x2-x+1, 0xFF404040); + + if(LanguageEnCn==0)TextRender_string24(x + 28, y + 9, aTClr, "执行打印"); + else TextRender_string24(x + 28, y + 9, aTClr, " Print "); +} + +void TPrintInf::ChangeWg(void) +{ + switch(FocusIndex){ + case 0: if(InfList[0]){ + InfList[0] = 0; + }else{ + InfList[0] = 0xA5; + } + break; + case 1: if(InfList[1]){ + InfList[1] = 0; + }else{ + InfList[1] = 0xA5; + } + break; + case 2: if(InfList[2]){ + InfList[2] = 0; + }else{ + InfList[2] = 0xA5; + } + break; + case 3: if(InfList[3]){ + InfList[3] = 0; + }else{ + InfList[3] = 0xA5; + } + break; + case 4: if(InfList[4]){ + InfList[4] = 0; + }else{ + InfList[4] = 0xA5; + } + break; + } +} + +void TPrintInf::SetEditStart(void) +{ + int x,y,w,h; + + IsEditing =1; + ReStoreP0 = SelectedFromOrEnd; + ReStoreP1 = SelectedIndex; + + x = 438 + (SelectedIndex * 48); + y = 210 + (SelectedFromOrEnd * 112); + w = 36; + h = 32; + + vEdit.Init(x,y,w,h,0,0,1,clTeal); + vEdit.Color = clTeal; + vEdit.SetMaxLen(2); + if(ReStoreP0 ==0){ + vEdit.Str.Text[0] = vtTextFrom[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextFrom[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + }else + if(ReStoreP0 ==1){ + vEdit.Str.Text[0] = vtTextTo[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextTo[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + } + vEdit.SetPstTail(); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); +} + +void TPrintInf::RestoreFromEdit(void) +{ + int x,y,w,h; + + if(IsEditing == 0)return; + + x = 438 + (SelectedIndex * 48); + y = 210 + (ReStoreP0 * 112); + w = 36; + h = 32; + + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + if(ReStoreP0 == 0){ + vtTextFrom[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextFrom[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextFrom[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[ReStoreP1]); + }else + if(ReStoreP0 == 1){ + vtTextTo[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextTo[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextTo[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[ReStoreP1]); + } + IsEditing = 0; +} + +TGuiMsgReturn TPrintInf::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + int isMaskReturn = 0; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else + if(WhatSel == 0){ + if( (aKey == VK_EXECUTE) || (aKey == dfKEY_SETUP) ){ + ChangeWg(); + DrawWidget(); + }else + if( aKey == VK_RIGHT){ + WhatSel = 1; + DrawBoxItemsOutLine(); + DrawBoxTimeOutLine(); + DrawSaveButton(); + if(WhatSel == 1){ + if(IsEditing == 0){ + SetEditStart(); + } + }else{ + if(IsEditing){ + RestoreFromEdit(); + } + } + }else + if(aKey == VK_UP){ + if(FocusIndex >0){ + FocusIndex--; + DrawWidget(); + } + }else + if(aKey == VK_DOWN){ + if(FocusIndex <4){ + FocusIndex++; + DrawWidget(); + } + } + }else + if(WhatSel == 1){ + if(aKey == VK_LEFT){ + if(SelectedIndex >0){ + RestoreFromEdit(); + SelectedIndex--; + SetEditStart(); + } + }else + if(aKey == VK_RIGHT){ + if(SelectedIndex <5){ + RestoreFromEdit(); + SelectedIndex++; + SetEditStart(); + } + }else + if(aKey == VK_UP){ + if(SelectedFromOrEnd >0){ + RestoreFromEdit(); + SelectedFromOrEnd--; + SetEditStart(); + } + }else + if(aKey == VK_DOWN){ + if(SelectedFromOrEnd <1){ + RestoreFromEdit(); + SelectedFromOrEnd++; + SetEditStart(); + }else{ + WhatSel = 2; + DrawBoxItemsOutLine(); + DrawBoxTimeOutLine(); + DrawSaveButton(); + if(WhatSel == 1){ + if(IsEditing == 0){ + SetEditStart(); + } + }else{ + if(IsEditing){ + RestoreFromEdit(); + } + } + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + }else + if(WhatSel == 2){ + if(aKey == VK_EXECUTE){ + //Get Detial Here + WhatSel = 3; + GetDetial(); + ShowDetial(); + }else + if(aKey == VK_UP){ + WhatSel = 1; + DrawBoxItemsOutLine(); + DrawBoxTimeOutLine(); + DrawSaveButton(); + if(WhatSel == 1){ + if(IsEditing == 0){ + SetEditStart(); + } + }else{ + if(IsEditing){ + RestoreFromEdit(); + } + } + } + }else + if(WhatSel == 3){ + if(aKey == VK_EXECUTE){ + //Print Here + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(200, 86, 400, 140, 2); + } + }else + if(aKey == VK_RETURN){ + isMaskReturn = 1; + WhatSel = 2; + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clFrmFace); + DrawBoxItems(); + ReDrawItems(); + DrawWidget(); + DrawBoxTimeOutLine(); + DrawTimeEntryNoUpdate(); + DrawBoxTimeString(); + DrawSaveButton(); + } + }else{ + WhatSel = 0; + } + + if(aKey == VK_TAB){ + WhatSel++; + if(WhatSel >2)WhatSel = 0; + DrawBoxItemsOutLine(); + DrawBoxTimeOutLine(); + DrawSaveButton(); + if(WhatSel == 1){ + if(IsEditing == 0){ + SetEditStart(); + } + }else{ + if(IsEditing){ + RestoreFromEdit(); + } + } + }else + if(aKey == VK_RETURN){ + if(isMaskReturn == 0){ + aMsg = guiMsgReturn; + } + } + return aMsg; +} + +void TPrintInf::GetDetial() +{ + GetStartStopTime(); + pMsg->LoadData(); + pMsg->StartTime = this->StartTime; + pMsg->StopTime = this->StopTime; + pMsg->FindInTimeEntry(); + + this->Count = pMsg->Count; + this->CountFire = pMsg->CountFire; + this->CountLinkage = pMsg->CountLinkage; + this->CountSv = pMsg->CountSv; + this->CountFault = pMsg->CountFault; + this->CountOperate = pMsg->CountOperate; + + this->Count2Print =0; + this->Count2Print += InfList[0] ? this->CountFire : 0; + this->Count2Print += InfList[1] ? this->CountLinkage : 0; + this->Count2Print += InfList[2] ? this->CountSv : 0; + this->Count2Print += InfList[3] ? this->CountFault : 0; + this->Count2Print += InfList[4] ? this->CountOperate : 0; + + this->InxScope.Begin.Fire = pMsg->InxScope.Begin.Fire; + this->InxScope.End.Fire = pMsg->InxScope.End.Fire; + this->InxScope.Begin.Lnk = pMsg->InxScope.Begin.Lnk; + this->InxScope.End.Lnk = pMsg->InxScope.End.Lnk; + this->InxScope.Begin.Sv = pMsg->InxScope.Begin.Sv; + this->InxScope.End.Sv = pMsg->InxScope.End.Sv; + this->InxScope.Begin.Fault = pMsg->InxScope.Begin.Fault; + this->InxScope.End.Fault = pMsg->InxScope.End.Fault; + this->InxScope.Begin.Opa = pMsg->InxScope.Begin.Opa; + this->InxScope.End.Opa = pMsg->InxScope.End.Opa; +} + + +unsigned long long TPrintInf::GetMsgMemInx(int What, int aInx) +{ + unsigned int Addr, SdAddr; + TDMix64 tMemInx; + tMemInx.D64 =0; + if(What == 0){ + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + tMemInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + tMemInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + }else + if(What == 1){ + Addr = Record.Buf4Linkage.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + tMemInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + tMemInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + }else + if(What == 2){ + Addr = Record.Buf4Sv.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + tMemInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + tMemInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + }else + if(What == 3){ + Addr = Record.Buf4Fault.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + tMemInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + tMemInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + }else + if(What == 4){ + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + tMemInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + tMemInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + } + return tMemInx.D64; +} + +int TPrintInf::PrintOneEntry() +{ + int i, WhatMax, tInx; + unsigned long long tMx; + tMx =0; + int tDoneCount =0; + WhatMax = -1; + for(i=0; i<5; i++){ + if(InfList[i]){ + OnGo.MemX[i] = GetMsgMemInx(i,OnGo.Inx[i]); + } + } + for(i=0; i<5; i++){ + if(InfList[i]){ + if(OnGo.MemX[i] > tMx){ + tMx = OnGo.MemX[i]; + tInx = OnGo.Inx[i]; + WhatMax = i; + } + } + } + + if(WhatMax <0)return 1; + + if( (WhatMax > -1) && (WhatMax < 5) ){ + if(WhatMax == 0){ + pMsg->MsgFire->GetEntry4Print(tInx); + RecordMsg.D32[0] = pMsg->MsgFire->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = pMsg->MsgFire->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = pMsg->MsgFire->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = pMsg->MsgFire->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = pMsg->MsgFire->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(0, RecordMsg, &pMsg->MsgFire->Text.Text[24]); + }else + if(WhatMax == 1){ + pMsg->MsgLinkage->GetEntry4Print(tInx); + RecordMsg.D32[0] = pMsg->MsgLinkage->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = pMsg->MsgLinkage->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = pMsg->MsgLinkage->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = pMsg->MsgLinkage->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = pMsg->MsgLinkage->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(1, RecordMsg, &pMsg->MsgLinkage->Text.Text[24]); + }else + if(WhatMax == 2){ + pMsg->MsgSv->GetEntry4Print(tInx); + RecordMsg.D32[0] = pMsg->MsgSv->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = pMsg->MsgSv->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = pMsg->MsgSv->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = pMsg->MsgSv->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = pMsg->MsgSv->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(2, RecordMsg, &pMsg->MsgSv->Text.Text[24]); + }else + if(WhatMax == 3){ + pMsg->MsgFault->GetEntry4Print(tInx); + RecordMsg.D32[0] = pMsg->MsgFault->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = pMsg->MsgFault->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = pMsg->MsgFault->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = pMsg->MsgFault->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = pMsg->MsgFault->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(3, RecordMsg, &pMsg->MsgFault->DescpText.Text[28]); + }else + if(WhatMax == 4){ + pMsg->MsgOperate->GetEntry4Print(tInx); + RecordMsg.D32[0] = pMsg->MsgOperate->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = pMsg->MsgOperate->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = pMsg->MsgOperate->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = pMsg->MsgOperate->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = pMsg->MsgOperate->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(4, RecordMsg, &pMsg->MsgOperate->Text.Text[28]); + } + OnGo.Inx[WhatMax]--; + } + if(InfList[0] && (OnGo.Inx[0] < InxScope.Begin.Fire) ){ + tDoneCount++; + } + if(InfList[1] && (OnGo.Inx[1] < InxScope.Begin.Lnk) ){ + tDoneCount++; + } + if(InfList[2] && (OnGo.Inx[2] < InxScope.Begin.Sv) ){ + tDoneCount++; + } + if(InfList[3] && (OnGo.Inx[3] < InxScope.Begin.Fault) ){ + tDoneCount++; + } + if(InfList[4] && (OnGo.Inx[4] < InxScope.Begin.Opa) ){ + tDoneCount++; + } + if(tDoneCount >= OnGo.AvaCount)return 1; + return 0; +} + +void TPrintInf::GoPrint() +{ + int i; + int MaxCount = PrintBuf_Count /2; + OnGo.Init(); + OnGo.Inx[0] = this->InxScope.End.Fire; + OnGo.Inx[1] = this->InxScope.End.Lnk; + OnGo.Inx[2] = this->InxScope.End.Sv; + OnGo.Inx[3] = this->InxScope.End.Fault; + OnGo.Inx[4] = this->InxScope.End.Opa; + + for(i=0;i<5;i++){ + if(InfList[i]) + OnGo.AvaCount++; + } + + for(OnGo.px=0, i=0; (OnGo.px打印机"); + + TextRender_string24(svGridX[0], Lv.Grid.Top[0] +10, clNearWhite, "打印机使能"); + TextRender_string24(svGridX[0], Lv.Grid.Top[1] +10, clNearWhite, "打印信息选择"); + + + TextRender_string24(svGridX[0] +28, Lv.Grid.Top[0] +46, clNearWhite, "开启"); + TextRender_string24(svGridX[1] +28, Lv.Grid.Top[0] +46, clNearWhite, "关闭"); + + TextRender_string24(svGridX[0] +28, Lv.Grid.Top[1] +46, clNearWhite, "全部"); + TextRender_string24(svGridX[1] +28, Lv.Grid.Top[1] +46, clNearWhite, "报警"); + TextRender_string24(svGridX[2] +28, Lv.Grid.Top[1] +46, clNearWhite, "联动"); + TextRender_string24(svGridX[3] +28, Lv.Grid.Top[1] +46, clNearWhite, "监管"); + TextRender_string24(svGridX[4] +28, Lv.Grid.Top[1] +46, clNearWhite, "故障"); + TextRender_string24(svGridX[5] +28, Lv.Grid.Top[1] +46, clNearWhite, "屏蔽"); + TextRender_string24(svGridX[6] +28, Lv.Grid.Top[1] +46, clNearWhite, "操作"); + TextRender_string24(svGridX[7] +28, Lv.Grid.Top[1] +46, clNearWhite, "其他"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Local->Printer Setup"); + + TextRender_string24(svGridX[0], Lv.Grid.Top[0] +10, clNearWhite, "Printer Enable Set"); + TextRender_string24(svGridX[0], Lv.Grid.Top[1] +10, clNearWhite, "Infomation Set"); + + + TextRender_string24(svGridX[0] +28, Lv.Grid.Top[0] +46, clNearWhite, "On"); + TextRender_string24(svGridX[1] +28, Lv.Grid.Top[0] +46, clNearWhite, "Off"); + + TextRender_string24(svGridX[0] +28, Lv.Grid.Top[1] +46, clNearWhite, "All"); + TextRender_string24(svGridX[1] +28, Lv.Grid.Top[1] +46, clNearWhite, "Fire"); + TextRender_string24(svGridX[2] +28, Lv.Grid.Top[1] +46, clNearWhite, "Link"); + TextRender_string24(svGridX[3] +28, Lv.Grid.Top[1] +46, clNearWhite, "SUPV"); + TextRender_string24(svGridX[4] +28, Lv.Grid.Top[1] +46, clNearWhite, "Flt."); + TextRender_string24(svGridX[5] +28, Lv.Grid.Top[1] +46, clNearWhite, "Mask"); + TextRender_string24(svGridX[6] +28, Lv.Grid.Top[1] +46, clNearWhite, "OPER"); + TextRender_string24(svGridX[7] +28, Lv.Grid.Top[1] +46, clNearWhite, "Oth."); + } + + DrawOnOff(); + DrawEvent(); +} + +void TPrinterSet::Show() +{ + RenderBackGround(); + DrawSelf(); + DrawSelected(1); +} + +void TPrinterSet::DrawTip() +{ + +} + +void TPrinterSet::FullRedraw(int Prm) +{ + if(Prm == 0){ + Show(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + DrawSelf(); + DrawSelected(1); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TPrinterSet::PermissionCmdReturnDraw() +{ + RectFillRender(Lv.Grid.Left[2] + 200 -10, Lv.Grid.Top[2] + 40 -10, Lv.Grid.Left[2] + 200 -10 + 400 + 20, Lv.Grid.Top[2] + 40 -10 + 140 + 20, ContentColor); +} + +void TPrinterSet::PermissionCmdGO() +{ + if( GoResult()){ + LoadSysCfg(); + } +} + +void TPrinterSet::ShowSaveResult() +{ + char *tText; + if(SaveResult == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, " "); + }else + if(SaveResult < 0){ + if(LanguageEnCn==0)tText = " 保存失败 "; else tText="Failed To Save"; + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, tText); + }else{ + if(LanguageEnCn==0)tText = " 保存成功 "; else tText="Saved OK "; + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, tText); + } +} + +void TPrinterSet::ShowSaveResult(int aNewResult) +{ + SaveResult = aNewResult; + ShowSaveResult(); +} + +void TPrinterSet::LoadSysCfg() +{ + Sta.OnOff = PriterSetting.OnOff; + Sta.All = PriterSetting.PrintSelected & (0x0001); + Sta.Fire = PriterSetting.PrintSelected & (0x0002); + Sta.Lnk = PriterSetting.PrintSelected & (0x0004); + Sta.Sv = PriterSetting.PrintSelected & (0x0008); + Sta.Fault = PriterSetting.PrintSelected & (0x0010); + Sta.Mask = PriterSetting.PrintSelected & (0x0020); + Sta.Opa = PriterSetting.PrintSelected & (0x0040); + Sta.Others = PriterSetting.PrintSelected & (0x0080); +} + +int TPrinterSet::GoResult() +{ + Sta.WriteByte = 0; + if(Sta.All) Sta.WriteByte = 1; + if(Sta.Fire) Sta.WriteByte |= 0x02; + if(Sta.Lnk) Sta.WriteByte |= 0x04; + if(Sta.Sv) Sta.WriteByte |= 0x08; + if(Sta.Fault) Sta.WriteByte |= 0x10; + if(Sta.Mask) Sta.WriteByte |= 0x20; + if(Sta.Opa) Sta.WriteByte |= 0x40; + if(Sta.Others) Sta.WriteByte |= 0x80; + + Record.WritePrinterState(Sta.OnOff); + Record.WritePrinterEvent(Sta.WriteByte); + Record.ReadPrintSet(); + + if( (PriterSetting.OnOff == Sta.OnOff) && (PriterSetting.PrintSelected == Sta.WriteByte) ){ + Record.OperateAdd_CfgPriter(PriterSetting.OnOff, PriterSetting.PrintSelected); + ShowSaveResult(1); + }else{ + ShowSaveResult(-1); + } + return 0; +} + +void TPrinterSet::sRecoverSetDefault() +{ + Record.WritePrinterState(0x01); + Record.WritePrinterEvent(0xFF); + Record.ReadPrintSet(); +} + +void TPrinterSet::DrawSelected(int IsSelected) +{ + unsigned int tClr; + tClr = IsSelected ? clNearWhite : ItemColor; + if(Tag.Group == 0){ + if(Tag.Inx0 == 0) + TRoundSquare::sSelected(svGridX[0] +2, Lv.Grid.Top[0] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx0 == 1) + TRoundSquare::sSelected(svGridX[1] +2, Lv.Grid.Top[0] + 46, dWWidth, dWHeigh, 4, tClr); + }else + if(Tag.Group == 1){ + if(Tag.Inx1 == 0) + TRoundSquare::sSelected(svGridX[0] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx1 == 1) + TRoundSquare::sSelected(svGridX[1] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx1 == 2) + TRoundSquare::sSelected(svGridX[2] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx1 == 3) + TRoundSquare::sSelected(svGridX[3] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx1 == 4) + TRoundSquare::sSelected(svGridX[4] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx1 == 5) + TRoundSquare::sSelected(svGridX[5] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx1 == 6) + TRoundSquare::sSelected(svGridX[6] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + else if(Tag.Inx1 == 7) + TRoundSquare::sSelected(svGridX[7] +2, Lv.Grid.Top[1] + 46, dWWidth, dWHeigh, 4, tClr); + } +} + +void TPrinterSet::ChangeValue() +{ + if(Tag.Group == 0){ + if(Tag.Inx0 == 0) + Sta.OnOff = Sta.OnOff ? 0 : 1; + else if(Tag.Inx0 == 1) + Sta.OnOff = Sta.OnOff ? 0 : 1; + }else + if(Tag.Group == 1){ + if(Tag.Inx1 == 0) + Sta.All = Sta.All ? 0: 1; + else if(Tag.Inx1 == 1) + Sta.Fire = Sta.Fire ? 0: 1; + else if(Tag.Inx1 == 2) + Sta.Lnk = Sta.Lnk ? 0: 1; + else if(Tag.Inx1 == 3) + Sta.Sv = Sta.Sv ? 0: 1; + else if(Tag.Inx1 == 4) + Sta.Fault = Sta.Fault ? 0: 1; + else if(Tag.Inx1 == 5) + Sta.Mask = Sta.Mask ? 0: 1; + else if(Tag.Inx1 == 6) + Sta.Opa = Sta.Opa ? 0: 1; + else if(Tag.Inx1 == 7) + Sta.Others = Sta.Others ? 0: 1; + } +} + +TGuiMsgReturn TPrinterSet::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + if(aKey == VK_LEFT){ + if(Tag.Group == 0){ + if(Tag.Inx0 >0){ + DrawSelected(0); + Tag.Inx0 --; + DrawSelected(1); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 >0){ + DrawSelected(0); + Tag.Inx1 --; + DrawSelected(1); + } + } + }else + if(aKey == VK_RIGHT){ + if(Tag.Group == 0){ + if(Tag.Inx0 <1){ + DrawSelected(0); + Tag.Inx0 ++; + DrawSelected(1); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 <7){ + DrawSelected(0); + Tag.Inx1 ++; + DrawSelected(1); + } + } + }else + if(aKey == VK_UP){ + if(Tag.Group == 0){ + + }else + if(Tag.Group == 1){ + DrawSelected(0); + Tag.Group = 0; + if(Tag.Inx0 >1)Tag.Inx0 = 1; + DrawSelected(1); + } + }else + if(aKey == VK_DOWN){ + if(Tag.Group == 0){ + DrawSelected(0); + Tag.Group = 1; + if(Tag.Inx1 >7)Tag.Inx1 =7; + DrawSelected(1); + }else + if(Tag.Group == 1){ + } + }else + if(aKey == VK_F1){ + ChangeValue(); + DrawOnOff(); + DrawEvent(); + }else + if(aKey == VK_EXECUTE){ + //Save Data Here + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 40, 400, 140, 2); + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + if( (aKey != VK_EXECUTE) && (aKey != VK_RETURN) ){ + if(SaveResult != 0)ShowSaveResult(0); + } + } + + + + return aMsg; +} + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/PrinterSet.h b/MyCode/Gui/PrinterSet.h new file mode 100644 index 0000000..4129360 --- /dev/null +++ b/MyCode/Gui/PrinterSet.h @@ -0,0 +1,154 @@ +#ifndef PRINTERSET_H_ +#define PRINTERSET_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" + +class TPrinterSet{ + public: + static constexpr unsigned short hList[12] = {80,80,32,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint TipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 20, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 80, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 20, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 10, + }; + + + struct{ + unsigned char OnOff; + unsigned char All; + unsigned char Fire; + unsigned char Lnk; + + unsigned char Sv; + unsigned char Fault; + unsigned char Mask; + unsigned char Opa; + + unsigned char Others; + unsigned char Dump0; + unsigned char Dump1; + unsigned char WriteByte; + }Sta; + + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Dump0; + }Tag; + + int SaveResult; + + unsigned char IsPermission; + public: + TPrinterSet(){}; + void Init(); + void RenderBackGround(void); + + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void Show(); + void DrawTip(); + void FullRedraw(int Prm); + + void DrawSelected(int IsSelected); + + void DrawOnOff(); + void DrawEvent(); + + void ChangeValue(); + + void ShowSaveResult(); + void ShowSaveResult(int aSaveResult); + + void LoadSysCfg(); + void SetDefault(); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void SetProperty(); + void SetEventType(); + + static void sRecoverSetDefault(); + + void ShowSta(int aGroup, int aInx); + void ShowStaAll(); + int GoResult(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + int ExtRequst(unsigned char Prm){return 0;} + +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/ProjectSet.cpp b/MyCode/Gui/ProjectSet.cpp new file mode 100644 index 0000000..ed66e01 --- /dev/null +++ b/MyCode/Gui/ProjectSet.cpp @@ -0,0 +1,739 @@ +#include "RuntimeData.h" +#include "ProjectSet.h" +#include "DevMask.h" + +extern "C"{ + #include "user_eeprom.h" +} + +void TProjectSet::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "工程->工程信息"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "工程名称"); + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +10, clNearWhite, "维保提醒"); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] +10, clNearWhite, "运行模式"); + TextRender_string24(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] +10, clNearWhite, "系统授权"); + TextRender_string24(Lv.Grid.Left[4] + 6, Lv.Grid.Top[4] +10, clNearWhite, "设计数量"); + TextRender_string24(Lv.Grid.Left[0] + 520, Lv.Grid.Top[0] +8, clNearWhite, "运行时长:"); + TextDigitRender5Right24(Lv.Grid.Left[0] + 636, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun / 24); + TextRender_string24(Lv.Grid.Left[0] + 698, Lv.Grid.Top[0] +8, clNearWhite, "天"); + TextDigitRender2Right24(Lv.Grid.Left[0] + 722, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun % 24); + TextRender_string24(Lv.Grid.Left[0] + 746, Lv.Grid.Top[0] +8, clNearWhite, "小时"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Project->Project Information"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "Project "); + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +10, clNearWhite, "Maintena"); + TextRender_string24(Lv.Grid.Left[2] + 6, Lv.Grid.Top[2] +10, clNearWhite, "RunMode "); + TextRender_string24(Lv.Grid.Left[3] + 6, Lv.Grid.Top[3] +10, clNearWhite, "Mandate "); + TextRender_string24(Lv.Grid.Left[4] + 6, Lv.Grid.Top[4] +10, clNearWhite, "Design Num of Terminal Device"); + } +} + +void TProjectSet::Init() +{ + IsExtInput = 1; + Tag.Reset(); + SubItemActive =0; + IsPermission = 0; + IsEditting = 0; +} + +void TProjectSet::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickBound.Left, aPanel->Bound.Top, aPanel->Bound.Right, aPanel->Bound.Bottom, ContentColor); + PermissionCmdReturnDraw(); + vEdit.Selected = 1; + vEdit.Show(); +} + +void TProjectSet::DrawCaption(void) +{ + +} + +void TProjectSet::Show() +{ + RenderBackGround(); + DrawSelf(); + LoadCfg(); + ShowInf(); + Check4Selected(); +} + +void TProjectSet::ShowSta() +{ + if(LanguageEnCn==0){ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, "保存成功 "); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, "保存失败 "); + } + }else{ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, "Save OK "); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, "Save Err "); + } + } +} + +void TProjectSet::ShowSta(int aSta) +{ + Sta = aSta; + ShowSta(); +} + +void TProjectSet::FullRedraw(int Prm) +{ + if(SubItemActive){ + if(SubItemActive == 1){ + Maintain.FullRedraw(Prm); + }else + if(SubItemActive == 2){ + RunModeCfg.FullRedraw(Prm); + }else + if(SubItemActive == 3){ + DevAuthorize.FullRedraw(Prm); + }else + if(SubItemActive == 4){ + DesignPrmSet.FullRedraw(Prm); + } + }else{ + if(Prm == 0){ + Show(); + Check4Selected(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + DrawSelf(); + ShowInf(); + Check4Selected(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } + } +} + +void TProjectSet::PermissionCmdReturnDraw() +{ + RectFillRender(Lv.Grid.Left[1] + 200-10, Lv.Grid.Top[1] + 0, Lv.Grid.Left[1] + 200-10 + 420, Lv.Grid.Top[1] + 0 + 164, ContentColor); + for(int i=0; i<4; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + DrawFixText(); + + vEdit.Show(); + + ShowInf(); +} + +void TProjectSet::PermissionCmdGO() +{ + //Save Data Here + if(PermissionCmd == 1){ + Write2Eep(); + }else + if(PermissionCmd == 2){ + vEdit.Selected = 0; + vEdit.Show(); + InitPanel(); + IsEditting = 1; + IsExtInput = 1; + } +} + + +void TProjectSet::ClearSelected(void) +{ + switch(Tag.Inx){ + case 0: + vEdit.Selected = 0; + vEdit.Show(); + break; + case 1: + RectFillRender(Lv.Grid.Left[1], Lv.Grid.Top[1], Lv.Grid.Left[1] + Lv.Grid.Right[1], Lv.Grid.Top[1] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[1], Lv.Grid.Top[1], Lv.Grid.Left[1] + 3, Lv.Grid.Bottom[1], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[1] -3, Lv.Grid.Top[1], Lv.Grid.Right[1], Lv.Grid.Bottom[1], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[1], Lv.Grid.Bottom[1] -3, Lv.Grid.Right[1], Lv.Grid.Bottom[1], ItemColor); //draw rectangle + break; + case 2: + RectFillRender(Lv.Grid.Left[2], Lv.Grid.Top[2], Lv.Grid.Left[2] + Lv.Grid.Right[2], Lv.Grid.Top[2] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[2], Lv.Grid.Top[2], Lv.Grid.Left[2] + 3, Lv.Grid.Bottom[2], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[2] -3, Lv.Grid.Top[2], Lv.Grid.Right[2], Lv.Grid.Bottom[2], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[2], Lv.Grid.Bottom[2] -3, Lv.Grid.Right[2], Lv.Grid.Bottom[2], ItemColor); //draw rectangle + break; + case 3: + RectFillRender(Lv.Grid.Left[3], Lv.Grid.Top[3], Lv.Grid.Left[3] + Lv.Grid.Right[3], Lv.Grid.Top[3] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[3], Lv.Grid.Top[3], Lv.Grid.Left[3] + 3, Lv.Grid.Bottom[3], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[3] -3, Lv.Grid.Top[3], Lv.Grid.Right[3], Lv.Grid.Bottom[3], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[3], Lv.Grid.Bottom[3] -3, Lv.Grid.Right[3], Lv.Grid.Bottom[3], ItemColor); //draw rectangle + break; + case 4: + RectFillRender(Lv.Grid.Left[4], Lv.Grid.Top[4], Lv.Grid.Left[4] + Lv.Grid.Right[4], Lv.Grid.Top[4] + 3, ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[4], Lv.Grid.Top[4], Lv.Grid.Left[4] + 3, Lv.Grid.Bottom[4], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Right[4] -3, Lv.Grid.Top[4], Lv.Grid.Right[4], Lv.Grid.Bottom[4], ItemColor); //draw rectangle + RectFillRender(Lv.Grid.Left[4], Lv.Grid.Bottom[4] -3, Lv.Grid.Right[4], Lv.Grid.Bottom[4], ItemColor); //draw rectangle + break; + default: + + break; + } +} + +void TProjectSet::Check4Selected(void) +{ + unsigned int i; + vEdit.Selected = 0; + + switch(Tag.Inx){ + case 0: + vEdit.Selected = 1; + vEdit.Show(); + break; + case 1: + RectFillRender(Lv.Grid.Left[1], Lv.Grid.Top[1], Lv.Grid.Left[1] + Lv.Grid.Right[1], Lv.Grid.Top[1] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[1], Lv.Grid.Top[1], Lv.Grid.Left[1] + 3, Lv.Grid.Bottom[1], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[1] -3, Lv.Grid.Top[1], Lv.Grid.Right[1], Lv.Grid.Bottom[1], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[1], Lv.Grid.Bottom[1] -3, Lv.Grid.Right[1], Lv.Grid.Bottom[1], clBlue); //draw rectangle + break; + case 2: + RectFillRender(Lv.Grid.Left[2], Lv.Grid.Top[2], Lv.Grid.Left[2] + Lv.Grid.Right[2], Lv.Grid.Top[2] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[2], Lv.Grid.Top[2], Lv.Grid.Left[2] + 3, Lv.Grid.Bottom[2], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[2] -3, Lv.Grid.Top[2], Lv.Grid.Right[2], Lv.Grid.Bottom[2], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[2], Lv.Grid.Bottom[2] -3, Lv.Grid.Right[2], Lv.Grid.Bottom[2], clBlue); //draw rectangle + break; + case 3: + RectFillRender(Lv.Grid.Left[3], Lv.Grid.Top[3], Lv.Grid.Left[3] + Lv.Grid.Right[3], Lv.Grid.Top[3] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[3], Lv.Grid.Top[3], Lv.Grid.Left[3] + 3, Lv.Grid.Bottom[3], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[3] -3, Lv.Grid.Top[3], Lv.Grid.Right[3], Lv.Grid.Bottom[3], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[3], Lv.Grid.Bottom[3] -3, Lv.Grid.Right[3], Lv.Grid.Bottom[3], clBlue); //draw rectangle + break; + case 4: + RectFillRender(Lv.Grid.Left[4], Lv.Grid.Top[4], Lv.Grid.Left[4] + Lv.Grid.Right[4], Lv.Grid.Top[4] + 3, clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[4], Lv.Grid.Top[4], Lv.Grid.Left[4] + 3, Lv.Grid.Bottom[4], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Right[4] -3, Lv.Grid.Top[4], Lv.Grid.Right[4], Lv.Grid.Bottom[4], clBlue); //draw rectangle + RectFillRender(Lv.Grid.Left[4], Lv.Grid.Bottom[4] -3, Lv.Grid.Right[4], Lv.Grid.Bottom[4], clBlue); //draw rectangle + break; + default: + + break; + } +} + +void TProjectSet::ShowInf(void) +{ + vEdit.Show(); + + Maintain.ExtLoadData(); + RunModeCfg.ExtLoadData(); + //SysAuthorize + DesignPrmSet.ExtLoadData(); + + if(LanguageEnCn==0){ + if(Maintain.ExtLoadSetting.IsCustomTime){ + if(Maintain.ExtLoadSetting.IsHalfYear)TextRender_string24(Lv.Grid.Left[1] + 20, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, "定时维保"); + TMyString::sClear( Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Month[0], Text); + TMyString::sAddOnStr("月",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Day[0], Text); + TMyString::sAddOnStr("日 ",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Month[1], Text); + TMyString::sAddOnStr("月",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Day[1], Text); + TMyString::sAddOnStr("日 ",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Month[2], Text); + TMyString::sAddOnStr("月",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Day[2], Text); + TMyString::sAddOnStr("日 ",Text); + //TMyString::sFillFixLen(Text, 28); + TextRender_string24(Lv.Grid.Left[1] + 140, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, Text); + }else{ + if(Maintain.ExtLoadSetting.IsHalfYear)TextRender_string24(Lv.Grid.Left[1] + 20, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, "半年"); + else TextRender_string24(Lv.Grid.Left[1] + 20, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, "一年"); + //TMyString::sClear( Text); + //TMyString::sAddOnStr(" ",Text); + //TMyString::sFillFixLen(Text, 28); + //TextRender_string24(Lv.Grid.Left[1] + 140, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, Text); + } + + if(RunState != TRunModeCfg::RunModeAdjust){ + TextRender_string24(Lv.Grid.Left[2] + 20, Lv.Grid.Top[2] + 42, clNearWhite, ItemColor, "正常运行"); + }else{ + TextRender_string24(Lv.Grid.Left[2] + 20, Lv.Grid.Top[2] + 42, clNearWhite, ItemColor, "调试运行"); + } + + if(SysAuthorize.fDa.Done){ + TCircle::sRender(Lv.Grid.Left[3] + 24, Lv.Grid.Top[3] +54, 12, clDeepGreen, 1); + TextRender_string24(Lv.Grid.Left[3] + 46, Lv.Grid.Top[3] +42, clNearWhite, "系统已授权"); + + TextRender_string24(Lv.Grid.Left[3] + 186, Lv.Grid.Top[3] +42, clNearWhite, " "); + }else{ + TCircle::sRender(Lv.Grid.Left[3] + 24, Lv.Grid.Top[3] +54, 12, clRed, 1); + TextRender_string24(Lv.Grid.Left[3] + 46, Lv.Grid.Top[3] +42, clNearWhite, "系统未授权"); + + TextRender_string24(Lv.Grid.Left[3] + 186, Lv.Grid.Top[3] +42, clNearWhite, "试用截止日期: 年 月 日"); + } + + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[4] + 20, Lv.Grid.Top[4] +42, clNearWhite, "共 种设备类型. 点位总数 点. 系统总容量 点."); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[4] + 20, Lv.Grid.Top[4] +42, clNearWhite, "共 种设备类型. 点位总数 点. 本机为区域机 "); + }else{ + TextRender_string24(Lv.Grid.Left[4] + 20, Lv.Grid.Top[4] +42, clNearWhite, "共 种设备类型. 点位总数 点. 本机为单机 "); + } + }else{ + if(Maintain.ExtLoadSetting.IsCustomTime){ + if(Maintain.ExtLoadSetting.IsHalfYear)TextRender_string24(Lv.Grid.Left[1] + 20, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, "Regularly"); + TMyString::sClear( Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Month[0], Text); + TMyString::sAddOnStr("Mon ",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Day[0], Text); + TMyString::sAddOnStr("Day, ",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Month[1], Text); + TMyString::sAddOnStr("Mon ",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Day[1], Text); + TMyString::sAddOnStr("Day, ",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Month[2], Text); + TMyString::sAddOnStr("Mon ",Text); + TMyString::sAddOn2Dg(Maintain.ExtLoadSetting.Day[2], Text); + TMyString::sAddOnStr("Day",Text); + //TMyString::sFillFixLen(Text, 42); + TextRender_string24(Lv.Grid.Left[1] + 140, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, Text); + }else{ + if(Maintain.ExtLoadSetting.IsHalfYear)TextRender_string24(Lv.Grid.Left[1] + 20, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, "Half Yesr"); + else TextRender_string24(Lv.Grid.Left[1] + 20, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, "YEAR"); + //TMyString::sClear( Text); + //TMyString::sAddOnStr(" ",Text); + //TMyString::sFillFixLen(Text, 28); + //TextRender_string24(Lv.Grid.Left[1] + 140, Lv.Grid.Top[1] + 42, clNearWhite, ItemColor, Text); + } + + if(RunState != TRunModeCfg::RunModeAdjust){ + TextRender_string24(Lv.Grid.Left[2] + 20, Lv.Grid.Top[2] + 42, clNearWhite, ItemColor, "Working "); + }else{ + TextRender_string24(Lv.Grid.Left[2] + 20, Lv.Grid.Top[2] + 42, clNearWhite, ItemColor, "TestMode"); + } + + if(SysAuthorize.fDa.Done){ + TCircle::sRender(Lv.Grid.Left[3] + 24, Lv.Grid.Top[3] +54, 12, clDeepGreen, 1); + TextRender_string24(Lv.Grid.Left[3] + 46, Lv.Grid.Top[3] +42, clNearWhite, "Authorized"); + + TextRender_string24(Lv.Grid.Left[3] + 186, Lv.Grid.Top[3] +42, clNearWhite, " "); + }else{ + TCircle::sRender(Lv.Grid.Left[3] + 24, Lv.Grid.Top[3] +54, 12, clRed, 1); + TextRender_string24(Lv.Grid.Left[3] + 46, Lv.Grid.Top[3] +42, clNearWhite, "Unauthoriz"); + + TextRender_string24(Lv.Grid.Left[3] + 186, Lv.Grid.Top[3] +42, clNearWhite, "Trial Period: Y M D"); + } + + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(Lv.Grid.Left[4] + 20, Lv.Grid.Top[4] +42, clNearWhite, " Types Of Dev; Devices: ; Devs On Sys: "); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(Lv.Grid.Left[4] + 20, Lv.Grid.Top[4] +42, clNearWhite, " Types Of Dev; Devices: ; Regional "); + }else{ + TextRender_string24(Lv.Grid.Left[4] + 20, Lv.Grid.Top[4] +42, clNearWhite, " Types Of Dev; Devices: ; Stand Alone "); + } + } + + + ShowDesignedCount(); +} + +void TProjectSet::InitPanel() +{ + int x,y,x2,y2, aW,aH,i; + + x = 20; + y = 120; + x2 = 799; + y2 = 310; + aW = x2 - x +1; + aH = y2 -y +1; + + aPanel->Init(x,y,aW,aH,0,0,clMoneyGreen, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearWhite,clBlue); + if(LanguageEnCn==0)aPanel->Caption.SetText("按中/EN键切换输入法,设置键保存更改,返回键放弃更改并返回",24); + else aPanel->Caption.SetText("'中/EN':switch input method; 'Set':Save",24); + aPanel->Caption.Enable = 1; + aPanel->Caption.Visible = 1; + + aPanel->SText[0].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0)TMyString::sFromStr( "请根据以下输入法提示输入", aPanel->SText[0].Text); + else TMyString::sFromStr( "According To The Prompts", aPanel->SText[0].Text); + aPanel->SText[0].Enable = 1; + aPanel->SText[0].Visible = 1; + + aPanel->Edit[ 0].Init(10,40,420,30,x,y,1,clNearBlack); + aPanel->Edit[ 0].Str.FromStr(vEdit.Str.Text); + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 1; + } + + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + + IsExtInput = 1; + CnInput.Init(aPanel->Bound.Left + 10, aPanel->Bound.Top +80, 760, 90, 0, 0, clGray); + CnInput.Show(); + if(LanguageEnCn==0)TMyString::sFromStr( "请根据以下输入法提示输入", aPanel->SText[0].Text); + else TMyString::sFromStr( "According To The Prompts", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +TGuiMsgReturn TProjectSet::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + int i; + const char *p; + TGuiMsgReturn PmsRtnMsg; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + if(SubItemActive){ + TGuiMsgReturn SubReturnMsg; + SubReturnMsg = guiMsgNone; + if(SubItemActive == 1){ + SubReturnMsg = Maintain.KeyIn(aKey); + }else + if(SubItemActive == 2){ + SubReturnMsg = RunModeCfg.KeyIn(aKey); + }else + if(SubItemActive == 3){ + SubReturnMsg = DevAuthorize.KeyIn(aKey); + }else + if(SubItemActive == 4){ + SubReturnMsg = DesignPrmSet.KeyIn(aKey); + } + + if(SubReturnMsg == guiMsgReturn){ + SubItemActive = 0; + Show(); + } + return aMsg; + } + + if(IsEditting){ + if(aKey == dfKEY_SETUP){ + TMyString::sFromStr(aPanel->Edit[0].Str.Text, vEdit.Str.Text); + TMyString::sBrokeFixLen(vEdit.Str.Text, 32); + DrawRecoveCnInput(); + IsEditting = 0; + }else + if(aKey == dfKEY_ENCN){ + CnInput.KeyIn(aKey); + if(0){ + IsExtInput = 0; + CnInput.OverPrint(this->aPanel->Color); + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + if(LanguageEnCn==0)TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + else TMyString::sFromStr("Enter 0..9", aPanel->SText[0].Text); + aPanel->SText[0].Show(); + } + }else + if(aKey == VK_RETURN){ + //Just return + DrawRecoveCnInput(); + ShowInf(); + IsEditting = 0; + }else{ + if( (aKey == VK_DELETE) && (CnInput.sEdit.Pst == -1) ){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); + }else{ + p = CnInput.KeyIn(aKey); + if(p != nullptr){ + if(CnInput.GotChar[0] != '\0'){ + aPanel->Edit[0].Pst = aPanel->Edit[0].Str.Insert(CnInput.GotChar, aPanel->Edit[0].Pst); + aPanel->Edit[0].Str.BrokeFixLen(32); + aPanel->Edit[0].CorrectPst(); + aPanel->Edit[0].Show(); + } + } + } + } + }else{ + switch(aKey){ + /*case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Tag.Inx == 0){ + vEdit.KeyIn(aKey); + vEdit.Str.BrokeFixLen(32); + vEdit.CorrectPst(); + vEdit.Show(); + } + break;*/ + case VK_UP: + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx <4){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + break; + case dfKEY_SETUP: + if(Tag.Inx == 0){ + PermissionCmd =2; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 12, 400, 140, 3); + } + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + if(Tag.Inx == 0){ + PermissionCmd =1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 12, 400, 140, 3); + } + }else{ + if(Tag.Inx == 1){ + SubItemActive = 1; + Maintain.Init() ; + Maintain.aPanel = &CommonPanel; + Maintain.InitPanel(); + Maintain.Show(); + Maintain.LoadData(); + }else + if(Tag.Inx == 2){ + SubItemActive = 2; + RunModeCfg.Init() ; + RunModeCfg.aPanel = &CommonPanel; + RunModeCfg.InitPanel(); + RunModeCfg.Show(); + RunModeCfg.LoadData(); + }else + if(Tag.Inx == 3){ + SubItemActive = 3; + DevAuthorize.Init() ; + DevAuthorize.aPanel = &CommonPanel; + DevAuthorize.Show(); + DevAuthorize.InitPanel(); + DevAuthorize.LoadData(); + }else + if(Tag.Inx == 4){ + SubItemActive = 4; + DesignPrmSet.Init() ; + DesignPrmSet.IconList = &ImageList; + DesignPrmSet.aPanel = &CommonPanel; + DesignPrmSet.LoadBaseTypeList(); + DesignPrmSet.Show(); + DesignPrmSet.InitPanel(); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + } + if(VK_EXECUTE != aKey){ + ShowSta(0); + } + } + return aMsg; +} + +void TProjectSet::LoadCfg() +{ + unsigned int aAddr; + int i; + //Read ExistTable + aAddr = dEepAddrProjectName; + sDelayMs(10); + eeprom_read_byte(0, aAddr, PrjName, 32); + PrjName[32] = '\0'; + PrjName[33] = '\0'; + + if( (PrjName[0] == 0xFF) && (PrjName[1] == 0xFF) ){ + PrjName[0] = '\0'; + PrjName[1] = '\0'; + } + + for(i=0; i<32; i++){ + vEdit.Str.Text[i] = PrjName[i]; + } + vEdit.Str.Text[32] = '\0'; + vEdit.Str.Text[33] = '\0'; + + vEdit.SetPstTail(); +} + +void TProjectSet::Write2Eep() +{ + unsigned int aAddr; + volatile unsigned int aWait; + volatile unsigned int NotEqual; + int i; + //Read ExistTable + for(i=0; i<32; i++){ + PrjName[i] = vEdit.Str.Text[i]; + } + PrjName[32] = '\0'; + PrjName[33] = '\0'; + + aAddr = dEepAddrProjectName; + sDelayMs(20); + eeprom_write_byte_via_page(0, aAddr, PrjName, 32); + + sDelayMs(20); + aAddr = dEepAddrProjectName; + eeprom_read_byte(0, aAddr, PrjName, 32); + vEdit.Show(); + + NotEqual = 0; + for(int x=0; x<32; x++){ + if(PrjName[x] != vEdit.Str.Text[x]){ + NotEqual = 1; + break; + } + } + + if(NotEqual){ + ShowSta(-1); + }else{ + ShowSta(1); + } +} + +void TProjectSet::ShowDesignedCount() +{ + pDpt->ReadData(); + pDpt->LoadBaseTypeList(); + pDpt->LoadData2RuntimeData(); + pDpt->ExtLoadData(); + + //TextRender_string24(Lv.Grid.Left[4] + 20, Lv.Grid.Top[4] +42, clNearWhite, "共 种设备类型. 点位总数 点. 系统总容量 点."); + TextDigitRender3Right24(Lv.Grid.Left[4] + 44, Lv.Grid.Top[4] + 42, clNearWhite, ItemColor, pDpt->ExtInf.UsingTypeCount % 1000); + TextDigitRender6Right24(Lv.Grid.Left[4] + 344, Lv.Grid.Top[4] + 42, clNearWhite, ItemColor, pDpt->ExtInf.EpCount % 1000000); +} + +void TProjectSet::sRecoverSetDefault() +{ + unsigned int aAddr; + int i; + //Read ExistTable + for(i=0; i<32; i++){ + PrjName[i] = '\0'; + } + PrjName[32] = '\0'; + PrjName[33] = '\0'; + + aAddr = dEepAddrProjectName; + sDelayMs(20); + eeprom_write_byte_via_page(0, aAddr, PrjName, 32); + + sDelayMs(20); + aAddr = dEepAddrProjectName; + eeprom_read_byte(0, aAddr, PrjName, 32); +} + + + + + + + + + + + + diff --git a/MyCode/Gui/ProjectSet.h b/MyCode/Gui/ProjectSet.h new file mode 100644 index 0000000..251d5da --- /dev/null +++ b/MyCode/Gui/ProjectSet.h @@ -0,0 +1,145 @@ +#ifndef PROJECTSET_H_ +#define PROJECTSET_H_ + +#include "CtlPanel1.h" +#include "DesignPrmSet.h" + +class TProjectSet{ + public: + static constexpr unsigned short hList[12] = {36,72,72,72, 72,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 +hList[3]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 +hList[3]) + hList[4], + + .Grid.UsingCount = 5, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint InputTipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 200, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 8, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 4, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 8, + }; + public: + TDesignPrmSet *pDpt; + + u32 Color; + + class TCtlPanel1 *aPanel; + + TRect Bound; + TRect Content; + TRect RectPanel; + + TEdit vEdit; + + unsigned char CtlIndex; + unsigned char IsExtInput; + + int Sta; + + struct{ + unsigned char Inx; + void Reset(){ + Inx = 0; + } + }Tag; + int SubItemActive; + char Text[48]; + unsigned char IsPermission; + unsigned char PermissionCmd; + unsigned char IsEditting; + public: + TProjectSet(){}; + void Init(); + static void sDelayMs(unsigned int aMs); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawRecoveCnInput(); + void ShowInf(void); + void DrawFixText(); + + void DrawSelf(void); + void FullRedraw(int Prm); + void DrawCaption(void); + void Show(); + void ShowSta(); + void ShowSta(int aSta); + + void ClearSelected(void); + void Check4Selected(); + void InitPanel(); + + void LoadCfg(); + TGuiMsgReturn KeyIn(unsigned char aKey); + void Write2Eep(); + + static void sRecoverSetDefault(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void ShowDesignedCount(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/QueryCfg.cpp b/MyCode/Gui/QueryCfg.cpp new file mode 100644 index 0000000..d300c60 --- /dev/null +++ b/MyCode/Gui/QueryCfg.cpp @@ -0,0 +1,286 @@ +#include "QueryCfg.h" +#include "XBox.h" +#include "Runtime.h" + +void TQueryCfg::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + BoundCaption.SetBySize(Left,Top,Width, CH); + Content.Set(Left, Top+CH, Right, Bottom); + + BoxBoundCfg.Set(Left + 100, Top+56, Right -145, Bottom -60); + + vEditDescp.Init(BoxBoundCfg.Left +10,BoxBoundCfg.Top + 232,530,34,0,0,1,clTeal); + + vEditDescp.Str.FromStr("未设定描述信息"); + vEditDescp.Pst = vEditDescp.Str.GetEndPst(); + vEditDescp.TextColor = clNearBlack; + vEditDescp.Selected = 0; + vEditDescp.SetMaxLen(32); + + EditIndex = 0; + IsEditing = 0; + + vtValue[0] = 0; + vtValue[1] = 0; + vtValue[2] = 0; + vtValue[3] = 0; + vtValue[4] = 0; + vtValue[5] = 0; + + qType == 0 ; + + #undef CH +} + +void TQueryCfg::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clFrmFace); + + RectFillRender(BoundCaption.Left, BoundCaption.Top, BoundCaption.Right, BoundCaption.Bottom, clMaroon); + + + if(qType)TextRender_string24(BoundCaption.Left+6, BoundCaption.Top +3, clNearWhite, clMaroon, "查询->网络配置"); + else TextRender_string24(BoundCaption.Left+6, BoundCaption.Top +3, clNearWhite, clMaroon, "查询->本机配置"); +} + + +void TQueryCfg::Show(void) +{ + DrawSelf(); + if(qType == 0){ + ShowThisCfg(); + }else + if(qType == 1){ + ShowNetwork(); + } +} + +void TQueryCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + if(qType == 0){ + ShowThisCfg(); + }else + if(qType == 1){ + ShowNetwork(); + } + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], clFrmFace); + if(qType == 0){ + ShowThisCfg(); + }else + if(qType == 1){ + ShowNetwork(); + } + } +} + +void TQueryCfg::DrawThisCfgOutLine() +{ + int aLen, aW; + unsigned int aClr,aTClr; + aLen = 8; + aW = aLen * 12 +12; + + aClr = clGray; + aTClr = clNearBlack; + + + VertLineRender(BoxBoundCfg.Left, BoxBoundCfg.Top+12, BoxBoundCfg.Height-12, aClr); + VertLineRender(BoxBoundCfg.Left+1, BoxBoundCfg.Top+12, BoxBoundCfg.Height-12, aClr); + VertLineRender(BoxBoundCfg.Right, BoxBoundCfg.Top+12, BoxBoundCfg.Height-12, aClr); + VertLineRender(BoxBoundCfg.Right-1,BoxBoundCfg.Top+12, BoxBoundCfg.Height-12, aClr); + + HorizLineRender(BoxBoundCfg.Left, BoxBoundCfg.Top+12, 6, aClr); + HorizLineRender(BoxBoundCfg.Left, BoxBoundCfg.Top+12+1, 6, aClr); + HorizLineRender(BoxBoundCfg.Left, BoxBoundCfg.Bottom, BoxBoundCfg.Width, aClr); + HorizLineRender(BoxBoundCfg.Left, BoxBoundCfg.Bottom -1, BoxBoundCfg.Width, aClr); + + HorizLineRender(BoxBoundCfg.Left + aW +6, BoxBoundCfg.Top+12, BoxBoundCfg.Width -6 -aW, aClr); + HorizLineRender(BoxBoundCfg.Left + aW +6, BoxBoundCfg.Top+12+1, BoxBoundCfg.Width -6 -aW, aClr); + + TextRender_string24(BoxBoundCfg.Left + 8, BoxBoundCfg.Top, aTClr, clFrmFace, "本机配置"); +} + +void TQueryCfg::DrawThisEntry() +{ + +} + +void TQueryCfg::ShowThisCfg(void) +{ + int i, x; + int MtbCount, CirCount, BusPadCount, DirectPadCount; + RectFillRender(BoxBoundCfg.Left, BoxBoundCfg.Top, BoxBoundCfg.Right, BoxBoundCfg.Bottom, clFrmFace); + + MtbCount = 0; + CirCount = 0; + BusPadCount = 0; + DirectPadCount = 0; + for(x=0; x<5; x++){ + for(i=0; i<8; i++){ + if(MainCtl.fData.Split.ExistTablePort[x*8+i]){ + MtbCount++; + break; + } + } + } + for(i=0; i查询全部信息", Caption.Text); + else TMyString::sFromStr("Recorded Info->Query All", Caption.Text); + + Caption.Show(); + DrawCaption2(); +} + +void TQueryMsg::DrawCaption2(void) +{ + +} + +void TQueryMsg::RenderWarningWait(void) +{ + int x,y,x2,y2, aW,aH; + x = 200; + y = 160; + x2 = 600; + y2 = 290; + aW = x2 - x +1; + aH = y2 - y +1; + VertLineRender(x, y, aH-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y+1, aH -2, 0xFF808080); + VertLineRender(x2, y, aH, 0xFF404040); + + HorizLineRender(x, y, aW - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, aW - 2, 0xFF808080); + HorizLineRender(x, y2, aW, 0xFF404040); + + RectFillRender(x+1,y+1,x2-2,y+30,clNavy); + RectFillRender(x+1,y+31,x2-2,y2-2,clGray); + if(LanguageEnCn==0){ + TextRender_string24(x+8, y+6, clNearWhite, "提示信息"); + TextRender_string24(x+66, y+36, clNearBlack, "正在读取,请等待"); + }else{ + TextRender_string24(x+8, y+6, clNearWhite, "Message"); + TextRender_string24(x+66, y+36, clNearBlack, "Reading,Please Wait"); + } +} + +void TQueryMsg::DrawItemCount(int aCount) +{ + + TextDigitRender6Left24(500,Caption.Bound.Top +3, clNearWhite, Caption.Color, CountTT); + TextDigitRender6Left24(720,Caption.Bound.Top +3, clNearWhite, Caption.Color, Count); + if(LanguageEnCn==0){ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "总数量:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "查看数量:"); + }else{ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "Total:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "Display:"); + } +} + +void TQueryMsg::DrawBoxTimeOutLine() +{ + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + + VertLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Height -1, 0xFFFFFFFF); + VertLineRender(BoxBoundTime.Right -1, BoxBoundTime.Top +1, BoxBoundTime.Height -2, 0xFF808080); + VertLineRender(BoxBoundTime.Right, BoxBoundTime.Top, BoxBoundTime.Height, 0xFF404040); + + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Width - 1, 0xFFFFFFFF); + HorizLineRender(BoxBoundTime.Left +1, BoxBoundTime.Bottom -1, BoxBoundTime.Width - 2, 0xFF808080); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom, BoxBoundTime.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "设置日期时间段,按确认键开始查询"); + else TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "Set Date And Time,OK Key:Start The Query"); +} + +void TQueryMsg::DrawTimeEntry(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + vtValueFrom[0] = DateTime.Date.Split.Year; + vtValueFrom[1] = DateTime.Date.Split.Month; + vtValueFrom[2] = DateTime.Date.Split.Day; + + vtValueFrom[3] = DateTime.Time.Split.Hour; + vtValueFrom[4] = DateTime.Time.Split.Minute; + vtValueFrom[5] = DateTime.Time.Split.Second; + + vtValueTo[0] =vtValueFrom[0]; + vtValueTo[1] =vtValueFrom[1]; + vtValueTo[2] =vtValueFrom[2]; + vtValueTo[3] =vtValueFrom[3]; + vtValueTo[4] =vtValueFrom[4]; + vtValueTo[5] =vtValueFrom[5]; + + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + + +void TQueryMsg::DrawTimeEntryNoUpdate(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + +void TQueryMsg::DrawIfAllTime(void) +{ + unsigned int aClr, bClr; + if(TimeEditFrom == -1){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + if(LanguageEnCn==0){ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "全部条目"); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "按时间段"); + } + }else{ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, " All "); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "Segments"); + } + } +} + +void TQueryMsg::DrawBoxTimeString(void) +{ + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + if(LanguageEnCn==0){ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "开始时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, "年 月 日 时 分 秒"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "结束时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, "年 月 日 时 分 秒"); + }else{ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "Begin"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, " Y M D H M S"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "End"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, " Y M D H M S"); + } +} + +void TQueryMsg::DrawBoxTime(void) +{ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); +} + +void TQueryMsg::DrawGoPrintOutLine() +{ + RectFillRender(GoPrint.Left, GoPrint.Top, GoPrint.Right, GoPrint.Bottom, clFrmFace); + + VertLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Height -1, 0xFFFFFFFF); + VertLineRender(GoPrint.Right -1, GoPrint.Top +1, GoPrint.Height -2, 0xFF808080); + VertLineRender(GoPrint.Right, GoPrint.Top, GoPrint.Height, 0xFF404040); + + HorizLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Width - 1, 0xFFFFFFFF); + HorizLineRender(GoPrint.Left +1, GoPrint.Bottom -1, GoPrint.Width - 2, 0xFF808080); + HorizLineRender(GoPrint.Left, GoPrint.Bottom, GoPrint.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "按确认键开始打印并返回"); + else TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "Confirm Print Or Return"); +} + +void TQueryMsg::DrawPrintWhat() +{ + if(LanguageEnCn==0)TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "打印当前选定条目"); + else TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "Print Current Item"); + return; + if(PrintWhat == 0){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "当前选定条目"); + }else + if(PrintWhat == 1){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "当前选定条目"); + //TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 当前页面 "); + }else{ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "当前选定条目"); + //TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 全部信息 "); + } +} + +void TQueryMsg::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + DrawListAll(); + } + DrawItemCount(Count); + ShowTip(); +} + +void TQueryMsg::ReDraw(void) +{ + Caption.Enable = 1; + //DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + DrawListAll(); + } +} + +void TQueryMsg::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + DrawItemCount(Count); + ShowTip(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + ShowTip(); + } +} + +void TQueryMsg::ShowTip() +{ + if(LanguageEnCn==0){ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, TAB键去打印"); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "上下左右键切换或编辑条目, 数字键删除键编辑 "); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "按确定键打印当前条目 "); + } + }else{ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down:Switch item; TAB To Print "); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down To Switch Item To Edit; Num Key To Edit"); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "Press The OK Key To Print The Current Item "); + } + } +} + +void TQueryMsg::SetEditStart(void) +{ + int x,y,w,h; + + IsEditing =1; + + ReStoreP0 = TimeEditFrom; + ReStoreP1 = TimeIndex; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + vEdit.Init(x,y,w,h,0,0,1,clTeal); + vEdit.Color = clTeal; + vEdit.SetMaxLen(2); + if(ReStoreP0 ==0){ + vEdit.Str.Text[0] = vtTextFrom[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextFrom[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + }else + if(ReStoreP0 ==1){ + vEdit.Str.Text[0] = vtTextTo[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextTo[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + } + vEdit.Pst = -1; + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); +} + +void TQueryMsg::RestoreFromEdit(void) +{ + int x,y,w,h; + + if(IsEditing == 0)return; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + if(ReStoreP0 == 0){ + vtTextFrom[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextFrom[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextFrom[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[ReStoreP1]); + }else + if(ReStoreP0 == 1){ + vtTextTo[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextTo[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextTo[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[ReStoreP1]); + } + IsEditing = 0; +} + +void TQueryMsg::FillDescpText(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + //Fire History + Text.D32[0] = 0x20202020; + Text.D32[1] = 0x20202020; + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + Text.D32[4] = 0x20202020; + Text.D32[5] = 0x20202020; + + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=7; d<15; d++){ + Text.D32[d-1] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[14] =0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); +} + +void TQueryMsg::FillDescpTextEmpty() +{ + Text.Text[0] = ' '; + Text.Text[1] = '\0'; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); +} + +void TQueryMsg::DrawListAll(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int TextClr, bClr, Wrote; + char *p, *fp; + const char *tText; + + aInx = TopIndex; + Wrote = 0; + for(i=0;i (Count-1))break; + if(SelectedIndex != aInx){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + if(List.Inx[i] > -1){ + if(List.What[i] == 0){ + MsgFire->FillText(List.Inx[i], aInx); + p = MsgFire->Text.Text; + }else + if(List.What[i] == 1){ + MsgLinkage->FillText(List.Inx[i], aInx); + p = MsgLinkage->Text.Text; + }else + if(List.What[i] == 2){ + MsgSv->FillText(List.Inx[i], aInx); + p = MsgSv->Text.Text; + }else + if(List.What[i] == 3){ + MsgFault->FillText(List.Inx[i], aInx); + p = MsgFault->Text.Text; + }else + if(List.What[i] == 4){ + MsgOperate->FillText(List.Inx[i], aInx); + p = MsgOperate->Text.Text; + } + + TMyString::sFillFixLen(p, dLineMaxLen); + TMyString::sBrokeFixLen(p, dLineMaxLen); + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, p); + + if(List.What[i] == 0){ + MsgFire->FillDescpText(List.Inx[i]); + p = MsgFire->Text.Text; + fp =p; + fp[4] = fp[0]; + fp[5] = fp[1]; + fp[6] = fp[2]; + fp[7] = fp[3]; + if(LanguageEnCn==0)tText = sCharFire; else tText= sCharFireEn; + fp[0] = tText[0]; + fp[1] = tText[1]; + fp[2] = tText[2]; + fp[3] = tText[3]; + }else + if(List.What[i] == 1){ + MsgLinkage->FillDescpText(List.Inx[i]); + p = MsgLinkage->Text.Text; + fp =p; + fp[4] = fp[0]; + fp[5] = fp[1]; + fp[6] = fp[2]; + fp[7] = fp[3]; + if(LanguageEnCn==0)tText = sCharLinkage; else tText= sCharLinkageEn; + fp[0] = tText[0]; + fp[1] = tText[1]; + fp[2] = tText[2]; + fp[3] = tText[3]; + }else + if(List.What[i] == 2){ + MsgSv->FillDescpText(List.Inx[i]); + p = MsgSv->Text.Text; + fp =p; + fp[4] = fp[0]; + fp[5] = fp[1]; + fp[6] = fp[2]; + fp[7] = fp[3]; + if(LanguageEnCn==0)tText = sCharSv; else tText= sCharSvEn; + fp[0] = tText[0]; + fp[1] = tText[1]; + fp[2] = tText[2]; + fp[3] = tText[3]; + }else + if(List.What[i] == 3){ + MsgFault->FillDescpText(List.Inx[i]); + p = MsgFault->DescpText.Text; + fp =p; + //fp[0] = sCharFault[0]; + //fp[1] = sCharFault[1]; + //fp[2] = sCharFault[2]; + //fp[3] = sCharFault[3]; + }else + if(List.What[i] == 4){ + MsgOperate->FillDescpText(List.Inx[i]); + p = MsgOperate->Text.Text; + fp =p; + if(fp[0] == 0x20){ + if(LanguageEnCn==0)tText = sCharOpa; else tText= sCharOpaEn; + fp[0] = tText[0]; + fp[1] = tText[1]; + fp[2] = tText[2]; + fp[3] = tText[3]; + } + } + + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, p); + }else{ + Text.Text[0] = ' '; + Text.Text[1] = 0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, Color); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], clWhite, Color, Text.Text); + FillDescpTextEmpty(); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, clNearBlack, Color, Text.Text); + FillDescpTextEmpty(); + } + aInx++; + Wrote++; + } + for(i=Wrote; i-1;i--){ + aTopInx = i*2; + if(aInx > (Count-1))break; + if(SelectedIndex != aInx)bClr = Color; + else bClr = clBlue; + if(List.Inx[i] < 0){ + break; + } + if(List.What[i] == 0){ + MsgFire->FillText(List.Inx[i], aInx); + p = MsgFire->Text.Text; + }else + if(List.What[i] == 1){ + MsgLinkage->FillText(List.Inx[i], aInx); + p = MsgLinkage->Text.Text; + }else + if(List.What[i] == 2){ + MsgSv->FillText(List.Inx[i], aInx); + p = MsgSv->Text.Text; + }else + if(List.What[i] == 3){ + MsgFault->FillText(List.Inx[i], aInx); + p = MsgFault->Text.Text; + }else + if(List.What[i] == 4){ + MsgOperate->FillText(List.Inx[i], aInx); + p = MsgOperate->Text.Text; + } + + TMyString::sFillFixLen(p, dLineMaxLen); + TMyString::sBrokeFixLen(p, dLineMaxLen); + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], clNearBlack, bClr, p); + + if(List.What[i] == 0){ + MsgFire->FillDescpText(List.Inx[i]); + p = MsgFire->Text.Text; + fp =p; + fp[0] = sCharFire[0]; + fp[1] = sCharFire[1]; + fp[2] = sCharFire[2]; + fp[3] = sCharFire[3]; + }else + if(List.What[i] == 1){ + MsgLinkage->FillDescpText(List.Inx[i]); + p = MsgLinkage->Text.Text; + fp =p; + fp[0] = sCharLinkage[0]; + fp[1] = sCharLinkage[1]; + fp[2] = sCharLinkage[2]; + fp[3] = sCharLinkage[3]; + }else + if(List.What[i] == 2){ + MsgSv->FillDescpText(List.Inx[i]); + p = MsgSv->Text.Text; + fp =p; + fp[0] = sCharSv[0]; + fp[1] = sCharSv[1]; + fp[2] = sCharSv[2]; + fp[3] = sCharSv[3]; + }else + if(List.What[i] == 3){ + MsgFault->FillDescpText(List.Inx[i]); + p = MsgFault->DescpText.Text; + fp =p; + //fp[0] = sCharFault[0]; + //fp[1] = sCharFault[1]; + //fp[2] = sCharFault[2]; + //fp[3] = sCharFault[3]; + }else + if(List.What[i] == 4){ + MsgOperate->FillDescpText(List.Inx[i]); + p = MsgOperate->Text.Text; + fp =p; + fp[0] = sCharOpa[0]; + fp[1] = sCharOpa[1]; + fp[2] = sCharOpa[2]; + fp[3] = sCharOpa[3]; + } + + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, clNearBlack, bClr, p); + aInx++; + Wrote++; + } + for(i=ListLineCnt - 1 - Wrote; i>-1; i--){ + Text.Text[0] = ' '; + Text.Text[1] = 0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + aTopInx = i*2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, Color); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], clWhite, Color, Text.Text); + FillDescpTextEmpty(); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, clNearBlack, Color, Text.Text); + FillDescpTextEmpty(); + } + aInx = TopIndex; + if(aInx <0)aInx = 0; + TVScrollBar::sDrawByPoint(777, stAllTop[0], 795, stAllTop[7] + 24, clBlue , clGray , Count, 8, TopIndex);*/ +} + +void TQueryMsg::DrawListInTime(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int bClr, Wrote; + + Wrote = 0; + if(InTimeCount >0){ + i = InTimeTopIndex; + for(;i<(InTimeStopIndex+1);i++){ + if(InTimeSelectedIndex != (InTimeTopIndex + Wrote))bClr = Color; + else bClr = clBlue; + aInx = InTimeTopIndex - InTimeStartIndex + Wrote; + //FillText(i, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = Wrote *2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], clNearBlack, bClr, Text.Text); + FillDescpText(i); + TextRender_string24(DescpX0, stAllTop[aTopInx +1]-6, clNearBlack, bClr, Text.Text); + + Wrote++; + if(Wrote >= ListLineCnt){ + break; + } + } + } + for(i=Wrote; iLoadData(); + MsgLinkage->LoadData(); + MsgSv->LoadData(); + MsgFault->LoadData(); + MsgOperate->LoadData(); + + CountFire =MsgFire->Count; + CountLinkage =MsgLinkage->Count; + CountSv =MsgSv->Count; + CountFault =MsgFault->Count; + CountOperate =MsgOperate->Count; + + CountTTFire =MsgFire->Count; + CountTTLinkage =MsgLinkage->Count; + CountTTSv =MsgSv->Count; + CountTTFault =MsgFault->Count; + CountTTOperate =MsgOperate->Count; + + InxScope.End.Fire = CountFire -1; + InxScope.End.Lnk = CountLinkage -1; + InxScope.End.Sv = CountSv -1; + InxScope.End.Fault = CountFault -1; + InxScope.End.Opa = CountOperate -1; + + InxScope.Begin.Fire = 0; + InxScope.Begin.Lnk = 0; + InxScope.Begin.Sv = 0; + InxScope.Begin.Fault = 0; + InxScope.Begin.Opa = 0; + + Inx[0] = InxScope.End.Fire; + Inx[1] = InxScope.End.Lnk; + Inx[2] = InxScope.End.Sv; + Inx[3] = InxScope.End.Fault; + Inx[4] = InxScope.End.Opa; + + Count = CountFire + CountLinkage + CountSv + CountFault + CountOperate; + CountTT = Count; + + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + if(Count >0){ + SelectedIndex = Count -1; + }else{ + SelectedIndex = TopIndex; + } + + FindMsgPrv4Entries(0xFFFF'FFFF'FFFF'0000); +} + + + +unsigned long long TQueryMsg::GetLongLongInx(int What, int aInx) +{ + unsigned int Addr, SdAddr, d; + TDMix64 aLLInx; + if(What == 0){ + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + aLLInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + aLLInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + return aLLInx.D64; + }else + if(What == 1){ + Addr = Record.Buf4Linkage.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + aLLInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + aLLInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + return aLLInx.D64; + }else + if(What == 2){ + Addr = Record.Buf4Sv.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + aLLInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + aLLInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + return aLLInx.D64; + }else + if(What == 3){ + Addr = Record.Buf4Fault.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + aLLInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + aLLInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + return aLLInx.D64; + }else + if(What == 3){ + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + aLLInx.D32[0] = *(volatile unsigned int *)(SdAddr + 0); + aLLInx.D32[1] = *(volatile unsigned int *)(SdAddr + 4); + return aLLInx.D64; + } + return 1; +} + + +void TQueryMsg::LoadMsgPrv16(int What) +{ + unsigned int Addr, SdAddr; + int aInx, d; + if(What == 0){ + for(d=15; d>-1; d--){ + ListPreLoad[0].llIndex[d].D32[0] = 0; + ListPreLoad[0].llIndex[d].D32[1] = 0; + ListPreLoad[0].Inx[d] = -1; + } + if(CountFire <1)return; + aInx = Inx[0]; + for(d=15; d>-1; d--){ + if(aInx = (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[0].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[0].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[0].Inx[d] = aInx; + aInx--; + } + }else + if(What == 1){ + for(d=15; d>-1; d--){ + ListPreLoad[1].llIndex[d].D32[0] = 0; + ListPreLoad[1].llIndex[d].D32[1] = 0; + ListPreLoad[1].Inx[d] = -1; + } + if(CountLinkage <1)return; + aInx = Inx[1]; + for(d=15; d>-1; d--){ + if(aInx = (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[1].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[1].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[1].Inx[d] = aInx; + aInx--; + } + }else + if(What == 2){ + for(d=15; d>-1; d--){ + ListPreLoad[2].llIndex[d].D32[0] = 0; + ListPreLoad[2].llIndex[d].D32[1] = 0; + ListPreLoad[2].Inx[d] = -1; + } + if(CountSv <1)return; + aInx = Inx[2]; + for(d=15; d>-1; d--){ + if(aInx = (dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[2].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[2].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[2].Inx[d] = aInx; + aInx--; + } + }else + if(What == 3){ + for(d=15; d>-1; d--){ + ListPreLoad[3].llIndex[d].D32[0] = 0; + ListPreLoad[3].llIndex[d].D32[1] = 0; + ListPreLoad[3].Inx[d] = -1; + } + if(CountFault <1)return; + aInx = Inx[3]; + for(d=15; d>-1; d--){ + if(aInx = (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[3].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[3].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[3].Inx[d] = aInx; + aInx--; + } + }else + if(What == 4){ + for(d=15; d>-1; d--){ + ListPreLoad[4].llIndex[d].D32[0] = 0; + ListPreLoad[4].llIndex[d].D32[1] = 0; + ListPreLoad[4].Inx[d] = -1; + } + if(CountOperate <1)return; + aInx = Inx[4]; + for(d=15; d>-1; d--){ + if(aInx = (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[4].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[4].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[4].Inx[d] = aInx; + aInx--; + } + } +} + + +void TQueryMsg::LoadMsgFwd16(int What) +{ + unsigned int Addr, SdAddr; + int aInx, d; + if(What == 0){ + for(d=0; d<16; d++){ + ListPreLoad[0].llIndex[d].D32[0] = 0; + ListPreLoad[0].llIndex[d].D32[1] = 0; + ListPreLoad[0].Inx[d] = -1; + } + if(CountFire <1)return; + aInx = Inx[0]; + for(d=0; d<16; d++){ + if(aInx > InxScope.End.Fire)break; + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[0].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[0].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[0].Inx[d] = aInx; + aInx++; + } + }else + if(What == 1){ + for(d=0; d<16; d++){ + ListPreLoad[1].llIndex[d].D32[0] = 0; + ListPreLoad[1].llIndex[d].D32[1] = 0; + ListPreLoad[1].Inx[d] = -1; + } + if(CountLinkage <1)return; + aInx = Inx[1]; + for(d=0; d<16; d++){ + if(aInx > InxScope.End.Lnk)return; + Addr = Record.Buf4Linkage.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[1].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[1].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[1].Inx[d] = aInx; + aInx++; + } + }else + if(What == 2){ + for(d=0; d<16; d++){ + ListPreLoad[2].llIndex[d].D32[0] = 0; + ListPreLoad[2].llIndex[d].D32[1] = 0; + ListPreLoad[2].Inx[d] = -1; + } + if(CountSv <1)return; + aInx = Inx[2]; + for(d=0; d<16; d++){ + if(aInx > InxScope.End.Fault)return; + Addr = Record.Buf4Sv.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[2].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[2].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[2].Inx[d] = aInx; + aInx++; + } + }else + if(What == 3){ + for(d=0; d<16; d++){ + ListPreLoad[3].llIndex[d].D32[0] = 0; + ListPreLoad[3].llIndex[d].D32[1] = 0; + ListPreLoad[3].Inx[d] = -1; + } + if(CountFault <1)return; + aInx = Inx[3]; + for(d=0; d<16; d++){ + if(aInx > InxScope.End.Fault)return; + Addr = Record.Buf4Fault.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[3].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[3].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[3].Inx[d] = aInx; + aInx++; + } + }else + if(What == 4){ + for(d=0; d<16; d++){ + ListPreLoad[4].llIndex[d].D32[0] = 0; + ListPreLoad[4].llIndex[d].D32[1] = 0; + ListPreLoad[4].Inx[d] = -1; + } + if(CountOperate <1)return; + aInx = Inx[4]; + for(d=0; d<16; d++){ + if(aInx > InxScope.End.Opa)return; + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + ListPreLoad[4].llIndex[d].D32[0] = *(volatile unsigned int *)(SdAddr + 0); + ListPreLoad[4].llIndex[d].D32[1] = *(volatile unsigned int *)(SdAddr + 4); + ListPreLoad[4].Inx[d] = aInx; + aInx++; + } + } +} + + +void TQueryMsg::FindBigMsgPrv(unsigned long long InxLimite) +{ + int InxInt; + int i, x, z; + + MsgFound.What = 1000; + MsgFound.sInx.D64 = 0; + for(i=0; i<5; i++){ + for(x=0; x<16; x++){ + if( (ListPreLoad[i].llIndex[x].D64 > MsgFound.sInx.D64) && (ListPreLoad[i].llIndex[x].D64 < InxLimite) && (ListPreLoad[i].Inx[x] > -1) ){ + MsgFound.What = i; + MsgFound.sInx.D64 = ListPreLoad[i].llIndex[x].D64; + MsgFound.Inx = ListPreLoad[i].Inx[x]; + } + } + } + if(MsgFound.What < 5){ + Inx[MsgFound.What] = MsgFound.Inx; + } +} + +void TQueryMsg::FindMinMsgFwd(unsigned long long InxLimite) +{ + int InxInt; + int i, x, z; + + MsgFound.What = 1000; + MsgFound.sInx.D64 = 0xFFFF'FFFF'FFFF'0000; + for(i=0; i<5; i++){ + for(x=0; x<16; x++){ + if( (ListPreLoad[i].llIndex[x].D64 < MsgFound.sInx.D64) && (ListPreLoad[i].llIndex[x].D64 > InxLimite) && (ListPreLoad[i].Inx[x] > -1)){ + MsgFound.What = i; + MsgFound.sInx.D64 = ListPreLoad[i].llIndex[x].D64; + MsgFound.Inx = ListPreLoad[i].Inx[x]; + } + } + } + if(MsgFound.What < 5){ + Inx[MsgFound.What] = MsgFound.Inx; + } +} + +void TQueryMsg::FindMsgPrvEntry(unsigned long long aInxLimite) +{ + int i, x, z; + int WhatMax; + + LoadMsgPrv16(0); + LoadMsgPrv16(1); + LoadMsgPrv16(2); + LoadMsgPrv16(3); + LoadMsgPrv16(4); + + FindBigMsgPrv(aInxLimite); + + if(MsgFound.What < 5){ + for(i=3; i>0; i--){ + List.What[i] = List.What[i-1]; + List.Inx[i] = List.Inx[i-1]; + List.sInx[i].D64 = List.sInx[i-1].D64; + } + List.What[0] = MsgFound.What; + List.Inx[0] = MsgFound.Inx; + List.sInx[0].D64 = MsgFound.sInx.D64; + } + CheckFixTopIndex(); +} + +void TQueryMsg::FindMsgFwdEntry(unsigned long long aInxLimite) +{ + int i, x, z; + int WhatMax; + int Found[4][2]; + + LoadMsgFwd16(0); + LoadMsgFwd16(1); + LoadMsgFwd16(2); + LoadMsgFwd16(3); + LoadMsgFwd16(4); + + FindMinMsgFwd(aInxLimite); + + if(MsgFound.What < 5){ + for(i=0; i<3; i++){ + List.What[i] = List.What[i+1]; + List.Inx[i] = List.Inx[i+1]; + List.sInx[i].D64 = List.sInx[i+1].D64; + } + List.What[3] = MsgFound.What; + List.Inx[3] = MsgFound.Inx; + List.sInx[3].D64 = MsgFound.sInx.D64; + } + CheckFixTopIndex(); +} + +void TQueryMsg::FindMsgPrv4Entries(unsigned long long InxLimite) +{ + unsigned long long NewLimite; + int i; + + LoadMsgPrv16(0); + LoadMsgPrv16(1); + LoadMsgPrv16(2); + LoadMsgPrv16(3); + LoadMsgPrv16(4); + + NewLimite = InxLimite; + for(i=3; i>-1; i--){ + FindBigMsgPrv(NewLimite); + if(MsgFound.What <5){ + NewLimite = MsgFound.sInx.D64; + List.What[i] = MsgFound.What; + List.Inx[i] = MsgFound.Inx; + List.sInx[i].D64 = MsgFound.sInx.D64; + } + } + CheckFixTopIndex(); +} + +void TQueryMsg::FindMsgFwd4Entries(unsigned long long InxLimite) +{ + unsigned long long NewLimite; + int i; + + LoadMsgFwd16(0); + LoadMsgFwd16(1); + LoadMsgFwd16(2); + LoadMsgFwd16(3); + LoadMsgFwd16(4); + + NewLimite = InxLimite; + for(i=0; i<4; i++){ + FindMinMsgFwd(NewLimite); + if(MsgFound.What <5){ + NewLimite = MsgFound.sInx.D64; + List.What[i] = MsgFound.What; + List.Inx[i] = MsgFound.Inx; + List.sInx[i].D64 = MsgFound.sInx.D64; + } + } + CheckFixTopIndex(); +} + +void TQueryMsg::FindMsgAtStart() +{ + Inx[0] = InxScope.Begin.Fire; + Inx[1] = InxScope.Begin.Lnk; + Inx[2] = InxScope.Begin.Sv; + Inx[3] = InxScope.Begin.Fault; + Inx[4] = InxScope.Begin.Opa; + + FindMsgFwd4Entries(1); +} + +void TQueryMsg::FindMsgAtEnd() +{ + Inx[0] = InxScope.End.Fire; + Inx[1] = InxScope.End.Lnk; + Inx[2] = InxScope.End.Sv; + Inx[3] = InxScope.End.Fault; + Inx[4] = InxScope.End.Opa; + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + FindMsgPrv4Entries(0xFFFF'FFFF'FFFF'0000); +} + +void TQueryMsg::CheckFixTopIndex() +{ + int LineCnt; + if( (List.Inx[0] < 0) && (List.Inx[3] < 0) ){ + FindMsgAtEnd(); + }else + if(List.Inx[0] < 0){ + TopIndex = 0; + SelectedIndex = TopIndex; + FindMsgAtStart(); + }else + if(List.Inx[3] < 0){ + LineCnt = 3; + if(List.Inx[2] < 0)LineCnt = 2; + if(List.Inx[1] < 0)LineCnt = 1; + if(TopIndex != LineCnt){ + FindMsgAtEnd(); + } + } +} + +unsigned long long TQueryMsg::aTimeGet(int aInx) +{ + volatile unsigned int SdAddr, Addr; + + //Fire History + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + alt.D32.Low4 = *(volatile unsigned int *)(SdAddr + 12); + alt.D32.Hi2 = *(volatile unsigned int *)(SdAddr + 16); + alt.D8[6] = 0; + alt.D8[7] = 0; + return alt.D64; +} + +void TQueryMsg::GetStartStopTime() +{ + int i; + + RestoreFromEdit(); + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextFrom[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextFrom[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StartTime = alt.D64; + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextTo[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextTo[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StopTime = alt.D64; +} + +void TQueryMsg::FindInTimeEntry() +{ + int aCnt; + + MsgFire->LoadData(); + MsgLinkage->LoadData(); + MsgSv->LoadData(); + MsgFault->LoadData(); + MsgOperate->LoadData(); + + if(CountTTFire){ + MsgFire->StartTime = StartTime; + MsgFire->StopTime = StopTime; + MsgFire->FindInTimeEntry(); + + CountFire = MsgFire->InTimeCount; + InxScope.Begin.Fire = MsgFire->InTimeStartIndex; + InxScope.End.Fire = MsgFire->InTimeStopIndex; + }else{ + CountFire =0; + } + + if(CountTTLinkage){ + MsgLinkage->StartTime = StartTime; + MsgLinkage->StopTime = StopTime; + MsgLinkage->FindInTimeEntry(); + + CountLinkage = MsgLinkage->InTimeCount; + InxScope.Begin.Lnk = MsgLinkage->InTimeStartIndex; + InxScope.End.Lnk = MsgLinkage->InTimeStopIndex; + }else{ + CountLinkage =0; + } + + if(CountTTSv){ + MsgSv->StartTime = StartTime; + MsgSv->StopTime = StopTime; + MsgSv->FindInTimeEntry(); + + CountSv = MsgSv->InTimeCount; + InxScope.Begin.Sv = MsgSv->InTimeStartIndex; + InxScope.End.Sv = MsgSv->InTimeStopIndex; + }else{ + CountSv =0; + } + + if(CountTTFault){ + MsgFault->StartTime = StartTime; + MsgFault->StopTime = StopTime; + MsgFault->FindInTimeEntry(); + + CountFault = MsgFault->InTimeCount; + InxScope.Begin.Fault = MsgFault->InTimeStartIndex; + InxScope.End.Fault = MsgFault->InTimeStopIndex; + }else{ + CountFault =0; + } + + if(CountTTOperate){ + MsgOperate->StartTime = StartTime; + MsgOperate->StopTime = StopTime; + MsgOperate->FindInTimeEntry(); + + CountOperate = MsgOperate->InTimeCount; + InxScope.Begin.Opa = MsgOperate->InTimeStartIndex; + InxScope.End.Opa = MsgOperate->InTimeStopIndex; + }else{ + CountOperate =0; + } + + Count = CountFire + CountLinkage + CountSv + CountFault + CountOperate; + + Inx[0] = InxScope.End.Fire; + Inx[1] = InxScope.End.Lnk; + Inx[2] = InxScope.End.Sv; + Inx[3] = InxScope.End.Fault; + Inx[4] = InxScope.End.Opa; + + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + + FindMsgPrv4Entries(0xFFFF'FFFF'FFFF'0000); +} + + +void TQueryMsg::Go4Print(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int TextClr, bClr, Wrote; + char *p, *fp; + + aInx = TopIndex; + for(i=0;i (Count-1))break; + if(SelectedIndex == aInx){ + if(List.Inx[i] > -1){ + if(List.What[i] == 0){ + MsgFire->GetEntry4Print(List.Inx[i]); + RecordMsg.D32[0] = MsgFire->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = MsgFire->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = MsgFire->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = MsgFire->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = MsgFire->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(0, RecordMsg, &MsgFire->Text.Text[24]); + }else + if(List.What[i] == 1){ + MsgLinkage->GetEntry4Print(List.Inx[i]); + RecordMsg.D32[0] = MsgLinkage->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = MsgLinkage->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = MsgLinkage->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = MsgLinkage->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = MsgLinkage->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(1, RecordMsg, &MsgLinkage->Text.Text[24]); + }else + if(List.What[i] == 2){ + MsgSv->GetEntry4Print(List.Inx[i]); + RecordMsg.D32[0] = MsgSv->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = MsgSv->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = MsgSv->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = MsgSv->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = MsgSv->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(2, RecordMsg, &MsgSv->Text.Text[24]); + }else + if(List.What[i] == 3){ + MsgFault->GetEntry4Print(List.Inx[i]); + RecordMsg.D32[0] = MsgFault->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = MsgFault->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = MsgFault->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = MsgFault->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = MsgFault->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(3, RecordMsg, &MsgFault->DescpText.Text[28]); + }else + if(List.What[i] == 4){ + MsgOperate->GetEntry4Print(List.Inx[i]); + RecordMsg.D32[0] = MsgOperate->EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = MsgOperate->EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = MsgOperate->EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = MsgOperate->EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = MsgOperate->EntryTmp.fData.UserCode; + DoPrint.PrintHistory(4, RecordMsg, &MsgOperate->Text.Text[28]); + } + } + } + aInx++; + } +} + +TGuiMsgReturn TQueryMsg::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = TopIndex -ListLineCnt; + if(aIndex > -1){ + TopIndex = aIndex; + SelectedIndex -= ListLineCnt; + FindMsgPrv4Entries(List.sInx[0].D64); + }else{ + if(TopIndex > 0){ + TopIndex = 0; + SelectedIndex = TopIndex; + FindMsgAtStart(); + }else{ + FindMsgAtEnd(); + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = TopIndex +ListLineCnt; + if(aIndex < Count){ + TopIndex = aIndex; + SelectedIndex += ListLineCnt; + if(SelectedIndex >= Count){ + SelectedIndex = Count-1; + } + FindMsgFwd4Entries(List.sInx[3].D64); + }else{ + TopIndex = 0; + SelectedIndex = TopIndex; + FindMsgAtStart(); + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = SelectedIndex -1; + if(aIndex > -1){ + SelectedIndex = aIndex; + if(SelectedIndex < TopIndex){ + TopIndex = SelectedIndex; + FindMsgPrvEntry(List.sInx[0].D64); + } + }else{ + FindMsgAtEnd(); + } + ReDraw(); + }else + if(VK_DOWN == aKey){ + aIndex = SelectedIndex +1; + if(aIndex < Count){ + SelectedIndex = aIndex; + if(SelectedIndex > (TopIndex + ListLineCnt -1) ){ + TopIndex++; + FindMsgFwdEntry(List.sInx[3].D64); + } + }else{ + TopIndex = 0; + SelectedIndex = 0; + FindMsgAtStart(); + } + ReDraw(); + }else + if(aKey == VK_F1 ){ + //Setup Device Property + //IsInputTime = 1; + //IsAllTimeTemp = IsAllTime; + //DrawBoxTimeOutLine(); + //DrawBoxTimeString(); + //DrawIfAllTime(); + //DrawTimeEntry(); + //ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + + if(IsInputTime){ + if(aKey == VK_UP){ + if(TimeEditFrom >0){ + RestoreFromEdit(); + TimeEditFrom =0; + SetEditStart(); + }else{ + if(TimeEditFrom > -1){ + RestoreFromEdit(); + TimeEditFrom = -1; + DrawIfAllTime(); + } + } + }else + if(aKey == VK_DOWN){ + if(TimeEditFrom <1){ + if(IsAllTimeTemp == 0){ + if(TimeEditFrom == 0)RestoreFromEdit(); + TimeEditFrom ++; + SetEditStart(); + DrawIfAllTime(); + } + } + }else + if(aKey == VK_LEFT){ + if(TimeEditFrom > -1){ + if(TimeIndex >0){ + RestoreFromEdit(); + TimeIndex--; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_RIGHT){ + if(TimeEditFrom > -1){ + if(TimeIndex <5){ + RestoreFromEdit(); + TimeIndex++; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_EXECUTE){ + //Read Here + if(IsAllTimeTemp){ + IsAllTime = IsAllTimeTemp; + LoadData(); + DrawItemCount(Count); + ReDraw(); + }else{ + IsAllTime = IsAllTimeTemp; + GetStartStopTime(); + FindInTimeEntry(); + DrawItemCount(Count); + IsInputTime = 0; + RenderContent(); + ReDraw(); + } + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsInputTime = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else{ + if(IsAllTimeTemp == 0){ + if(IsEditing){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + } + } + } + + if(IsGoPrint){ + if(aKey == VK_LEFT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_RIGHT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_EXECUTE){ + //Print Here + Go4Print(); + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + } + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TQueryMsg::Task1000Ms() +{ + if(IsShowing){ + if(Count != Record.Buf4Fire.Count){ + TopIndex = Count - ListLineCnt +1; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } +} + +int TQueryMsg::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} diff --git a/MyCode/Gui/QueryMessage.h b/MyCode/Gui/QueryMessage.h new file mode 100644 index 0000000..f3cdec0 --- /dev/null +++ b/MyCode/Gui/QueryMessage.h @@ -0,0 +1,1084 @@ +#ifndef QUERYMESSAGE_H_ +#define QUERYMESSAGE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "ProtoFecBus.h" + +typedef struct{ + int What; + int Inx; + TDMix64 sInx; +}TMsgFoundInf; + +//For Message View +class TQueryMessageFire{ + public: + int TopIndex; + int SelectedIndex; + int Count; + int IsShowing; + int NeedDisplayDescp; + int IsFirst; + + int InTimeStartIndex; + int InTimeStopIndex; + int InTimeCount; + int InTimeTopIndex; + int InTimeSelectedIndex; + int InTimeList[8]; + unsigned long long StartTime; + unsigned long long StopTime; + + union{ + unsigned long long D64; + unsigned char D8[8]; + struct{ + unsigned int Low4; + unsigned int Hi2; + }D32; + }alt; + public: + TStaticText Caption; + int ActiveLineNum; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect BoxBoundTime; + TRect Content; + TRect GoPrint; + + unsigned char vtValueFrom[8]; + unsigned char vtValueTo[8]; + unsigned char vtTextFrom[6][4]; + unsigned char vtTextTo[6][4]; + char vtTextCount[8]; + int IsInputTime; + int IsAllTime; + int IsAllTimeTemp; + int TimeEditFrom; + int TimeIndex; + int IsEditing; + int ReStoreP0; + int ReStoreP1; + int IsGoPrint; + int PrintWhat; + + TRecordEntry EntryTmp; + TRecordCommon RecordMsg; + + union{ + unsigned int D32[16]; + char Text[64]; + }Text, DescpText; + + TDateTimeBytes DateTimeCovered; + class TEdit vEdit; + + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath0Item(TRootDevice *pItem); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TQueryMessageFire(){}; + TQueryMessageFire(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void InitBackEnd(); + void LoadData(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixCol(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawItemCount(int aCount); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + void RenderContent(void); + void RenderWarningWait(void); + + void DrawBoxTimeOutLine(); + void DrawIfAllTime(); + void DrawTimeEntry(void); + void DrawTimeEntryNoUpdate(); + void DrawBoxTime(void); + void DrawBoxTimeString(void); + + void ShowTip(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + void DrawListAll(void); + void DrawListInTime(void); + + void SetShowAllMsg(void); + void SetShowFireMsg(void); + void SetShowLinkage(); + void SetShowFaultMsg(void); + void SetShowOperate(void); + void SetSuperVs(void); + + void LoadPrv(void); + void LoadFroward(void); + + void SetEditStart(void); + void RestoreFromEdit(void); + + void DrawGoPrintOutLine(); + void DrawPrintWhat(); + + int FillText(int aInx, int ShowInx); + void FillDescpText(int aInx); + void FillDescpTextEmpty(); + void GetStartStopTime(); + void FindInTimeEntry(); + unsigned long long aTimeGet(int aInx); + + void GetEntry4Print(int aInx); + void AddOnUserCode(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); +}; + + + + +//For Message View +class TQueryMsgLinkage{ + public: + int TopIndex; + int SelectedIndex; + int Count; + int IsShowing; + int NeedDisplayDescp; + + int InTimeStartIndex; + int InTimeStopIndex; + int InTimeCount; + int InTimeTopIndex; + int InTimeSelectedIndex; + int InTimeList[8]; + unsigned long long StartTime; + unsigned long long StopTime; + + union{ + unsigned long long D64; + unsigned char D8[8]; + struct{ + unsigned int Low4; + unsigned int Hi2; + }D32; + }alt; + public: + TStaticText Caption; + int ActiveLineNum; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect BoxBoundTime; + TRect Content; + TRect GoPrint; + + unsigned char vtValueFrom[8]; + unsigned char vtValueTo[8]; + unsigned char vtTextFrom[6][4]; + unsigned char vtTextTo[6][4]; + char vtTextCount[8]; + int IsInputTime; + int IsAllTime; + int IsAllTimeTemp; + int TimeEditFrom; + int TimeIndex; + int IsEditing; + int ReStoreP0; + int ReStoreP1; + int IsGoPrint; + int PrintWhat; + + TRecordEntry EntryTmp; + TRecordCommon RecordMsg; + + union{ + unsigned int D32[16]; + char Text[64]; + }Text, DescpText; + + TDateTimeBytes DateTimeCovered; + + class TEdit vEdit; + + unsigned char IsSimulate; + + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath0Item(TRootDevice *pItem); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TQueryMsgLinkage(){}; + TQueryMsgLinkage(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void InitBackEnd(); + void LoadData(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixCol(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawItemCount(int aCount); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + void RenderContent(void); + void RenderWarningWait(void); + + void DrawBoxTimeOutLine(); + void DrawIfAllTime(); + void DrawTimeEntry(void); + void DrawTimeEntryNoUpdate(); + void DrawBoxTime(void); + void DrawBoxTimeString(void); + + void ShowTip(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + void DrawListAll(void); + void DrawListInTime(void); + + void SetShowAllMsg(void); + void SetShowFireMsg(void); + void SetShowLinkage(); + void SetShowFaultMsg(void); + void SetShowOperate(void); + void SetSuperVs(void); + + void LoadPrv(void); + void LoadFroward(void); + + void SetEditStart(void); + void RestoreFromEdit(void); + + void DrawGoPrintOutLine(); + void DrawPrintWhat(); + + int FillText(int aInx, int ShowInx); + void FillDescpText(int aInx); + void FillDescpTextEmpty(); + void GetStartStopTime(); + void FindInTimeEntry(); + unsigned long long aTimeGet(int aInx); + + void GetEntry4Print(int aInx); + void AddOnUserCode(); + + void Task1000Ms(); + + + int ExtRequst(unsigned char Prm); +}; + + + + +//For Message View +class TQueryMsgSv{ + public: + int TopIndex; + int SelectedIndex; + int Count; + int IsShowing; + int NeedDisplayDescp; + + int InTimeStartIndex; + int InTimeStopIndex; + int InTimeCount; + int InTimeTopIndex; + int InTimeSelectedIndex; + int InTimeList[8]; + unsigned long long StartTime; + unsigned long long StopTime; + + union{ + unsigned long long D64; + unsigned char D8[8]; + struct{ + unsigned int Low4; + unsigned int Hi2; + }D32; + }alt; + public: + TStaticText Caption; + int ActiveLineNum; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect BoxBoundTime; + TRect Content; + TRect GoPrint; + + unsigned char vtValueFrom[8]; + unsigned char vtValueTo[8]; + unsigned char vtTextFrom[6][4]; + unsigned char vtTextTo[6][4]; + char vtTextCount[8]; + int IsInputTime; + int IsAllTime; + int IsAllTimeTemp; + int TimeEditFrom; + int TimeIndex; + int IsEditing; + int ReStoreP0; + int ReStoreP1; + int IsGoPrint; + int PrintWhat; + + TRecordEntry EntryTmp; + TRecordCommon RecordMsg; + + union{ + unsigned int D32[16]; + char Text[64]; + }Text; + TDateTimeBytes DateTimeCovered; + + class TEdit vEdit; + + unsigned char IsSimulate; + + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath0Item(TRootDevice *pItem); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TQueryMsgSv(){}; + TQueryMsgSv(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void InitBackEnd(); + void LoadData(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixCol(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawItemCount(int aCount); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + void RenderContent(void); + void RenderWarningWait(void); + + void DrawBoxTimeOutLine(); + void DrawIfAllTime(); + void DrawTimeEntry(void); + void DrawTimeEntryNoUpdate(); + void DrawBoxTime(void); + void DrawBoxTimeString(void); + + void ShowTip(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + void DrawListAll(void); + void DrawListInTime(void); + + void SetShowAllMsg(void); + void SetShowFireMsg(void); + void SetShowLinkage(); + void SetShowFaultMsg(void); + void SetShowOperate(void); + void SetSuperVs(void); + + void LoadPrv(void); + void LoadFroward(void); + + void SetEditStart(void); + void RestoreFromEdit(void); + + void DrawGoPrintOutLine(); + void DrawPrintWhat(); + + int FillText(int aInx, int ShowInx); + void FillDescpText(int aInx); + void FillDescpTextEmpty(); + void GetStartStopTime(); + void FindInTimeEntry(); + unsigned long long aTimeGet(int aInx); + + void GetEntry4Print(int aInx); + void AddOnUserCode(); + + void Task1000Ms(); + + + int ExtRequst(unsigned char Prm); +}; + + + +//For Message View +class TQueryMsgFault{ + public: + int TopIndex; + int SelectedIndex; + int Count; + int IsShowing; + int NeedDisplayDescp; + + int InTimeStartIndex; + int InTimeStopIndex; + int InTimeCount; + int InTimeTopIndex; + int InTimeSelectedIndex; + int InTimeList[8]; + unsigned long long StartTime; + unsigned long long StopTime; + + union{ + unsigned long long D64; + unsigned char D8[8]; + struct{ + unsigned int Low4; + unsigned int Hi2; + }D32; + }alt; + public: + TStaticText Caption; + int ActiveLineNum; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect BoxBoundTime; + TRect Content; + TRect GoPrint; + + unsigned char vtValueFrom[8]; + unsigned char vtValueTo[8]; + unsigned char vtTextFrom[6][4]; + unsigned char vtTextTo[6][4]; + char vtTextCount[8]; + int IsInputTime; + int IsAllTime; + int IsAllTimeTemp; + int TimeEditFrom; + int TimeIndex; + int IsEditing; + int ReStoreP0; + int ReStoreP1; + int IsGoPrint; + int PrintWhat; + + TRecordEntry EntryTmp; + TRecordCommon RecordMsg; + + union{ + unsigned int D32[17]; + char Text[68]; + }Text, DescpText; + TDateTimeBytes DateTimeCovered; + + class TEdit vEdit; + + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath0Item(TRootDevice *pItem); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TQueryMsgFault(){}; + TQueryMsgFault(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void InitBackEnd(); + void LoadData(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixCol(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawItemCount(int aCount); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + void RenderContent(void); + void RenderWarningWait(void); + + void DrawBoxTimeOutLine(); + void DrawIfAllTime(); + void DrawTimeEntry(void); + void DrawTimeEntryNoUpdate(); + void DrawBoxTime(void); + void DrawBoxTimeString(void); + + void ShowTip(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + void DrawListAll(void); + void DrawListInTime(void); + + void SetShowAllMsg(void); + void SetShowFireMsg(void); + void SetShowLinkage(); + void SetShowFaultMsg(void); + void SetShowOperate(void); + void SetSuperVs(void); + + void LoadPrv(void); + void LoadFroward(void); + + void SetEditStart(void); + void RestoreFromEdit(void); + + void DrawGoPrintOutLine(); + void DrawPrintWhat(); + + int FillText(int aInx, int ShowInx); + void FillDescpText(int aInx); + void FillDescpTextEmpty(); + void GetStartStopTime(); + void FindInTimeEntry(); + unsigned long long aTimeGet(int aInx); + + void GetEntry4Print(int aInx); + + void Task1000Ms(); + + + int ExtRequst(unsigned char Prm); +}; + + +//For Message View +class TQueryMsgOperate{ + public: + int TopIndex; + int SelectedIndex; + int Count; + int IsShowing; + int NeedDisplayDescp; + int NeedDrawCfg; + + int InTimeStartIndex; + int InTimeStopIndex; + int InTimeCount; + int InTimeTopIndex; + int InTimeSelectedIndex; + int InTimeList[8]; + unsigned long long StartTime; + unsigned long long StopTime; + + union{ + unsigned long long D64; + unsigned char D8[8]; + struct{ + unsigned int Low4; + unsigned int Hi2; + }D32; + }alt; + public: + TStaticText Caption; + int ActiveLineNum; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect BoxBoundTime; + TRect Content; + TRect GoPrint; + + unsigned char vtValueFrom[8]; + unsigned char vtValueTo[8]; + unsigned char vtTextFrom[6][4]; + unsigned char vtTextTo[6][4]; + char vtTextCount[8]; + int IsInputTime; + int IsAllTime; + int IsAllTimeTemp; + int TimeEditFrom; + int TimeIndex; + int IsEditing; + int ReStoreP0; + int ReStoreP1; + int IsGoPrint; + int PrintWhat; + + TRecordEntry EntryTmp; + TRecordCommon RecordMsg; + + union{ + unsigned int D32[16]; + char Text[64]; + }Text; + + TDateTimeBytes DateTimeCovered; + class TEdit vEdit; + + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath0Item(TRootDevice *pItem); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TQueryMsgOperate(){}; + TQueryMsgOperate(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void InitBackEnd(); + void LoadData(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixCol(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawItemCount(int aCount); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + void RenderContent(void); + void RenderWarningWait(void); + + void DrawBoxTimeOutLine(); + void DrawIfAllTime(); + void DrawTimeEntry(void); + void DrawTimeEntryNoUpdate(); + void DrawBoxTime(void); + void DrawBoxTimeString(void); + + void ShowTip(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + void DrawListAll(void); + void DrawListInTime(void); + + void SetShowAllMsg(void); + void SetShowFireMsg(void); + void SetShowLinkage(); + void SetShowFaultMsg(void); + void SetShowOperate(void); + void SetSuperVs(void); + + void LoadPrv(void); + void LoadFroward(void); + + void SetEditStart(void); + void RestoreFromEdit(void); + + void DrawGoPrintOutLine(); + void DrawPrintWhat(); + + void FillCtlNum(); + void FillCtlNumNoSpace(); + void FillTextWithDateTime(); + void FillTextWithPath(); + void FillTextWithDType(); + + void FillText4PowerOff(); + void FillText4PowerUp(); + void FillText4MsgReset(unsigned char Data1); + void FillText4MsgMute(); + void FillText4AllowSet(); + void FillText4MsgMask(); + void FillText4MsgUnMask(); + void FillText4AlramSetOnOff(); + void FillText4BusPadOn(); + void FillText4BusPadOff(); + void FillText4DirectPadManualAllowOn(); + void FillText4DirectPadManualAllowOff(); + void FillText4DirectPadNodeOn(); + void FillText4DirectPadNodeOff(); + void FillText4UserCheck(); + void FillText4LinkageGo(unsigned char Data1); + + void FillText4MsgDateTimeSet(); + void AddOnFireMsg(); + void AddOnFaultMsg(); + + int FillTextCN(int aInx, int ShowInx); + int FillTextEN(int aInx, int ShowInx); + int FillText(int aInx, int ShowInx); + void FillDescpText(int aInx); + void FillDescpTextEmpty(); + void GetStartStopTime(); + void FindInTimeEntry(); + unsigned long long aTimeGet(int aInx); + + void GetEntry4Print(int aInx); + void AddOnUserCode(); + + void Task1000Ms(); + + + int ExtRequst(unsigned char Prm); +}; + +//For Message View +class TQueryMsg{ + public: + TQueryMessageFire *MsgFire; + TQueryMsgLinkage *MsgLinkage; + TQueryMsgSv *MsgSv; + TQueryMsgFault *MsgFault; + TQueryMsgOperate *MsgOperate; + + int MsgWhat; + + TMsgFoundInf MsgFound; + + struct{ + unsigned char What[8]; + int Inx[5]; + TDMix64 sInx[5]; + }List; + + struct{ + int Inx[16]; + TDMix64 llIndex[16]; + }ListPreLoad[5]; + + int Inx[5]; + + struct{ + struct{ + int Fire; + int Lnk; + int Sv; + int Fault; + int Opa; + }Begin,End; + }InxScope; + + int TopIndex; + int SelectedIndex; + + int CountTT; + int CountTTFire; + int CountTTLinkage; + int CountTTSv; + int CountTTFault; + int CountTTOperate; + + int Count; + int CountFire; + int CountLinkage; + int CountSv; + int CountFault; + int CountOperate; + + int IsShowing; + int NeedDisplayDescp; + + int InTimeStartIndex; + int InTimeStopIndex; + int InTimeCount; + int InTimeTopIndex; + int InTimeSelectedIndex; + int InTimeList[8]; + unsigned long long StartTime; + unsigned long long StopTime; + + union{ + unsigned long long D64; + unsigned char D8[8]; + struct{ + unsigned int Low4; + unsigned int Hi2; + }D32; + }alt; + public: + TStaticText Caption; + int ActiveLineNum; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect BoxBoundTime; + TRect Content; + TRect GoPrint; + + unsigned char vtValueFrom[8]; + unsigned char vtValueTo[8]; + unsigned char vtTextFrom[6][4]; + unsigned char vtTextTo[6][4]; + char vtTextCount[8]; + int IsInputTime; + int IsAllTime; + int IsAllTimeTemp; + int TimeEditFrom; + int TimeIndex; + int IsEditing; + int ReStoreP0; + int ReStoreP1; + int IsGoPrint; + int PrintWhat; + + TRecordEntry EntryTmp; + TRecordCommon RecordMsg; + + union{ + unsigned int D32[16]; + char Text[64]; + }Text; + class TEdit vEdit; + + private: + void CalcIconDrawPrm(void); + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath0Item(TRootDevice *pItem); + void LoadPath1Item(TEpDevice *pItem); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TQueryMsg(){}; + TQueryMsg(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void LoadData(); + + void InitBackEnd(); + + unsigned long long GetLongLongInx(int What, int aInx); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixCol(void); + void DrawVertScrollBar(void); + void DrawShortList(void); + void DrawItemCount(int aCount); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void DrawCaption2(void); + void RenderContent(void); + void RenderWarningWait(void); + + void DrawBoxTimeOutLine(); + void DrawIfAllTime(); + void DrawTimeEntry(void); + void DrawTimeEntryNoUpdate(); + void DrawBoxTime(void); + void DrawBoxTimeString(void); + + void ShowTip(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void FullRePaint(void); + void RePaint(void); + void FullRedraw(int Prm); + + void LoadMsgPrv16(int What); + void LoadMsgFwd16(int What); + void FindBigMsgPrv(unsigned long long InxLimite); + void FindMinMsgFwd(unsigned long long InxLimite); + void FindMsgPrvEntry(unsigned long long InxLimite); + void FindMsgFwdEntry(unsigned long long aInxLimite); + void FindMsgPrv4Entries(unsigned long long InxLimite); + void FindMsgFwd4Entries(unsigned long long InxLimite); + void FindLastMsg(); + void FindList(); + void FindMsgAtStart(); + void FindMsgAtEnd(); + void CheckFixTopIndex(); + + void DrawListAll(void); + void DrawListAllUp(void); + void DrawListInTime(void); + + void SetShowAllMsg(void); + void SetShowFireMsg(void); + void SetShowLinkage(); + void SetShowFaultMsg(void); + void SetShowOperate(void); + void SetSuperVs(void); + + void LoadPrv(void); + void LoadFroward(void); + + void SetEditStart(void); + void RestoreFromEdit(void); + + void DrawGoPrintOutLine(); + void DrawPrintWhat(); + + int FillText(int aInx, int ShowInx); + void FillDescpText(int aInx); + void FillDescpTextEmpty(); + void GetStartStopTime(); + void FindInTimeEntry(); + unsigned long long aTimeGet(int aInx); + + void Go4Print(void); + + void Task1000Ms(); + + + int ExtRequst(unsigned char Prm); +}; + + + + + + + + + + + +#endif + + + + + diff --git a/MyCode/Gui/QueryMessageFire.cpp b/MyCode/Gui/QueryMessageFire.cpp new file mode 100644 index 0000000..c11e556 --- /dev/null +++ b/MyCode/Gui/QueryMessageFire.cpp @@ -0,0 +1,1362 @@ +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "QueryMessage.h" + +#define TextTopOffSet 6 +#define ListLineCnt 4 +#define ColHeight 33 + +#define FixTop 69 +#define MsgX0 6 +#define DescpX0 270 //90 + +#define dLineMaxLen 64 + +const static unsigned short stAllTop[10] = { + 80, 120, 160, 200, 240, + 280, 320, 360, 400, 440 +}; + +static const short qmFixCol[8] = { + 20,100,160,240, 320,400,520,600 +}; + +void TQueryMessageFire::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + BoxBoundTime.Set(Left+170, Top+80, Right-170, Bottom-30); + GoPrint.Set(Left+170, Top+150, Right-170, Bottom-130); + Color = aColor; + #undef CH + + + Caption.Border.Color = clGray; + + FixColColor = clMaroon; + FixColTextColor = clNearWhite; + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; +} + +void TQueryMessageFire::InitBackEnd() +{ + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; +} + +void TQueryMessageFire::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8) +{ + +} + +void TQueryMessageFire::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMessageFire::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TQueryMessageFire::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMessageFire::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TQueryMessageFire::DrawCaption(void) +{ + if(LanguageEnCn==0)TMyString::sFromStr("历史记录->查询火警信息", Caption.Text); + else TMyString::sFromStr("Recorded Info->Query Fire Alarm", Caption.Text); + + Caption.Show(); + DrawCaption2(); +} + +void TQueryMessageFire::DrawCaption2(void) +{ + +} + +void TQueryMessageFire::RenderWarningWait(void) +{ + int x,y,x2,y2, aW,aH; + x = 200; + y = 160; + x2 = 600; + y2 = 290; + aW = x2 - x +1; + aH = y2 - y +1; + VertLineRender(x, y, aH-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y+1, aH -2, 0xFF808080); + VertLineRender(x2, y, aH, 0xFF404040); + + HorizLineRender(x, y, aW - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, aW - 2, 0xFF808080); + HorizLineRender(x, y2, aW, 0xFF404040); + + RectFillRender(x+1,y+1,x2-2,y+30,clNavy); + RectFillRender(x+1,y+31,x2-2,y2-2,clGray); + if(LanguageEnCn==0){ + TextRender_string24(x+8, y+6, clNearWhite, "提示信息"); + TextRender_string24(x+66, y+36, clNearBlack, "正在读取,请等待"); + }else{ + TextRender_string24(x+8, y+6, clNearWhite, "Message"); + TextRender_string24(x+66, y+36, clNearBlack, "Reading,Please Wait"); + } +} + +void TQueryMessageFire::DrawItemCount(int aCount) +{ + + TextDigitRender6Left24(500,Caption.Bound.Top +3, clNearWhite, Caption.Color, Count); + TextDigitRender6Left24(720,Caption.Bound.Top +3, clNearWhite, Caption.Color, aCount); + if(LanguageEnCn==0){ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "总数量:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "查看数量:"); + }else{ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "Total:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "Display:"); + } +} + +void TQueryMessageFire::DrawBoxTimeOutLine() +{ + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + + VertLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Height -1, 0xFFFFFFFF); + VertLineRender(BoxBoundTime.Right -1, BoxBoundTime.Top +1, BoxBoundTime.Height -2, 0xFF808080); + VertLineRender(BoxBoundTime.Right, BoxBoundTime.Top, BoxBoundTime.Height, 0xFF404040); + + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Width - 1, 0xFFFFFFFF); + HorizLineRender(BoxBoundTime.Left +1, BoxBoundTime.Bottom -1, BoxBoundTime.Width - 2, 0xFF808080); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom, BoxBoundTime.Width, 0xFF404040); + + if(LanguageEnCn==0) TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "设置日期时间段,按确认键开始查询"); + else TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "Set Date And Time,OK Key:Start The Query"); +} + +void TQueryMessageFire::DrawTimeEntry(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + vtValueFrom[0] = DateTime.Date.Split.Year; + vtValueFrom[1] = DateTime.Date.Split.Month; + vtValueFrom[2] = DateTime.Date.Split.Day; + + vtValueFrom[3] = DateTime.Time.Split.Hour; + vtValueFrom[4] = DateTime.Time.Split.Minute; + vtValueFrom[5] = DateTime.Time.Split.Second; + + vtValueTo[0] =vtValueFrom[0]; + vtValueTo[1] =vtValueFrom[1]; + vtValueTo[2] =vtValueFrom[2]; + vtValueTo[3] =vtValueFrom[3]; + vtValueTo[4] =vtValueFrom[4]; + vtValueTo[5] =vtValueFrom[5]; + + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + +void TQueryMessageFire::DrawTimeEntryNoUpdate(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + +void TQueryMessageFire::DrawIfAllTime(void) +{ + unsigned int aClr, bClr; + if(TimeEditFrom == -1){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + TTriangleLeftRight::sDrawLeftByHight(BoxBoundTime.Left + 150 - 20, BoxBoundTime.Top + 44, 20, clBlue); + TTriangleLeftRight::sDrawRightByHight(BoxBoundTime.Left + 150 + 106, BoxBoundTime.Top + 44, 20, clBlue); + if(LanguageEnCn==0){ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "全部条目"); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "按时间段"); + } + }else{ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, " All "); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "Segments"); + } + } +} + +void TQueryMessageFire::DrawBoxTimeString(void) +{ + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + if(LanguageEnCn==0){ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "开始时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, "年 月 日 时 分 秒"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "结束时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, "年 月 日 时 分 秒"); + }else{ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "Begin"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, " Y M D H M S"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "End"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, " Y M D H M S"); + } +} + +void TQueryMessageFire::DrawBoxTime(void) +{ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); +} + +void TQueryMessageFire::DrawGoPrintOutLine() +{ + RectFillRender(GoPrint.Left, GoPrint.Top, GoPrint.Right, GoPrint.Bottom, clFrmFace); + + VertLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Height -1, 0xFFFFFFFF); + VertLineRender(GoPrint.Right -1, GoPrint.Top +1, GoPrint.Height -2, 0xFF808080); + VertLineRender(GoPrint.Right, GoPrint.Top, GoPrint.Height, 0xFF404040); + + HorizLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Width - 1, 0xFFFFFFFF); + HorizLineRender(GoPrint.Left +1, GoPrint.Bottom -1, GoPrint.Width - 2, 0xFF808080); + HorizLineRender(GoPrint.Left, GoPrint.Bottom, GoPrint.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "按确认键开始打印并返回"); + else TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "Confirm Print Or Return"); +} + +void TQueryMessageFire::DrawPrintWhat() +{ + if(LanguageEnCn==0)TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "打印当前选定条目"); + else TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "Print Current Item"); + return; + if(PrintWhat == 0){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, "当前选定条目"); + }else + if(PrintWhat == 1){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 当前页面 "); + }else{ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 全部信息 "); + } +} + +void TQueryMessageFire::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } + DrawItemCount(Count); + ShowTip(); +} + +void TQueryMessageFire::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + DrawItemCount(Count); + ShowTip(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + ShowTip(); + } +} + + + +void TQueryMessageFire::ReDraw(void) +{ + Caption.Enable = 1; + //DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } +} + +void TQueryMessageFire::ShowTip() +{ + if(LanguageEnCn==0){ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, TAB键去打印"); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "上下左右键切换或编辑条目, 数字键删除键编辑 "); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "按确定键打印当前条目 "); + } + }else{ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down:Switch item; TAB To Print "); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down To Switch Item To Edit; Num Key To Edit"); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "Press The OK Key To Print The Current Item "); + } + } +} + +void TQueryMessageFire::SetEditStart(void) +{ + int x,y,w,h; + + IsEditing =1; + + ReStoreP0 = TimeEditFrom; + ReStoreP1 = TimeIndex; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + vEdit.Init(x,y,w,h,0,0,1,clTeal); + vEdit.Color = clTeal; + vEdit.SetMaxLen(2); + if(ReStoreP0 ==0){ + vEdit.Str.Text[0] = vtTextFrom[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextFrom[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + }else + if(ReStoreP0 ==1){ + vEdit.Str.Text[0] = vtTextTo[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextTo[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + } + vEdit.Pst = -1; + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); +} + +void TQueryMessageFire::RestoreFromEdit(void) +{ + int x,y,w,h; + + if(IsEditing == 0)return; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + if(ReStoreP0 == 0){ + vtTextFrom[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextFrom[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextFrom[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[ReStoreP1]); + }else + if(ReStoreP0 == 1){ + vtTextTo[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextTo[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextTo[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[ReStoreP1]); + } + IsEditing = 0; +} + +void TQueryMessageFire::AddOnUserCode() +{ + TMyString::sAddOn8Dg(EntryTmp.fData.UserCode, Text.Text); +} + +int TQueryMessageFire::FillText(int aInx, int ShowInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + //Fire History + NeedDisplayDescp = 0; + + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=2; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + CoverDateTimeIllegal(EntryTmp.fData.Body, &DateTimeCovered); + Text.Text[7] = DateTimeCovered.Year / 16 % 10 + '0'; + Text.Text[8] = DateTimeCovered.Year % 16 % 10 + '0'; + Text.Text[9] = '/'; + Text.Text[10] = DateTimeCovered.Month / 16 % 10 + '0'; + Text.Text[11] = DateTimeCovered.Month % 16 % 10 + '0'; + Text.Text[12] = '/'; + Text.Text[13] = DateTimeCovered.Day / 16 % 10 + '0'; + Text.Text[14] = DateTimeCovered.Day % 16 % 10 + '0'; + Text.Text[15] = ' '; + Text.Text[16] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text.Text[17] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text.Text[18] = ':'; + Text.Text[19] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text.Text[20] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text.Text[21] = ':'; + Text.Text[22] = DateTimeCovered.Second / 16 % 10 + '0'; + Text.Text[23] = DateTimeCovered.Second % 16 % 10 + '0'; + Text.Text[24] = ' '; + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + Text.Text[25] = e + '0'; + e = data % 10; + Text.Text[26] = e + '0'; + Text.Text[27] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + Text.Text[28] = e + '0'; + e = data % 10; + Text.Text[29] = e + '0'; + Text.Text[30] = '-'; + + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + Text.Text[31] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[32] = e + '0'; + e = data % 10; + Text.Text[33] = e + '0'; + Text.Text[34] = ' '; + Text.Text[35] = '\0'; + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + AddOnUserCode(); + TMyString::sAddOnStr(" ",Text.Text); + + if( (aP0) && (aP0<=dPORT_MAX_COUNT) ){ + NeedDisplayDescp = 1; + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && ( aP0 <= dADDR_DIRECTPAD_END)){ + NeedDisplayDescp = 1; + } + + if(EntryTmp.fData.Body.Splite.Data1){ + IsFirst = 1; + }else{ + IsFirst = 0; + } + + return NeedDisplayDescp; +} + + +void TQueryMessageFire::FillDescpText(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=2; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + if(NeedDisplayDescp){ + //Fire History + if(EntryTmp.fData.Body.Splite.Data0 == TControlCenter::LinkInputTypeFireSimulate){ + if(LanguageEnCn==0)TMyString::sFromStr("模拟",Text.Text); + else TMyString::sFromStr(" SIM",Text.Text); + }else{ + Text.D32[0] = 0x20202020; + } + Text.D32[1] = 0x20202020; + if(IsFirst){ + Text.D32[2] = 0; + if(LanguageEnCn==0)TMyString::sAddOnStr(" 首火警 ",Text.Text); + else TMyString::sAddOnStr("Fire 1st",Text.Text); + }else{ + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + } + Text.D32[4] = 0x20202020; + Text.D32[5] = 0x20202020; + + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=7; d<15; d++){ + Text.D32[d-1] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[14] =0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + }else{ + if(EntryTmp.fData.Body.Splite.Data0 == TControlCenter::LinkInputTypeFireSimulate){ + if(LanguageEnCn==0)TMyString::sFromStr("模拟",Text.Text); + else TMyString::sFromStr(" SIM",Text.Text); + }else{ + Text.D32[0] = 0x20202020; + } + Text.D32[1] = 0x20202020; + if(IsFirst){ + Text.D32[2] = 0; + if(LanguageEnCn==0)TMyString::sAddOnStr(" 首火警 ",Text.Text); + else TMyString::sAddOnStr("Fire 1st",Text.Text); + }else{ + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + } + Text.D32[4] = 0x20202020; + Text.D32[5] = 0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + } +} + +void TQueryMessageFire::FillDescpTextEmpty() +{ + Text.Text[0] = ' '; + Text.Text[1] = '\0'; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); +} + +void TQueryMessageFire::DrawListAll(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int TextClr, bClr, Wrote; + int DrawDescp; + + aInx = TopIndex; + Wrote = 0; + for(i=0;i (Count-1))break; + if(SelectedIndex != aInx){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + DrawDescp = FillText(aInx, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(aInx); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + aInx++; + Wrote++; + } + for(i=Wrote; i0){ + i = InTimeTopIndex; + for(;i<(InTimeStopIndex+1);i++){ + if(InTimeSelectedIndex != (InTimeTopIndex + Wrote)){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + aInx = InTimeTopIndex - InTimeStartIndex + Wrote; + FillText(i, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = Wrote *2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(i); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + + Wrote++; + if(Wrote >= ListLineCnt){ + break; + } + } + } + for(i=Wrote; i0){ + SelectedIndex = Count -1; + }else{ + SelectedIndex = TopIndex; + } +} + +unsigned long long TQueryMessageFire::aTimeGet(int aInx) +{ + volatile unsigned int SdAddr, Addr; + + //Fire History + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + alt.D32.Low4 = *(volatile unsigned int *)(SdAddr + 12); + alt.D32.Hi2 = *(volatile unsigned int *)(SdAddr + 16); + alt.D8[6] = 0; + alt.D8[7] = 0; + return alt.D64; +} + +void TQueryMessageFire::GetStartStopTime() +{ + int i; + + RestoreFromEdit(); + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextFrom[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextFrom[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StartTime = alt.D64; + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextTo[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextTo[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StopTime = alt.D64; +} + +void TQueryMessageFire::FindInTimeEntry() +{ + int i, aCnt, SatrtFound, StopFound; + unsigned long long aT; + SatrtFound = 0; + StopFound = 0; + InTimeStartIndex = 0; + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT < StartTime){ + InTimeStartIndex = i+1; + if(InTimeStartIndex >(Count-1)){ + SatrtFound = 0; + }else{ + SatrtFound = 1; + } + break; + } + } + if(SatrtFound == 0){ + if(InTimeStartIndex == 0){ + SatrtFound =1; + } + } + if(SatrtFound){ + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT <= StopTime){ + InTimeStopIndex = i; + StopFound = 1; + break; + } + } + if(StopFound == 0){ + InTimeStopIndex = Count-1; + } + if(InTimeStopIndex < InTimeStartIndex){ + InTimeCount = 0; + }else{ + aCnt = InTimeStopIndex - InTimeStartIndex + 1; + if(aCnt <0)aCnt = 0; + InTimeCount = aCnt; + } + + InTimeTopIndex = InTimeStopIndex - ListLineCnt +1; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + }else{ + InTimeCount = 0; + InTimeTopIndex = 0; + InTimeStopIndex = 0; + } +} + + +void TQueryMessageFire::GetEntry4Print(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char NeedDescp; + + //Fire History + NeedDescp = 0; + + Addr = Record.Buf4Fire.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=3; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if( (aP0) && (aP0<=dPORT_MAX_COUNT) ){ + NeedDescp = 1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && ( aP0 <= dADDR_DIRECTPAD_END)){ + NeedDescp = 1; + } + + if(NeedDescp){ + //Fire History + for(d=7; d<15; d++){ + Text.D32[d-1] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[14] =0; + }else{ + Text.D32[6] = 0; + } +} + + +TGuiMsgReturn TQueryMessageFire::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + if(IsAllTime){ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = TopIndex -ListLineCnt; + if(aIndex > -1){ + TopIndex = aIndex; + SelectedIndex -= ListLineCnt; + }else{ + if(TopIndex > 0){ + TopIndex = 0; + SelectedIndex = TopIndex; + }else{ + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = TopIndex +ListLineCnt; + if(aIndex < Count){ + TopIndex = aIndex; + SelectedIndex += ListLineCnt; + if(SelectedIndex >= Count){ + SelectedIndex = Count-1; + } + }else{ + TopIndex = 0; + SelectedIndex = TopIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = SelectedIndex -1; + if(aIndex > -1){ + SelectedIndex = aIndex; + if(SelectedIndex < TopIndex){ + TopIndex = SelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = SelectedIndex +1; + if(aIndex < Count){ + SelectedIndex = aIndex; + if(SelectedIndex > (TopIndex + ListLineCnt -1) ){ + TopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + }else{ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = InTimeTopIndex -ListLineCnt; + if(aIndex >= InTimeStartIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex -= ListLineCnt; + }else{ + if(InTimeTopIndex > InTimeStartIndex){ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + }else{ + InTimeTopIndex = InTimeStopIndex - ListLineCnt; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = InTimeTopIndex +ListLineCnt; + if(aIndex <= InTimeStopIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex += ListLineCnt; + if(InTimeSelectedIndex > InTimeStopIndex){ + InTimeSelectedIndex = InTimeStopIndex; + } + }else{ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = InTimeSelectedIndex -1; + if(aIndex >= InTimeStartIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex < InTimeTopIndex){ + InTimeTopIndex = InTimeSelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = InTimeSelectedIndex +1; + if(aIndex <= InTimeStopIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex > (InTimeTopIndex + ListLineCnt -1) ){ + InTimeTopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + } + + if(IsInputTime){ + if(aKey == VK_UP){ + if(TimeEditFrom >0){ + RestoreFromEdit(); + TimeEditFrom =0; + SetEditStart(); + }else{ + if(TimeEditFrom > -1){ + RestoreFromEdit(); + TimeEditFrom = -1; + DrawIfAllTime(); + } + } + }else + if(aKey == VK_DOWN){ + if(TimeEditFrom <1){ + if(IsAllTimeTemp == 0){ + if(TimeEditFrom == 0)RestoreFromEdit(); + TimeEditFrom ++; + SetEditStart(); + DrawIfAllTime(); + } + } + }else + if(aKey == VK_LEFT){ + if(TimeEditFrom > -1){ + if(TimeIndex >0){ + RestoreFromEdit(); + TimeIndex--; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_RIGHT){ + if(TimeEditFrom > -1){ + if(TimeIndex <5){ + RestoreFromEdit(); + TimeIndex++; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_EXECUTE){ + //Read Here + if(IsAllTimeTemp){ + IsAllTime = IsAllTimeTemp; + DrawItemCount(Count); + ReDraw(); + }else{ + IsAllTime = IsAllTimeTemp; + GetStartStopTime(); + FindInTimeEntry(); + DrawItemCount(InTimeCount); + IsInputTime = 0; + RenderContent(); + ReDraw(); + } + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsInputTime = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else{ + if(IsAllTimeTemp == 0){ + if(IsEditing){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + } + } + } + + if(IsGoPrint){ + if(aKey == VK_LEFT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_RIGHT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_EXECUTE){ + //Print Here + if(Count){ + if(SelectedIndex < Count){ + GetEntry4Print(SelectedIndex); + RecordMsg.D32[0] = EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = EntryTmp.fData.UserCode; + DoPrint.PrintHistory(0, RecordMsg, &Text.Text[24]); + } + } + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + } + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TQueryMessageFire::Task1000Ms() +{ + if(IsShowing){ + if(Count != Record.Buf4Fire.Count){ + TopIndex = Count - ListLineCnt +1; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } +} + +int TQueryMessageFire::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} diff --git a/MyCode/Gui/QueryMessageFire.h b/MyCode/Gui/QueryMessageFire.h new file mode 100644 index 0000000..1aeeb59 --- /dev/null +++ b/MyCode/Gui/QueryMessageFire.h @@ -0,0 +1,22 @@ +#ifndef QUERYMESSAGEFIRE_H_ +#define QUERYMESSAGEFIRE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "ProtoFecBus.h" + + + + + +#endif + + diff --git a/MyCode/Gui/QueryMsgFault.cpp b/MyCode/Gui/QueryMsgFault.cpp new file mode 100644 index 0000000..9c9b2c9 --- /dev/null +++ b/MyCode/Gui/QueryMsgFault.cpp @@ -0,0 +1,1544 @@ +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" +#include "QueryMessage.h" + +#define TextTopOffSet 6 +#define ListLineCnt 4 +#define ColHeight 33 + +#define FixTop 69 +#define MsgX0 6 +#define DescpX0 270 //90 + +#define dLineMaxLen 64 + +const static unsigned short stAllTop[10] = { + 80, 120, 160, 200, 240, + 280, 320, 360, 400, 440 +}; + +static const short qmFixCol[8] = { + 20,100,160,240, 320,400,520,600 +}; + +void TQueryMsgFault::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + BoxBoundTime.Set(Left+170, Top+80, Right-170, Bottom-30); + GoPrint.Set(Left+170, Top+150, Right-170, Bottom-130); + Color = aColor; + #undef CH + + + Caption.Border.Color = clGray; + + FixColColor = clMaroon; + FixColTextColor = clNearWhite; + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; +} + +void TQueryMsgFault::InitBackEnd() +{ + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; +} + +void TQueryMsgFault::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8) +{ + +} + +void TQueryMsgFault::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgFault::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TQueryMsgFault::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgFault::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TQueryMsgFault::DrawCaption(void) +{ + if(LanguageEnCn==0)TMyString::sFromStr("历史记录->查询故障信息", Caption.Text); + else TMyString::sFromStr("Recorded Info->Query Fault", Caption.Text); + + Caption.Show(); + DrawCaption2(); +} + +void TQueryMsgFault::DrawCaption2(void) +{ + +} + +void TQueryMsgFault::RenderWarningWait(void) +{ + int x,y,x2,y2, aW,aH; + x = 200; + y = 160; + x2 = 600; + y2 = 290; + aW = x2 - x +1; + aH = y2 - y +1; + VertLineRender(x, y, aH-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y+1, aH -2, 0xFF808080); + VertLineRender(x2, y, aH, 0xFF404040); + + HorizLineRender(x, y, aW - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, aW - 2, 0xFF808080); + HorizLineRender(x, y2, aW, 0xFF404040); + + RectFillRender(x+1,y+1,x2-2,y+30,clNavy); + RectFillRender(x+1,y+31,x2-2,y2-2,clGray); + if(LanguageEnCn==0){ + TextRender_string24(x+8, y+6, clNearWhite, "提示信息"); + TextRender_string24(x+66, y+36, clNearBlack, "正在读取,请等待"); + }else{ + TextRender_string24(x+8, y+6, clNearWhite, "Message"); + TextRender_string24(x+66, y+36, clNearBlack, "Reading,Please Wait"); + } +} + +void TQueryMsgFault::DrawItemCount(int aCount) +{ + TextDigitRender6Left24(500,Caption.Bound.Top +3, clNearWhite, Caption.Color, Count); + TextDigitRender6Left24(720,Caption.Bound.Top +3, clNearWhite, Caption.Color, aCount); + + if(LanguageEnCn==0){ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "总数量:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "查看数量:"); + }else{ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "Total:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "Display:"); + } +} + +void TQueryMsgFault::DrawBoxTimeOutLine() +{ + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + + VertLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Height -1, 0xFFFFFFFF); + VertLineRender(BoxBoundTime.Right -1, BoxBoundTime.Top +1, BoxBoundTime.Height -2, 0xFF808080); + VertLineRender(BoxBoundTime.Right, BoxBoundTime.Top, BoxBoundTime.Height, 0xFF404040); + + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Width - 1, 0xFFFFFFFF); + HorizLineRender(BoxBoundTime.Left +1, BoxBoundTime.Bottom -1, BoxBoundTime.Width - 2, 0xFF808080); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom, BoxBoundTime.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "设置日期时间段,按确认键开始查询"); + else TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "Set Date And Time,Key OK:Query "); +} + +void TQueryMsgFault::DrawTimeEntry(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + vtValueFrom[0] = DateTime.Date.Split.Year; + vtValueFrom[1] = DateTime.Date.Split.Month; + vtValueFrom[2] = DateTime.Date.Split.Day; + + vtValueFrom[3] = DateTime.Time.Split.Hour; + vtValueFrom[4] = DateTime.Time.Split.Minute; + vtValueFrom[5] = DateTime.Time.Split.Second; + + vtValueTo[0] =vtValueFrom[0]; + vtValueTo[1] =vtValueFrom[1]; + vtValueTo[2] =vtValueFrom[2]; + vtValueTo[3] =vtValueFrom[3]; + vtValueTo[4] =vtValueFrom[4]; + vtValueTo[5] =vtValueFrom[5]; + + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + + +void TQueryMsgFault::DrawTimeEntryNoUpdate(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + +void TQueryMsgFault::DrawIfAllTime(void) +{ + unsigned int aClr, bClr; + if(TimeEditFrom == -1){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + TTriangleLeftRight::sDrawLeftByHight(BoxBoundTime.Left + 150 - 20, BoxBoundTime.Top + 44, 20, clBlue); + TTriangleLeftRight::sDrawRightByHight(BoxBoundTime.Left + 150 + 106, BoxBoundTime.Top + 44, 20, clBlue); + if(LanguageEnCn==0){ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "全部条目"); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "按时间段"); + } + }else{ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, " All "); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "Segments"); + } + } +} + +void TQueryMsgFault::DrawBoxTimeString(void) +{ + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + if(LanguageEnCn==0){ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "开始时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, "年 月 日 时 分 秒"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "结束时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, "年 月 日 时 分 秒"); + }else{ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "Begin"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, " Y M D H M S"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "End"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, " Y M D H M S"); + } +} + +void TQueryMsgFault::DrawBoxTime(void) +{ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); +} + +void TQueryMsgFault::DrawGoPrintOutLine() +{ + RectFillRender(GoPrint.Left, GoPrint.Top, GoPrint.Right, GoPrint.Bottom, clFrmFace); + + VertLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Height -1, 0xFFFFFFFF); + VertLineRender(GoPrint.Right -1, GoPrint.Top +1, GoPrint.Height -2, 0xFF808080); + VertLineRender(GoPrint.Right, GoPrint.Top, GoPrint.Height, 0xFF404040); + + HorizLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Width - 1, 0xFFFFFFFF); + HorizLineRender(GoPrint.Left +1, GoPrint.Bottom -1, GoPrint.Width - 2, 0xFF808080); + HorizLineRender(GoPrint.Left, GoPrint.Bottom, GoPrint.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "按确认键开始打印并返回"); + else TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "Confirm Print Or Return"); +} + +void TQueryMsgFault::DrawPrintWhat() +{ + if(LanguageEnCn==0)TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "打印当前选定条目"); + else TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "Print Current Item"); + return; + if(PrintWhat == 0){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, "当前选定条目"); + }else + if(PrintWhat == 1){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 当前页面 "); + }else{ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 全部信息 "); + } +} + +void TQueryMsgFault::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } + DrawItemCount(Count); + ShowTip(); +} + +void TQueryMsgFault::ReDraw(void) +{ + Caption.Enable = 1; + //DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } +} + + +void TQueryMsgFault::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + DrawItemCount(Count); + ShowTip(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + ShowTip(); + } +} + + +void TQueryMsgFault::ShowTip() +{ + if(LanguageEnCn==0){ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, TAB键去打印"); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "上下左右键切换或编辑条目, 数字键删除键编辑 "); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "按确定键打印当前条目 "); + } + }else{ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down:Switch item; TAB To Print "); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down To Switch Item To Edit; Num Key To Edit"); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "Press The OK Key To Print The Current Item "); + } + } +} + +void TQueryMsgFault::SetEditStart(void) +{ + int x,y,w,h; + + IsEditing =1; + + ReStoreP0 = TimeEditFrom; + ReStoreP1 = TimeIndex; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + vEdit.Init(x,y,w,h,0,0,1,clTeal); + vEdit.Color = clTeal; + vEdit.SetMaxLen(2); + if(ReStoreP0 ==0){ + vEdit.Str.Text[0] = vtTextFrom[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextFrom[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + }else + if(ReStoreP0 ==1){ + vEdit.Str.Text[0] = vtTextTo[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextTo[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + } + vEdit.Pst = -1; + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); +} + +void TQueryMsgFault::RestoreFromEdit(void) +{ + int x,y,w,h; + + if(IsEditing == 0)return; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + if(ReStoreP0 == 0){ + vtTextFrom[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextFrom[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextFrom[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[ReStoreP1]); + }else + if(ReStoreP0 == 1){ + vtTextTo[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextTo[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextTo[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[ReStoreP1]); + } + IsEditing = 0; +} + +int TQueryMsgFault::FillText(int aInx, int ShowInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + NeedDisplayDescp = 0; + TMyString::sClear(DescpText.Text); + if(LanguageEnCn==0)TMyString::sFromStr("故障 ", DescpText.Text); + else TMyString::sFromStr("FLT. ", DescpText.Text); + + //Fault History + Addr = Record.Buf4Fault.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=2; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + CoverDateTimeIllegal(EntryTmp.fData.Body, &DateTimeCovered); + Text.Text[7] = DateTimeCovered.Year / 16 % 10 + '0'; + Text.Text[8] = DateTimeCovered.Year % 16 % 10 + '0'; + Text.Text[9] = '/'; + Text.Text[10] = DateTimeCovered.Month / 16 % 10 + '0'; + Text.Text[11] = DateTimeCovered.Month % 16 % 10 + '0'; + Text.Text[12] = '/'; + Text.Text[13] = DateTimeCovered.Day / 16 % 10 + '0'; + Text.Text[14] = DateTimeCovered.Day % 16 % 10 + '0'; + Text.Text[15] = ' '; + Text.Text[16] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text.Text[17] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text.Text[18] = ':'; + Text.Text[19] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text.Text[20] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text.Text[21] = ':'; + Text.Text[22] = DateTimeCovered.Second / 16 % 10 + '0'; + Text.Text[23] = DateTimeCovered.Second % 16 % 10 + '0'; + Text.Text[24] = ' '; + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + Text.Text[25] = e + '0'; + e = data % 10; + Text.Text[26] = e + '0'; + Text.Text[27] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + Text.Text[28] = e + '0'; + e = data % 10; + Text.Text[29] = e + '0'; + Text.Text[30] = '-'; + + Text.Text[31] = '\0'; + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xC0){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + if(LanguageEnCn==0)TMyString::sAddOnStr("总线盘 ",Text.Text); + else TMyString::sAddOnStr("BusPad Brd ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,Text.Text); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" 离线",Text.Text); + else TMyString::sAddOnStr(" 恢复",Text.Text); + }else{ + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" OffLine",Text.Text); + else TMyString::sAddOnStr(" Recover",Text.Text); + } + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + if(LanguageEnCn==0)TMyString::sAddOnStr("多线盘 ",Text.Text); + else TMyString::sAddOnStr("DirectCtrl Brd ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,Text.Text); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" 离线",Text.Text); + else TMyString::sAddOnStr(" 恢复",Text.Text); + }else{ + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" OffLine",Text.Text); + else TMyString::sAddOnStr(" Recover",Text.Text); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xD0){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + if(LanguageEnCn==0)TMyString::sAddOnStr("设备故障 ",Text.Text); + else TMyString::sAddOnStr("DevFault ",Text.Text); + aType = EntryTmp.fData.Body.Splite.Data0; + if(LanguageEnCn==0){ + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultType[aType],Text.Text); + }else{ + TMyString::sAddOnStr("未知类型",Text.Text); + } + }else{ + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultTypeEn[aType],Text.Text); + }else{ + TMyString::sAddOnStr("Unknown",Text.Text); + } + } + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr(" ",Text.Text); + if( (aType == 15) || (aType == 16) ){ + Text.Text[28] = '\0'; + if(LanguageEnCn==0){ + TMyString::sAddOnStr(StrDevFaultType[aType],Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" 通讯故障",Text.Text); + }else{ + TMyString::sAddOnStr(StrDevFaultTypeEn[aType],Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" OffLine ",Text.Text); + } + //if(EntryTmp.fData.Body.Splite.mType > 200){ + // TMyString::sAddOnStr("通讯故障条目数:多于200",Text.Text); + //}else{ + // TMyString::sAddOnStr("通讯故障条目数:",Text.Text); + // TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.mType, Text.Text); + //} + }else + if( (aType == 19) || (aType == 20) || (aType == 21) || (aType == 23) ){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + } + if(LanguageEnCn==0)TMyString::sAddOnStr(" 恢复",Text.Text); + else TMyString::sAddOnStr(" Recovered",Text.Text); + }else{ + TMyString::sAddOnStr(" ",Text.Text); + if( (aType == 15) || (aType == 16) ){ + Text.Text[28] = '\0'; + if(LanguageEnCn==0){ + TMyString::sAddOnStr(StrDevFaultType[aType],Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" 通讯故障",Text.Text); + }else{ + TMyString::sAddOnStr(StrDevFaultTypeEn[aType],Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" OffLine ",Text.Text); + } + //if(EntryTmp.fData.Body.Splite.mType > 200){ + // TMyString::sAddOnStr("通讯故障条目数:多于200",Text.Text); + //}else{ + // TMyString::sAddOnStr("通讯故障条目数:",Text.Text); + // TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.mType, Text.Text); + //} + }else + if( (aType == 19) || (aType == 20) || (aType == 21) || (aType == 23)|| (aType == 26)|| (aType == 27)){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xE0){ + //Cir Error + if(LanguageEnCn==0){ + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr("回路故障-恢复",Text.Text); + }else{ + //TMyString::sAddOnStr("回路故障-发生",Text.Text); + TMyString::sAddOnStr("回路故障",Text.Text); + } + }else{ + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr("LoopFault-Recovered",Text.Text); + }else{ + //TMyString::sAddOnStr("回路故障-发生",Text.Text); + TMyString::sAddOnStr("LoopFault",Text.Text); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + if(LanguageEnCn==0)TMyString::sAddOnStr("板卡故障 ",Text.Text); + else TMyString::sAddOnStr("BoardErr ",Text.Text); + aType = EntryTmp.fData.Body.Splite.Data0; + if( (aType == TBoardFaultType::LoopMotherBoard) || + (aType == TBoardFaultType::RegisteredData) || + (aType == TBoardFaultType::MaskedData) || + (aType == TBoardFaultType::StorageEpDType) || + (aType == TBoardFaultType::StorageEpAuxId) || + (aType == TBoardFaultType::StorageEpArea) || + (aType == TBoardFaultType::StorageEpAssignedType) || + (aType == TBoardFaultType::StorageEpSignalType) || + (aType == TBoardFaultType::StorageDirectPadCfg) || + (aType == TBoardFaultType::StoragePortDpSet) || + (aType == TBoardFaultType::StorageBusPadCfg) ){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + }else + if( (aType == TBoardFaultType::StorageLinkExpressionPart1) || + (aType == TBoardFaultType::StorageLinkExpressionPart2) || + (aType == TBoardFaultType::StorageLinkExpressionPart3) || + (aType == TBoardFaultType::StorageLinkExpressionPart4) || + (aType == TBoardFaultType::StorageLinkExpressionPart5) || + (aType == TBoardFaultType::StorageLinkExpressionPart6) || + (aType == TBoardFaultType::StorageLinkExpressionPart7) || + (aType == TBoardFaultType::StorageLinkExpressionPart8) || + (aType == TBoardFaultType::StorageLinkExpressionPart9) ){ + unsigned short tInx = aType - static_cast(TBoardFaultType::StorageLinkExpressionPart1); + tInx = tInx * 256 + EntryTmp.fData.Body.Splite.P1; + TMyString::sAddOn4Dg(tInx % 10000,Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + } + if(aType < TBoardFaultType::MaxValue){ + if(LanguageEnCn==0)TMyString::sAddOnStr(StrBrdFaultType[aType],Text.Text); + else TMyString::sAddOnStr(StrBrdFaultTypeEn[aType],Text.Text); + }else{ + if(LanguageEnCn==0)TMyString::sAddOnStr("未知类型",Text.Text); + else TMyString::sAddOnStr("Unknown ",Text.Text); + } + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + if(LanguageEnCn==0)TMyString::sAddOnStr(" 恢复",Text.Text); + else TMyString::sAddOnStr(" Recovered",Text.Text); + }else{ + //TMyString::sAddOnStr(" 发生",Text.Text); + } + }else{ + //EpError + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + Text.Text[31] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[32] = e + '0'; + e = data % 10; + Text.Text[33] = e + '0'; + Text.Text[34] = ' '; + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + data = EntryTmp.fData.UserCode; + d = data/1000'0000; + e = d % 10; + Text.Text[35] = e + '0'; + d = data/100'0000; + e = d % 10; + Text.Text[36] = e + '0'; + d = data/10'0000; + e = d % 10; + Text.Text[37] = e + '0'; + d = data/10000; + e = d % 10; + Text.Text[38] = e + '0'; + d = data/1000; + e = d % 10; + Text.Text[39] = e + '0'; + d = data/100; + e = d % 10; + Text.Text[40] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[41] = e + '0'; + e = data % 10; + Text.Text[42] = e + '0'; + Text.Text[43] = ' '; + + Text.Text[44] = 0; + + aType = EntryTmp.fData.Body.Splite.Data0; + if(LanguageEnCn==0){ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultType[aType],Text.Text); + }else{ + TMyString::sAddOnStr("未知故障",Text.Text); + } + + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("-恢复",Text.Text); + }else{ + //TMyString::sAddOnStr("-发生",Text.Text); + } + }else{ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultTypeEn[aType],Text.Text); + }else{ + TMyString::sAddOnStr("Unknown",Text.Text); + } + + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("-Recovered",Text.Text); + }else{ + //TMyString::sAddOnStr("-发生",Text.Text); + } + } + + NeedDisplayDescp = 1; + if(LanguageEnCn==0){ + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],DescpText.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",DescpText.Text); + } + }else{ + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortNameEn[aType],DescpText.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("Pad Of DirectCtrl ",DescpText.Text); + } + } + } + + return NeedDisplayDescp; +} + +void TQueryMsgFault::FillDescpText(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + if(NeedDisplayDescp){ + //Fault History + TMyString::sFillFixLen(DescpText.Text, 34); + + Addr = Record.Buf4Fault.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=7; d<15; d++){ + DescpText.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + TMyString::sFillFixLen(DescpText.Text, dLineMaxLen); + }else{ + TMyString::sFillFixLen(DescpText.Text, dLineMaxLen); + } +} + +void TQueryMsgFault::FillDescpTextEmpty() +{ + TMyString::sFillFixLen(DescpText.Text, dLineMaxLen); +} + + +void TQueryMsgFault::DrawListAll(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int TextClr, bClr, Wrote; + + aInx = TopIndex; + Wrote = 0; + for(i=0;i (Count-1))break; + if(SelectedIndex != aInx){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + NeedDisplayDescp = FillText(aInx, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = i*2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + if(NeedDisplayDescp)FillDescpText(aInx); + else FillDescpTextEmpty(); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, DescpText.Text); + aInx++; + Wrote++; + } + for(i=Wrote; i0){ + i = InTimeTopIndex; + for(;i<(InTimeStopIndex+1);i++){ + if(InTimeSelectedIndex != (InTimeTopIndex + Wrote)){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + aInx = InTimeTopIndex - InTimeStartIndex + Wrote; + NeedDisplayDescp = FillText(i, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = Wrote *2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + if(NeedDisplayDescp)FillDescpText(i); + else FillDescpTextEmpty(); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, DescpText.Text); + Wrote++; + if(Wrote >= ListLineCnt){ + break; + } + } + } + for(i=Wrote; i0){ + SelectedIndex = Count -1; + }else{ + SelectedIndex = TopIndex; + } +} + +unsigned long long TQueryMsgFault::aTimeGet(int aInx) +{ + volatile unsigned int SdAddr, Addr; + + //Fault History + Addr = Record.Buf4Fault.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + alt.D32.Low4 = *(volatile unsigned int *)(SdAddr + 12); + alt.D32.Hi2 = *(volatile unsigned int *)(SdAddr + 16); + alt.D8[6] = 0; + alt.D8[7] = 0; + return alt.D64; +} + +void TQueryMsgFault::GetStartStopTime() +{ + int i; + + RestoreFromEdit(); + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextFrom[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextFrom[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StartTime = alt.D64; + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextTo[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextTo[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StopTime = alt.D64; +} + +void TQueryMsgFault::FindInTimeEntry() +{ + int i, aCnt, SatrtFound, StopFound; + unsigned long long aT; + SatrtFound = 0; + StopFound = 0; + InTimeStartIndex = 0; + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT < StartTime){ + InTimeStartIndex = i+1; + if(InTimeStartIndex >(Count-1)){ + SatrtFound = 0; + }else{ + SatrtFound = 1; + } + break; + } + } + if(SatrtFound == 0){ + if(InTimeStartIndex == 0){ + SatrtFound =1; + } + } + if(SatrtFound){ + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT <= StopTime){ + InTimeStopIndex = i; + StopFound = 1; + break; + } + } + if(StopFound == 0){ + InTimeStopIndex = Count-1; + } + if(InTimeStopIndex < InTimeStartIndex){ + InTimeCount = 0; + }else{ + aCnt = InTimeStopIndex - InTimeStartIndex + 1; + if(aCnt <0)aCnt = 0; + InTimeCount = aCnt; + } + + InTimeTopIndex = InTimeStopIndex - ListLineCnt +1; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + }else{ + InTimeCount = 0; + InTimeTopIndex = 0; + InTimeStopIndex = 0; + } +} + + +void TQueryMsgFault::GetEntry4Print(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char NeedDescp; + + NeedDescp = 0; + + //Fault History + Addr = Record.Buf4Fault.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=3; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xC0){ + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xD0){ + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xE0){ + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xF0){ + + }else{ + NeedDisplayDescp = 1; + } + + if(NeedDescp){ + //Fault History + for(d=7; d<15; d++){ + DescpText.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + TMyString::sFillFixLen(DescpText.Text, dLineMaxLen); + }else{ + DescpText.D32[7] =0; + } +} + +TGuiMsgReturn TQueryMsgFault::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + if(IsAllTime){ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = TopIndex -ListLineCnt; + if(aIndex > -1){ + TopIndex = aIndex; + SelectedIndex -= ListLineCnt; + }else{ + if(TopIndex > 0){ + TopIndex = 0; + SelectedIndex = TopIndex; + }else{ + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = TopIndex +ListLineCnt; + if(aIndex < Count){ + TopIndex = aIndex; + SelectedIndex += ListLineCnt; + if(SelectedIndex >= Count){ + SelectedIndex = Count-1; + } + }else{ + TopIndex = 0; + SelectedIndex = TopIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = SelectedIndex -1; + if(aIndex > -1){ + SelectedIndex = aIndex; + if(SelectedIndex < TopIndex){ + TopIndex = SelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = SelectedIndex +1; + if(aIndex < Count){ + SelectedIndex = aIndex; + if(SelectedIndex > (TopIndex + ListLineCnt -1) ){ + TopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + }else{ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = InTimeTopIndex -ListLineCnt; + if(aIndex >= InTimeStartIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex -= ListLineCnt; + }else{ + if(InTimeTopIndex > InTimeStartIndex){ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + }else{ + InTimeTopIndex = InTimeStopIndex - ListLineCnt; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = InTimeTopIndex +ListLineCnt; + if(aIndex <= InTimeStopIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex += ListLineCnt; + if(InTimeSelectedIndex > InTimeStopIndex){ + InTimeSelectedIndex = InTimeStopIndex; + } + }else{ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = InTimeSelectedIndex -1; + if(aIndex >= InTimeStartIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex < InTimeTopIndex){ + InTimeTopIndex = InTimeSelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = InTimeSelectedIndex +1; + if(aIndex <= InTimeStopIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex > (InTimeTopIndex + ListLineCnt -1) ){ + InTimeTopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + } + + if(IsInputTime){ + if(aKey == VK_UP){ + if(TimeEditFrom >0){ + RestoreFromEdit(); + TimeEditFrom =0; + SetEditStart(); + }else{ + if(TimeEditFrom > -1){ + RestoreFromEdit(); + TimeEditFrom = -1; + DrawIfAllTime(); + } + } + }else + if(aKey == VK_DOWN){ + if(TimeEditFrom <1){ + if(IsAllTimeTemp == 0){ + if(TimeEditFrom == 0)RestoreFromEdit(); + TimeEditFrom ++; + SetEditStart(); + DrawIfAllTime(); + } + } + }else + if(aKey == VK_LEFT){ + if(TimeEditFrom > -1){ + if(TimeIndex >0){ + RestoreFromEdit(); + TimeIndex--; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_RIGHT){ + if(TimeEditFrom > -1){ + if(TimeIndex <5){ + RestoreFromEdit(); + TimeIndex++; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_EXECUTE){ + //Read Here + if(IsAllTimeTemp){ + IsAllTime = IsAllTimeTemp; + DrawItemCount(Count); + ReDraw(); + }else{ + IsAllTime = IsAllTimeTemp; + GetStartStopTime(); + FindInTimeEntry(); + DrawItemCount(InTimeCount); + IsInputTime = 0; + RenderContent(); + ReDraw(); + } + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsInputTime = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else{ + if(IsAllTimeTemp == 0){ + if(IsEditing){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + } + } + } + + if(IsGoPrint){ + if(aKey == VK_LEFT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_RIGHT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_EXECUTE){ + //Print Here + if(Count){ + if(SelectedIndex < Count){ + GetEntry4Print(SelectedIndex); + RecordMsg.D32[0] = EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = EntryTmp.fData.UserCode; + DoPrint.PrintHistory(3,RecordMsg, &DescpText.Text[28]); + } + } + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + } + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TQueryMsgFault::Task1000Ms() +{ + if(IsShowing){ + if(Count != Record.Buf4Fault.Count){ + TopIndex = Count - ListLineCnt +1; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } +} + +int TQueryMsgFault::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} + + diff --git a/MyCode/Gui/QueryMsgFault.h b/MyCode/Gui/QueryMsgFault.h new file mode 100644 index 0000000..63eb800 --- /dev/null +++ b/MyCode/Gui/QueryMsgFault.h @@ -0,0 +1,24 @@ +#ifndef QUERYMSGFAULT_H_ +#define QUERYMSGFAULT_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "ProtoFecBus.h" + + + + + + + +#endif + + diff --git a/MyCode/Gui/QueryMsgLinkage.cpp b/MyCode/Gui/QueryMsgLinkage.cpp new file mode 100644 index 0000000..41563d4 --- /dev/null +++ b/MyCode/Gui/QueryMsgLinkage.cpp @@ -0,0 +1,1463 @@ +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" +#include "QueryMessage.h" + +#define TextTopOffSet 6 +#define ListLineCnt 4 +#define ColHeight 33 + +#define FixTop 69 +#define MsgX0 6 +#define DescpX0 270 //90 + +#define dLineMaxLen 64 + +const static unsigned short stAllTop[10] = { + 80, 120, 160, 200, 240, + 280, 320, 360, 400, 440 +}; + +static const short qmFixCol[8] = { + 20,100,160,240, 320,400,520,600 +}; + +void TQueryMsgLinkage::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + BoxBoundTime.Set(Left+170, Top+80, Right-170, Bottom-30); + GoPrint.Set(Left+170, Top+150, Right-170, Bottom-130); + Color = aColor; + #undef CH + + + Caption.Border.Color = clGray; + + FixColColor = clMaroon; + FixColTextColor = clNearWhite; + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; + IsSimulate =0; +} + +void TQueryMsgLinkage::InitBackEnd() +{ + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; + IsSimulate = 0; +} + +void TQueryMsgLinkage::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8) +{ + +} + +void TQueryMsgLinkage::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgLinkage::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TQueryMsgLinkage::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgLinkage::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TQueryMsgLinkage::DrawCaption(void) +{ + if(LanguageEnCn==0)TMyString::sFromStr("历史记录->查询联动信息", Caption.Text); + else TMyString::sFromStr("Recorded Info->Query Linkage", Caption.Text); + + Caption.Show(); + DrawCaption2(); +} + +void TQueryMsgLinkage::DrawCaption2(void) +{ + +} + +void TQueryMsgLinkage::RenderWarningWait(void) +{ + int x,y,x2,y2, aW,aH; + x = 200; + y = 160; + x2 = 600; + y2 = 290; + aW = x2 - x +1; + aH = y2 - y +1; + VertLineRender(x, y, aH-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y+1, aH -2, 0xFF808080); + VertLineRender(x2, y, aH, 0xFF404040); + + HorizLineRender(x, y, aW - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, aW - 2, 0xFF808080); + HorizLineRender(x, y2, aW, 0xFF404040); + + RectFillRender(x+1,y+1,x2-2,y+30,clNavy); + RectFillRender(x+1,y+31,x2-2,y2-2,clGray); + + if(LanguageEnCn==0){ + TextRender_string24(x+8, y+6, clNearWhite, "提示信息"); + TextRender_string24(x+66, y+36, clNearBlack, "正在读取,请等待"); + }else{ + TextRender_string24(x+8, y+6, clNearWhite, "Message"); + TextRender_string24(x+66, y+36, clNearBlack, "Reading,Please Wait"); + } +} + +void TQueryMsgLinkage::DrawItemCount(int aCount) +{ + TextDigitRender6Left24(500,Caption.Bound.Top +3, clNearWhite, Caption.Color, Count); + TextDigitRender6Left24(720,Caption.Bound.Top +3, clNearWhite, Caption.Color, aCount); + + if(LanguageEnCn==0){ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "总数量:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "查看数量:"); + }else{ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "Total:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "Display:"); + } +} + +void TQueryMsgLinkage::DrawBoxTimeOutLine() +{ + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + + VertLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Height -1, 0xFFFFFFFF); + VertLineRender(BoxBoundTime.Right -1, BoxBoundTime.Top +1, BoxBoundTime.Height -2, 0xFF808080); + VertLineRender(BoxBoundTime.Right, BoxBoundTime.Top, BoxBoundTime.Height, 0xFF404040); + + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Width - 1, 0xFFFFFFFF); + HorizLineRender(BoxBoundTime.Left +1, BoxBoundTime.Bottom -1, BoxBoundTime.Width - 2, 0xFF808080); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom, BoxBoundTime.Width, 0xFF404040); + + if(LanguageEnCn==0) TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "设置日期时间段,按确认键开始查询"); + else TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "Set Date And Time,OK Key:Start The Query"); +} + +void TQueryMsgLinkage::DrawTimeEntry(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + vtValueFrom[0] = DateTime.Date.Split.Year; + vtValueFrom[1] = DateTime.Date.Split.Month; + vtValueFrom[2] = DateTime.Date.Split.Day; + + vtValueFrom[3] = DateTime.Time.Split.Hour; + vtValueFrom[4] = DateTime.Time.Split.Minute; + vtValueFrom[5] = DateTime.Time.Split.Second; + + vtValueTo[0] =vtValueFrom[0]; + vtValueTo[1] =vtValueFrom[1]; + vtValueTo[2] =vtValueFrom[2]; + vtValueTo[3] =vtValueFrom[3]; + vtValueTo[4] =vtValueFrom[4]; + vtValueTo[5] =vtValueFrom[5]; + + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10 ; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10 ; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + + +void TQueryMsgLinkage::DrawTimeEntryNoUpdate(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + +void TQueryMsgLinkage::DrawIfAllTime(void) +{ + unsigned int aClr, bClr; + if(TimeEditFrom == -1){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + TTriangleLeftRight::sDrawLeftByHight(BoxBoundTime.Left + 150 - 20, BoxBoundTime.Top + 44, 20, clBlue); + TTriangleLeftRight::sDrawRightByHight(BoxBoundTime.Left + 150 + 106, BoxBoundTime.Top + 44, 20, clBlue); + if(LanguageEnCn==0){ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "全部条目"); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "按时间段"); + } + }else{ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, " All "); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "Segments"); + } + } +} + +void TQueryMsgLinkage::DrawBoxTimeString(void) +{ + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + if(LanguageEnCn==0){ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "开始时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, "年 月 日 时 分 秒"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "结束时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, "年 月 日 时 分 秒"); + }else{ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "Begin"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, " Y M D H M S"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "End"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, " Y M D H M S"); + } +} + +void TQueryMsgLinkage::DrawBoxTime(void) +{ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); +} + +void TQueryMsgLinkage::DrawGoPrintOutLine() +{ + RectFillRender(GoPrint.Left, GoPrint.Top, GoPrint.Right, GoPrint.Bottom, clFrmFace); + + VertLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Height -1, 0xFFFFFFFF); + VertLineRender(GoPrint.Right -1, GoPrint.Top +1, GoPrint.Height -2, 0xFF808080); + VertLineRender(GoPrint.Right, GoPrint.Top, GoPrint.Height, 0xFF404040); + + HorizLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Width - 1, 0xFFFFFFFF); + HorizLineRender(GoPrint.Left +1, GoPrint.Bottom -1, GoPrint.Width - 2, 0xFF808080); + HorizLineRender(GoPrint.Left, GoPrint.Bottom, GoPrint.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "按确认键开始打印并返回"); + else TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "Confirm Print Or Return"); +} + +void TQueryMsgLinkage::DrawPrintWhat() +{ + if(LanguageEnCn==0)TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "打印当前选定条目"); + else TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "Print Current Item"); + return; + if(PrintWhat == 0){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, "当前选定条目"); + }else + if(PrintWhat == 1){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 当前页面 "); + }else{ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 全部信息 "); + } +} + +void TQueryMsgLinkage::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } + DrawItemCount(Count); + ShowTip(); +} + +void TQueryMsgLinkage::ReDraw(void) +{ + Caption.Enable = 1; + //DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } +} + + +void TQueryMsgLinkage::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + DrawItemCount(Count); + ShowTip(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + ShowTip(); + } +} + + +void TQueryMsgLinkage::ShowTip() +{ + if(LanguageEnCn==0){ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, TAB键去打印"); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "上下左右键切换或编辑条目, 数字键删除键编辑 "); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "按确定键打印当前条目 "); + } + }else{ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down:Switch item; TAB To Print "); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down To Switch Item To Edit; Num Key To Edit"); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "Press The OK Key To Print The Current Item "); + } + } +} + +void TQueryMsgLinkage::SetEditStart(void) +{ + int x,y,w,h; + + IsEditing =1; + + ReStoreP0 = TimeEditFrom; + ReStoreP1 = TimeIndex; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + vEdit.Init(x,y,w,h,0,0,1,clTeal); + vEdit.Color = clTeal; + vEdit.SetMaxLen(2); + if(ReStoreP0 ==0){ + vEdit.Str.Text[0] = vtTextFrom[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextFrom[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + }else + if(ReStoreP0 ==1){ + vEdit.Str.Text[0] = vtTextTo[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextTo[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + } + vEdit.Pst = -1; + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); +} + +void TQueryMsgLinkage::RestoreFromEdit(void) +{ + int x,y,w,h; + + if(IsEditing == 0)return; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + if(ReStoreP0 == 0){ + vtTextFrom[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextFrom[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextFrom[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[ReStoreP1]); + }else + if(ReStoreP0 == 1){ + vtTextTo[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextTo[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextTo[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[ReStoreP1]); + } + IsEditing = 0; +} + +void TQueryMsgLinkage::AddOnUserCode() +{ + TMyString::sAddOn8Dg(EntryTmp.fData.UserCode, Text.Text); +} + +int TQueryMsgLinkage::FillText(int aInx, int ShowInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + //Linkage History + NeedDisplayDescp = 0; + IsSimulate =0; + + Addr = Record.Buf4Linkage.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=2; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + CoverDateTimeIllegal(EntryTmp.fData.Body, &DateTimeCovered); + Text.Text[7] = DateTimeCovered.Year / 16 % 10 + '0'; + Text.Text[8] = DateTimeCovered.Year % 16 % 10 + '0'; + Text.Text[9] = '/'; + Text.Text[10] = DateTimeCovered.Month / 16 % 10 + '0'; + Text.Text[11] = DateTimeCovered.Month % 16 % 10 + '0'; + Text.Text[12] = '/'; + Text.Text[13] = DateTimeCovered.Day / 16 % 10 + '0'; + Text.Text[14] = DateTimeCovered.Day % 16 % 10 + '0'; + Text.Text[15] = ' '; + Text.Text[16] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text.Text[17] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text.Text[18] = ':'; + Text.Text[19] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text.Text[20] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text.Text[21] = ':'; + Text.Text[22] = DateTimeCovered.Second / 16 % 10 + '0'; + Text.Text[23] = DateTimeCovered.Second % 16 % 10 + '0'; + Text.Text[24] = ' '; + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + Text.Text[25] = e + '0'; + e = data % 10; + Text.Text[26] = e + '0'; + Text.Text[27] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + Text.Text[28] = e + '0'; + e = data % 10; + Text.Text[29] = e + '0'; + Text.Text[30] = '-'; + + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + Text.Text[31] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[32] = e + '0'; + e = data % 10; + Text.Text[33] = e + '0'; + Text.Text[34] = ' '; + Text.Text[35] = '\0'; + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + AddOnUserCode(); + TMyString::sAddOnStr(" ",Text.Text); + + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text.Text); + NeedDisplayDescp = 1; + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if( (aP1) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + aType = DirectCtlBoard[aP0-dADDR_DIRECTPAD_START].AssignType[aP1-1]; + if(aType){ + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text.Text); + }else{ + if(LanguageEnCn==0)TMyString::sAddOnStr( "多线盘节点",Text.Text); + else TMyString::sAddOnStr( "DirectNode",Text.Text); + NeedDisplayDescp = 1; + } + } + } + + data = EntryTmp.fData.Body.Splite.iByte0; + + if(LanguageEnCn==0){ + if(data == 0x01){ + TMyString::sAddOnStr("-启动",Text.Text); + }else + if(data == 0x02){ + TMyString::sAddOnStr("-区声光启动",Text.Text); + }else + if(data == 0x03){ + TMyString::sAddOnStr("-反馈",Text.Text); + }else + if(data == 0x04){ + TMyString::sAddOnStr("-反馈缺失",Text.Text); + }else + if(data == 0x05){ + //TMyString::sAddOnStr("-手动启动",Text.Text); + TMyString::sAddOnStr("-启动",Text.Text); + }else + if(data == 0x06){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + //TMyString::sAddOnStr("-手动声光启动",Text.Text); + TMyString::sAddOnStr("-声光启动",Text.Text); + }else + if(data == 0x07){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + TMyString::sAddOnStr("-应答消钮",Text.Text); + }else + if(data == 0xB1){ + TMyString::sAddOnStr("-停止",Text.Text); + }else + if(data == 0xB3){ + TMyString::sAddOnStr("-反馈取消",Text.Text); + }else + if(data == 0xB5){ + //TMyString::sAddOnStr("-手动停止",Text.Text); + TMyString::sAddOnStr("-停止",Text.Text); + }else + if(data == 0xB6){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + //TMyString::sAddOnStr("-手动声光停止",Text.Text); + TMyString::sAddOnStr("-声光停止",Text.Text); + }else + if(data == 0xB7){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + TMyString::sAddOnStr("-应答消钮取消",Text.Text); + }else + if(data == 0x0A){ + TMyString::sAddOnStr("-延时启动",Text.Text); + } + }else{ + if(data == 0x01){ + TMyString::sAddOnStr("-Act",Text.Text); + }else + if(data == 0x02){ + TMyString::sAddOnStr("-Zone Alram On",Text.Text); + }else + if(data == 0x03){ + TMyString::sAddOnStr("-FB",Text.Text); + }else + if(data == 0x04){ + TMyString::sAddOnStr("-FB Miss",Text.Text); + }else + if(data == 0x05){ + //TMyString::sAddOnStr("-手动启动",Text.Text); + TMyString::sAddOnStr("-Act",Text.Text); + }else + if(data == 0x06){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + //TMyString::sAddOnStr("-手动声光启动",Text.Text); + TMyString::sAddOnStr("-Alram On",Text.Text); + }else + if(data == 0x07){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + TMyString::sAddOnStr("-Hydrant FB",Text.Text); + }else + if(data == 0xB1){ + TMyString::sAddOnStr("-Stop",Text.Text); + }else + if(data == 0xB3){ + TMyString::sAddOnStr("-NFB",Text.Text); + }else + if(data == 0xB5){ + //TMyString::sAddOnStr("-手动停止",Text.Text); + TMyString::sAddOnStr("-Stop",Text.Text); + }else + if(data == 0xB6){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + //TMyString::sAddOnStr("-手动声光停止",Text.Text); + TMyString::sAddOnStr("-Alram Off",Text.Text); + }else + if(data == 0xB7){ + Text.Text[27] = ' '; + Text.Text[28] = '\0'; + TMyString::sAddOnStr("-Hydrant NFB",Text.Text); + }else + if(data == 0x0A){ + TMyString::sAddOnStr("-Act Delay",Text.Text); + } + } + + if(EntryTmp.fData.Body.Splite.Data1 == TControlCenter::StartTypeSimulate) IsSimulate = 1; + return NeedDisplayDescp; +} + + +void TQueryMsgLinkage::FillDescpText(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + if(NeedDisplayDescp){ + //Linkage History + if(IsSimulate){ + if(LanguageEnCn==0)TMyString::sFromStr("模拟",Text.Text); + else TMyString::sFromStr(" SIM",Text.Text); + }else{ + Text.D32[0] = 0x20202020; + } + Text.D32[1] = 0x20202020; + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + Text.D32[4] = 0x20202020; + Text.D32[5] = 0x20202020; + + Addr = Record.Buf4Linkage.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=7; d<15; d++){ + Text.D32[d-1] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[14] =0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + }else{ + if(IsSimulate){ + if(LanguageEnCn==0)TMyString::sFromStr("模拟",Text.Text); + else TMyString::sFromStr(" SIM",Text.Text); + }else{ + Text.D32[0] = 0x20202020; + } + Text.D32[1] = 0x20202020; + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + Text.D32[4] = 0x20202020; + Text.D32[5] = 0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + } +} + +void TQueryMsgLinkage::FillDescpTextEmpty() +{ + Text.Text[0] = ' '; + Text.Text[1] = '\0'; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); +} + + +void TQueryMsgLinkage::DrawListAll(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int TextClr, bClr, Wrote; + int DrawDescp; + + aInx = TopIndex; + Wrote = 0; + for(i=0;i (Count-1))break; + if(SelectedIndex != aInx){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + DrawDescp = FillText(aInx, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = i*2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(aInx); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + aInx++; + Wrote++; + } + for(i=Wrote; i0){ + i = InTimeTopIndex; + for(;i<(InTimeStopIndex+1);i++){ + if(InTimeSelectedIndex != (InTimeTopIndex + Wrote)){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + aInx = InTimeTopIndex - InTimeStartIndex + Wrote; + DrawDescp= FillText(i, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = Wrote *2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(i); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + + Wrote++; + if(Wrote >= ListLineCnt){ + break; + } + } + } + for(i=Wrote; i0){ + SelectedIndex = Count -1; + }else{ + SelectedIndex = TopIndex; + } +} + +unsigned long long TQueryMsgLinkage::aTimeGet(int aInx) +{ + volatile unsigned int SdAddr, Addr; + + //Linkage History + Addr = Record.Buf4Linkage.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + alt.D32.Low4 = *(volatile unsigned int *)(SdAddr + 12); + alt.D32.Hi2 = *(volatile unsigned int *)(SdAddr + 16); + alt.D8[6] = 0; + alt.D8[7] = 0; + return alt.D64; +} + +void TQueryMsgLinkage::GetStartStopTime() +{ + int i; + + RestoreFromEdit(); + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextFrom[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextFrom[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StartTime = alt.D64; + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextTo[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextTo[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StopTime = alt.D64; +} + +void TQueryMsgLinkage::FindInTimeEntry() +{ + int i, aCnt, SatrtFound, StopFound; + unsigned long long aT; + SatrtFound = 0; + StopFound = 0; + InTimeStartIndex = 0; + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT < StartTime){ + InTimeStartIndex = i+1; + if(InTimeStartIndex >(Count-1)){ + SatrtFound = 0; + }else{ + SatrtFound = 1; + } + break; + } + } + if(SatrtFound == 0){ + if(InTimeStartIndex == 0){ + SatrtFound =1; + } + } + if(SatrtFound){ + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT <= StopTime){ + InTimeStopIndex = i; + StopFound = 1; + break; + } + } + if(StopFound == 0){ + InTimeStopIndex = Count-1; + } + if(InTimeStopIndex < InTimeStartIndex){ + InTimeCount = 0; + }else{ + aCnt = InTimeStopIndex - InTimeStartIndex + 1; + if(aCnt <0)aCnt = 0; + InTimeCount = aCnt; + } + + InTimeTopIndex = InTimeStopIndex - ListLineCnt +1; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + }else{ + InTimeCount = 0; + InTimeTopIndex = 0; + InTimeStopIndex = 0; + } +} + + +void TQueryMsgLinkage::GetEntry4Print(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + //Linkage History + NeedDisplayDescp = 0; + + Addr = Record.Buf4Linkage.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=3; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + NeedDisplayDescp = 1; + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + NeedDisplayDescp = 1; + } + + if(NeedDisplayDescp){ + //Linkage History + for(d=7; d<15; d++){ + Text.D32[d-1] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[14] =0; + }else{ + Text.D32[6] = 0; + } +} + +TGuiMsgReturn TQueryMsgLinkage::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + if(IsAllTime){ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = TopIndex -ListLineCnt; + if(aIndex > -1){ + TopIndex = aIndex; + SelectedIndex -= ListLineCnt; + }else{ + if(TopIndex > 0){ + TopIndex = 0; + SelectedIndex = TopIndex; + }else{ + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = TopIndex +ListLineCnt; + if(aIndex < Count){ + TopIndex = aIndex; + SelectedIndex += ListLineCnt; + if(SelectedIndex >= Count){ + SelectedIndex = Count-1; + } + }else{ + TopIndex = 0; + SelectedIndex = TopIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = SelectedIndex -1; + if(aIndex > -1){ + SelectedIndex = aIndex; + if(SelectedIndex < TopIndex){ + TopIndex = SelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = SelectedIndex +1; + if(aIndex < Count){ + SelectedIndex = aIndex; + if(SelectedIndex > (TopIndex + ListLineCnt -1) ){ + TopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + }else{ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = InTimeTopIndex -ListLineCnt; + if(aIndex >= InTimeStartIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex -= ListLineCnt; + }else{ + if(InTimeTopIndex > InTimeStartIndex){ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + }else{ + InTimeTopIndex = InTimeStopIndex - ListLineCnt; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = InTimeTopIndex +ListLineCnt; + if(aIndex <= InTimeStopIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex += ListLineCnt; + if(InTimeSelectedIndex > InTimeStopIndex){ + InTimeSelectedIndex = InTimeStopIndex; + } + }else{ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = InTimeSelectedIndex -1; + if(aIndex >= InTimeStartIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex < InTimeTopIndex){ + InTimeTopIndex = InTimeSelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = InTimeSelectedIndex +1; + if(aIndex <= InTimeStopIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex > (InTimeTopIndex + ListLineCnt -1) ){ + InTimeTopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + } + + if(IsInputTime){ + if(aKey == VK_UP){ + if(TimeEditFrom >0){ + RestoreFromEdit(); + TimeEditFrom =0; + SetEditStart(); + }else{ + if(TimeEditFrom > -1){ + RestoreFromEdit(); + TimeEditFrom = -1; + DrawIfAllTime(); + } + } + }else + if(aKey == VK_DOWN){ + if(TimeEditFrom <1){ + if(IsAllTimeTemp == 0){ + if(TimeEditFrom == 0)RestoreFromEdit(); + TimeEditFrom ++; + SetEditStart(); + DrawIfAllTime(); + } + } + }else + if(aKey == VK_LEFT){ + if(TimeEditFrom > -1){ + if(TimeIndex >0){ + RestoreFromEdit(); + TimeIndex--; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_RIGHT){ + if(TimeEditFrom > -1){ + if(TimeIndex <5){ + RestoreFromEdit(); + TimeIndex++; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_EXECUTE){ + //Read Here + if(IsAllTimeTemp){ + IsAllTime = IsAllTimeTemp; + DrawItemCount(Count); + ReDraw(); + }else{ + IsAllTime = IsAllTimeTemp; + GetStartStopTime(); + FindInTimeEntry(); + DrawItemCount(InTimeCount); + IsInputTime = 0; + RenderContent(); + ReDraw(); + } + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsInputTime = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else{ + if(IsAllTimeTemp == 0){ + if(IsEditing){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + } + } + } + + if(IsGoPrint){ + if(aKey == VK_LEFT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_RIGHT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_EXECUTE){ + //Print Here + if(Count){ + if(SelectedIndex < Count){ + GetEntry4Print(SelectedIndex); + RecordMsg.D32[0] = EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = EntryTmp.fData.UserCode; + DoPrint.PrintHistory(1, RecordMsg, &Text.Text[24]); + } + } + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + } + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TQueryMsgLinkage::Task1000Ms() +{ + if(IsShowing){ + if(Count != Record.Buf4Linkage.Count){ + TopIndex = Count - ListLineCnt +1; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } +} + +int TQueryMsgLinkage::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} diff --git a/MyCode/Gui/QueryMsgLinkage.h b/MyCode/Gui/QueryMsgLinkage.h new file mode 100644 index 0000000..3f46a52 --- /dev/null +++ b/MyCode/Gui/QueryMsgLinkage.h @@ -0,0 +1,26 @@ +#ifndef QUERYMSGLINKAGE_H_ +#define QUERYMSGLINKAGE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "ProtoFecBus.h" + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/QueryMsgOperate.cpp b/MyCode/Gui/QueryMsgOperate.cpp new file mode 100644 index 0000000..ca9fc7f --- /dev/null +++ b/MyCode/Gui/QueryMsgOperate.cpp @@ -0,0 +1,3404 @@ +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" +#include "QueryMessage.h" + +#define TextTopOffSet 6 +#define ListLineCnt 4 +#define ColHeight 33 + +#define FixTop 69 +#define MsgX0 6 +#define DescpX0 270 //90 + +#define dLineMaxLen 64 + +const char cFireCfm[24] = "火警确认 "; +const char cFaultCfm[24] = "故障确认 "; +const char cFireRemoteCfm[24] = "火警远程确认 "; +const char cFaultRemoteCfm[24] = "故障远程确认 "; + +const char cFireSimCfm[24] = "模拟火警确认 "; +const char cFireSimRemoteCfm[24] = "模拟火警远程确认 "; + +const char cFireCfmEn[24] = "Confirmed Fire "; +const char cFaultCfmEn[24] = "Confirmed Fault "; +const char cFireRemoteCfmEn[24] = "Confirmed-Far Fire "; +const char cFaultRemoteCfmEn[24] = "Confirmed-Far Fault "; + +const char cFireSimCfmEn[24] = "Confirmed Sim-Fire "; +const char cFireSimRemoteCfmEn[24] = "Confirmed-Far Sim-Fire"; //Length = 22 + +const char cMask[24] = "屏蔽部件 "; +const char cMaskEn[24] = "Blocked Device "; +const char cUnMask[24] = "取消屏蔽部件 "; +const char cUnMaskEn[24] = "Blocked Device Cancel "; + +const static unsigned short stAllTop[10] = { + 80, 120, 160, 200, 240, + 280, 320, 360, 400, 440 +}; + +static const short qmFixCol[8] = { + 20,100,160,240, 320,400,520,600 +}; + +void TQueryMsgOperate::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + BoxBoundTime.Set(Left+170, Top+80, Right-170, Bottom-30); + GoPrint.Set(Left+170, Top+150, Right-170, Bottom-130); + Color = aColor; + #undef CH + + + Caption.Border.Color = clGray; + + FixColColor = clMaroon; + FixColTextColor = clNearWhite; + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; +} + +void TQueryMsgOperate::InitBackEnd() +{ + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; +} + +void TQueryMsgOperate::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8) +{ + +} + +void TQueryMsgOperate::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgOperate::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TQueryMsgOperate::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgOperate::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TQueryMsgOperate::DrawCaption(void) +{ + if(LanguageEnCn==0)TMyString::sFromStr("历史记录->查询操作信息", Caption.Text); + else TMyString::sFromStr("Recorded Info->Query Operations", Caption.Text); + + Caption.Show(); + DrawCaption2(); +} + +void TQueryMsgOperate::DrawCaption2(void) +{ + +} + +void TQueryMsgOperate::RenderWarningWait(void) +{ + int x,y,x2,y2, aW,aH; + x = 200; + y = 160; + x2 = 600; + y2 = 290; + aW = x2 - x +1; + aH = y2 - y +1; + VertLineRender(x, y, aH-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y+1, aH -2, 0xFF808080); + VertLineRender(x2, y, aH, 0xFF404040); + + HorizLineRender(x, y, aW - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, aW - 2, 0xFF808080); + HorizLineRender(x, y2, aW, 0xFF404040); + + RectFillRender(x+1,y+1,x2-2,y+30,clNavy); + RectFillRender(x+1,y+31,x2-2,y2-2,clGray); + if(LanguageEnCn==0){ + TextRender_string24(x+8, y+6, clNearWhite, "提示信息"); + TextRender_string24(x+66, y+36, clNearBlack, "正在读取,请等待"); + }else{ + TextRender_string24(x+8, y+6, clNearWhite, "Message"); + TextRender_string24(x+66, y+36, clNearBlack, "Reading,Please Wait"); + } +} + +void TQueryMsgOperate::DrawItemCount(int aCount) +{ + TextDigitRender6Left24(500,Caption.Bound.Top +3, clNearWhite, Caption.Color, Count); + TextDigitRender6Left24(720,Caption.Bound.Top +3, clNearWhite, Caption.Color, aCount); + if(LanguageEnCn==0){ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "总数量:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "查看数量:"); + }else{ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "Total:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "Display:"); + } +} + +void TQueryMsgOperate::DrawBoxTimeOutLine() +{ + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + + VertLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Height -1, 0xFFFFFFFF); + VertLineRender(BoxBoundTime.Right -1, BoxBoundTime.Top +1, BoxBoundTime.Height -2, 0xFF808080); + VertLineRender(BoxBoundTime.Right, BoxBoundTime.Top, BoxBoundTime.Height, 0xFF404040); + + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Width - 1, 0xFFFFFFFF); + HorizLineRender(BoxBoundTime.Left +1, BoxBoundTime.Bottom -1, BoxBoundTime.Width - 2, 0xFF808080); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom, BoxBoundTime.Width, 0xFF404040); + + if(LanguageEnCn==0) TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "设置日期时间段,按确认键开始查询"); + else TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "Set Date And Time,OK Key:Start The Query"); +} + +void TQueryMsgOperate::DrawTimeEntry(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + vtValueFrom[0] = DateTime.Date.Split.Year; + vtValueFrom[1] = DateTime.Date.Split.Month; + vtValueFrom[2] = DateTime.Date.Split.Day; + + vtValueFrom[3] = DateTime.Time.Split.Hour; + vtValueFrom[4] = DateTime.Time.Split.Minute; + vtValueFrom[5] = DateTime.Time.Split.Second; + + vtValueTo[0] =vtValueFrom[0]; + vtValueTo[1] =vtValueFrom[1]; + vtValueTo[2] =vtValueFrom[2]; + vtValueTo[3] =vtValueFrom[3]; + vtValueTo[4] =vtValueFrom[4]; + vtValueTo[5] =vtValueFrom[5]; + + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + + +void TQueryMsgOperate::DrawTimeEntryNoUpdate(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + +void TQueryMsgOperate::DrawIfAllTime(void) +{ + unsigned int aClr, bClr; + if(TimeEditFrom == -1){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + TTriangleLeftRight::sDrawLeftByHight(BoxBoundTime.Left + 150 - 20, BoxBoundTime.Top + 44, 20, clBlue); + TTriangleLeftRight::sDrawRightByHight(BoxBoundTime.Left + 150 + 106, BoxBoundTime.Top + 44, 20, clBlue); + if(LanguageEnCn==0){ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "全部条目"); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "按时间段"); + } + }else{ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, " All "); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "Segments"); + } + } +} + +void TQueryMsgOperate::DrawBoxTimeString(void) +{ + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + if(LanguageEnCn==0){ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "开始时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, "年 月 日 时 分 秒"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "结束时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, "年 月 日 时 分 秒"); + }else{ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "Begin"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, " Y M D H M S"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "End"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, " Y M D H M S"); + } +} + +void TQueryMsgOperate::DrawBoxTime(void) +{ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); +} + +void TQueryMsgOperate::DrawGoPrintOutLine() +{ + RectFillRender(GoPrint.Left, GoPrint.Top, GoPrint.Right, GoPrint.Bottom, clFrmFace); + + VertLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Height -1, 0xFFFFFFFF); + VertLineRender(GoPrint.Right -1, GoPrint.Top +1, GoPrint.Height -2, 0xFF808080); + VertLineRender(GoPrint.Right, GoPrint.Top, GoPrint.Height, 0xFF404040); + + HorizLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Width - 1, 0xFFFFFFFF); + HorizLineRender(GoPrint.Left +1, GoPrint.Bottom -1, GoPrint.Width - 2, 0xFF808080); + HorizLineRender(GoPrint.Left, GoPrint.Bottom, GoPrint.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "按确认键开始打印并返回"); + else TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "Confirm Print Or Return"); +} + +void TQueryMsgOperate::DrawPrintWhat() +{ + if(LanguageEnCn==0)TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "打印当前选定条目"); + else TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "Print Current Item"); + return; + if(PrintWhat == 0){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, "当前选定条目"); + }else + if(PrintWhat == 1){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 当前页面 "); + }else{ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 全部信息 "); + } +} + +void TQueryMsgOperate::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } + DrawItemCount(Count); + ShowTip(); +} + +void TQueryMsgOperate::ReDraw(void) +{ + Caption.Enable = 1; + //DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } +} + + +void TQueryMsgOperate::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + DrawItemCount(Count); + ShowTip(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + ShowTip(); + } +} + + +void TQueryMsgOperate::ShowTip() +{ + if(LanguageEnCn==0){ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, TAB键去打印"); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "上下左右键切换或编辑条目, 数字键删除键编辑 "); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "按确定键打印当前条目 "); + } + }else{ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down:Switch item; TAB To Print "); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down To Switch Item To Edit; Num Key To Edit"); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "Press The OK Key To Print The Current Item "); + } + } +} + +void TQueryMsgOperate::SetEditStart(void) +{ + int x,y,w,h; + + IsEditing =1; + + ReStoreP0 = TimeEditFrom; + ReStoreP1 = TimeIndex; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + vEdit.Init(x,y,w,h,0,0,1,clTeal); + vEdit.Color = clTeal; + vEdit.SetMaxLen(2); + if(ReStoreP0 ==0){ + vEdit.Str.Text[0] = vtTextFrom[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextFrom[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + }else + if(ReStoreP0 ==1){ + vEdit.Str.Text[0] = vtTextTo[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextTo[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + } + vEdit.Pst = -1; + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); +} + +void TQueryMsgOperate::RestoreFromEdit(void) +{ + int x,y,w,h; + + if(IsEditing == 0)return; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + if(ReStoreP0 == 0){ + vtTextFrom[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextFrom[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextFrom[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[ReStoreP1]); + }else + if(ReStoreP0 == 1){ + vtTextTo[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextTo[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextTo[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[ReStoreP1]); + } + IsEditing = 0; +} + +void TQueryMsgOperate::FillTextWithDateTime() +{ + int aLen; + aLen = TMyString::sGetLen(Text.Text); + if(aLen < 40){ + CoverDateTimeIllegal(EntryTmp.fData.Body, &DateTimeCovered); + Text.Text[aLen + 0] = DateTimeCovered.Year / 16 % 10 + '0'; + Text.Text[aLen + 1] = DateTimeCovered.Year % 16 % 10+ '0'; + Text.Text[aLen + 2] = '/'; + Text.Text[aLen + 3] = DateTimeCovered.Month / 16 % 10 + '0'; + Text.Text[aLen + 4] = DateTimeCovered.Month % 16 % 10 + '0'; + Text.Text[aLen + 5] = '/'; + Text.Text[aLen + 6] = DateTimeCovered.Day / 16 % 10 + '0'; + Text.Text[aLen + 7] = DateTimeCovered.Day % 16 % 10 + '0'; + Text.Text[aLen + 8] = ' '; + Text.Text[aLen + 9] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text.Text[aLen + 10] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text.Text[aLen + 11] = ':'; + Text.Text[aLen + 12] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text.Text[aLen +13] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text.Text[aLen +14] = ':'; + Text.Text[aLen +15] = DateTimeCovered.Second / 16 % 10 + '0'; + Text.Text[aLen +16] = DateTimeCovered.Second % 16 % 10 + '0'; + + Text.Text[aLen +17] = ' '; + Text.Text[aLen +18] = '\0'; + } +} + +void TQueryMsgOperate::FillTextWithPath() +{ + int aLen; + unsigned int data, d,e; + aLen = TMyString::sGetLen(Text.Text); + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + Text.Text[aLen + 0] = e + '0'; + e = data % 10; + Text.Text[aLen + 1] = e + '0'; + Text.Text[aLen + 2] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + Text.Text[aLen + 3] = e + '0'; + e = data % 10; + Text.Text[aLen + 4] = e + '0'; + Text.Text[aLen + 5] = '-'; + + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + Text.Text[aLen + 6] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[aLen + 7] = e + '0'; + e = data % 10; + Text.Text[aLen + 8] = e + '0'; + Text.Text[aLen + 9] = ' '; + + Text.Text[aLen +10] = ' '; + Text.Text[aLen +11] = '\0'; +} + +void TQueryMsgOperate::FillTextWithDType() +{ + unsigned char aType; + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text.Text); + TMyString::sAddOnStr(" ",Text.Text); +} + +void TQueryMsgOperate::FillCtlNum() +{ + if(EntryTmp.fData.Body.Splite.PCtlNum == 0){ + if(LanguageEnCn==0)TMyString::sAddOnStr("本机 ",Text.Text); + else TMyString::sAddOnStr("Local",Text.Text); + }else{ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum,Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + } +} + +void TQueryMsgOperate::FillCtlNumNoSpace() +{ + if(EntryTmp.fData.Body.Splite.PCtlNum == 0){ + if(LanguageEnCn==0)TMyString::sAddOnStr("本机 ",Text.Text); + else TMyString::sAddOnStr("Local",Text.Text); + }else{ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum,Text.Text); + } +} + +void TQueryMsgOperate::FillText4PowerOff() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("关机 ",Text.Text); + else TMyString::sAddOnStr("Power Off ",Text.Text); +} + +void TQueryMsgOperate::FillText4PowerUp() +{ + + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("开机 ",Text.Text); + else TMyString::sAddOnStr("Power On ",Text.Text); +} + +void TQueryMsgOperate::FillText4MsgReset(unsigned char Data1) +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("手动复位 ",Text.Text); + if(Data1){ + TMyString::sAddOnStr("集中机呼叫执行 ",Text.Text); + } + }else{ + TMyString::sAddOnStr("Manual Reset ",Text.Text); + if(Data1){ + TMyString::sAddOnStr("Call By Master ",Text.Text); + } + } +} + +void TQueryMsgOperate::FillText4MsgMute() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("手动消音 ",Text.Text); + else TMyString::sAddOnStr("Manual Mute ",Text.Text); +} + +void TQueryMsgOperate::FillText4MsgMask() +{ + FillTextWithDateTime(); + FillCtlNum(); + FillTextWithPath(); + AddOnUserCode(); + FillTextWithDType(); +} + +void TQueryMsgOperate::FillText4MsgUnMask() +{ + FillTextWithDateTime(); + FillCtlNum(); + FillTextWithPath(); + AddOnUserCode(); + FillTextWithDType(); +} + +void TQueryMsgOperate::FillText4AllowSet() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("设置允许状态 ",Text.Text); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01){ + TMyString::sAddOnStr("自动允许 ",Text.Text); + }else{ + TMyString::sAddOnStr("自动禁止 ",Text.Text); + } + if(EntryTmp.fData.Body.Splite.Data1 & 0x02){ + TMyString::sAddOnStr("手动允许 ",Text.Text); + }else{ + TMyString::sAddOnStr("手动禁止 ",Text.Text); + } + }else{ + TMyString::sAddOnStr("Set Operating ",Text.Text); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01){ + TMyString::sAddOnStr("Auto ",Text.Text); + }else{ + TMyString::sAddOnStr("Not Auto ",Text.Text); + } + if(EntryTmp.fData.Body.Splite.Data1 & 0x02){ + TMyString::sAddOnStr("Manual Allow ",Text.Text); + }else{ + TMyString::sAddOnStr("Manual Not Allow",Text.Text); + } + } +} + +void TQueryMsgOperate::FillText4AlramSetOnOff() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("警报声光 ",Text.Text); + if(EntryTmp.fData.Body.Splite.Data1){ + TMyString::sAddOnStr("启动 ",Text.Text); + }else{ + TMyString::sAddOnStr("停止 ",Text.Text); + } + }else{ + TMyString::sAddOnStr("Alarm SL ",Text.Text); + if(EntryTmp.fData.Body.Splite.Data1){ + TMyString::sAddOnStr("Active ",Text.Text); + }else{ + TMyString::sAddOnStr("Stop ",Text.Text); + } + } +} + +void TQueryMsgOperate::FillText4MsgDateTimeSet() +{ + int aLen; + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("设置日期时间为 ",Text.Text); + else TMyString::sAddOnStr("Set Datetime: ",Text.Text); + + aLen = TMyString::sGetLen(Text.Text); + if(aLen < 46){ + Text.Text[aLen + 0] = EntryTmp.fData.Body.Splite.P0 / 16 % 10 + '0'; + Text.Text[aLen + 1] = EntryTmp.fData.Body.Splite.P0 % 16 % 10 + '0'; + Text.Text[aLen + 2] = '-'; + Text.Text[aLen + 3] = EntryTmp.fData.Body.Splite.P1 / 16 % 10 + '0'; + Text.Text[aLen + 4] = EntryTmp.fData.Body.Splite.P1 % 16 % 10 + '0'; + Text.Text[aLen + 5] = '-'; + Text.Text[aLen + 6] = EntryTmp.fData.Body.Splite.P2 / 16 % 10 + '0'; + Text.Text[aLen + 7] = EntryTmp.fData.Body.Splite.P2 % 16 % 10 + '0'; + Text.Text[aLen + 8] = ' '; + Text.Text[aLen + 9] = EntryTmp.fData.Body.Splite.Data1 / 16 % 10 + '0'; + Text.Text[aLen +10] = EntryTmp.fData.Body.Splite.Data1 % 16 % 10 + '0'; + Text.Text[aLen +11] = ':'; + Text.Text[aLen +12] = EntryTmp.fData.Body.Splite.iByte0 / 16 % 10 + '0'; + Text.Text[aLen +13] = EntryTmp.fData.Body.Splite.iByte0 % 16 % 10 + '0'; + Text.Text[aLen +14] = ':'; + Text.Text[aLen +15] = EntryTmp.fData.Body.Splite.iByte1 / 16 % 10 + '0'; + Text.Text[aLen +16] = EntryTmp.fData.Body.Splite.iByte1 % 16 % 10 + '0'; + + Text.Text[aLen +17] = ' '; + Text.Text[aLen +18] = '\0'; + } +} + +void TQueryMsgOperate::FillText4BusPadOn() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("总线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" 按键 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" 手动启动 ",Text.Text); + }else{ + TMyString::sAddOnStr("BusPad ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" Pad ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" Active ",Text.Text); + } +} + +void TQueryMsgOperate::FillText4BusPadOff() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("总线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" 按键 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" 手动关闭 ",Text.Text); + }else{ + TMyString::sAddOnStr("BusPad ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" Pad ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" DeActive ",Text.Text); + } +} + +void TQueryMsgOperate::FillText4DirectPadManualAllowOn() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("多线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" 手动允许 ",Text.Text); + }else{ + TMyString::sAddOnStr("DirectCtrl ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" Allowed ",Text.Text); + } +} + +void TQueryMsgOperate::FillText4DirectPadManualAllowOff() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("多线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" 手动禁止 ",Text.Text); + }else{ + TMyString::sAddOnStr("DirectCtrl ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" Locked ",Text.Text); + } +} + +void TQueryMsgOperate::FillText4DirectPadNodeOn() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("多线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" 节点 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" 手动开启 ",Text.Text); + }else{ + TMyString::sAddOnStr("DirectCtrl ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" Node ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" Active ",Text.Text); + } +} + +void TQueryMsgOperate::FillText4DirectPadNodeOff() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("多线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" 节点 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" 手动关闭 ",Text.Text); + }else{ + TMyString::sAddOnStr("DirectCtrl ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + TMyString::sAddOnStr(" Node ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" Stop ",Text.Text); + } +} + +void TQueryMsgOperate::FillText4UserCheck() +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("检查 ",Text.Text); + else TMyString::sAddOnStr("User Check ",Text.Text); +} + +void TQueryMsgOperate::FillText4LinkageGo(unsigned char Data1) +{ + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("联动执行",Text.Text); + if(Data1 == 0){ + TMyString::sAddOnStr("-区域机报告",Text.Text); + }else + if(Data1 == 1){ + TMyString::sAddOnStr("-本机执行",Text.Text); + }else + if(Data1 == 3){ + TMyString::sAddOnStr("-集中机呼叫执行",Text.Text); + } + }else{ + TMyString::sAddOnStr("Linkage Exe",Text.Text); + if(Data1 == 0){ + TMyString::sAddOnStr("-Slave Reported",Text.Text); + }else + if(Data1 == 1){ + TMyString::sAddOnStr("-Self Execute",Text.Text); + }else + if(Data1 == 3){ + TMyString::sAddOnStr("-Call By Master",Text.Text); + } + } +} + +void TQueryMsgOperate::AddOnUserCode() +{ + TMyString::sAddOn8Dg(EntryTmp.fData.UserCode, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); +} + +void TQueryMsgOperate::AddOnFireMsg() +{ + unsigned char aType; + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text.Text); +} + +void TQueryMsgOperate::AddOnFaultMsg() +{ + unsigned char aType; + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xC0){ + FillCtlNum(); + if(LanguageEnCn==0){ + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("总线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,Text.Text); + TMyString::sAddOnStr(" 离线",Text.Text); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("多线盘 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,Text.Text); + TMyString::sAddOnStr(" 离线",Text.Text); + } + }else{ + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("BusPad Board ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,Text.Text); + TMyString::sAddOnStr(" Offline",Text.Text); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("Direct Ctrl Board ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,Text.Text); + TMyString::sAddOnStr(" Offline",Text.Text); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xD0){ + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("设备故障 ",Text.Text); + else TMyString::sAddOnStr("Device Fault ",Text.Text); + aType = EntryTmp.fData.Body.Splite.P2; + if(LanguageEnCn==0){ + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultType[aType],Text.Text); + }else{ + TMyString::sAddOnStr("未知错误",Text.Text); + } + }else{ + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultTypeEn[aType],Text.Text); + }else{ + TMyString::sAddOnStr("Unknown Fault",Text.Text); + } + } + TMyString::sAddOnStr(" ",Text.Text); + if( (aType == 15) || (aType == 16) ){ + Text.Text[28] = '\0'; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrDevFaultType[aType],Text.Text); + else TMyString::sAddOnStr(StrDevFaultTypeEn[aType],Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + if(LanguageEnCn==0)TMyString::sAddOnStr("通讯故障",Text.Text); + else TMyString::sAddOnStr("Offline",Text.Text); + //if(EntryTmp.fData.Body.Splite.mType > 200){ + // TMyString::sAddOnStr("通讯故障条目数:多于200",Text.Text); + //}else{ + // TMyString::sAddOnStr("通讯故障条目数:",Text.Text); + // TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.mType, Text.Text); + //} + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xE0){ + FillCtlNum(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,Text.Text); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 回路故障",Text.Text); + else TMyString::sAddOnStr(" Loop Fault",Text.Text); + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("板卡故障 ",Text.Text); + else TMyString::sAddOnStr("Board Fault",Text.Text); + aType = EntryTmp.fData.Body.Splite.P2; + if(aType == 10){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + } + if(LanguageEnCn==0){ + if(aType < 32){ + TMyString::sAddOnStr(StrBrdFaultType[aType],Text.Text); + }else{ + TMyString::sAddOnStr("未知类型",Text.Text); + } + }else{ + if(aType < 32){ + TMyString::sAddOnStr(StrBrdFaultTypeEn[aType],Text.Text); + }else{ + TMyString::sAddOnStr("Unknown Fault",Text.Text); + } + } + }else{ + //EpError + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + + aType = EntryTmp.fData.Body.Splite.P2; + if(LanguageEnCn==0){ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultType[aType],Text.Text); + }else{ + TMyString::sAddOnStr("未知故障",Text.Text); + } + }else{ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultTypeEn[aType],Text.Text); + }else{ + TMyString::sAddOnStr("Unknown Fault",Text.Text); + } + } + } +} + +int TQueryMsgOperate::FillTextCN(int aInx, int ShowInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned int ExpsInx; + + NeedDisplayDescp = 0; + NeedDrawCfg = 0; + + //Operate History + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=2; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + Text.Text[7] = '\0'; + + if(EntryTmp.fData.Body.Splite.mType == etOperate){ + switch(EntryTmp.fData.Body.Splite.Data0){ + case otPowerOff: + FillText4PowerOff(); + break; + case otPowerOn: + FillText4PowerUp(); + break; + case otReset: + FillText4MsgReset(EntryTmp.fData.Body.Splite.Data1); + break; + case otMute: + FillText4MsgMute(); + break; + case otMask: + FillText4MsgMask(); + NeedDisplayDescp =1; + NeedDrawCfg =0xB1; + break; + case otUnMask: + FillText4MsgUnMask(); + NeedDisplayDescp =1; + NeedDrawCfg =0xB0; + break; + case otRegiste: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("开始注册设备",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("设备注册成功",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("呼叫区域机注册",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr("集中机呼叫注册",Text.Text); + } + break; + case otUnRegiste: + + + break; + case otSetCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("设置本机为集中机:",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("设置本机为区域机:",Text.Text); + }else{ + TMyString::sAddOnStr("设置本机为单机:",Text.Text); + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + break; + case otCfgBoard: + + break; + case otCfgCrt: + + break; + case otCfgPriter: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("打印机关闭",Text.Text); + }else{ + TMyString::sAddOnStr("打印机开启",Text.Text); + } + if(1){ + TMyString::sAddOnStr("打印:",Text.Text); + data = 0; + if(EntryTmp.fData.Body.Splite.P0 & 0x01){ + TMyString::sAddOnStr("全部",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x02){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("火警",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x04){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("联动",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x08){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("监管",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x10){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("故障",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x20){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("屏蔽",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x40){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("操作",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x80){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("其他",Text.Text); + data++; + } + if(data == 0){ + TMyString::sAddOnStr("全部类型信息不打印",Text.Text); + } + } + break; + case otCfgDevice: + + NeedDisplayDescp = 1; + break; + case otCfgDateTime: + FillText4MsgDateTimeSet(); + break; + case otCfgPermissionAllow: + + break; + case otAllowSet: + FillText4AllowSet(); + break; + case otAlramSetOnOff: + FillText4AlramSetOnOff(); + break; + case otBusPadOn: + FillText4BusPadOn(); + break; + case otBusPadOff: + FillText4BusPadOff(); + break; + case otDirectPadManualAllowOn: + FillText4DirectPadManualAllowOn(); + break; + case otDirectPadManualAllowOff: + FillText4DirectPadManualAllowOff(); + break; + case otDirectPadNodeOn: + FillText4DirectPadNodeOn(); + break; + case otDirectPadNodeOff: + FillText4DirectPadNodeOff(); + break; + case otUserCheck: + FillText4UserCheck(); + break; + case otLinkageGo: + FillText4LinkageGo(EntryTmp.fData.Body.Splite.Data1); + break; + case otSetNwTime: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("设置各区域机日期时间",Text.Text); + break; + case otReqNwTime: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("向集中机请求日期时间",Text.Text); + break; + case otSelfCheck: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("自检",Text.Text); + break; + case otSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许",Text.Text); + else TMyString::sAddOnStr("手动禁止",Text.Text); + break; + case otSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许",Text.Text); + else TMyString::sAddOnStr("自动禁止",Text.Text); + break; + case otRemoteSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许-集中机呼叫执行",Text.Text); + else TMyString::sAddOnStr("手动禁止--集中机呼叫执行",Text.Text); + break; + case otRemoteSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许-集中机呼叫执行",Text.Text); + else TMyString::sAddOnStr("自动禁止--集中机呼叫执行",Text.Text); + break; + case otReportManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许-区域机报告",Text.Text); + else TMyString::sAddOnStr("手动禁止-区域机报告",Text.Text); + break; + case otReportAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许-区域机报告",Text.Text); + else TMyString::sAddOnStr("自动禁止-区域机报告",Text.Text); + break; + case otFireConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警确认 ",Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 1; + NeedDrawCfg =1; + break; + case otFireSimConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警确认 ",Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 1; + NeedDrawCfg =11; + break; + case otFireRemoteConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警远程确认 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 3; + NeedDrawCfg = 3; + break; + case otFireSimRemoteConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警远程确认 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 3; + NeedDrawCfg = 13; + break; + case otFaultConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + NeedDisplayDescp = 1; + } + AddOnFaultMsg(); + NeedDrawCfg = 2; + break; + case otFaultRemoteConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + NeedDisplayDescp = 1; + } + /*if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("故障远程确认 ",Text.Text); + //TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text); + NeedDisplayDescp = 1; + NeedDrawCfg = 2; + }else{ + FillCtlNum(); + TMyString::sAddOnStr(" 故障远程确认 ",Text.Text); + //TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text); + NeedDrawCfg = 2; + }*/ + AddOnFaultMsg(); + NeedDrawCfg = 4; + break; + case otSetSmokeSensViaCircuit: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 低",Text.Text); + TMyString::sAddOnStr(" 回路烟感设置敏感度为 标准",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 中",Text.Text); + TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",Text.Text); + TMyString::sAddOnStr(" 回路烟感设置敏感度为 未定义",Text.Text); + }else{ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 未定义",Text.Text); + } + break; + case otSetSmokeSensViaAddr: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + //TMyString::sAddOnStr("烟感设置敏感度 低",Text.Text); + TMyString::sAddOnStr("烟感设置敏感度 标准",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + //TMyString::sAddOnStr("回路烟感设置敏感度为 中",Text.Text); + TMyString::sAddOnStr("烟感设置敏感度 高",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",Text.Text); + TMyString::sAddOnStr("烟感设置敏感度 未知",Text.Text); + }else{ + TMyString::sAddOnStr("烟感设置敏感度 未知",Text.Text); + } + NeedDisplayDescp = 1; + break; + case otCleanUp: + FillTextWithDateTime(); + FillCtlNum(); + //aPanel->Btn[0].Caption.FromStr(" 清除回路终端设备的登记 "); + //aPanel->Btn[1].Caption.FromStr(" 清除总线盘配置 "); + //aPanel->Btn[2].Caption.FromStr(" 清除多线盘配置 "); + //aPanel->Btn[3].Caption.FromStr(" 清除所有联动表达式 "); + //aPanel->Btn[4].Caption.FromStr(" 清除本机终端设备注释 "); + //aPanel->Btn[5].Caption.FromStr(" 清除组网配置 "); + //aPanel->Btn[6].Caption.FromStr(" 清除网络加载的设备注释 "); + //aPanel->Btn[7].Caption.FromStr(" 预设描述 "); + + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("清除回路注册",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("清除总线盘配置",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("清除多线盘配置",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("清除所有联动表达式 ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr("清除本机终端设备注释",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 5){ + TMyString::sAddOnStr("清除组网配置",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 6){ + TMyString::sAddOnStr("清除网络加载的设备注释",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 7){ + TMyString::sAddOnStr("清除用户码及指派类型",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF0){ + TMyString::sAddOnStr("清除回路注册-中途退出",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF3){ + TMyString::sAddOnStr("清除联动关系-中途退出",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF4){ + TMyString::sAddOnStr("清除注释-中途退出",Text.Text); + } + break; + case otLinkageExpsSaveRemove: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("保存一个联动表达式 编号:",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("删除一个联动表达式 编号:",Text.Text); + } + ExpsInx = EntryTmp.fData.Body.Splite.P0; + ExpsInx = ExpsInx * 256; + ExpsInx = ExpsInx + EntryTmp.fData.Body.Splite.P1; + TMyString::sAddOn4Dg(ExpsInx, Text.Text); + break; + case otBusPadModify: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("总线盘:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr(" 按键号:",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" 配置",Text.Text); + break; + case otDirectPadModify: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("多线盘:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr(" 配置",Text.Text); + break; + case otDescpModify: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + if(EntryTmp.fData.Body.Splite.P0 <= dPORT_MAX_COUNT){ + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("设备描述更改 ",Text.Text); + NeedDisplayDescp = 1; + }else + if( (EntryTmp.fData.Body.Splite.P0 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P0 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("多线盘:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0-dADDR_DIRECTPAD_START+1, Text.Text); + TMyString::sAddOnStr(" 节点:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" 描述更改 ",Text.Text); + NeedDisplayDescp = 1; + } + break; + case otPassWdModify: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 二级密码更改",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" 三级密码更改",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 12){ + TMyString::sAddOnStr(" 系统故障,二级密码写入失败",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 13){ + TMyString::sAddOnStr(" 系统故障,三级密码写入失败",Text.Text); + } + break; + case otRegisterByManual: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + if(EntryTmp.fData.Body.Splite.Data1){ + TMyString::sAddOnStr("手动注册,类型:",Text.Text); + TMyString::sAddOnStr(StrTypeShortName[EntryTmp.fData.Body.Splite.dType],Text.Text); + }else{ + TMyString::sAddOnStr("手动注册,删除",Text.Text); + } + + break; + case otAddRemoveNwCtl: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 手动添加区域机 ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 手动删除区域机 ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" 手动添加集中机 ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr(" 手动删除集中机 ",Text.Text); + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + break; + case otRegCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("本集中机注册区域机数量:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + }else{ + TMyString::sAddOnStr("本集中机清除联机区域机",Text.Text); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("本区域机联机注册,集中机号:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + }else{ + TMyString::sAddOnStr("本区域机联机清除,集中机号:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("设置网络共存集中机数量:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + }else{ + TMyString::sAddOnStr("清除网络共存集中机:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + } + } + break; + case otClearNetworkCfg: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("清除所有区域机",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("清除挂载的集中机",Text.Text); + } + break; + case otBroadcastVa: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("设置广播与声光 路径:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" 并行模式",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 交替模式",Text.Text); + } + break; + + case otSetAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("自动允许-手动允许",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动允许-手动禁止",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("自动禁止-手动允许",Text.Text); + else TMyString::sAddOnStr("自动禁止-手动禁止",Text.Text); + break; + case otRemoteSetAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("自动允许-手动允许-集中机呼叫执行",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动允许-手动禁止-集中机呼叫执行",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("自动禁止-手动允许-集中机呼叫执行",Text.Text); + else TMyString::sAddOnStr("自动禁止-手动禁止-集中机呼叫执行",Text.Text); + break; + case otReportAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("自动允许-手动允许-区域机报告",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动允许-手动禁止-区域机报告",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动禁止-手动允许-区域机报告",Text.Text); + else TMyString::sAddOnStr("自动禁止-手动禁止-区域机报告",Text.Text); + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("自动允许-手动允许-区域机报告",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动允许-手动禁止-区域机报告",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动禁止-手动允许-区域机报告",Text.Text); + else TMyString::sAddOnStr("自动禁止-手动禁止-区域机报告",Text.Text); + } + break; + } + } + if(0){ + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + + Text.Text[7] = EntryTmp.fData.Body.Splite.Month / 16 % 10 + '0'; + Text.Text[8] = EntryTmp.fData.Body.Splite.Month % 16 + '0'; + Text.Text[9] = '-'; + Text.Text[10] = EntryTmp.fData.Body.Splite.Day / 16 % 10 + '0'; + Text.Text[11] = EntryTmp.fData.Body.Splite.Day % 16 + '0'; + Text.Text[12] = ' '; + Text.Text[13] = EntryTmp.fData.Body.Splite.Hour / 16 % 10 + '0'; + Text.Text[14] = EntryTmp.fData.Body.Splite.Hour % 16 + '0'; + Text.Text[15] = ':'; + Text.Text[16] = EntryTmp.fData.Body.Splite.Minute / 16 % 10 + '0'; + Text.Text[17] = EntryTmp.fData.Body.Splite.Minute % 16 + '0'; + Text.Text[18] = ':'; + Text.Text[19] = EntryTmp.fData.Body.Splite.Second / 16 % 10 + '0'; + Text.Text[20] = EntryTmp.fData.Body.Splite.Second % 16 + '0'; + Text.Text[21] = ' '; + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + Text.Text[22] = e + '0'; + e = data % 10; + Text.Text[23] = e + '0'; + Text.Text[24] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + Text.Text[25] = e + '0'; + e = data % 10; + Text.Text[26] = e + '0'; + Text.Text[27] = '-'; + + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + Text.Text[28] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[29] = e + '0'; + e = data % 10; + Text.Text[30] = e + '0'; + Text.Text[31] = ' '; + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if( (aP0 >0) && (aP0 < 64) ){ + if(aP1 >0){ + if(aP0 < 40){ + aP0--; + data = Port[aP0].UcList[aP1-1].Full; + } + } + } + d = data/10000; + e = d % 10; + Text.Text[32] = e + '0'; + d = data/1000; + e = d % 10; + Text.Text[33] = e + '0'; + d = data/100; + e = d % 10; + Text.Text[34] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[35] = e + '0'; + e = data % 10; + Text.Text[36] = e + '0'; + Text.Text[37] = ' '; + + Text.Text[38] = 0; + + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + //TMyString::sAddOnStr(" ",Text); + //TMyString::sAddOnStrL32(EntryTmp.fData.Descp, Text); + } + return NeedDisplayDescp; +} + + +int TQueryMsgOperate::FillTextEN(int aInx, int ShowInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned int ExpsInx; + + NeedDisplayDescp = 0; + NeedDrawCfg = 0; + + //Operate History + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=2; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + Text.Text[7] = '\0'; + + if(EntryTmp.fData.Body.Splite.mType == etOperate){ + switch(EntryTmp.fData.Body.Splite.Data0){ + case otPowerOff: + FillText4PowerOff(); + break; + case otPowerOn: + FillText4PowerUp(); + break; + case otReset: + FillText4MsgReset(EntryTmp.fData.Body.Splite.Data1); + break; + case otMute: + FillText4MsgMute(); + break; + case otMask: + FillText4MsgMask(); + NeedDisplayDescp =1; + NeedDrawCfg =0xB1; + break; + case otUnMask: + FillText4MsgUnMask(); + NeedDisplayDescp =1; + NeedDrawCfg =0xB0; + break; + case otRegiste: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Start Register",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("Regist Succeed",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("Call Slaver To Register",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr("Do Register Call By Master",Text.Text); + } + break; + case otUnRegiste: + + + break; + case otSetCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Set To Master:",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("Set To Slaver:",Text.Text); + }else{ + TMyString::sAddOnStr("Set To Single:",Text.Text); + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + break; + case otCfgBoard: + + break; + case otCfgCrt: + + break; + case otCfgPriter: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("Print Off ",Text.Text); + }else{ + TMyString::sAddOnStr("Print On ",Text.Text); + } + if(1){ + TMyString::sAddOnStr("Print:",Text.Text); + data = 0; + if(EntryTmp.fData.Body.Splite.P0 & 0x01){ + TMyString::sAddOnStr("All",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x02){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("Fire",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x04){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("Link",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x08){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("Supv",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x10){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("Fail",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x20){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("Mask",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x40){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("OPR.",Text.Text); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x80){ + if(data)TMyString::sAddOnStr("+",Text.Text); + TMyString::sAddOnStr("Oth.",Text.Text); + data++; + } + if(data == 0){ + TMyString::sAddOnStr("Not Print Any Type",Text.Text); + } + } + break; + case otCfgDevice: + + NeedDisplayDescp = 1; + break; + case otCfgDateTime: + FillText4MsgDateTimeSet(); + break; + case otCfgPermissionAllow: + + break; + case otAllowSet: + FillText4AllowSet(); + break; + case otAlramSetOnOff: + FillText4AlramSetOnOff(); + break; + case otBusPadOn: + FillText4BusPadOn(); + break; + case otBusPadOff: + FillText4BusPadOff(); + break; + case otDirectPadManualAllowOn: + FillText4DirectPadManualAllowOn(); + break; + case otDirectPadManualAllowOff: + FillText4DirectPadManualAllowOff(); + break; + case otDirectPadNodeOn: + FillText4DirectPadNodeOn(); + break; + case otDirectPadNodeOff: + FillText4DirectPadNodeOff(); + break; + case otUserCheck: + FillText4UserCheck(); + break; + case otLinkageGo: + FillText4LinkageGo(EntryTmp.fData.Body.Splite.Data1); + break; + case otSetNwTime: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("Set Salver Datetime",Text.Text); + break; + case otReqNwTime: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("Req Datetime To Master",Text.Text); + break; + case otSelfCheck: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("Selfcheck",Text.Text); + break; + case otSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Enable Manual",Text.Text); + else TMyString::sAddOnStr("Disable Manual",Text.Text); + break; + case otSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Enable Auto",Text.Text); + else TMyString::sAddOnStr("Disable Auto",Text.Text); + break; + case otRemoteSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Enable Manual(Master Call)",Text.Text); + else TMyString::sAddOnStr("Disable Manual(Master Call)",Text.Text); + break; + case otRemoteSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Enable Auto(Master Call)",Text.Text); + else TMyString::sAddOnStr("Disable Auto(Master Call)",Text.Text); + break; + case otReportManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Enable Manual(Slaver Report)",Text.Text); + else TMyString::sAddOnStr("Disable Manual(Slaver Report)",Text.Text); + break; + case otReportAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Enable Auto(Slaver Report)",Text.Text); + else TMyString::sAddOnStr("Disable Auto(Slaver Report)",Text.Text); + break; + case otFireConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警确认 ",Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 1; + NeedDrawCfg =1; + break; + case otFireSimConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警确认 ",Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 1; + NeedDrawCfg =11; + break; + case otFireRemoteConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警远程确认 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 3; + NeedDrawCfg = 3; + break; + case otFireSimRemoteConfirm: + FillTextWithDateTime(); + /*FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("火警远程确认 ",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text);*/ + AddOnFireMsg(); + NeedDisplayDescp = 3; + NeedDrawCfg = 13; + break; + case otFaultConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + NeedDisplayDescp = 1; + } + AddOnFaultMsg(); + NeedDrawCfg = 2; + break; + case otFaultRemoteConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + NeedDisplayDescp = 1; + } + /*if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("故障远程确认 ",Text.Text); + //TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text); + NeedDisplayDescp = 1; + NeedDrawCfg = 2; + }else{ + FillCtlNum(); + TMyString::sAddOnStr(" 故障远程确认 ",Text.Text); + //TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, Text.Text); + NeedDrawCfg = 2; + }*/ + AddOnFaultMsg(); + NeedDrawCfg = 4; + break; + case otSetSmokeSensViaCircuit: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" Set Smoke detector:Std",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" Set Smoke detector:High",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" Set Smoke detector:ExHigh",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" Set Smoke detector:Ultra",Text.Text); + }else{ + TMyString::sAddOnStr(" Set Smoke detector:Unknow",Text.Text); + } + break; + case otSetSmokeSensViaAddr: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("Set Smoke detector:Std",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Set Smoke detector:High",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("Set Smoke detector:ExHigh",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("Set Smoke detector:Ultra",Text.Text); + }else{ + TMyString::sAddOnStr("Set Smoke detector:Unknow",Text.Text); + } + NeedDisplayDescp = 1; + break; + case otCleanUp: + FillTextWithDateTime(); + FillCtlNum(); + //aPanel->Btn[0].Caption.FromStr(" 清除回路终端设备的登记 "); + //aPanel->Btn[1].Caption.FromStr(" 清除总线盘配置 "); + //aPanel->Btn[2].Caption.FromStr(" 清除多线盘配置 "); + //aPanel->Btn[3].Caption.FromStr(" 清除所有联动表达式 "); + //aPanel->Btn[4].Caption.FromStr(" 清除本机终端设备注释 "); + //aPanel->Btn[5].Caption.FromStr(" 清除组网配置 "); + //aPanel->Btn[6].Caption.FromStr(" 清除网络加载的设备注释 "); + //aPanel->Btn[7].Caption.FromStr(" 预设描述 "); + + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("Clear Loop Regist",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Clear Bus Pnl Config",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("Clear Direct Config",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("Clear All Linkage Expression ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr("Clear All Endpoint Description",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 5){ + TMyString::sAddOnStr("Clear LAN Config",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 6){ + TMyString::sAddOnStr("Clear LAN Description",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 7){ + TMyString::sAddOnStr("Clear Usercode & Assigntype",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF0){ + TMyString::sAddOnStr("Blocking,Clear Loop Regist",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF3){ + TMyString::sAddOnStr("Blocking,Clear All Linkage Expressions",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF4){ + TMyString::sAddOnStr("Blocking,Clear Descriptions",Text.Text); + } + break; + case otLinkageExpsSaveRemove: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Save Linkage Exp. Num:",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("Delete Linkage Exp. Num:",Text.Text); + } + ExpsInx = EntryTmp.fData.Body.Splite.P0; + ExpsInx = ExpsInx * 256; + ExpsInx = ExpsInx + EntryTmp.fData.Body.Splite.P1; + TMyString::sAddOn4Dg(ExpsInx, Text.Text); + break; + case otBusPadModify: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("BusPnl:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr(" Key:",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" Config",Text.Text); + break; + case otDirectPadModify: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("Direct:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr(" Config",Text.Text); + break; + case otDescpModify: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + if(EntryTmp.fData.Body.Splite.P0 <= dPORT_MAX_COUNT){ + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("Changed Device Descp ",Text.Text); + NeedDisplayDescp = 1; + }else + if( (EntryTmp.fData.Body.Splite.P0 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P0 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + TMyString::sAddOnStr("Direct:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0-dADDR_DIRECTPAD_START+1, Text.Text); + TMyString::sAddOnStr(" Node:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" Changed Descp ",Text.Text); + NeedDisplayDescp = 1; + } + break; + break; + case otPassWdModify: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" Change Password II",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" Change Password III",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 12){ + TMyString::sAddOnStr(" Sys Fault,Fail Password II",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 13){ + TMyString::sAddOnStr(" Sys Fault,Fail Password III",Text.Text); + } + break; + case otRegisterByManual: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + TMyString::sAddOnStr(" ",Text.Text); + AddOnUserCode(); + if(EntryTmp.fData.Body.Splite.Data1){ + TMyString::sAddOnStr("Manual Reg Type:",Text.Text); + TMyString::sAddOnStr(StrTypeShortNameEn[EntryTmp.fData.Body.Splite.dType],Text.Text); + }else{ + TMyString::sAddOnStr("Manual Reg Delete",Text.Text); + } + + break; + case otAddRemoveNwCtl: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" Manual Add Slaver ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" Manual Del Slaver ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" Manual Add Master ",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr(" Manual Del Master ",Text.Text); + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + break; + case otRegCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("Slaver Count In Master:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + }else{ + TMyString::sAddOnStr("Cleared Slavers In Master",Text.Text); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("Inject Num Of Master::",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + }else{ + TMyString::sAddOnStr("Cleared Master Conection",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("Set Master Count:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + }else{ + TMyString::sAddOnStr("Clear iConnected Master",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + } + } + break; + case otClearNetworkCfg: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Clear All Slaver",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("Clear Link Master",Text.Text); + } + break; + case otBroadcastVa: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("Set BCT & SL Path:",Text.Text); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, Text.Text); + TMyString::sAddOnStr("-",Text.Text); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, Text.Text); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" Parallel Mode",Text.Text); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" Alternate Mode",Text.Text); + } + break; + + case otSetAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("En Auto,En Manual",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("En Auto,Dis Manual",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("Dis Auto,En Manual",Text.Text); + else TMyString::sAddOnStr("Dis Auto,Dis Manual",Text.Text); + break; + case otRemoteSetAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("En Auto,En Manual(Master Call)",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("En Auto,Dis Manual(Master Call)",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("Dis Auto,En Manual(Master Call)",Text.Text); + else TMyString::sAddOnStr("Dis Auto,Dis Manual(Master Call)",Text.Text); + break; + case otReportAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("En Auto,En Manual(Slaver Report)",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("En Auto,Dis Manual(Slaver Report)",Text.Text); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("Dis Auto,En Manual(Slaver Report)",Text.Text); + else TMyString::sAddOnStr("Dis Auto,Dis Manual(Slaver Report)",Text.Text); + break; + } + } + if(0){ + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + + Text.Text[7] = EntryTmp.fData.Body.Splite.Month / 16 % 10 + '0'; + Text.Text[8] = EntryTmp.fData.Body.Splite.Month % 16 + '0'; + Text.Text[9] = '-'; + Text.Text[10] = EntryTmp.fData.Body.Splite.Day / 16 % 10 + '0'; + Text.Text[11] = EntryTmp.fData.Body.Splite.Day % 16 + '0'; + Text.Text[12] = ' '; + Text.Text[13] = EntryTmp.fData.Body.Splite.Hour / 16 % 10 + '0'; + Text.Text[14] = EntryTmp.fData.Body.Splite.Hour % 16 + '0'; + Text.Text[15] = ':'; + Text.Text[16] = EntryTmp.fData.Body.Splite.Minute / 16 % 10 + '0'; + Text.Text[17] = EntryTmp.fData.Body.Splite.Minute % 16 + '0'; + Text.Text[18] = ':'; + Text.Text[19] = EntryTmp.fData.Body.Splite.Second / 16 % 10 + '0'; + Text.Text[20] = EntryTmp.fData.Body.Splite.Second % 16 + '0'; + Text.Text[21] = ' '; + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + Text.Text[22] = e + '0'; + e = data % 10; + Text.Text[23] = e + '0'; + Text.Text[24] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + Text.Text[25] = e + '0'; + e = data % 10; + Text.Text[26] = e + '0'; + Text.Text[27] = '-'; + + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + Text.Text[28] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[29] = e + '0'; + e = data % 10; + Text.Text[30] = e + '0'; + Text.Text[31] = ' '; + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if( (aP0 >0) && (aP0 < 64) ){ + if(aP1 >0){ + if(aP0 < 40){ + aP0--; + data = Port[aP0].UcList[aP1-1].Full; + } + } + } + d = data/10000; + e = d % 10; + Text.Text[32] = e + '0'; + d = data/1000; + e = d % 10; + Text.Text[33] = e + '0'; + d = data/100; + e = d % 10; + Text.Text[34] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[35] = e + '0'; + e = data % 10; + Text.Text[36] = e + '0'; + Text.Text[37] = ' '; + + Text.Text[38] = 0; + + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text.Text); + //TMyString::sAddOnStr(" ",Text); + //TMyString::sAddOnStrL32(EntryTmp.fData.Descp, Text); + } + return NeedDisplayDescp; +} + +int TQueryMsgOperate::FillText(int aInx, int ShowInx) +{ + if(LanguageEnCn==0){ + return FillTextCN(aInx, ShowInx); + }else{ + return FillTextEN(aInx, ShowInx); + } +} + + +void TQueryMsgOperate::FillDescpText(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + const char * tText; + + if(NeedDrawCfg == 1){ + if(LanguageEnCn==0)tText=cFireCfm; else tText=cFireCfmEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else + if(NeedDrawCfg == 11){ + if(LanguageEnCn==0)tText=cFireSimCfm; else tText=cFireSimCfmEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else + if(NeedDrawCfg == 2){ + if(LanguageEnCn==0)tText=cFaultCfm; else tText=cFaultCfmEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else + if(NeedDrawCfg == 3){ + if(LanguageEnCn==0)tText=cFireRemoteCfm; else tText=cFireRemoteCfmEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else + if(NeedDrawCfg == 13){ + if(LanguageEnCn==0)tText=cFireSimRemoteCfm;else tText=cFireSimRemoteCfmEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else + if(NeedDrawCfg == 4){ + if(LanguageEnCn==0)tText=cFaultRemoteCfm;else tText=cFaultRemoteCfmEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else + if(NeedDrawCfg == 0xB1){ + if(LanguageEnCn==0)tText=cMask;else tText=cMaskEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else + if(NeedDrawCfg == 0xB0){ + if(LanguageEnCn==0)tText=cUnMask;else tText=cUnMaskEn; + for(d=0; d<22; d++)Text.Text[d] = tText[d]; + Text.Text[22] = '\0'; + /*if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",Text.Text); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",Text.Text); + } + }*/ + TMyString::sFillFixLen(Text.Text, 28); + }else{ + Text.D32[0] = 0x20202020; + Text.D32[1] = 0x20202020; + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + Text.D32[4] = 0x20202020; + Text.D32[5] = 0x20202020; + Text.D32[6] = 0x20202020; + Text.D32[7] = 0x20202020; + Text.D32[8] = 0; + } + + if(NeedDisplayDescp){ + //Operate History + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=7; d<15; d++){ + Text.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[15] =0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + } + + TMyString::sFillFixLen(Text.Text, dLineMaxLen); +} + +void TQueryMsgOperate::FillDescpTextEmpty() +{ + Text.Text[0] = ' '; + Text.Text[1] = '\0'; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); +} + +void TQueryMsgOperate::DrawListAll(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int TextClr, bClr, Wrote; + + aInx = TopIndex; + Wrote = 0; + for(i=0;i (Count-1))break; + if(SelectedIndex != aInx){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + NeedDisplayDescp = FillText(aInx, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(aInx); + //else FillDescpTextEmpty(); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + aInx++; + Wrote++; + } + for(i=Wrote; i0){ + i = InTimeTopIndex; + for(;i<(InTimeStopIndex+1);i++){ + if(InTimeSelectedIndex != (InTimeTopIndex + Wrote)){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + aInx = InTimeTopIndex - InTimeStartIndex + Wrote; + NeedDisplayDescp = FillText(i, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = Wrote *2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(i); + //else FillDescpTextEmpty(); + TextRender_string24(DescpX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + + Wrote++; + if(Wrote >= ListLineCnt){ + break; + } + } + } + for(i=Wrote; i0){ + SelectedIndex = Count -1; + }else{ + SelectedIndex = TopIndex; + } +} + +unsigned long long TQueryMsgOperate::aTimeGet(int aInx) +{ + volatile unsigned int SdAddr, Addr; + + //Operate History + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + alt.D32.Low4 = *(volatile unsigned int *)(SdAddr + 12); + alt.D32.Hi2 = *(volatile unsigned int *)(SdAddr + 16); + alt.D8[6] = 0; + alt.D8[7] = 0; + return alt.D64; +} + +void TQueryMsgOperate::GetStartStopTime() +{ + int i; + + RestoreFromEdit(); + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextFrom[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextFrom[i][1] - '0'); + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StartTime = alt.D64; + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextTo[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextTo[i][1] - '0'); + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StopTime = alt.D64; +} + +void TQueryMsgOperate::FindInTimeEntry() +{ + int i, aCnt, SatrtFound, StopFound; + unsigned long long aT; + SatrtFound = 0; + StopFound = 0; + InTimeStartIndex = 0; + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT < StartTime){ + InTimeStartIndex = i+1; + if(InTimeStartIndex >(Count-1)){ + SatrtFound = 0; + }else{ + SatrtFound = 1; + } + break; + } + } + if(SatrtFound == 0){ + if(InTimeStartIndex == 0){ + SatrtFound =1; + } + } + if(SatrtFound){ + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT <= StopTime){ + InTimeStopIndex = i; + StopFound = 1; + break; + } + } + if(StopFound == 0){ + InTimeStopIndex = Count-1; + } + if(InTimeStopIndex < InTimeStartIndex){ + InTimeCount = 0; + }else{ + aCnt = InTimeStopIndex - InTimeStartIndex + 1; + if(aCnt <0)aCnt = 0; + InTimeCount = aCnt; + } + + InTimeTopIndex = InTimeStopIndex - ListLineCnt +1; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + }else{ + InTimeCount = 0; + InTimeTopIndex = 0; + InTimeStopIndex = 0; + } +} + +void TQueryMsgOperate::GetEntry4Print(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned int NeedDescp; + + NeedDescp = 0; + + //Operate History + Addr = Record.Buf4Operate.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=3; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + + if(EntryTmp.fData.Body.Splite.mType == etOperate){ + switch(EntryTmp.fData.Body.Splite.Data0){ + case otMask: + NeedDescp =1; + break; + case otUnMask: + NeedDescp =1; + break; + case otCfgDevice: + NeedDescp = 1; + break; + case otFireConfirm: + NeedDescp = 1; + break; + case otFireRemoteConfirm: + NeedDescp = 1; + break; + case otFaultConfirm: + NeedDescp = 2; + break; + case otFaultRemoteConfirm: + NeedDescp = 1; + break; + case otSetSmokeSensViaAddr: + NeedDescp = 1; + break; + case otDescpModify: + if(EntryTmp.fData.Body.Splite.P0 <= dPORT_MAX_COUNT){ + NeedDescp = 1; + }else + if( (EntryTmp.fData.Body.Splite.P0 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P0 <= dADDR_DIRECTPAD_END) ){ + NeedDescp = 1; + } + break; + } + } + + if(NeedDescp){ + //Operate History + for(d=7; d<15; d++){ + Text.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[15] =0; + }else{ + Text.D32[7] = 0; + } +} + +TGuiMsgReturn TQueryMsgOperate::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + if(IsAllTime){ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = TopIndex -ListLineCnt; + if(aIndex > -1){ + TopIndex = aIndex; + SelectedIndex -= ListLineCnt; + }else{ + if(TopIndex > 0){ + TopIndex = 0; + SelectedIndex = TopIndex; + }else{ + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = TopIndex +ListLineCnt; + if(aIndex < Count){ + TopIndex = aIndex; + SelectedIndex += ListLineCnt; + if(SelectedIndex >= Count){ + SelectedIndex = Count-1; + } + }else{ + TopIndex = 0; + SelectedIndex = TopIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = SelectedIndex -1; + if(aIndex > -1){ + SelectedIndex = aIndex; + if(SelectedIndex < TopIndex){ + TopIndex = SelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = SelectedIndex +1; + if(aIndex < Count){ + SelectedIndex = aIndex; + if(SelectedIndex > (TopIndex + ListLineCnt -1) ){ + TopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + }else{ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = InTimeTopIndex -ListLineCnt; + if(aIndex >= InTimeStartIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex -= ListLineCnt; + }else{ + if(InTimeTopIndex > InTimeStartIndex){ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + }else{ + InTimeTopIndex = InTimeStopIndex - ListLineCnt; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = InTimeTopIndex +ListLineCnt; + if(aIndex <= InTimeStopIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex += ListLineCnt; + if(InTimeSelectedIndex > InTimeStopIndex){ + InTimeSelectedIndex = InTimeStopIndex; + } + }else{ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = InTimeSelectedIndex -1; + if(aIndex >= InTimeStartIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex < InTimeTopIndex){ + InTimeTopIndex = InTimeSelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = InTimeSelectedIndex +1; + if(aIndex <= InTimeStopIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex > (InTimeTopIndex + ListLineCnt -1) ){ + InTimeTopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + } + + if(IsInputTime){ + if(aKey == VK_UP){ + if(TimeEditFrom >0){ + RestoreFromEdit(); + TimeEditFrom =0; + SetEditStart(); + }else{ + if(TimeEditFrom > -1){ + RestoreFromEdit(); + TimeEditFrom = -1; + DrawIfAllTime(); + } + } + }else + if(aKey == VK_DOWN){ + if(TimeEditFrom <1){ + if(IsAllTimeTemp == 0){ + if(TimeEditFrom == 0)RestoreFromEdit(); + TimeEditFrom ++; + SetEditStart(); + DrawIfAllTime(); + } + } + }else + if(aKey == VK_LEFT){ + if(TimeEditFrom > -1){ + if(TimeIndex >0){ + RestoreFromEdit(); + TimeIndex--; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_RIGHT){ + if(TimeEditFrom > -1){ + if(TimeIndex <5){ + RestoreFromEdit(); + TimeIndex++; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_EXECUTE){ + //Read Here + if(IsAllTimeTemp){ + IsAllTime = IsAllTimeTemp; + DrawItemCount(Count); + ReDraw(); + }else{ + IsAllTime = IsAllTimeTemp; + GetStartStopTime(); + FindInTimeEntry(); + DrawItemCount(InTimeCount); + IsInputTime = 0; + RenderContent(); + ReDraw(); + } + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsInputTime = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else{ + if(IsAllTimeTemp == 0){ + if(IsEditing){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + } + } + } + + if(IsGoPrint){ + if(aKey == VK_LEFT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_RIGHT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_EXECUTE){ + //Print Here + if(Count){ + if(SelectedIndex < Count){ + GetEntry4Print(SelectedIndex); + RecordMsg.D32[0] = EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = EntryTmp.fData.UserCode; + DoPrint.PrintHistory(4,RecordMsg, &Text.Text[28]); + } + } + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + } + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TQueryMsgOperate::Task1000Ms() +{ + if(IsShowing){ + if(Count != Record.Buf4Operate.Count){ + TopIndex = Count - ListLineCnt +1; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } +} + +int TQueryMsgOperate::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} diff --git a/MyCode/Gui/QueryMsgOperate.h b/MyCode/Gui/QueryMsgOperate.h new file mode 100644 index 0000000..1d13f26 --- /dev/null +++ b/MyCode/Gui/QueryMsgOperate.h @@ -0,0 +1,27 @@ +#ifndef QUERYMSGOPERATE_H_ +#define QUERYMSGOPERATE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "ProtoFecBus.h" + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/QueryMsgSv.cpp b/MyCode/Gui/QueryMsgSv.cpp new file mode 100644 index 0000000..b66f16c --- /dev/null +++ b/MyCode/Gui/QueryMsgSv.cpp @@ -0,0 +1,1376 @@ +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "MainCtl.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" +#include "QueryMessage.h" + +#define TextTopOffSet 6 +#define ListLineCnt 4 +#define ColHeight 33 + +#define FixTop 69 +#define MsgX0 6 +#define DescpX0 270 //90 + +#define dLineMaxLen 64 + +const static unsigned short stAllTop[10] = { + 80, 120, 160, 200, 240, + 280, 320, 360, 400, 440 +}; + +static const short qmFixCol[8] = { + 20,100,160,240, 320,400,520,600 +}; + +void TQueryMsgSv::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + BoxBoundTime.Set(Left+170, Top+80, Right-170, Bottom-30); + GoPrint.Set(Left+170, Top+150, Right-170, Bottom-130); + Color = aColor; + #undef CH + + + Caption.Border.Color = clGray; + + FixColColor = clMaroon; + FixColTextColor = clNearWhite; + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; + + IsSimulate = 0; +} + +void TQueryMsgSv::InitBackEnd() +{ + Count=0; + SelectedIndex=0; + SelectedIndex = 0; + TopIndex = 0; + + IsInputTime = 0; + IsGoPrint = 0; + IsAllTime = 1; + TimeEditFrom = -1; + TimeIndex =0; + IsEditing = 0; + PrintWhat = 0; + ReStoreP0 = 0; + ReStoreP1 = 0; +} + +void TQueryMsgSv::SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8) +{ + +} + +void TQueryMsgSv::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgSv::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TQueryMsgSv::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TQueryMsgSv::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TQueryMsgSv::DrawCaption(void) +{ + if(LanguageEnCn==0)TMyString::sFromStr("历史记录->查询监管信息", Caption.Text); + else TMyString::sFromStr("Recorded Info->Query Supervision", Caption.Text); + + Caption.Show(); + DrawCaption2(); +} + +void TQueryMsgSv::DrawCaption2(void) +{ + +} + +void TQueryMsgSv::RenderWarningWait(void) +{ + int x,y,x2,y2, aW,aH; + x = 200; + y = 160; + x2 = 600; + y2 = 290; + aW = x2 - x +1; + aH = y2 - y +1; + VertLineRender(x, y, aH-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y+1, aH -2, 0xFF808080); + VertLineRender(x2, y, aH, 0xFF404040); + + HorizLineRender(x, y, aW - 1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, aW - 2, 0xFF808080); + HorizLineRender(x, y2, aW, 0xFF404040); + + RectFillRender(x+1,y+1,x2-2,y+30,clNavy); + RectFillRender(x+1,y+31,x2-2,y2-2,clGray); + + if(LanguageEnCn==0){ + TextRender_string24(x+8, y+6, clNearWhite, "提示信息"); + TextRender_string24(x+66, y+36, clNearBlack, "正在读取,请等待"); + }else{ + TextRender_string24(x+8, y+6, clNearWhite, "Message"); + TextRender_string24(x+66, y+36, clNearBlack, "Reading,Please Wait"); + } +} + +void TQueryMsgSv::DrawItemCount(int aCount) +{ + TextDigitRender6Left24(500,Caption.Bound.Top +3, clNearWhite, Caption.Color, Count); + TextDigitRender6Left24(720,Caption.Bound.Top +3, clNearWhite, Caption.Color, aCount); + + if(LanguageEnCn==0){ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "总数量:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "查看数量:"); + }else{ + TextRender_string24(400, Caption.Bound.Top +3, clNearWhite, "Total:"); + TextRender_string24(600, Caption.Bound.Top +3, clNearWhite, "Display:"); + } +} + +void TQueryMsgSv::DrawBoxTimeOutLine() +{ + RectFillRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Right, BoxBoundTime.Bottom, clFrmFace); + + VertLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Height -1, 0xFFFFFFFF); + VertLineRender(BoxBoundTime.Right -1, BoxBoundTime.Top +1, BoxBoundTime.Height -2, 0xFF808080); + VertLineRender(BoxBoundTime.Right, BoxBoundTime.Top, BoxBoundTime.Height, 0xFF404040); + + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Top, BoxBoundTime.Width - 1, 0xFFFFFFFF); + HorizLineRender(BoxBoundTime.Left +1, BoxBoundTime.Bottom -1, BoxBoundTime.Width - 2, 0xFF808080); + HorizLineRender(BoxBoundTime.Left, BoxBoundTime.Bottom, BoxBoundTime.Width, 0xFF404040); + + if(LanguageEnCn==0) TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "设置日期时间段,按确认键开始查询"); + else TStaticText::sShow(BoxBoundTime.Left+2, BoxBoundTime.Top+2, BoxBoundTime.Right-2, BoxBoundTime.Top+32, clNearWhite, clBlue, "Set Date And Time,OK Key:Start The Query"); +} + +void TQueryMsgSv::DrawTimeEntry(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + vtValueFrom[0] = DateTime.Date.Split.Year; + vtValueFrom[1] = DateTime.Date.Split.Month; + vtValueFrom[2] = DateTime.Date.Split.Day; + + vtValueFrom[3] = DateTime.Time.Split.Hour; + vtValueFrom[4] = DateTime.Time.Split.Minute; + vtValueFrom[5] = DateTime.Time.Split.Second; + + vtValueTo[0] =vtValueFrom[0]; + vtValueTo[1] =vtValueFrom[1]; + vtValueTo[2] =vtValueFrom[2]; + vtValueTo[3] =vtValueFrom[3]; + vtValueTo[4] =vtValueFrom[4]; + vtValueTo[5] =vtValueFrom[5]; + + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + + +void TQueryMsgSv::DrawTimeEntryNoUpdate(void) +{ + int x,y,w,h; + int i; + unsigned char aHex0, aHex1; + + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + + w = 36; + h = 32; + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (0 * 112); + + aHex0 = vtValueFrom[i] / 16 % 10; + aHex1 = vtValueFrom[i] % 16 % 10; + vtTextFrom[i][0] = aHex0 + '0'; + vtTextFrom[i][1] = aHex1 + '0'; + vtTextFrom[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextFrom[i]); + } + + for(i=0; i<6; i++){ + x = BoxBoundTime.Left + 80 + (i * 48); + y = BoxBoundTime.Top + 140 + (1 * 112); + + aHex0 = vtValueTo[i] / 16 % 10; + aHex1 = vtValueTo[i] % 16 % 10; + vtTextTo[i][0] = aHex0 + '0'; + vtTextTo[i][1] = aHex1 + '0'; + vtTextTo[i][2] = 0; + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + TextRender_string24(x+3, y+3, aClr, vtTextTo[i]); + } +} + +void TQueryMsgSv::DrawIfAllTime(void) +{ + unsigned int aClr, bClr; + if(TimeEditFrom == -1){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + TTriangleLeftRight::sDrawLeftByHight(BoxBoundTime.Left + 150 - 20, BoxBoundTime.Top + 44, 20, clBlue); + TTriangleLeftRight::sDrawRightByHight(BoxBoundTime.Left + 150 + 106, BoxBoundTime.Top + 44, 20, clBlue); + if(LanguageEnCn==0){ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "全部条目"); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "按时间段"); + } + }else{ + if(IsAllTimeTemp){ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, " All "); + }else{ + TextRender_string24(BoxBoundTime.Left + 150, BoxBoundTime.Top + 42, aClr, bClr, "Segments"); + } + } +} + +void TQueryMsgSv::DrawBoxTimeString(void) +{ + unsigned int aClr; + if(IsAllTimeTemp){ + aClr = clSilver; + }else{ + aClr = clNearBlack; + } + if(LanguageEnCn==0){ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "开始时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, "年 月 日 时 分 秒"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "结束时间"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, "年 月 日 时 分 秒"); + }else{ + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 74, aClr, "Begin"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 108, aClr, " Y M D H M S"); + TextRender_string24(BoxBoundTime.Left + 52, BoxBoundTime.Top + 187, aClr, "End"); + TextRender_string24(BoxBoundTime.Left + 82, BoxBoundTime.Top + 219, aClr, " Y M D H M S"); + } +} + +void TQueryMsgSv::DrawBoxTime(void) +{ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); +} + +void TQueryMsgSv::DrawGoPrintOutLine() +{ + RectFillRender(GoPrint.Left, GoPrint.Top, GoPrint.Right, GoPrint.Bottom, clFrmFace); + + VertLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Height -1, 0xFFFFFFFF); + VertLineRender(GoPrint.Right -1, GoPrint.Top +1, GoPrint.Height -2, 0xFF808080); + VertLineRender(GoPrint.Right, GoPrint.Top, GoPrint.Height, 0xFF404040); + + HorizLineRender(GoPrint.Left, GoPrint.Top, GoPrint.Width - 1, 0xFFFFFFFF); + HorizLineRender(GoPrint.Left +1, GoPrint.Bottom -1, GoPrint.Width - 2, 0xFF808080); + HorizLineRender(GoPrint.Left, GoPrint.Bottom, GoPrint.Width, 0xFF404040); + + if(LanguageEnCn==0)TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "按确认键开始打印并返回"); + else TStaticText::sShow(GoPrint.Left+2, GoPrint.Top+2, GoPrint.Right-2, GoPrint.Top+32, clNearWhite, clBlue, "Confirm Print Or Return"); +} + +void TQueryMsgSv::DrawPrintWhat() +{ + if(LanguageEnCn==0)TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "打印当前选定条目"); + else TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clFrmFace, "Print Current Item"); + return; + if(PrintWhat == 0){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, "当前选定条目"); + }else + if(PrintWhat == 1){ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 当前页面 "); + }else{ + TextRender_string24(GoPrint.Left + 150, GoPrint.Top + 66, clNearBlack, clTeal, " 全部信息 "); + } +} + +void TQueryMsgSv::Show(void) +{ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } + DrawItemCount(Count); + ShowTip(); +} + +void TQueryMsgSv::ReDraw(void) +{ + Caption.Enable = 1; + //DrawCaption(); + if(IsInputTime){ + DrawBoxTime(); + }else{ + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + } +} + + +void TQueryMsgSv::FullRedraw(int Prm) +{ + if(Prm == 0){ + DrawSelf(); + Caption.Enable = 1; + DrawCaption(); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + DrawItemCount(Count); + ShowTip(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + if(IsAllTime){ + DrawListAll(); + }else{ + DrawListInTime(); + } + if(IsInputTime){ + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntryNoUpdate(); + if(TimeEditFrom > -1){ + SetEditStart(); + }else{ + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(IsGoPrint){ + DrawGoPrintOutLine(); + DrawPrintWhat(); + } + ShowTip(); + } +} + + +void TQueryMsgSv::ShowTip() +{ + if(LanguageEnCn==0){ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, TAB键去打印"); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "上下左右键切换或编辑条目, 数字键删除键编辑 "); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "按确定键打印当前条目 "); + } + }else{ + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + //TextRender_string24(40, 410, clNearBlack, Color, "左右键翻页, 上下键加减一条目, 设置键设定时间段, TAB键去打印"); + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down:Switch item; TAB To Print "); + } + if(IsInputTime){ + TextRender_string24(40, 410, clNearBlack, Color, "Left,Right,Up,Down To Switch Item To Edit; Num Key To Edit"); + }else + if(IsGoPrint){ + TextRender_string24(40, 410, clNearBlack, Color, "Press The OK Key To Print The Current Item "); + } + } +} + +void TQueryMsgSv::SetEditStart(void) +{ + int x,y,w,h; + + IsEditing =1; + + ReStoreP0 = TimeEditFrom; + ReStoreP1 = TimeIndex; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + vEdit.Init(x,y,w,h,0,0,1,clTeal); + vEdit.Color = clTeal; + vEdit.SetMaxLen(2); + if(ReStoreP0 ==0){ + vEdit.Str.Text[0] = vtTextFrom[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextFrom[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + }else + if(ReStoreP0 ==1){ + vEdit.Str.Text[0] = vtTextTo[ReStoreP1][0]; + vEdit.Str.Text[1] = vtTextTo[ReStoreP1][1]; + vEdit.Str.Text[2] = 0; + } + vEdit.Pst = -1; + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); +} + +void TQueryMsgSv::RestoreFromEdit(void) +{ + int x,y,w,h; + + if(IsEditing == 0)return; + + x = BoxBoundTime.Left + 80 + (ReStoreP1 * 48); + y = BoxBoundTime.Top + 140 + (ReStoreP0 * 112); + w = 36; + h = 32; + + RectFillRender(x, y, x+w-1, y+h-1, clFrmFace); + if(ReStoreP0 == 0){ + vtTextFrom[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextFrom[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextFrom[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextFrom[ReStoreP1]); + }else + if(ReStoreP0 == 1){ + vtTextTo[ReStoreP1][0] = vEdit.Str.Text[0]; + vtTextTo[ReStoreP1][1] = vEdit.Str.Text[1]; + vtTextTo[ReStoreP1][2] = 0; + TextRender_string24(x+3, y+3, clNearBlack, vtTextTo[ReStoreP1]); + } + IsEditing = 0; +} + +void TQueryMsgSv::AddOnUserCode() +{ + TMyString::sAddOn8Dg(EntryTmp.fData.UserCode, Text.Text); +} + +int TQueryMsgSv::FillText(int aInx, int ShowInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + TUserCode Uc; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + //Sv History + IsSimulate = 0; + NeedDisplayDescp = 0; + + Addr = Record.Buf4Sv.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=2; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + data = ShowInx +1; + + d = data/100000; + e = d % 10; + Text.Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text.Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text.Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text.Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text.Text[4] = e + '0'; + + e = data % 10; + Text.Text[5] = e + '0'; + + Text.Text[6] = ' '; + CoverDateTimeIllegal(EntryTmp.fData.Body, &DateTimeCovered); + Text.Text[7] = DateTimeCovered.Year / 16 % 10 + '0'; + Text.Text[8] = DateTimeCovered.Year % 16 % 10 + '0'; + Text.Text[9] = '/'; + Text.Text[10] = DateTimeCovered.Month / 16 % 10 + '0'; + Text.Text[11] = DateTimeCovered.Month % 16 % 10 + '0'; + Text.Text[12] = '/'; + Text.Text[13] = DateTimeCovered.Day / 16 % 10 + '0'; + Text.Text[14] = DateTimeCovered.Day % 16 % 10 + '0'; + Text.Text[15] = ' '; + Text.Text[16] = DateTimeCovered.Hour / 16 % 10 + '0'; + Text.Text[17] = DateTimeCovered.Hour % 16 % 10 + '0'; + Text.Text[18] = ':'; + Text.Text[19] = DateTimeCovered.Minute / 16 % 10 + '0'; + Text.Text[20] = DateTimeCovered.Minute % 16 % 10 + '0'; + Text.Text[21] = ':'; + Text.Text[22] = DateTimeCovered.Second / 16 % 10 + '0'; + Text.Text[23] = DateTimeCovered.Second % 16 % 10 + '0'; + Text.Text[24] = ' '; + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + Text.Text[25] = e + '0'; + e = data % 10; + Text.Text[26] = e + '0'; + Text.Text[27] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + Text.Text[28] = e + '0'; + e = data % 10; + Text.Text[29] = e + '0'; + Text.Text[30] = '-'; + + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + Text.Text[31] = e + '0'; + d = data/10; + e = d % 10; + Text.Text[32] = e + '0'; + e = data % 10; + Text.Text[33] = e + '0'; + Text.Text[34] = ' '; + Text.Text[35] = '\0'; + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if( (aP0 >0) && (aP0 < 64) ){ + if(aP1 >0){ + if(aP0 < 40){ + aP0--; + data = Port[aP0].UcList[aP1-1].Full; + } + } + } + + AddOnUserCode(); + TMyString::sAddOnStr(" ",Text.Text); + + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],Text.Text); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],Text.Text); + + data = EntryTmp.fData.Body.Splite.iByte0; + if(data == 0x01){ + //TMyString::sAddOnStr("-启动",Text.Text); + }else + if(data == 0x02){ + //TMyString::sAddOnStr("-区声光启动",Text.Text); + }else + if(data == 0x03){ + //TMyString::sAddOnStr("-应答",Text.Text); + }else + if(data == 0x04){ + //TMyString::sAddOnStr("-应答缺失",Text.Text); + } + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + NeedDisplayDescp = 1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + NeedDisplayDescp = 1; + } + } + if(EntryTmp.fData.Body.Splite.Data1 == TControlCenter::StartTypeSimulate){ + IsSimulate = 1; + } + return NeedDisplayDescp; +} + + +void TQueryMsgSv::FillDescpText(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + if(NeedDisplayDescp){ + //Sv History + if(IsSimulate){ + if(LanguageEnCn==0)TMyString::sFromStr("模拟",Text.Text); + else TMyString::sFromStr(" SIM",Text.Text); + }else{ + Text.D32[0] = 0x20202020; + } + Text.D32[1] = 0x20202020; + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + Text.D32[4] = 0x20202020; + Text.D32[5] = 0x20202020; + + Addr = Record.Buf4Sv.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=7; d<15; d++){ + Text.D32[d-1] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[14] =0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + }else{ + if(IsSimulate){ + if(LanguageEnCn==0)TMyString::sFromStr("模拟",Text.Text); + else TMyString::sFromStr(" SIM",Text.Text); + }else{ + Text.D32[0] = 0x20202020; + } + Text.D32[1] = 0x20202020; + Text.D32[2] = 0x20202020; + Text.D32[3] = 0x20202020; + Text.D32[4] = 0x20202020; + Text.D32[5] = 0; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + } +} + +void TQueryMsgSv::FillDescpTextEmpty() +{ + Text.Text[0] = ' '; + Text.Text[1] = '\0'; + TMyString::sFillFixLen(Text.Text, dLineMaxLen); +} + +void TQueryMsgSv::DrawListAll(void) +{ + volatile unsigned int i, aLen; + int aInx, aTopInx; + volatile unsigned int TextClr, bClr, Wrote; + + aInx = TopIndex; + Wrote = 0; + for(i=0;i (Count-1))break; + if(SelectedIndex != aInx){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + NeedDisplayDescp = FillText(aInx, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = i*2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(aInx); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + aInx++; + Wrote++; + } + for(i=Wrote; i0){ + i = InTimeTopIndex; + for(;i<(InTimeStopIndex+1);i++){ + if(InTimeSelectedIndex != (InTimeTopIndex + Wrote)){ + bClr = Color; + TextClr = clNearBlack; + }else{ + bClr = clBlue; + TextClr = clNearWhite; + } + aInx = InTimeTopIndex - InTimeStartIndex + Wrote; + FillText(i, aInx); + TMyString::sFillFixLen(Text.Text, dLineMaxLen); + TMyString::sBrokeFixLen(Text.Text, dLineMaxLen); + aTopInx = Wrote *2; + RectFillRender(MsgX0, stAllTop[aTopInx] + 24, MsgX0 + 767, stAllTop[aTopInx +1]-6-1, bClr); + TextRender_string24(MsgX0, stAllTop[aTopInx +0], TextClr, bClr, Text.Text); + FillDescpText(i); + TextRender_string24(MsgX0, stAllTop[aTopInx +1]-6, TextClr, bClr, Text.Text); + + Wrote++; + if(Wrote >= ListLineCnt){ + break; + } + } + } + for(i=Wrote; i0){ + SelectedIndex = Count -1; + }else{ + SelectedIndex = TopIndex; + } +} + +unsigned long long TQueryMsgSv::aTimeGet(int aInx) +{ + volatile unsigned int SdAddr, Addr; + + //Sv History + Addr = Record.Buf4Sv.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramSvHistoryContentBaseAddr + 0x320000) ) + SdAddr = Addr - 0x320000; + else + SdAddr = Addr; + alt.D32.Low4 = *(volatile unsigned int *)(SdAddr + 12); + alt.D32.Hi2 = *(volatile unsigned int *)(SdAddr + 16); + alt.D8[6] = 0; + alt.D8[7] = 0; + return alt.D64; +} + +void TQueryMsgSv::GetStartStopTime() +{ + int i; + + RestoreFromEdit(); + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextFrom[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextFrom[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StartTime = alt.D64; + + for(i=0; i<6;i++){ + alt.D8[5-i] = (vtTextTo[i][0] - '0') * 16; + alt.D8[5-i] += (vtTextTo[i][1] - '0'); + + } + alt.D8[6] = 0; + alt.D8[7] = 0; + StopTime = alt.D64; +} + +void TQueryMsgSv::FindInTimeEntry() +{ + int i, aCnt, SatrtFound, StopFound; + unsigned long long aT; + SatrtFound = 0; + StopFound = 0; + InTimeStartIndex = 0; + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT < StartTime){ + InTimeStartIndex = i+1; + if(InTimeStartIndex >(Count-1)){ + SatrtFound = 0; + }else{ + SatrtFound = 1; + } + break; + } + } + if(SatrtFound == 0){ + if(InTimeStartIndex == 0){ + SatrtFound =1; + } + } + if(SatrtFound){ + for(i=Count-1; i>-1; i--){ + aT = aTimeGet(i); + if(aT <= StopTime){ + InTimeStopIndex = i; + StopFound = 1; + break; + } + } + if(StopFound == 0){ + InTimeStopIndex = Count-1; + } + if(InTimeStopIndex < InTimeStartIndex){ + InTimeCount = 0; + }else{ + aCnt = InTimeStopIndex - InTimeStartIndex + 1; + if(aCnt <0)aCnt = 0; + InTimeCount = aCnt; + } + + InTimeTopIndex = InTimeStopIndex - ListLineCnt +1; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + }else{ + InTimeCount = 0; + InTimeTopIndex = 0; + InTimeStopIndex = 0; + } +} + + +void TQueryMsgSv::GetEntry4Print(int aInx) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char NeedDescp; + + //Sv History + NeedDescp = 0; + + Addr = Record.Buf4Sv.SdramAddrStart + aInx * 64; + if(Addr >= (dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) ) + SdAddr = Addr - dSdramHistoryBytesLength; + else + SdAddr = Addr; + for(d=3; d<14; d++){ + EntryTmp.D32[d] = *(volatile unsigned int *)(SdAddr + d * 4); + } + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + NeedDescp = 1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + NeedDescp = 1; + } + } + + + if(NeedDescp){ + //Sv History + for(d=7; d<15; d++){ + Text.D32[d-1] = *(volatile unsigned int *)(SdAddr + d * 4); + } + Text.D32[14] =0; + }else{ + Text.D32[6] = 0; + } +} + + +TGuiMsgReturn TQueryMsgSv::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if( (IsInputTime == 0) && (IsGoPrint == 0) ){ + if(IsAllTime){ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = TopIndex -ListLineCnt; + if(aIndex > -1){ + TopIndex = aIndex; + SelectedIndex -= ListLineCnt; + }else{ + if(TopIndex > 0){ + TopIndex = 0; + SelectedIndex = TopIndex; + }else{ + TopIndex = Count - ListLineCnt; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = TopIndex +ListLineCnt; + if(aIndex < Count){ + TopIndex = aIndex; + SelectedIndex += ListLineCnt; + if(SelectedIndex >= Count){ + SelectedIndex = Count-1; + } + }else{ + TopIndex = 0; + SelectedIndex = TopIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = SelectedIndex -1; + if(aIndex > -1){ + SelectedIndex = aIndex; + if(SelectedIndex < TopIndex){ + TopIndex = SelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = SelectedIndex +1; + if(aIndex < Count){ + SelectedIndex = aIndex; + if(SelectedIndex > (TopIndex + ListLineCnt -1) ){ + TopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + }else{ + if(aKey == VK_TAB){ + //Items.SelectedIndex = 0; + //Lv.SelectedCol = 0; + //Lv.TopIndex = 0; + IsGoPrint = 1; + DrawGoPrintOutLine(); + DrawPrintWhat(); + ShowTip(); + }else + if(VK_LEFT == aKey){ + aIndex = InTimeTopIndex -ListLineCnt; + if(aIndex >= InTimeStartIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex -= ListLineCnt; + }else{ + if(InTimeTopIndex > InTimeStartIndex){ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + }else{ + InTimeTopIndex = InTimeStopIndex - ListLineCnt; + if(InTimeTopIndex < InTimeStartIndex)InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeTopIndex; + } + } + ReDraw(); + }else + if(VK_RIGHT == aKey){ + aIndex = InTimeTopIndex +ListLineCnt; + if(aIndex <= InTimeStopIndex){ + InTimeTopIndex = aIndex; + InTimeSelectedIndex += ListLineCnt; + if(InTimeSelectedIndex > InTimeStopIndex){ + InTimeSelectedIndex = InTimeStopIndex; + } + }else{ + InTimeTopIndex = InTimeStartIndex; + InTimeSelectedIndex = InTimeStartIndex; + } + ReDraw(); + }else + if(VK_UP == aKey){ + aIndex = InTimeSelectedIndex -1; + if(aIndex >= InTimeStartIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex < InTimeTopIndex){ + InTimeTopIndex = InTimeSelectedIndex; + } + ReDraw(); + } + }else + if(VK_DOWN == aKey){ + aIndex = InTimeSelectedIndex +1; + if(aIndex <= InTimeStopIndex){ + InTimeSelectedIndex = aIndex; + if(InTimeSelectedIndex > (InTimeTopIndex + ListLineCnt -1) ){ + InTimeTopIndex++; + } + ReDraw(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + IsInputTime = 1; + IsAllTimeTemp = IsAllTime; + DrawBoxTimeOutLine(); + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + ShowTip(); + }else + if(aKey == VK_F2){ + //Query Device Property + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + } + } + + if(IsInputTime){ + if(aKey == VK_UP){ + if(TimeEditFrom >0){ + RestoreFromEdit(); + TimeEditFrom =0; + SetEditStart(); + }else{ + if(TimeEditFrom > -1){ + RestoreFromEdit(); + TimeEditFrom = -1; + DrawIfAllTime(); + } + } + }else + if(aKey == VK_DOWN){ + if(TimeEditFrom <1){ + if(IsAllTimeTemp == 0){ + if(TimeEditFrom == 0)RestoreFromEdit(); + TimeEditFrom ++; + SetEditStart(); + DrawIfAllTime(); + } + } + }else + if(aKey == VK_LEFT){ + if(TimeEditFrom > -1){ + if(TimeIndex >0){ + RestoreFromEdit(); + TimeIndex--; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_RIGHT){ + if(TimeEditFrom > -1){ + if(TimeIndex <5){ + RestoreFromEdit(); + TimeIndex++; + SetEditStart(); + } + }else{ + if(IsAllTimeTemp){ + IsAllTimeTemp = 0; + }else{ + IsAllTimeTemp = 1; + } + DrawBoxTimeString(); + DrawIfAllTime(); + DrawTimeEntry(); + } + }else + if(aKey == VK_EXECUTE){ + //Read Here + if(IsAllTimeTemp){ + IsAllTime = IsAllTimeTemp; + DrawItemCount(Count); + ReDraw(); + }else{ + IsAllTime = IsAllTimeTemp; + GetStartStopTime(); + FindInTimeEntry(); + DrawItemCount(InTimeCount); + IsInputTime = 0; + RenderContent(); + ReDraw(); + } + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsInputTime = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else{ + if(IsAllTimeTemp == 0){ + if(IsEditing){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + } + } + } + } + } + + if(IsGoPrint){ + if(aKey == VK_LEFT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_RIGHT){ + if(PrintWhat ==0)PrintWhat=1; + else PrintWhat = 0; + DrawPrintWhat(); + }else + if(aKey == VK_EXECUTE){ + //Print Here + if(Count){ + if(SelectedIndex < Count){ + GetEntry4Print(SelectedIndex); + RecordMsg.D32[0] = EntryTmp.fData.Body.D32[0]; + RecordMsg.D32[1] = EntryTmp.fData.Body.D32[1]; + RecordMsg.D32[2] = EntryTmp.fData.Body.D32[2]; + RecordMsg.D32[3] = EntryTmp.fData.Body.D32[3]; + RecordMsg.Splite.UserCode = EntryTmp.fData.UserCode; + DoPrint.PrintHistory(2,RecordMsg, &Text.Text[24]); + } + } + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + }else + if(aKey == VK_RETURN){ + IsGoPrint = 0; + RenderContent(); + ReDraw(); + ShowTip(); + } + } + //____________________________________________________________________<- List View + + return aMsg; +} + +void TQueryMsgSv::Task1000Ms() +{ + if(IsShowing){ + if(Count != Record.Buf4Sv.Count){ + TopIndex = Count - ListLineCnt +1; + if(TopIndex < 0)TopIndex = 0; + SelectedIndex =TopIndex; + } + } +} + +int TQueryMsgSv::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} diff --git a/MyCode/Gui/QueryMsgSv.h b/MyCode/Gui/QueryMsgSv.h new file mode 100644 index 0000000..883662a --- /dev/null +++ b/MyCode/Gui/QueryMsgSv.h @@ -0,0 +1,28 @@ +#ifndef QUERYMSGSV_H_ +#define QUERYMSGSV_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "MainCtl.h" +#include "Device.h" +#include "EpDevice.h" +#include "DevProperty.h" +#include "ProtoFecBus.h" + + + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/RealTimeData.cpp b/MyCode/Gui/RealTimeData.cpp new file mode 100644 index 0000000..eaffe47 --- /dev/null +++ b/MyCode/Gui/RealTimeData.cpp @@ -0,0 +1,475 @@ +#include "RuntimeData.h" +#include "RealTimeData.h" + +#define dfDataLen 0x10000 +#define dfDataPieceLen 0x2000 + +static const unsigned char stCmd[8] = {221,222,223,224,225,226,227,228}; +static const unsigned char stPrm[8] = {0,1,2,3,4,5,6,7}; +static const unsigned char stHexNum[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'}; + +void TRealTimeData::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("系统调试->回路设备运行数据", Caption.Text); + + CtlIndex = 0; + IsStart = 0; + IsShowing = 0; + DrawLine = 0; + + ResetData(); +} + +void TRealTimeData::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TRealTimeData::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TRealTimeData::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TRealTimeData::DrawCaption2(void) +{ + +} + +void TRealTimeData::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + IsShowing = 1; + + TextRender_string24(300, 400, clNearBlack, "输入回路号地址号后按确认键"); +} + +void TRealTimeData::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + TextRender_string24(300, 400, clNearBlack, "输入回路号地址号后按确认键"); + aPanel->ReDrawItems(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->ReDrawItems(); + } +} + +void TRealTimeData::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +void TRealTimeData::ShowState() +{ + if(IsStart){ + TMyString::sFromStr("正在接收", aPanel->SText[2].Text); + }else{ + TMyString::sFromStr(" 已停止", aPanel->SText[2].Text); + } + aPanel->SText[2].Show(); +} + +//______________________________________________________________________________________________________________________________ + +void TRealTimeData::Check4Selected(void) +{ + unsigned int i; + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + default: + + break; + } +} + +void TRealTimeData::ResetData() +{ + int Top, i; + unsigned int aAddr; + + aAddr = dAddrSdRam_Commom; + for(i=0; i 20){ + SendTick = 0; + SendCmd(IsStart); + } + DrawList(); + } +} + +void TRealTimeData::DrawList() +{ + int i, m, aInx, Num, Num10, Tail, x, y; + unsigned int aAddr; + + while(PrcIndex != InputIndex){ + if(InputIndex >= dfDataPieceLen){ + ResetData(); + break; + } + PrcIndex++; + + aAddr = dAddrSdRam_Commom + PrcIndex * 8; + if(*(volatile unsigned char *)(aAddr) == 0)continue; + + aInx = *(volatile unsigned char *)(aAddr + 3); + if(aInx == 0){ + RecData[0] = *(volatile unsigned char *)(aAddr + 4); + RecData[1] = *(volatile unsigned char *)(aAddr + 5); + RecData[2] = *(volatile unsigned char *)(aAddr + 6); + RecData[3] = *(volatile unsigned char *)(aAddr + 7); + for(i=4; i<16; i++){ + RecData[i] = 0; + } + DrawLine++; + if(DrawLine >7){ + RectFillRender(Content.Left+8, Content.Top+ 60, Content.Right - 100, Content.Bottom - 40, Color); + DrawLine = 0; + } + y = Content.Top + 60; + y = y + DrawLine * 32; + x = Content.Left + 10; + for(i=0; i<4; i++){ + Num = RecData[i] % 16; + Num10 = RecData[i] / 16 % 16; + gui_write_EN2412(x,y,clNearBlack, stHexNum[Num10]); + x += 12; + gui_write_EN2412(x,y,clNearBlack, stHexNum[Num]); + x += 24; + } + }else{ + if(aInx < 4){ + RecData[aInx * 4 + 0] = *(volatile unsigned char *)(aAddr + 4); + RecData[aInx * 4 + 1] = *(volatile unsigned char *)(aAddr + 5); + RecData[aInx * 4 + 2] = *(volatile unsigned char *)(aAddr + 6); + RecData[aInx * 4 + 3] = *(volatile unsigned char *)(aAddr + 7); + y = Content.Top + 60; + y = y + DrawLine * 32; + x = Content.Left + 10 + aInx * 170; + for(i=0; i<4; i++){ + Num = RecData[aInx*4 +i] % 16; + Num10 = RecData[aInx*4 +i] / 16 % 16; + gui_write_EN2412(x,y,clNearBlack, stHexNum[Num10]); + x += 12; + gui_write_EN2412(x,y,clNearBlack, stHexNum[Num]); + x += 24; + } + } + } + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TRealTimeData::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) || + (aKey == VK_LEFT) || + (aKey == VK_RIGHT) + ){ + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].ReDraw(); + }else + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].ReDraw(); + } + } + + if(aKey == VK_UP){ + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + }else + if(aKey == VK_DOWN){ + if(CtlIndex <1){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + }else + if(aKey == VK_TAB){ + if(CtlIndex == 0){ + CtlIndex =1; + }else{ + CtlIndex =0; + } + Check4Selected(); + aPanel->ReDrawItems(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + if(IsStart == 0){ + IsStart = 1; + }else{ + IsStart = 0; + } + SendTick = 0; + ShowState(); + SendCmd(IsStart); + }else + if(aKey == VK_RETURN){ + IsShowing = 0; + IsStart = 0; + SendTick = 0; + SendCmd(IsStart); + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TRealTimeData::InitPanel(void) +{ + int x,y, aW,aH,i; + + x = Content.Left; + y = Content.Top; + aW = Content.Width; + aH = 40; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + aPanel->Caption.Text[0] = 0; + + aPanel->SText[0].Init(70,10,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(320,10,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(560,10,100,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路号:", aPanel->SText[0].Text); + TMyString::sFromStr("地址号:", aPanel->SText[1].Text); + TMyString::sFromStr(" 已停止", aPanel->SText[2].Text); + + aPanel->Edit[0].Init(170,10,40,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(420,10,50,30,x,y,clNearBlack,clNearWhite); + + for(i=0; i<2;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.Clear(); + } + aPanel->Edit[0].Str.FromStr("01"); + aPanel->Edit[1].Str.FromStr("001"); + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[1].SetMaxLen(3); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[1].Pst = 2; + + aPanel->Caption.Visible = 1; + + //aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + ShowState(); +} + +void TRealTimeData::SendCmd(int StartStop) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + if(StartStop){ + aIde.BitF.Cmd = cmQueryRuntimeData; + }else{ + aIde.BitF.Cmd = cmQueryAbout; + } + + Len = 4; + + //Path 0 + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP0 = cVal; + + //Path 1 + iVal = aPanel->Edit[1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aP1 = cVal; + + Path0 = aP0; + Path1 = aP1; + + //Prm + Data[0] = 0; + Data[1] = 0; + Data[2] = aP0; + Data[3] = aP1; + + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TRealTimeData::SendCmdAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + unsigned char aP0,aP1; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + aIde.BitF.Cmd = cmQueryAbout; + + + Len = 4; + + //Prm + Data[0] = 0; + Data[1] = 0; + Data[2] = Path0; + Data[3] = Path1; + + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + + +void TRealTimeData::PushOneDataReport(u8 aP0, u8 aP1, u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3) +{ + unsigned int aAddr; + InputIndex++; + if(InputIndex >= dfDataPieceLen){ + InputIndex = 0; + } + aAddr = dAddrSdRam_Commom + InputIndex * 8; + *(volatile unsigned char *)(aAddr + 0) = 1; + *(volatile unsigned char *)(aAddr + 1) = aP0; + *(volatile unsigned char *)(aAddr + 2) = aP1; + *(volatile unsigned char *)(aAddr + 3) = aInx; + *(volatile unsigned char *)(aAddr + 4) = D0; + *(volatile unsigned char *)(aAddr + 5) = D1; + *(volatile unsigned char *)(aAddr + 6) = D2; + *(volatile unsigned char *)(aAddr + 7) = D3; +} + +int TRealTimeData::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + IsStart = 0; + SendCmdAbort(); + return 0; +} + + + + + diff --git a/MyCode/Gui/RealTimeData.h b/MyCode/Gui/RealTimeData.h new file mode 100644 index 0000000..5a3dbc4 --- /dev/null +++ b/MyCode/Gui/RealTimeData.h @@ -0,0 +1,88 @@ +#ifndef REALTIMEDATA_H_ +#define REALTIMEDATA_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +#include "Record.h" + +class TRealTimeData{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + + u32 Color; + + int TabOrder; + + TRect Bound; + + TRect Content; + + unsigned char CtlIndex; + unsigned char IsStart; + unsigned char SendTick; + + unsigned char Data[12]; + unsigned char RecData[16]; + unsigned char NewIndex; + unsigned char DrawLine; + + int IsShowing; + int PrcIndex; + int InputIndex; + + unsigned char Path0; + unsigned char Path1; + + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TRealTimeData(){}; + TRealTimeData(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + void ShowState(); + void DrawList(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void Check4Selected(void); + + void SendCmd(int StartStop); + void SendCmdAbort(); + void ResetData(); + + void Task1000Ms(); + + void PushOneDataReport(u8 aP0, u8 aP1, u8 aInx, u8 D0, u8 D1, u8 D2, u8 D3); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + diff --git a/MyCode/Gui/RecoverAll.cpp b/MyCode/Gui/RecoverAll.cpp new file mode 100644 index 0000000..7beb510 --- /dev/null +++ b/MyCode/Gui/RecoverAll.cpp @@ -0,0 +1,184 @@ +#include "RecoverAll.h" +#include "Runtime.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +static const int xFirst = 10; + + +void TRecoverAll::Init() +{ + CtlIndex = 0; + IsShowing = 0; + + PermissionCmd =0; + IsPermission =0; +} + +void TRecoverAll::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick恢复出厂设置"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "恢复出厂设置"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "确定", 12, clNearWhite); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Advanced Setup->Factory Reset"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Factory Reset"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clBlue, "Reset", 6, clNearWhite); + } +} + +void TRecoverAll::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + if(LanguageEnCn==0) TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "确定", 12, clNearBlack); + else TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "Reset", 6, clNearBlack); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Bottom[0] + 40, 600 , 120, 3); + } + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +int TRecoverAll::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} + +void TRecoverAll::Task1000Ms() +{ + +} + + + + + + diff --git a/MyCode/Gui/RecoverAll.h b/MyCode/Gui/RecoverAll.h new file mode 100644 index 0000000..a09fd9d --- /dev/null +++ b/MyCode/Gui/RecoverAll.h @@ -0,0 +1,112 @@ +#ifndef RECOVERALL_H_ +#define RECOVERALL_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TRecoverAll{ + public: + static constexpr unsigned short hList[12] = {76,70,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 1, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4, + .Panel.Width = 796, + .Panel.Heigh = 140, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4 + 140 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + unsigned char PermissionCmd; + unsigned char IsPermission; + unsigned char Rsv1; + public: + TRecoverAll(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + static void sDelayMs(unsigned int aMs); + void DoCover(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void Task1000Ms(); + + void (*DoRecover)(void); + + int ExtRequst(unsigned char Prm); +}; + + + + +#endif diff --git a/MyCode/Gui/Register.cpp b/MyCode/Gui/Register.cpp new file mode 100644 index 0000000..f91c9c1 --- /dev/null +++ b/MyCode/Gui/Register.cpp @@ -0,0 +1,2381 @@ +#include "RuntimeData.h" +#include "Register.h" +#include "DevMask.h" +#include "server.h" + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" + #include "fdcan_task.h" + #include "uart_key_drv.h" + #include "HW_config.h" +} +#define dOffSetTransmite_Flag 0x10000 + +#define dclSearch clBlue +#define dclUpLoad clTeal + +class TItemList *TRegister::sIList; +void TRegister::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->自动注册"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "按\"确认\"键开始本机注册,若需注册单一回路可设置"); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 36, 120, 30, 7, clBlue, "开始注册", 14, clNearWhite); + + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "分回路注册"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "回路号"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 76, 120, 30, 7, clNearWhite, "回路注册", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Auto Register"); + TextRender_string24(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 4, clNearWhite, ItemColor, "All loops register"); + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 36, 120, 30, 7, clBlue, "Register", 14, clNearWhite); + + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 4, clNearWhite, ItemColor, "Single Loop Register"); + TextRender_string24(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 38, clNearWhite, ItemColor, "LoopID"); + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 76, 120, 30, 7, clNearWhite, "Register", 14, clNearBlack); + } +} + +void TRegister::Init() +{ + IsOnShow = 0; + IsOnGo = 0; + IsPermission = 0; + + InitDataBuf(); + IsDevRegisting = 0; + IsTimeOutReturn = 0; + + Tag.Reset(); + if(MainCtl.fData.Split.NetworkMode== 1){ + Tag.InxMax = 6; + }else{ + Tag.InxMax = 2; + } + + IsOverWrite =1; +} + +void TRegister::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TRegister::DrawSelf(void) +{ + RenderBackGround(); + + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iEdit[0].Init(Lv.Grid.Left[1] +100, Lv.Grid.Top[1] + 36, 100,30,0,0,1,clNearBlack); + IList->Edit[0].SetMaxLen(2); + IList->Edit[0].Str.Clear(); + IList->Edit[0].SetText("01", 24); + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + + if(Tag.InxMax > 2){ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "远程注册"); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "机器号"); + }else{ + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "Register Via Remoting"); + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 38, clNearWhite, ItemColor, "CtlID"); + } + IList->Edit[1].Init(Lv.Grid.Left[2] +100, Lv.Grid.Top[2] + 36, 100,30,0,0,1,clNearBlack); + IList->Edit[1].SetMaxLen(2); + IList->Edit[1].Str.Clear(); + IList->Edit[1].SetText("01", 24); + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + if(LanguageEnCn==0){ + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 80, clNearWhite, ItemColor, "回路号"); + }else{ + TextRender_string24(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 80, clNearWhite, ItemColor, "LoopID"); + } + IList->Edit[2].Init(Lv.Grid.Left[2] +100, Lv.Grid.Top[2] + 80, 100,30,0,0,1,clNearBlack); + IList->Edit[2].SetMaxLen(2); + IList->Edit[2].Str.Clear(); + IList->Edit[2].SetText("01", 24); + IList->Edit[2].SetPstTail(); + IList->Edit[2].Show(); + if(LanguageEnCn==0){ + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 120, 128, 30, 5, clNearWhite, "全回路注册", 4, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +160, Lv.Grid.Top[2] + 120, 128, 30, 5, clNearWhite, "分回路注册", 4, clNearBlack); + }else{ + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 120, 128, 30, 5, clNearWhite, "RegAllLoop", 4, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +160, Lv.Grid.Top[2] + 120, 128, 30, 5, clNearWhite, "Reg Single", 4, clNearBlack); + } + } +} + +void TRegister::DrawCommonByExReturn() +{ + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + //if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + DrawFixText(); + IList->Edit[0].Show(); + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +void TRegister::Show() +{ + IsOnShow = 1; + DrawSelf(); +} + +void TRegister::Show4Slave() +{ + IsOnShow = 1; + IsOnNetwork = 2; + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路注册,集中机呼叫执行,请稍后"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Registering,Call By Master,Wait"); + } + + for(int i=0; iEdit[0].Selected = 0; + IList->Edit[0].Show(); + break; + case 2: + if(LanguageEnCn==0)tText="回路注册"; else tText="Register"; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 76, 120, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 3: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + break; + case 4: + IList->Edit[2].Selected = 0; + IList->Edit[2].Show(); + break; + case 5: + if(LanguageEnCn==0)tText="全回路注册"; else tText="RegAllLoop"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 120, 128, 30, 5, clNearWhite, tText, 4, clNearBlack); + break; + case 6: + if(LanguageEnCn==0)tText="分回路注册"; else tText="Reg Single"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +160, Lv.Grid.Top[2] + 120, 128, 30, 5, clNearWhite, tText, 4, clNearBlack); + break; + } +} + +void TRegister::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + if(LanguageEnCn==0)tText="开始注册"; else tText="Register"; + TRoundRect::sDrawBySize(Lv.Grid.Left[0] +16, Lv.Grid.Top[0] + 36, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 1: + IList->Edit[0].Selected = 1; + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 2: + if(LanguageEnCn==0)tText="回路注册"; else tText="Register"; + TRoundRect::sDrawBySize(Lv.Grid.Left[1] +16, Lv.Grid.Top[1] + 76, 120, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 3: + IList->Edit[1].Selected = 1; + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + case 4: + IList->Edit[2].Selected = 1; + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + break; + case 5: + if(LanguageEnCn==0)tText="全回路注册"; else tText="RegAllLoop"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +16, Lv.Grid.Top[2] + 120, 128, 30, 5, clBlue, tText, 4, clNearWhite); + break; + case 6: + if(LanguageEnCn==0)tText="分回路注册"; else tText="Reg Single"; + TRoundRect::sDrawBySize(Lv.Grid.Left[2] +160, Lv.Grid.Top[2] + 120, 128, 30, 5, clBlue, tText, 4, clNearWhite); + break; + } +} + +void TRegister::ShowPortCount() +{ + int PortCount =0; + for(int i=0; i 40)return; + if(RegWhat){ + if(RegWhat == aP0)SearchCompleted[aP0-1] = 1; + }else{ + SearchCompleted[aP0-1] = 1; + } + }else + if(aCmd == cmPortRegistProgress){ + aP0 = aIm.Splite.P0; + if(aP0 == 0)return; + if(aP0 > 40)return; + aPgs = aIm.Splite.P1; + if(RegWhat){ + if(RegWhat == aP0){ + HasRpy[aP0-1] = 1; + ProgressVal[aP0 -1] = aPgs; + } + }else{ + HasRpy[aP0-1] = 1; + ProgressVal[aP0 -1] = aPgs; + } + }else + if(aCmd == cmQueryPortReg){ + //D0 D1=PortNum D2=Index D3-7 dType + aP0 = aIm.Splite.PCtlNum; + aPgs = aIm.Splite.P0; + if(aP0 == 0)return; + if(aP0 > 40)return; + if(aPgs == 0)return; + if(aPgs > 50)return; + RecData[3] = aIm.Splite.P1; + RecData[4] = aIm.Splite.P2; + RecData[5] = aIm.Splite.dType; + RecData[6] = aIm.Splite.Data0; + RecData[7] = aIm.Splite.Data1; + PushRegisterData(aP0, aPgs); + } +} + +void TRegister::PermissionCmdReturnDraw() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + +} + +void TRegister::PermissionCmdGO() +{ + if(PermissionCmd == 0){ + //Local All + IsOnNetwork = 0; + HasDrawDetailOnFinish = 0; + InitDataBuf(); + ClearProgressVal(); + Count.Reset(); + IsTimeOutReturn = 0; + WastTimeSec = 0; + TotalProgress = 0; + QueryTimeOut = 0; + IsTransmiting = 0; + IsQuerying = 0; + if(1){ + IsOverWrite = 1; + }else{ + IsOverWrite = 0; + } + RegWhat = 0; + SendCmdAll(); + IsOnGo = 1; + HasDone = 0; + ResetHasSend = 0; + RdyToShowTick = 0; + DelayCheckTick = 0; + IsDevRegisting = 0x00A5A5A5; + Record.OperateAdd_Registe(1); + + for(int i=0;i<4;i++)Psv.Exist[i] =0; + }else + if(PermissionCmd == 1){ + //Local One Port + IsOnNetwork = 0; + HasDrawDetailOnFinish = 0; + InitDataBuf(); + ClearProgressVal(); + Count.Reset(); + IsTimeOutReturn = 0; + WastTimeSec = 0; + TotalProgress = 0; + QueryTimeOut = 0; + IsTransmiting = 0; + IsQuerying = 0; + if(1){ + IsOverWrite = 1; + }else{ + IsOverWrite = 0; + } + RegWhat = PortNumOnGoing; + //SendCmdAll(); + SendCmdOne(PortNumOnGoing); + IsOnGo = 1; + HasDone = 0; + ResetHasSend = 0; + RdyToShowTick = 0; + DelayCheckTick = 0; + IsDevRegisting = 0x00A5A5A5; + Record.OperateAdd_Registe(1); + }else + if(PermissionCmd == 2){ + //Network All + MasterStartByRemote(Nw.CtlNum, PortNumOnGoing); + }else + if(PermissionCmd == 3){ + //Network One Port + MasterStartByRemote(Nw.CtlNum, PortNumOnGoing); + } +} + +TGuiMsgReturn TRegister::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char tCtlNum, aCc, Ow, Err; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + } + + if(IsOnGo){ + switch(aKey){ + case VK_UP: + + break; + case VK_DOWN: + + break; + case VK_TAB: + + break; + case VK_EXECUTE: + + break; + case VK_RETURN: + //IsOnShow = 0; + //IsOnGo =0; + //aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + if(Tag.Inx ==1){ + IList->Edit[0].KeyIn(aKey); + aCc = IList->Edit[0].Str.ToInteger(); + if( (aCc == 0) || (aCc > 24) ){ + IList->Edit[0].SelectedColor = clRed; + }else{ + IList->Edit[0].SelectedColor = clBlue; + } + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + }else + if(Tag.Inx ==3){ + IList->Edit[1].KeyIn(aKey); + aCc = IList->Edit[1].Str.ToInteger(); + if( (aCc == 0) || (aCc > dNETWORK_MACHINE_COUNT) ){ + IList->Edit[1].SelectedColor = clRed; + }else{ + IList->Edit[1].SelectedColor = clBlue; + } + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + }else + if(Tag.Inx ==4){ + IList->Edit[2].KeyIn(aKey); + aCc = IList->Edit[2].Str.ToInteger(); + if( (aCc == 0) || (aCc > 24) ){ + IList->Edit[2].SelectedColor = clRed; + }else{ + IList->Edit[2].SelectedColor = clBlue; + } + IList->Edit[2].Show(); + IList->Edit[2].ShowCursor(); + }else + if(Tag.Inx == 5){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + } + }else + if(Tag.Inx == 6){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + } + break; + case VK_UP: + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx 2){ + PermissionCmd = 0; + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = 0; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else + if(Tag.Inx == 2){ + aCc = IList->Edit[0].Str.ToInteger(); + if( (aCc >0) && (aCc < 25) ){ + PortNumOnGoing = aCc; + if(SystemPermission > 2){ + PermissionCmd = 1; + PermissionCmdGO(); + }else{ + IsPermission = 1; + PermissionCmd = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + }else + if(Tag.Inx == 5){ + //NetWork all Port + tCtlNum = IList->Edit[1].Str.ToInteger(); + if( (tCtlNum) && (tCtlNum<=dNETWORK_MACHINE_COUNT) ){ + if( (tCtlNum < ProtoC2C.CtlMask.StartNum) || (tCtlNum > ProtoC2C.CtlMask.EndNum) ){ + if(ProtoC2C.CheckIsInSlaveList(tCtlNum)){ + IsOnNetwork = 1; + Nw.CtlNum = tCtlNum; + PortNumOnGoing =0; + PermissionCmd = 2; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + } + }else + if(Tag.Inx == 6){ + //NetWork a Port + tCtlNum = IList->Edit[1].Str.ToInteger(); + if( (tCtlNum) && (tCtlNum<=dNETWORK_MACHINE_COUNT) ){ + if( (tCtlNum < ProtoC2C.CtlMask.StartNum) || (tCtlNum > ProtoC2C.CtlMask.EndNum) ){ + if(ProtoC2C.CheckIsInSlaveList(tCtlNum)){ + IsOnNetwork = 1; + aCc = IList->Edit[2].Str.ToInteger(); + if( (aCc >0) && (aCc < 25) ){ + Nw.CtlNum = tCtlNum; + PortNumOnGoing = aCc; + PermissionCmd = 3; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + } + } + } + } + } + break; + case VK_RETURN: + IsOnShow = 0; + IsOnGo =0; + IsDevRegisting = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TRegister::ClearProgressVal() +{ + int i; + IsQuerying =0; + QueryNum =0; + for(i=0; i<40; i++){ + ProgressVal[i] = 0; + SearchCompleted[i] = 0; + HasRpy[i] =0; + HasQuery[i] =0; + TransmiteCompleted[i] = 0; + ItemsCount[i] =0; + } +} + +void TRegister::SendCmdAll() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =1; + + aIde.BitF.Cmd = cmAllPortAutoRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TRegister::SendCmdOne(unsigned char aCc) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =4; + + aIde.BitF.Cmd = cmSinglePortAutoRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TRegister::SendCmdQuery(unsigned char aCc) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmQueryPortReg; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +void TRegister::SendCmdAbort() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmPortRegistAbort; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = ReqPath; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, Data, Len); +} + +unsigned char TRegister::GetItemsCount(unsigned char aCc) +{ + unsigned int aAddr,x; + int i; + x = aCc; + x = x * 256; + aAddr = dAddrSdRam_Register + x; + x = 0; + for(i=0; i<250; i++){ + if(*(volatile unsigned char *)(aAddr)){ + x++; + } + } + return x; +} + +int TRegister::CheckIsDone() +{ + int i, done; + done = 1; + if(WastTimeSec > 20){ + if(TotalProgress > 60){ + for(i=0; i 300){ + IsOnGo = 0; + if(LanguageEnCn==0) + TextRender_string24(Lv.PanelSmall.Left, Lv.PanelSmall.Top + 46 ,clNearWhite, ContentColor, "注册超时,返回 "); + else + TextRender_string24(Lv.PanelSmall.Left, Lv.PanelSmall.Top + 46 ,clNearWhite, ContentColor, "Time Out,Return "); + //SaveToFlash(); + IsTimeOutReturn = 1; + return 1; + } + return 0; +} + +int TRegister::Task1000Ms() +{ + int i, dn; + if(IsOnNetwork == 0){ + if(IsOnShow == 0)return 0; + if(IsOnGo == 0)return 0; + PreventPermissionDown(); + PreventEventShow(); + + if(WastTimeSec < 400)WastTimeSec++; + if(RdyToShowTick <2){ + RdyToShowTick++; + return 0; + } + + ShowPortCount(); + + if(HasDone){ + if(ResetHasSend == 0){ + if(get_can_tx_complete()){ + ResetHasSend = 1; + IsOnGo = 0; + //DevMask.ClearAllMask(); + //CtlCenter.ReadMaskFromFlash(); + //ExRecord.SetStateCodeMask(); + //FecBusCRT.SetStateCodeMask(); + Record.ReadDevUserSet(); + ProtoC2C.ResetCoomm(); + FecBusCRT.ResetCallBack(); + FecStd.ResetCallBack(); + Record.OperateAdd_Registe(2); + Record.OperateAdd_Reset(MainCtl.fData.Split.MyNum); + ResetCallBack(); + IsDevRegisting = 0; + MainMenu.Hide(); + return 100; + } + } + return 0; + }else + if(IsTimeOutReturn){ + if(ResetHasSend == 0){ + if(get_can_tx_complete()){ + SendCmdAbort(); + ResetHasSend = 1; + IsOnGo = 0; + ProtoC2C.ResetCoomm(); + FecBusCRT.ResetCallBack(); + ResetCallBack(); + IsDevRegisting = 0; + MainMenu.Hide(); + return 100; + } + } + return 0; + } + + if(CheckIsDone())return 0; + + if(RegWhat == 0){ + if(DelayCheckTick < 15){ + DelayCheckTick++; + }else{ + if(IsQuerying == 0){ + dn = 1; + for(i=0; i= (dPORT_MAX_COUNT-1)){ + QueryNum = 0; + }else{ + QueryNum++; + } + } + }else{ + QueryTimeOut++; + if(QueryTimeOut > 20){ + QueryTimeOut = 0; + IsTransmiting = 0; + } + if(TransmiteCompleted[QueryNum]){ + ItemsCount[QueryNum] = GetItemsCount(QueryNum); + IsTransmiting = 0; + } + } + + } + } + }else{ + const unsigned char aP0 = RegWhat-1; + if(DelayCheckTick < 15){ + DelayCheckTick++; + }else{ + if(IsQuerying == 0){ + dn = 1; + if(HasRpy[aP0]){ + if(SearchCompleted[aP0] == 0){ + dn = 0; + } + } + if(dn){ + QueryTimeOut = 0; + IsTransmiting = 0; + IsQuerying = 1; + } + }else{ + if(IsTransmiting == 0){ + if(SearchCompleted[aP0]){ + if(TransmiteCompleted[aP0] == 0){ + ClearCircuitTranmiteData(aP0); + SendCmdQuery(RegWhat); + QueryTimeOut = 0; + IsTransmiting = 1; + } + } + }else{ + QueryTimeOut++; + if(QueryTimeOut > 20){ + QueryTimeOut = 0; + IsTransmiting = 0; + } + if(TransmiteCompleted[aP0]){ + ItemsCount[aP0] = GetItemsCount(aP0); + IsTransmiting = 0; + } + } + + } + } + } + DrawProgressAll(); + }else + if(IsOnNetwork == 1){ + if(IsOnShow == 0)return 0; + if(IsOnGo == 0)return 0; + PreventPermissionDown(); + PreventEventShow(); + + if(WastTimeSec < 600)WastTimeSec++; + if(Nw.SlaveState == 0){ + if(LanguageEnCn==0)TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "等待区域机响应 "); + else TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "Wait for Slaver Rpy"); + if(WastTimeSec > 16){ + if(LanguageEnCn==0)TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "区域机无响应,已退回"); + else TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "Slaver Offline,Back"); + IsOnNetwork =0; + IsOnGo = 0; + IsDevRegisting =0; + }else{ + TextDigitRender2_24(Lv.Panel.Left+ 186, Lv.Panel.Top + 4, clNearWhite, PanelColor, 16- WastTimeSec); + } + } + if(RdyToShowTick <2){ + RdyToShowTick++; + return 0; + } + + if(Nw.SlaveState == 2){ + if(LanguageEnCn==0)TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "区域机已拒绝执行 "); + else TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "Slaver Rejected "); + IsOnNetwork =0; + IsOnGo = 0; + IsDevRegisting =0; + }if(Nw.SlaveState == 3){ + if(LanguageEnCn==0)TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "区域机远程任务繁忙 "); + else TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "Slaver Busy "); + IsOnNetwork =0; + IsOnGo = 0; + IsDevRegisting =0; + }else + if(Nw.SlaveState == 1){ + if(Nw.Completed){ + if(Nw.MasterShowDetailTick == 0){ + ShowDetail(1); + }else + if(Nw.MasterShowDetailTick >4){ + if(LanguageEnCn==0) + TextRender_string24(Lv.PanelSmall.Left, Lv.PanelSmall.Top + 46 ,clNearWhite, ContentColor, "已完成"); + else + TextRender_string24(Lv.PanelSmall.Left, Lv.PanelSmall.Top + 46 ,clNearWhite, ContentColor, "Completed"); + IsOnNetwork =0; + IsOnGo = 0; + IsDevRegisting =0; + }else{ + + } + Nw.MasterShowDetailTick++; + }else{ + if(Nw.HadTransited2Master){ + if(CompCount()){ + Nw.Completed = 1; + MasterSendCmdEpCountCorrect(); + }else{ + MasterSendCmdReqEpCount(); + } + Nw.HadTransited2Master = 0; + } + if(Nw.EpCountHasUpdate){ + ShowDetail(1); + Nw.EpCountHasUpdate =0; + } + if(Nw.PortCountHasUpdate){ + //Show Port Count + if(LanguageEnCn==0)TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "区域机 "); + else TextRender_string24(Lv.Panel.Left+6, Lv.Panel.Top + 4, clNearWhite, PanelColor, "Slaver "); + TextDigitRender2_24(Lv.Panel.Left+ 88, Lv.Panel.Top + 4, clNearWhite, PanelColor, Nw.CtlNum); + + if(LanguageEnCn==0)TextRender_string24(Lv.Panel.Left+130, Lv.Panel.Top + 4, clNearWhite, PanelColor, "回路数量 "); + else TextRender_string24(Lv.Panel.Left+130, Lv.Panel.Top + 4, clNearWhite, PanelColor, "Loop(s) "); + TextDigitRender2_24(Lv.Panel.Left+ 226, Lv.Panel.Top + 4, clNearWhite, PanelColor, Nw.PortCount); + Nw.PortCountHasUpdate =0; + } + if(Nw.ProgressHasUpdate){ + int x,y; + x = Lv.PanelSmall.Left; y = Lv.PanelSmall.Top +6; + TProgressBar::sDrawBySize(x,y,Lv.PanelSmall.Width-100, 32,Nw.ProgressVal,100,dclSearch,clGray,clBlack); + y += 4; + x = Lv.PanelSmall.Right - 80; + TextDigitRender3Right24(x,y ,clNearWhite, ContentColor, Nw.ProgressVal); + x = Lv.PanelSmall.Right - 80 + 36; + TextRender_string24(x, y ,clNearWhite, "%"); + if(Nw.ProgressVal ==100){ + Nw.HasDone =1; + } + Nw.ProgressHasUpdate =0; + } + } + } + if(WastTimeSec > 400){ + IsOnGo = 0; + if(LanguageEnCn==0)TextRender_string24(Lv.PanelSmall.Left, Lv.PanelSmall.Top + 46 ,clNearWhite, ContentColor, "注册超时,返回 "); + else TextRender_string24(Lv.PanelSmall.Left, Lv.PanelSmall.Top + 46 ,clNearWhite, ContentColor, "Time Out "); + //SaveToFlash(); + IsOnGo = 0; + IsDevRegisting =0; + return 1; + } + }else + if(IsOnNetwork == 2){ + //Move to Server.cpp + //SlaveModeTask1000Ms(); + } + return 0; +} + + +void TRegister::SlaveModeTask1000Ms() +{ + int i, dn; + + if(IsOnShow == 0)return; + if(IsOnGo == 0)return; + PreventPermissionDown(); + PreventEventShow(); + + if(WastTimeSec < 410)WastTimeSec++; + if(WastTimeSec > 400){ + if(ResetHasSend == 0){ + if(get_can_tx_complete()){ + SendCmdAbort(); + ResetHasSend = 1; + IsOnGo = 0; + Record.ReadDevUserSet(); + ProtoC2C.ResetCoomm(); + FecBusCRT.ResetCallBack(); + ResetCallBack(); + IsDevRegisting = 0; + MainMenu.Hide(); + return; + } + } + return; + } + if(RdyToShowTick <2){ + RdyToShowTick++; + return; + } + + ShowPortCount(); + + if(HasDone){ + if(ResetHasSend == 0){ + if(Nw.Completed){ + if(Nw.Wait4SendFinishedTick<11)Nw.Wait4SendFinishedTick++; + if(Nw.Wait4SendFinishedTick > 10){ + if(get_can_tx_complete()){ + ResetHasSend = 1; + IsOnShow =0; + IsOnGo = 0; + //DevMask.ClearAllMask(); + //CtlCenter.ReadMaskFromFlash(); + //ExRecord.SetStateCodeMask(); + //FecBusCRT.SetStateCodeMask(); + ProtoC2C.ResetCoomm(); + FecBusCRT.ResetCallBack(); + FecStd.ResetCallBack(); + Record.OperateAdd_Registe(2); + Record.OperateAdd_Reset(MainCtl.fData.Split.MyNum); + ResetCallBack(); + IsDevRegisting = 0; + MainMenu.Hide(); + return; + } + } + return; + }else{ + if(Nw.ReSendEpCountTick > 12){ + Nw.ReSendEpCountTick = 0; + SlaveReplyAllEpCount(); + } + Nw.ReSendEpCountTick ++; + } + } + return; + } + + if(CheckIsDone())return; + + if(RegWhat == 0){ + if(DelayCheckTick < 15){ + DelayCheckTick++; + }else{ + if(IsQuerying == 0){ + dn = 1; + for(i=0; i= (dPORT_MAX_COUNT-1)){ + QueryNum = 0; + }else{ + QueryNum++; + } + } + }else{ + QueryTimeOut++; + if(QueryTimeOut > 20){ + QueryTimeOut = 0; + IsTransmiting = 0; + } + if(TransmiteCompleted[QueryNum]){ + ItemsCount[QueryNum] = GetItemsCount(QueryNum); + IsTransmiting = 0; + } + } + + } + } + }else{ + const unsigned char aP0 = RegWhat-1; + if(DelayCheckTick < 15){ + DelayCheckTick++; + }else{ + if(IsQuerying == 0){ + dn = 1; + if(HasRpy[aP0]){ + if(SearchCompleted[aP0] == 0){ + dn = 0; + } + } + if(dn){ + QueryTimeOut = 0; + IsTransmiting = 0; + IsQuerying = 1; + } + }else{ + if(IsTransmiting == 0){ + if(SearchCompleted[aP0]){ + if(TransmiteCompleted[aP0] == 0){ + ClearCircuitTranmiteData(aP0); + SendCmdQuery(RegWhat); + QueryTimeOut = 0; + IsTransmiting = 1; + } + } + }else{ + QueryTimeOut++; + if(QueryTimeOut > 20){ + QueryTimeOut = 0; + IsTransmiting = 0; + } + if(TransmiteCompleted[aP0]){ + ItemsCount[aP0] = GetItemsCount(aP0); + IsTransmiting = 0; + } + } + + } + } + } + DrawProgressAll(); +} + +void TRegister::ClearCircuitTranmiteData(unsigned char aCc) +{ + int y, iCc; + unsigned int aAddr; + + iCc = aCc; + + aAddr = dAddrSdRam_Register; + for(y=0; y<64; y++){ + *(volatile unsigned int *)(aAddr + (iCc*256) + y * 4) = 0; + } + aAddr = dAddrSdRam_Register + dOffSetTransmite_Flag; + for(y=0; y<50; y++){ + *(volatile unsigned char *)(aAddr + (iCc * 50) + y) =0; + } +} + +void TRegister::PushRegisterData(unsigned char aCc, unsigned char aInx) +{ + int x, y, aCount; + unsigned int aAddr; + + if(RegWhat){ + if(aCc != RegWhat)return; + } + + x = aCc -1; + y = (aInx-1) * 5; + aAddr = dAddrSdRam_Register; + *(volatile unsigned char *)(aAddr + (x*256) + y + 0) = RecData[3]; + *(volatile unsigned char *)(aAddr + (x*256) + y + 1) = RecData[4]; + *(volatile unsigned char *)(aAddr + (x*256) + y + 2) = RecData[5]; + *(volatile unsigned char *)(aAddr + (x*256) + y + 3) = RecData[6]; + *(volatile unsigned char *)(aAddr + (x*256) + y + 4) = RecData[7]; + + y = (aInx -1); + aAddr = dAddrSdRam_Register + dOffSetTransmite_Flag; + *(volatile unsigned char *)(aAddr + (x * 50) + y) = 1; + + aCount =0; + for(y=0; y<50; y++){ + if(*(volatile unsigned char *)(aAddr + (x * 50) + y) )aCount++; + } + if(aCount >= 50)TransmiteCompleted[x] = 1; + + QueryNumRpy = x; +} + +void TRegister::KeyPadUartPushData(unsigned char aCmd, unsigned char *pData) +{ + unsigned char tHwType, tNum, tLen; + int i,x; + + if(IsOnShow == 0)return; + if(IsOnGo == 0)return; + tHwType = pData[0]; + tNum = pData[1]; + tLen = pData[2]; + if(aCmd == cmQueryBoardModel){ + if(tHwType == btPowerSuply){ + if( tNum < 4 ){ + } + } + }else + if(aCmd == cmQueryVer){ + if(tHwType == btPowerSuply){ + if( tNum < 4 ){ + Psv.Exist[tNum] =1; + } + } + } +} + +void TRegister::GetEpDevCount() +{ + unsigned int aAddr; + unsigned int i,m; + int aPc, aCount; + unsigned char aType; + unsigned int aP0; + //if(IsOnNetwork == 0){ + if(1){ + if(RegWhat == 0){ + //Show Data + Count.Reset(); + aAddr = dAddrSdRam_Register; + for(m=0; m= dPORT_MAX_COUNT)return; + Count.Reset(); + aAddr = dAddrSdRam_Register; + if(TransmiteCompleted[aP0]){ + for(i=0; i<250; i++){ + aType = *(volatile unsigned char *)(aAddr + (aP0*256) + i); + if(aType){ + Count.All++; + if( (aType == dgTYPE_SMOKE_DETECTOR) ){ + Count.Smoke++; + }else + if( aType == dgTYPE_TEMPE_DETECTOR ){ + Count.Tempe++; + }else + if( (aType == dgTYPE_HAND_REPORT ) ){ + Count.HandReport++; + }else + if( (aType == dgTYPE_FIRE_HydrantKp ) ){ + Count.HydKp++; + }else + if( (aType == dgTYPE_IN_MODULE ) ){ + Count.ModuleInput++; + }else + if( (aType == dgTYPE_INOUT_MODULE_NonSource) || + (aType == dgTYPE_INOUT_MODULE_Source) ){ + Count.ModuleInOut++; + }else + if( (aType == dgTYPE_OUT_MODULE) ){ + Count.ModuleOutput++; + }else + if( (aType == dgType_VAALRAM ) ){ + Count.Va++; + }else + if( aType == dgTYPE_DISPLAY_PAD ){ + Count.FDisplay++; + }else + if( aType == dgTYPE_SMOKE_TEMPE_DETECTOR ){ + Count.SmokeTempe++; + }else + if( aType == dgTYPE_LINKAGE_POWERSUPLY){ + Count.LINKAGE_POWERSUPLY++; + }else{ + Count.cOther++; + } + } + } + } + } + }else{ + if(RegWhat == 0){ + + }else + if(RegWhat){ + + } + } +} + +int TRegister::CompCount() +{ + int tAll =0; + tAll += Count.Smoke; + tAll += Count.Tempe; + tAll += Count.HandReport; + tAll += Count.HydKp; + tAll += Count.ModuleInput; + tAll += Count.ModuleInOut; + tAll += Count.ModuleOutput; + tAll += Count.Va; + tAll += Count.FDisplay; + tAll += Count.SmokeTempe; + tAll += Count.LINKAGE_POWERSUPLY; + tAll += Count.cOther; + + if(Count.All == tAll){ + return 1; + }else{ + return 0; + } +} + +void TRegister::LoadToMainCtl() +{ + unsigned int aAddr; + unsigned int i,m; + int aPc, aCount; + unsigned char aType; + unsigned int aP0; + if( (IsOnNetwork == 0) || (IsOnNetwork == 2) ){ + if(RegWhat == 0){ + if(IsOverWrite){ + for(m=0; m= dPORT_MAX_COUNT)return; + if(IsOverWrite){ + for(i=0; i<256; i++){ + Port[aP0].ExistTable[i] = 0; + Port[aP0].dTypeTable[i] = 0; + //EpDev[aP0][i].fData.Split.dType = 0; + //EpDev[aP0][i].fData.Split.Id = 0; + } + MainCtl.fData.Split.ExistTablePort[aP0] = 0; + } + + if(TransmiteCompleted[aP0]){ + MainCtl.fData.Split.ExistTablePort[aP0] = 0xA5; + Port[aP0].fData.Port.dType = dgTYPE_PORT; + Port[aP0].fData.Port.Id = aP0+1; + aAddr = dAddrSdRam_Register; + + for(i=0; i<250; i++){ + aType = *(volatile unsigned char *)(aAddr + (aP0*256) + i); + if(aType){ + Port[aP0].ExistTable[i] = 0xA5; + Port[aP0].dTypeTable[i] = aType; + //EpDev[aP0][i].fData.Split.dType = aType; + //EpDev[aP0][i].fData.Split.Id = i+1; + } + } + if(IsOverWrite){ + Port[aP0].fData.Port.ResistedCount = aCount; + }else{ + + } + } + + + aPc = 0; + for(m=0; mdPORT_MAX_COUNT)return; + i=aPort-1; + + sIList->ReadWriteData.Reset(); + LoopCheck1S(); + for(m=0; mReadWriteData.D8[m] = Port[i].ExistTable[m]; + } + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * i) + (256 * 0); + nor_write_page(0, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + + LoopCheck1S(); + //write dType + for(m=0; mReadWriteData.D8[m] = Port[i].dTypeTable[m]; + } + Crc32Reset(); + for(m=0; m(Port[i].ExistTable[m])); + for(m=0; m(Port[i].dTypeTable[m])); + tDm.D32 = Crc32GetResult(); + sIList->ReadWriteData.D8[252] = tDm.D8[0]; + sIList->ReadWriteData.D8[253] = tDm.D8[1]; + sIList->ReadWriteData.D8[254] = tDm.D8[2]; + sIList->ReadWriteData.D8[255] = tDm.D8[3]; + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * i) + (256 * 1); + nor_write_page(0, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + + LoopCheck1S(); + //write DisplaySetting + Port[i].SortDisplayPad(); + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * i) + (256 * 2); + nor_write_byte_via_page(0, fAddr, &Port[i].DisplayPadSet[0].MemBytes[0], 256); + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + LoopCheck1S(); + Crc32Reset(); + for(m=0; m<16; m++){ + for(int x=0; x<4; x++)Crc32Feed(Port[i].DisplayPadSet[m].MemD32[x]); + } + tDm.D32 = Crc32GetResult(); + sIList->ReadWriteData.D8[0] = tDm.D8[0]; + sIList->ReadWriteData.D8[1] = tDm.D8[1]; + sIList->ReadWriteData.D8[2] = tDm.D8[2]; + sIList->ReadWriteData.D8[3] = tDm.D8[3]; + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * i) + (256 * 3); + nor_write_byte_via_page(0, fAddr, sIList->ReadWriteData.D8, 256); + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); +} + +void TRegister::sWritePortList() +{ + int m; + volatile unsigned int fAddr, aFlashState; + TDMix tDm; + if(sIList==nullptr)return; + sIList->ReadWriteData.Reset(); + + Crc32Reset(); + for(m=0; mReadWriteData.D8[m] = 0xA5; + } + Crc32Feed(static_cast(sIList->ReadWriteData.D8[m])); + } + tDm.D32 = Crc32GetResult(); + sIList->ReadWriteData.D8[dPORT_MAX_COUNT +0] = tDm.D8[0]; + sIList->ReadWriteData.D8[dPORT_MAX_COUNT +1] = tDm.D8[1]; + sIList->ReadWriteData.D8[dPORT_MAX_COUNT +2] = tDm.D8[2]; + sIList->ReadWriteData.D8[dPORT_MAX_COUNT +3] = tDm.D8[3]; + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * dPORT_MAX_COUNT ) + (256 * 0); + nor_write_page(0, fAddr, sIList->ReadWriteData.D8); + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); +} + +void TRegister::SaveToFlash() +{ + unsigned int i,m; + volatile unsigned int aFlashState; + TDMix tDm; + if( (IsOnNetwork != 0) && (IsOnNetwork != 2) )return; + + //Save Power Supply Inf + if(RegWhat == 0){ + if(Psv.Exist[0]){ + //Record.WritePowerSuplyCount(Psv.Exist[1], Psv.Exist[2]); + //Record.ReadPowerSuplyCount(); + } + } + + do{ + sDelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + for(i=0; i<8; i++){ + fAddr = dFlashRegisterDataAddr + (0x000010000 * i); + nor_erase_sector_64k(0,fAddr); + sDelayMs(250); + do{ + sDelayMs(30); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + } + + for(i=0; i(aCnt & 0x00FF); + HiByte = static_cast(aCnt >> 8); + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Priority = 1; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Order = 0; + ProtoC2C.TxMsg.Data.Identification = 0; + + ProtoC2C.TxMsg.Data.Data[0] = 0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_DevRegRpyEpCount; + ProtoC2C.TxMsg.Data.Data[3] = aDType; + ProtoC2C.TxMsg.Data.Data[4] = LowByte; + ProtoC2C.TxMsg.Data.Data[5] = HiByte; + ProtoC2C.TxMsg.Data.Data[6] = 0; + ProtoC2C.TxMsg.Data.Data[7] = 0; + ProtoC2C.oBufInsert(); +} + + +void TRegister::SlaveReplyPortCount(unsigned char aCnt) +{ + unsigned char LowByte, HiByte; + LowByte = static_cast(aCnt & 0x00FF); + HiByte = static_cast(aCnt >> 8); + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Priority = 1; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Order = 0; + ProtoC2C.TxMsg.Data.Identification = 0; + + ProtoC2C.TxMsg.Data.Data[0] = 0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_DevRegRpyPortCnt; + ProtoC2C.TxMsg.Data.Data[3] = aCnt; + ProtoC2C.TxMsg.Data.Data[4] = 0; + ProtoC2C.TxMsg.Data.Data[5] = 0; + ProtoC2C.TxMsg.Data.Data[6] = 0; + ProtoC2C.TxMsg.Data.Data[7] = 0; + ProtoC2C.oBufInsert(); +} + +void TRegister::SlaveReplyEpCountTransmited() +{ + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Priority = 1; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Order = 0; + ProtoC2C.TxMsg.Data.Identification = 0; + + ProtoC2C.TxMsg.Data.Data[0] = 0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_DevRegRpyEpCompleted; + ProtoC2C.TxMsg.Data.Data[3] = 0; + ProtoC2C.TxMsg.Data.Data[4] = 0; + ProtoC2C.TxMsg.Data.Data[5] = 0; + ProtoC2C.TxMsg.Data.Data[6] = 0; + ProtoC2C.TxMsg.Data.Data[7] = 0; + ProtoC2C.oBufInsert(); +} + +void TRegister::MasterSendCmdReqEpCount() +{ + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Priority = 1; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Order = 0; + ProtoC2C.TxMsg.Data.Identification = 0; + + ProtoC2C.TxMsg.Data.Data[0] = 0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_DevRegReqEpCount; + ProtoC2C.TxMsg.Data.Data[3] = Nw.CtlNum; + ProtoC2C.TxMsg.Data.Data[4] = 0; + ProtoC2C.TxMsg.Data.Data[5] = 0; + ProtoC2C.TxMsg.Data.Data[6] = 0; + ProtoC2C.TxMsg.Data.Data[7] = 0; + ProtoC2C.oBufInsert(); +} + +void TRegister::MasterSendCmdEpCountCorrect() +{ + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Priority = 1; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Order = 0; + ProtoC2C.TxMsg.Data.Identification = 0; + + ProtoC2C.TxMsg.Data.Data[0] = 0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_DevRegEpCountCorrect; + ProtoC2C.TxMsg.Data.Data[3] = Nw.CtlNum; + ProtoC2C.TxMsg.Data.Data[4] = 0; + ProtoC2C.TxMsg.Data.Data[5] = 0; + ProtoC2C.TxMsg.Data.Data[6] = 0; + ProtoC2C.TxMsg.Data.Data[7] = 0; + ProtoC2C.oBufInsert(); +} + +void TRegister::SlaveReplyAllEpCount() +{ + if(Count.Smoke >0) SlaveReplyEpCount(dgTYPE_SMOKE_DETECTOR, Count.Smoke); + if(Count.Tempe >0) SlaveReplyEpCount(dgTYPE_TEMPE_DETECTOR, Count.Tempe); + if(Count.HandReport >0) SlaveReplyEpCount(dgTYPE_HAND_REPORT, Count.HandReport); + if(Count.HydKp >0) SlaveReplyEpCount(dgTYPE_FIRE_HydrantKp, Count.HydKp); + if(Count.ModuleInput >0) SlaveReplyEpCount(dgTYPE_IN_MODULE, Count.ModuleInput); + if(Count.ModuleInOut >0) SlaveReplyEpCount(dgTYPE_INOUT_MODULE_Source, Count.ModuleInOut); + if(Count.ModuleOutput >0) SlaveReplyEpCount(dgTYPE_OUT_MODULE, Count.ModuleOutput); + if(Count.Va >0) SlaveReplyEpCount(dgType_VAALRAM, Count.Va); + if(Count.FDisplay >0) SlaveReplyEpCount(dgTYPE_DISPLAY_PAD, Count.FDisplay); + if(Count.SmokeTempe >0) SlaveReplyEpCount(dgTYPE_SMOKE_TEMPE_DETECTOR, Count.SmokeTempe); + if(Count.LINKAGE_POWERSUPLY > 0) SlaveReplyEpCount(dgTYPE_LINKAGE_POWERSUPLY, Count.LINKAGE_POWERSUPLY); + if(Count.cOther >0) SlaveReplyEpCount(0xFE, Count.cOther); + + SlaveReplyEpCount(0xFF, Count.All); + + SlaveReplyEpCountTransmited(); +} + +void TRegister::SlaveRpyEpCount() +{ + if((Register.IsOnGo) && (Register.IsOnNetwork == 2)){ + SlaveReplyAllEpCount(); + } +} + +void TRegister::SlaveRecMasterGotCompleted() +{ + if((Register.IsOnGo) && (Register.IsOnNetwork == 2)){ + Nw.Completed = 1; + } +} + +int TRegister::ExtRequst(unsigned char Prm) +{ + IsOnShow = 0; + IsOnGo =0; + SendCmdAbort(); + IsDevRegisting = 0; + return 0; +} + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/Register.h b/MyCode/Gui/Register.h new file mode 100644 index 0000000..2ea273b --- /dev/null +++ b/MyCode/Gui/Register.h @@ -0,0 +1,372 @@ +#ifndef REGISTER_H_ +#define REGISTER_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "EditML.h" +#include "CtlPanel1.h" + +#include "Record.h" + +#define nrCtl 0 +#define nrShowDetails 1 + +class TRegister{ + public: + static constexpr unsigned short hList[12] = {72,108,154,28, 26,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,290,290,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 4, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 220, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1, + + .PanelSmall.Active = 1, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 72, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 220 -1 + 1 + 72 -1, + }; + static constexpr TRect ModuleRectLv3 = { + .Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3] + 30, + + }; + static constexpr TRect ModuleRectLv4 = { + .Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + 30, + .Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + }; + static const unsigned int LvGridHighBottom3 = 102; + static constexpr unsigned char dTypeList[256] = { + dgTYPE_SMOKE_DETECTOR, + dgTYPE_TEMPE_DETECTOR, + dgType_VAALRAM, + }; + static constexpr unsigned char dSmokeSensGrade_MarkValue[8] = { + //100, 75, 50, 25 + 0, 100, 75, 50, 25, 0, 0, 0 + }; + + static constexpr unsigned char dNetDevRegCmdSeq[4][8] = { + "REMOTE\0", + "REGIST\0", + "TRY\0", + "START\0", + }; + + + public: + static class TItemList *sIList; + class TItemList *IList; + + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + void Reset(){ + Inx = 0; + InxMin = 0; + InxMax =2; + } + }Tag; + + class TThisMainCtl *aMc; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char IsOnShow; + unsigned char IsOnGo; + unsigned char IsOverWrite; + unsigned char IsOnNetwork; + unsigned char HasDrawDetailOnFinish; + //int SpendTime; + + unsigned char ProgressVal[40]; + unsigned char SearchCompleted[40]; + unsigned char HasRpy[40]; + unsigned char HasQuery[40]; + unsigned char TransmiteCompleted[40]; + unsigned char ItemsCount[40]; + unsigned char DelayCheckTick; + unsigned char IsTransmiting; + + struct{ + unsigned short All; + unsigned short Smoke; + unsigned short Tempe; + unsigned short HandReport; + unsigned short HydKp; + unsigned short ModuleInput; + unsigned short ModuleInOut; + unsigned short ModuleOutput; + unsigned short Va; + unsigned short FDisplay; + unsigned short SmokeTempe; + unsigned short LINKAGE_POWERSUPLY; + unsigned short cOther; + void Reset(){ + All =0; + Smoke =0; + Tempe =0; + HandReport =0; + HydKp =0; + ModuleInput =0; + ModuleInOut =0; + ModuleOutput =0; + Va =0; + FDisplay =0; + SmokeTempe =0; + LINKAGE_POWERSUPLY = 0; + cOther =0; + } + }Count; + + union{ + unsigned int D32[16]; + char Body[64]; + }Text; + unsigned char Data[8]; + unsigned char RecData[8]; + unsigned char RegWhat; + unsigned char ReqPath; + unsigned char IsQuerying; + unsigned char QueryNum; + unsigned char QueryNumRpy; + unsigned char QueryTimeOut; + unsigned char RdyToShowTick; + unsigned char TotalProgress; + unsigned char HasDone; + unsigned char ResetHasSend; + unsigned char IsTimeOutReturn; + unsigned char PortNumOnGoing; + + int WastTimeSec; + + unsigned int fAddr; + unsigned char FlashPageData[256]; + + int IsDevRegisting; + + struct{ + unsigned char CtlNum; + unsigned char RegWhat; + unsigned char TryStart; + unsigned char ProgressVal; + unsigned char PortCount; + unsigned char HasDone; + unsigned char SlaveState; + unsigned char ProgressHasUpdate; + unsigned char PortCountHasUpdate; + unsigned char EpCountHasUpdate; + unsigned char HadTransited2Master; + unsigned char MasterShowDetailTick; + unsigned char StartSeqIdf; + unsigned char Wait4SendFinishedTick; + unsigned char MasterHasRecCount; + unsigned char Completed; + unsigned char ReSendEpCountTick; + + void Reset(){ + CtlNum =0; + RegWhat =0; + TryStart =0; + ProgressVal =0; + PortCount =0; + HasDone =0; + SlaveState =0; + ProgressHasUpdate =0; + PortCountHasUpdate =0; + EpCountHasUpdate =0; + HadTransited2Master =0; + MasterShowDetailTick =0; + StartSeqIdf = 0; + Wait4SendFinishedTick = 0; + MasterHasRecCount =0; + Completed =0; + ReSendEpCountTick = 0; + } + }Nw; + struct{ + unsigned char Exist[4]; + }Psv; + public: + TRegister(){ + IsOnShow = 0; + IsOnGo = 0; + }; + void Init(); + void RenderBackGround(void); + + void DrawSelf(void); + void DrawCommonByExReturn(); + void Show(); + void FullRedraw(int Prm); + void ShowPortCount(); + void ShowDetail(int aForce =0); + + static void sDelayMs(unsigned int aMs); + + void DrawProgressAll(); + void DrawProgress100(); + void DrawDoneAll(); + void DrawFixText(); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + void ClearSelected(void); + void Check4Selected(); + void InitDataBuf(); + void GetEpDevCount(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearProgressVal(); + void ClearCircuitTranmiteData(unsigned char aCc); + void SendCmdAll(); + void SendCmdOne(unsigned char aCc); + void SendCmdQuery(unsigned char aCc); + void SendCmdAbort(); + + void PushRegisterData(unsigned char aCc, unsigned char aInx); + void KeyPadUartPushData(unsigned char aCmd, unsigned char *pData); + + void iePushOneMsgReport(TRecordCommon aIm, unsigned char aCmd); + + + + unsigned char GetItemsCount(unsigned char aCc); + int CheckIsDone(); + void LoadToMainCtl(); + void SaveToFlash(); + + int Task1000Ms(); + + + void Show4Slave(); + + void MasterStartByRemote(unsigned char aCtlNum, unsigned char aPath); + void MasterCanNetGetPortCount(unsigned char aCnt); + void MasterCanNetGetProgressVal(unsigned char aVal); + void MasterCanNetGetEpCount(unsigned char aDType, unsigned char LowByte, unsigned char HiByte); + void MasterCanNetGetEpCountFinished(); + void MasterCanNetSendStartSeq(unsigned char aCtlNum, unsigned char aPath); + void MasterCanNetGetStartState(); + + void MasterCanNetShowTryStart(); + void MasterCanNetShowStart(); + void MasterCanNetShowProgress(); + void MasterCanNetShowItems(); + + void MasterSendCmdReqEpCount(); + void MasterSendCmdEpCountCorrect(); + + void SlaveReplyEpCountTransmited(); + void SlaveRpyEpCount(); + + unsigned char SlaveGetStartSeq(unsigned char *pData); + void SlaveRegInit(unsigned char aPath); + void SlaveReplyProgress(unsigned char aProg); + void SlaveReplyPortCount( unsigned char aCnt); + void SlaveReplyEpCount(unsigned char aDType, unsigned short aCnt); + void SlaveReplyAllEpCount(); + void SlaveReplyStartState(unsigned char aSta); + void SlaveModeTask1000Ms(); + int SlaveCheckIsDone(); + + int CompCount(); + void SlaveRecMasterGotCompleted(); + + static void sWriteOnePort(unsigned char aPort); + static void sWritePortList(); + + int ExtRequst(unsigned char Prm); +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/RegisterAdd.cpp b/MyCode/Gui/RegisterAdd.cpp new file mode 100644 index 0000000..bd78a6f --- /dev/null +++ b/MyCode/Gui/RegisterAdd.cpp @@ -0,0 +1,901 @@ +#include "ReGisterAdd.h" +#include "MainCtl.h" + +#define nrdNoneColor clMedGray + + +#define TextTopOffSet 6 +#define ListLineCnt 10 + + +static const char *StrWaitForReply = "等待接收到新数据"; +static const char *StrGotNewReg = "已接收一个注册包"; + +void TRegisterAdd::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right-20, Bottom); + VScrollBarBox.Set(Right-20 +1, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + ActiveLineNum=0; + + ListView.ColHeight = 33; + ListView.TopIndex=0; + ListView.RowCount = 9; + ListView.FixColTop = Content.Top; + ListView.FixColBottom = ListView.FixColTop + ListView.ColHeight; + ListView.ColTop[0] = ListView.FixColBottom + 1; + ListView.ColBottom[0] = ListView.ColTop[0] + ListView.ColHeight -1; + ListView.ColLeft[0] = 1; + ListView.ColRight[0] = ListView.ColWidth[0] +1; + for(i=1; i<12; i++){ + ListView.ColTop[i] = ListView.ColTop[i -1] + ListView.ColHeight; + ListView.ColBottom[i] = ListView.ColBottom[i-1] + ListView.ColHeight; + } + for(i=1;i Content.Bottom)y2 = Content.Bottom; + if(x == ListView.SelectedCol){ + RectFillRender(Content.Left, y, Content.Right, y2, SelectedColor); + }else{ + if(x & 1){ + RectFillRender(Content.Left, y, Content.Right, y2, OddColor); + }else{ + RectFillRender(Content.Left, y, Content.Right, y2, Color); + } + } + y = y2 + 1; + if(y>Content.Bottom)break; + } +} + +void TRegisterAdd::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TRegisterAdd::DrawCaption(void) +{ + Caption.Show(); +} + +void TRegisterAdd::DrawVertScrollBar(void) +{ + TVScrollBar::sDrawBySize(VScrollBarBox.Left, VScrollBarBox.Top, + VScrollBarBox.Width, VScrollBarBox.Height, + VScrollBar.RibbonColor, VScrollBar.Color, + 10, 10, ListView.TopIndex); +} + +void TRegisterAdd::DrawBtn(unsigned int x, unsigned int y, unsigned int x2, unsigned int y2, unsigned int aClr) +{ + RectFillRender(x, y, x2, y2, aClr); + + VertLineRender(x, y, y2-y+1-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y +1, y2-y+1-2, 0xFF808080); + VertLineRender(x2, y, y2-y+1-2, 0xFF404040); + + HorizLineRender(x, y, x2-x+1-1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, x2-x+1 - 2, 0xFF808080); + HorizLineRender(x, y2, x2-x+1, 0xFF404040); +} + +void TRegisterAdd::DrawCtlItem() +{ + unsigned int x, y, x2, y2, aClr, aClrText; + + TMyString::sFromStr("注册设备-本机", Caption.Text); + DrawCaption(); + + Content.SetWidth(Bound.Width -7); + RenderBackGround(clMoneyGreen); + + x =100; y =100; x2 =420; y2 = y+36; //0 + if(CtlIndex == 0){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+30,y+6, aClrText, "读取显示本机原注册信息"); + + x =100; y =160; x2 =420; y2 = y+36; //1 + if(CtlIndex == 1){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+30,y+6, aClrText, "开始追加注册"); + + x =100; y =220; x2 =420; y2 = y+36; //2 + if(CtlIndex == 2){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + if(NewRegCompleted) + TextRender_string24(x+30,y+6, aClrText, "显示新注册概览"); + else + TextRender_string24(x+30,y+6, clSilver, "显示新注册概览"); + + x =100; y =280; x2 =420; y2 = y+36; //3 + if(CtlIndex == 3){aClr = clRed; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + if(NewRegCompleted) + TextRender_string24(x+30,y+6, aClrText, "保存到本机 !"); + else + TextRender_string24(x+30,y+6, clSilver, "保存到本机 !"); + + x =100; y =340; x2 =420; y2 = y+36; //3 + if(CtlIndex == 4){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+30,y+6, aClrText, "停止注册并退出"); +} + +void TRegisterAdd::DrawList(void) +{ + int i, index, BGClr, TextClr, aTop; + unsigned int aClr; + //if(EntryCount < 1)return; + + RenderContent(); + aTop = ListView.FixColTop + TextTopOffSet; + + SetListColWidth(30,90,100,130,100,100,1,1,1); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, " 序号" ); + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, " 路径"); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, "设备类型"); + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "棣属于"); + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, "棣属于"); + + for(i=0; iCountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountAllDevice); + + aTop = ListView.ColTop[1] + TextTopOffSet; + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountRootDev); + + aTop = ListView.ColTop[2] + TextTopOffSet; + if(aP->CountRootDev)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountPort); + + aTop = ListView.ColTop[3] + TextTopOffSet; + if(aP->CountHandCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtl); + + aTop = ListView.ColTop[4] + TextTopOffSet; + if(aP->CountDirectCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtl); + + aTop = ListView.ColTop[5] + TextTopOffSet; + if(aP->CountMotherBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountMotherBoard); + + aTop = ListView.ColTop[6] + TextTopOffSet; + if(aP->CountCommBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountCommBoard); + + aTop = ListView.ColTop[7] + TextTopOffSet; + if(aP->CountEpAll)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountEpAll); + + aTop = ListView.ColTop[8] + TextTopOffSet; + if(aP->CountHandCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtlPad); + + aTop = ListView.ColTop[9] + TextTopOffSet; + if(aP->CountDirectCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtlPad); + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + + aTop = ListView.ColTop[0] + TextTopOffSet; + if(aP->CountEp.Smoker)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Smoker); + + aTop = ListView.ColTop[1] + TextTopOffSet; + if(aP->CountEp.Tempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Tempe); + + aTop = ListView.ColTop[2] + TextTopOffSet; + if(aP->CountEp.SmokeTempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.SmokeTempe); + + aTop = ListView.ColTop[3] + TextTopOffSet; + if(aP->CountEp.HandReport)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.HandReport); + + aTop = ListView.ColTop[4] + TextTopOffSet; + if(aP->CountEp.Input)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Input); + + aTop = ListView.ColTop[5] + TextTopOffSet; + if(aP->CountEp.Output)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Output); + + aTop = ListView.ColTop[6] + TextTopOffSet; + if(aP->CountEp.InOut)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.InOut); + + aTop = ListView.ColTop[7] + TextTopOffSet; + if(aP->CountEp.VaAlram)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.VaAlram); + + aTop = ListView.ColTop[8] + TextTopOffSet; + if(aP->CountEp.BusBroke)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.BusBroke); + + aTop = ListView.ColTop[9] + TextTopOffSet; + if(aP->CountEp.DisplayPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.DisplayPad); + + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + + aTop = ListView.ColTop[0] + TextTopOffSet; + if(aP->CountEp.UnDefine)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.UnDefine); + + aTop = ListView.ColTop[1] + TextTopOffSet; + if(aP->CountEp.Unknown)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.Unknown); +} + +void TRegisterAdd::DrawOverViewAllHost() +{ + TThisMainCtl *aP = &MainCtl; + if(aP == nullptr)return; +} + +void TRegisterAdd::DrawOverViewHost() +{ + int i; + unsigned int aTop, aClr; + TThisMainCtl *aP = &MainCtl; + //Line0,ALl + //Line1,CountRootDev + //Line2,CountPort + //Line3,CountHandCtl + //Line4,CountDirectCtl + //Line5,CountMotherBoard + //Line6,CountCommBoard + //Line7,CountEpAll + //Line8,CountHandCtlPad + //Line9,CountDirectCtlPad + if(aP == nullptr)return; + + Content.SetWidth(Bound.Width -7); + RenderBackGround(clMoneyGreen); + + TMyString::sFromStr("注册信息详情", Caption.Text); + DrawCaption(); + + SetListColWidth(120,160,130,150,120,120,1,1,1); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, " 条目" ); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, "总数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "所有设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountAllDevice); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "根设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountRootDev); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路" ); + if(aP->CountRootDev)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountPort); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘" ); + if(aP->CountHandCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtl); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘" ); + if(aP->CountDirectCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtl); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路母板" ); + if(aP->CountMotherBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountMotherBoard); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "通讯板" ); + if(aP->CountCommBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountCommBoard); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "终端设备" ); + if(aP->CountEpAll)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountEpAll); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘按钮" ); + if(aP->CountHandCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtlPad); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘按钮" ); + if(aP->CountDirectCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtlPad); + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型烟感" ); + if(aP->CountEp.Smoker)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Smoker); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型温感" ); + if(aP->CountEp.Tempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Tempe); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "烟温一体" ); + if(aP->CountEp.SmokeTempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.SmokeTempe); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "手报" ); + if(aP->CountEp.HandReport)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.HandReport); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入模块" ); + if(aP->CountEp.Input)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Input); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输出模块" ); + if(aP->CountEp.Output)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Output); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入输出模块" ); + if(aP->CountEp.InOut)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.InOut); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "声光报警" ); + if(aP->CountEp.VaAlram)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.VaAlram); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "断路器" ); + if(aP->CountEp.BusBroke)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.BusBroke); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "显示盘" ); + if(aP->CountEp.DisplayPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.DisplayPad); + + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未定义设备" ); + if(aP->CountEp.UnDefine)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.UnDefine); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未知设备" ); + if(aP->CountEp.Unknown)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.Unknown); +} + +void TRegisterAdd::DrawOverViewReg() +{ + int i; + unsigned int aTop, aClr; + TThisMainCtl *aP = &MainCtlReg; + //Line0,ALl + //Line1,CountRootDev + //Line2,CountPort + //Line3,CountHandCtl + //Line4,CountDirectCtl + //Line5,CountMotherBoard + //Line6,CountCommBoard + //Line7,CountEpAll + //Line8,CountHandCtlPad + //Line9,CountDirectCtlPad + if(aP == nullptr)return; + + Content.SetWidth(Bound.Width -7); + RenderBackGround(clMoneyGreen); + + TMyString::sFromStr("注册信息详情", Caption.Text); + DrawCaption(); + + SetListColWidth(120,160,130,150,120,120,1,1,1); + + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, " 条目" ); + TextRender_string24(ListView.ColLeft[1],aTop,TextColor, "总数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "所有设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountAllDevice); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "根设备" ); + if(aP->CountAllDevice)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountRootDev); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路" ); + if(aP->CountRootDev)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountPort); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘" ); + if(aP->CountHandCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtl); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘" ); + if(aP->CountDirectCtl)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtl); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "回路母板" ); + if(aP->CountMotherBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountMotherBoard); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "通讯板" ); + if(aP->CountCommBoard)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountCommBoard); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "终端设备" ); + if(aP->CountEpAll)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountEpAll); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "总线盘按钮" ); + if(aP->CountHandCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountHandCtlPad); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[0],aTop,TextColor, "直控盘按钮" ); + if(aP->CountDirectCtlPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[1], aTop, aClr, aP->CountDirectCtlPad); + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[3],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型烟感" ); + if(aP->CountEp.Smoker)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Smoker); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "点型温感" ); + if(aP->CountEp.Tempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Tempe); + + aTop = ListView.ColTop[2] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "烟温一体" ); + if(aP->CountEp.SmokeTempe)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.SmokeTempe); + + aTop = ListView.ColTop[3] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "手报" ); + if(aP->CountEp.HandReport)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.HandReport); + + aTop = ListView.ColTop[4] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入模块" ); + if(aP->CountEp.Input)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Input); + + aTop = ListView.ColTop[5] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输出模块" ); + if(aP->CountEp.Output)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.Output); + + aTop = ListView.ColTop[6] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "输入输出模块" ); + if(aP->CountEp.InOut)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.InOut); + + aTop = ListView.ColTop[7] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "声光报警" ); + if(aP->CountEp.VaAlram)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.VaAlram); + + aTop = ListView.ColTop[8] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "断路器" ); + if(aP->CountEp.BusBroke)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.BusBroke); + + aTop = ListView.ColTop[9] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[2],aTop,TextColor, "显示盘" ); + if(aP->CountEp.DisplayPad)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[3], aTop, aClr, aP->CountEp.DisplayPad); + + //___________________________________________________________________ + aTop = ListView.FixColTop + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "条目"); + TextRender_string24(ListView.ColLeft[5],aTop,TextColor, " 数量 |"); + + aTop = ListView.ColTop[0] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未定义设备" ); + if(aP->CountEp.UnDefine)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.UnDefine); + + aTop = ListView.ColTop[1] + TextTopOffSet; + TextRender_string24(ListView.ColLeft[4],aTop,TextColor, "未知设备" ); + if(aP->CountEp.Unknown)aClr = clBlack; else aClr =nrdNoneColor; + TextDigitRender6Right24(ListView.ColLeft[5], aTop, aClr, aP->CountEp.Unknown); +} + + +TGuiMsgReturn TRegisterAdd::KeyIn(unsigned char aKey) +{ + int ind,i,aIndex; + TGuiMsgReturn aMsg = guiMsgNone; + //Up or Down One Index___________________ + + if(aKey == VK_TAB){ + + } + if(1){ + if(VK_UP == aKey){ + if(State == nrCtl){ + if(CtlIndex >0){ + CtlIndex--; + if( (CtlIndex == 2) || (CtlIndex == 3) ){ + CtlIndex =1; + } + DrawCtlItem(); + } + } + if(ListView.SelectedCol >0){ + + }else{ + if(ListView.TopIndex >0){ + ReDraw(); + } + } + }else + if(VK_DOWN == aKey){ + if(State == nrCtl){ + if(CtlIndex < 4){ + CtlIndex++; + if( (CtlIndex == 2) || (CtlIndex == 3) ){ + CtlIndex =4; + } + DrawCtlItem(); + } + } + if( ListView.SelectedCol < (ListLineCnt -1) ){ + + }else{ + + } + } + } + + if(aKey == VK_EXECUTE){ + //Open path Device + if(State == nrCtl){ + if(CtlIndex ==0){ + MainCtl.LoadVisioInf(); + DrawOverViewHost(); + State = nrShowDetails; + }else + if(CtlIndex ==1){ + NewRegCompleted = 0; + }else + if(CtlIndex ==2){ + if(NewRegCompleted){ + MainCtlReg.LoadVisioInf(); + DrawOverViewReg(); + State = nrShowDetails; + } + }else + if(CtlIndex ==3){ + if(NewRegCompleted){ + + } + }else + if(CtlIndex ==4){ + //do something before return + aMsg = guiMsgReturn; + } + }else + if(State == nrShowDetails){ + State = nrCtl; + DrawCtlItem(); + } + }else + if(aKey == VK_F2){ + + }else + if(aKey == VK_RETURN){ + if(State == nrShowDetails){ + State = nrCtl; + DrawCtlItem(); + } + } + + return aMsg; +} + diff --git a/MyCode/Gui/RegisterAdd.h b/MyCode/Gui/RegisterAdd.h new file mode 100644 index 0000000..234b605 --- /dev/null +++ b/MyCode/Gui/RegisterAdd.h @@ -0,0 +1,124 @@ +#ifndef REGISTERADD_H_ +#define REGISTERADD_H_ + + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "StaticText.h" +#include "Device.h" +#include "EpDevice.h" + +#define arCtl 0 +#define arShowDetails 1 + +class TRegisterAdd{ + public: + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + struct{ + int TopIndex; + int SelectedCol; + unsigned short RowCount; + unsigned short ColTop[12]; + unsigned short ColBottom[12]; + unsigned short ColHeight; + unsigned short ColWidth[12]; + unsigned short ColLeft[12]; + unsigned short ColRight[12]; + unsigned short FixColTop; + unsigned short FixColBottom; + }ListView; + public: + TStaticText Caption; + int ActiveLineNum; + int LineCount; + int LineHeight; + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + int SelectedIndex; + + TMyString Str; + + unsigned char State; + unsigned char CtlIndex; + unsigned char NewRegCompleted; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TRegisterAdd(){}; + TRegisterAdd(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawVertScrollBar(void); + void DrawList(void); + void Show(void); + void ReDraw(void); + void DrawCaption(void); + void RenderContent(void); + + void DrawBtn(unsigned int x, unsigned int y, unsigned int x2, unsigned int y2, unsigned int aClr); + void DrawCtlItem(void); + void ShowCtl(void); + void DrawOverViewName(void); + + void DrawOverViewCountHost(void); + void DrawOverViewAllHost(void); + void DrawOverViewHost(void); + + void DrawOverViewReg(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void Read(); + void Clear(); + void Save(void); + void Search(void); + + void ShowAllInf(); + + void FullRePaint(void); + void RePaint(void); + + +}; + + + + + + + + + +#endif + + diff --git a/MyCode/Gui/RegisterAddRemove.cpp b/MyCode/Gui/RegisterAddRemove.cpp new file mode 100644 index 0000000..15e807e --- /dev/null +++ b/MyCode/Gui/RegisterAddRemove.cpp @@ -0,0 +1,1287 @@ +#include "RegisterAddRemove.h" +#include "RuntimeData2.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +void TRegisterAddRemove::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left, Top, Width, CH, 0, 0, clWhite, clMaroon); + SText.Init (319, Top, 480, CH, 0, 0, clWhite, clMaroon); + + Content0.Set(Left, Top+CH, Left + ipdWidth0 -1, Bottom); + Left = Left + ipdWidth0 ; + Content1.Set(Left, Top+CH, Right, Bottom); + + VScrollBarBox.Set(Right -20 +1, Top + CH, Right, Bottom); + Color = aColor; + #undef CH + + ActiveLineNum=0; + + ListView.ColHeight = 33; + ListView.RowCount = 9; + ListView.FixColTop = Content0.Top; + ListView.FixColBottom = ListView.FixColTop + ListView.ColHeight; + ListView.ColTop[0] = ListView.FixColBottom + 1; + ListView.ColBottom[0] = ListView.ColTop[0] + ListView.ColHeight -1; + ListView.ColLeft[0] = 1; + ListView.ColRight[0] = ListView.ColWidth[0] +1; + for(i=1; i<12; i++){ + ListView.ColTop[i] = ListView.ColTop[i -1] + ListView.ColHeight; + ListView.ColBottom[i] = ListView.ColBottom[i-1] + ListView.ColHeight; + } + for(i=1;iEdit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 1){ + //Edit 0 key + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 1; + aPanel->Edit[3].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 2){ + //Edit 0 key + aPanel->Edit[0].Selected = 1; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 3){ + //Edit 0 key + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 1; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 4){ + //Edit 0 key + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 1; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 5){ + //Edit 0 key + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 0; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + } + } +} + +void TRegisterAddRemove::Check4SelectedRemove(void) +{ + if(IsSelecting ==0){ + if(CtlIndex){ + //User Code Mode + if(Level0.SelectedIndex == 0){ + //Edit 0 key + aPanel->Edit[0].Selected = 1; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 1){ + aPanel->Edit[0].Selected = 0; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 2){ + aPanel->Edit[0].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 1; + } + }else{ + //Addr Mode + if(Level0.SelectedIndex == 0){ + //Edit 0 key + aPanel->Edit[0].Selected = 1; + aPanel->Edit[1].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 1){ + //Edit 0 key + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 1; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 2){ + //Edit 0 key + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + }else + if(Level0.SelectedIndex == 3){ + //Edit 0 key + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + } + } + } +} + + + + +void TRegisterAddRemove::DrawBtn(unsigned int x, unsigned int y, unsigned int x2, unsigned int y2, unsigned int aClr) +{ + RectFillRender(x, y, x2, y2, aClr); + + VertLineRender(x, y, y2-y+1-1, 0xFFFFFFFF); + VertLineRender(x2 -1, y +1, y2-y+1-2, 0xFF808080); + VertLineRender(x2, y, y2-y+1-2, 0xFF404040); + + HorizLineRender(x, y, x2-x+1-1, 0xFFFFFFFF); + HorizLineRender(x +1, y2 -1, x2-x+1 - 2, 0xFF808080); + HorizLineRender(x, y2, x2-x+1, 0xFF404040); +} + + +void TRegisterAddRemove::DrawCtlItemRemove() +{ + unsigned int x, y, x2, y2, aClr, aClrText; + + RenderBackGround(clMoneyGreen); + + x =100; y =100; x2 =380; y2 = y+36; //0 + if(CtlIndex == 0){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+10,y+6, aClrText, "根据地址号删除设备"); + + x =100; y =160; x2 =380; y2 = y+36; //1 + if(CtlIndex == 1){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+10,y+6, aClrText, "根据用户码删除设备"); +} + +void TRegisterAddRemove::ShowItemDetailRemove() +{ + unsigned int aP0, aP1, Found; + Found =0; + RenderContent0(0xFF000000); + + Selected.iType = 0; + Selected.Path0 = 0; + Selected.Path1 = 0; + Selected.Path2 = 0; + Selected.Ava = 0; + + TextRender_string24 ( 136, 130, clNearBlack, "类型"); + TextRender_string24 ( 136, 170, clNearBlack, "回路"); + TextRender_string24 ( 136, 210, clNearBlack, "地址"); + TextRender_string24 ( 136, 250, clNearBlack, "用户码"); + TextRender_string24 ( 6, 296, clNearBlack, "描述:"); + + if(CtlIndex){ + //User Code Mode + aP0 = aPanel->Edit[0].Str.ToInteger(); + if( (aP0 >0) && (aP0 < 1000000) ){ + + } + }else{ + //Addr Mode + aP0 = aPanel->Edit[0].Str.ToInteger(); + aP1 = aPanel->Edit[1].Str.ToInteger(); + if( (aP0 >0) && (aP0 < 41) ){ + if( (aP1 >0) && (aP1 < 256) ){ + aP0--; + aP1--; + if(MainCtl.fData.Split.ExistTablePort[aP0] == 0xA5){ + if(Port[aP0].ExistTable[aP1] == 0xA5){ + Found = 1; + + } + } + } + } + } + + if(Found){ + TMyString::sFromStr("注册设备已找到", aPanel->Caption.Text); + Selected.Ava = 1; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 1; + + TextRender_string24 ( 220, 130, clNearBlack, StrType[EpDev[aP0][aP1].fData.Split.dType]); + TextDigitRender2Right24 ( 284, 170, clNearBlack, aP0 +1); + TextDigitRender3Right24 ( 272, 210, clNearBlack, aP1 +1); + TextDigitRender6Right24 ( 236, 250, clNearBlack, EpDev[aP0][aP1].fData.Split.UserCode); + aPanel->Edit[3].Str.FromStr("未定义描述字"); + aPanel->Edit[3].Show(); + + }else{ + TMyString::sFromStr("未找到设备", aPanel->Caption.Text); + Selected.Ava = 0; + aPanel->Btn[0].Enable = 0; + aPanel->Btn[1].Enable = 0; + + TextRender_string24 ( 220, 130, clFrmFace, clFrmFace, " "); + TextRender_string24 ( 284, 170, clFrmFace, clFrmFace, " "); + TextRender_string24 ( 272, 210, clFrmFace, clFrmFace, " "); + TextRender_string24 ( 236, 250, clFrmFace, clFrmFace, " "); + aPanel->Edit[3].Str.Clear(); + aPanel->Edit[3].Show(); + } +} + +void TRegisterAddRemove::InitPanel4Remove(void) +{ + int x,y,x2,y2, aW,aH; + x = 420; + y = 140; + x2 = 680; + y2 = 325; + aW = x2 - x +1; + aH = y2 - y +1; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("未选定设备", aPanel->Caption.Text); + + aPanel->SText[0].Init(16,46,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(16,82,60,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("回路", aPanel->SText[0].Text); + TMyString::sFromStr("地址", aPanel->SText[1].Text); + + aPanel->Edit[0].Init(120,46,60,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(120,82,60,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[1].SetMaxLen(3); + aPanel->Edit[0].SetInputMaskEn(); + aPanel->Edit[1].SetInputMaskEn(); + aPanel->Edit[0].Str.FromStr("01"); + aPanel->Edit[1].Str.FromStr("001"); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[1].Pst = 2; + + aPanel->Btn[0].Init(68,130,120,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("确认删除"); + aPanel->Btn[1].Init(68,180,120,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Caption.FromStr("取消"); + + aPanel->Caption.Visible = 1; + aPanel->SText[0].Visible = 1; + aPanel->SText[1].Visible = 1; + aPanel->Edit[0].Visible = 1; + aPanel->Edit[1].Visible = 1; + aPanel->Btn[0].Visible = 1; + aPanel->Btn[1].Visible = 0; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 1; + aPanel->Btn[0].SetCaptionLeftSpacing(8); + aPanel->Btn[1].SetCaptionLeftSpacing(28); + + aPanel->Btn[0].SelectedColor = clRed; + aPanel->Btn[0].SelectedTextColor = clNearWhite; + + aPanel->Edit[3].Init(6,330,394,32,0,0,clNearBlack,clNearWhite); + aPanel->Edit[3].SetMaxLen(32); + aPanel->Edit[3].Str.FromStr("未定义描述字"); + aPanel->Edit[3].Pst = 13; + aPanel->Edit[3].Visible = 1; + + ShowItemDetailRemove(); + aPanel->Show(); + + TextRender_string24 ( 136, 130, clNearBlack, "类型"); + TextRender_string24 ( 136, 170, clNearBlack, "回路"); + TextRender_string24 ( 136, 210, clNearBlack, "地址"); + TextRender_string24 ( 136, 250, clNearBlack, "用户码"); + TextRender_string24 ( 6, 296, clNearBlack, "描述:"); +} + + +void TRegisterAddRemove::InitPanel4RemoveViaUserCode(void) +{ + int x,y,x2,y2, aW,aH; + x = 420; + y = 140; + x2 = 680; + y2 = 325; + aW = x2 - x +1; + aH = y2 - y +1; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("未选定设备", aPanel->Caption.Text); + + aPanel->SText[0].Init(16,46,60,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("用户码", aPanel->SText[0].Text); + + aPanel->Edit[0].Init(120,46,120,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[0].SetMaxLen(6); + aPanel->Edit[0].SetInputMaskEn(); + aPanel->Edit[0].Str.FromStr("000001"); + aPanel->Edit[0].Pst = 5; + + aPanel->Btn[0].Init(68,130,120,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("确认删除"); + aPanel->Btn[1].Init(68,180,120,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Caption.FromStr("取消"); + + aPanel->Caption.Visible = 1; + aPanel->SText[0].Visible = 1; + aPanel->Edit[0].Visible = 1; + aPanel->Btn[0].Visible = 1; + aPanel->Btn[1].Visible = 0; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 0; + aPanel->Btn[0].SetCaptionLeftSpacing(8); + aPanel->Btn[1].SetCaptionLeftSpacing(28); + + + aPanel->Btn[0].SelectedColor = clRed; + aPanel->Btn[0].SelectedTextColor = clNearWhite; + + ShowItemDetailRemove(); + aPanel->Show(); + +} + +void TRegisterAddRemove::DrawCtlItemAdd() +{ + unsigned int x, y, x2, y2, aClr, aClrText; + + TMyString::sFromStr("手动添加消防设备-本机", Caption.Text); + Caption.Show(); + + RenderBackGround(clMoneyGreen); + + x =100; y =100; x2 =380; y2 = y+36; //0 + if(CtlIndex == 0){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+10,y+6, aClrText, "退出手动添加设备"); + + x =100; y =160; x2 =380; y2 = y+36; //1 + if(CtlIndex == 1){aClr = clNavy; aClrText =clNearWhite;} + else{aClr = clFrmFace; aClrText =clNearBlack;} + DrawBtn(x,y,x2,y2,aClr); + TextRender_string24(x+10,y+6, aClrText, "开始手动添加消防设备"); +} + +void TRegisterAddRemove::InitPanel4Add(void) +{ + int x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = 420; + y = 100; + x2 = 680; + y2 = 370; + aW = x2 - x +1; + aH = y2 - y +1; + + if(aPanel == nullptr)return; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearBlack,clFrmFace); + + if(AddTargetLevel == 0){ + TMyString::sFromStr("添加根设备", aPanel->Caption.Text); + }else + if(AddTargetLevel == 1){ + TMyString::sFromStr("添加终端设备", aPanel->Caption.Text); + } + + aPanel->SText[0].Init(16,128,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(16,168,60,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("回路", aPanel->SText[0].Text); + TMyString::sFromStr("地址", aPanel->SText[1].Text); + + aPanel->Edit[0].Init(120,128,60,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(120,168,60,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[1].SetMaxLen(3); + aPanel->Edit[0].SetInputMaskEn(); + aPanel->Edit[1].SetInputMaskEn(); + aPanel->Edit[0].Str.FromStr("0"); + aPanel->Edit[1].Str.FromStr("00"); + aPanel->Edit[0].Pst = 0; + aPanel->Edit[1].Pst = 1; + + aPanel->Btn[0].Init(68,218,120,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("确认添加"); + aPanel->Btn[1].Init(68,258,120,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Caption.FromStr("取消"); + + aPanel->Caption.Visible = 1; + aPanel->SText[0].Visible = 1; + aPanel->SText[1].Visible = 1; + aPanel->Edit[0].Visible = 1; + aPanel->Edit[1].Visible = 1; + aPanel->Btn[0].Visible = 1; + aPanel->Btn[1].Visible = 0; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 0; + aPanel->Btn[0].SetCaptionLeftSpacing(8); + aPanel->Btn[1].SetCaptionLeftSpacing(8); + + aPanel->Edit[2].Init(120,88,60,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[2].SetMaxLen(2); + aPanel->Edit[2].SetInputMaskEn(); + aPanel->Edit[2].Str.FromStr("00"); + aPanel->Edit[2].Pst = 1; + aPanel->Edit[2].Visible = 1; + + aPanel->Edit[3].Init(6,330,394,32,0,0,clNearBlack,clNearWhite); + aPanel->Edit[3].SetMaxLen(32); + aPanel->Edit[3].Str.FromStr("在此输入描述字"); + aPanel->Edit[3].Pst = 13; + aPanel->Edit[3].Visible = 1; + + + aPanel->Btn[0].SelectedColor = clRed; + aPanel->Btn[0].SelectedTextColor = clNearWhite; + + ShowItemDetailAdd(); + aPanel->Show(); + + TextRender_string24(436, 148, clNearBlack, clFrmFace, "设备层"); + TextRender_string24(436, 188, clNearBlack, clFrmFace, "类型号"); + if(Level0.SelectedIndex == 0){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + if(AddTargetLevel == 0){ + TextRender_string24(540, 154, aClr, bClr, "<板卡>"); + }else + if(AddTargetLevel == 1){ + TextRender_string24(540, 154, aClr, bClr, "<终端>"); + } +} + + +void TRegisterAddRemove::ShowItemDetailAdd() +{ + unsigned int aP0, aP1, Found; + unsigned int aClr, bClr, aType; + Found =0; + RenderContent0(0xFF000000); + + Selected.iType = 0; + Selected.Path0 = 0; + Selected.Path1 = 0; + Selected.Path2 = 0; + Selected.Ava = 0; + + if(1){ + //Addr Mode + aP0 = aPanel->Edit[0].Str.ToInteger(); + aP1 = aPanel->Edit[1].Str.ToInteger(); + aType = aPanel->Edit[2].Str.ToInteger(); + } + + if(Level0.SelectedIndex == 0){ + aClr = clNearWhite; + bClr = clBlue; + }else{ + aClr = clNearBlack; + bClr = clFrmFace; + } + + if(aType < 16){ + AddTargetType = aType; + }else{ + AddTargetType = 0; + } + if(AddTargetLevel == 0){ + TMyString::sFromStr("添加根设备", aPanel->Caption.Text); + TextRender_string24(540, 154, aClr, bClr, "<板卡>"); + + if(AddTargetType < 16){ + TextRender_string24 ( 136, 130, clNearBlack, "类型"); + TextRender_string24 ( 230, 130, clNearBlack, StrRootType[AddTargetType]); + + TextRender_string24 ( 136, 170, clNearBlack, "序号"); + TextDigitRender2Right24 ( 284, 170, clNearBlack, aP0 +1); + + TextRender_string24 ( 136, 210, clNearBlack, "根路径"); + TextDigitRender3Right24 ( 272, 210, clNearBlack, aP1 +1); + + TextRender_string24 ( 136, 290, clNearBlack, "描述:"); + TextRender_string24 ( 220, 290, clNearBlack, "请在以下定义"); + } + }else + if(AddTargetLevel == 1){ + TMyString::sFromStr("添加终端设备", aPanel->Caption.Text); + TextRender_string24(540, 154, aClr, bClr, "<终端>"); + + TextRender_string24 ( 136, 130, clNearBlack, "类型"); + TextRender_string24 ( 230, 130, clNearBlack, StrType[AddTargetType]); + + TextRender_string24 ( 136, 170, clNearBlack, "回路"); + TextDigitRender2Right24 ( 284, 170, clNearBlack, aP0 +1); + + TextRender_string24 ( 136, 210, clNearBlack, "地址"); + TextDigitRender3Right24 ( 272, 210, clNearBlack, aP1 +1); + + TextRender_string24 ( 136, 290, clNearBlack, "描述:"); + TextRender_string24 ( 220, 290, clNearBlack, "请在以下定义"); + } + + aPanel->Btn[0].Enable = 1; +} + + +//_____________________________________________________________________________________________________________________________ + + +TGuiMsgReturn TRegisterAddRemove::KeyInAddStart(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + TDMix aFullPath; + unsigned char aType; + Updata = 0; + + if(aKey == VK_UP){ + + }else + if(aKey == VK_DOWN){ + + } + if(aKey == VK_EXECUTE){ + //Save Here + IsSelecting = 0; + //Addr Mode + InitPanel4Add(); + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + if(Updata){ + ShowItemDetailAdd(); + } + + return aMsg; +} + + +TGuiMsgReturn TRegisterAddRemove::KeyInRemoveStart(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + TDMix aFullPath; + unsigned char aType; + Updata = 0; + + if(aKey == VK_LEFT){ + + }else + if(aKey == VK_RIGHT){ + + }else + if(aKey == VK_UP){ + + }else + if(aKey == VK_DOWN){ + + }else + if(aKey == VK_F1){ + + }else + if(aKey == VK_TAB){ + + } + if(aKey == VK_EXECUTE){ + IsSelecting = 0; + InitPanel4Remove(); + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + if(Updata){ + ShowItemDetailAdd(); + } + + return aMsg; +} + + + +TGuiMsgReturn TRegisterAddRemove::KeyInAdd(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + TDMix aFullPath; + unsigned char aType; + Updata = 0; + + Check4SelectedAdd(); + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) + ){ + if(1){ + //Addr Mode + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[2].Selected){ + aPanel->Edit[2].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[3].Selected){ + aPanel->Edit[3].KeyIn(aKey); + Updata = 1; + } + } + } + + if(aKey == VK_LEFT){ + if(IsSelecting){ + + }else{ + if(1){ + //Addr Mode + if(Level0.SelectedIndex == 0){ + if(AddTargetLevel){ + AddTargetLevel = 0; + }else{ + AddTargetLevel = 1; + } + Updata = 1; + } + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[2].Selected){ + aPanel->Edit[2].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[3].Selected){ + aPanel->Edit[3].KeyIn(aKey); + Updata = 1; + } + } + } + }else + if(aKey == VK_RIGHT){ + if(IsSelecting){ + + }else{ + if(1){ + //Addr Mode + if(Level0.SelectedIndex == 0){ + if(AddTargetLevel){ + AddTargetLevel = 0; + }else{ + AddTargetLevel = 1; + } + Updata = 1; + } + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[2].Selected){ + aPanel->Edit[2].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[3].Selected){ + aPanel->Edit[3].KeyIn(aKey); + Updata = 1; + } + } + } + }else + if(aKey == VK_UP){ + if(IsSelecting){ + if(CtlIndex >0){ + CtlIndex =0; + DrawCtlItemAdd(); + } + }else{ + if(1){ + //Addr Mode + if(Level0.SelectedIndex >0){ + Level0.SelectedIndex--; + Updata = 1; + } + } + } + }else + if(aKey == VK_DOWN){ + if(IsSelecting){ + if(CtlIndex ==0 ){ + CtlIndex =1; + DrawCtlItemAdd(); + } + }else{ + if(1){ + //Addr Mode + if(Level0.SelectedIndex <5){ + Level0.SelectedIndex++; + Updata = 1; + } + } + } + }else + if(aKey == VK_F1){ + //Go Modify + if(IsSelecting){ + + } + }else + if(aKey == VK_TAB){ + if(IsSelecting){ + //User Not Save Here + //if(1){ + //Addr Mode + // Level0.SelectedIndex ++; + // if(Level0.SelectedIndex >3){ + // Level0.SelectedIndex = 0; + // Updata = 1; + // } + //} + } + } + if(aKey == VK_EXECUTE){ + //Save Data Here + if(IsSelecting){ + //Save Here + IsSelecting = 0; + //Addr Mode + InitPanel4Add(); + }else{ + if(1){ + //Addr Mode + if(Level0.SelectedIndex == 4){ + //Mask Here + aFullPath.D8[0] = 0; + aFullPath.D8[1] = Selected.Path0; + aFullPath.D8[2] = Selected.Path1; + aFullPath.D8[3] = Selected.Path2; + Record.OperateAdd_Mask(aFullPath, Selected.iType); + } + } + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + Check4SelectedAdd(); + if(Updata){ + ShowItemDetailAdd(); + aPanel->ReDrawItems(); + } + + return aMsg; +} + + + +TGuiMsgReturn TRegisterAddRemove::KeyInRemove(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + TDMix aFullPath; + unsigned char aType; + Updata = 0; + + Check4SelectedRemove(); + + if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) + ){ + if(CtlIndex){ + //User Code Mode + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + }else{ + //Addr Mode + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + Updata = 1; + } + } + } + + if(aKey == VK_LEFT){ + if(IsSelecting){ + + }else{ + if(CtlIndex){ + //User Code Mode + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + }else{ + //Addr Mode + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + Updata = 1; + } + } + } + }else + if(aKey == VK_RIGHT){ + if(IsSelecting){ + + }else{ + if(CtlIndex){ + //User Code Mode + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + }else{ + //Addr Mode + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + Updata = 1; + } + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + Updata = 1; + } + } + } + }else + if(aKey == VK_UP){ + if(IsSelecting){ + if(CtlIndex >0){ + CtlIndex =0; + DrawCtlItemRemove(); + } + }else{ + if(CtlIndex){ + //User Code Mode + if(Level0.SelectedIndex >0){ + Level0.SelectedIndex--; + Updata = 1; + } + }else{ + //Addr Mode + if(Level0.SelectedIndex >0){ + Level0.SelectedIndex--; + Updata = 1; + } + } + } + }else + if(aKey == VK_DOWN){ + if(IsSelecting){ + if(CtlIndex ==0 ){ + CtlIndex =1; + DrawCtlItemRemove(); + } + }else{ + if(CtlIndex){ + //User Code Mode + if(Level0.SelectedIndex <2){ + if(Selected.Ava){ + Level0.SelectedIndex++; + Updata = 1; + } + } + }else{ + //Addr Mode + if(Level0.SelectedIndex <1){ + Level0.SelectedIndex++; + Updata = 1; + }else + if(Level0.SelectedIndex <2){ + if(Selected.Ava){ + Level0.SelectedIndex++; + Updata = 1; + } + } + } + } + }else + if(aKey == VK_F1){ + //Go Modify + if(IsSelecting){ + + } + }else + if(aKey == VK_TAB){ + if(IsSelecting){ + //User Not Save Here + if(CtlIndex){ + //User Code Mode + Level0.SelectedIndex ++; + if(Level0.SelectedIndex >2){ + Level0.SelectedIndex = 0; + Updata = 1; + } + }else{ + //Addr Mode + Level0.SelectedIndex ++; + if(Level0.SelectedIndex >3){ + Level0.SelectedIndex = 0; + Updata = 1; + } + } + } + } + if(aKey == VK_EXECUTE){ + //Save Data Here + if(IsSelecting){ + //Save Here + IsSelecting = 0; + if(CtlIndex){ + //User Code Mode + InitPanel4RemoveViaUserCode(); + }else{ + //Addr Mode + InitPanel4Remove(); + } + }else{ + if(CtlIndex){ + //User Code Mode + if(Level0.SelectedIndex == 1){ + //Mask Here + aFullPath.D8[0] = 0; + aFullPath.D8[1] = Selected.Path0; + aFullPath.D8[2] = Selected.Path1; + aFullPath.D8[3] = Selected.Path2; + Record.OperateAdd_Mask(aFullPath, Selected.iType); + }else + if(Level0.SelectedIndex == 2){ + //UnMask Here + aFullPath.D8[0] = 0; + aFullPath.D8[1] = Selected.Path0; + aFullPath.D8[2] = Selected.Path1; + aFullPath.D8[3] = Selected.Path2; + Record.OperateAdd_UnMask(aFullPath, Selected.iType); + } + }else{ + //Addr Mode + if(Level0.SelectedIndex == 2){ + //Mask Here + aFullPath.D8[0] = 0; + aFullPath.D8[1] = Selected.Path0; + aFullPath.D8[2] = Selected.Path1; + aFullPath.D8[3] = Selected.Path2; + Record.OperateAdd_Mask(aFullPath, Selected.iType); + }else + if(Level0.SelectedIndex == 3){ + //UnMask Here + aFullPath.D8[0] = 0; + aFullPath.D8[1] = Selected.Path0; + aFullPath.D8[2] = Selected.Path1; + aFullPath.D8[3] = Selected.Path2; + Record.OperateAdd_UnMask(aFullPath, Selected.iType); + } + } + } + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + Check4SelectedRemove(); + if(Updata){ + ShowItemDetailRemove(); + aPanel->ReDrawItems(); + } + + return aMsg; +} + + +TGuiMsgReturn TRegisterAddRemove::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + TDMix aFullPath; + unsigned char aType; + Updata = 0; + + unsigned char IsAdd; + unsigned char IsSelecting; + + if(IsAdd){ + if(IsSelecting){ + + }else{ + + } + }else{ + if(IsSelecting){ + + }else{ + + } + } + return aMsg; +} + + + + diff --git a/MyCode/Gui/RegisterAddRemove.h b/MyCode/Gui/RegisterAddRemove.h new file mode 100644 index 0000000..0da3267 --- /dev/null +++ b/MyCode/Gui/RegisterAddRemove.h @@ -0,0 +1,134 @@ +#ifndef REGISTERADDREMOVE_H_ +#define REGISTERADDREMOVE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TRegisterAddRemove{ + public: + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + struct{ + unsigned short RowCount; + unsigned short ColTop[12]; + unsigned short ColBottom[12]; + unsigned short ColHeight; + unsigned short ColWidth[12]; + unsigned short ColLeft[12]; + unsigned short ColRight[12]; + unsigned short FixColTop; + unsigned short FixColBottom; + }ListView; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + int ActiveLineNum; + int LineCount; + int LineHeight; + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + + TRect Content0; + TRect Content1; + + TMyString Str; + + unsigned char CtlIndex; + + unsigned char ParentType; + struct{ + unsigned int Ava; + unsigned char iType; + unsigned char Path0; + unsigned char Path1; + unsigned char Path2; + }Selected; + + struct{ + int TopIndex; + int SelectedCol; + int SelectedIndex; + unsigned char CurrentType; + }Level0, Level1; + + unsigned char IsAdd; + unsigned char IsSelecting; + + unsigned char CtlLevel; + + unsigned char AddTargetLevel; + unsigned char AddTargetType; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TRegisterAddRemove(){}; + TRegisterAddRemove(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderContent(TRect aRect, unsigned int aClr, unsigned int Index); + void RenderContent0(unsigned int aClr); + void RenderContent1(unsigned int aClr); + void RenderContent2(unsigned int aClr); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawVertScrollBar0(void); + void DrawVertScrollBar1(void); + + void Show(void); + void ReDraw(void); + void DrawCaption2(void); + + void DrawBtn(unsigned int x, unsigned int y, unsigned int x2, unsigned int y2, unsigned int aClr); + void DrawCtlItemAdd(); + void DrawCtlItemRemove(); + void ShowItemDetailAdd(); + void ShowItemDetailRemove(); + void RenderWarningSave(void); + + void HandCtlList(void); + + TGuiMsgReturn KeyInAddStart(unsigned char aKey); + TGuiMsgReturn KeyInRemoveStart(unsigned char aKey); + TGuiMsgReturn KeyInAdd(unsigned char aKey); + TGuiMsgReturn KeyInRemove(unsigned char aKey); + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel4Add(void); + void Check4SelectedAdd(void); + + void InitPanel4RemoveViaUserCode(void); + void InitPanel4Remove(void); + void Check4SelectedRemove(void); +}; + + + +#endif + diff --git a/MyCode/Gui/RegisterManual.cpp b/MyCode/Gui/RegisterManual.cpp new file mode 100644 index 0000000..8033cb6 --- /dev/null +++ b/MyCode/Gui/RegisterManual.cpp @@ -0,0 +1,1472 @@ +#include "RuntimeData.h" +#include "RegisterManual.h" + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +extern "C"{ + #include "user_norflash.h" + #include "uart_key_drv.h" +} + +void TRegisterManual::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "回路->手动注册"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "回路号"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "地址号"); + TextRender_string24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +40, clNearWhite, "类型:"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "二次码"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "分区号"); + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "设备定义"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "输入信号"); + TextRender_string24(Lv.Grid.Left[3] +42, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "反馈"); + TextRender_string24(Lv.Grid.Left[3] +140, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "报警"); + TextRender_string24(Lv.Grid.Left[3] +236, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "监管"); + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 4, clNearWhite, ItemColor, "操作"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, "注册", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, "清除", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Loop->Register By Manual"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "LoopID"); + TextRender_string24(Lv.Grid.Left[0] + 160, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +6, clNearWhite, "Local"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] + 40, clNearWhite, "Addr"); + TextRender_string24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +40, clNearWhite, "Type:"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "AuxID"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Zone"); + TextRender_string24(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] + 4, clNearWhite, ItemColor, "Assign"); + TextRender_string24(Lv.Grid.Left[3] +10, Lv.Grid.Top[3] + 4, clNearWhite, ItemColor, "Signal"); + TextRender_string24(Lv.Grid.Left[3] +42, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "FBCK"); + TextRender_string24(Lv.Grid.Left[3] +140, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "Fire"); + TextRender_string24(Lv.Grid.Left[3] +236, Lv.Grid.Top[3] + 36, clNearWhite, ItemColor, "SPER"); + TextRender_string24(Lv.Grid.Left[4] +10, Lv.Grid.Top[4] + 4, clNearWhite, ItemColor, "OPR"); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, "Reg", 14, clNearBlack); + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, "Del", 14, clNearBlack); + } +} + +void TRegisterManual::Init() +{ + IsViewList = 0; + IsPermission = 0; + ShowingResultOdd =0; + + IsOnGo =0; + IsOnShow =0; + IsWait4Rpy = 0; + IsRecData = 0; + + Tag.Reset(); + LastSta = 0; + List4What = 0; + Pitch = 1; + + + SignalInputType =0; + Cover.Reset(); +} + +void TRegisterManual::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickEditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 2, 50, 30, 0, 0, 1, clNearWhite); + + + TextDigitRender2Right24(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + + + + //Addr Start Editor + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + TextRender_string24(Lv.Grid.Left[0] + 140, Lv.Grid.Top[0] + 40, clNearWhite, "-"); + //Addr End Editor + IList->EditDescpShow.Init(Lv.Grid.Left[0] + 156, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + + + //dType Editor + IList->Edit[0].Init(Lv.Grid.Left[0] + 326, Lv.Grid.Top[0] + 36, 50, 30, 0, 0, 1, clNearWhite); + IList->STextDType.Init(Lv.Grid.Left[0] + 380, Lv.Grid.Top[0] + 40, 240, 30, 0, 0, clNearWhite, ItemColor); + if(LanguageEnCn==0){ + IList->STextDType.SetText("未定义", 24); + }else{ + IList->STextDType.SetText("undefine", 24); + } + + IList->STextDType.Enable = 1; + IList->STextDType.Visible =1; + IList->STextCtlNum.Enable = 1; + IList->STextCtlNum.Visible =1; + + IList->EditPortNum.SetMaxLen(2); + IList->EditAddrNum.SetMaxLen(3); + IList->EditDescpShow.SetMaxLen(3); + IList->Edit[0].SetMaxLen(3); + IList->EditPortNum.Enable = 1; + IList->EditPortNum.Visible = 1; + IList->EditAddrNum.Enable = 1; + IList->EditAddrNum.Visible = 1; + IList->EditDescpShow.Enable = 1; + IList->EditDescpShow.Visible = 1; + IList->Edit[0].Enable = 1; + IList->Edit[0].Visible = 1; + + //User Code & Area Assign + + IList->EditUserCode.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 6, 108, 30, 0, 0, 1, clNearWhite); + IList->EditAreaAssign.Init(Lv.Grid.Left[1] + 84, Lv.Grid.Top[1] + 40, 108, 30, 0, 0, 1, clNearWhite); + + IList->EditUserCode.Enable = 1; + IList->EditUserCode.Visible =1; + IList->EditUserCode.SetMaxLen(8); + IList->EditAreaAssign.Enable = 1; + IList->EditAreaAssign.Visible =1; + IList->EditAreaAssign.SetMaxLen(5); + + for(int i=2; iEdit[1].Init(Lv.Grid.Left[2] +110, Lv.Grid.Top[2] + 4, 100,30,0,0,1,clNearBlack); + IList->Edit[1].SetMaxLen(3); + IList->Edit[1].Str.Clear(); + IList->STextModuleInDefineType.Init(Lv.Grid.Left[2] +6, Lv.Grid.Top[2] + 38, 240,30,0,0,clNearWhite, ItemColor); + IList->STextModuleInDefineType.Enable = 1; + IList->STextModuleInDefineType.Visible = 1; + if(LanguageEnCn==0)IList->STextModuleInDefineType.SetText("未定义",24); + else IList->STextModuleInDefineType.SetText("undefine",24); + + IList->STextLastState.Init(Lv.Grid.Left[4] +120, Lv.Grid.Top[4] + 4, 156, 30, 0, 0, clNearWhite, ItemColor); + IList->STextLastState.TextClear(); + + IList->EditPortNum.SetText("01",24); + IList->EditAddrNum.SetText("001",24); + IList->EditDescpShow.SetText("002",24); + IList->EditUserCode.SetText("00000000",24); + IList->EditAreaAssign.SetText("0000",24); + IList->Edit[0].SetText("000",24); + IList->Edit[1].SetText("000",24); + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->EditDescpShow.Show(); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + IList->Edit[0].Show(); + IList->STextDType.Show(); + IList->Edit[1].Show(); + IList->STextModuleInDefineType.Show(); + + DrawFixText(); + + RedrawModuleInSignalInType(); + + Check4Selected(); + + ShowCover(); +} + +void TRegisterManual::ShowCoverAuxId() //1 Cover ,0 ignore +{ + if(LanguageEnCn==0){ + if(Cover.AuxId){ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 6, clNearWhite, ItemColor, "覆盖 "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 6, clNearWhite, ItemColor, "不覆盖"); + } + }else{ + if(Cover.AuxId){ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 6, clNearWhite, ItemColor, "Cover "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 6, clNearWhite, ItemColor, "Ignore"); + } + } +} + +void TRegisterManual::ShowCoverZone() +{ + if(LanguageEnCn==0){ + if(Cover.Zone){ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 36, clNearWhite, ItemColor, "覆盖 "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 36, clNearWhite, ItemColor, "不覆盖"); + } + }else{ + if(Cover.Zone){ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 36, clNearWhite, ItemColor, "Cover "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 200, Lv.Grid.Top[1] + 36, clNearWhite, ItemColor, "Ignore"); + } + } +} + +void TRegisterManual::ShowCoverAssignType() +{ + if(LanguageEnCn==0){ + if(Cover.AssignType){ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "覆盖 "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "不覆盖"); + } + }else{ + if(Cover.AssignType){ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "Cover "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[2] + 6, clNearWhite, ItemColor, "Ignore"); + } + } +} + +void TRegisterManual::ShowCoverSignal() +{ + if(LanguageEnCn==0){ + if(Cover.Signal){ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "覆盖 "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "不覆盖"); + } + }else{ + if(Cover.Signal){ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "Cover "); + }else{ + TextRender_string24(Lv.Grid.Left[1] + 216, Lv.Grid.Top[3] + 6, clNearWhite, ItemColor, "Ignore"); + } + } +} + +void TRegisterManual::ShowCover() +{ + ShowCoverAuxId(); + ShowCoverZone(); + ShowCoverAssignType(); + ShowCoverSignal(); +} + +void TRegisterManual::DrawCommonByExReturn() +{ + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + + TextDigitRender2Right24(Lv.Grid.Left[0] + 232, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + + for(int i=2; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + + + if(Lv.Panel.Active)RectFillRender(Lv.PanelSmall.Left, Lv.PanelSmall.Top, Lv.PanelSmall.Right, Lv.PanelSmall.Bottom, SmallPanelColor); + DrawListDetail(); + + DrawFixText(); + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->EditDescpShow.Show(); + IList->EditUserCode.Show(); + IList->EditAreaAssign.Show(); + IList->Edit[0].Show(); + IList->STextDType.Show(); + IList->Edit[1].Show(); + IList->STextModuleInDefineType.Show(); + + Check4Selected(); +} + +void TRegisterManual::DrawListDetail() +{ + int i; + if(List4What == 0){ + if(LanguageEnCn==0)TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, "注册类型列表 数量:"); + else TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, "Hardware Dev Type:"); + for(i=0;i<8;i++)TextDrawCount[i]=0; + TMyString::sFrom3Dg(HtEntryCount,TextDrawCount); + TMyString::sFillFixLen(TextDrawCount, 4); + TextRender_string24(Lv.PanelSmall.Left + 230, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, TextDrawCount); + }else + if(List4What == 1){ + if(LanguageEnCn==0)TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, "指派类型列表 数量:"); + else TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, "Assign Type: "); + for(i=0;i<8;i++)TextDrawCount[i]=0; + TMyString::sFrom3Dg(AtEntryCount,TextDrawCount); + TMyString::sFillFixLen(TextDrawCount, 4); + TextRender_string24(Lv.PanelSmall.Left + 230, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, TextDrawCount); + }else + if(List4What == 2){ + if(LanguageEnCn==0)TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, "有效区域列表 数量:"); + else TextRender_string24(Lv.PanelSmall.Left + 10, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, "List Of Zone:"); + for(i=0;i<8;i++)TextDrawCount[i]=0; + TMyString::sFrom4Dg(AreaEntryCount,TextDrawCount); + TMyString::sFillFixLen(TextDrawCount, 4); + TextRender_string24(Lv.PanelSmall.Left + 230, Lv.PanelSmall.Top + 6, clNearWhite, SmallPanelColor, TextDrawCount); + } +} + + +void TRegisterManual::Show(void) +{ + LoadHwTypeListStr(); + LoadAssignTypeListStr(); + LoadAreaInf(); + + RenderBackGround(); + DrawSelf(); + IsOnGo =1; + IsOnShow =1; + + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); +} + +void TRegisterManual::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + DrawCommonByExReturn(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TRegisterManual::RedrawModuleInSignalInType() +{ + if(SignalInputType == 1){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(SignalInputType == 2){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else + if(SignalInputType == 3){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[3] + 206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TRegisterManual::ClearSelected() +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 0; + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 1: + IList->EditAddrNum.Selected = 0; + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 2: + IList->EditDescpShow.Selected = 0; + IList->EditDescpShow.Show(); + IList->EditDescpShow.ShowCursor(); + break; + case 3: + IList->Edit[0].Selected = 0; + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 4: + IList->EditUserCode.Selected = 0; + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 0; + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[1].Selected = 0; + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + case 7: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, ItemColor); + break; + case 10: + if(LanguageEnCn==0)tText="注册"; else tText="Reg "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 11: + if(LanguageEnCn==0)tText="清除"; else tText="Del "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + } +} + +//______________________________________________________________________________________________________________________________ +void TRegisterManual::Check4Selected(void) +{ + char *tText; + switch(Tag.Inx){ + case 0: + IList->EditPortNum.Selected = 1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + IList->EditPortNum.ShowCursor(); + break; + case 1: + IList->EditAddrNum.Selected = 1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + IList->EditAddrNum.ShowCursor(); + break; + case 2: + IList->EditDescpShow.Selected = 1; + IList->EditDescpShow.SetPstTail(); + IList->EditDescpShow.Show(); + IList->EditDescpShow.ShowCursor(); + break; + case 3: + IList->Edit[0].Selected = 1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + IList->Edit[0].ShowCursor(); + break; + case 4: + IList->EditUserCode.Selected = 1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + IList->EditUserCode.ShowCursor(); + break; + case 5: + IList->EditAreaAssign.Selected = 1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + IList->EditAreaAssign.ShowCursor(); + break; + case 6: + IList->Edit[1].Selected = 1; + IList->Edit[1].SetPstTail(); + IList->Edit[1].Show(); + IList->Edit[1].ShowCursor(); + break; + case 7: + TRoundSquare::sSelected(Lv.Grid.Left[3] +12, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 8: + TRoundSquare::sSelected(Lv.Grid.Left[3] +110, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 9: + TRoundSquare::sSelected(Lv.Grid.Left[3] +206, Lv.Grid.Top[3] + 36, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 10: + if(LanguageEnCn==0)tText="注册"; else tText="Reg "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +60, Lv.Grid.Top[4] + 36, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 11: + if(LanguageEnCn==0)tText="清除"; else tText="Del "; + TRoundRect::sDrawBySize(Lv.Grid.Left[4] +150, Lv.Grid.Top[4] + 36, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + } +} + +//_____________________________________________________________________________________________________________________________ + +void TRegisterManual::ShowHardwareTypeList() +{ + int i, x, y; + unsigned int aClr, aAddr, Index, wc; + if(IsViewList){ + aClr = clBlue; + }else{ + aClr = clMedGray; + } + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + + i = HtListIndex * 16; + wc =0; + for(; i= 16)break; + } + i = HtListIndex * 16; + TVScrollBar::sDrawByPoint(Lv.Panel.Right-24, Lv.Panel.Top +4, Lv.Panel.Right -4, Lv.Panel.Bottom -4, clBlue, clGray, HtEntryCount, 16, i); +} + +void TRegisterManual::ShowAssignTypeList() +{ + int i, x, y; + unsigned int aClr, aAddr, Index, wc; + if(IsViewList){ + aClr = clBlue; + }else{ + aClr = clMedGray; + } + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + + i = AtListIndex * 8; + wc =0; + for(; i= 8)break; + } + i = AtListIndex * 8; + TVScrollBar::sDrawByPoint(Lv.Panel.Right-24, Lv.Panel.Top +4, Lv.Panel.Right -4, Lv.Panel.Bottom -4, clBlue, clGray, AtEntryCount, 8, i); +} + +void TRegisterManual::ShowAreaList() +{ + //__________________________________________ + int i, x, y; + unsigned int aClr, aAddr, Index, wc; + if(IsViewList){ + aClr = clBlue; + }else{ + aClr = clMedGray; + } + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); +} + +void TRegisterManual::RedrawSta() +{ + IList->STextLastState.Show(); +} + +void TRegisterManual::LoadHwTypeListStr() +{ + int i; + unsigned int aAddr; + char *cText; + if(LanguageEnCn==0){ + cText = "未"; + }else{ + cText = "un"; + } + HtEntryCount = 0; + for(i=0; i<256; i++){ + aAddr = dAddrSdRam_Register + (i * 4); + *(volatile unsigned int *)(aAddr) = 0; + + } + if(LanguageEnCn==0){ + for(i=0; i<256; i++){ + if( (StrHwType[i][0] != cText[0]) || (StrHwType[i][1] != cText[1]) ){ + aAddr = dAddrSdRam_Register + (HtEntryCount * 4); + *(volatile unsigned int *)(aAddr) = i; + HtEntryCount++; + }else{ + continue; + } + } + }else{ + for(i=0; i<256; i++){ + if( (StrHwTypeEn[i][0] != cText[0]) || (StrHwTypeEn[i][1] != cText[1]) ){ + aAddr = dAddrSdRam_Register + (HtEntryCount * 4); + *(volatile unsigned int *)(aAddr) = i; + HtEntryCount++; + }else{ + continue; + } + } + } + HtPageCount = HtEntryCount / 16; + if(HtEntryCount % 16){ + HtPageCount++; + } + + HtListIndex = 0; +} + +void TRegisterManual::LoadAssignTypeListStr() +{ + int i; + unsigned int aAddr; + char *cText; + if(LanguageEnCn==0){ + cText = "未"; + }else{ + cText = "un"; + } + AtEntryCount = 0; + for(i=0; i<256; i++){ + aAddr = dAddrSdRam_Register + 1024 + (i * 4); + *(volatile unsigned int *)(aAddr) = 0; + + } + if(LanguageEnCn==0){ + for(i=0; i<256; i++){ + if( (StrTypeShortName[i][0] != cText[0]) || (StrTypeShortName[i][1] != cText[1]) ){ + aAddr = dAddrSdRam_Register + 1024 + (AtEntryCount * 4); + *(volatile unsigned int *)(aAddr) = i; + AtEntryCount++; + }else{ + continue; + } + } + }else{ + for(i=0; i<256; i++){ + if( (StrTypeShortNameEn[i][0] != cText[0]) || (StrTypeShortNameEn[i][1] != cText[1]) ){ + aAddr = dAddrSdRam_Register + 1024 + (AtEntryCount * 4); + *(volatile unsigned int *)(aAddr) = i; + AtEntryCount++; + }else{ + continue; + } + } + } + AtPageCount = AtEntryCount / 8; + if(AtEntryCount % 8){ + AtPageCount++; + } + + AtListIndex = 0; +} + +void TRegisterManual::LoadAreaInf() +{ + AreaEntryCount = 0; + AreaListIndex = 0; +} + +void TRegisterManual::PermissionCmdReturnDraw() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + DrawListDetail(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); +} + +void TRegisterManual::PermissionCmdGO() +{ + if(PermissionCmd){ + SendCmdOneAddr(1); + IsWait4Rpy =1; + IsAdd =1; + IsRecData =0; + TimeOut =0; + IList->STextLastState.TextClear(); + IList->STextLastState.Show(); + }else{ + SendCmdOneAddr(0); + IsWait4Rpy =1; + IsAdd =0; + IsRecData =0; + TimeOut =0; + IList->STextLastState.TextClear(); + IList->STextLastState.Show(); + } +} + +TGuiMsgReturn TRegisterManual::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + TDMix aFullPath; + unsigned int IsHasPrc = 0; + + if(IsWait4Rpy){ + if(aKey != VK_RETURN)return aMsg; + } + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + }else + if(IsViewList == 0){ + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Inx == 0){ + IList->EditPortNum.KeyIn(aKey); + IList->EditPortNum.Show(); + }else + if(Tag.Inx == 1){ + if(aKey == VK_RIGHT){ + if(IList->EditAddrNum.Pst >= IList->EditAddrNum.Str.GetEndPst()){ + ClearSelected(); + Tag.Inx =2; + Check4Selected(); + IsHasPrc = 1; + } + } + if(IsHasPrc == 0){ + IList->EditAddrNum.KeyIn(aKey); + IList->EditAddrNum.Show(); + } + }else + if(Tag.Inx == 2){ + if(aKey == VK_RIGHT){ + if(IList->EditDescpShow.Pst >= IList->EditDescpShow.Str.GetEndPst()){ + ClearSelected(); + Tag.Inx =3; + Check4Selected(); + IsHasPrc = 1; + } + }else + if(aKey == VK_LEFT){ + if(IList->EditDescpShow.Pst < 0){ + ClearSelected(); + Tag.Inx =1; + Check4Selected(); + IsHasPrc = 1; + } + } + if(IsHasPrc == 0){ + IList->EditDescpShow.KeyIn(aKey); + IList->EditDescpShow.Show(); + } + }else + if(Tag.Inx == 3){ + if(aKey == VK_LEFT){ + if(IList->Edit[0].Pst < 0){ + ClearSelected(); + Tag.Inx =2; + Check4Selected(); + IsHasPrc = 1; + } + } + if(IsHasPrc == 0){ + IList->Edit[0].KeyIn(aKey); + int iVal = IList->Edit[0].Str.ToInteger(); + if(iVal <0){ + iVal = 0; + IList->Edit[0].Str.FromUInt3Dg(iVal); + }else + if(iVal >255){ + iVal = 0; + IList->Edit[0].Str.FromUInt3Dg(iVal); + } + NewHardwareType = iVal; + IList->Edit[0].Show(); + if(LanguageEnCn == 0) + IList->STextDType.SetText(StrHwType[iVal],24); + else + IList->STextDType.SetText(StrHwTypeEn[iVal],24); + IList->STextDType.Show(); + } + }else + if(Tag.Inx == 4){ + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + int iVal = IList->EditUserCode.Str.ToInteger(); + if((iVal >0) && (iVal<100000000))Cover.AuxId=1; else Cover.AuxId=0; + ShowCoverAuxId(); + }else + if(Tag.Inx == 5){ + IList->EditAreaAssign.KeyIn(aKey); + IList->EditAreaAssign.Show(); + int iVal = IList->EditAreaAssign.Str.ToInteger(); + if((iVal >0) && (iVal<=dAreaCountMax))Cover.Zone=1; else Cover.Zone=0; + ShowCoverZone(); + }else + if(Tag.Inx == 6){ + IList->Edit[1].KeyIn(aKey); + IList->Edit[1].Show(); + int iVal = IList->Edit[1].Str.ToInteger(); + if(iVal <0)iVal = 0; + if(iVal >255)iVal = 0; + if(LanguageEnCn==0)IList->STextModuleInDefineType.SetText(StrTypeShortName[iVal],24); + else IList->STextModuleInDefineType.SetText(StrTypeShortNameEn[iVal],24); + IList->STextModuleInDefineType.Show(); + iVal = IList->Edit[1].Str.ToInteger(); + if((iVal >0) && (iVal<=254))Cover.AssignType=1; else Cover.AssignType=0; + ShowCoverAssignType(); + }else + if(Tag.Inx == 7){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx =8; + Check4Selected(); + } + }else + if(Tag.Inx == 8){ + if(aKey == VK_RIGHT){ + ClearSelected(); + Tag.Inx =9; + Check4Selected(); + }else + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx =7; + Check4Selected(); + } + }else + if(Tag.Inx == 9){ + if(aKey == VK_LEFT){ + ClearSelected(); + Tag.Inx =8; + Check4Selected(); + } + } + break; + case VK_UP: + if(Tag.Inx >0){ + ClearSelected(); + Tag.Inx--; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx=11; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Inx <11){ + ClearSelected(); + Tag.Inx++; + Check4Selected(); + }else{ + ClearSelected(); + Tag.Inx=0; + Check4Selected(); + } + break; + case VK_TAB: + IsViewList = 1; + ClearSelected(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); + break; + case VK_EXECUTE: + if(Tag.Inx == 7){ + if(SignalInputType==1)SignalInputType =0; + else SignalInputType=1; + RedrawModuleInSignalInType(); + if((SignalInputType >0) && (SignalInputType<4))Cover.Signal=1; else Cover.Signal=0; + ShowCoverSignal(); + }else + if(Tag.Inx == 8){ + if(SignalInputType==2)SignalInputType =0; + else SignalInputType=2; + RedrawModuleInSignalInType(); + if((SignalInputType >0) && (SignalInputType<4))Cover.Signal=1; else Cover.Signal=0; + ShowCoverSignal(); + }else + if(Tag.Inx == 9){ + if(SignalInputType==3)SignalInputType =0; + else SignalInputType=3; + RedrawModuleInSignalInType(); + if((SignalInputType >0) && (SignalInputType<4))Cover.Signal=1; else Cover.Signal=0; + ShowCoverSignal(); + }else + if(Tag.Inx == 10){ + //Add + if(PrepUserCodeAssignTypeData2Write()){ + PermissionCmd = 1; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("数据错误",24); + else IList->STextLastState.SetText("Data Err",24); + IList->STextLastState.Show(); + } + }else + if(Tag.Inx == 11){ + //Remove + if(PrepCheckToRemove()){ + PermissionCmd = 0; + if(SystemPermission >2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -34, 140, 3); + } + }else{ + if(LanguageEnCn==0)IList->STextLastState.SetText("路径错误",24); + else IList->STextLastState.SetText("Path Err",24); + IList->STextLastState.Show(); + } + } + break; + case VK_RETURN: + IsOnGo =0; + IsOnShow =0; + IsWait4Rpy = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case VK_UP: + if(List4What == 0){ + //Show dType + if(HtListIndex >0){ + HtListIndex--; + ShowHardwareTypeList(); + } + }else + if(List4What == 1){ + //Show Assign Type + if(AtListIndex >0){ + AtListIndex--; + ShowAssignTypeList(); + } + }else + if(List4What == 2){ + //Show Area Inf + if(AreaListIndex >0){ + AreaListIndex--; + ShowAreaList(); + } + } + break; + case VK_DOWN: + if(List4What == 0){ + if(HtListIndex < (HtPageCount -1)){ + HtListIndex++; + ShowHardwareTypeList(); + } + }else + if(List4What == 1){ + //Show Assign Type + if(AtListIndex < (AtPageCount -1)){ + AtListIndex++; + ShowAssignTypeList(); + } + }else + if(List4What == 2){ + //Show Area Inf + if(AreaListIndex < (AreaPageCount -1)){ + AreaListIndex++; + ShowAreaList(); + } + } + break; + case VK_TAB: + IsViewList = 0; + Check4Selected(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); + break; + case VK_LEFT: + if(List4What >0)List4What--;else List4What =2; + DrawListDetail(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); + break; + case VK_RIGHT: + if(List4What <2)List4What++;else List4What =0; + DrawListDetail(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); + break; + case VK_EXECUTE: + List4What ++ ; + if(List4What > 2)List4What = 0; + DrawListDetail(); + if(List4What == 0)ShowHardwareTypeList(); + else if(List4What == 1)ShowAssignTypeList(); + else if(List4What == 2)ShowAreaList(); + break; + case VK_RETURN: + IsOnGo =0; + IsOnShow =0; + IsWait4Rpy = 0; + aMsg = guiMsgReturn; + break; + } + } + return aMsg; +} + +void TRegisterManual::FillRegData() +{ + unsigned int i, x; + if(P0 == 0)return; + if(P0 > dPORT_MAX_COUNT)return; + if(P1Start == 0)return; + if(P1Start > 250)return; + if(P1End == 0)return; + if(P1End > 250)return; + + if(IsAdd){ + if(IsAllTypeModify){ + for(i=P1Start-1; iSTextLastState.SetText("注册成功",24); + }else{ + IList->STextLastState.SetText("清除成功",24); + } + }else{ + if(IsAdd){ + IList->STextLastState.SetText("Reg OK ",24); + }else{ + IList->STextLastState.SetText("Del OK ",24); + } + } + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + IList->STextLastState.Show(); + //Write to Flash Here + FillRegData(); + SaveToFlash(P0); + Record.OperateAdd_RegisterByManual(Data[2], Data[3], Data[4], Data[6], IsAdd); + Record.ReadRegisterData(); + Record.ReadDisplayPadSet(); + + Record.ReadDevUserSet(); + Record.ReadDevAreaNum(); + unsigned int aUcFull = this->UserCode; + int SaveOk =1; + if(IsAdd){ + for(int x=P1Start-1; xSTextLastState.SetText("保存失败",24); + }else{ + IList->STextLastState.SetText("Save Err",24); + } + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + IList->STextLastState.Show(); + } + }else{ + //Fail + IsWait4Rpy = 0; + if(LanguageEnCn==0){ + if(IsAdd){ + IList->STextLastState.SetText("注册失败",24); + }else{ + IList->STextLastState.SetText("清除失败",24); + } + }else{ + if(IsAdd){ + IList->STextLastState.SetText("Reg Err ",24); + }else{ + IList->STextLastState.SetText("Del Err ",24); + } + } + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + IList->STextLastState.Show(); + } + IsWait4Rpy = 0; + }else{ + TimeOut++; + if(TimeOut > 6){ + IsWait4Rpy = 0; + if(LanguageEnCn==0)IList->STextLastState.SetText("回复超时",24); + else IList->STextLastState.SetText("Time Out",24); + if( (IsSelfChecking == 0) && (PmsIntervene.IsShow == 0) ) + IList->STextLastState.Show(); + } + } + }else{ + TimeOut++; + if(TimeOut > 10){ + IsWait4Rpy = 0; + } + } + } +} + +void TRegisterManual::SendCmdAddMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr) +{ + Data[0] = 0; + Data[1] = MainCtl.fData.Split.MyNum; + Data[2] = aCc; + Data[3] = sAddr; + Data[4] = eAddr; + Data[5] = TypeToBeModify; + Data[6] = NewHardwareType; + Data[7] = 1; + + InnerCan.OBufInsert(1, cmSinglePortAddrManualRegist, Data, 8); +} + +void TRegisterManual::SendCmdRemoveMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr) +{ + Data[0] = 0; + Data[1] = MainCtl.fData.Split.MyNum; + Data[2] = aCc; + Data[3] = sAddr; + Data[4] = eAddr; + Data[5] = TypeToBeModify; + Data[6] = 0;//NewHardwareType; + Data[7] = 0; + + InnerCan.OBufInsert(1, cmSinglePortAddrManualRegist, Data, 8); +} + +void TRegisterManual::SendCmdOneAddr(int AddOrRemove) +{ + IsAllTypeModify = 1; + if(AddOrRemove){ + SendCmdAddMultAddr(P0,P1Start,P1End); + }else{ + SendCmdRemoveMultAddr(P0, P1Start, P1End); + } + IsWait4Rpy = 1; + +} + +void TRegisterManual::PushRecData(unsigned char *p) +{ + RecData[0] = p[0]; + RecData[1] = p[1]; + RecData[2] = p[2]; + RecData[3] = p[3]; + RecData[4] = p[4]; + RecData[5] = p[5]; + RecData[6] = p[6]; + RecData[7] = p[7]; + IsRecData = 1; +} + +void TRegisterManual::SaveToFlash(unsigned char aPath0) +{ + unsigned int aAddr; + unsigned char aP0, aP1; + volatile unsigned int aWait; + volatile unsigned int aFlashState; + int i,x, iVal; + if(aPath0 == 0)return; + if(aPath0 > dPORT_MAX_COUNT)return; + + aP0 = aPath0-1; + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + //Erase + aAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * aP0) + (256 * 0); + nor_erase_sector_4k(dFlashRegisterDataChip,aAddr); + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + //write ExistTable dType DisplaySetting + TRegister::sIList = IList; + TRegister::sWriteOnePort(aPath0); + + //Write AuxID, AssignType, Signal Type + if( (Cover.AuxId) || (Cover.AssignType) || (Cover.Signal) ){ + //AudId + iVal = IList->EditUserCode.Str.ToInteger(); + AuxId = static_cast(iVal); + if(AuxId>99999999)AuxId=1; + //Assign Type + iVal = IList->Edit[1].Str.ToInteger(); + if(iVal<0) iVal =1; + if(iVal>255)iVal =1; + AssignType = static_cast(iVal); + //Signal Type + if(SignalInputType){ + if(SignalInputType==1)Signal=1; + if(SignalInputType==2)Signal=2; + if(SignalInputType==3)Signal=4; + }else{ + Cover.Signal = 0; + } + + for(x=P1Start -1; (x>-1)and(x99999999)AuxId=1; + } + if(Cover.AssignType)Port[aP0].AssignType[x]=AssignType; + if(Cover.Signal)Port[aP0].FuncSetByte[x]=Signal; + } + + //Write + TDevProperty::sIList = IList; + TDevProperty::sWriteAuxIdAssignTypeSignalType(aP0+1); + } + + if(Cover.Zone){ + iVal = IList->EditAreaAssign.Str.ToInteger(); + if(iVal<1)iVal=1; + if(iVal>dAreaCountMax)iVal=1; + ZoneID = static_cast(iVal); + for(x=P1Start -1; (x>-1)and(xEditPortNum.Str.ToInteger(); + //P1Start = IList->EditAddrNum.Str.ToInteger(); + //P1End = IList->EditDescpShow.Str.ToInteger(); + //this->UserCode = IList->EditUserCode.Str.ToInteger(); + + iVal = IList->EditPortNum.Str.ToInteger(); + if(iVal<0)return 0; + if(iVal>dPORT_MAX_COUNT)return 0; + P0=iVal; + + iVal = IList->EditAddrNum.Str.ToInteger(); + if(iVal<1)return 0; + if(iVal>dEP_MAX_COUNT_PER_PORT)return 0; + P1Start = iVal; + + iVal = IList->EditDescpShow.Str.ToInteger(); + if(iVal<1)return 0; + if(iVal>dEP_MAX_COUNT_PER_PORT)return 0; + P1End = iVal; + + iVal = IList->Edit[0].Str.ToInteger(); + if(iVal <1)return 0; + if(iVal >255)return 0; + NewHardwareType = iVal; + + iVal = IList->Edit[1].Str.ToInteger(); + if(iVal <0)return 0; + if(iVal >255)return 0; + NewAssignType = iVal; + + iVal = IList->EditUserCode.Str.ToInteger(); + if(iVal>999999999)return 0; + + Pitch = 1; + TypeToBeModify = 0; + + return 1; + } + return 0; +} + +int TRegisterManual::PrepCheckToRemove() +{ + int iVal; + if(3){ + //P0 = IList->EditPortNum.Str.ToInteger(); + //P1Start = IList->EditAddrNum.Str.ToInteger(); + //P1End = IList->EditDescpShow.Str.ToInteger(); + //this->UserCode = IList->EditUserCode.Str.ToInteger(); + + iVal = IList->EditPortNum.Str.ToInteger(); + if(iVal<0)return 0; + if(iVal>dPORT_MAX_COUNT)return 0; + P0=iVal; + + iVal = IList->EditAddrNum.Str.ToInteger(); + if(iVal<1)return 0; + if(iVal>dEP_MAX_COUNT_PER_PORT)return 0; + P1Start = iVal; + + iVal = IList->EditDescpShow.Str.ToInteger(); + if(iVal<1)return 0; + if(iVal>dEP_MAX_COUNT_PER_PORT)return 0; + P1End = iVal; + + //iVal = IList->Edit[0].Str.ToInteger(); + //if(iVal <0)return 0; + //if(iVal >255)return 0; + //NewHardwareType = iVal; + + //iVal = IList->Edit[1].Str.ToInteger(); + //if(iVal <0)return 0; + //if(iVal >255)return 0; + //NewAssignType = iVal; + + //iVal = IList->EditUserCode.Str.ToInteger(); + //if(iVal>999999999)return 0; + + //Pitch = 1; + TypeToBeModify = 0; + + return 1; + } + return 0; +} + +int TRegisterManual::ExtRequst(unsigned char Prm) +{ + IsOnGo =0; + IsOnShow =0; + IsWait4Rpy = 0; + return 0; +} + + + diff --git a/MyCode/Gui/RegisterManual.h b/MyCode/Gui/RegisterManual.h new file mode 100644 index 0000000..3e07ae7 --- /dev/null +++ b/MyCode/Gui/RegisterManual.h @@ -0,0 +1,224 @@ +#ifndef REGISTERMANUAL_H_ +#define REGISTERMANUAL_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TRegisterManual{ + public: + static constexpr unsigned short hList[12] = {72,72,72,72, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,290,290,290, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 5, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +6, + .Panel.Width = 502, + .Panel.Heigh = 250, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 250 -1, + + .PanelSmall.Active = 1, + .PanelSmall.Left = wList[1] + 6, + .PanelSmall.Top = (36 + 32 +2) + hList[0] +6 + 250 -1 + 1, + .PanelSmall.Width = 502, + .PanelSmall.Heigh = 42, + .PanelSmall.Right = wList[1] + 6 + 502 -1, + .PanelSmall.Bottom = (36 + 32 +2) + hList[0] +6 + 250 -1 + 1 + 42 -1, + }; + + public: + class TItemList *IList; + struct{ + unsigned char InxMin; + unsigned char InxMax; + unsigned char Inx; + void Reset(){ + Inx = 0; + InxMin = 0; + InxMax =11; + } + }Tag; + unsigned char LastSta; + + TMyString Str; + + unsigned char IsPermission; + unsigned char PermissionCmd; + unsigned char IsViewList; + unsigned char ShowingResultOdd; + + //Hardware Type + unsigned int HtListIndex; + unsigned int HtEntryCount; + unsigned int HtPageCount; + + //Assign Type + unsigned int AtListIndex; + unsigned int AtEntryCount; + unsigned int AtPageCount; + + //Area + unsigned int AreaListIndex; + unsigned int AreaEntryCount; + unsigned int AreaPageCount; + + unsigned char Data[8]; + unsigned char RecData[8]; + + //unsigned char ExistTable[256]; + //unsigned char TypeTable[256]; + + int IsOnGo; + int IsOnShow; + + unsigned char IsWait4Rpy; + unsigned char IsAdd; + unsigned char IsRecData; + unsigned char TimeOut; + + unsigned char P0; + unsigned char P1Start; + unsigned char P1End; + unsigned char IsAllTypeModify; + unsigned char TypeToBeModify; + unsigned char NewHardwareType; + unsigned char List4What; + + unsigned int UserCode; + unsigned char NewAssignType; + unsigned char SignalInputType; + unsigned int Pitch; + + unsigned int AuxId; + unsigned char AssignType; + unsigned char Signal; + unsigned short ZoneID; + struct { + unsigned char AuxId; + unsigned char Zone; + unsigned char AssignType; + unsigned char Signal; + void Reset(){ + AuxId =0; + Zone = 0; + AssignType = 0; + Signal = 0; + } + }Cover; + + union{ + unsigned char D8[256]; + unsigned short D16[128]; + unsigned int D32[64]; + }ReadWriteData; + char TextDrawCount[16]; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TRegisterManual(){}; + TRegisterManual(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(); + } + void Init(); + + void LoadHwTypeListStr(); + void LoadAssignTypeListStr(); + void LoadAreaInf(); + + void DelayMs(unsigned int aMs); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawCommonByExReturn(); + void PermissionCmdReturnDraw(); + void RedrawSta(); + void DrawListDetail(); + void DrawFixText(); + + void ShowHardwareTypeList(); + void ShowAssignTypeList(); + void ShowAreaList(); + void ShowCoverAuxId(); //1 Cover ,0 ignore + void ShowCoverZone(); + void ShowCoverAssignType(); + void ShowCoverSignal(); + void ShowCover(); + + void Show(void); + void FullRedraw(int Prm); + void RedrawModuleInSignalInType(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void LoadData(); + void FillRegData(); + + void ShowWait(); + void PushRecData(unsigned char *p); + void PermissionCmdGO(); + + void ClearSelected(); + void Check4Selected(void); + + void Task1000Ms(); + + void SendCmdAddMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr); + void SendCmdRemoveMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr); + void SendCmdOneAddr(int AddOrRemove); + + void SaveToFlash(unsigned char aPath0); + int PrepUserCodeAssignTypeData2Write(); + int PrepCheckToRemove(); + + int ExtRequst(unsigned char Prm); +}; + + + +#endif + diff --git a/MyCode/Gui/RootDevVoltage.cpp b/MyCode/Gui/RootDevVoltage.cpp new file mode 100644 index 0000000..8c28e27 --- /dev/null +++ b/MyCode/Gui/RootDevVoltage.cpp @@ -0,0 +1,456 @@ +#include "RuntimeData.h" +#include "RootDevVoltage.h" + +//Unit For Voltage 0.2V +//unit For Current 0.01A + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +#define dfCMD_UpdateVoltage 220 + +static int xs[8] ={ + 126, 208, 268, 331, 421, 515, 597, 700 +}; +static int xv[8] ={ + 126, 230, 280, 343, 433, 543, 625, 700 +}; + +void TRootDevVoltage::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+358,Top,434, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + RectPanel.Set(120,78,680,410); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("系统调试->根设备电压电流", Caption.Text); + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + TopIndex = 0; +} + +void TRootDevVoltage::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TRootDevVoltage::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TRootDevVoltage::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TRootDevVoltage::DrawCaption2(void) +{ + TMyString::sFromStr("xxxxxxx", SText.Text); + //SText.Show(); +} + +void TRootDevVoltage::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); +} + +void TRootDevVoltage::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + aPanel->Show(); + PanelCanvasOut(); + DrawItems(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + PanelCanvasOut(); + DrawItems(); + } +} + +void TRootDevVoltage::SetAndShowCaption(unsigned char aType) +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); +} + +//______________________________________________________________________________________________________________________________ + +void TRootDevVoltage::DrawItems(void) +{ + unsigned int i, times; + unsigned int aP0; + unsigned int pn,nn, aClr; + int aTop = 128; + times = 0; + + RectFillRender(aPanel->Content.Left, aPanel->Content.Top+8, aPanel->Content.Right, aPanel->Content.Bottom -46, clFrmFace); + + for(i=TopIndex; i<64; i++){ + if(times>5)break; + if(i<40){ + aP0 = i+1; + TMyString::sClear(Text[1]); + TMyString::sClear(Text[2]); + TMyString::sAddOn2Dg(aP0, Text[1]); + if(Port[i].fData.Common.Id){ + aClr = clNearBlack; + }else{ + aClr = clGray; + } + + if(Port[i].fData.Common.Id){ + TMyString::sAddOn2Dg(aP0, Text[2]); + pn = static_cast(Port[i].fVoltage); + nn = static_cast(Port[i].fVoltage * 100); + pn = pn %100; + nn = nn %100; + TMyString::sClear(Text[3]); + TMyString::sAddOn2Dg(pn, Text[3]); + TMyString::sAddOnStr(".", Text[3]); + TMyString::sAddOn2Dg(nn, Text[3]); + pn = static_cast(Port[i].fCurrent); + nn = static_cast(Port[i].fCurrent * 1000); + pn = pn %10; + nn = nn %1000; + TMyString::sClear(Text[4]); + TMyString::sAddOn1Dg(pn, Text[4]); + TMyString::sAddOnStr(".", Text[4]); + TMyString::sAddOn3Dg(nn, Text[4]); + TextRender_string24(xv[0],aTop,aClr, " 回路"); + TextRender_string24(xv[1],aTop,aClr, Text[1]); + TextRender_string24(xv[2],aTop,aClr, Text[2]); + TextRender_string24(xv[3],aTop,aClr, Text[3]); + TextRender_string24(xv[4],aTop,aClr, Text[4]); + pn = Port[i].fData.Port.ResistedCount; + TMyString::sClear(Text[5]); + TMyString::sAddOn3Dg(pn, Text[5]); + TextRender_string24(xv[5],aTop,aClr, Text[5]); + pn = Port[i].fData.Port.OnlineCount; + TMyString::sClear(Text[6]); + TMyString::sAddOn3Dg(pn, Text[6]); + TextRender_string24(xv[6],aTop,aClr, Text[6]); + }else{ + TMyString::sAddOn2Dg(aP0, Text[2]); + TMyString::sFromStr("无数据", Text[3]); + TextRender_string24(xv[0],aTop,aClr, " 回路"); + TextRender_string24(xv[1],aTop,aClr, Text[1]); + TextRender_string24(xv[2],aTop,aClr, Text[2]); + TextRender_string24(xv[3],aTop,aClr, Text[3]); + } + }else + if(i<48){ + aP0 = i+1 - 40; + TMyString::sClear(Text[1]); + TMyString::sClear(Text[2]); + TMyString::sAddOn2Dg(aP0, Text[1]); + if(HandCtlBoard[i-40].fData.Common.Id){ + aClr = clNearBlack; + }else{ + aClr = clGray; + } + + if(HandCtlBoard[i-40].fData.Common.Id){ + TMyString::sAddOn2Dg(aP0 + 40, Text[2]); + pn = static_cast(HandCtlBoard[i-40].fVoltage); + nn = static_cast(HandCtlBoard[i-40].fVoltage*100); + pn = pn %100; + nn = nn %100; + TMyString::sClear(Text[3]); + TMyString::sAddOn2Dg(pn, Text[3]); + TMyString::sAddOnStr(".", Text[3]); + TMyString::sAddOn2Dg(nn, Text[3]); + pn = static_cast(HandCtlBoard[i-40].fCurrent); + nn = static_cast(HandCtlBoard[i-40].fCurrent*100); + pn = pn %100; + nn = nn %100; + TMyString::sClear(Text[4]); + TMyString::sAddOn2Dg(pn, Text[4]); + TMyString::sAddOnStr(".", Text[4]); + TMyString::sAddOn2Dg(nn, Text[4]); + TextRender_string24(xv[0],aTop,aClr, "总线盘"); + TextRender_string24(xv[1],aTop,aClr, Text[1]); + TextRender_string24(xv[2],aTop,aClr, Text[2]); + TextRender_string24(xv[3],aTop,aClr, Text[3]); + TextRender_string24(xv[4],aTop,aClr, Text[4]); + pn = HandCtlBoard[i-40].fData.HandCtl.ResistedCount; + TMyString::sClear(Text[5]); + TMyString::sAddOn3Dg(pn, Text[5]); + TextRender_string24(xv[5],aTop,aClr, Text[5]); + pn = HandCtlBoard[i-40].fData.HandCtl.ResistedCount; + TMyString::sClear(Text[6]); + TMyString::sAddOn3Dg(pn, Text[6]); + TextRender_string24(xv[6],aTop,aClr, Text[6]); + }else{ + TMyString::sAddOn2Dg(aP0 + 40, Text[2]); + TMyString::sFromStr("无数据", Text[3]); + TextRender_string24(xv[0],aTop,aClr, "总线盘"); + TextRender_string24(xv[1],aTop,aClr, Text[1]); + TextRender_string24(xv[2],aTop,aClr, Text[2]); + TextRender_string24(xv[3],aTop,aClr, Text[3]); + } + }else + if(i<56){ + aP0 = i+1 - 48; + TMyString::sClear(Text[1]); + TMyString::sClear(Text[2]); + TMyString::sAddOn2Dg(aP0, Text[1]); + if(DirectCtlBoard[i-48].fData.Common.Id){ + aClr = clNearBlack; + }else{ + aClr = clGray; + } + if(DirectCtlBoard[i-48].fData.Common.Id){ + TMyString::sAddOn2Dg(aP0 + 48, Text[2]); + pn = static_cast(DirectCtlBoard[i-48].fVoltage); + nn = static_cast(DirectCtlBoard[i-48].fVoltage * 100); + pn = pn %100; + nn = nn %100; + TMyString::sClear(Text[3]); + TMyString::sAddOn2Dg(pn, Text[3]); + TMyString::sAddOnStr(".", Text[3]); + TMyString::sAddOn2Dg(nn, Text[3]); + pn = static_cast(DirectCtlBoard[i-48].fCurrent); + nn = static_cast(DirectCtlBoard[i-48].fCurrent * 100); + pn = pn %100; + nn = nn %100; + TMyString::sClear(Text[4]); + TMyString::sAddOn2Dg(pn, Text[4]); + TMyString::sAddOnStr(".", Text[4]); + TMyString::sAddOn2Dg(nn, Text[4]); + TextRender_string24(xv[0],aTop,aClr, "多线盘"); + TextRender_string24(xv[1],aTop,aClr, Text[1]); + TextRender_string24(xv[2],aTop,aClr, Text[2]); + TextRender_string24(xv[3],aTop,aClr, Text[3]); + TextRender_string24(xv[4],aTop,aClr, Text[4]); + pn = DirectCtlBoard[i-48].fData.DirectCtl.ResistedCount; + TMyString::sClear(Text[5]); + TMyString::sAddOn3Dg(pn, Text[5]); + TextRender_string24(xv[5],aTop,aClr, Text[5]); + pn = DirectCtlBoard[i-48].fData.DirectCtl.ResistedCount; + TMyString::sClear(Text[6]); + TMyString::sAddOn3Dg(pn, Text[6]); + TextRender_string24(xv[6],aTop,aClr, Text[6]); + }else{ + TMyString::sAddOn2Dg(aP0 + 48, Text[2]); + TMyString::sFromStr("无数据", Text[3]); + TextRender_string24(xv[0],aTop,aClr, "多线盘"); + TextRender_string24(xv[1],aTop,aClr, Text[1]); + TextRender_string24(xv[2],aTop,aClr, Text[2]); + TextRender_string24(xv[3],aTop,aClr, Text[3]); + } + } + aTop+=40; + times++; + } +} + + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TRootDevVoltage::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Updata; + unsigned char x,y,aCh; + Updata = 0; + + /*if( (aKey == VK_DELETE) || + (aKey == VK_0) || + (aKey == VK_1) || + (aKey == VK_2) || + (aKey == VK_3) || + (aKey == VK_4) || + (aKey == VK_5) || + (aKey == VK_6) || + (aKey == VK_7) || + (aKey == VK_8) || + (aKey == VK_9) + ){ + + }*/ + + if(aKey == VK_LEFT){ + + }else + if(aKey == VK_RIGHT){ + + }else + if(aKey == VK_UP){ + if(TopIndex>0){ + TopIndex--; + DrawItems(); + } + }else + if(aKey == VK_DOWN){ + if(TopIndex<60){ + TopIndex++; + DrawItems(); + } + }else + if(aKey == VK_TAB){ + + } + if(aKey == VK_EXECUTE){ + //Save Data Here + SendCmd(); + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + + return aMsg; +} + +void TRootDevVoltage::PanelCanvasOut() +{ + //TXBox::sDrawBoxBorder(RectPanel.Left + 8, RectPanel.Top + 3, RectPanel.Left + 362, RectPanel.Top + 150, "自定义命令", 8, 1, 0, clFrmFace); +} + +void TRootDevVoltage::InitPanel(void) +{ + int x,y,x2,y2, aW,aH,i; + x = RectPanel.Left; + y = RectPanel.Top; + x2 = RectPanel.Right; + y2 = RectPanel.Bottom; + aW = RectPanel.Width; + aH = RectPanel.Height; + + aPanel->Init(x,y,aW,aH,0,0,clFrmFace, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clFrmFace,clFrmFace); + aPanel->Caption.Text[0] = 0; + + aPanel->SText[0].Init(xs[0],10,80,30,0,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(xs[1],10,60,30,0,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(xs[2],10,60,30,0,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(xs[3],10,60,30,0,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(xs[4],10,60,30,0,y,clNearBlack,clFrmFace); + aPanel->SText[5].Init(xs[5],10,80,30,0,y,clNearBlack,clFrmFace); + aPanel->SText[6].Init(xs[6],10,80,30,0,y,clNearBlack,clFrmFace); + + TMyString::sFromStr(" 类型", aPanel->SText[0].Text); + TMyString::sFromStr("序号", aPanel->SText[1].Text); + TMyString::sFromStr("路径", aPanel->SText[2].Text); + TMyString::sFromStr("电压(V)", aPanel->SText[3].Text); + TMyString::sFromStr("电流(A)", aPanel->SText[4].Text); + TMyString::sFromStr("登记数", aPanel->SText[5].Text); + TMyString::sFromStr("在线数", aPanel->SText[6].Text); + + for(i=0; i<7;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[0].Visible = 1; + } + + aPanel->Btn[0].Init(430,290,120,36,x,y,1,clFrmFace); + aPanel->Btn[0].Caption.FromStr("强制更新"); + + for(i=0; i<1;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].Selected = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(10); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + aPanel->ReDrawItems(); + PanelCanvasOut(); + DrawItems(); +} + + +void TRootDevVoltage::SendCmd() +{ + TCanHeaderID aIde; + unsigned int Len,i; + Len = 4; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 1; + + //Path 0 + Data[2] = 127; + + //Cmd 1 + aIde.BitF.Cmd = dfCMD_UpdateVoltage; + + //Prm + Data[3] = 255; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + + + + + + + + diff --git a/MyCode/Gui/RootDevVoltage.h b/MyCode/Gui/RootDevVoltage.h new file mode 100644 index 0000000..27f0754 --- /dev/null +++ b/MyCode/Gui/RootDevVoltage.h @@ -0,0 +1,74 @@ +#ifndef ROOTDEVVOLTAGE_H_ +#define ROOTDEVVOLTAGE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TRootDevVoltage{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect VScrollBarBox; + + TRect Content; + TRect RectPanel; + + TMyString Str; + char Text[16][8]; + + unsigned int TopIndex; + + int IsFastCmd; + unsigned char Data[8]; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TRootDevVoltage(){}; + TRootDevVoltage(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void PanelCanvasOut(); + void DrawCaption2(void); + void DrawItems(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void SendCmd(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/RunModeCfg.cpp b/MyCode/Gui/RunModeCfg.cpp new file mode 100644 index 0000000..8031d49 --- /dev/null +++ b/MyCode/Gui/RunModeCfg.cpp @@ -0,0 +1,477 @@ +#include "RunModeCfg.h" +#include "Runtime.h" + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TRunModeCfg::Init() +{ + IsShow = 0; + Tag.Reset(); + SaveSta = 0; + IsPermission = 0; + + IsEnteringNewMode =0; + EnteringModeWhat =0; + + for(int i=0; i运行模式"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "工程名称"); + TextRender_string24(Lv.Grid.Left[0] + 520, Lv.Grid.Top[0] +8, clNearWhite, "运行时长:"); + TextDigitRender5Right24(Lv.Grid.Left[0] + 636, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun / 24); + TextRender_string24(Lv.Grid.Left[0] + 698, Lv.Grid.Top[0] +8, clNearWhite, "天"); + TextDigitRender2Right24(Lv.Grid.Left[0] + 722, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun % 24); + TextRender_string24(Lv.Grid.Left[0] + 746, Lv.Grid.Top[0] +8, clNearWhite, "小时"); + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +10, clNearWhite, "运行模式"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +50, clNearWhite, "正常运行"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +90, clNearWhite, "调试运行"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Project->Maintenance Reminder"); + TextRender_string24(Lv.Grid.Left[0] + 6, Lv.Grid.Top[0] +8, clNearWhite, "PrjName"); + TextRender_string24(Lv.Grid.Left[0] + 520, Lv.Grid.Top[0] +8, clNearWhite, "Duration:"); + TextDigitRender5Right24(Lv.Grid.Left[0] + 636, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun / 24); + TextRender_string24(Lv.Grid.Left[0] + 698, Lv.Grid.Top[0] +8, clNearWhite, "D"); + TextDigitRender2Right24(Lv.Grid.Left[0] + 722, Lv.Grid.Top[0] +8, clNearWhite, TimeSecHasRun % 24); + TextRender_string24(Lv.Grid.Left[0] + 746, Lv.Grid.Top[0] +8, clNearWhite, "Hour"); + + TextRender_string24(Lv.Grid.Left[1] + 6, Lv.Grid.Top[1] +10, clNearWhite, "Run Mode"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +50, clNearWhite, "Normal Run"); + TextRender_string24(Lv.Grid.Left[1] + 46, Lv.Grid.Top[1] +90, clNearWhite, "Test Mode "); + } + + + ShowIfNormal(); +} + +void TRunModeCfg::Show(void) +{ + IsShow =1; + RenderBackGround(); + DrawSelf(); +} + +void TRunModeCfg::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf();aPanel->ReDrawItems(); + Check4Selected(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + DrawSelf(); + aPanel->ReDrawItems(); + Check4Selected(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TRunModeCfg::PermissionCmdReturnDraw() +{ + RectFillRender(Lv.Grid.Left[2] + 200 -10, Lv.Grid.Top[2] + 40 -10, Lv.Grid.Left[2] + 200 -10 + 400 + 20, Lv.Grid.Top[2] + 40 -10 + 140 + 20, ContentColor); +} + +void TRunModeCfg::PermissionCmdGO() +{ + //for(int i=0; i<24; i++)DirectPadMode[i] = 0; + //DirectPadHasUpdata =0; + //RetryTimes =0; + //SpendSecond =0; + //IsEnteringNewMode =1; + //EnteringModeWhat =SettingState; + //SendNewMode(EnteringModeWhat); + //StateBarReflash(); + //ShowSta(2); + EnteringModeWhat =SettingState; + IsEnteringNewMode =0; + RunState = EnteringModeWhat; + if(IsSelfChecking == 0){ + StateBarReflash(); + if(IsShow){ + ShowSta(1); + } + } +} + +void TRunModeCfg::StartupSetRunMode() +{ + for(int i=0; i<24; i++)DirectPadMode[i] = 0; + DirectPadHasUpdata =0; + RetryTimes =0; + SpendSecond =0; + IsEnteringNewMode =1; + EnteringModeWhat = RunModeRun; + SendNewMode(EnteringModeWhat); +} + +//______________________________________________________________________________________________________________________________ +void TRunModeCfg::ClearSelected(void) +{ + unsigned int i; + for(i=1; i<8;i++)aPanel->Edit[i].Selected = 0; + if(Tag.Group == 0){ + switch(Tag.Inx0){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, 4, ItemColor); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, 4, ItemColor); + break; + default: + + break; + } + } +} + +void TRunModeCfg::Check4Selected(void) +{ + unsigned int i; + for(i=1; i<8;i++)aPanel->Edit[i].Selected = 0; + if(Tag.Group == 0){ + switch(Tag.Inx0){ + case 0: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 1: + TRoundSquare::sSelected(Lv.Grid.Left[1] +10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, 4, clNearWhite); + break; + default: + + break; + } + } +} + +void TRunModeCfg::ShowIfNormal() +{ + if(SettingState == RunModeAdjust){ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + }else{ + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 52, dWWidth, dWHeigh, dRoundR, dWdClr, 1); + TRoundSquare::sDrawBySize(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] + 92, dWWidth, dWHeigh, dRoundR, dWdDisabelClr, 0); + } +} + +void TRunModeCfg::ShowMth() +{ + +} + +void TRunModeCfg::ShowVision() +{ + +} + +void TRunModeCfg::ShowSound() +{ + +} + +void TRunModeCfg::ExtLoadData() +{ + +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TRunModeCfg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn MBoxMsg = guiMsgNone; + int iVal; + TGuiMsgReturn PmsRtnMsg; + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(Tag.Group == 0){ + if(Tag.Inx0 == 0){ + if(SettingState == RunModeAdjust) SettingState = RunModeRun; else SettingState = RunModeAdjust; + ShowIfNormal(); + }else + if(Tag.Inx0 == 1){ + if(SettingState == RunModeAdjust) SettingState = RunModeRun; else SettingState = RunModeAdjust; + ShowIfNormal(); + } + } + break; + case VK_UP: + if(Tag.Group == 0){ + ClearSelected(); + Tag.Inx0 =0; + Check4Selected(); + } + break; + case VK_DOWN: + if(Tag.Group == 0){ + ClearSelected(); + Tag.Inx0 =1; + Check4Selected(); + } + break; + case VK_F1: + if(Tag.Group == 0){ + if(Tag.Inx0 == 0){ + if(SettingState == RunModeAdjust) SettingState = RunModeRun; else SettingState = RunModeAdjust; + ShowIfNormal(); + }else + if(Tag.Inx0 == 1){ + if(SettingState == RunModeAdjust) SettingState = RunModeRun; else SettingState = RunModeAdjust; + ShowIfNormal(); + } + } + break; + case VK_EXECUTE: + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[2] + 200, Lv.Grid.Top[2] + 40, 400, 140, 3); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + if( (aKey != VK_EXECUTE) && (aKey != VK_RETURN) ){ + ShowSta(0); + } + } + + return aMsg; +} + +void TRunModeCfg::InitPanel(void) +{ + int i; + aPanel->Init(400,400,10,10,0,0,clFrmFace, bvRaised); + + aPanel->Edit[0].Init(Lv.Grid.Left[0] +104, Lv.Grid.Top[0] + 2, 400, 32, 0,0, 1,ItemColor); + + aPanel->Edit[1].Init(Lv.Grid.Left[1] +280, Lv.Grid.Top[1] + 86,46, 30, 0,0, 1,ItemColor); + + + for(i=0; i<1; i++){ + aPanel->Edit[i].IsShowCursor = 0; + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + } + for(i=1; i<2; i++){ + //aPanel->Edit[i].IsShowCursor = 1; + //aPanel->Edit[i].Enable = 1; + //aPanel->Edit[i].Visible = 1; + //aPanel->Edit[i].MaxLen = 2; + //aPanel->Edit[i].IsShowCursor = 1; + } +} + +void TRunModeCfg::LoadData() +{ + SettingState = RunState; + + for(int i=0; i<32; i++){ + aPanel->Edit[0].Str.Text[i] = PrjName[i]; + } + aPanel->Edit[0].Str.Text[32] = '\0'; + aPanel->Edit[0].Str.Text[33] = '\0'; + + //aPanel->Edit[1].Str.FromUInt2Dg(Setting.Hours); + + ShowIfNormal(); + aPanel->ReDrawItems(); + + Check4Selected(); +} + +void TRunModeCfg::WriteData() +{ + +} + +void TRunModeCfg::sRecoverSetDefault() +{ + +} + +void TRunModeCfg::ShowSta() +{ + if(IsShow == 0)return; + if(LanguageEnCn==0){ + if(SaveSta == 0){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, " "); + }else + if(SaveSta == 1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "设置成功 "); + }else + if(SaveSta == -1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "设置失败 "); + }else + if(SaveSta == 2){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "等待多线盘就绪"); + } + }else{ + if(SaveSta == 0){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, " "); + }else + if(SaveSta == 1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "Set Successful "); + }else + if(SaveSta == -1){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "Failed To Set "); + }else + if(SaveSta == 2){ + TextRender_string24(ResultSavePoint.x, ResultSavePoint.y, clNearWhite, ContentColor, "Wait for Direct Pad Board Ready"); + } + } +} + +void TRunModeCfg::SendNewMode(unsigned char aNewMode) +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + Len =4; + for(i=0; i<8; i++){ + CommData[i] = 0; + } + + CommData[0] = 0; + CommData[1] = MainCtl.fData.Split.MyNum; + CommData[2] = 0; + CommData[3] = 0; + + if(aNewMode == RunModeAdjust){ + aIde.BitF.Cmd = cmEnterAdjustMode; + }else{ + aIde.BitF.Cmd = cmExitAdjustMode; + } + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.Buf4GuiSend.Insert(aIde, CommData, Len); + + RunState = 0; +} + +void TRunModeCfg::GetInnerCanData(unsigned char aCmd, unsigned char aDirectPadNum) +{ + if(aCmd == cmEnterAdjustMode ){ + if((aDirectPadNum >= dADDR_DIRECTPAD_START) && (aDirectPadNum <= dADDR_DIRECTPAD_END)){ + RunModeCfg.DirectPadMode[aDirectPadNum - dADDR_DIRECTPAD_START] = RunModeAdjust; + DirectPadHasUpdata =1; + } + }else + if(aCmd == cmExitAdjustMode ){ + if((aDirectPadNum >= dADDR_DIRECTPAD_START) && (aDirectPadNum <= dADDR_DIRECTPAD_END)){ + RunModeCfg.DirectPadMode[aDirectPadNum - dADDR_DIRECTPAD_START] = RunModeRun; + DirectPadHasUpdata =1; + } + } +} + +void TRunModeCfg::Task1000Ms() +{ + /* + int NotEnterCount, i; + if(IsEnteringNewMode){ + DirectPadHasUpdata =0; + NotEnterCount = 0; + for(i=0; i 6){ + SpendSecond =0; + RetryTimes++; + if(RetryTimes > 10){ + IsEnteringNewMode =0; + }else{ + StartupSetRunMode(); + } + } + }*/ +} + +void TRunModeCfg::ShowSta(int aSta) +{ + SaveSta = aSta; + ShowSta(); +} + + + + + + diff --git a/MyCode/Gui/RunModeCfg.h b/MyCode/Gui/RunModeCfg.h new file mode 100644 index 0000000..9f591eb --- /dev/null +++ b/MyCode/Gui/RunModeCfg.h @@ -0,0 +1,140 @@ +#ifndef RUNMODECFG_H_ +#define RUNMODECFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TRunModeCfg{ + public: + static constexpr unsigned short hList[12] = {36,126,60,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[2] + 340, + .y = Lv.Grid.Top[2] + 132, + }; + static constexpr TPoint ResultSavePoint = { + .x = Lv.Grid.Left[2] + 40, + .y = Lv.Grid.Top[2] + 12, + }; + static const unsigned char RunModeUnknown = 0; + static const unsigned char RunModeRun = 1; + static const unsigned char RunModeAdjust = 2; + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + unsigned int IsShow; + TStaticText Caption; + + u32 Color; + + + TRect Bound; + TRect Content; + + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Dump0; + void Reset(){ + Group = 0; + Inx0 = 0; + Inx1 = 0; + } + }Tag; + unsigned char SettingState; + int SaveSta; + unsigned char IsPermission; + unsigned char DirectPadMode[24]; + unsigned char IsEnteringNewMode; + unsigned char EnteringModeWhat; + unsigned char DirectPadHasUpdata; + unsigned char RetryTimes; + unsigned char SpendSecond; + + unsigned char CommData[16]; + + public: + TRunModeCfg(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void FullRedraw(int Prm); + void ReDraw(void); + void ShowMth(); + void ShowVision(); + void ShowSound(); + void ShowIfNormal(); + + void ClearSelected(void); + void Check4Selected(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + + void ExtLoadData(); + void LoadData(); + void WriteData(); + static void sRecoverSetDefault(); + + void ShowSta(); + void ShowSta(int aSta); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + void SendNewMode(unsigned char aNewMode); + + void StartupSetRunMode(); + void GetInnerCanData(unsigned char aCmd, unsigned char aDirectPadNum); + + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm){ + IsShow = 0; + return 0; + } +}; + + + +#endif diff --git a/MyCode/Gui/ScreenLock.cpp b/MyCode/Gui/ScreenLock.cpp new file mode 100644 index 0000000..e69de29 diff --git a/MyCode/Gui/ScreenLock.h b/MyCode/Gui/ScreenLock.h new file mode 100644 index 0000000..573b909 --- /dev/null +++ b/MyCode/Gui/ScreenLock.h @@ -0,0 +1,10 @@ +#ifndef SCREENLOCK_H_ +#define SCREENLOCK_H_ + + + + +#endif + + + diff --git a/MyCode/Gui/ScreenSaveCfg.cpp b/MyCode/Gui/ScreenSaveCfg.cpp new file mode 100644 index 0000000..38dc73c --- /dev/null +++ b/MyCode/Gui/ScreenSaveCfg.cpp @@ -0,0 +1,368 @@ +#include "ScreenSaveCfg.h" +#include "Runtime.h" + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +void TScreenSaveCfg::DrawFixText() +{ + if(LanguageEnCn==0){ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "本机->屏保设置"); + TextRender_string24(Lv.Grid.Left[0] + 52, Lv.Grid.Top[0] +10, clNearWhite, "屏保设置"); + TextRender_string24(Lv.Grid.Left[0] + 52, Lv.Grid.Top[0] +10, clNearWhite, "屏保设置"); + TextRender_string24(Lv.Grid.Left[0] +52, Lv.Grid.Top[0] +50, clNearWhite, "启用屏保"); + TextRender_string24(Lv.Grid.Left[0] +52, Lv.Grid.Top[0] +90, clNearWhite, ItemColor, "屏保时间"); + TextRender_string24(Lv.Grid.Left[0] +200, Lv.Grid.Top[0] +90, clNearWhite, ItemColor, "分钟"); + TextRender_string24(Lv.Grid.Left[1] +52, Lv.Grid.Top[1] +10, clNearWhite, "火警状态时禁止屏保"); + TextRender_string24(Lv.Grid.Left[1] +52, Lv.Grid.Top[1] +50, clNearWhite, "监管状态时禁止屏保"); + TextRender_string24(Lv.Grid.Left[1] +52, Lv.Grid.Top[1] +90, clNearWhite, "故障状态时禁止屏保"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, "Local->Screen Safe Set"); + TextRender_string24(Lv.Grid.Left[0] + 52, Lv.Grid.Top[0] +10, clNearWhite, "Setting"); + TextRender_string24(Lv.Grid.Left[0] +52, Lv.Grid.Top[0] +50, clNearWhite, "Enable"); + TextRender_string24(Lv.Grid.Left[0] +52, Lv.Grid.Top[0] +90, clNearWhite, ItemColor, "Time "); + TextRender_string24(Lv.Grid.Left[0] +200, Lv.Grid.Top[0] +90, clNearWhite, ItemColor, "Minute"); + TextRender_string24(Lv.Grid.Left[1] +52, Lv.Grid.Top[1] +10, clNearWhite, "Disable Screen Saver In FireAlarm"); + TextRender_string24(Lv.Grid.Left[1] +52, Lv.Grid.Top[1] +50, clNearWhite, "Disable Screen Saver In Supervision"); + TextRender_string24(Lv.Grid.Left[1] +52, Lv.Grid.Top[1] +90, clNearWhite, "Disable Screen Saver In Fault"); + } +} + +void TScreenSaveCfg::Init() +{ + Tag.Group = 0; + Tag.Inx0 = 0; + Tag.Inx1 = 0; + + IsPermission =0; + + SaveResult = 0; +} + +void TScreenSaveCfg::RenderBackGround(void) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, ContentColor); +} + +void TScreenSaveCfg::RenderBackGround(unsigned int aClr) +{ + RectFillRender(ContentGeometry.Left, ContentGeometry.Top, ContentGeometry.Right, ContentGeometry.Bottom, aClr); +} + + +void TScreenSaveCfg::DrawSelf(void) +{ + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i0){ + Tag.Inx0--; + Check4Selected(); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 >0){ + Tag.Inx1--; + Check4Selected(); + }else{ + Tag.Group = 0; + Tag.Inx0 =1; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(Tag.Group == 0){ + if(Tag.Inx0 <1){ + Tag.Inx0++; + Check4Selected(); + }else{ + Tag.Group = 1; + Tag.Inx1 =0; + Check4Selected(); + } + }else + if(Tag.Group == 1){ + if(Tag.Inx1 <2){ + Tag.Inx1++; + Check4Selected(); + } + } + break; + case VK_F1: + if(Tag.Group == 0){ + if(Tag.Inx0 == 0){ + if(Setting.OnOff)Setting.OnOff = 0; + else Setting.OnOff =1; + } + }else + if(Tag.Group ==1){ + if(Tag.Inx1 == 0){ + if(Setting.PrvOnFire)Setting.PrvOnFire = 0; + else Setting.PrvOnFire =1; + }else + if(Tag.Inx1 == 1){ + if(Setting.PrvOnSv)Setting.PrvOnSv = 0; + else Setting.PrvOnSv =1; + }else + if(Tag.Inx1 == 2){ + if(Setting.PrvOnFault)Setting.PrvOnFault = 0; + else Setting.PrvOnFault =1; + } + } + ShowSetting(); + break; + case VK_EXECUTE: + if(SystemPermission > 1){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + PmsIntervene4Gui.Show4Gui(Lv.Grid.Left[0] + 200, Lv.Grid.Top[0] + 40, 400, 140, 2); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default: + break; + } + } + if(VK_EXECUTE != aKey){ + ShowSaveResult(0); + } + return aMsg; +} + +void TScreenSaveCfg::ShowSaveResult() +{ + char *tText; + if(SaveResult == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, " "); + }else + if(SaveResult < 0){ + if(LanguageEnCn==0)tText=" 保存失败 "; else tText="Failed To Save"; + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, tText); + }else{ + if(LanguageEnCn==0)tText=" 保存成功 "; else tText="Saved OK"; + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ContentColor, tText); + } +} + +void TScreenSaveCfg::ShowSaveResult(int aNewResult) +{ + SaveResult = aNewResult; + ShowSaveResult(); +} + +void TScreenSaveCfg::LoadData() +{ + Setting.OnOff = ScreenAndKeyLock.SaveOn; + Setting.Minute = ScreenAndKeyLock.SaveTime; + vEdit.Str.FromUInt2Dg(Setting.Minute); + if(ScreenAndKeyLock.IsKeyLock & 0x01) Setting.PrvOnFire = 1; else Setting.PrvOnFire = 0; + if(ScreenAndKeyLock.IsKeyLock & 0x02) Setting.PrvOnSv = 1; else Setting.PrvOnSv = 0; + if(ScreenAndKeyLock.IsKeyLock & 0x04) Setting.PrvOnFault = 1; else Setting.PrvOnFault = 0; +} + +void TScreenSaveCfg::SaveData() +{ + int iVal; + unsigned char tOnOff, SettingByte; + unsigned char tMinute; + if(Setting.OnOff)tOnOff = 1; else tOnOff = 0; + iVal = vEdit.Str.ToInteger(); + if(iVal > 20)iVal = 20; + if(iVal < 1)iVal = 1; + tMinute = iVal; + SettingByte = 0; + if(Setting.PrvOnFire) SettingByte |= 0x01; + if(Setting.PrvOnSv) SettingByte |= 0x02; + if(Setting.PrvOnFault) SettingByte |= 0x04; + + Record.OperateAdd_ScreenKeyLock(tOnOff, tMinute, SettingByte, "****"); + Record.WriteScreenKeyLock(tOnOff, tMinute, SettingByte, "****"); + + //Read Back + //Record.ReadScreenSave(); + if( (tOnOff == ScreenAndKeyLock.SaveOn) && (tMinute == ScreenAndKeyLock.SaveTime) && (SettingByte == ScreenAndKeyLock.IsKeyLock) ) { + ShowSaveResult(1); + }else{ + ShowSaveResult(-1); + ScreenAndKeyLock.SaveOn = tOnOff; + ScreenAndKeyLock.SaveTime = tMinute; + ScreenAndKeyLock.IsKeyLock = SettingByte; + } + //Redraw +} + +void TScreenSaveCfg::sRecoverSetDefault() +{ + Record.WriteScreenKeyLock(0, 20, 0, "****"); +} + + + + diff --git a/MyCode/Gui/ScreenSaveCfg.h b/MyCode/Gui/ScreenSaveCfg.h new file mode 100644 index 0000000..f233b54 --- /dev/null +++ b/MyCode/Gui/ScreenSaveCfg.h @@ -0,0 +1,112 @@ +#ifndef SCREENSAVECFG_H_ +#define SCREENSAVECFG_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TScreenSaveCfg{ + public: + static constexpr unsigned short hList[12] = {126,126,60,32, 32,32,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,800,800,800, 800,800,800,800, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +8), + .Grid.Top[1] = (36 + 32 +8) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + + .Grid.Bottom[0] = (36 + 32 +8) + hList[0], + .Grid.Bottom[1] = (36 + 32 +8) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +8) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + + .Grid.UsingCount = 2, + + .Panel.Active = 0, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint TipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 20, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 80, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[Lv.Grid.UsingCount -1] + 20, + .y = Lv.Grid.Bottom[Lv.Grid.UsingCount -1] + 10, + }; + public: + class TEdit vEdit; + + u32 Color; + + + + int SaveResult; + + struct{ + unsigned char OnOff; + unsigned char PrvOnFire; + unsigned char PrvOnSv; + unsigned char PrvOnFault; + unsigned int Minute; + }Setting; + + struct{ + unsigned char Group; + unsigned char Inx0; + unsigned char Inx1; + unsigned char Inx2; + }Tag; + + unsigned char IsPermission; + public: + TScreenSaveCfg(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawFixText(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void ShowSetting(); + + static void sRecoverSetDefault(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + unsigned int GetTextBkgColor(unsigned char aGroup, unsigned char aInx); + void Check4Selected(void); + + void LoadData(); + void SaveData(); + void ShowSaveResult(); + void ShowSaveResult(int aSta); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/SimRun.cpp b/MyCode/Gui/SimRun.cpp new file mode 100644 index 0000000..c546b22 --- /dev/null +++ b/MyCode/Gui/SimRun.cpp @@ -0,0 +1,746 @@ +#include "RuntimeData.h" +#include "SimRun.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define ipdWidth0 400 +#define ipdWidth1 390 + +const char tCmd_98[16] = "报警 "; +const char tCmd_99[16] = "报警取消 "; +const char tCmd_100[16] = "启动 "; +const char tCmd_101[16] = "停止 "; +const char tCmd_102[16] = "应答 "; +const char tCmd_103[16] = "停止应答 "; +const char tCmd_104[16] = "消火栓应答"; +const char tCmd_105[16] = "声光启动 "; +const char tCmd_106[16] = "声光停止 "; + + + +void TSimRun::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + SText.Init(Left+358,Top,434, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("模拟运行与操作-本机", Caption.Text); + Caption.Visible = 1; + + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + CtlIndex = 0; + FastIndex = 0; + OnActive = 0; + SelectedCmd = 0; + RunTick = 0; + + if(RunState == 0){ + IsReqAdjMode = 1; + }else{ + IsReqAdjMode = 0; + } + + IsOnShow = 1; + IsRunCmd =0; + + InitData(); +} + +void TSimRun::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TSimRun::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TSimRun::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + + +void TSimRun::DrawCaption2(void) +{ + //TMyString::sFromStr("TAB键在快捷命令与定义命令之间切换", SText.Text); + //SText.Show(); +} + +void TSimRun::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + + if(IsReqAdjMode){ + MessageBox.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + MessageBox.SetReturnValue(guiMsgNone, guiMsgOkAndReturn, guiMsgReturn,guiMsgNone); + MessageBox.SetBtnOkCancel(); + MessageBox.Show(); + MessageBox.ReqAdjMode(); + }else{ + InitPanel(); + } +} + +void TSimRun::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + DrawCaption2(); + + if(IsReqAdjMode){ + MessageBox.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + MessageBox.SetReturnValue(guiMsgNone, guiMsgOkAndReturn, guiMsgReturn,guiMsgNone); + MessageBox.SetBtnOkCancel(); + MessageBox.Show(); + MessageBox.ReqAdjMode(); + }else{ + aPanel->Show(); + } + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + + if(IsReqAdjMode){ + MessageBox.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + MessageBox.SetReturnValue(guiMsgNone, guiMsgOkAndReturn, guiMsgReturn,guiMsgNone); + MessageBox.SetBtnOkCancel(); + MessageBox.Show(); + MessageBox.ReqAdjMode(); + }else{ + aPanel->Show(); + } + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +//______________________________________________________________________________________________________________________________ + +void TSimRun::ShowType(void) +{ + int iVal; + unsigned char aType; + iVal = aPanel->Edit[4].Str.ToInteger(); + if(iVal > 255)iVal = 255; + aPanel->Edit[5].Str.FromStr(StrTypeShortName[iVal]); + aPanel->Edit[5].Show(); +} + +void TSimRun::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<5;i++)aPanel->Edit[i].Selected = 0; + for(i=0; i<11;i++)aPanel->Btn[i].Selected = 0; + if(1){ + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Edit[2].Selected = 1; + break; + case 3: + aPanel->Edit[3].Selected = 1; + break; + case 4: + aPanel->Edit[4].Selected = 1; + break; + case 5: + aPanel->Btn[0].Selected = 1; + break; + case 6: + aPanel->Btn[1].Selected = 1; + break; + case 7: + aPanel->Btn[2].Selected = 1; + break; + case 8: + aPanel->Btn[3].Selected = 1; + break; + case 9: + aPanel->Btn[4].Selected = 1; + break; + case 10: + aPanel->Btn[5].Selected = 1; + break; + case 11: + aPanel->Btn[6].Selected = 1; + break; + case 12: + aPanel->Btn[7].Selected = 1; + break; + case 13: + aPanel->Btn[8].Selected = 1; + break; + case 14: + aPanel->Btn[9].Selected = 1; + break; + case 15: + aPanel->Btn[10].Selected = 1; + break; + default: + + break; + } + } +} + + +void TSimRun::InitData() +{ + int i,x; + unsigned int aAddr; + Index =0; + for(i=0; i<64; i++){ + Text[i] =0; + } + aAddr = dAddrSdRam_CtrlInf; + for(i=0; i<10; i++){ + for(x=0; x<64; x++) + *(volatile unsigned char *)(aAddr + i*64 + x) =0; + } +} + +void TSimRun::FillTime(char *p) +{ + #define stRadix 16 + unsigned int d,e; + + d = DateTime.Time.Split.Hour /stRadix % 10; + e = DateTime.Time.Split.Hour % stRadix; + p[0] = d + '0'; + p[1] = e + '0'; + p[2] = ':'; + + d = DateTime.Time.Split.Minute /stRadix % 10; + e = DateTime.Time.Split.Minute % stRadix; + p[3] = d + '0'; + p[4] = e + '0'; + p[5] = ':'; + + d = DateTime.Time.Split.Second /stRadix % 10; + e = DateTime.Time.Split.Second % stRadix; + p[6] = d + '0'; + p[7] = e + '0'; + p[8] = ' '; + p[9] = 0; +} + +void TSimRun::InfInc(unsigned char aCmd, unsigned char aP0, unsigned char aP1, unsigned char aType) +{ + unsigned int aAddr,z; + aAddr = dAddrSdRam_CtrlInf + Index * 64; + if(1){ + FillTime(Text); + TMyString::sAddOn2Dg(aP0, Text); + TMyString::sAddOnStr("-", Text); + TMyString::sAddOn3Dg(SendingAddr, Text); + TMyString::sAddOnStr(" t", Text); + TMyString::sAddOn3Dg(SelectedType, Text); + TMyString::sAddOnStr(" ", Text); + if(aCmd == 98) + TMyString::sAddOnStr(tCmd_98,Text); + else if(aCmd == 99) + TMyString::sAddOnStr(tCmd_99,Text); + else if(aCmd == 100) + TMyString::sAddOnStr(tCmd_100,Text); + else if(aCmd == 101) + TMyString::sAddOnStr(tCmd_101,Text); + else if(aCmd == 102) + TMyString::sAddOnStr(tCmd_102,Text); + else if(aCmd == 103) + TMyString::sAddOnStr(tCmd_103,Text); + else if(aCmd == 104) + TMyString::sAddOnStr(tCmd_104,Text); + else if(aCmd == 105) + TMyString::sAddOnStr(tCmd_105,Text); + else if(aCmd == 106) + TMyString::sAddOnStr(tCmd_106,Text); + + TMyString::sFillFixLen(Text, 32); + TMyString::sBrokeFixLen(Text, 32); + for(z=0; z<41; z++){ + *(volatile unsigned char *)(aAddr + z) = Text[z]; + } + } + Index++; + if(Index>9)Index=0; +} + +void TSimRun::ReDrawInf() +{ + int i, z, aInx; + unsigned int aAddr; + aInx = Index; + for(i=0; i<10; i++){ + aAddr = dAddrSdRam_CtrlInf + aInx * 64; + for(z=0;z<64;z++){ + Text[z] = *(volatile unsigned char *)(aAddr + z); + } + TMyString::sFillFixLen(Text, 32); + TMyString::sBrokeFixLen(Text, 32); + TextDigitRender2_24(4, i*36 + 72, clNearWhite, Color, i +1); + TextRender_string24(40, i*36 + 72, clNearWhite, Color, Text); + aInx++; + if(aInx>9)aInx = 0; + } + +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TSimRun::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn MBoxMsg = guiMsgNone; + int iVal; + unsigned char Val; + unsigned char x,y,aCh; + + if(IsReqAdjMode){ + switch(aKey){ + case VK_LEFT: + MBoxMsg = MessageBox.KeyIn(aKey); + break; + case VK_RIGHT: + MBoxMsg = MessageBox.KeyIn(aKey); + break; + case VK_EXECUTE: + MBoxMsg = MessageBox.KeyIn(aKey); + if(MBoxMsg == guiMsgOkAndReturn){ + IsReqAdjMode = 0; + RunState = 1; + STextAdjust.SetText("调试",24); + STextAdjust.Color = clMedOrange; + STextAdjust.Show(); + Show(); + }else + if(MBoxMsg == guiMsgReturn){ + aMsg = guiMsgReturn; + } + break; + case VK_RETURN: + IsOnShow = 0; + aMsg = guiMsgReturn; + break; + } + return aMsg; + }else{ + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex < 5){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].ReDraw(); + if(CtlIndex == 4){ + ShowType(); + } + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <4){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + }else{ + if(CtlIndex <13){ + CtlIndex +=2; + if(CtlIndex > 14){ + CtlIndex = 14; + } + Check4Selected(); + aPanel->ReDrawItems(); + }else + if(CtlIndex < 14){ + CtlIndex = 14; + Check4Selected(); + aPanel->ReDrawItems(); + }else + if(CtlIndex < 15){ + CtlIndex = 15; + Check4Selected(); + aPanel->ReDrawItems(); + } + } + break; + case VK_TAB: + break; + case VK_EXECUTE: + //Save Data Here + if( (CtlIndex >4) && (CtlIndex<14) ){ + //98 cmVIrtualAlram 模拟报警 + //99 cmVIrtualAlramCancle 模拟报警测消 + //100 cmVIrtualStart 模拟启动 + //101 smVIrtualStop 模拟停止 + //102 cmVIrtualAck 模拟应答 + //103 cmVIrtualAckStop 模拟停止应答 + //104 cmVIrtualHydrantAck 模拟消火栓应答 + //105 cmVIrtualVaActive 模拟声光启动 + //106 cmVIrtualVaNotActive 模拟声光停止 + //aP0, aAStart, aAEnd, aType; + iVal = aPanel->Edit[0].Str.ToInteger(); + aP0 = static_cast(iVal); + iVal = aPanel->Edit[1].Str.ToInteger(); + aAStart = static_cast(iVal); + iVal = aPanel->Edit[2].Str.ToInteger(); + aAEnd = static_cast(iVal); + iVal = aPanel->Edit[3].Str.ToInteger(); + TickCount = static_cast(iVal); + iVal = aPanel->Edit[4].Str.ToInteger(); + SelectedType = static_cast(iVal); + + SendingAddr = aAStart; + switch (CtlIndex){ + case 5: SelectedCmd = 98; IsRunCmd = 1; RunTick = 250; break; + case 6: SelectedCmd = 99; IsRunCmd = 1; RunTick = 250; break; + case 7: SelectedCmd = 100; IsRunCmd = 1; RunTick = 250; break; + case 8: SelectedCmd = 101; IsRunCmd = 1; RunTick = 250; break; + case 9: SelectedCmd = 102; IsRunCmd = 1; RunTick = 250; break; + case 10: SelectedCmd = 103; IsRunCmd = 1; RunTick = 250; break; + case 11: SelectedCmd = 105; IsRunCmd = 1; RunTick = 250; break; + case 12: SelectedCmd = 106; IsRunCmd = 1; RunTick = 250; break; + case 13: SelectedCmd = 104; IsRunCmd = 1; RunTick = 250; break; + case 14: SelectedCmd = 0; IsRunCmd = 0; RunTick = 250; break; + } + }else + if(CtlIndex == 14){ + IsRunCmd = 0; + }else + if(CtlIndex == 15){ + IsRunCmd =0; + RunState = 0; + STextAdjust.SetText("运行",24); + STextAdjust.Color = clFrmFace; + STextAdjust.Show(); + + IsOnShow = 0; + aMsg = guiMsgReturn; + } + break; + case VK_RETURN: + IsRunCmd =0; + RunState = 0; + STextAdjust.SetText("运行",24); + STextAdjust.Color = clFrmFace; + STextAdjust.Show(); + + IsOnShow = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TSimRun::InitPanel(void) +{ + int x,y,x2,y2,i; + + y = y+6; + + aPanel->Init(450,72,346,360,0,0,clFrmFace, bvRaised); + aPanel->Caption.Init(451,73, 346-3 ,32,0,0,clFrmFace,clFrmFace); + + x = aPanel->Bound.Left; + y = aPanel->Bound.Top; + + aPanel->SText[0].Init(6,3,102,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(6,35,102,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(6,67,102,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(6,99,102,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("回路", aPanel->SText[0].Text); + TMyString::sFromStr("地址段", aPanel->SText[1].Text); + TMyString::sFromStr("间隔时间", aPanel->SText[2].Text); + TMyString::sFromStr("类型", aPanel->SText[3].Text); + + + for(i=0; i<4;i++){ + aPanel->SText[i].Enable = 1; + aPanel->SText[i].Visible = 1; + } + + aPanel->Edit[0].Init(112,3,48,30,x,y,1,clNearWhite); + aPanel->Edit[1].Init(112,35,48,30,x,y,1,clNearWhite); + aPanel->Edit[2].Init(166,35,48,30,x,y,1,clNearWhite); + aPanel->Edit[3].Init(112,67,48,30,x,y,1,clNearWhite); + aPanel->Edit[4].Init(112,99,48,30,x,y,1,clNearWhite); + aPanel->Edit[5].Init(166,99,176,30,x,y,1,clNearWhite); + + aPanel->Btn[0].Init(8, 140,156,30,x,y,1,clFrmFace); + aPanel->Btn[1].Init(178,140,156,30,x,y,1,clFrmFace); + aPanel->Btn[2].Init(8, 172,156,30,x,y,1,clFrmFace); + aPanel->Btn[3].Init(178,172,156,30,x,y,1,clFrmFace); + aPanel->Btn[4].Init(8, 204,156,30,x,y,1,clFrmFace); + aPanel->Btn[5].Init(178,204,156,30,x,y,1,clFrmFace); + aPanel->Btn[6].Init(8, 236,156,30,x,y,1,clFrmFace); + aPanel->Btn[7].Init(178,236,156,30,x,y,1,clFrmFace); + + aPanel->Btn[8].Init(8, 268,156,30,x,y,1,clFrmFace); + + aPanel->Btn[9].Init(8, 310,156,30,x,y,1,clFrmFace); + aPanel->Btn[10].Init(178,310,156,30,x,y,1,clFrmFace); + + aPanel->Btn[0].Caption.FromStr(" m报警 "); + aPanel->Btn[1].Caption.FromStr(" m报警取消 "); + + aPanel->Btn[2].Caption.FromStr(" m启动 "); + aPanel->Btn[3].Caption.FromStr(" m停止 "); + + aPanel->Btn[4].Caption.FromStr(" m应答 "); + aPanel->Btn[5].Caption.FromStr(" m停止应答 "); + + aPanel->Btn[6].Caption.FromStr(" m声光启动 "); + aPanel->Btn[7].Caption.FromStr(" m声光停止 "); + + aPanel->Btn[8].Caption.FromStr("m消火栓应答"); + + aPanel->Btn[9].Caption.FromStr("所有命令停止"); + + aPanel->Btn[10].Caption.FromStr("退出调试返回"); + + for(i=0; i<11;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + for(i=0; i<6;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("001"); + } + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[1].SetMaxLen(3); + aPanel->Edit[2].SetMaxLen(3); + aPanel->Edit[3].SetMaxLen(2); + aPanel->Edit[4].SetMaxLen(3); + aPanel->Edit[5].SetMaxLen(62); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[1].Pst = 2; + aPanel->Edit[2].Pst = 2; + aPanel->Edit[3].Pst = 1; + aPanel->Edit[4].Pst = 1; + aPanel->Edit[5].Pst = -1; + + aPanel->Edit[5].Enable = 0; + + aPanel->Btn[0].SetCaptionLeftSpacing(4); + aPanel->Btn[1].SetCaptionLeftSpacing(4); + aPanel->Btn[2].SetCaptionLeftSpacing(4); + aPanel->Btn[3].SetCaptionLeftSpacing(4); + aPanel->Btn[4].SetCaptionLeftSpacing(4); + aPanel->Btn[5].SetCaptionLeftSpacing(4); + aPanel->Btn[6].SetCaptionLeftSpacing(4); + aPanel->Btn[7].SetCaptionLeftSpacing(4); + aPanel->Btn[8].SetCaptionLeftSpacing(4); + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + ShowType(); +} + +void TSimRun::SendCmd() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len = aPanel->Edit[9].Str.ToInteger(); + if(Len >8)Len =8; + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + aIde.BitF.Cmd = cVal; + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + for(i=0; iEdit[i+1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[i] = cVal; + } + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TSimRun::SendFastCmd() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + if(FastIndex == 0){ + // 15 Start 手动启动 + aIde.BitF.Cmd = 15; + Len = 5; + }else + if(FastIndex == 1){ + // 16 Stop 手动停止 + aIde.BitF.Cmd = 16; + Len = 5; + }else + if(FastIndex == 2){ + // 18 自动启动 + aIde.BitF.Cmd = 18; + Len = 5; + }else + if(FastIndex == 3){ + // 19 自动停止 + aIde.BitF.Cmd = 19; + Len = 5; + }else + if(FastIndex == 4){ + // 25 声光启动 + aIde.BitF.Cmd = 25; + Len = 3; + }else + if(FastIndex == 5){ + // 26 声光停止 + aIde.BitF.Cmd = 26; + Len = 2; + } + + for(i=0; i<8; i++){ + Data[i] = 0; + } + + for(i=0; iEdit[i+1].Str.ToInteger(); + if(iVal>255)iVal=255; + cVal = iVal; + Data[i] = cVal; + } + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TSimRun::Task1000Ms() +{ + if(IsOnShow){ + if(IsRunCmd){ + RunTick++; + if(RunTick >= TickCount){ + RunTick = 0; + if( (SendingAddr < aAStart) || (SendingAddr > aAEnd) ){ + SendingAddr = aAStart; + } + InfInc(SelectedCmd, aP0, SendingAddr, SelectedType); + ReDrawInf(); + } + } + } +} + +int TSimRun::ExtRequst(unsigned char Prm) +{ + IsOnShow =0; + IsRunCmd =0; + RunState = 0; + STextAdjust.SetText("运行",24); + STextAdjust.Color = clFrmFace; + STextAdjust.Show(); + return 0; +} + + + + + + diff --git a/MyCode/Gui/SimRun.h b/MyCode/Gui/SimRun.h new file mode 100644 index 0000000..3886f0e --- /dev/null +++ b/MyCode/Gui/SimRun.h @@ -0,0 +1,98 @@ +#ifndef SIMRUN_H_ +#define SIMRUN_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TSimRun{ + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TRect Bound; + TRect VScrollBarBox; + + TRect Content; + TRect RectPanel; + + TMyString Str; + + unsigned int CtlIndex; + unsigned int FastIndex; + + int IsReqAdjMode; + int Index; + unsigned char Data[8]; + unsigned char SelectedType; + unsigned char SelectedCmd; + int IsOnShow; + int IsRunCmd; + unsigned char RunTick; + unsigned char SendingAddr; + + char tText[12]; + char Text[64]; + + unsigned char aP0, aAStart, aAEnd ,TickCount; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TSimRun(){}; + TSimRun(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawCaption2(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + void ShowType(void); + + void Check4Selected(void); + + void SendCmd(); + void SendFastCmd(); + + void InitData(); + void FillTime(char *p); + void InfInc(unsigned char aCmd, unsigned char aP0, unsigned char aP1, unsigned char aType); + void ReDrawInf(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + +#endif + diff --git a/MyCode/Gui/SlaveRegByRemote.cpp b/MyCode/Gui/SlaveRegByRemote.cpp new file mode 100644 index 0000000..4ae44d3 --- /dev/null +++ b/MyCode/Gui/SlaveRegByRemote.cpp @@ -0,0 +1,124 @@ +#include "SlaveRegByRemote.h" +#include "gType.h" +#include "gvalue.h" +#include "ProtoC2C.h" +#include "Runtime.h" +#include "Gui.h" + +extern "C"{ + #include "user_norflash.h" + //#include "user_eeprom.h" + #include "fdcan_task.h" + #include "uart_key_drv.h" +} + +void TSlaveRegByRemote::Init() +{ + IsShow = 0; +} + +void TSlaveRegByRemote::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick62)len = 62; + for(i=0; i62)len = 62; + for(i=0; i0) + RectRender(Bound.Left,Bound.Top,Bound.Right,Bound.Bottom, Border.Width, Border.Color); + + if(Enable){ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); + }else{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); + } +} + +void TStaticText::TextDraw(void) +{ + int aVal, tclr; + if(Enable){ + tclr = TextColor; + }else{ + tclr = clSilver; + } + + aVal = GetFontHeight(FontSize); + TextTop = Content.Top + (Content.Height - aVal) / 2; + aVal = Content.Left + TextLeftSpacing; + + if(FontSize == 16){ + TextRender_string24(aVal, TextTop, tclr, Color, Text); + }else + if(FontSize == 24){ + TextRender_string24(aVal, TextTop, tclr, Color, Text); + }else{ + TextRender_string24(aVal, TextTop, tclr, Color, Text); + } +} + +void TStaticText::FullRedraw(void) +{ + SelfDraw(); + TextDraw(); +} + +void TStaticText::Show(void) +{ + Visible = 1; + SelfDraw(); + TextDraw(); +} + +void TStaticText::sShow(int aX, int aY, int aR, int aB, unsigned int aTc, char *Text) +{ + TextRender_string24(aX +4, aY+2, aTc, Text); +} + +void TStaticText::sShow(int aX, int aY, int aR, int aB, unsigned int aTc, unsigned int aBc, char *Text) +{ + RectFillRender(aX, aY, aR, aB, aBc); + TextRender_string24(aX +4, aY+2, aTc, Text); +} + +void TStaticText::sDrawDump(int aX, int aY, int aR, int aB, unsigned int aBc) +{ + RectFillRender(aX, aY, aR, aB, aBc); +} + + + + + + + + diff --git a/MyCode/Gui/StaticText.h b/MyCode/Gui/StaticText.h new file mode 100644 index 0000000..0f9223a --- /dev/null +++ b/MyCode/Gui/StaticText.h @@ -0,0 +1,78 @@ +#ifndef STATICTEXT_H_ +#define STATICTEXT_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +//#include "stdio.h" +//#include "stdlib.h" +//#include "string.h" +#include "my_string.h" + +class TStaticText{ + private: + u16 TextTop; + u16 TextLeftSpacing; + public: + struct{ + int Width; + unsigned int Color; + }Border; + char Text[64]; + int FontSize; + int DrawMode; //dmRaised=1 dmLowered=-1 dmNone=0 + unsigned int Color; + unsigned int TextBGRColor; + unsigned int TextColor; + unsigned int Enable; + unsigned int Visible; + int TabOrder; + + TRect Bound; + TPoint OwnerLeftTop; //Parrent Left Top; + TRect Content; + + unsigned int Selected; + public: + TStaticText(){}; + TStaticText(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY,unsigned int aTextColor, unsigned int aBgColor){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aTextColor, aBgColor); + }; + void Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, unsigned int aTextColor, unsigned int aBgColor); + void SetText(const char *p, int aFontSize); + void SetText( char *cr, int aFontSize); + void SetTextLeftSpacing(unsigned int spc); + void SetEnable(void); + void SetDisable(void); + void TextClear(void); + void SelfDraw(void); + void TextDraw(void); + void FullRedraw(void); + void Show(void); + static void sShow(int aX, int aY, int aW, int aH, unsigned int aTc, char *Text); + static void sShow(int aX, int aY, int aW, int aH, unsigned int aTc, unsigned int aBc, char *Text); + static void sDrawDump(int aX, int aY, int aR, int aB, unsigned int aBc); +}; + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/TAuthorizeState.cpp b/MyCode/Gui/TAuthorizeState.cpp new file mode 100644 index 0000000..2be97c5 --- /dev/null +++ b/MyCode/Gui/TAuthorizeState.cpp @@ -0,0 +1,119 @@ +#include "TAuthorizeState.h" + +void TAuthorizeState::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("授权状态-本机", Caption.Text); + Caption.Visible = 1; + + OnActive = 0; + +} + +void TAuthorizeState::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TAuthorizeState::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TAuthorizeState::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + +void TAuthorizeState::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + ReDrawInf(); +} + +void TAuthorizeState::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + ReDrawInf(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + ReDrawInf(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +//______________________________________________________________________________________________________________________________ + +void TAuthorizeState::ReDrawInf() +{ + TextRender_string24(40, 86, clNearBlack, "型号: FA001"); + TextRender_string24(40, 110, clNearBlack, "授权形式:"); + + TextRender_string24(100, 144, clNearBlack, "授权到期日期:"); + TextRender_string24(100, 178, clNearBlack, "授权最大回路数量:"); + + TextRender_string24(100, 212, clNearBlack, "授权最大终端数量:"); +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TAuthorizeState::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + + switch(aKey){ + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + + return aMsg; +} + diff --git a/MyCode/Gui/TAuthorizeState.h b/MyCode/Gui/TAuthorizeState.h new file mode 100644 index 0000000..f9909c7 --- /dev/null +++ b/MyCode/Gui/TAuthorizeState.h @@ -0,0 +1,51 @@ +#ifndef TAUTHORIZESTATE_H_ +#define TAUTHORIZESTATE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TAuthorizeState{ + public: + unsigned int OnActive; + public: + TStaticText Caption; + + u32 Color; + + int TabOrder; + TRect Bound; + TRect Content; + public: + TAuthorizeState(){}; + TAuthorizeState(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void FullRedraw(int Prm); + void ReDraw(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void LoadData(); + void ReDrawInf(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/TButton.cpp b/MyCode/Gui/TButton.cpp new file mode 100644 index 0000000..35a3774 --- /dev/null +++ b/MyCode/Gui/TButton.cpp @@ -0,0 +1,145 @@ +#include "TButton.h" + +#include "stdio.h" +#include "stdlib.h" +#include "string.h" + +#include "gType.h" +#include "GraphLow.h" + +void TButton::Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aBorderWidth, u32 aBorderColor) +{ + unsigned short Left,Right,Top,Bottom; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + OwnerLeftTop.x = OwnerX; + OwnerLeftTop.y = OwnerY; + Border.Width = aBorderWidth; + Border.Color = aBorderColor; + + Left = Bound.Left + 2; + Right = Bound.Right - 2; + Top = Bound.Top + 2; + Bottom = Bound.Bottom - 2; + + Content.Set(Left,Top,Right,Bottom); + + Color = clNearWhite; + TextColor = clNearBlack; + + SelectedColor = clAqua; + SelectedTextColor = clNearBlack; + + DisableColor = clFrmFace; + DisableTextColor = clSilver; + + SetCaption("Button xx", 24); + + Enable = true; + Selected =0; +} + + +void TButton::SetCaption(const char *p, unsigned int aFontSize) +{ + s16 len, i; + s16 PixelWidth; + + len = sizeof(p); + if(len>30)len = 30; + Caption.FromStr(p); + FontSize = aFontSize; + PixelWidth = GetFontWidth(aFontSize); + if( (aFontSize==16) || (aFontSize == 24) ) PixelWidth = PixelWidth * len; + CaptionLeftSpacing = (Bound.Width-PixelWidth) / 2; +} + +void TButton::SetColor(unsigned int aClr) +{ + Color = aClr; +} + +void TButton::SetTextColor(unsigned int aClr) +{ + TextColor = aClr; +} + +void TButton::SetCaptionLeftSpacing(u16 spc) +{ + CaptionLeftSpacing = spc; +} + +void TButton::Draw(void) +{ + VertLineRender(Bound.Left+1, Bound.Top+1, Bound.Height-2, 0xFF808080); + VertLineRender(Bound.Right-1, Bound.Top+1, Bound.Height-2, 0xFF808080); + VertLineRender(Bound.Left, Bound.Top, Bound.Height, 0xFF000000); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left+1, Bound.Top+1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left+1, Bound.Bottom-1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width, 0xFF000000); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF000000); + + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); + TextRender_string24(Content.Left + 1 + CaptionLeftSpacing , Content.Top + 2, TextColor, Caption.Text); +} + +void TButton::Draw2(void) +{ + if(Enable){ + if(Selected) + RectFillRender(Bound.Left, Bound.Top, Bound.Right, Bound.Bottom, SelectedColor); + else + RectFillRender(Bound.Left, Bound.Top, Bound.Right, Bound.Bottom, Color); + }else{ + RectFillRender(Bound.Left, Bound.Top, Bound.Right, Bound.Bottom, DisableColor); + } + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + if(Enable){ + if(Selected) + TextRender_string24( (Content.Left + 1 + CaptionLeftSpacing) , (Content.Top + 2) , SelectedTextColor, Caption.Text); + else + TextRender_string24( (Content.Left + 1 + CaptionLeftSpacing) , (Content.Top + 2) , TextColor, Caption.Text); + }else{ + TextRender_string24( (Content.Left + 1 + CaptionLeftSpacing) , (Content.Top + 2) , DisableTextColor, Caption.Text); + } + +} + +void TButton::DrawInPress(void) +{ + if(Selected) + RectFillRender(Bound.Left, Bound.Top, Bound.Right, Bound.Bottom, SelectedColor); + else + RectFillRender(Bound.Left, Bound.Top, Bound.Right, Bound.Bottom, Color); + + VertLineRender(Bound.Left+1, Bound.Top+1, Bound.Height-2, 0xFF808080); + VertLineRender(Bound.Right-1, Bound.Top+1, Bound.Height-2, 0xFF808080); + VertLineRender(Bound.Left, Bound.Top, Bound.Height, 0xFF000000); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF000000); + + HorizLineRender(Bound.Left+1, Bound.Top+1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left+1, Bound.Bottom-1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width, 0xFF000000); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF000000); + + if(Selected) + TextRender_string24( (Content.Left + 1 + CaptionLeftSpacing) , (Content.Top + 2) , SelectedTextColor, Caption.Text); + else + TextRender_string24( (Content.Left + 1 + CaptionLeftSpacing) , (Content.Top + 2) , TextColor, Caption.Text); +} + +void TButton::Show(void) +{ + Draw2(); +} + + diff --git a/MyCode/Gui/TButton.h b/MyCode/Gui/TButton.h new file mode 100644 index 0000000..6441fbb --- /dev/null +++ b/MyCode/Gui/TButton.h @@ -0,0 +1,56 @@ +#ifndef TBUTTON_H_ +#define TBUTTON_H_ + +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" + +class TButton{ + private: + struct{ + unsigned int Width; + unsigned int Color; + }Border; + u16 CaptionLeftSpacing; + public: + bool Enable; + TMyString Caption; + int FontSize; + TRect Bound; + int DrawMode; //dmRaised=1 dmLowered=-1 dmNone=0 + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + u32 DisableColor; + u32 DisableTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Content; + unsigned int Visible; + unsigned int Selected; + public: + TButton(){}; + TButton(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aBorderWidth, u32 aBorderColor){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aBorderWidth, aBorderColor); + }; + void Init(int aX, int aY, int aW, int aH, int OwnerX, int OwnerY, u32 aBorderWidth, u32 aBorderColor); + void SetCaption( char *p, unsigned int aFontSize); + void SetCaption(const char *p, unsigned int aFontSize); + void SetColor(unsigned int aClr); + void SetTextColor(unsigned int aClr); + void SetCaptionLeftSpacing(u16 spc); + void Draw(void); + void Draw2(void); + void DrawInPress(void); + void Show(void); +}; + +#endif + + diff --git a/MyCode/Gui/TEdit.cpp b/MyCode/Gui/TEdit.cpp new file mode 100644 index 0000000..35afb19 --- /dev/null +++ b/MyCode/Gui/TEdit.cpp @@ -0,0 +1,304 @@ + +#include "gType.h" +#include"GraphLow.h" +#include"TEdit.h" + +const static unsigned char CharStart = '*'; + + +void TEdit::Init(u16 aX, u16 aY, u16 aW, u16 aH, u16 OwnerX, u16 OwnerY, u32 aBorderWidth, u32 aBorderColor) +{ + unsigned short Left,Right,Top,Bottom, aBW; + aBW = aBorderWidth; + aBW = 2; + Bound.SetBySize(aX+OwnerX, aY+OwnerY, aW, aH); + OwnerLeftTop.x = OwnerX; + OwnerLeftTop.y = OwnerY; + Border.Width = aBW; + Border.Color = aBorderColor; + + Left = Bound.Left + aBW; + Right = Bound.Right - aBW; + Top = Bound.Top + aBW; + Bottom = Bound.Bottom - aBW; + + Content.Set(Left,Top,Right,Bottom); + Index = 0; + + Color = clNearWhite; + TextColor = clNearBlack; + SelectedColor = clBlue; + SelectedTextColor = clNearWhite; + + SetText("Edit xx", 24); + + FontSize = 24; + Enable = true; + FlickDominance = true; + FlickTick = 0; + Pst = -1; + IsShowCursor = 1; + MaxLen = 60; + + CursorMode =0; + MaskMode =0; + Selected = 0; +} + +void TEdit::SetText(char *p, int aFontSize) +{ + Str.FromStr(p); + FontSize = aFontSize; +} + +void TEdit::SetText(const char *p, int aFontSize) +{ + Str.FromStr(p); + FontSize = aFontSize; +} + +void TEdit::TextClear(void) +{ + Str.Text[0]=0; + Str.Text[1]=0; + Pst = -1; + ReDraw(); +} + +void TEdit::SelfDraw(void) +{ + if (Border.Width>0){ + VertLineRender(Bound.Left, Bound.Top, Bound.Height-1, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Top, Bound.Width-1, 0xFF808080); + + VertLineRender(Bound.Left+1, Bound.Top+1, Bound.Height-2, 0xFF404040); + HorizLineRender(Bound.Left+1, Bound.Top+1, Bound.Width-2, 0xFF404040); + + VertLineRender(Bound.Right-1, Bound.Top+1, Bound.Height-2, 0xFFD4D0C8); + HorizLineRender(Bound.Left+1, Bound.Bottom-1, Bound.Width-2, 0xFFD4D0C8); + + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFFFFFFFF); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFFFFFFFF); + } + + ReDraw(); +} + +void TEdit::CorrectPst() +{ + int aLen = Str.GetEndPst(); + if(Pst > aLen) Pst = aLen; +} + +void TEdit::ShowCursor(void) +{ + unsigned int aPst; + aPst = (Pst + 1) * 12 +1; + VertLineRender(Content.Left + aPst, Bound.Top+2, Bound.Height-3, SelectedTextColor); +} + +void TEdit::ShowCursor(unsigned int aClr) +{ + unsigned int aPst; + aPst = (Pst + 1) * 12 +1; + VertLineRender(Content.Left + aPst, Bound.Top+2, Bound.Height-3, aClr); +} + +void TEdit::ReDraw(void) +{ + int Len,i; + if(FontSize == 16){ + + }else{ + if(Enable){ + if(Selected){ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, SelectedColor); + if(MaskMode == CharStart){ + Len = Str.GetLength(); + for(i=0; i 0){ + PrvCharType = 0; + const int tPst = Str.GetEndPst(); + if(Pst > tPst)Pst = tPst; + for(i=0; i<=Pst; i++){ + if(Str.Text[i] & 0x80){ + PrvCharType = 1; + i++; + }else{ + PrvCharType = 0; + } + } + if( PrvCharType == 0){ + //this is AscII + Pst--; + }else{ + Pst -=2; + } + }else + if(Pst >-1){ + Pst--; + } + break; + case VK_RIGHT: + aEp = Str.GetEndPst(); + if(Pst < (aEp)){ + if( (Str.Text[Pst+1] & 0x80) == 0){ + //this is AscII + Pst++; + }else{ + if((Pst+2)>aEp){ + Str.Text[Pst] = 0; + Pst --; + }else{ + Pst +=2; + } + } + }else{ + Pst = aEp; + } + break; + } + + if(InputMethod == EN){ + if( (aKey >= VK_0) && (aKey <= VK_9) ){ + if(aKey == VK_0)Str.Insert("0",Pst); + if(aKey == VK_1)Str.Insert("1",Pst); + if(aKey == VK_2)Str.Insert("2",Pst); + if(aKey == VK_3)Str.Insert("3",Pst); + if(aKey == VK_4)Str.Insert("4",Pst); + if(aKey == VK_5)Str.Insert("5",Pst); + if(aKey == VK_6)Str.Insert("6",Pst); + if(aKey == VK_7)Str.Insert("7",Pst); + if(aKey == VK_8)Str.Insert("8",Pst); + if(aKey == VK_9)Str.Insert("9",Pst); + Pst++; + } + if(aKey == VK_DECIMAL){Str.Insert("*",Pst); Pst++;} + if(aKey == VK_OEM_2){Str.Insert("#",Pst);Pst++;} + }else + if(InputMethod == CN){ + + }else{ + InputMethod = EN; + } + Str.Text[MaxLen] = 0; + if(Pst >= MaxLen)Pst = MaxLen -1; +} + +void TEdit::OnTime100mS(void) +{ + FlickTick++; + if(FlickTick>4){ + FlickTick = 0; + if(FlickDominance){ + FlickDominance = false; + }else{ + FlickDominance = true; + } + } +} + +void TEdit::SetMaxLen(unsigned int aLen) +{ + if(aLen > 60){ + MaxLen = 60; + }else{ + MaxLen = aLen; + } +} + +void TEdit::SetInputMaskEn(void) +{ + InputMethod = EN; +} + +void TEdit::SetInputCN(void) +{ + InputMethod = CN; +} + +void TEdit::SetPstTail(void) +{ + Pst = Str.GetEndPst(); +} + +void TEdit::sDrawSelf(int x, int y, int w, int h, unsigned int aClr) +{ + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender(x, y, w-1, 0xFF808080); + + VertLineRender( x+1, y+1, h-2, 0xFF404040); + HorizLineRender(x+1, y+1, w-2, 0xFF404040); + + VertLineRender(x+w-1-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender(x+1, y+h-1-1, w-2, 0xFFD4D0C8); + + VertLineRender(x+w-1, y, h, 0xFFFFFFFF); + HorizLineRender(x, y+h-1, w, 0xFFFFFFFF); + + RectFillRender(x+2, y+2, x+w-3, y+h-3, aClr); + +} + + diff --git a/MyCode/Gui/TEdit.h b/MyCode/Gui/TEdit.h new file mode 100644 index 0000000..d995c1c --- /dev/null +++ b/MyCode/Gui/TEdit.h @@ -0,0 +1,83 @@ +#ifndef TEDIT_H_ +#define TEDIT_H_ + +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" + + +class TEdit{ + private: + struct{ + unsigned int Width; + unsigned int Color; + }Border; + public: + TMyString Str; + bool Enable; + int FontSize; + int DrawMode; //dmRaised=1 dmLowered=-1 dmNone=0 + unsigned int Color; + unsigned int TextColor; + unsigned int Index; + unsigned int Edit; + int TabOrder; + + int Selected; + unsigned int SelectedColor; + unsigned int SelectedTextColor; + + TPoint OwnerLeftTop; //Parrent Left Top; + TRect Bound; + TRect Content; + + int Pst; + int MaxLen; + bool FlickDominance; + unsigned int FlickTick; + TInputMethod InputMethod; + unsigned int Visible; + unsigned char IsShowCursor; + + unsigned char CursorMode; + unsigned char MaskMode; + public: + TEdit(void){}; + TEdit(u16 aX, u16 aY, u16 aW, u16 aH, u16 OwnerX, u16 OwnerY, u32 aBorderWidth, u32 aBorderColor){ + Init(aX, aY, aW, aH, OwnerX, OwnerY, aBorderWidth, aBorderColor); + } + void Init(u16 aX, u16 aY, u16 aW, u16 aH, u16 OwnerX, u16 OwnerY, u32 aBorderWidth, u32 aBorderColor); + void SetText(char *p, int aFontSize); + void SetText(const char *p, int aFontSize); + void SelfDraw(void); + void TextClear(void); + + void SetSelect(void); + void SetDeSelect(void); + void ShowCursor(void); + void ShowCursor(unsigned int aClr); + void ReDraw(void); + void Show(void); + + void KeyIn(unsigned char aKey); + + void OnTime100mS(void); + void SetMaxLen(unsigned int aLen); + + void SetInputMaskEn(void); + void SetInputCN(void); + void CorrectPst(); + + void SetPstTail(void); + + void SetTextShowMaskNone(){MaskMode = 0;} + void SetTextShowMaskByAsterisk(){MaskMode = '*';} + + static void sDrawSelf(int x, int y, int x2, int y2, unsigned int aClr); +}; + +#endif + diff --git a/MyCode/Gui/TMenu.cpp b/MyCode/Gui/TMenu.cpp new file mode 100644 index 0000000..38b0175 --- /dev/null +++ b/MyCode/Gui/TMenu.cpp @@ -0,0 +1,1659 @@ +#include "TMenu.h" +#include "gvalue.h" +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "GlobalString.h" +#include "ImageData.h" + +#define Icon16_Up 1 +#define Icon16_Down 2 + +#define MainShowFont 24 + +#define SubShowFont 24 + +#define SubShowHeight 32 + +#define SubTextLeft 24 + +static const unsigned char SavePassWord[32] = "9910232250266023\0"; + +/* + +const char StrMainMenuName[28] = {"系统设置"}; + +const char StrMainMenu[8][20] = { + "设备注册", + "设备定义", + "联动公式", + "网络设置", + "工作模式", + "密码设置", + "其他设置", + "清除故障从机" +}; + +const char StrSubMenuItem[48][40] = { + //0 + "设备追加注册", + "全部更新注册", + "板卡更新注册", + "手动增加设备", + "手动减少设备", + + //5 + "总线设备定义", + "手动盘定义", + "多线盘定义", + "广播/电话盘定义", + "联网控制器定义", + "自定义设备类型", + "回路注释定义", + "工程名称", + + //13 + "新建联动公式", + "修改联动公式", + "删除联动公式", + + //16 + "本机地址设置", + "通讯板设置", + + //18 + "调试模式设置", + "广播同步设置", + "预警功能设置", + "火警输出设置", + "接地检查设置", + "显示盘静音设置", + "控制器静音设置", + "声光报警器反馈设置", + + //26 + "权限I级密码设置", + "权限II级密码设置", + "权限III级密码设置", + "权限IV级密码设置-最高", + "气体密码设置", + + //31 + "定点调试", + "数字化设备调试", + "修改设备编码", + "重码检测", + "探测器污染补偿", + "探测器清洗修正", + "REV0", + "REV1", + "REV2", + "REV3" + + //41 +}; +*/ + + + +const char StrMainMenuName[28] = {"系统设置"}; + + +const char StrMainMenu[12][36]={ + //"1.操作权限登录", + "1.本机", + "2.历史事件", + "3.工程", + "4.回路", + "5.手动控制盘", + "6.联动", + "7.局域网", + "8.数据传输", + "9.高级设计", + "*,--------", + "*,--------" +}; + +const char StrMainMenuEn[12][36]={ + //"1.操作权限登录", + "1.Local Machine", + "2.Histroy Message", + "3.Project", + "4.Loop", + "5.App Keypad Boards", + "6.Linkage", + "7.LAN", + "8.Data Transfer", + "9.Data Setting", + "*,--------", + "*,--------" +}; + +//const xxxx MenuActionList_0[4] ={ActLoginII, ActLoginIII, ActLoginIV, Null0}; +//const char StrSubMenu_0 [SubItemCount_0] [32]={ + //"权限登录", 1111_ 1=allow 0=NotAllow S=BySet +// "1110_1.II级权限登录", +// "1110_2.III级权限登录", +// "1110_3.退出登录", +//}; + +//const xxxx MenuActionList_1[12] ={ActQueDevice, ActQueRegAddr, ActQueMaskDevice, ActQueConfig, ActQueInterLink, ActQueInterLink4Pad, ActQueNetwork, Null1}; +const char StrSubMenu_0 [SubItemCount_0] [SubItemTextLen]={ + //"查询信息", 1111_ 1=allow 0=NotAllow S=BySet + /*"S110_1.注册信息", + "S110_2.设备状态", + "S110_3.屏蔽部件", + "S110_4.注释信息", + "S110_5.本机配置", + "S110_6.网络配置", + "S110_7.联动编程", + "S110_8.总线盘编程", + "S110_9.多线盘配置信息",*/ + + "1110_1.硬件", + "1110_2.电源", + "1110_3.打印机", + "0110_4.日期时间", + "1110_5.密码", + "1110_6.屏保", + "1110_7.语言/Language" +}; + +const char StrSubMenu_0_En [SubItemCount_0] [SubItemTextLen]={ + //"查询信息", 1111_ 1=allow 0=NotAllow S=BySet + /*"S110_1.注册信息", + "S110_2.设备状态", + "S110_3.屏蔽部件", + "S110_4.注释信息", + "S110_5.本机配置", + "S110_6.网络配置", + "S110_7.联动编程", + "S110_8.总线盘编程", + "S110_9.多线盘配置信息",*/ + + "1110_1.Hardware", + "1110_2.Power Suppy Info", + "1110_3.Printer", + "0110_4.Date and time", + "1110_5.Password", + "1110_6.Screen Saver", + "1110_7.Language/语言" +}; + +//const xxxx MenuActionList_2[12] ={ActQueMsgAll, ActQueMsgAlarm, ActQueMsgInterLink, ActQueMsgFault, ActQueMsgOperator, ActQueMsgMonitor, Null2}; +const char StrSubMenu_1 [SubItemCount_1] [SubItemTextLen]={ + //"查询历史记录", 1111_ 1=allow 0=NotAllow S=BySet + /*"S110_1.全部事件", + "S110_2.火警事件", + "S110_3.联动事件", + "S110_4.故障事件", + "S110_5.操作事件", + "S110_6.监管事件", + "S110_7.打印事件"*/ + + "1110_1.全部事件", + "1110_2.报警事件", + "1110_3.联动事件", + "1110_4.监管事件", + "1110_5.故障事件", + "1110_6.操作事件", + "1110_7.打印事件" +}; + +const char StrSubMenu_1_En [SubItemCount_1] [SubItemTextLen]={ + //"查询历史记录", 1111_ 1=allow 0=NotAllow S=BySet + /*"S110_1.全部事件", + "S110_2.火警事件", + "S110_3.联动事件", + "S110_4.故障事件", + "S110_5.操作事件", + "S110_6.监管事件", + "S110_7.打印事件"*/ + + "1110_1.All", + "1110_2.Alarm", + "1110_3.Linkage", + "1110_4.Supervision", + "1110_5.Fault", + "1110_6.Operation", + "1110_7.Print" +}; + +//const xxxx MenuActionList_3[12] ={ActQueValue, ActQueMsgAlarm, ActQueMsgInterLink, ActQueMsgFault, ActQueMsgOperator, ActQueMsgMonitor, Null3}; +const char StrSubMenu_2 [SubItemCount_2] [SubItemTextLen]={ + //"通用设置", 1111_ 1=allow 0=NotAllow S=BySet + "1110_1.工程信息", + "1110_2.维保提醒", + "1110_3.运行模式", + "1110_4.系统授权", + "1110_5.设计数量", + "1110_6.按回路查询模块输出检线", //"1110_6.批量设置模块输出检线", + "1110_7.按回路查询烟感灵敏度", //"1110_7.批量设置烟感灵敏度", + "1110_8.按回路查询声光", //"1110_8.批量设置声光", + "1110_9.层显信息下载", +}; + +const char StrSubMenu_2_En [SubItemCount_2] [SubItemTextLen]={ + //"通用设置", 1111_ 1=allow 0=NotAllow S=BySet + "1110_1.Information", + "1110_2.Maintenance", + "1110_3.Operating State", + "1110_4.System Authorized", + "1110_5.Designed Numbers", + "1110_6.Output Line Inspection", + "1110_7.Smoke Det Sensitivity", + "1110_8.Acoustooptic Parameter", + "1110_9.Floor Display KeyPad Cfg", +}; + +//const xxxx MenuActionList_4[12] ={ActDeviceSetup, guiQueMsgAlarm, guiQueMsgInterLink, guiQueMsgFault, guiQueMsgOperator, guiQueMsgMonitor, Null4}; +const char StrSubMenu_3 [SubItemCount_3] [SubItemTextLen]={ + //"系统调试", 1111_ 1=allow 0=NotAllow S=BySet + + /*"0010_1.探测器模拟曲线", + "0010_2.回路设备运行状态", + "0010_3.回路设备实时数据", + "0010_4.回路设备在线配置", + "0010_5.回路设备运行电压", + "0010_6.回路设备手动启动", + "0S10_7.回路设备状态", + "0010_8.回路重号检测", + "0010_9.设备地址变更", + "0010_0.模拟运行与操作"*/ + + "1110_1.注册数据", + "1110_2.状态总览", + "1110_3.部件数据", + "1110_4.部件控制", + "1110_5.自动注册", + "1110_6.手动注册", + "1110_7.部件屏蔽", + "1110_8.重码检测", + "1110_9.部件分类数量", + "1110_0.注释编辑" +}; + +const char StrSubMenu_3_En [SubItemCount_3] [SubItemTextLen]={ + //"系统调试", 1111_ 1=allow 0=NotAllow S=BySet + + /*"0010_1.探测器模拟曲线", + "0010_2.回路设备运行状态", + "0010_3.回路设备实时数据", + "0010_4.回路设备在线配置", + "0010_5.回路设备运行电压", + "0010_6.回路设备手动启动", + "0S10_7.回路设备状态", + "0010_8.回路重号检测", + "0010_9.设备地址变更", + "0010_0.模拟运行与操作"*/ + + "1110_1.Registration Information", + "1110_2.Overview", + "1110_3.Device Information", + "1110_4.Device Control", + "1110_5.Auto Register", + "1110_6.Manual Register", + "1110_7.Device Blocking", + "1110_8.Duplicate Addr Check", + "1110_9.Device Types Count", + "1110_0.Device Annotation" +}; + +const char StrSubMenu_4 [SubItemCount_4] [SubItemTextLen]={ + //"系统设置", 1111_ 1=allow 0=NotAllow S=BySet + "1110_1.手动控制盘信息", + "1110_2.多线盘配置", + "1110_3.总线盘配置" +}; + +const char StrSubMenu_4_En [SubItemCount_4] [SubItemTextLen]={ + //"系统设置", 1111_ 1=allow 0=NotAllow S=BySet + "1110_1.App Keypad Boards Info", + "1110_2.Direct Keypad Boards Cfg", + "1110_3.Bus Keypad Boards Cfg" +}; + +const char StrSubMenu_5 [SubItemCount_5] [SubItemTextLen]={ + //"系统安装", 1111_ 1=allow 0=NotAllow S=BySet + "1110_1.编程查询", + "1110_2.编程输入", + "1110_3.广播控制", + "1110_4.手/自动控制状态", + "1110_5.联动设备控制总线FECBUS", + "1110_6.分区编辑", + "1110_7.二次码编辑(按回路)", + "1110_8.二次码编辑(按分区)" +}; + +const char StrSubMenu_5_En [SubItemCount_5] [SubItemTextLen]={ + //"系统安装", 1111_ 1=allow 0=NotAllow S=BySet + "1110_1.Linkage Expressions List", + "1110_2.Linkage Expressions Edit", + "1110_3.Broadcast Config", + "1110_4.Manual-Auto Switch", + "1110_5.FECBus Setting", + "1110_6.Zone Setting", + "1110_7.Aux ID Setting(Loop)", + "1110_8.Aux ID Setting(Zone)" +}; + +const char StrSubMenu_6 [SubItemCount_6] [SubItemTextLen]={ + //"网络设置" 1111_ 1=allow 0=NotAllow S=BySet + "1110 1.组网信息", + "1110_2.本机模式与注册", + "1110_3.网络屏蔽", + "1110_4.消防控制室图形显示装置" +}; + +const char StrSubMenu_6_En [SubItemCount_6] [SubItemTextLen]={ + //"网络设置" 1111_ 1=allow 0=NotAllow S=BySet + "1110 1.Network Information", + "1110_2.Local Setting", + "1110_3.Network ID Mask", + "1110_4.Graphic Display Setting" +}; + +const char StrSubMenu_7 [SubItemCount_7] [SubItemTextLen]={ + //本机 1=allow 0=NotAllow S=BySet + "1110_1.在线调试", + "0010_2.U盘传输", + "0010_3.蓝牙连接", + "0010_4.WIFI连接", + "0010_5.传输装置", + "0010_6.固件升级", +}; + +const char StrSubMenu_7_En [SubItemCount_7] [SubItemTextLen]={ + //本机 1=allow 0=NotAllow S=BySet + "1110_1.Online Test", + "0010_2.USB Disk Config", + "0010_3.Blue Tooth", + "0010_4.WIFI Setting", + "0010_5.Transmission Setting", + "0010_6.Firmware Upgrade", +}; + +const char StrSubMenu_8 [SubItemCount_8] [SubItemTextLen]={ + //高级设置 + "0010_1.清除注册数据", + "0010_2.清除联动编程", + "0010_3.清除注释信息", + "0010_4.恢复出厂设置" +}; + +const char StrSubMenu_8_En [SubItemCount_8] [SubItemTextLen]={ + //高级设置 + "1110_1.Clear Registered Data", + "1110_2.Clear Linkage Expressions", + "1110_3.Clear All Descriptions", + "1110_4.Restore Factory Setting" +}; + +const char StrSubMenu_9 [SubItemCount_9] [SubItemTextLen]={ + //"出厂设置， 隐藏", + "0010_1.生产过程检验信息", + "0010_2.清除全部配置信息", + "0010_3.清除全部历史事件", +}; + +const unsigned char SubMenuItem_Count[12] = { + SubItemCount_0, + SubItemCount_1, + SubItemCount_2, + SubItemCount_3, + SubItemCount_4, + SubItemCount_5, + SubItemCount_6, + SubItemCount_7, + SubItemCount_8, + SubItemCount_9, + SubItemCount_0, + SubItemCount_0 +}; + +const char *const pPermissionText[MainItemCount] ={ + &StrSubMenu_0[0][0], + &StrSubMenu_1[0][0], + &StrSubMenu_2[0][0], + &StrSubMenu_3[0][0], + &StrSubMenu_4[0][0], + &StrSubMenu_5[0][0], + &StrSubMenu_6[0][0], + &StrSubMenu_7[0][0], + &StrSubMenu_8[0][0], +}; + +const unsigned short Main_Top[12] = { + + 56, + 102, + 148, + 194, + 240, + + 286, + 332, + 378, +}; + +const unsigned short Main_Bottom[12] = { + + 98, + 144, + 190, + 236, + 282, + + 328, + 374, + 420, +}; + +const unsigned short Sub_Top[16] = { + // 320 / 8 / = 40, +56, +92, +128, +164, +200, + +236, +272, +308, +344, +380 + +}; + +const unsigned short Sub_Bottom[16] = { + // 320 / 8 / = 40, +88, +124, +160, +196, +232, + +268, +304, +340, +376, +412 + +}; + + + +void TMenu::Init(int x1, int y1, int x2, int y2) +{ + unsigned int i,j,x; + //0 level + BorderWidth = 2; + BorderColor = 0x00343242; + + MainBound.Set(x1,y1,299,y2); + SubBound.Set(300,y1,x2,y2); + + BevelOuter = bvRaised; + if(BevelOuter == bvRaised){ + MainContent.Set(x1 +1, y1 +1, 297, y2-2); + SubContent.Set(301, y1 +1, 797, y2-2); + }else{ + MainContent.Set(x1 +2, y1 +2, 297, y2-2); + SubContent.Set(301, y1 +2, 797, y2-2); + } + + MainFontSize = 24; + SubFontSize = 24; + + MainIndexOnTop = 0; + SelectedMainIndex = 0; + SelectedSubIndex = 0; + LastMainIndex =0xFF; + LastSubIndex =0xFF; + ActiveLevel = 0; + NeedRedraw =0; + + Active = 0; + OnAction = 0; + IsHasActive2 = 0; + + LoadText(); + LoadPermission(0); +} + +void TMenu::LoadText(void) +{ + unsigned int i; + //1 level + for(i=0; iRender(16,Icon16_Up , MainFixLeft, MainTFixTop); + IconList->Render(16,Icon16_Down, MainFixLeft, MainBFixTop); + } + }else{ + RectFillRender(MainFixLeft, MainTFixTop, MainFixRight, MainTFixBottom, clFrmFace); + RectFillRender(MainFixLeft, MainBFixTop, MainFixRight, MainBFixBottom, clFrmFace); + } + aIdx = MainIndexOnTop; + for(i=0; i< MainShowCount; i++){ + RectFillRender(MainIconLeft, Main_Top[i], MainIconRight, Main_Bottom[i], clFrmFace); + + if(SelectedMainIndex == aIdx){ + VertLineRender(MainLeft, Main_Top[i], MainHeight-1, 0xFF808080); + HorizLineRender(MainLeft, Main_Top[i], MainWidth-1, 0xFF808080); + + VertLineRender(MainLeft+1, Main_Top[i]+1, MainHeight-2, 0xFF404040); + HorizLineRender(MainLeft+1, Main_Top[i]+1, MainWidth-2, 0xFF404040); + + VertLineRender(MainRight-1, Main_Top[i]+1, MainHeight-2, 0xFFD4D0C8); + HorizLineRender(MainLeft+1, Main_Bottom[i]-1, MainWidth-2, 0xFFD4D0C8); + + VertLineRender(MainRight, Main_Top[i], MainHeight, 0xFFFFFFFF); + HorizLineRender(MainLeft, Main_Bottom[i], MainWidth, 0xFFFFFFFF); + + if(ActiveLevel == 0){ + if(IconList != nullptr)IconList->Render(24, 0, MainIconLeft ,Main_Top[i]+10); + RectFillRender(MainConLeft, Main_Top[i]+2, MainConRight, Main_Bottom[i]-2, clMaroon); + }else{ + if(IconList != nullptr)IconList->Render(24, 9, MainIconLeft ,Main_Top[i]+10); + RectFillRender(MainConLeft, Main_Top[i]+2, MainConRight, Main_Bottom[i]-2, clNearTeal); + } + + TextRender_string24(MainConLeft+16, Main_Top[i]+12, MENU_SELECTED_TEXT_CLR, MainItemList[aIdx].fName); + + }else{ + RectFillRender(MainLeft, Main_Top[i], MainRight, Main_Bottom[i], MENU_BG_COLOR); + RectFillRender(MainIconLeft ,Main_Top[i]+10, MainIconRight, Main_Bottom[i], clFrmFace); + TextRender_string24(MainLeft+10, Main_Top[i]+9, MENU_TEXT_CLR, MainItemList[aIdx].fName); + } + + aIdx++; + } +} + +void TMenu::SubDraw(void) +{ + + #define SubShowCount 10 + + #define Sub_Sel_EN_BG_CLR clSkyBlue + #define Sub_Sel_DIS_BG_CLR clLtGray + #define Sub_EN_BG_CLR clTeal + #define Sub_DIS_BG_CLR clOlive + + #define Sub_TEXT_Sel_EN_CLR clNearWhite + #define Sub_TEXT_Sel_DIS_CLR clGray + #define Sub_TEXT_EN_CLR clNearBlack + #define Sub_TEXT_DIS_CLR clGray + + #define Sub_Static_CLR clGray + #define Sub_Static_Text_CLR clOlive + + #define SubLeft 340 + #define SubRight 780 + + #define SubIconLeft 308 + #define SubIconRight 332 + + #define SubFixLeft 312 + #define SubFixRight 328 + #define SubTFixTop 40 + #define SubTFixBottom 56 + #define SubBFixTop 422 + #define SubBFixBottom 438 + + #define SubSelRectLeft 332 + #define SubSelRectRight 782 + int i; + unsigned int Tidx, Mid,Sid; + unsigned int Lstart, Lend, aClr; + if( (ActiveLevel != 0) && (ActiveLevel != 1) )ActiveLevel = 0; + for(i=0; iRender(16,Icon16_Up , SubFixLeft, SubTFixTop); + IconList->Render(16,Icon16_Down, SubFixLeft, SubBFixTop); + } + }else{ + RectFillRender(SubFixLeft, SubTFixTop, SubFixRight, SubTFixBottom, clFrmFace); + RectFillRender(SubFixLeft, SubBFixTop, SubFixRight, SubBFixBottom, clFrmFace); + } + Lstart = (SubShowCount - SubMenuItem_Count[SelectedMainIndex]) / 2; + //sp = 0; + Tidx = 0; + Lstart = 0; + for(i=Lstart; iRender(24,dIcon24_Allow1, SubIconLeft, Sub_Top[i]+6); + RectFillRender(SubLeft, Sub_Top[i], SubRight, Sub_Bottom[i], aClr); + TextRender_string24(SubLeft+6, Sub_Top[i]+6, clWhite, &SubItemList[SelectedMainIndex][Tidx].fName[5]); + }else{ + if(IconList != nullptr) IconList->Render(24,dIcon24_NotAllow1, SubIconLeft, Sub_Top[i]+6); + RectFillRender(SubLeft, Sub_Top[i], SubRight, Sub_Bottom[i], aClr); + TextRender_string24(SubLeft+6, Sub_Top[i]+6, clWhite, &SubItemList[SelectedMainIndex][Tidx].fName[5]); + } + }else{ + if(SubItemList[SelectedMainIndex][Tidx].Enable){ + if(IconList != nullptr) IconList->Render(24,dIcon24_Allow1, SubIconLeft, Sub_Top[i]+6); + RectFillRender(SubLeft, Sub_Top[i], SubRight, Sub_Bottom[i], clTeal); + TextRender_string24(SubLeft+6, Sub_Top[i]+6, clNearBlack, &SubItemList[SelectedMainIndex][Tidx].fName[5]); + }else{ + if(IconList != nullptr) IconList->Render(24,dIcon24_NotAllow1, SubIconLeft, Sub_Top[i]+6); + RectFillRender(SubLeft, Sub_Top[i], SubRight, Sub_Bottom[i], clTeal); + TextRender_string24(SubLeft+6, Sub_Top[i]+6, clNearBlack, &SubItemList[SelectedMainIndex][Tidx].fName[5]); + } + } + Lend = Lstart + Tidx; + Tidx++; + }else{ + break; + } + } + /*if(Lstart >0){ + if(SelectedMainIndex > 0){ + //get prv MainIndex + Mid = SelectedMainIndex - 1; + Sid = SubMenuItem_Count[Mid] -1; + for(i=Lstart-1; i>-1; i--){ + if(Sid>0){ + RectFillRender(SubLeft + 40, Sub_Top[i], SubRight, Sub_Bottom[i], clGray); + TextRender_string24(SubLeft + 46, Sub_Top[i]+6, clNearBlack, &SubItemList[Mid][Sid].fName[5]); + Sid--; + } + } + } + } + if(Lend < SubShowCount){ + if(SelectedMainIndex < (MainItemCount - 1)){ + //get Next MainIndex + Mid = SelectedMainIndex + 1; + Sid = 0; + for(i=Lend+1; i 3)return; + Permisson = aPms; + if( (aPms <1) || (aPms >3) ){ + Permisson = 1; + } + BitX = Permisson -1; + if(1){ + for(j=0; jGuiLoginIIIShow(); + PmsIntervene4Gui.Show4Gui(200, 200, 400, 140, 2); + }else + if(aPms == 3){ + //aPanel->GuiLoginIIIShow(); + PmsIntervene4Gui.Show4Gui(200, 200, 400, 140, 3); + } +} + +void TMenu::GoAction() +{ + if(SelectedMainIndex == 0){ + ActList_0 = static_cast(SelectedSubIndex); + if(ActList_0_Call(ActList_0)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 1){ + ActList_1 = static_cast(SelectedSubIndex); + if(ActList_1_Call(ActList_1)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 2){ + ActList_2 = static_cast(SelectedSubIndex); + if(ActList_2_Call(ActList_2)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 3){ + ActList_3 = static_cast(SelectedSubIndex); + if(ActList_3_Call(ActList_3)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 4){ + ActList_4 = static_cast(SelectedSubIndex); + if(ActList_4_Call(ActList_4)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 5){ + ActList_5 = static_cast(SelectedSubIndex); + if(ActList_5_Call(ActList_5)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 6){ + ActList_6 = static_cast(SelectedSubIndex); + if(ActList_6_Call(ActList_6)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 7){ + ActList_7 = static_cast(SelectedSubIndex); + if(ActList_7_Call(ActList_7)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 8){ + ActList_8 = static_cast(SelectedSubIndex); + if(ActList_8_Call(ActList_8)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }else + if(SelectedMainIndex == 9){ + ActList_9 = static_cast(SelectedSubIndex); + if(ActList_9_Call(ActList_9)){ + ActiveLevel = 2; + OnAction = 1; + IsHasActive2 = 1; + } + }/*else + if(SelectedMainIndex == 10){ + ActList_10 = static_cast(SelectedSubIndex); + if(ActList_10_Call(ActList_10)){ + ActiveLevel = 2; + } + }*/ +} + +void TMenu::CheckPermission() +{ + int NeedPms; + const char *p; + char aPmsChar[4]; + unsigned int OffsetCnt; + unsigned int aVal; + + aVal = SelectedSubIndex; + OffsetCnt = aVal * SubItemTextLen; + p = pPermissionText[SelectedMainIndex]; + p += OffsetCnt; + aPmsChar[0] = static_cast(*p++); + aPmsChar[1] = static_cast(*p++); + aPmsChar[2] = static_cast(*p++); + aPmsChar[3] = static_cast(*p++); + + if(aPmsChar[0] == '1'){ + NeedPms = 1; + }else + if(aPmsChar[1] == '1'){ + NeedPms = 2; + }else + if(aPmsChar[2] == '1'){ + NeedPms = 3; + }else{ + NeedPms = 4; + } + + if(SystemPermission < NeedPms){ + if(NeedPms == 2){ + IsBlockPermission = 1; + PmsIntervene4Gui.Show4Gui(200, 200, 400, 140, 2); + NeedingPermission = 2; + }else + if(NeedPms == 3){ + IsBlockPermission = 1; + PmsIntervene4Gui.Show4Gui(200, 200, 400, 140, 3); + NeedingPermission = 3; + } + } +} + +void TMenu::CheckSystemPermissionII() +{ + unsigned int Len,i, Cok, Cing; + Len = aPanel->Edit[0].Str.GetLength(); + if(Len <6)return; + if(Len >12)return; + Cok = 0; + Cing = 1; + if(Len == CtlCenter.PassWordII.Len){ + for(i=0; iEdit[0].Str.Text[i] != CtlCenter.PassWordII.Content[i]){ + Cing = 0; + } + } + if(Cing){ + Cok = 1; + if( (NeedingPermission >1) && (NeedingPermission < 4) ){ + SystemPermission = NeedingPermission; + }else{ + SystemPermission = 2; + } + SystemPermissionTick = 0; + } + } +} + +void TMenu::CheckSystemPermissionIII() +{ + unsigned int Len,i, Cok, Cing; + Len = aPanel->Edit[0].Str.GetLength(); + + if(Len == 16){ + Cok =0; + for(i=0; i<16; i++){ + if(SavePassWord[i] == aPanel->Edit[0].Str.Text[i])Cok++; + } + if(Cok == 16){ + SystemPermission = 3; + SystemPermissionTick = 0; + } + return; + } + + if(Len <6)return; + if(Len >12)return; + Cok = 0; + Cing = 1; + if(Len == CtlCenter.PassWordIII.Len){ + for(i=0; iEdit[0].Str.Text[i] != CtlCenter.PassWordIII.Content[i]){ + Cing = 0; + } + } + if(Cing){ + Cok = 1; + if( (NeedingPermission >1) && (NeedingPermission < 4) ){ + SystemPermission = NeedingPermission; + }else{ + SystemPermission = 3; + } + SystemPermissionTick = 0; + } + } +} + + +TGuiMsgReturn TMenu::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg; + unsigned char aNum, NewInx; + if(IsBlockPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsBlockPermission = 0; + SystemPermissionTick = 0; + MainMenu.LoadPermission(SystemPermission); + GoAction(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsBlockPermission = 0; + NeedFullRedraw = 1; + } + Check4ReDraw(); + return guiMsgNone; + } + /*if(IsBlockPermission){ + if(VK_RETURN == aKey){ + IsBlockPermission =0; + NeedFullRedraw = 1; + }else{ + if(NeedingPermission == 2){ + aMsg = aPanel->GuiLoginII_KeyIn(aKey); + aPanel->Edit[0].Show(); + if(aMsg == guiMsgOkAndReturn){ + CheckSystemPermissionII(); + CheckSystemPermissionIII(); + if(SystemPermission >= 2){ + SystemPermissionTick = 0; + IsBlockPermission =0; + MainMenu.LoadPermission(SystemPermission); + GoAction(); + }else{ + aPanel->GuiLoginPasswdErrShow(); + } + } + }else + if(NeedingPermission == 3){ + aMsg = aPanel->GuiLoginIII_KeyIn(aKey); + aPanel->Edit[0].Show(); + if(aMsg == guiMsgOkAndReturn){ + CheckSystemPermissionIII(); + if(SystemPermission >= 3){ + SystemPermissionTick = 0; + IsBlockPermission =0; + MainMenu.LoadPermission(SystemPermission); + GoAction(); + }else{ + aPanel->GuiLoginPasswdErrShow(); + } + } + } + } + Check4ReDraw(); + return guiMsgNone; + }*/ + + if(ActiveLevel == 0){ + switch(aKey){ + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if(aKey == '0'){ + aNum = aKey - '0' + 10; + }else{ + aNum = aKey - '0'; + } + NewInx = aNum -1; + if(NewInx < MainItemCount){ + if(SelectedMainIndex == NewInx){ + SelectedSubIndex = 0; + ActiveLevel = 1; + IsHasActive2 = 0; + }else{ + SelectedMainIndex = NewInx; + if(SelectedMainIndex < 8){ + MainIndexOnTop = 0; + }else{ + MainIndexOnTop = 1; + } + } + SelectedSubIndex = 0; + NeedRedraw = 1; + } + break; + } + }else + if(ActiveLevel == 1){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if(aKey == '0'){ + aNum = aKey - '0' + 10; + }else{ + aNum = aKey - '0'; + } + NewInx = aNum -1; + if(NewInx < SubMenuItem_Count[SelectedMainIndex]){ + if(SelectedSubIndex == NewInx){ + CheckPermission(); + if(IsBlockPermission == 0) + GoAction(); + }else{ + SelectedSubIndex = NewInx; + NeedRedraw = 1; + } + } + break; + } + } + + if(ActiveLevel == 2){ + if(SelectedMainIndex == 0){ + ActList_0 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_0_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 1){ + ActList_1 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_1_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 2){ + ActList_2 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_2_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 3){ + ActList_3 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_3_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 4){ + ActList_4 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_4_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 5){ + ActList_5 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_5_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 6){ + ActList_6 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_6_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 7){ + ActList_7 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_7_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 8){ + ActList_8 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_8_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }else + if(SelectedMainIndex == 9){ + ActList_9 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_9_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + OnAction = 0; + } + }/*else + if(SelectedMainIndex == 10){ + ActList_10 = static_cast(SelectedSubIndex); + if(guiMsgReturn == ActList_10_ToDo(aKey)){ + ActiveLevel = 1; + NeedFullRedraw = 1; + } + }*/ + Check4ReDraw(); + return aMsg; + } + + if(VK_LEFT == aKey){ + if(ActiveLevel == 1){ + ActiveLevel = 0; + NeedRedraw = 1; + } + }else + if(VK_RIGHT == aKey){ + if(ActiveLevel == 0){ + ActiveLevel = 1; + NeedRedraw = 1; + } + }else + if(VK_UP == aKey){ + if(ActiveLevel == 0){ + if(SelectedMainIndex > 0){ + SelectedMainIndex--; + SelectedSubIndex = 0; + NeedRedraw = 1; + if(SelectedMainIndex < MainIndexOnTop){ + MainIndexOnTop--; + } + } + }else + if(ActiveLevel == 1){ + if(SelectedSubIndex > 0){ + SelectedSubIndex--; + NeedRedraw = 1; + }else{ + if(SelectedMainIndex > 0){ + SelectedMainIndex--; + SelectedSubIndex = SubMenuItem_Count[SelectedMainIndex] - 1; + NeedRedraw = 1; + if(SelectedMainIndex < MainIndexOnTop){ + MainIndexOnTop--; + } + } + } + } + }else + if(VK_DOWN == aKey){ + if(ActiveLevel == 0){ + if( SelectedMainIndex < (MainItemCount - 1) ){ + SelectedMainIndex++; + SelectedSubIndex = 0; + NeedRedraw = 1; + if(SelectedMainIndex > (MainIndexOnTop + MainShowCount - 1)){ + MainIndexOnTop++; + } + } + }else + if(ActiveLevel == 1){ + if( SelectedSubIndex < (SubMenuItem_Count[SelectedMainIndex]-1) ){ + SelectedSubIndex++; + NeedRedraw = 1; + }else{ + if(SelectedMainIndex < (MainItemCount - 1)){ + SelectedMainIndex++; + SelectedSubIndex = 0; + NeedRedraw = 1; + if(SelectedMainIndex > (MainIndexOnTop + MainShowCount - 1)){ + MainIndexOnTop++; + } + } + } + } + }else + if(VK_RETURN == aKey){ + if(ActiveLevel == 0){ + IsBlockPermission = 0; + Active = 0; + OnAction = 0; + aMsg = guiMsgReturn; + }else + if(ActiveLevel == 1){ + IsBlockPermission = 0; + ActiveLevel = 0; + NeedRedraw = 1; + OnAction = 0; + }else + if(ActiveLevel == 2){ + + }else{ + NeedRedraw = 1; + } + }else + if(VK_MENU == aKey){ + //NeedRedraw = 1; + }else + if(VK_EXECUTE == aKey){ + if(ActiveLevel == 0){ + ActiveLevel = 1; + NeedRedraw = 1; + }else + if(ActiveLevel == 1){ + CheckPermission(); + if(IsBlockPermission == 0) + GoAction(); + } + } + + Check4ReDraw(); + + return aMsg; +} + +void TMenu::Hide() +{ + IsBlockPermission = 0; + Active = 0; + OnAction = 0; + if(IsHasActive2){ + IsHasActive2 = 0; + ExtReqExit(); + } + ActiveLevel = 0; +} + +void TMenu::FullRedrawFrm(int Prm) +{ + if(SelectedMainIndex == 0){ + ActList_0 = static_cast(SelectedSubIndex); + if(ActList_0_RedrawCallBack(Prm)){ + + } + }else + if(SelectedMainIndex == 1){ + ActList_1 = static_cast(SelectedSubIndex); + if(ActList_1_RedrawCallBack(Prm)){ + + } + + }else + if(SelectedMainIndex == 2){ + ActList_2 = static_cast(SelectedSubIndex); + if(ActList_2_RedrawCallBack(Prm)){ + + } + + }else + if(SelectedMainIndex == 3){ + ActList_3 = static_cast(SelectedSubIndex); + if(ActList_3_RedrawCallBack(Prm)){ + + } + + }else + if(SelectedMainIndex == 4){ + ActList_4 = static_cast(SelectedSubIndex); + if(ActList_4_RedrawCallBack(Prm)){ + + } + + }else + if(SelectedMainIndex == 5){ + ActList_5 = static_cast(SelectedSubIndex); + if(ActList_5_RedrawCallBack(Prm)){ + + } + + }else + if(SelectedMainIndex == 6){ + ActList_6 = static_cast(SelectedSubIndex); + if(ActList_6_RedrawCallBack(Prm)){ + + } + + }else + if(SelectedMainIndex == 7){ + ActList_7 = static_cast(SelectedSubIndex); + if(ActList_7_RedrawCallBack(Prm)){ + + } + + }else + if(SelectedMainIndex == 8){ + ActList_8 = static_cast(SelectedSubIndex); + if(ActList_8_RedrawCallBack(Prm)){ + + } + }else + if(SelectedMainIndex == 9){ + ActList_9 = static_cast(SelectedSubIndex); + if(ActList_9_RedrawCallBack(Prm)){ + + } + } +} + +void TMenu::ExtReqExit() +{ + if(SelectedMainIndex == 0){ + ActList_0 = static_cast(SelectedSubIndex); + if(ActList_0_CallBack(ActList_0)){ + + } + + }else + if(SelectedMainIndex == 1){ + ActList_1 = static_cast(SelectedSubIndex); + if(ActList_1_CallBack(ActList_1)){ + + } + + }else + if(SelectedMainIndex == 2){ + ActList_2 = static_cast(SelectedSubIndex); + if(ActList_2_CallBack(ActList_2)){ + + } + + }else + if(SelectedMainIndex == 3){ + ActList_3 = static_cast(SelectedSubIndex); + if(ActList_3_CallBack(ActList_3)){ + + } + + }else + if(SelectedMainIndex == 4){ + ActList_4 = static_cast(SelectedSubIndex); + if(ActList_4_CallBack(ActList_4)){ + + } + + }else + if(SelectedMainIndex == 5){ + ActList_5 = static_cast(SelectedSubIndex); + if(ActList_5_CallBack(ActList_5)){ + + } + + }else + if(SelectedMainIndex == 6){ + ActList_6 = static_cast(SelectedSubIndex); + if(ActList_6_CallBack(ActList_6)){ + + } + + }else + if(SelectedMainIndex == 7){ + ActList_7 = static_cast(SelectedSubIndex); + if(ActList_7_CallBack(ActList_7)){ + + } + + }else + if(SelectedMainIndex == 8){ + ActList_8 = static_cast(SelectedSubIndex); + if(ActList_8_CallBack(ActList_8)){ + + } + + }else + if(SelectedMainIndex == 9){ + ActList_9 = static_cast(SelectedSubIndex); + if(ActList_9_CallBack(ActList_9)){ + + } + + } +} + + + + + + diff --git a/MyCode/Gui/TMenu.h b/MyCode/Gui/TMenu.h new file mode 100644 index 0000000..fb90d33 --- /dev/null +++ b/MyCode/Gui/TMenu.h @@ -0,0 +1,121 @@ +#ifndef MENU_H_ +#define MENU_H_ + +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "GlobalString.h" +#include "gvalue.h" +#include "CtlPanel1.h" +#include "ActionListCall.h" + +#define MainItemCount 9 +#define SubItemTextLen 36 + +#define SubItemCount_0 7 +#define SubItemCount_1 7 +#define SubItemCount_2 9 +#define SubItemCount_3 10 +#define SubItemCount_4 3 +#define SubItemCount_5 8 +#define SubItemCount_6 4 +#define SubItemCount_7 6 +#define SubItemCount_8 4 //interlink + +#define SubItemCount_9 4 //passwd + +extern const unsigned char SubMenu_Count[12]; + +typedef struct{ + const char *fName; + int Enable; +}TmenuItem; + +class TMenu{ + public: + int ItemsCount; + unsigned int BorderColor; + unsigned char BorderWidth; + + //TRect Bound; + TRect MainBound; + TRect SubBound; + TRect MainContent; + TRect SubContent; + TBvStyle BevelOuter; + + char MainFontSize; + char SubFontSize; + + unsigned char MainIndexOnTop; + unsigned char ActiveLevel; + unsigned char NeedRedraw; + unsigned char NeedFullRedraw; + + unsigned int Permisson; + TmenuItem MainItemList[12]; + TmenuItem SubItemList[12][10]; + + unsigned char IsHasActive2; + unsigned char SelectedMainIndex; + unsigned char SelectedSubIndex; + unsigned char LastMainIndex; + unsigned char LastSubIndex; + unsigned char IsBlockPermission; + int NeedingPermission; + + + int Active; + int OnAction; + class TImageList *IconList; + class TCtlPanelLite *aPanel; + public: + TMenu(){}; + TMenu(int x1, int y1, int x2, int y2){ + Init(x1, y1, x2, y2); + } + + void LoadText(void); + void SelfDraw(void); + void MainDraw(void); + void SubDraw(void); + void Show(void); + void ReDraw(void); + void FullRedraw(); + void FullRedrawFrm(int Prm); + void RedrawFrmVoidArea(int x, int y, int x2, int y2); + + void Hide(); + + void Init(int x1, int y1, int x2, int y2); + + TGuiMsgReturn KeyIn(unsigned char aKey); + void Check4ReDraw(void); + + void ItemsLoadCaption(const char* pc, s16 Index); + void SubItemsLoadCaption(const char* pc, s16 Index, s16 SubIndex); + + void LoadPermission(unsigned int aPms); + + void CheckPermission(); + void LoginBlock(int aPms); + void GoAction(); + + void CheckSystemPermissionII(); + void CheckSystemPermissionIII(); + + void ExtReqExit(); + + +}; + + + + + + + + +#endif + diff --git a/MyCode/Gui/ThisCtlInf.cpp b/MyCode/Gui/ThisCtlInf.cpp new file mode 100644 index 0000000..0a8d79a --- /dev/null +++ b/MyCode/Gui/ThisCtlInf.cpp @@ -0,0 +1,149 @@ +#include "ThisCtlInf.h" +#include "DevMask.h" + + + +void TThisCtlInf::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + + Color = aColor; + #undef CH + Caption.Border.Color = clGray; +} + +void TThisCtlInf::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TThisCtlInf::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TThisCtlInf::RenderContent(void) +{ + #define FixColColor clMedGray + #define OddColor clNearMoneyGreen + unsigned int x,y, y2, clr; + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, FixColColor); +} + +void TThisCtlInf::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TThisCtlInf::DrawCaption(void) +{ + TMyString::sFromStr("本机硬件信息", Caption.Text); + Caption.Show(); +} + +void TThisCtlInf::Show() +{ + DrawSelf(); + DrawCaption(); +} + +void TThisCtlInf::ShowInf() +{ + +} + +TGuiMsgReturn TThisCtlInf::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + if(IsProgram){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + + break; + case VK_UP: + + break; + case VK_DOWN: + + break; + case VK_TAB: + + break; + case VK_EXECUTE: + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/ThisCtlInf.h b/MyCode/Gui/ThisCtlInf.h new file mode 100644 index 0000000..34f9a9a --- /dev/null +++ b/MyCode/Gui/ThisCtlInf.h @@ -0,0 +1,88 @@ +#ifndef THISCTLINF_H_ +#define THISCTLINF_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "EditML.h" +#include "CtlPanel1.h" + +class TThisCtlInf{ + public: + TStaticText Caption; + u32 Color; + + TRect Bound; + TRect Content; + TRect RectPanel; + class TCtlPanel1 *aPanel; + + unsigned char CtlIndex; + unsigned char IsProgram; + + unsigned char PadNum; + unsigned char KeyNum; + unsigned char IsUsing; + unsigned char Type; + unsigned char Ferture; + unsigned char Fon; + + public: + TThisCtlInf(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + void RenderBackGround(void); + + void RenderBackGround(unsigned int aClr); + void RenderContent(void); + void DrawSelf(void); + void DrawCaption(void); + void Show(); + + void ShowInf(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/TipPopup.cpp b/MyCode/Gui/TipPopup.cpp new file mode 100644 index 0000000..ce7b478 --- /dev/null +++ b/MyCode/Gui/TipPopup.cpp @@ -0,0 +1,346 @@ +#include "TipPopup.h" +#include "Runtime.h" +#include "Server.h" + +extern "C"{ + #include "HW_config.h" + #include "user_eeprom.h" +} + +static const char LicenseText[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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centre_y, unsigned int cClr, unsigned int bClr) +{ + const char* p; + int start_x; + int start_y; + int ix = 0; + int iy = 0; + unsigned int i; + + if(centre_x > (64*3))start_x = centre_x - 64*3; + else start_x = 0; + + if(centre_y > (64/2))start_y = centre_y - 64/2; + else start_y = 0; + + if(LanguageEnCn==0)p = LicenseText; + else p = LicenseTextEn; + + while(iy<64){ + for(i=0;i<8;i++){ + if((*p)&(0x80>>i)){ + PixelRender(start_x+ix, start_y+iy, cClr); + }else{ + PixelRender(start_x+ix, start_y+iy, bClr); + } + ix++; + if(ix>=(64*6)){ + ix=0; + iy++; + } + } + p++; + } +} + + +void TTipPopup::DrawSelf() +{ + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + //Fill Rect Box + RectFillRender(Caption.Left, Caption.Top, Caption.Right, Caption.Bottom, Color4Caption); + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, clFrmFace); +} + +void TTipPopup::Show() +{ + //System unauthorized + DrawSelf(); + TickCountDown2SelfCheck =0; + Tick4Refresh =0; + IsShowTipPopup =1; + IsShow =1; + + RectFillRender(Caption.Left, Caption.Top, Caption.Right, Caption.Bottom, Color4Caption); + if(What == 0x03){ + if(LanguageEnCn==0)TMyString::sFromStr("系统未授权,正运行在调试模式", Text); + else TMyString::sFromStr("Unauthorized, Running In Test Mode", Text); + DrawLicenseText(Content.Left + (Content.Width/2), Content.Top + 46,clRed,clFrmFace); + TPageIdle::sDrawDebugText(Content.Left + (Content.Width/2), Content.Top + 118,clRed,clFrmFace); + }else + if(What == 0x01){ + if(LanguageEnCn==0)TMyString::sFromStr("系统未授权", Text); + else TMyString::sFromStr("Unauthorized", Text); + DrawLicenseText(Content.Left + (Content.Width/2), Content.Top + (Content.Height/2),clRed,clFrmFace); + }else + if(What == 0x02){ + if(LanguageEnCn==0)TMyString::sFromStr("正运行在调试模式", Text); + else TMyString::sFromStr("Running In Test Mode", Text); + TPageIdle::sDrawDebugText(Content.Left + (Content.Width/2), Content.Top + (Content.Height/2),clRed,clFrmFace); + } + TextRender_string24(Caption.Left + 6, Caption.Top+ 4, clNearWhite, Color4Caption, Text); +} + +void TTipPopup::ShowLicenseError() +{ + DrawSelf(); + DrawLicenseText(Content.Left + (Content.Width/2), Content.Top + (Content.Height/2),clRed,clNearWhite); + IsShowTipPopup =1; + IsShow =1; +} + +void TTipPopup::RedrawTip() +{ + +} + +void TTipPopup::Hide() +{ + IsShowTipPopup = 0; + IsShow = 0; +} + +void TTipPopup::Init() +{ + Clear(); +} + +void TTipPopup::Clear() +{ + TickNoKey4PopupTip =0; + TickCountDown2SelfCheck =0; + Tick4Refresh =0; +} + +void TTipPopup::ClearTickOnKeyPress() +{ + Clear(); +} + +void TTipPopup::ClearTickOnEventOcc() +{ + Clear(); +} + +int TTipPopup::Task1000Ms() +{ + unsigned int NewWhat; + int CheckNone = 2; + int tResult =0; + if(TickNoKey4PopupTip SelCheckCountDownPoint){ + //Go SelfCheck + Hide(); + TickCountDown2SelfCheck =0; + Tick4Refresh =0; + if(TickNoKeyPoint > 90){ + TickNoKey4PopupTip = TickNoKeyPoint -90; + } + return 2; + }else{ + TMyString::sFrom3Dg((SelCheckCountDownPoint - TickCountDown2SelfCheck), NumText); + TextRender_string24(Content.Right - 48, Content.Bottom - 28, Color4Caption , clFrmFace, NumText); + } + } + return 1; + } + }else{ + if(IsShow){ + Hide(); + return -1; + } + } + return 0; +} + +int TTipPopup::ExtRequst(unsigned char Prm) +{ + IsShow = 0; + IsShowTipPopup = 0; + return 0; +} + diff --git a/MyCode/Gui/TipPopup.h b/MyCode/Gui/TipPopup.h new file mode 100644 index 0000000..9be1f64 --- /dev/null +++ b/MyCode/Gui/TipPopup.h @@ -0,0 +1,78 @@ +#ifndef TIPPOPUP_H_ +#define TIPPOPUP_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "my_string.h" +#include "TMenu.h" + + +//aPanel with Caption, StaticText, Btn, Edit, +class TTipPopup{ + public: + static constexpr const unsigned int Color = clNearWhite; + static constexpr const unsigned int Color4Caption = clRed; + static constexpr const unsigned int TickNoKeyPoint = 520; + static constexpr const int SelCheckCountDownPoint = 100; + static constexpr const TRect Bound = { + .Left = 100, + .Top = 120, + .Right = 699, + .Bottom = 319, + .Width = 699-100+1, + .Height =319-120+1 + }; + static constexpr struct TRect Caption = { + .Left = 100 +2, + .Top = 120 +2, + .Right = 699 -1, + .Bottom = 120 +2 +32, + .Width = 699-100+1 -3, + .Height = 32 + }; + static constexpr struct TRect Content = { + .Left = 100 +2, + .Top = 120 +2 +32, + .Right = 699 -1, + .Bottom = 319 -1, + .Width = 699-100+1 -3, + .Height =319-120+1 -3 - 32 + }; + static constexpr TPoint ResultTipPoint = { + .x = 100, + .y = 200, + }; + public: + int IsShow; + unsigned int TickCountDown2SelfCheck; + unsigned int Tick4Refresh; + unsigned int What; + class TMenu *pMenu; + char Text[64]; + char NumText[12]; + public: + TTipPopup(){}; + void Init(); + void DrawSelf(void); + void Show(); + void ShowLicenseError(); + void Hide(); + void RedrawTip(); + + void RePaint(void); + void DrawLicenseText(int centre_x, int centre_y, unsigned int cClr, unsigned int bClr); + + void ClearTickOnKeyPress(); + void ClearTickOnEventOcc(); + void Clear(); + void DoResume(); + int Task1000Ms(); + int ExtRequst(unsigned char Prm); +}; + + + + + + +#endif diff --git a/MyCode/Gui/TransmiteDeviceCfg.cpp b/MyCode/Gui/TransmiteDeviceCfg.cpp new file mode 100644 index 0000000..20d3d25 --- /dev/null +++ b/MyCode/Gui/TransmiteDeviceCfg.cpp @@ -0,0 +1,492 @@ +#include "TransmiteDeviceCfg.h" +#include "Runtime.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +static const int xFirst = 10; +static const int xSec = 120; +static const int xThird = 230; +static const int xFourth= 340; +static const int xFifth = 450; +static const int xSixth = 560; +static const int xSeventh = 661; + +void TTransmiteDev::Init() +{ + CtlIndex = 0; + IsShowing = 0; + IsOnGoing = 0; + ReadWrite =0; + + IsPermission =0; + + OnOff.Fire =1; + OnOff.Lnk =0; + OnOff.Sv =1; + OnOff.Fault =1; + OnOff.Mask =0; + OnOff.Opa =1; + OnOff.Other =0; + + State.DeviceOn =0; + State.Connection =0; + State.Rsv1 =1; + State.Rsv2 =2; +} + +void TTransmiteDev::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick传输装置"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "传输装置设置"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "接口选择"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "数据信息选择"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "开启", 12, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[0] + 36, 72, 30, 7, clNearWhite, "关闭", 12, clNearBlack); + TextRender_string24(xFirst + 30, Lv.Grid.Top[1] + 40, clNearWhite, "RS485"); + TextRender_string24(xSec +30, Lv.Grid.Top[1] + 40, clNearWhite, "CAN"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[2] + 40, clNearWhite, "火警"); + TextRender_string24(xSec +30, Lv.Grid.Top[2] + 40, clNearWhite, "联动"); + TextRender_string24(xThird + 30, Lv.Grid.Top[2] + 40, clNearWhite, "监管"); + TextRender_string24(xFourth +30, Lv.Grid.Top[2] + 40, clNearWhite, "故障"); + TextRender_string24(xFifth + 30, Lv.Grid.Top[2] + 40, clNearWhite, "屏蔽"); + TextRender_string24(xSixth +30, Lv.Grid.Top[2] + 40, clNearWhite, "操作"); + TextRender_string24(xSeventh + 30, Lv.Grid.Top[2] + 40, clNearWhite, "其他"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Data Transmission->Device"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Device Setting"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Port Choice"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Data Select"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 108, 30, 7, clNearWhite, "Enable", 12, clNearBlack); + TRoundRect::sDrawBySize(160, Lv.Grid.Top[0] + 36, 108, 30, 7, clNearWhite, "Disable", 12, clNearBlack); + TextRender_string24(xFirst + 30, Lv.Grid.Top[1] + 40, clNearWhite, "RS485"); + TextRender_string24(xSec +30, Lv.Grid.Top[1] + 40, clNearWhite, "CAN"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[2] + 40, clNearWhite, "Fire"); + TextRender_string24(xSec +30, Lv.Grid.Top[2] + 40, clNearWhite, "Link"); + TextRender_string24(xThird + 30, Lv.Grid.Top[2] + 40, clNearWhite, "SUPV"); + TextRender_string24(xFourth +30, Lv.Grid.Top[2] + 40, clNearWhite, "Fail"); + TextRender_string24(xFifth + 30, Lv.Grid.Top[2] + 40, clNearWhite, "Mask"); + TextRender_string24(xSixth +30, Lv.Grid.Top[2] + 40, clNearWhite, "OPER"); + TextRender_string24(xSeventh + 30, Lv.Grid.Top[2] + 40, clNearWhite, "Other"); + } +} + +void TTransmiteDev::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i 5){ + ClearSelected(); + CtlIndex =3; + Check4Selected(); + }else + if(CtlIndex > 1){ + ClearSelected(); + CtlIndex-=2; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex < 4){ + ClearSelected(); + CtlIndex+=2; + Check4Selected(); + } + break; + case dfKEY_SETUP: + if(CtlIndex == 2){ + LineType = LineType ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 3){ + LineType = LineType ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 4){ + OnOff.Fire = OnOff.Fire ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 5){ + OnOff.Lnk = OnOff.Lnk ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 6){ + OnOff.Sv = OnOff.Sv ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 7){ + OnOff.Fault = OnOff.Fault ? 0 : 1; + DrawSetting(); + } + if(CtlIndex == 8){ + OnOff.Mask = OnOff.Mask ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 9){ + OnOff.Opa = OnOff.Opa ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 10){ + OnOff.Other = OnOff.Other ? 0 : 1; + DrawSetting(); + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + //Active + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Top[1] + 12, 600 , 120, 3); + } + }else + if(CtlIndex == 1){ + //Close + PermissionCmd = 2; + PermissionCmdGO(); + } + if(CtlIndex == 2){ + LineType = LineType ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 3){ + LineType = LineType ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 4){ + OnOff.Fire = OnOff.Fire ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 5){ + OnOff.Lnk = OnOff.Lnk ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 6){ + OnOff.Sv = OnOff.Sv ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 7){ + OnOff.Fault = OnOff.Fault ? 0 : 1; + DrawSetting(); + } + if(CtlIndex == 8){ + OnOff.Mask = OnOff.Mask ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 9){ + OnOff.Opa = OnOff.Opa ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 10){ + OnOff.Other = OnOff.Other ? 0 : 1; + DrawSetting(); + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TTransmiteDev::sRecoverSetDefault() +{ + SysLoopTick = 0; +} + +int TTransmiteDev::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} + +void TTransmiteDev::Task1000Ms() +{ + +} + + + + + + diff --git a/MyCode/Gui/TransmiteDeviceCfg.h b/MyCode/Gui/TransmiteDeviceCfg.h new file mode 100644 index 0000000..7249af4 --- /dev/null +++ b/MyCode/Gui/TransmiteDeviceCfg.h @@ -0,0 +1,147 @@ +#ifndef TRANSMITEDEVICE_H_ +#define TRANSMITEDEVICE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TTransmiteDev{ + public: + static constexpr unsigned short hList[12] = {70,70,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 3, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4, + .Panel.Width = 796, + .Panel.Heigh = 140, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2] +4 + 140 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char CrtNum; + unsigned char CrtNumValid; + + + unsigned char LineType; + unsigned char ReadWrite; + unsigned char IsOnGoing; + + char Text[68]; + + struct{ + unsigned char Fire; + unsigned char Lnk; + unsigned char Sv; + unsigned char Fault; + unsigned char Mask; + unsigned char Opa; + unsigned char Other; + unsigned char Sv2; + }OnOff; + struct{ + unsigned char DeviceOn; + unsigned char Connection; + unsigned char Rsv1; + unsigned char Rsv2; + }State; + + public: + TTransmiteDev(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DelayMs(unsigned int aMs); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + void DrawConnState(); + + void DrawSetting(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + static void sRecoverSetDefault(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + +#endif diff --git a/MyCode/Gui/UnRegister.cpp b/MyCode/Gui/UnRegister.cpp new file mode 100644 index 0000000..ba01311 --- /dev/null +++ b/MyCode/Gui/UnRegister.cpp @@ -0,0 +1,979 @@ +#include "RuntimeData.h" +#include "UnRegister.h" + +void TUnRegister::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left, Top, Width, CH, 0, 0, clWhite, clMaroon); + SText.Init (429, Top, 370, CH, 0, 0, clWhite, clMaroon); + + Content.Set(Left, Top+CH, Right, Bottom); + + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + + CtlIndex = 0; + ListIndex = 0; + IsViewList = 0; + IsAskingRemoveWhat = 1; +} + +void TUnRegister::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TUnRegister::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TUnRegister::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderBackGround(); +} + + +void TUnRegister::DrawCaption2(void) +{ + TMyString::sFromStr("TAB键在编辑与类型列表之间切换", SText.Text); + SText.Show(); +} + +void TUnRegister::Show(void) +{ + RenderBackGround(); + DrawSelf(); + TMyString::sFromStr("删除消防设备-本机", Caption.Text); + Caption.Show(); +} + +void TUnRegister::ShowCaption() +{ + TMyString::sFromStr(" zzzzzzz", Caption.Text); + Caption.Show(); +} + +//______________________________________________________________________________________________________________________________ +void TUnRegister::Check4Selected4Part(void) +{ + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + aPanel->Edit[3].Selected = 0; + aPanel->Btn[0].Selected = 0; + if(IsViewList == 0){ + if(CtlIndex == 0){ + aPanel->Edit[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Edit[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Edit[2].Selected = 1; + }else + if(CtlIndex == 3){ + aPanel->Edit[3].Selected = 1; + }else + if(CtlIndex == 4){ + aPanel->Btn[0].Selected = 1; + } + } +} + +void TUnRegister::InitPanel(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + if(aPanel == nullptr)return; + + aPanel->Init(200,40,400,200,x,y,clFrmFace, bvRaised); + aPanel->Caption.Init(200+1,40+1,400-3,32,x,y,clNearWhite,clDeepBlue); + TMyString::sFromStr("选择清除方法", aPanel->Caption.Text); + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + + aPanel->Btn[0].Init(80,40,240,36,x,y,1,clFrmFace); + aPanel->Btn[1].Init(80,90,240,36,x,y,1,clFrmFace); + aPanel->Btn[0].Caption.FromStr(" 解除全部注册信息"); + aPanel->Btn[1].Caption.FromStr(" 根据地址段清除"); + aPanel->Btn[0].SetCaptionLeftSpacing(6); + aPanel->Btn[0].Enable =1; + aPanel->Btn[0].Visible =1; + aPanel->Btn[1].SetCaptionLeftSpacing(6); + aPanel->Btn[1].Enable =1; + aPanel->Btn[1].Visible =1; + + CtlIndex = 1; + aPanel->Btn[0].Selected =0; + aPanel->Btn[1].Selected =1; + + aPanel->Show(); + aPanel->ReDrawItems(); +} + +void TUnRegister::InitPanel4All(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + if(aPanel == nullptr)return; + + aPanel->Init(200,40,400,200,x,y,clFrmFace, bvRaised); + aPanel->Caption.Init(201,41,400-3,32,x,y,clNearWhite,clDeepBlue); + TMyString::sFromStr("准备清除全部信息", aPanel->Caption.Text); + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->SText[0].Init(146,6,100,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr(" ", aPanel->SText[0].Text); + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->Btn[0].Init(80,40,240,34,x,y,1,clFrmFace); + aPanel->Btn[1].Init(80,90,240,34,x,y,1,clFrmFace); + aPanel->Btn[0].Caption.FromStr(" 确定执行清除全部"); + aPanel->Btn[1].Caption.FromStr(" 取消清除"); + aPanel->Btn[0].SetCaptionLeftSpacing(6); + aPanel->Btn[0].Enable =1; + aPanel->Btn[0].Visible =1; + aPanel->Btn[0].SelectedColor = clRed; + aPanel->Btn[0].SelectedTextColor = clNearWhite; + aPanel->Btn[1].SetCaptionLeftSpacing(6); + aPanel->Btn[1].Enable =1; + aPanel->Btn[1].Visible =1; + + CtlIndex = 1; + aPanel->Btn[0].Selected =0; + aPanel->Btn[1].Selected =1; + + aPanel->Show(); + aPanel->ReDrawItems(); +} + +void TUnRegister::InitPanel4Part(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + TextRender_string24(x+86,y + 93,clBlack,"设置键减1,查询键加1"); + TextRender_string24(x+400,y + 93,clRed,"按确认键直接解除"); + if(aPanel == nullptr)return; + + aPanel->Init(4,6,784,82,x,y,clFrmFace, bvRaised); + aPanel->Caption.Init(4+1,6+1,781,32,x,y,clFrmFace,clFrmFace); + + x = aPanel->Bound.Left; + y = aPanel->Bound.Top; + aPanel->SText[0].Init(0,4,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(107,4,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(308,4,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(0, 47,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(231,4,60,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[5].Init(608, 47,102,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("回路", aPanel->SText[0].Text); + TMyString::sFromStr("地址段", aPanel->SText[1].Text); + TMyString::sFromStr("类型", aPanel->SText[2].Text); + TMyString::sFromStr("地址段1~250时解除整回路,地址段始末相等则解除单地址", aPanel->SText[3].Text); + TMyString::sClear(aPanel->SText[5].Text); + TMyString::sFromStr("-", aPanel->SText[4].Text); + aPanel->SText[3].TextColor = clDeepGray; + + aPanel->Edit[0].Init(52,6,40,30,x,y,1,clNearWhite); + aPanel->Edit[1].Init(184,6,50,30,x,y,1,clNearWhite); + aPanel->Edit[2].Init(248,6,50,30,x,y,1,clNearWhite); + aPanel->Edit[3].Init(360,6,50,30,x,y,1,clNearWhite); + aPanel->Edit[4].Init(420,6,270,30,x,y,1,clNearWhite); + + for(i=0; i<5; i++){ + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].Enable = 1; + } + + aPanel->Edit[0].Str.FromStr("01"); + aPanel->Edit[0].SetInputMaskEn(); + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[0].Pst = 1; + aPanel->Edit[1].Str.FromStr("001"); + aPanel->Edit[1].SetMaxLen(3); + aPanel->Edit[1].Pst = 2; + aPanel->Edit[2].Str.FromStr("001"); + aPanel->Edit[2].SetInputMaskEn(); + aPanel->Edit[2].SetMaxLen(3); + aPanel->Edit[2].Pst = 2; + aPanel->Edit[3].Str.FromStr("002"); + aPanel->Edit[3].SetInputMaskEn(); + aPanel->Edit[3].SetMaxLen(3); + aPanel->Edit[3].Pst = 2; + aPanel->Edit[4].Str.FromStr("未定义"); + aPanel->Edit[4].SetInputMaskEn(); + aPanel->Edit[4].SetMaxLen(3); + aPanel->Edit[4].Pst = 2; + aPanel->Edit[4].Enable = 0; + + aPanel->Btn[0].Init(700,4,68,34,x,y,1,clFrmFace); + aPanel->Btn[0].Caption.FromStr("解除"); + aPanel->Btn[0].SetCaptionLeftSpacing(6); + aPanel->Btn[0].Enable =1; + aPanel->Btn[0].Visible =1; + aPanel->Btn[0].SelectedColor = clRed; + aPanel->Btn[0].SelectedTextColor = clNearWhite; + + DrawCaption2(); + + aPanel->Show(); + Check4Selected4Part(); + aPanel->ReDrawItems(); + + LoadListStr(); + ShowList(); + ShowType(); +} + +//_____________________________________________________________________________________________________________________________ + +void TUnRegister::ShowList() +{ + int i, x, y; + unsigned int aClr, aAddr, Index, wc; + if(IsViewList){ + aClr = clBlue; + }else{ + aClr = clMedGray; + } + RectFillRender(6,192,10,430,aClr); + RectFillRender(6,192,792,196,aClr); + RectFillRender(6,430,792,434,aClr); + RectFillRender(788,192,792,434,aClr); + + RectFillRender(11,197,787,429,clMoneyGreen); + + i = ListIndex * 14; + wc =0; + for(; i= 14)break; + } + i = ListIndex * 14; + TVScrollBar::sDrawByPoint(767, 197, 786, 428, clBlue, clGray, EntryCount, 14, i); +} + +void TUnRegister::ShowType() +{ + unsigned char aType; + int i; + i = aPanel->Edit[3].Str.ToInteger(); + if(i>255){ + aPanel->Edit[4].Str.FromStr("类型选择超出范围"); + aPanel->Edit[4].TextColor = clRed; + }else + if(i == 0){ + aPanel->Edit[4].Str.FromStr("全部类型"); + aPanel->Edit[4].TextColor = clRed; + }else{ + aType = static_cast(i); + aPanel->Edit[4].Str.FromStr(StrType[aType]); + aPanel->Edit[4].TextColor = clNearBlack; + } + aPanel->Edit[4].Show(); +} + +void TUnRegister::ClearClearAllText() +{ + TMyString::sFromStr(" ", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TUnRegister::ShowClearAllText() +{ + TMyString::sFromStr("执行完成", aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TUnRegister::ClearOutText() +{ + TMyString::sClear(aPanel->SText[5].Text); + aPanel->SText[5].Show(); +} + +void TUnRegister::ShowInputErr() +{ + TMyString::sFromStr(" 输入错误", aPanel->SText[5].Text); + aPanel->SText[5].TextColor = clRed; + aPanel->SText[5].Show(); +} + +void TUnRegister::ShowExResult(int What, int aRst) +{ + if(What ==0){ + if(aRst){ + TMyString::sFromStr(" 回路解除成功", aPanel->SText[5].Text); + aPanel->SText[5].TextColor = clNearBlack; + }else{ + + TMyString::sFromStr(" 回路解除失败", aPanel->SText[5].Text); + aPanel->SText[5].TextColor = clNearBlack; + } + }else + if(What == 1){ + if(aRst){ + TMyString::sFromStr("地址段解除成功", aPanel->SText[5].Text); + aPanel->SText[5].TextColor = clNearBlack; + }else{ + + TMyString::sFromStr("地址段解除失败", aPanel->SText[5].Text); + aPanel->SText[5].TextColor = clNearBlack; + } + }else + if(What == 2){ + if(aRst){ + TMyString::sFromStr("单地址解除成功", aPanel->SText[5].Text); + aPanel->SText[5].TextColor = clNearBlack; + }else{ + + TMyString::sFromStr("单地址解除失败", aPanel->SText[5].Text); + aPanel->SText[5].TextColor = clNearBlack; + } + } + + aPanel->SText[5].Show(); +} + +void TUnRegister::TryIncValue() +{ + int i; + if(IsViewList)return; + if(CtlIndex == 0){ + i = aPanel->Edit[0].Str.ToInteger(); + if(i<255){ + i++; + aPanel->Edit[0].Str.FromUInt2Dg(i); + aPanel->Edit[0].Show(); + } + }else + if(CtlIndex == 1){ + i = aPanel->Edit[1].Str.ToInteger(); + if(i<255){ + i++; + aPanel->Edit[1].Str.FromUInt3Dg(i); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 2){ + i = aPanel->Edit[2].Str.ToInteger(); + if(i<255){ + i++; + aPanel->Edit[2].Str.FromUInt3Dg(i); + aPanel->Edit[2].Show(); + } + }else + if(CtlIndex == 3){ + i = aPanel->Edit[3].Str.ToInteger(); + if(i<255){ + i++; + aPanel->Edit[3].Str.FromUInt3Dg(i); + aPanel->Edit[3].Show(); + ShowType(); + } + } +} + + +void TUnRegister::TryDecValue() +{ + int i; + if(IsViewList)return; + if(CtlIndex == 0){ + i = aPanel->Edit[0].Str.ToInteger(); + if(i>0){ + i--; + aPanel->Edit[0].Str.FromUInt2Dg(i); + aPanel->Edit[0].Show(); + } + }else + if(CtlIndex == 1){ + i = aPanel->Edit[1].Str.ToInteger(); + if(i>0){ + i--; + aPanel->Edit[1].Str.FromUInt3Dg(i); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 2){ + i = aPanel->Edit[2].Str.ToInteger(); + if(i>0){ + i--; + aPanel->Edit[2].Str.FromUInt3Dg(i); + aPanel->Edit[2].Show(); + } + }else + if(CtlIndex == 3){ + i = aPanel->Edit[3].Str.ToInteger(); + if(i>0){ + i--; + aPanel->Edit[3].Str.FromUInt3Dg(i); + aPanel->Edit[3].Show(); + ShowType(); + } + } +} + +void TUnRegister::LoadListStr() +{ + int i; + unsigned int aAddr; + char cText[4] = "未"; + EntryCount = 0; + for(i=0; i<256; i++){ + aAddr = dAddrSdRam_Register + (i * 4); + *(volatile unsigned int *)(aAddr) = 0; + + } + for(i=0; i<256; i++){ + if(StrType[i][0] != cText[0]){ + aAddr = dAddrSdRam_Register + (EntryCount * 4); + *(volatile unsigned int *)(aAddr) = i; + EntryCount++; + }else{ + continue; + } + } + PageCount = EntryCount / 14; + if(EntryCount % 14){ + PageCount++; + } +} + + + +TGuiMsgReturn TUnRegister::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + TDMix aFullPath; + if(IsAskingRemoveWhat){ + switch(aKey){ + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <1){ + CtlIndex++; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 1; + aPanel->ReDrawItems(); + } + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + IsAskingRemoveWhat = 0; + IsRemoveAll = 1; + CtlIndex = 0; + InitPanel4All(); + }else{ + IsAskingRemoveWhat = 0; + IsRemoveAll = 0; + CtlIndex = 0; + RenderBackGround(); + InitPanel4Part(); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + return aMsg; + } + + if(IsRemoveAll){ + switch(aKey){ + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + aPanel->Btn[0].Selected = 1; + aPanel->Btn[1].Selected = 0; + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <1){ + CtlIndex++; + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 1; + aPanel->ReDrawItems(); + } + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + //Start to Clear All + ClearClearAllText(); + + SendCmdClearAll(); + + ShowClearAllText(); + }else{ + //Cancel and Return + aMsg = guiMsgReturn; + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + + } + return aMsg; + }else{ + if(IsViewList == 0){ + switch(aKey){ + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_DELETE: + if(aPanel->Edit[0].Selected){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + + }else + if(aPanel->Edit[1].Selected){ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + }else + if(aPanel->Edit[2].Selected){ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + }else + if(aPanel->Edit[3].Selected){ + aPanel->Edit[3].KeyIn(aKey); + aPanel->Edit[3].Show(); + ShowType(); + } + break; + case VK_LEFT: + if(CtlIndex == 0){ + if(aPanel->Edit[0].Pst <0){ + CtlIndex = 4; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + } + }else + if(CtlIndex == 1){ + if(aPanel->Edit[1].Pst <0){ + CtlIndex--; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 2){ + if(aPanel->Edit[2].Pst <0){ + CtlIndex--; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + } + }else + if(CtlIndex == 3){ + if(aPanel->Edit[3].Pst <0){ + CtlIndex--; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[3].KeyIn(aKey); + aPanel->Edit[3].Show(); + ShowType(); + } + }else + if(CtlIndex == 4){ + CtlIndex--; + Check4Selected4Part(); + aPanel->ReDrawItems(); + } + break; + case VK_RIGHT: + if(CtlIndex == 0){ + if(aPanel->Edit[0].Pst > 0){ + CtlIndex ++; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + } + }else + if(CtlIndex == 1){ + if(aPanel->Edit[1].Pst >1){ + CtlIndex ++; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 2){ + if(aPanel->Edit[2].Pst >1){ + CtlIndex++; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + } + }else + if(CtlIndex == 3){ + if(aPanel->Edit[3].Pst >1){ + CtlIndex++; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[3].KeyIn(aKey); + aPanel->Edit[3].Show(); + ShowType(); + } + }else + if(CtlIndex == 4){ + CtlIndex =0; + Check4Selected4Part(); + aPanel->ReDrawItems(); + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + CtlIndex=3; + Check4Selected4Part(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <4){ + CtlIndex++; + Check4Selected4Part(); + aPanel->ReDrawItems(); + }else{ + CtlIndex=0; + Check4Selected4Part(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + IsViewList = 1; + Check4Selected4Part(); + aPanel->ReDrawItems(); + ShowList(); + break; + case dfKEY_SETUP: + TryDecValue(); + break; + case dfKEY_QUERY: + TryIncValue(); + break; + case VK_EXECUTE: + //Do Remove Here + if(1){ + ClearOutText(); + SendCmdClear(); + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case VK_UP: + if(ListIndex >0){ + ListIndex--; + ShowList(); + } + break; + case VK_DOWN: + if(ListIndex < (PageCount -1)){ + ListIndex++; + ShowList(); + } + break; + case VK_TAB: + IsViewList = 0; + CtlIndex=2; + Check4Selected4Part(); + aPanel->ReDrawItems(); + ShowList(); + break; + case VK_EXECUTE: + + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + } + } + return aMsg; +} + +void TUnRegister::SendCmdClearAll() +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearAllRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = 0xFe; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TUnRegister::SendCmdClearOnePort(unsigned char aCc) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearSinglePortRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TUnRegister::SendCmdClearMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr, unsigned char aType) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearSinglePortRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + Data[3] = sAddr; + Data[4] = eAddr; + Data[5] = aType; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TUnRegister::SendCmdClearOneAddr(unsigned char aCc, unsigned char aAddr, unsigned char aType) +{ + TCanHeaderID aIde; + unsigned char cVal; + unsigned int i; + unsigned int Len; + int iVal; + + Len =3; + + aIde.BitF.Cmd = cmClearSinglePortAddrRegist; + for(i=0; i<8; i++){ + Data[i] = 0; + } + + Data[0] = 0; + Data[1] = 0; + Data[2] = aCc; + Data[3] = aAddr; + Data[4] = aAddr; + Data[5] = aType; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data, Len); +} + +void TUnRegister::SendCmdClear() +{ + unsigned int iVal; + unsigned char aCc, sAddr, eAddr, aType; + unsigned int Err = 0; + + iVal = aPanel->Edit[0].Str.ToInteger(); + if(iVal ==0)Err=1; + if(iVal > 40)Err=1; + aCc = static_cast(iVal); + + iVal = aPanel->Edit[1].Str.ToInteger(); + if(iVal == 0)Err=1; + if(iVal > 250)Err=1; + sAddr = static_cast(iVal); + + iVal = aPanel->Edit[2].Str.ToInteger(); + if(iVal == 0)Err=1; + if(iVal > 250)Err=1; + eAddr = static_cast(iVal); + + iVal = aPanel->Edit[3].Str.ToInteger(); + if(iVal > 255)Err=1; + aType = static_cast(iVal); + + if(Err == 0){ + if(sAddr == eAddr){ + //Remove One Addr + SendCmdClearOneAddr(aCc,sAddr,aType); + ShowExResult(2,1); + }else{ + if( (sAddr == 1) && (eAddr == 250) ){ + //Remove One Port + SendCmdClearOnePort(aCc); + ShowExResult(0,1); + }else{ + if(sAddr < eAddr){ + //Remove From Addr to Addr + SendCmdClearMultAddr(aCc, sAddr, eAddr, aType); + ShowExResult(1,1); + }else{ + Err = 1; + } + } + } + } + + if(Err){ + ShowInputErr(); + } +} + + + + diff --git a/MyCode/Gui/UnRegister.h b/MyCode/Gui/UnRegister.h new file mode 100644 index 0000000..4dd016b --- /dev/null +++ b/MyCode/Gui/UnRegister.h @@ -0,0 +1,88 @@ +#ifndef UNREGISTER_H_ +#define UNREGISTER_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TUnRegister{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + u32 Color; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + TMyString Str; + + unsigned char CtlIndex; + unsigned char ListIndex; + unsigned char IsViewList; + unsigned char EntryCount; + unsigned char PageCount; + unsigned char IsRemoveAll; + unsigned char IsAskingRemoveWhat; + + unsigned char Data[8]; + unsigned char RecData[8]; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8, int w9); + public: + TUnRegister(){}; + TUnRegister(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void ShowList(); + void ShowType(); + void ClearClearAllText(); + void ShowClearAllText(); + void ClearOutText(); + void ShowInputErr(); + void ShowExResult(int What, int aRst); + + void Show(void); + void ShowCaption(); + void ReDraw(void); + void DrawCaption2(void); + + void TryIncValue(); + void TryDecValue(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(void); + void InitPanel4All(void); + void InitPanel4Part(void); + void Check4Selected4Part(void); + void LoadListStr(); + + void SendCmdClearAll(); + + void SendCmdClearOnePort(unsigned char aCc); + void SendCmdClearMultAddr(unsigned char aCc, unsigned char sAddr, unsigned char eAddr, unsigned char aType); + void SendCmdClearOneAddr(unsigned char aCc, unsigned char aAddr, unsigned char aType); + void SendCmdClear(); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/UserCodeSet.cpp b/MyCode/Gui/UserCodeSet.cpp new file mode 100644 index 0000000..d96c6ce --- /dev/null +++ b/MyCode/Gui/UserCodeSet.cpp @@ -0,0 +1,1238 @@ +#include "UserCodeSet.h" +#include "Runtime.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "HW_config.h" +} + +//#define dFlash4AreaChip (0) +//#define dFlash4Area (0x00BB'0000) + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const int xInc = 84; +const int xDec = 180; +const int xModify = 84; +const int xSave = 180; + +static const char CharBcdText[20]= {"0123456789*------\0"}; + +void TUserCodeSet::Init() +{ + IsPermission =0; + + CtlIndex = 0; + IsShow = 0; + ListPage = 0; + + PortNum = 0; + AddrStart =0; + AddrEnd =0; + dType =0; + + PortValid = 1; + AddrStartValid =1; + AddrEndValid =1; + dTypeValid =1; + + IncDec = 0; + + Sta =0; +} + +void TUserCodeSet::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick二次码编辑"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "回路号"); + TextRender_string24(Lv.Grid.Left[0] + 186, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 286, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +44, clNearWhite, "地址段"); + TextRender_string24(Lv.Grid.Left[0] + 136, Lv.Grid.Top[0] +44, clNearWhite, "-"); + TextRender_string24(Lv.Grid.Left[0] + 240, Lv.Grid.Top[0] +44, clNearWhite, "起始地址指派类型"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "起始地址分区简称"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "通配二次码"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "置换二次码"); + TextRender_string24(Lv.Grid.Left[4] + 10, Lv.Grid.Top[4] +6, clNearWhite, "模式"); + TextRender_string24(Lv.Grid.Left[4] + xInc +30, Lv.Grid.Top[4] +8, clNearWhite, "递增"); + TextRender_string24(Lv.Grid.Left[4] + xDec +30, Lv.Grid.Top[4] +8, clNearWhite, "递减"); + TextRender_string24(Lv.Grid.Left[5] + 10, Lv.Grid.Top[5] +6, clNearWhite, "操作"); + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[5] + 6, 76, 30, 7, clNearWhite, "确认", 14, clNearBlack); + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[5] + 6, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Linkage->Aux ID Setting"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "LoopID"); + TextRender_string24(Lv.Grid.Left[0] + 186, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 286, Lv.Grid.Top[0] +6, clNearWhite, " Local"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +44, clNearWhite, "Range"); + TextRender_string24(Lv.Grid.Left[0] + 136, Lv.Grid.Top[0] +44, clNearWhite, "-"); + TextRender_string24(Lv.Grid.Left[0] + 240, Lv.Grid.Top[0] +44, clNearWhite, " Device Type"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Zone Brief"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "ID With * "); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "ReplaceNum"); + TextRender_string24(Lv.Grid.Left[4] + 10, Lv.Grid.Top[4] +6, clNearWhite, "Mode"); + TextRender_string24(Lv.Grid.Left[4] + xInc +30, Lv.Grid.Top[4] +8, clNearWhite, "Inc "); + TextRender_string24(Lv.Grid.Left[4] + xDec +30, Lv.Grid.Top[4] +8, clNearWhite, "Dec "); + TextRender_string24(Lv.Grid.Left[5] + 10, Lv.Grid.Top[5] +6, clNearWhite, "Opera"); + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[5] + 6, 76, 30, 7, clNearWhite, "View", 14, clNearBlack); + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[5] + 6, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + } +} + +void TUserCodeSet::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iSTextDType.Init(Lv.Grid.Left[0] + 492, Lv.Grid.Top[0] +44, 300, 32, 0,0, clNearWhite, ItemColor); + IList->STextDType.TextClear(); + IList->STextDType.Visible = 1; + + //Port Num + IList->EditPortNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] +4, 48, 30, 0,0,1,clNearWhite); + IList->EditPortNum.Str.Clear(); + IList->EditPortNum.SetMaxLen(2); + IList->EditPortNum.Enable =1; + + //Start Addr + IList->EditAddrNum.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] +40, 48, 30, 0,0,1,clNearWhite); + IList->EditAddrNum.Str.Clear(); + IList->EditAddrNum.SetMaxLen(3); + IList->EditAddrNum.Enable =1; + + //End Addr + IList->Edit[0].Init(Lv.Grid.Left[0] + 152, Lv.Grid.Top[0] +40, 48, 30, 0,0,1,clNearWhite); + IList->Edit[0].Str.Clear(); + IList->Edit[0].SetMaxLen(3); + IList->Edit[0].Enable =1; + + //Assign Type + IList->EditCtlNum.Init(Lv.Grid.Left[0] + 440, Lv.Grid.Top[0] +40, 48, 30, 0,0,1,clNearWhite); + IList->EditCtlNum.Str.Clear(); + IList->EditCtlNum.SetMaxLen(3); + IList->EditCtlNum.Enable =0; + + //Short Name + IList->Edit[1].Init(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +36, 270, 30, 0,0,1,clNearWhite); + IList->Edit[1].Str.Clear(); + IList->Edit[1].Enable =0; + + //Descp + //mlEdit.Init(Lv.Grid.Left[2] +10, Lv.Grid.Top[2] +32, 270, 64, 0,0,1,clNearWhite); + //mlEdit.SetLineSpacing(4); + //mlEdit.Str.Clear(); + //mlEdit.Enable =0; + + //Prv UserCode + IList->Edit[2].Init(Lv.Grid.Left[2] + 132, Lv.Grid.Top[2] +4, 110, 30, 0,0,1,clNearWhite); + IList->Edit[2].SetMaxLen(8); + IList->Edit[2].Str.Clear(); + IList->Edit[2].Enable =1; + + //New UserCode + IList->Edit[3].Init(Lv.Grid.Left[3] + 132, Lv.Grid.Top[3] +4, 110, 30, 0,0,1,clNearWhite); + IList->Edit[3].SetMaxLen(8); + IList->Edit[3].Str.Clear(); + IList->Edit[3].Enable =1; + + IList->EditPortNum.Str.FromUInt2Dg(PortNum+1); + IList->EditAddrNum.Str.FromUInt3Dg(AddrStart+1); + IList->Edit[0].Str.FromUInt3Dg(AddrEnd+1); + IList->EditCtlNum.Str.FromUInt3Dg(dType); + IList->EditPortNum.SetPstTail(); + IList->EditAddrNum.SetPstTail(); + IList->Edit[0].SetPstTail(); + IList->EditCtlNum.SetPstTail(); + + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->Edit[0].Show(); + IList->EditCtlNum.Show(); + IList->STextDType.Show(); + IList->Edit[1].Show(); + IList->Edit[2].Show(); + IList->Edit[3].Show(); + //IList->EditAreaAssign.Show(); + //mlEdit.Show(); + DrawFixText(); + DrawIncDec(); + + Check4Selected(); +} + +void TUserCodeSet::Show(void) +{ + IsShow = 1; + RenderBackGround(); + DrawSelf(); + DrawList(); +} + +void TUserCodeSet::DrawIncDec() +{ + if(IncDec==0){ + TRoundSquare::sDrawBySize(xInc, Lv.Grid.Top[4] + 8, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(xDec, Lv.Grid.Top[4] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + }else{ + TRoundSquare::sDrawBySize(xInc, Lv.Grid.Top[4] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(xDec, Lv.Grid.Top[4] + 8, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + } +} + +void TUserCodeSet::ShowSta() +{ + if(LanguageEnCn==0){ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "保存成功"); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "保存失败"); + }else + if(Sta == -2){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "无效操作"); + } + }else{ + if(Sta == 0){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, " "); + }else + if(Sta == 1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Saved OK"); + }else + if(Sta == -1){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Failed "); + }else + if(Sta == -2){ + TextRender_string24(ResultTipPoint.x, ResultTipPoint.y, clNearWhite, ItemColor, "Invalid "); + } + } +} + +void TUserCodeSet::ShowSta(int aSta) +{ + Sta = aSta; + ShowSta(); +} + +void TUserCodeSet::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + ShowSta(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<3; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + + TextDigitRender2_24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + DrawFixText(); + + IList->STextDType.Show(); + IList->EditPortNum.Show(); + IList->EditAddrNum.Show(); + IList->Edit[0].Show(); + IList->EditCtlNum.Show(); + IList->Edit[1].Show(); + IList->Edit[2].Show(); + + Check4Selected(); + + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + + +//______________________________________________________________________________________________________________________________ +void TUserCodeSet::ClearSelected(void) +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->EditPortNum.Selected =0; + IList->EditPortNum.Show(); + break; + case 1: + IList->EditAddrNum.Selected =0; + IList->EditAddrNum.Show(); + break; + case 2: + IList->Edit[0].Selected =0; + IList->Edit[0].Show(); + break; + case 3: + IList->Edit[2].Selected =0; + IList->Edit[2].Show(); + break; + case 4: + IList->Edit[3].Selected =0; + IList->Edit[3].Show(); + break; + case 5: + TRoundSquare::sSelected(xInc, Lv.Grid.Top[4]+8, dWWidth, dWHeigh, 4, ItemColor); + break; + case 6: + TRoundSquare::sSelected(xDec, Lv.Grid.Top[4]+8, dWWidth, dWHeigh, 4, ItemColor); + break; + case 7: + if(LanguageEnCn==0)tText="确定"; else tText="View"; + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[5] + 6, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[5] + 6, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + default: + + break; + } +} + +void TUserCodeSet::Check4Selected(void) +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->EditPortNum.Selected =1; + IList->EditPortNum.SetPstTail(); + IList->EditPortNum.Show(); + break; + case 1: + IList->EditAddrNum.Selected =1; + IList->EditAddrNum.SetPstTail(); + IList->EditAddrNum.Show(); + break; + case 2: + IList->Edit[0].Selected =1; + IList->Edit[0].SetPstTail(); + IList->Edit[0].Show(); + break; + case 3: + IList->Edit[2].Selected =1; + IList->Edit[2].SetPstTail(); + IList->Edit[2].Show(); + break; + case 4: + IList->Edit[3].Selected =1; + IList->Edit[3].SetPstTail(); + IList->Edit[3].Show(); + break; + case 5: + TRoundSquare::sSelected(xInc, Lv.Grid.Top[4]+8, dWWidth, dWHeigh, 4, clNearWhite); + //sDrawBySize(int x, int y, int aW, int aH, int RoundR, u32 aClr, int Active); + break; + case 6: + TRoundSquare::sSelected(xDec, Lv.Grid.Top[4]+8, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 7: + if(LanguageEnCn==0)tText="确定"; else tText="View"; + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[5] + 6, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 8: + if(LanguageEnCn==0)tText="保存"; else tText="Save"; + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[5] + 6, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + default: + + break; + } +} + +void TUserCodeSet::PermissionCmdGO() +{ + if((PermissionCmd == 1) || (PermissionCmd == 2)){ + if(0 == DrawDetail()){ + Write2Flash(); + }else{ + ShowSta(-2); + } + } +} + +void TUserCodeSet::PermissionCmdReturnDraw() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +void TUserCodeSet::InitPanel() +{ + int x,y,x2,y2, aW,aH,i; + + x = 10; + y = 240; + x2 = 789; + y2 = 430; + aW = x2 - x +1; + aH = y2 -y +1; + + aPanel->Init(x,y,aW,aH,0,0,clMoneyGreen, bvRaised); + + aPanel->Caption.Init(1,1,aW-3,32,x,y,clNearWhite,clBlue); + if(LanguageEnCn==0)aPanel->Caption.SetText("按中/EN键切换输入法,设置键保存更改,返回键放弃更改并返回",24); + else aPanel->Caption.SetText("Key 中/EN To Switch Input Method,Key Set To Save",24); + aPanel->Caption.Enable = 1; + aPanel->Caption.Visible = 1; + + aPanel->SText[0].Init(460,40,300,34,x,y,clNearBlack,clMoneyGreen); + if(LanguageEnCn==0)TMyString::sFromStr("当前快捷输入数字", aPanel->SText[0].Text); + else TMyString::sFromStr("Enter Numbers", aPanel->SText[0].Text); + aPanel->SText[0].Enable = 1; + aPanel->SText[0].Visible = 1; + + aPanel->Edit[ 0].Init(10,40,420,30,x,y,1,clNearBlack); + aPanel->Edit[ 0].Str.FromStr(IList->EditDescpShow.Str.Text); + + for(i=0; i<1;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetMaxLen(32); + aPanel->Edit[i].SetPstTail(); + aPanel->Edit[i].Selected = 1; + } + + aPanel->Show(); + aPanel->Caption.Show(); + aPanel->SText[0].Show(); + aPanel->Edit[0].Show(); + aPanel->Edit[0].ShowCursor(); +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TUserCodeSet::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + int iVal; + int HadPrc; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + HadPrc =0; + if( (aKey == VK_LEFT) || (aKey == VK_RIGHT) ){ + if(CtlIndex == 1){ + if(aKey == VK_RIGHT){ + if(IList->EditAddrNum.Pst >= IList->EditAddrNum.Str.GetEndPst()){ + if( (PortValid + dTypeValid + AddrStartValid + AddrEndValid) == 4){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + } + } + }else + if(CtlIndex == 2){ + if(aKey == VK_LEFT){ + if(IList->Edit[0].Pst <0){ + if( (PortValid + dTypeValid + AddrStartValid + AddrEndValid) == 4){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + } + } + }else + if(CtlIndex == 5){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 6){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 7){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 8){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + } + } + if(HadPrc == 0){ + if(CtlIndex == 0){ + IList->EditPortNum.KeyIn(aKey); + int iVal; + iVal = IList->EditPortNum.Str.ToInteger(); + if( (iVal <1) || (iVal > dPORT_MAX_COUNT) ){ + PortValid =0; + IList->EditPortNum.SelectedColor = clRed; + }else{ + PortValid =1; + IList->EditPortNum.SelectedColor = clBlue; + iVal--; + if(iVal != PortNum){ + PortNum = iVal; + LoadData(); + } + } + IList->EditPortNum.Show(); + }else + if(CtlIndex == 1){ + IList->EditAddrNum.KeyIn(aKey); + int iVal; + iVal = IList->EditAddrNum.Str.ToInteger(); + if( (iVal <1) || (iVal > dEP_MAX_COUNT_PER_PORT) ){ + AddrStartValid =0; + IList->EditAddrNum.SelectedColor = clRed; + }else{ + AddrStartValid =1; + IList->EditAddrNum.SelectedColor = clBlue; + iVal--; + if(iVal != AddrStart){ + AddrStart = iVal; + LoadData(); + } + } + IList->EditAddrNum.Show(); + }else + if(CtlIndex == 2){ + IList->Edit[0].KeyIn(aKey); + int iVal; + iVal = IList->Edit[0].Str.ToInteger(); + if( (iVal <1) || (iVal > dEP_MAX_COUNT_PER_PORT) ){ + AddrEndValid =0; + IList->Edit[0].SelectedColor = clRed; + }else{ + AddrEndValid =1; + IList->Edit[0].SelectedColor = clBlue; + iVal--; + if(iVal != AddrEnd){ + AddrEnd = iVal; + } + } + IList->Edit[0].Show(); + }else + if(CtlIndex == 3){ + IList->Edit[2].KeyIn(aKey); + IList->Edit[2].Show(); + }else + if(CtlIndex == 4){ + IList->Edit[3].KeyIn(aKey); + IList->Edit[3].Show(); + } + } + break; + case dfKEY_ASTERISK: + if(CtlIndex == 3){ + IList->Edit[2].KeyIn(aKey); + IList->Edit[2].Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + if( (PortValid + dTypeValid + AddrStartValid + AddrEndValid) == 4){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + } + }else{ + if( (PortValid + dTypeValid + AddrStartValid + AddrEndValid) == 4){ + ClearSelected(); + CtlIndex =8; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(CtlIndex <8){ + if( (PortValid + dTypeValid + AddrStartValid + AddrEndValid) == 4){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + break; + + case VK_TAB: + //IsList = 1; + //DrawList(); + //ClearSelected(); + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + if( (CtlIndex == 5) || (CtlIndex == 6) ){ + IncDec = IncDec ? 0 :1; + DrawIncDec(); + } + break; + case VK_EXECUTE: + if( (CtlIndex == 5) || (CtlIndex == 6) ){ + IncDec = IncDec ? 0 :1; + DrawIncDec(); + }else + if(CtlIndex == 7){ + DrawDetail(); + }else + if(CtlIndex == 8){ + //Save Data Here + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default : + break; + } + + if(VK_EXECUTE != aKey){ + ShowSta(0); + } + } + + return aMsg; +} + +void TUserCodeSet::LoadAssignType() +{ + int i; + unsigned int Idf, aOrd, sAddr; + unsigned char AssignType; + + if( (PortNum < dPORT_MAX_COUNT ) && (AddrStart < dEP_MAX_COUNT_PER_PORT) ){ + AssignType = Port[PortNum].AssignType[AddrStart]; + IList->EditCtlNum.Str.FromUInt3Dg(AssignType); + if(LanguageEnCn==0)IList->STextDType.SetText(StrTypeShortName[AssignType] ,24); + else IList->STextDType.SetText(StrTypeShortNameEn[AssignType] ,24); + }else{ + IList->EditCtlNum.Str.FromStr("---"); + IList->STextDType.SetText("----" ,24); + } + IList->EditCtlNum.Show(); + IList->STextDType.Show(); +} + +void TUserCodeSet::LoadUcBcdText() +{ + int i; + unsigned int Idf, aOrd, sAddr; + + if( (PortNum < dPORT_MAX_COUNT ) && (AddrStart < dEP_MAX_COUNT_PER_PORT) ){ + IList->Edit[2].Str.FromUInt8Dg(Port[PortNum].UcList[AddrStart].Full); + }else{ + IList->Edit[2].Str.FromStr("00000000"); + } + IList->Edit[2].Show(); +} + +void TUserCodeSet::LoadShortName() +{ + unsigned int Idf, sAddr; + + if( (PortNum < dPORT_MAX_COUNT ) && (AddrStart < dEP_MAX_COUNT_PER_PORT) ){ + AreaNum = Port[PortNum].Area[AddrStart]; + if(AreaNum){ + AreaNum--; + }else{ + AreaNum = dAreaCountMax +10; + } + }else{ + AreaNum = dAreaCountMax +10;; + } + + if(AreaNum >= dAreaCountMax ){ + IList->Edit[1].Str.FromStr("------"); + IList->Edit[1].Show(); + return; + } + + sAddr = dAddrSdRam_4Area + (AreaNum * 64); + Idf = *(volatile unsigned int *)(sAddr); + if(Idf == 0xA8A7A6A5){ + sAddr = dAddrSdRam_4Area + (AreaNum * 64) + 16; + for(int i=0; i<16; i++){ + IList->Edit[1].Str.Text[i] = *(volatile unsigned char *)(sAddr +i); + } + IList->Edit[1].Str.Text[16] = '\0'; + }else{ + IList->Edit[1].Str.Text[0] = '\0'; + IList->Edit[1].Str.Text[1] = '\0'; + } + IList->Edit[1].Show(); +} + +void TUserCodeSet::LoadData() +{ + LoadAssignType(); + LoadUcBcdText(); + LoadShortName(); +} + +int TUserCodeSet::DrawDetail() +{ + int x,y, Pst; + char tText[16]; + unsigned int tUc, HadGotAsFinished; + int AstStartPoint, AstEndPoint, AstLength, InputLength, InputVal, Step; + x = Lv.Panel.Left +4; + y = Lv.Panel.Top +4; + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + if(LanguageEnCn==0){ + if(PortNum >= dPORT_MAX_COUNT){ + TextRender_string24(x, y, clNearWhite, "回路号不正确"); + return -1; + }else + if(AddrStart >= dEP_MAX_COUNT_PER_PORT){ + TextRender_string24(x, y, clNearWhite, "起始地址不正确"); + return -1; + }else + if(AddrEnd >= dEP_MAX_COUNT_PER_PORT){ + TextRender_string24(x, y, clNearWhite, "结束地址不正确"); + return -1; + }else + if(AddrStart > AddrEnd){ + TextRender_string24(x, y, clNearWhite, "起始-结束 地址不正确"); + return -1; + } + + if(IList->Edit[2].Str.Text[8] != '\0'){ + TextRender_string24(x, y, clNearWhite, "通配二次码超出长度"); + return -1; + } + }else{ + if(PortNum >= dPORT_MAX_COUNT){ + TextRender_string24(x, y, clNearWhite, "Loop ID Invalid"); + return -1; + }else + if(AddrStart >= dEP_MAX_COUNT_PER_PORT){ + TextRender_string24(x, y, clNearWhite, "Begin Addr Invalid"); + return -1; + }else + if(AddrEnd >= dEP_MAX_COUNT_PER_PORT){ + TextRender_string24(x, y, clNearWhite, "End Addr Invalid"); + return -1; + }else + if(AddrStart > AddrEnd){ + TextRender_string24(x, y, clNearWhite, "Begin-End Addr Invalid"); + return -1; + } + + if(IList->Edit[2].Str.Text[8] != '\0'){ + TextRender_string24(x, y, clNearWhite, "Aux ID Invalid"); + return -1; + } + } + Step =0; + GotAst = 0; + HadGotAsFinished =0; + for(int i=0; i<16; i++)tText[i] = '\0'; + for(Pst=0; Pst<8; Pst++){ + if(IList->Edit[2].Str.Text[Pst] != '\0'){ + if(HadGotAsFinished == 1){ + if(IList->Edit[2].Str.Text[Pst] == '*'){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "通配二次码存在两段或以上的通配字段"); + else TextRender_string24(x, y, clNearWhite, "Invalid,Aux ID 2 Paragraphs Wildcard"); + return -1; + }else{ + tText[Pst] = IList->Edit[2].Str.Text[Pst]; + Step++; + } + }else{ + if(IList->Edit[2].Str.Text[Pst] == '*'){ + tText[Pst] = '0'; + if(GotAst == 0)AstStartPoint = Pst; + GotAst =1; + AstEndPoint = Pst; + }else{ + tText[Pst] = IList->Edit[2].Str.Text[Pst]; + if(GotAst){ + HadGotAsFinished = 1; + Step++; + } + } + } + }else{ + break; + } + } + UserCodeItv = 1; + for(int i=0; i< Step; i++){ + UserCodeItv *= 10; + } + AstLength = AstEndPoint - AstStartPoint +1; + if(IList->Edit[3].Str.Text[8] != '\0'){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "新二次码长度超出范围"); + else TextRender_string24(x, y, clNearWhite, "New Aux ID Invalid"); //value out of range + return -1; + } + InputLength =0; + for(int i=0; i<8; i++){ + if(IList->Edit[3].Str.Text[i] != '\0')InputLength++; + else break; + } + InputVal = IList->Edit[3].Str.ToInteger(); + + if(GotAst){ + if(InputLength > AstLength){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "新二次码长度超出通配字段长度"); + else TextRender_string24(x, y, clNearWhite, "Replacing Num Out Of Wildcard"); + return -1; + } + unsigned int tScope =1; + for(int i=0, z=0; (i<8) && (zEdit[3].Str.ToInteger(); + if(IncDec == 0){ + if( (InputVal + (AddrEnd - AddrStart) ) > tScope){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "通配字段递增溢出"); + else TextRender_string24(x, y, clNearWhite, "Invalid,Value Out Of Range"); + return -1; + } + }else{ + if( (InputVal - (AddrEnd - AddrStart) ) < 0){ + if(LanguageEnCn)TextRender_string24(x, y, clNearWhite, "通配字段递减溢出"); + else TextRender_string24(x, y, clNearWhite, "Invalid,Value Out Of Range"); + return -1; + } + } + + + + UserCodePrv = TMyString::sToInteger(tText); + if(UserCodePrv>99'999'999)UserCodePrv=99'999'999; + if(UserCodePrv==0)UserCodePrv=1; + UserCodeStart = UserCodePrv + (InputVal * UserCodeItv); + if(UserCodeStart>99'999'999)UserCodeStart=99'999'999; + else if(UserCodeStart==0)UserCodeStart=1; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "使用通配字:"); + x += 132; + TextDigitRender8_24(x, y, clNearWhite, UserCodePrv); + x += 110; + TextRender_string24(x, y, clNearWhite, "开始"); + x += 48; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeItv); + }else{ + TextRender_string24(x, y, clNearWhite, "With Wildcard"); + x += 13 *12; + TextDigitRender8_24(x, y, clNearWhite, UserCodePrv); + x += 110; + TextRender_string24(x, y, clNearWhite, "Begin"); + x += 5*12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeItv); + } + }else{ + UserCodeStart = IList->Edit[2].Str.ToInteger(); + if(UserCodeStart>99'999'999)UserCodeStart=99'999'999; + else if(UserCodeStart==0)UserCodeStart=1; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "无通配字 开始:"); + x += 170; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, 1); + }else{ + TextRender_string24(x, y, clNearWhite, "Without Wildcard"); + x += 16*12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, 1); + } + } + + IList->RealtimeData.Reset(); + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "写入条目数量:"); + x += 156; + }else{ + TextRender_string24(x, y, clNearWhite, "Numbers Of Items:"); + x += 17*12; + } + TextDigitRender5_24(x, y, clNearWhite, AddrEnd-AddrStart+1); + x += 72; + TextDigitRender5_24(x, y, clNearWhite, AddrStart+1); + x += 72; + TextRender_string24(x, y, clNearWhite, "-"); + x += 12; + TextDigitRender3_24(x, y, clNearWhite, AddrEnd+1); + + + const int Count = AddrEnd - AddrStart +1; + tUc = UserCodeStart; + int aAddr = AddrStart; + if(Count < 7){ + for(int i=0; i"); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, tUc ); + + if(IncDec==0){ + tUc += UserCodeItv; + if( (tUc>99'999'999) || (tUc==0) )tUc=1; + }else{ + tUc -= UserCodeItv; + if( (tUc>99'999'999) || (tUc==0) )tUc=99'999'999; + } + aAddr ++; + } + }else{ + for(int i=0; i(Count-4)) ){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "回路:"); + else TextRender_string24(x, y, clNearWhite, "Loop:"); + x += 60; + TextDigitRender2_24(x, y, clNearWhite, PortNum+1); + x += 36; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "地址:"); + else TextRender_string24(x, y, clNearWhite, "Addr:"); + x += 60; + TextDigitRender3_24(x, y, clNearWhite, aAddr+1); + x += 60; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "原:"); + else TextRender_string24(x, y, clNearWhite, " "); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, Port[PortNum].UcList[aAddr].Full ); + x += 100; + TextRender_string24(x, y, clNearWhite, "-->"); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, tUc ); + } + if( i==3){ + x = Lv.Panel.Left + 200; + y+=28; + TextRender_string24(x, y, clNearWhite, "............"); + } + + if(IncDec==0){ + tUc += UserCodeItv; + if( (tUc>99'999'999) || (tUc==0) )tUc=1; + }else{ + tUc -= UserCodeItv; + if( (tUc>99'999'999) || (tUc==0) )tUc=99'999'999; + } + aAddr ++; + } + } + + return 0; +} + +void TUserCodeSet::Write2Flash() +{ + unsigned int fAddr; + unsigned int i,z; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char wP1; + TDMix tCrc; + + if( (PortValid + dTypeValid + AddrStartValid + AddrEndValid) != 4){ + return; + } + + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (PortNum < dPORT_MAX_COUNT) ){ + fAddr = dFlashAddrDevUserCode + (PortNum * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + DelayMs(100); + + do{ + DelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + aUcFull = UserCodeStart; + Crc32Reset(); + for(i=0; i<64; i++)IList->ReadWriteData.D32[i] = 0; + for(i=0; i<4; i++){ + for(x=0;x<64;x++){ + IList->ReadWriteData.D32[x] = Port[PortNum].UcList[i*64 + x].Full; + if( ( (i*64 + x) >= AddrStart) && ((i*64 + x) <= AddrEnd) ){ + IList->ReadWriteData.D32[x] = aUcFull; + if(IncDec == 0){ + aUcFull += UserCodeItv; + if( (aUcFull >99999999) || (aUcFull==0) )aUcFull =1; + }else{ + aUcFull -= UserCodeItv; + if( (aUcFull >99999999) || (aUcFull==0) )aUcFull =99999999; + } + } + if( (i<3) or (x< (dEP_MAX_COUNT_PER_PORT % 64 ) ) ){ + Crc32Feed(IList->ReadWriteData.D32[x]); + } + } + if(i==3){ + IList->ReadWriteData.D32[63] = Crc32GetResult(); + } + fAddr = dFlashAddrDevUserCode + (PortNum * 4096) + (i * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, IList->ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } + + for(x=0;xReadWriteData.D8[x] = Port[PortNum].AssignType[x]; + if(dType !=0){ + if( (x >= AddrStart) && (x <= AddrEnd) ){ + IList->ReadWriteData.D8[x] = dType; + } + } + } + Crc32Reset(); + for(x=0; x(IList->ReadWriteData.D8[x])); + tCrc.D32 = Crc32GetResult(); + IList->ReadWriteData.D8[252] = tCrc.D8[0]; + IList->ReadWriteData.D8[253] = tCrc.D8[1]; + IList->ReadWriteData.D8[254] = tCrc.D8[2]; + IList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (PortNum * 4096) + (4 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, IList->ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Signal Type + for(x=0;xReadWriteData.D8[x] = Port[PortNum].FuncSetByte[x]; + } + Crc32Reset(); + for(x=0; x(IList->ReadWriteData.D8[x])); + tCrc.D32 = Crc32GetResult(); + IList->ReadWriteData.D8[252] = tCrc.D8[0]; + IList->ReadWriteData.D8[253] = tCrc.D8[1]; + IList->ReadWriteData.D8[254] = tCrc.D8[2]; + IList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (PortNum * 4096) + (5 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, IList->ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } + + Record.ReadDevUserSet(); + + int Count = AddrEnd -AddrEnd +1; + int NotEqOcc =0; + int aAddr = AddrStart; + aUcFull = UserCodeStart; + for(int Gz=0; Gz99999999) || (aUcFull==0) )aUcFull =1; + }else{ + aUcFull -= UserCodeItv; + if( (aUcFull >99999999) || (aUcFull==0) )aUcFull =99999999; + } + aAddr++; + } + + if(NotEqOcc){ + //Error + ShowSta(-1); + }else{ + //OK + ShowSta(1); + } +} + +void TUserCodeSet::DrawList() +{ + int i, z, x, y; + unsigned int aClr, TopInx, sAddr, Idf; + + return; + + IsList ? aClr=clBlue : aClr=clMedGray; + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,PanelColor); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Left +4,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Top +4,aClr); + RectFillRender(Lv.Panel.Right-4,Lv.Panel.Top,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + RectFillRender(Lv.Panel.Left,Lv.Panel.Bottom -4,Lv.Panel.Right,Lv.Panel.Bottom,aClr); + + const unsigned int PageCount = dAreaCountMax / 8; + if(ListPage >= PageCount) ListPage = 0; + + x = Lv.Panel.Left+6; + y = Lv.Panel.Top +6; + TextRender_string24(x, y, clNearBlack, PanelColor, "区域号 配置 简称 二次码"); + TopInx = ListPage * 8; + for(i=0,z=TopInx; (i<8) && (z二次码编辑"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "分区号"); + TextRender_string24(Lv.Grid.Left[0] + 186, Lv.Grid.Top[0] +6, clNearWhite, "机器号"); + TextRender_string24(Lv.Grid.Left[0] + 286, Lv.Grid.Top[0] +6, clNearWhite, "本机"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +44, clNearWhite, "二次码覆盖:"); + TextRender_string24(xRecover +30, Lv.Grid.Top[0] +44, clNearWhite, "覆盖"); + TextRender_string24(xAvoid +30, Lv.Grid.Top[0] +44, clNearWhite, "绕过"); + TextRender_string24(xType, Lv.Grid.Top[0] +44, clNearWhite, "指定类型"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "简称"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "描述"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "新二次码"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "模式"); + TextRender_string24(Lv.Grid.Left[3] + xInc +30, Lv.Grid.Top[3] +8, clNearWhite, "递增"); + //TextRender_string24(Lv.Grid.Left[3] + xDec +30, Lv.Grid.Top[3] +8, clNearWhite, "递减"); + TextRender_string24(Lv.Grid.Left[4] + 10, Lv.Grid.Top[4] +6, clNearWhite, "操作"); + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "确认", 14, clNearBlack); + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "保存", 14, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Linkage->Aux ID Editting By Zone"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Zone"); + TextRender_string24(Lv.Grid.Left[0] + 186, Lv.Grid.Top[0] +6, clNearWhite, "CtlID"); + TextRender_string24(Lv.Grid.Left[0] + 286, Lv.Grid.Top[0] +6, clNearWhite, " Local"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +44, clNearWhite, "Apply Mode"); + TextRender_string24(xRecover +30, Lv.Grid.Top[0] +44, clNearWhite, "Cover"); + TextRender_string24(xAvoid +30, Lv.Grid.Top[0] +44, clNearWhite, "Avoid"); + TextRender_string24(xType, Lv.Grid.Top[0] +44, clNearWhite, " Assign"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Brie"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +40, clNearWhite, "Desc"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "New Aux ID"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "Mode"); + TextRender_string24(Lv.Grid.Left[3] + xInc +30, Lv.Grid.Top[3] +8, clNearWhite, "Inc "); + //TextRender_string24(Lv.Grid.Left[3] + xDec +30, Lv.Grid.Top[3] +8, clNearWhite, "Dec "); + TextRender_string24(Lv.Grid.Left[4] + 10, Lv.Grid.Top[4] +6, clNearWhite, "Opera"); + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "View", 14, clNearBlack); + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, "Save", 14, clNearBlack); + } +} + +void TUserCodeSetByArea::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iSTextDType.Init(xType + 96 + 48 +4, Lv.Grid.Top[0] +40, 286, 32, 0,0, clNearWhite, ItemColor); + IList->STextDType.TextClear(); + IList->STextDType.Visible = 1; + + //Area Num + IList->EditAreaAssign.Init(Lv.Grid.Left[0] + 86, Lv.Grid.Top[0] +4, 60, 30, 0,0,1,clNearWhite); + IList->EditAreaAssign.Str.Clear(); + IList->EditAreaAssign.SetText("0001",24); + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.SetMaxLen(4); + IList->EditAreaAssign.Enable =1; + + //Assign Type + IList->EditCtlNum.Init(xType + 96, Lv.Grid.Top[0] +40, 48, 30, 0,0,1,clNearWhite); + IList->EditCtlNum.Str.Clear(); + IList->EditCtlNum.Str.FromStr("000"); + IList->EditCtlNum.SetMaxLen(3); + IList->EditCtlNum.Enable =1; + + //Short Name + IList->Edit[0].Init(Lv.Grid.Left[1] + 60, Lv.Grid.Top[1] +4, 226, 30, 0,0,1,clNearWhite); + IList->Edit[0].Str.Clear(); + IList->Edit[0].Enable =0; + + //Descp + mlEdit.Init(Lv.Grid.Left[1] +60, Lv.Grid.Top[1] +36, 226, 64, 0,0,1,clNearWhite); + mlEdit.SetLineSpacing(4); + mlEdit.Str.Clear(); + mlEdit.Enable =0; + + //New UserCode + IList->EditUserCode.Init(Lv.Grid.Left[2] + 176, Lv.Grid.Top[2] +4, 110, 30, 0,0,1,clNearWhite); + IList->EditUserCode.SetMaxLen(8); + IList->EditUserCode.Str.Clear(); + IList->EditUserCode.Enable =1; + + IList->EditCtlNum.Str.FromUInt3Dg(dType); + IList->Edit[0].SetPstTail(); + IList->EditCtlNum.SetPstTail(); + + IList->STextDType.Show(); + IList->Edit[0].Show(); + mlEdit.Show(); + + IList->EditAreaAssign.Show(); + IList->EditCtlNum.Show(); + IList->EditUserCode.Show(); + + DrawAssignTypeText(); + DrawRecover(); + DrawIncDec(); + + LoadData(); + + Check4Selected(); +} + +void TUserCodeSetByArea::Show(void) +{ + IsShow = 1; + RenderBackGround(); + DrawSelf(); +} + +void TUserCodeSetByArea::DrawRecover() +{ + if(IsRecover==0){ + TRoundSquare::sDrawBySize(xRecover, Lv.Grid.Top[0] + 44, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + TRoundSquare::sDrawBySize(xAvoid, Lv.Grid.Top[0] + 44, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + }else{ + TRoundSquare::sDrawBySize(xRecover, Lv.Grid.Top[0] + 44, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + TRoundSquare::sDrawBySize(xAvoid, Lv.Grid.Top[0] + 44, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + } +} + +void TUserCodeSetByArea::DrawIncDec() +{ + if(IncDec==0){ + TRoundSquare::sDrawBySize(xInc, Lv.Grid.Top[3] + 8, dWWidth, dWHeigh, dRoundR, dWdClr , 1); + //TRoundSquare::sDrawBySize(xDec, Lv.Grid.Top[3] + 8, dWWidth, dWHeigh, dRoundR, dWdInvalidClr , 0); + }else{ + TRoundSquare::sDrawBySize(xInc, Lv.Grid.Top[3] + 8, dWWidth, dWHeigh, dRoundR, dWdDisabelClr , 0); + //TRoundSquare::sDrawBySize(xDec, Lv.Grid.Top[3] + 8, dWWidth, dWHeigh, dRoundR, dWdInvalidClr , 1); + } +} + +void TUserCodeSetByArea::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + DrawWriteSta(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], ContentColor); + for(int i=0; i<2; i++)RectFillRender(Lv.Grid.Left[i], Lv.Grid.Top[i], Lv.Grid.Right[i], Lv.Grid.Bottom[i], ItemColor); + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + TextDigitRender2_24(Lv.Grid.Left[0] + 260, Lv.Grid.Top[0] +6, clNearWhite, MainCtl.fData.Split.MyNum); + DrawFixText(); + DrawRecover(); + IList->STextDType.Show(); + IList->EditAreaAssign.Show(); + IList->EditCtlNum.Show(); + IList->Edit[0].Show(); + mlEdit.Show(); + Check4Selected(); + if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +//______________________________________________________________________________________________________________________________ +void TUserCodeSetByArea::ClearSelected(void) +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->EditAreaAssign.Selected =0; + IList->EditAreaAssign.Show(); + break; + case 1: + TRoundSquare::sSelected(xRecover, Lv.Grid.Top[0]+44, dWWidth, dWHeigh, 4, ItemColor); + break; + case 2: + TRoundSquare::sSelected(xAvoid, Lv.Grid.Top[0]+44, dWWidth, dWHeigh, 4, ItemColor); + break; + case 3: + IList->EditCtlNum.Selected =0; + IList->EditCtlNum.Show(); + break; + case 4: + IList->EditUserCode.Selected =0; + IList->EditUserCode.Show(); + break; + case 5: + TRoundSquare::sSelected(xInc, Lv.Grid.Top[3]+8, dWWidth, dWHeigh, 4, ItemColor); + break; + case 6: + TRoundSquare::sSelected(xDec, Lv.Grid.Top[3]+8, dWWidth, dWHeigh, 4, ItemColor); + break; + case 7: + if(LanguageEnCn==0)tText="确定";else tText="View"; + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + case 8: + if(LanguageEnCn==0)tText="保存";else tText="Save"; + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[4] + 6, 76, 30, 7, clNearWhite, tText, 14, clNearBlack); + break; + default: + + break; + } +} + +void TUserCodeSetByArea::Check4Selected(void) +{ + char *tText; + switch(CtlIndex){ + case 0: + IList->EditAreaAssign.Selected =1; + IList->EditAreaAssign.SetPstTail(); + IList->EditAreaAssign.Show(); + break; + case 1: + TRoundSquare::sSelected(xRecover, Lv.Grid.Top[0]+44, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 2: + TRoundSquare::sSelected(xAvoid, Lv.Grid.Top[0]+44, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 3: + IList->EditCtlNum.Selected =1; + IList->EditCtlNum.SetPstTail(); + IList->EditCtlNum.Show(); + break; + case 4: + IList->EditUserCode.Selected =1; + IList->EditUserCode.SetPstTail(); + IList->EditUserCode.Show(); + break; + case 5: + TRoundSquare::sSelected(xInc, Lv.Grid.Top[3]+8, dWWidth, dWHeigh, 4, clNearWhite); + //sDrawBySize(int x, int y, int aW, int aH, int RoundR, u32 aClr, int Active); + break; + case 6: + TRoundSquare::sSelected(xDec, Lv.Grid.Top[3]+8, dWWidth, dWHeigh, 4, clNearWhite); + break; + case 7: + if(LanguageEnCn==0)tText="确定";else tText="View"; + TRoundRect::sDrawBySize(xModify, Lv.Grid.Top[4] + 6, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + case 8: + if(LanguageEnCn==0)tText="保存";else tText="Save"; + TRoundRect::sDrawBySize(xSave, Lv.Grid.Top[4] + 6, 76, 30, 7, clBlue, tText, 14, clNearWhite); + break; + default: + + break; + } +} + +void TUserCodeSetByArea::PermissionCmdGO() +{ + int aResult; + if(PermissionCmd == 1){ + aResult = Write(); + Record.ReadDevUserSet(); + Record.ReadDirectPadUserSet(); + if(aResult > 0){ + DrawWriteSta(aResult); + }else{ + DrawWriteSta(aResult); + } + Check4Selected(); + } +} + +void TUserCodeSetByArea::PermissionCmdReturnDraw() +{ + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); +} + +//_____________________________________________________________________________________________________________________________ +TGuiMsgReturn TUserCodeSetByArea::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn PmsRtnMsg = guiMsgNone; + int iVal; + int HadPrc; + + if(IsPermission){ + PmsRtnMsg = PmsIntervene4Gui.KeyIn(aKey); + if(PmsRtnMsg == guiMsgOkAndReturn){ + //Enter And Run Go + IsPermission = 0; + PermissionCmdReturnDraw(); + PermissionCmdGO(); + }else + if(PmsRtnMsg == guiMsgReturn){ + //Not Enter Redraw + IsPermission = 0; + PermissionCmdReturnDraw(); + } + return aMsg; + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + HadPrc =0; + if( (aKey == VK_LEFT) || (aKey == VK_RIGHT) ){ + if(CtlIndex == 1){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 2){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + }else + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 3){ + if(aKey == VK_LEFT){ + if(IList->EditCtlNum.Pst <0){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + } + }else + if(CtlIndex == 5){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 6){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 7){ + if(aKey == VK_RIGHT){ + ClearSelected(); + CtlIndex++; + Check4Selected(); + HadPrc =1; + } + }else + if(CtlIndex == 8){ + if(aKey == VK_LEFT){ + ClearSelected(); + CtlIndex--; + Check4Selected(); + HadPrc =1; + } + } + } + if(HadPrc == 0){ + if(CtlIndex == 0){ + IList->EditAreaAssign.KeyIn(aKey); + int iVal; + iVal = IList->EditAreaAssign.Str.ToInteger(); + if( (iVal <1) || (iVal > dAreaCountMax) ){ + AreaValid =0; + IList->EditAreaAssign.SelectedColor = clRed; + }else{ + AreaValid =1; + IList->EditAreaAssign.SelectedColor = clBlue; + iVal--; + if(iVal != AreaNum){ + AreaNum = iVal; + LoadData(); + } + } + IList->EditAreaAssign.Show(); + }else + if(CtlIndex == 3){ + IList->EditCtlNum.KeyIn(aKey); + int iVal; + iVal = IList->EditCtlNum.Str.ToInteger(); + if( (iVal <0) || (iVal > 255) ){ + dTypeValid =0; + IList->EditCtlNum.SelectedColor = clRed; + }else{ + dTypeValid =1; + IList->EditCtlNum.SelectedColor = clBlue; + if(iVal != dType){ + dType = iVal; + } + } + IList->EditCtlNum.Show(); + DrawAssignTypeText(); + }else + if(CtlIndex == 4){ + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + } + } + break; + case dfKEY_ASTERISK: + if(CtlIndex == 4){ + IList->EditUserCode.KeyIn(aKey); + IList->EditUserCode.Show(); + } + break; + case VK_UP: + if(CtlIndex >0){ + if( dTypeValid && AreaValid ){ + ClearSelected(); + CtlIndex--; + if( (CtlIndex == 5) || (CtlIndex == 6) ){ + CtlIndex = 4; + } + Check4Selected(); + } + }else{ + if( AreaValid && dTypeValid ){ + ClearSelected(); + CtlIndex =8; + Check4Selected(); + } + } + break; + case VK_DOWN: + if(CtlIndex <8){ + if( AreaValid && dTypeValid ){ + ClearSelected(); + CtlIndex++; + if( (CtlIndex == 5) || (CtlIndex == 6) ){ + CtlIndex = 7; + } + Check4Selected(); + } + }else{ + ClearSelected(); + CtlIndex=0; + Check4Selected(); + } + break; + case VK_TAB: + //IsList = 1; + //DrawList(); + //ClearSelected(); + break; + case dfKEY_SETUP: //0x70 // Key value for SETUP + if( (CtlIndex == 1) || (CtlIndex == 2) ){ + IsRecover = IsRecover ? 0 :1; + DrawRecover(); + }else + if( (CtlIndex == 5) || (CtlIndex == 6) ){ + //IncDec = IncDec ? 0 :1; + IncDec =0; + DrawIncDec(); + } + break; + case VK_EXECUTE: + if( (CtlIndex == 1) || (CtlIndex == 2) ){ + IsRecover = IsRecover ? 0 :1; + DrawRecover(); + }else + if( (CtlIndex == 5) || (CtlIndex == 6) ){ + //IncDec = IncDec ? 0 :1; + IncDec =0; + DrawIncDec(); + }else + if(CtlIndex == 7){ + if(IsShowwingDetail){ + DrawDetailGoOn(); + }else{ + DrawDetailStart(); + } + }else + if(CtlIndex == 8){ + //Save Data Here + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(Lv.Panel.Left + 16, Lv.Panel.Top + 16, Lv.Panel.Width -36 , 140, 3); + } + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + default : + break; + } + + if(VK_EXECUTE != aKey){ + IsShowwingDetail = 0; + DrawWriteSta(0); + } + } + + return aMsg; +} + +void TUserCodeSetByArea::DrawAssignTypeText() +{ + if(dTypeValid == 0){ + IList->STextDType.SetText("--------" ,24); + }else{ + if(LanguageEnCn==0){ + if( dType ){ + IList->STextDType.SetText(StrTypeShortName[dType] ,24); + }else{ + IList->STextDType.SetText("所有类型" ,24); + } + }else{ + if( dType ){ + IList->STextDType.SetText(StrTypeShortNameEn[dType] ,24); + }else{ + IList->STextDType.SetText("All Types" ,24); + } + } + } + IList->STextDType.Show(); +} + +void TUserCodeSetByArea::LoadAUserCode() +{ + int i,x, Got =0; + unsigned int tUc; + for(i=0; iEditUserCode.Str.FromUInt8Dg(tUc); + }else{ + IList->EditUserCode.Str.FromStr("00000000"); + } + IList->EditUserCode.Show(); +} + +void TUserCodeSetByArea::LoadShortName() +{ + unsigned int Idf, sAddr; + + if(AreaNum >= dAreaCountMax ){ + IList->Edit[0].Str.FromStr("------"); + IList->Edit[0].Show(); + return; + } + + sAddr = dAddrSdRam_4Area + (AreaNum * 64); + Idf = *(volatile unsigned int *)(sAddr); + if(Idf == 0xA8A7A6A5){ + sAddr = dAddrSdRam_4Area + (AreaNum * 64) + 16; + for(int i=0; i<16; i++){ + IList->Edit[0].Str.Text[i] = *(volatile unsigned char *)(sAddr +i); + } + IList->Edit[0].Str.Text[16] = '\0'; + }else{ + IList->Edit[0].Str.FromStr("------"); + } + IList->Edit[0].Show(); +} + +void TUserCodeSetByArea::LoadDescp() +{ + unsigned int Idf, sAddr; + + if(AreaNum >= dAreaCountMax ){ + mlEdit.Str.FromStr("----"); + mlEdit.Show(); + return; + } + + sAddr = dAddrSdRam_4Area + (AreaNum * 64); + Idf = *(volatile unsigned int *)(sAddr); + if(Idf == 0xA8A7A6A5){ + sAddr = dAddrSdRam_4Area + (AreaNum * 64) + 32; + for(int i=0; i<32; i++){ + mlEdit.Str.Text[i] = *(volatile unsigned char *)(sAddr +i);; + } + mlEdit.Str.Text[32] = '\0'; + }else{ + mlEdit.Str.FromStr("----"); + } + + mlEdit.Show(); +} + +void TUserCodeSetByArea::LoadData() +{ + LoadAUserCode(); + LoadShortName(); + LoadDescp(); +} + +int TUserCodeSetByArea::DrawDetailStart() +{ + int x,y, Pst; + char tText[16]; + unsigned int tUc, HadGotAsFinished; + unsigned short AreaNumCmp; + int AstStartPoint, AstEndPoint, AstLength, InputLength, Step; + x = Lv.Panel.Left +4; + y = Lv.Panel.Top +4; + + AreaNumCmp = AreaNum +1; + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + + if(AreaNumCmp > dAreaCountMax){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "分区号错误"); + else TextRender_string24(x, y, clNearWhite, "Zone Error"); + return -1; + } + if(dTypeValid == 0){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "指定类型超出范围 "); + else TextRender_string24(x, y, clNearWhite, "Assigned Type Invalid"); + return -1; + } + + Detail.Erase.PortNum =0;; + Detail.Erase.EpAddr =0; + Detail.Erase.DirectPadNum =0; + Detail.Erase.DirectKey =0; + + Detail.Write.PortNum =0;; + Detail.Write.EpAddr =0; + Detail.Write.DirectPadNum =0; + Detail.Write.DirectKey =0; + + Detail.IsPortOrPad =0; + Detail.IsWritting =0; + + Detail.Counts4ThisArea =0; + for(int i=0; iEditUserCode.Str.Text[Pst] != '\0'){ + if(HadGotAsFinished == 1){ + if(IList->EditUserCode.Str.Text[Pst] == '*'){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "通配二次码存在两段或以上的通配字段"); + else TextRender_string24(x, y, clNearWhite, "Invalid,Aux ID 2 Paragraphs Wildcard"); + return -1; + }else{ + tText[Pst] = IList->EditUserCode.Str.Text[Pst]; + Step++; + } + }else{ + if(IList->EditUserCode.Str.Text[Pst] == '*'){ + tText[Pst] = '0'; + if(GotAst == 0)AstStartPoint = Pst; + GotAst =1; + AstEndPoint = Pst; + }else{ + tText[Pst] = IList->EditUserCode.Str.Text[Pst]; + if(GotAst){ + HadGotAsFinished = 1; + Step++; + } + } + } + }else{ + break; + } + } + UserCodeItv = 1; + for(int i=0; i< Step; i++){ + UserCodeItv *= 10; + } + AstLength = AstEndPoint - AstStartPoint +1; + if(IList->EditUserCode.Str.Text[8] != '\0'){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "新二次码长度超出范围"); + else TextRender_string24(x, y, clNearWhite, "New Aux ID Invalid"); //value out of range + return -1; + } + + UserCodeStart = TMyString::sToInteger(tText); + + if(GotAst){ + int tScope =1; + for(int i=0, z=0; (i<8) && (z 99999999){ + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "通配字段递增溢出"); + else TextRender_string24(x, y, clNearWhite, "Invalid,Value Out Of Range"); + return -1; + } + }else{ + if( (UserCodeStart - (UserCodeItv * tScope) ) < 0){ + if(LanguageEnCn)TextRender_string24(x, y, clNearWhite, "通配字段递减溢出"); + else TextRender_string24(x, y, clNearWhite, "Invalid,Value Out Of Range"); + return -1; + } + } + + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "使用通配字:"); + x += 132; + TextRender_string24(x, y, clNearWhite, "开始"); + x += 48; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeItv); + }else{ + TextRender_string24(x, y, clNearWhite, "With Wildcard"); + x += 13 *12; + TextRender_string24(x, y, clNearWhite, "Begin"); + x += 5*12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeItv); + } + }else{ + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "无通配字 开始:"); + x += 170; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, 1); + }else{ + TextRender_string24(x, y, clNearWhite, "Without Wildcard"); + x += 17*12; + TextDigitRender8_24(x, y, clNearWhite, UserCodeStart); + x += 96; + TextRender_string24(x, y, clNearWhite, "+"); + x += 12; + TextDigitRender8_24(x, y, clNearWhite, 1); + } + } + + IList->RealtimeData.Reset(); + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "本区域设备数量:"); + x += 180; + }else{ + TextRender_string24(x, y, clNearWhite, "Amount Of This Zone "); + x += 20*12; + } + TextDigitRender8_24(x, y, clNearWhite, Detail.Counts4ThisArea); + + UserCodeEnd = UserCodeStart + (UserCodeItv * Detail.Counts4ThisArea); + UserCode = UserCodeStart; + if(IsRecover) Detail.IsWritting =1; + IsShowwingDetail = 1; + + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "按确定键继续"); + else TextRender_string24(x, y, clNearWhite, "Press Key OK Continue"); + + Detail.Counts4ThisArea =0; + return 0; +} + +void TUserCodeSetByArea::DrawDetailGoOn() +{ + int x,y, UcFound=0; + int ThisPressDrawCount = 0; + unsigned int AreaNumCmp; + int LoadStartAddr; + int LoadStartKey; + x = Lv.Panel.Left +4; + y = Lv.Panel.Top +4; + + AreaNumCmp = AreaNum+1; + + if(Lv.Panel.Active)RectFillRender(Lv.Panel.Left, Lv.Panel.Top+26, Lv.Panel.Right, Lv.Panel.Bottom, PanelColor); + + if(IsRecover){ + //Recover Mode + //Showwing Erase Tntry + if(Detail.IsWritting == 0){ + while(UserCode <= UserCodeEnd){ + for(; Detail.Erase.PortNum < dPORT_MAX_COUNT; Detail.Erase.PortNum++){ + int i=Detail.Erase.PortNum; + if(ThisPressDrawCount > 7)break; + for(; Detail.Erase.EpAddr 7)break; + int g=Detail.Erase.EpAddr; + if( (Port[i].Area[g] == AreaNumCmp) && ((Port[i].AssignType[g] == dType) || (dType == 0) ) ) { + if(UserCode == Port[i].UcList[g].Full){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "删除 回路:"); + x += 120; + }else{ + TextRender_string24(x, y, clNearWhite, "Del Loop: "); + x += 120; + } + TextDigitRender2_24(x, y, clNearWhite, i+1); + x += 36; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "地址:"); + else TextRender_string24(x, y, clNearWhite, "Addr:"); + x += 60; + TextDigitRender3_24(x, y, clNearWhite, g+1); + x += 60; + TextDigitRender8_24(x, y, clNearWhite, Port[i].UcList[g].Full ); + ThisPressDrawCount++; + } + } + if(ThisPressDrawCount > 7)break; + } + if(ThisPressDrawCount > 7)break; + } + + for(; Detail.Erase.DirectPadNum < dDIRECTCTL_MAX_COUNT; Detail.Erase.DirectPadNum++){ + int i=Detail.Erase.DirectPadNum; + if(ThisPressDrawCount > 7)break; + for(; Detail.Erase.DirectKey < dDIRECTCTL_KEY_MAX_COUNT; Detail.Erase.DirectKey++){ + int g=Detail.Erase.DirectKey; + if(ThisPressDrawCount > 7)break; + if( (DirectCtlBoard[i].Area[g] == AreaNumCmp) && ((DirectCtlBoard[i].AssignType[g] == dType) || (dType == 0) ) ) { + if(UserCode == DirectCtlBoard[i].UcList[g].Full){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "删除 多线盘号:"); + x += 168; + }else{ + TextRender_string24(x, y, clNearWhite, "Del Direct Brd:"); + x += 15*12; + } + TextDigitRender2_24(x, y, clNearWhite, i+1); + x += 36; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "节点:"); + else TextRender_string24(x, y, clNearWhite, "Node:"); + x += 60; + TextDigitRender3_24(x, y, clNearWhite, g+1); + x += 60; + TextDigitRender8_24(x, y, clNearWhite, DirectCtlBoard[i].UcList[g].Full ); + ThisPressDrawCount++; + } + } + if(ThisPressDrawCount > 7)break; + } + if(ThisPressDrawCount > 7)break; + } + + if(Detail.Erase.DirectPadNum >= dDIRECTCTL_MAX_COUNT){ + UserCode += UserCodeItv; + Detail.Erase.PortNum =0; + Detail.Erase.EpAddr =0; + Detail.Erase.DirectPadNum =0; + Detail.Erase.DirectKey =0; + } + + if(ThisPressDrawCount > 7){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "按确定键继续"); + else TextRender_string24(x, y, clNearWhite, "Press Key OK Continue"); + return; + } + } + if(UserCode > UserCodeEnd){ + UserCode = UserCodeStart; + Detail.IsWritting =1; + } + } + //Show Write Entry + if(Detail.IsWritting){ + LoadStartAddr =0; + LoadStartKey =0; + for(; Detail.Write.PortNum < dPORT_MAX_COUNT; Detail.Write.PortNum++){ + if(ThisPressDrawCount > 7)break; + int i=Detail.Write.PortNum; + if(LoadStartAddr == 1){ + Detail.Write.EpAddr =0; + } + LoadStartAddr =1; + for(; Detail.Write.EpAddr < dEP_MAX_COUNT_PER_PORT; Detail.Write.EpAddr++){ + if(ThisPressDrawCount > 7)break; + int g=Detail.Write.EpAddr; + if(Port[i].Area[g] == AreaNumCmp){ + int toCheck =0; + if(dType == 0)toCheck =1; + if(Port[i].AssignType[g]){ + if(Port[i].AssignType[g] == dType)toCheck =1; + }else{ + if(Port[i].dTypeTable[g] == dType)toCheck =1; + } + if(toCheck){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "回路:"); + else TextRender_string24(x, y, clNearWhite, "Loop:"); + x += 60; + TextDigitRender2_24(x, y, clNearWhite, i+1); + x += 36; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "地址:"); + else TextRender_string24(x, y, clNearWhite, "Addr:"); + x += 60; + TextDigitRender3_24(x, y, clNearWhite, g+1); + x += 60; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "原:"); + else TextRender_string24(x, y, clNearWhite, " "); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, Port[i].UcList[g].Full ); + x += 100; + TextRender_string24(x, y, clNearWhite, "-->"); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, UserCode ); + ThisPressDrawCount++; + UserCode += UserCodeItv; + Detail.Counts4ThisArea++; + } + } + if(ThisPressDrawCount > 7)break; + } + + if(ThisPressDrawCount > 7)break; + } + + for(; Detail.Write.DirectPadNum < dDIRECTCTL_MAX_COUNT; Detail.Write.DirectPadNum++){ + int i =Detail.Write.DirectPadNum; + if(ThisPressDrawCount > 7)break; + if(LoadStartKey == 1){ + Detail.Write.DirectKey =0; + } + LoadStartKey =1; + for(; Detail.Write.DirectKey < dDIRECTCTL_KEY_MAX_COUNT; Detail.Write.DirectKey++){ + int g =Detail.Write.DirectKey; + if(ThisPressDrawCount > 7)break; + if(DirectCtlBoard[i].Area[g] == AreaNumCmp){ + if( (dType == 0) || (DirectCtlBoard[i].AssignType[g] == dType) ){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "多线盘号:"); + x += 108; + }else{ + TextRender_string24(x, y, clNearWhite, "Direct Brd:"); + x += 11*12; + } + TextDigitRender2_24(x, y, clNearWhite, i+1); + x += 36; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "节点:"); + else TextRender_string24(x, y, clNearWhite, "Node:"); + x += 60; + TextDigitRender2_24(x, y, clNearWhite, g+1); + x += 48; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "原"); + else TextRender_string24(x, y, clNearWhite, " "); + x += 24; + TextDigitRender8_24(x, y, clNearWhite, DirectCtlBoard[i].UcList[g].Full ); + x += 96; + TextRender_string24(x, y, clNearWhite, "->"); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, UserCode ); + + ThisPressDrawCount++; + UserCode += UserCodeItv; + Detail.Counts4ThisArea++; + } + } + if(ThisPressDrawCount > 7)break; + } + if(ThisPressDrawCount > 7)break; + } + if(ThisPressDrawCount > 7){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "按确定键继续"); + else TextRender_string24(x, y, clNearWhite, "Press Key OK Continue"); + return; + } + } + if(Detail.Write.DirectPadNum >= dDIRECTCTL_MAX_COUNT) { + IsShowwingDetail = 0; + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "修改数量"); + TextDigitRender5_24(x+96, y, clNearWhite, Detail.Counts4ThisArea); + TextRender_string24(x+156, y, clNearWhite, " 展示完毕"); + }else{ + TextRender_string24(x, y, clNearWhite, "To Be Modify"); + TextDigitRender5_24(x+12*12, y, clNearWhite, Detail.Counts4ThisArea); + TextRender_string24(x+156, y, clNearWhite, " Completed"); + } + } + }else{ + //Avoid Mode + while(Detail.Write.DirectPadNum < dDIRECTCTL_MAX_COUNT){ + while(Detail.Write.PortNum 7)break; + int i= Detail.Write.PortNum; + while(Detail.Write.EpAddr < dEP_MAX_COUNT_PER_PORT){ + if(ThisPressDrawCount >7)break; + int g=Detail.Write.EpAddr; + if(Port[i].Area[g] == AreaNumCmp){ + int toCheck =0; + if(dType == 0)toCheck =1; + if(Port[i].AssignType[g]){ + if(Port[i].AssignType[g] == dType)toCheck =1; + }else{ + if(Port[i].dTypeTable[g] == dType)toCheck =1; + } + if(toCheck){ + int DoSkip; + do{ + DoSkip =0; + for(int i=0; i"); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, UserCode ); + + ThisPressDrawCount++; + UserCode += UserCodeItv; + Detail.Counts4ThisArea++; + } + } + } + Detail.Write.EpAddr++; + if(Detail.Write.EpAddr >= dEP_MAX_COUNT_PER_PORT){ + Detail.Write.PortNum++; + Detail.Write.EpAddr = 0; + break; + } + if(ThisPressDrawCount >7)break; + } + if(ThisPressDrawCount > 7)break; + } + while(Detail.Write.DirectPadNum < dDIRECTCTL_MAX_COUNT){ + if(ThisPressDrawCount >7)break; + int i=Detail.Write.DirectPadNum; + while(Detail.Write.DirectKey < dDIRECTCTL_KEY_MAX_COUNT){ + if(ThisPressDrawCount >7)break; + int g=Detail.Write.DirectKey; + if(DirectCtlBoard[i].Area[g] == AreaNumCmp){ + if( (dType ==0) || (dType == DirectCtlBoard[i].AssignType[g]) ){ + int DoSkip; + do{ + DoSkip =0; + for(int i=0; i"); + x += 36; + TextDigitRender8_24(x, y, clNearWhite, UserCode ); + ThisPressDrawCount++; + UserCode += UserCodeItv; + Detail.Counts4ThisArea++; + } + } + } + Detail.Write.DirectKey++; + if(Detail.Write.DirectKey >= dDIRECTCTL_KEY_MAX_COUNT){ + Detail.Write.DirectPadNum++; + Detail.Write.DirectKey = 0; + break; + } + if(ThisPressDrawCount >7)break; + } + if(ThisPressDrawCount > 7)break; + } + if(ThisPressDrawCount >7){ + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0)TextRender_string24(x, y, clNearWhite, "按确定键继续"); + else TextRender_string24(x, y, clNearWhite, "Press Key OK Continue"); + return; + } + } + if( Detail.Write.DirectPadNum >= dDIRECTCTL_MAX_COUNT ){ + IsShowwingDetail = 0; + x = Lv.Panel.Left +4; + y+=28; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, "修改数量"); + TextDigitRender5_24(x+96, y, clNearWhite, Detail.Counts4ThisArea); + TextRender_string24(x+156, y, clNearWhite, " 展示完毕"); + }else{ + TextDigitRender5_24(x, y, clNearWhite, Detail.Counts4ThisArea); + TextRender_string24(x+6*12, y, clNearWhite, "Items To Be Modify,Completed"); + } + } + } +} + +void TUserCodeSetByArea::Write2Flash() +{ + /*unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char wP1; + int NotEqOcc =0; + + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + Record.ReadDevUserSet(); + + if(NotEqOcc){ + //Error + }else{ + //OK + }*/ +} + +int TUserCodeSetByArea::WriteOnePort(unsigned int aP0) +{ + unsigned int fAddr; + unsigned int i; + unsigned int aUcFull; + volatile unsigned int x, GetSta; + unsigned char wP1; + TDMix tCrc; + + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( (aP0 < dPORT_MAX_COUNT) ){ + fAddr = dFlashAddrDevUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + DelayMs(100); + + do{ + DelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + Crc32Reset(); + for(i=0; i<64; i++)IList->ReadWriteData.D32[i] = 0; + for(i=0; i<4; i++){ + for(x=0;x<64;x++){ + IList->ReadWriteData.D32[x] = Port[aP0].UcList[i*64 + x].Full; + if( (i<3) or (x< (dEP_MAX_COUNT_PER_PORT % 64))){ + Crc32Feed(IList->ReadWriteData.D32[x]); + } + } + if(i==3){ + IList->ReadWriteData.D32[63] = Crc32GetResult(); + } + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (i * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, IList->ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } + + for(x=0;xReadWriteData.D8[x] = Port[aP0].AssignType[x]; + } + Crc32Reset(); + for(x=0; x(IList->ReadWriteData.D8[x])); + tCrc.D32 = Crc32GetResult(); + IList->ReadWriteData.D8[252] = tCrc.D8[0]; + IList->ReadWriteData.D8[253] = tCrc.D8[1]; + IList->ReadWriteData.D8[254] = tCrc.D8[2]; + IList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (4 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, IList->ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Signal Type + for(x=0;x<256;x++){ + IList->ReadWriteData.D8[x] = Port[aP0].FuncSetByte[x]; + } + Crc32Reset(); + for(x=0; x(IList->ReadWriteData.D8[x])); + tCrc.D32 = Crc32GetResult(); + IList->ReadWriteData.D8[252] = tCrc.D8[0]; + IList->ReadWriteData.D8[253] = tCrc.D8[1]; + IList->ReadWriteData.D8[254] = tCrc.D8[2]; + IList->ReadWriteData.D8[255] = tCrc.D8[3]; + fAddr = dFlashAddrDevUserCode + (aP0 * 4096) + (5 * 256); + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, IList->ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + } + + //Check First 64 UserCode + do{ + DelayMs(2); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + fAddr = dFlashAddrDevUserCode + (4096 * aP0) + (256 * 0); + nor_read_byte(dFlashAddrDevUserCodeChip,fAddr,IList->ReadWriteData.D8,256); + for(x=0; x<64; x++){ + if(Port[aP0].UcList[x].Full != IList->ReadWriteData.D32[x]){ + return -9; + } + } + return 0; +} + +int TUserCodeSetByArea::WriteOneDirectPad(unsigned char aP0) +{ + unsigned int fAddr; + unsigned int i; + volatile unsigned int x, GetSta; + TDMix tCrc1, tCrc2; + + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + //Erase 1 * 4K Blocks + if( aP0 < dDIRECTCTL_MAX_COUNT ){ + fAddr = dFlashAddrDirectPadUserCode + (aP0 * 4096); + nor_erase_sector_4k(dFlashAddrDevUserCodeChip,fAddr); + DelayMs(100); + + do{ + DelayMs(10); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + for(x=0;xReadWriteData.D32[x] = DirectCtlBoard[aP0].UcList[x].Full; + IList->ReadWriteData.D8[x + 32] = DirectCtlBoard[aP0].AssignType[x]; + } + Crc32Reset(); + for(x=0;xReadWriteData.D32[x]); + tCrc1.D32 = Crc32GetResult(); + Crc32Reset(); + for(x=0;xReadWriteData.D8[x + 32]); + tCrc2.D32 = Crc32GetResult(); + + IList->ReadWriteData.D8[32+8 +0] = tCrc1.D8[0]; + IList->ReadWriteData.D8[32+8 +1] = tCrc1.D8[1]; + IList->ReadWriteData.D8[32+8 +2] = tCrc1.D8[2]; + IList->ReadWriteData.D8[32+8 +3] = tCrc1.D8[3]; + IList->ReadWriteData.D8[32+8 +4] = tCrc2.D8[0]; + IList->ReadWriteData.D8[32+8 +5] = tCrc2.D8[1]; + IList->ReadWriteData.D8[32+8 +6] = tCrc2.D8[2]; + IList->ReadWriteData.D8[32+8 +7] = tCrc2.D8[3]; + + nor_write_page(dFlashAddrDevUserCodeChip, fAddr, IList->ReadWriteData.D8); + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(GetSta); + + nor_read_byte(dFlashAddrDevUserCodeChip,fAddr,IList->ReadWriteData.D8,256); + for(x=0; xReadWriteData.D32[x] != DirectCtlBoard[aP0].UcList[x].Full){ + //Direct Pad Write Error + return -11; + } + } + return 0; + } + //Direct Pad No Exist + return -12; +} + + +int TUserCodeSetByArea::Write() +{ + int x,y, UcFound=0; + int ProceduredCount = 0; + int ToWriteThis; + unsigned short AreaNumCmp; + + int Pst; + char tText[16]; + unsigned int tUc, HadGotAsFinished; + int AstStartPoint, AstEndPoint, AstLength, InputLength, Step; + + AreaNumCmp = AreaNum +1; + + if(AreaNumCmp > dAreaCountMax){ + //TextRender_string24(x, y, clNearWhite, "分区号错误"); + return -1; + } + if(dTypeValid == 0){ + //TextRender_string24(x, y, clNearWhite, "指定类型超出范围"); + return -2; + } + + Writing.Erase.PortNum =0;; + Writing.Erase.EpAddr =0; + Writing.Erase.DirectPadNum =0; + Writing.Erase.DirectKey =0; + + Writing.Write.PortNum =0;; + Writing.Write.EpAddr =0; + Writing.Write.DirectPadNum =0; + Writing.Write.DirectKey =0; + + Writing.IsPortOrPad =0; + Writing.IsWritting =0; + + //Get Items Count + Writing.Counts4ThisArea =0; + for(int i=0; iEditUserCode.Str.Text[Pst] != '\0'){ + if(HadGotAsFinished == 1){ + if(IList->EditUserCode.Str.Text[Pst] == '*'){ + //TextRender_string24(x, y, clNearWhite, "通配二次码存在两段或以上的通配字段"); + return -4; + }else{ + tText[Pst] = IList->EditUserCode.Str.Text[Pst]; + Step++; + } + }else{ + if(IList->EditUserCode.Str.Text[Pst] == '*'){ + tText[Pst] = '0'; + if(GotAst == 0)AstStartPoint = Pst; + GotAst =1; + AstEndPoint = Pst; + }else{ + tText[Pst] = IList->EditUserCode.Str.Text[Pst]; + if(GotAst){ + HadGotAsFinished = 1; + Step++; + } + } + } + }else{ + break; + } + } + UserCodeItv = 1; + for(int i=0; i< Step; i++){ + UserCodeItv *= 10; + } + AstLength = AstEndPoint - AstStartPoint +1; + if(IList->EditUserCode.Str.Text[8] != '\0'){ + //TextRender_string24(x, y, clNearWhite, "新二次码长度超出范围"); + return -3; + } + UserCodeStart = TMyString::sToInteger(tText); + //__________________________Get User Code 4 Start <- + + //Get User Code And The UserCodeItv=Inteval + if(GotAst){ + int tScope =1; + for(int i=0, z=0; (i<8) && (z 99999999){ + //TextRender_string24(x, y, clNearWhite, "通配字段递增溢出"); + return -6; + } + }else{ + if( (UserCodeStart - (UserCodeItv * tScope) ) < 0){ + //TextRender_string24(x, y, clNearWhite, "通配字段递减溢出"); + return -7; + } + } + }else{ + //TextRender_string24(x, y, clNearWhite, "无通配字 开始:"); + } + + + UserCodeEnd = UserCodeStart + (UserCodeItv * Writing.Counts4ThisArea); + UserCode = UserCodeStart; + if(IsRecover){ + //Recover Mode + //Write Port + for(x=0; x99999999){ + //UserCode OverFlow + return -10; + } + Port[x].UcList[y].Full = UserCode; + UserCode += UserCodeItv; + ToWriteThis =1; + ProceduredCount++; + } + } + if(ToWriteThis){ + //Write One Port Here + if(WriteOnePort(x) !=0){ + //Write One Port Error + return -8; + } + } + //} + } + //Write Direct Pad + for(x=0; x < dDIRECTCTL_MAX_COUNT; x++){ + ToWriteThis = 0; + for(y=0; y < dDIRECTCTL_KEY_MAX_COUNT; y++){ + if(DirectCtlBoard[x].Area[y] == AreaNumCmp){ + if( (dType == 0) || (DirectCtlBoard[x].AssignType[y] == dType) ){ + if(UserCode >99999999){ + //UserCode OverFlow + return -10; + } + DirectCtlBoard[x].UcList[y].Full = UserCode; + UserCode += UserCodeItv; + ToWriteThis = 1; + ProceduredCount++; + } + } + } + if(ToWriteThis){ + ////Write One Direct Pad Here + if(WriteOneDirectPad(x) !=0){ + //Write One Direct Pad Error + return -9; + } + } + } + }else{ + //Avoid Mode + for(x=0; x99999999){ + //UserCode OverFlow + return -10; + } + Port[x].UcList[y].Full = UserCode; + UserCode += UserCodeItv; + ToWriteThis =1; + ProceduredCount++; + } + } + if(ToWriteThis){ + //Write One Port Here + if(WriteOnePort(x) !=0){ + //Write One Port Error + return -8; + } + } + //} + } + //Write Direct Pad + for(x=0; x < dDIRECTCTL_MAX_COUNT; x++){ + ToWriteThis = 0; + for(y=0; y < dDIRECTCTL_KEY_MAX_COUNT; y++){ + if(DirectCtlBoard[x].Area[y] == AreaNumCmp){ + if( (dType == 0) || (DirectCtlBoard[x].AssignType[y] == dType) ){ + int DoSkip; + do{ + DoSkip =0; + for(int i=0; i99999999){ + //UserCode OverFlow + return -10; + } + DirectCtlBoard[x].UcList[y].Full = UserCode; + UserCode += UserCodeItv; + ToWriteThis = 1; + ProceduredCount++; + } + } + } + if(ToWriteThis){ + ////Write One Direct Pad Here + if(WriteOneDirectPad(x) !=0){ + //Write One Direct Pad Error + return -9; + } + } + } + } + if(ProceduredCount == 0){ + return -100; + } + return ProceduredCount; +} + +void TUserCodeSetByArea::DrawWriteSta() +{ + int x,y; + x = Lv.Grid.Left[5] +4; + y = Lv.Grid.Top[5] +8; + if(Sta >0){ + if(Sta>99999)Sta = 99999; + if(LanguageEnCn==0){ + TextRender_string24(x, y, clNearWhite, ItemColor, "保存了"); + TextDigitRender5_24(x+72, y, clNearWhite, ItemColor, Sta); + TextRender_string24(x+132, y, clNearWhite, ItemColor, "个更改 "); + }else{ + TextDigitRender5_24(x, y, clNearWhite, ItemColor, Sta); + TextRender_string24(x+72, y, clNearWhite, ItemColor, "Items Been Saved"); + } + }else{ + if(LanguageEnCn==0){ + switch(Sta){ + case -100: + TextRender_string24(x, y, clNearWhite, ItemColor,"0 个更改 "); + break; + case -1: + TextRender_string24(x, y, clNearWhite, ItemColor,"分区号错误 "); + + break; + case -2: + TextRender_string24(x, y, clNearWhite, ItemColor,"类型超出范围 "); + break; + case -3: + TextRender_string24(x, y, clNearWhite, ItemColor,"新二次码长度超出范围"); + break; + case -4: + TextRender_string24(x, y, clNearWhite, ItemColor,"两段或以上的通配字段"); + break; + case -5: + TextRender_string24(x, y, clNearWhite, ItemColor,"通配字段长度不足 "); + break; + case -6: + TextRender_string24(x, y, clNearWhite, ItemColor,"通配字段递增溢出 "); + break; + case -7: + TextRender_string24(x, y, clNearWhite, ItemColor,"通配字段递减溢出 "); + break; + case -8: + //Write One Port Error + TextRender_string24(x, y, clNearWhite, ItemColor,"写入回路错误 "); + break; + case -9: + //Write One Direct Pad Error + TextRender_string24(x, y, clNearWhite, ItemColor,"写入多线盘错误 "); + break; + case -10: + //UserCode OverFlow + TextRender_string24(x, y, clNearWhite, ItemColor,"二次码超出范围 "); + break; + default: + TextRender_string24(x, y, clNearWhite, ItemColor," "); + break; + + } + }else{ + switch(Sta){ + case -100: + TextRender_string24(x, y, clNearWhite, ItemColor,"0 Items To Be Modify "); + break; + case -1: + TextRender_string24(x, y, clNearWhite, ItemColor,"Invalid Zone "); + + break; + case -2: + TextRender_string24(x, y, clNearWhite, ItemColor,"Invalid Assigned Type "); + break; + case -3: + TextRender_string24(x, y, clNearWhite, ItemColor,"Invalid,New ID "); + break; + case -4: + TextRender_string24(x, y, clNearWhite, ItemColor,"Invalid,Wildcard Field "); + break; + case -5: + TextRender_string24(x, y, clNearWhite, ItemColor,"Invalid,Wildcard Field "); + break; + case -6: + TextRender_string24(x, y, clNearWhite, ItemColor,"Invalid,Out Of Range "); + break; + case -7: + TextRender_string24(x, y, clNearWhite, ItemColor,"Invalid,Out Of Range "); + break; + case -8: + //Write One Port Error + TextRender_string24(x, y, clNearWhite, ItemColor,"Failed To Write To Loop"); + break; + case -9: + //Write One Direct Pad Error + TextRender_string24(x, y, clNearWhite, ItemColor,"Failed To Write To DB "); + break; + case -10: + //UserCode OverFlow + TextRender_string24(x, y, clNearWhite, ItemColor,"AuxID Out Of Range "); + break; + default: + TextRender_string24(x, y, clNearWhite, ItemColor," "); + break; + + } + } + } +} + +void TUserCodeSetByArea::DrawWriteSta(int aSta) +{ + Sta = aSta; + DrawWriteSta(); +} + + + diff --git a/MyCode/Gui/UserCodeSetByArea.h b/MyCode/Gui/UserCodeSetByArea.h new file mode 100644 index 0000000..810f7bc --- /dev/null +++ b/MyCode/Gui/UserCodeSetByArea.h @@ -0,0 +1,208 @@ +#ifndef USERCODESETBYAREA_H_ +#define USERCODESETBYAREA_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "EditML.h" + +//#pragma pack(push, 1) + +class TUserCodeSetByArea{ + public: + static constexpr unsigned short hList[12] = {78,114,40,40, 40,40,32,32, 32,32,32,32}; + static constexpr unsigned short wList[12] = {800,290,290,290, 290,290,290,290, 800,800,800,800}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]) +2, + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1] +2, + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (6 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + + .Grid.UsingCount = 6, + + .Panel.ItemType = piMemo, + .Panel.Left = wList[1] + 6, + .Panel.Top = (36 + 32 +2) + hList[0] +8, + .Panel.Width = 502, + .Panel.Heigh = 282, + .Panel.Right = wList[1] + 6 + 502 -1, + .Panel.Bottom = (36 + 32 +2) + hList[0] +6 + 282 -1, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .PanelSmall.Active = 0, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[5] + 10, + .y = Lv.Grid.Top[5] + 8, + }; + public: + int IsShow; + class TEditML mlEdit; + class TItemList *IList; + class TCtlPanel1 *aPanel; + + unsigned int AreaNum; + unsigned char dType; + unsigned char IsRecover; + unsigned char IncDec; + unsigned char AreaValid; + unsigned char dTypeValid; + unsigned char IsShowwingDetail; + unsigned char IsPermission; + unsigned char PermissionCmd; + + struct{ + struct{ + unsigned char PortNum; + unsigned char EpAddr; + unsigned char DirectPadNum; + unsigned char DirectKey; + }Erase, Write; + unsigned char IsPortOrPad; + unsigned char IsWritting; + unsigned char Dump0; + unsigned char Dump1; + int Counts4ThisArea; + }Detail; + + struct{ + struct{ + unsigned char PortNum; + unsigned char EpAddr; + unsigned char DirectPadNum; + unsigned char DirectKey; + }Erase, Write; + unsigned char IsPortOrPad; + unsigned char IsWritting; + unsigned char Dump0; + unsigned char Dump1; + int Counts4ThisArea; + }Writing; + + unsigned int CtlIndex; + + int Sta; + + char RawData[64]; + char UserCodeStr[8]; + + unsigned char IsEdittingDescp; + unsigned char IsExtInput; + unsigned char IsEdittingShortName; + unsigned char GotAst; + + int ItemCount; + int ListPage; + char ListText[20]; + + unsigned int UserCodePrv; + unsigned int UserCode; + + int UserCodeStart; + int UserCodeEnd; + int UserCodeItv; + public: + TUserCodeSetByArea(){}; + void Init(); + static void DelayMs(unsigned int aMs); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawRecover(); + void DrawIncDec(); + void DrawAssignTypeText(); + int DrawDetailStart(); + void DrawDetailGoOn(); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(void); + void Check4Selected(void); + + void CheckCount(); + void LoadAUserCode(); + void LoadShortName(); + void LoadDescp(); + void LoadData(); + + + void PermissionCmdGO(); + void PermissionCmdReturnDraw(); + + void DrawWriteSta(); + void DrawWriteSta(int aSta); + void ReadAllFromFlash(); + void ReadEntryViaFlash(); + void Write2Flash(); + int WriteOnePort(unsigned int aP0); + int WriteOneDirectPad(unsigned char aP0); + int Write(); + + int ExtRequst(unsigned char Prm){IsShow =0; return 0;} + +}; + + + + + + + + + + + + + + + + + + + + + + + + + +//#pragma pack(pop) + + + +#endif + diff --git a/MyCode/Gui/UserSet.cpp b/MyCode/Gui/UserSet.cpp new file mode 100644 index 0000000..c7f64fb --- /dev/null +++ b/MyCode/Gui/UserSet.cpp @@ -0,0 +1,1187 @@ +#include "UserSet.h" + +#include "Runtime.h" + +#define TextTopOffSet 6 +#define ListLineCnt 10 + +#define dAddrSdram_UserCodeP0 (dAddrSdRam_Commom) +#define dAddrSdram_UserCodeP1 (dAddrSdRam_Commom + 2048) +#define dAddrSdram_DescpBufP0 (dAddrSdRam_Commom + 4096) +#define dAddrSdram_DescpBufP1 (dAddrSdRam_Commom + 20480) + +void TUserSet::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + SText.Init (519, Top, 280, CH, 0, 0, clWhite, clMaroon); + VScrollBarBox.Set(Right-20 +1, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + ActiveLineNum=0; + Load0.Count=0; + Load1.SelectedIndex=0; + + Lv.ColHeight = 33; + Lv.TopIndex=0; + Lv.RowCount = 9; + Lv.FixColTop = Content.Top; + Lv.FixColBottom = Lv.FixColTop + Lv.ColHeight; + Lv.ColTop[0] = Lv.FixColBottom + 1; + Lv.ColBottom[0] = Lv.ColTop[0] + Lv.ColHeight -1; + Lv.ColLeft[0] = 1; + Lv.ColRight[0] = Lv.ColWidth[0] +1; + for(i=1; i<12; i++){ + Lv.ColTop[i] = Lv.ColTop[i -1] + Lv.ColHeight; + Lv.ColBottom[i] = Lv.ColBottom[i-1] + Lv.ColHeight; + } + for(i=1;i Content.Bottom)y2 = Content.Bottom; + if(x == Lv.SelectedCol){ + RectFillRender(Content.Left, y, Content.Right, y2, SelectedColor); + }else{ + if(x & 1){ + RectFillRender(Content.Left, y, Content.Right, y2, OddColor); + }else{ + RectFillRender(Content.Left, y, Content.Right, y2, Color); + } + } + y = y2 + 1; + if(y>Content.Bottom)break; + } +} + +void TUserSet::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderContent(); +} + +void TUserSet::DrawCaption(void) +{ + Caption.Show(); + if(ViewPath == 0){ + DrawCaption1(); + }else{ + DrawCaption2(); + } +} + +void TUserSet::DrawCaption1(void) +{ + if(IsProgram){ + TMyString::sFromStr("按查询键进入子部件设置", SText.Text); + }else{ + TMyString::sFromStr(" 按查询键进入子部件 ", SText.Text); + } + SText.Show(); +} + +void TUserSet::DrawCaption2(void) +{ + if(IsProgram){ + TMyString::sFromStr("按确定键确认保存", SText.Text); + }else{ + TMyString::sFromStr(" ", SText.Text); + } + SText.Show(); +} + +void TUserSet::LoadTextToTemp(unsigned int aAddr) +{ + int i; + for(i=0; i<32; i++){ + CommomGuiTempText[i] = *(volatile unsigned char *)(aAddr + i); + } + CommomGuiTempText[32]='\0'; +} + +void TUserSet::DrawList(void) +{ + int i,j, aTop, aImg; + unsigned int idx, addr, aP0, aP1, aCode; + unsigned int aClr; + unsigned char aType; + if(1){ + RenderContent(); + aTop = Lv.FixColTop + TextTopOffSet; + if(ViewPath == 0){ + if(Load0.Count <1)return; + SetListColWidth(30,80,60,80,500,1,1,1,1); + TextRender_string24(Lv.ColLeft[1],aTop,TextColor, "类型" ); + TextRender_string24(Lv.ColLeft[2],aTop,TextColor, "序号" ); + TextRender_string24(Lv.ColLeft[3],aTop,TextColor, " 用户码"); + TextRender_string24(Lv.ColLeft[4],aTop,TextColor, " 描述"); + idx = Lv.TopIndex ; + for(i=0; i -1){ + RestoreFromEdit(); + if(aIndex < Lv.TopIndex){ + Lv.TopIndex = aIndex; + }else{ + Lv.SelectedCol--; + } + Load0.SelectedIndex = aIndex; + ReDraw(); + SetEditStart(); + } + break; + case VK_DOWN: + aIndex = Load0.SelectedIndex +1; + if(aIndex < Load0.Count){ + RestoreFromEdit(); + if(aIndex > (Lv.TopIndex + ListLineCnt -1) ){ + Lv.TopIndex++; + }else{ + Lv.SelectedCol++; + } + Load0.SelectedIndex = aIndex; + ReDraw(); + SetEditStart(); + } + break; + case VK_TAB: + /*if(IsEditUsercode){ + RestoreFromEdit(); + IsEditUsercode = 0; + IsEditDescp = 1; + ReDraw(); + SetEditStart(); + }else{ + RestoreFromEdit(); + IsEditUsercode = 1; + IsEditDescp = 0; + ReDraw(); + SetEditStart(); + }*/ + break; + case VK_EXECUTE: + ShowIfSave(); + break; + } + }else + if(ViewPath == 1){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case '*': + case '#': + case VK_LEFT: + case VK_RIGHT: + case VK_DELETE: + vEdit.KeyIn(aKey); + vEdit.Show(); + vEdit.ShowCursor(clNearWhite); + break; + case VK_UP: + aIndex = Load1.SelectedIndex -1; + if(aIndex > -1){ + RestoreFromEdit(); + if(aIndex < Lv.TopIndex){ + Lv.TopIndex = aIndex; + }else{ + Lv.SelectedCol--; + } + Load1.SelectedIndex = aIndex; + ReDraw(); + SetEditStart(); + } + break; + case VK_DOWN: + aIndex = Load1.SelectedIndex +1; + if(aIndex < Load1.Count){ + RestoreFromEdit(); + if(aIndex > (Lv.TopIndex + ListLineCnt -1) ){ + Lv.TopIndex++; + }else{ + Lv.SelectedCol++; + } + Load1.SelectedIndex = aIndex; + ReDraw(); + SetEditStart(); + } + break; + case VK_TAB: + /*if(IsEditUsercode){ + RestoreFromEdit(); + IsEditUsercode = 0; + IsEditDescp = 1; + ReDraw(); + SetEditStart(); + }else{ + RestoreFromEdit(); + IsEditUsercode = 1; + IsEditDescp = 0; + ReDraw(); + SetEditStart(); + }*/ + break; + case VK_EXECUTE: + ShowIfSave(); + break; + } + } + if(aKey == VK_RETURN){ + RestoreFromEdit(); + OnEditing = 0; + ReDraw(); + } + }else{ + if(aKey == VK_TAB){ + + } + if(VK_UP == aKey){ + if(ViewPath ==0){ + aIndex = Load0.SelectedIndex -1; + if(aIndex > -1){ + if(aIndex < Lv.TopIndex){ + Lv.TopIndex = aIndex; + }else{ + Lv.SelectedCol--; + } + Load0.SelectedIndex = aIndex; + ReDraw(); + } + }else + if(ViewPath ==1){ + aIndex = Load1.SelectedIndex -1; + if(aIndex > -1){ + if(aIndex < Lv.TopIndex){ + Lv.TopIndex = aIndex; + }else{ + Lv.SelectedCol--; + } + Load1.SelectedIndex = aIndex; + ReDraw(); + } + } + }else + if(VK_DOWN == aKey){ + if(ViewPath ==0){ + aIndex = Load0.SelectedIndex +1; + if(aIndex < Load0.Count){ + if(aIndex > (Lv.TopIndex + ListLineCnt -1) ){ + Lv.TopIndex++; + }else{ + Lv.SelectedCol++; + } + Load0.SelectedIndex = aIndex; + ReDraw(); + } + }else + if(ViewPath ==1){ + aIndex = Load1.SelectedIndex +1; + if(aIndex < Load1.Count){ + if(aIndex > (Lv.TopIndex + ListLineCnt -1) ){ + Lv.TopIndex++; + }else{ + Lv.SelectedCol++; + } + Load1.SelectedIndex = aIndex; + ReDraw(); + } + } + }else + //Page up or Down____________________________ + + if(aKey == VK_LEFT){ + if(ViewPath == 0){ + GridX = 0; + }else + if(ViewPath == 1){ + GridX = 0; + } + }else + if(aKey == VK_RIGHT){ + if(ViewPath == 0){ + GridX = 0; + }else + if(ViewPath == 1){ + GridX = 1; + } + }else + if(aKey == VK_EXECUTE){ + //Open path Device + if(IsProgram){ + ShowIfSave(); + } + }else + if(aKey == VK_F1 ){ + //Setup Device Property + if(IsProgram){ + if(ViewPath == 0){ + SetEditStart(); + }else + if(ViewPath == 1){ + SetEditStart(); + } + } + }else + if(aKey == VK_F2){ + if(ViewPath == 0){ + if(Load0.addr[Load0.SelectedIndex] != 0){ + BkP0TopIndex = Lv.TopIndex; + ClearPath1(); + LoadPath1(); + ViewPath = 1; + ReDraw(); + } + } + }else + if(aKey == VK_RETURN){ + if(ViewPath == 0){ + aMsg = guiMsgReturn; + }else + if(ViewPath == 1){ + ClearPath0(); + LoadPath0(); + Lv.TopIndex = BkP0TopIndex; + Lv.SelectedCol = Load0.SelectedIndex - Lv.TopIndex; + ViewPath = 0; + ReDraw(); + }else + if(ViewPath > 1){ + ClearPath1(); + LoadPath1(); + ViewPath = 1; + ReDraw(); + } + } + } + //____________________________________________________________________<- List View + + return aMsg; + +} + +void TUserSet::ClearPath0(void) +{ + unsigned int i; + Load0.Count =0; + for(i=0;i<64;i++){ + Load0.addr[i] =0; + } + Load0.SelectedIndex = 0; + Lv.TopIndex = 0; +} + +void TUserSet::ClearPath1(void) +{ + unsigned int i; + for(i=0;i<256;i++){ + Load1.addr[i] = 0; + } + Load1.Count = 0; + Load1.SelectedIndex = 0; + Lv.TopIndex = 0; +} + +void TUserSet::LoadPath0Item(unsigned char aP) +{ + if(Load0.Count < 65){ + Load0.addr[Load0.Count] = aP; + Load0.Count++; + } +} + +void TUserSet::LoadPath1Item(unsigned char aP) +{ + if(Load1.Count < 256){ + Load1.addr[Load1.Count]= aP; + Load1.Count++; + } +} + +void TUserSet::LoadPath0(void) +{ + int i; + for(i=0; i用户码->根设备", Caption.Text); + TMyString::sAddOnStr(" 按设置键开始设置", Caption.Text); + + Caption.FullRedraw(); +} + +void TUserSet::LoadPath1(void) +{ + unsigned int i; + unsigned char aP0, aLim; + + aP0 = Load0.addr[Load0.SelectedIndex]; + if(aP0 == 0)return; + if(aP0 > 64) return; + Load1.Count = 0; + if(aP0 < 41){ + ClearPath1(); + Load1.P0 = aP0; + aP0 = aP0-1; + + for(i=0; i< dEP_MAX_COUNT_PER_PORT; i++){ + if(Port[aP0].ExistTable[i] == 0xA5) + LoadPath1Item(i+1); + } + }else + if(aP0 < 49){ + ClearPath1(); + Load1.P0 = aP0; + aP0 = aP0 -40 -1; + aLim = HandCtlBoard[aP0].fData.HandCtl.ResistedCount; + for(i=0; i< aLim; i++){ + LoadPath1Item(i+1); + } + }else + if(aP0 < 57){ + ClearPath1(); + Load1.P0 = aP0; + aP0 = aP0 -48 -1; + aLim = DirectCtlBoard[aP0].fData.HandCtl.ResistedCount; + for(i=0; i< aLim; i++){ + LoadPath1Item(i+1); + } + } + + TMyString::sFromStr("系统设置->用户码->终端设备", Caption.Text); + TMyString::sAddOnStr(" 按设置键开始设置", Caption.Text); + + Caption.FullRedraw(); + + Lv.SelectedCol = 0; + Lv.TopIndex = 0; +} + diff --git a/MyCode/Gui/UserSet.h b/MyCode/Gui/UserSet.h new file mode 100644 index 0000000..7eb1b9d --- /dev/null +++ b/MyCode/Gui/UserSet.h @@ -0,0 +1,180 @@ +#ifndef USERSET_H_ +#define USERSET_H_ + +#include "gType.h" +#include "GraphBase.h" +//#include "stdio.h" +//#include "stdlib.h" +//#include "string.h" +#include "my_string.h" +#include "TEdit.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "MainCtl.h" +#include "Runtime.h" + +#define dLISTVIEW_VSCOLLBAR_WIDTH 20 + +//For Device View or Edit +class TUserSet{ + public: + struct{ + u32 Color; + u32 RibbonColor; + }VScrollBar; + class TEdit vEdit; + struct{ + int TopIndex; + unsigned short RowCount; + unsigned short ColTop[12]; + unsigned short ColBottom[12]; + unsigned short ColHeight; + unsigned short ColWidth[12]; + unsigned short ColLeft[12]; + unsigned short ColRight[12]; + unsigned short FixColTop; + unsigned short FixColBottom; + unsigned int TransparrentColor; + int SelectedCol; + }Lv; + int BkP0TopIndex; + struct{ + int Count; + int SelectedIndex; + unsigned char addr[64]; + }Load0; + struct{ + int Count; + int SelectedIndex; + unsigned char P0; + unsigned char addr[256]; + }Load1; + + unsigned char IsProgram; + + public: + TStaticText Caption; + TStaticText SText; + unsigned int ViewPath; + int ActiveLineNum; + int LineHeight; + float ScrollVertical; + + u32 FixColColor; + u32 FixColTextColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect VScrollBarBox; + TRect Content; + + unsigned char GridX; + unsigned char OnEditing; + unsigned char IsEditUsercode; + unsigned char IsEditDescp; + unsigned char EditUsercodeIndex; + unsigned char EditDescpIndex; + unsigned char AskingSave; + private: + void SetListColWidth(int w0, int w1, int w2, int w3, int w4,int w5,int w6, int w7, int w8); + void LoadPath0Item(unsigned char aP); + void LoadPath1Item(unsigned char aP); + + void DrawVScrollBar_ListView(void); + void DrawVScrollBar_IconView(void); + TGuiMsgReturn QueryKeyIn(unsigned char aKey); + TGuiMsgReturn EditKeyIn(unsigned char aKey); + + public: + TUserSet(){}; + TUserSet(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + unsigned int ItemGetIcon(unsigned int aIndex); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DrawShortList(void); + void DrawList(void); + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawCaption(void); + void DrawCaption1(void); + void DrawCaption2(void); + void RenderContent(void); + + void DrawValueP0(void); + void DrawValueP1(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearPath0(void); + void ClearPath1(void); + void LoadPath0(void); + void LoadPath1(void); + void SetEditMode(unsigned int aMode); + + void DataInit(); + void DataLoad(); + void LoadTextToTemp(unsigned int aAddr); + + void FullRePaint(void); + void RePaint(void); + void ShowIfSave(); + + void DevPropertyInit(void); + + void SetEditStart(void); + void RestoreFromEdit(void); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif + diff --git a/MyCode/Gui/WifiConn.cpp b/MyCode/Gui/WifiConn.cpp new file mode 100644 index 0000000..17d2b64 --- /dev/null +++ b/MyCode/Gui/WifiConn.cpp @@ -0,0 +1,442 @@ +#include "WifiConn.h" +#include "Runtime.h" + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +static const int xFirst = 10; +static const int xSec = 260; +static const int xThi = 290; +static const int xFourth = 430; +static const int xFifth = 570; + +void TWifiConn::Init() +{ + CtlIndex = 0; + IsShowing = 0; + IsOnGoing = 0; + ReadWrite =0; + + IsPermission =0; + + OnOff.Share =0; + OnOff.Cmsn =0; + OnOff.ReadOnly =1; + OnOff.Mute =0; + OnOff.Reset =0; + + State.DeviceOn =0; + State.Connection =0; + State.Rsv1 =1; + State.Rsv2 =2; +} + +void TWifiConn::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickWifi传输"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Wifi设置"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "工作模式"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "数据权限"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "操作权限"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "开启", 38, clNearBlack); + TRoundRect::sDrawBySize(160, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "关闭", 38, clNearBlack); + TextRender_string24(xFirst + 30, Lv.Grid.Top[1] + 40, clNearWhite, "信息共享"); + TextRender_string24(xSec +30, Lv.Grid.Top[1] + 40, clNearWhite, "调试"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[2] + 40, clNearWhite, "只读"); + TextRender_string24(xSec +30, Lv.Grid.Top[2] + 40, clNearWhite, "读写"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[3] + 40, clNearWhite, "消音"); + TextRender_string24(xSec +30, Lv.Grid.Top[3] + 40, clNearWhite, "复位"); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Data Transmission->Wifi"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "Wifi Setting"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Mode"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Data Permission"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "Operating Permission"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "Enable", 26, clNearBlack); + TRoundRect::sDrawBySize(160, Lv.Grid.Top[0] + 36, 120, 30, 7, clNearWhite, "Disable", 26, clNearBlack); + TextRender_string24(xFirst + 30, Lv.Grid.Top[1] + 40, clNearWhite, "Interconnection"); + TextRender_string24(xSec +30, Lv.Grid.Top[1] + 40, clNearWhite, "Test Only"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[2] + 40, clNearWhite, "Read Only"); + TextRender_string24(xSec +30, Lv.Grid.Top[2] + 40, clNearWhite, "Read Write"); + TextRender_string24(xFirst + 30, Lv.Grid.Top[3] + 40, clNearWhite, "Mute"); + TextRender_string24(xSec +30, Lv.Grid.Top[3] + 40, clNearWhite, "Reset"); + } +} + +void TWifiConn::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + for(int i=0; i 1){ + ClearSelected(); + CtlIndex-=2; + Check4Selected(); + } + break; + case VK_DOWN: + if(CtlIndex < 6){ + ClearSelected(); + CtlIndex+=2; + Check4Selected(); + } + break; + case dfKEY_SETUP: + if(CtlIndex == 2){ + OnOff.Share = OnOff.Share ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 3){ + OnOff.Cmsn = OnOff.Cmsn ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 4){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 5){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 6){ + OnOff.Mute = OnOff.Mute ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 7){ + OnOff.Reset = OnOff.Reset ? 0 : 1; + DrawSetting(); + } + break; + case VK_TAB: + + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + //Active + PermissionCmd = 1; + if(SystemPermission > 2){ + PermissionCmdGO(); + }else{ + IsPermission = 1; + ClearSelected(); + PmsIntervene4Gui.Show4Gui(100, Lv.Grid.Top[1] + 12, 600 , 120, 3); + } + }else + if(CtlIndex == 1){ + //Close + PermissionCmd = 2; + PermissionCmdGO(); + } + if(CtlIndex == 2){ + OnOff.Share = OnOff.Share ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 3){ + OnOff.Cmsn = OnOff.Cmsn ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 4){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 5){ + OnOff.ReadOnly = OnOff.ReadOnly ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 6){ + OnOff.Mute = OnOff.Mute ? 0 : 1; + DrawSetting(); + }else + if(CtlIndex == 7){ + OnOff.Reset = OnOff.Reset ? 0 : 1; + DrawSetting(); + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + + return aMsg; +} + +void TWifiConn::sRecoverSetDefault() +{ + SysLoopTick = 0; +} + +int TWifiConn::ExtRequst(unsigned char Prm) +{ + IsShowing =0; + return 0; +} + +void TWifiConn::Task1000Ms() +{ + +} + + + + + + diff --git a/MyCode/Gui/WifiConn.h b/MyCode/Gui/WifiConn.h new file mode 100644 index 0000000..b037987 --- /dev/null +++ b/MyCode/Gui/WifiConn.h @@ -0,0 +1,147 @@ +#ifndef WIFICONN_H_ +#define WIFICONN_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TWifiConn{ + public: + static constexpr unsigned short hList[12] = {70,70,70,70, 72,72,34,34, 34,34,34,34}; + static constexpr unsigned short wList[12] = {800,800,800,800, 290,290,290,290, 290,290,290,290}; + static constexpr TLv Lv = { + .Caption.Left = 0, + .Caption.Top = 36, + .Caption.Width = 800, + .Caption.Heigh = 32, + .Caption.Right = 800 -0 -1, + .Caption.Bottom = 36 + 32, + + .Grid.Left = {0,0,0,0, 0,0,0,0, 0,0,0,0}, + .Grid.Right = {wList[0]-1,wList[1]-1,wList[2]-1,wList[3]-1, wList[4]-1,wList[5]-1,wList[6]-1,wList[7]-1, wList[8]-1,wList[9]-1,wList[10]-1,wList[11]-1}, + .Grid.Top[0] = (36 + 32 +2), + .Grid.Top[1] = (36 + 32 +2) + (2 + hList[0]), + .Grid.Top[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]), + .Grid.Top[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]), + .Grid.Top[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]), + .Grid.Top[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]), + .Grid.Top[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]), + .Grid.Top[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]), + .Grid.Top[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]), + .Grid.Top[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]), + .Grid.Top[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]), + .Grid.Top[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]), + + .Grid.Bottom[0] = (36 + 32 +2) + hList[0], + .Grid.Bottom[1] = (36 + 32 +2) + (2 + hList[0]) + hList[1], + .Grid.Bottom[2] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + hList[2], + .Grid.Bottom[3] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3], + .Grid.Bottom[4] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + hList[4], + .Grid.Bottom[5] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + hList[5], + .Grid.Bottom[6] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + hList[6], + .Grid.Bottom[7] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + hList[7], + .Grid.Bottom[8] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + hList[8], + .Grid.Bottom[9] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + hList[9], + .Grid.Bottom[10] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + hList[10], + .Grid.Bottom[11] = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + (2 + hList[3]) + (2 + hList[4]) + (2 + hList[5]) + (2 + hList[6]) + (2 + hList[7]) + (2 + hList[8]) + (2 + hList[9]) + (2 + hList[10]) + hList[11], + + .Grid.UsingCount = 4, + + .Panel.Active = 1, + .Panel.ItemType = piMemo, + .Panel.Left = 0 + 2, + .Panel.Top = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3] +4, + .Panel.Width = 796, + .Panel.Heigh = 80, + .Panel.Right = 0 + 2 + 796 -1, + .Panel.Bottom = (36 + 32 +2) + (2 + hList[0]) + (2 + hList[1]) + (2 + hList[2]) + hList[3] +4 + 80 -1, + + .PanelSmall.Active = 0, + .PanelSmall.Left = 0 + 6, + .PanelSmall.Top = (36 + 36 +2) + hList[0] +6 + 220 -1 + 3, + .PanelSmall.Width = 788, + .PanelSmall.Heigh = 70, + .PanelSmall.Right = 0 + 6 + 788 -1, + .PanelSmall.Bottom = (36 + 36 +2) + hList[0] +6 + 220 -1 + 1 + 70 -1, + }; + static constexpr TPoint ResultTipPoint = { + .x = Lv.Grid.Left[6] + 10, + .y = Lv.Grid.Top[6] + 8, + }; + public: + int IsShowing; + unsigned char CtlIndex; + + unsigned char IsPermission; + unsigned char PermissionCmd; + + unsigned char CrtNum; + unsigned char CrtNumValid; + + + unsigned char LineType; + unsigned char ReadWrite; + unsigned char IsOnGoing; + + char Text[68]; + + struct{ + unsigned char Share; + unsigned char Cmsn; + unsigned char ReadOnly; + unsigned char Mute; + unsigned char Reset; + unsigned char Sv0; + unsigned char Sv1; + unsigned char Sv2; + }OnOff; + struct{ + unsigned char DeviceOn; + unsigned char Connection; + unsigned char Rsv1; + unsigned char Rsv2; + }State; + + public: + TWifiConn(){}; + void Init(); + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void DelayMs(unsigned int aMs); + + void Show(void); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawFixText(); + + void DrawConnState(); + + void DrawSetting(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void ClearSelected(); + void Check4Selected(void); + + void PermissionCmdReturnDraw(); + void PermissionCmdGO(); + + static void sRecoverSetDefault(); + + void Task1000Ms(); + + int ExtRequst(unsigned char Prm); + +}; + + + + +#endif diff --git a/MyCode/Gui/XBox.cpp b/MyCode/Gui/XBox.cpp new file mode 100644 index 0000000..beae7f3 --- /dev/null +++ b/MyCode/Gui/XBox.cpp @@ -0,0 +1,282 @@ +#include "XBox.h" + +void TXBox::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + + OutlineColor = clGray; + TextColor = clNearBlack; + SelectedColor = clBlue; + + LineSpacing = 36; + CheckPointX = Content.Left +10; + TextPstX = Content.Left + 40; + ItemsTopY = Content.Top + 15; + CheckWidgetSize = 8; + TextPixelWidth = 240; + + Items.FocusIndex =0; + Items.SelectedIndex =-1; + + BoxType = btRadioGroup; +} + +void TXBox::ReDrawItems() +{ + int i, x1, x2, y1, y2; + if(Items.Count > drgMAX_COUNT) Items.Count =drgMAX_COUNT; + if(CheckWidgetSize > 12)CheckWidgetSize =12; + x1 = CheckPointX + Content.Left + 12; + y1 = ItemsTopY + Content.Top + 12; + x2 = TextPstX + Content.Left; + y2 = ItemsTopY + Content.Top; + if(BoxType == btRadioGroup){ + for(i=0; i 0) ){ + Items.SelectedIndex --; + ReDrawItems(); + } + }else + if(aKey == VK_RIGHT){ + if( (Items.SelectedIndex < Items.Count) && (Items.SelectedIndex > 0) ){ + Items.SelectedIndex --; + ReDrawItems(); + } + }else + if(aKey == VK_UP){ + if(Items.SelectedIndex >0){ + Items.SelectedIndex--; + ReDrawItems(); + } + }else + if(aKey == VK_DOWN){ + if(Items.SelectedIndex <(Items.Count-1)){ + Items.SelectedIndex++; + ReDrawItems(); + } + }else + if(aKey == VK_F1){ + Items.SelectedIndex++; + if(Items.SelectedIndex >= Items.Count){ + Items.SelectedIndex = 0; + } + ReDrawItems(); + }else + if(aKey == VK_TAB){ + Items.SelectedIndex++; + if(Items.SelectedIndex >= Items.Count){ + Items.SelectedIndex = 0; + } + ReDrawItems(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + return aMsg; + }else + if(BoxType == btGroupBox){ + if(aKey == VK_LEFT){ + if( Items.SelectedIndex < Items.Count ){ + if(Items.CheckList[Items.SelectedIndex]) + Items.CheckList[Items.SelectedIndex] =0; + else + Items.CheckList[Items.SelectedIndex] =1; + ReDrawItems(); + } + }else + if(aKey == VK_RIGHT){ + if( Items.SelectedIndex < Items.Count ){ + if(Items.CheckList[Items.SelectedIndex]) + Items.CheckList[Items.SelectedIndex] =0; + else + Items.CheckList[Items.SelectedIndex] =1; + ReDrawItems(); + } + }else + if(aKey == VK_UP){ + if(Items.SelectedIndex >0){ + Items.SelectedIndex--; + ReDrawItems(); + } + }else + if(aKey == VK_DOWN){ + if(Items.SelectedIndex <(Items.Count-1)){ + Items.SelectedIndex++; + ReDrawItems(); + } + }else + if(aKey == VK_F1){ + if( (Items.SelectedIndex < Items.Count) && (Items.SelectedIndex > -1) ){ + if(Items.CheckList[Items.SelectedIndex]) + Items.CheckList[Items.SelectedIndex] =0; + else + Items.CheckList[Items.SelectedIndex] =1; + ReDrawItems(); + } + }else + if(aKey == VK_TAB){ + Items.SelectedIndex++; + if(Items.SelectedIndex >= Items.Count){ + Items.SelectedIndex = 0; + } + ReDrawItems(); + } + if(aKey == VK_EXECUTE){ + //Save Data Here + + }else + if(aKey == VK_RETURN){ + aMsg = guiMsgReturn; + } + return aMsg; + } + return aMsg; +} + +void TXBox::sDrawBoxBorder(int x, int y, int x2, int y2, char *chr, int tLen, int aEn, int aSel, unsigned int bClr) +{ + int aW, aH, aTW; + unsigned int aClr, aTClr; + aTW = tLen * 12 +12; + + if(aSel){ + aClr = clBlue; + aTClr = clBlue; + }else{ + if(aEn){ + aClr = clGray; + aTClr = clGray; + }else{ + aClr = clSilver; + aTClr = clSilver; + } + } + + aW = x2 - x +1; + aH = y2 - y +1; + + VertLineRender(x, y+12, aH-12, aClr); + VertLineRender(x+1, y+12, aH-12, aClr); + VertLineRender(x2, y+12, aH-12, aClr); + VertLineRender(x2-1, y+12, aH-12, aClr); + + HorizLineRender(x, y+12, 6, aClr); + HorizLineRender(x, y+12+1, 6, aClr); + HorizLineRender(x, y2, aW, aClr); + HorizLineRender(x, y2 -1, aW, aClr); + + HorizLineRender(x + aTW +6, y+12, aW -6 -aTW, aClr); + HorizLineRender(x + aTW +6, y+12+1, aW -6 -aTW, aClr); + + TextRender_string24(x + 8, y, aTClr, bClr, chr); +} + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/XBox.h b/MyCode/Gui/XBox.h new file mode 100644 index 0000000..2e44cbb --- /dev/null +++ b/MyCode/Gui/XBox.h @@ -0,0 +1,84 @@ +#ifndef XBOX_H_ +#define XBOX_H_ + +#include "gType.h" +#include "GraphLow.h" +#include "GraphBase.h" +#include "stdio.h" +#include "stdlib.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "TEdit.h" + +#define drgMAX_COUNT 12 + +typedef enum{ + btRadioGroup = 0, + btGroupBox =1, + +}TXBoxType; + +class TXBox{ + public: + struct{ + int Count; + int SelectedIndex; + int FocusIndex; + unsigned char CheckList[drgMAX_COUNT]; + }Items; + TStaticText Caption; + TMyString Str[drgMAX_COUNT]; + + int LineSpacing; + + u32 OutlineColor; + u32 Color; + u32 TextColor; + u32 SelectedColor; + u32 SelectedTextColor; + + TRect Bound; + TRect Content; + + int CheckPointX; + int TextPstX; + int ItemsTopY; + int CheckWidgetSize; + int TextPixelWidth; + TXBoxType BoxType; + public: + TXBox(){}; + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetTextPixelWidth(int aW); + void ReDrawItems(); + void Show(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + int ExtRequst(unsigned char Prm){return 0;} + + static void sDrawBoxBorder(int x, int y, int x2, int y2, char *chr, int tLen, int aEn, int aSel, unsigned int bClr); + + + +}; + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/Gui/aBefore.cpp b/MyCode/Gui/aBefore.cpp new file mode 100644 index 0000000..7d52cb7 --- /dev/null +++ b/MyCode/Gui/aBefore.cpp @@ -0,0 +1,246 @@ +#include "aBefore.h" + +void TaBefore::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left,Top,Width, CH, 0, 0, clWhite, clMaroon); + Content.Set(Left, Top+CH, Right, Bottom); + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + TMyString::sFromStr("设置试用期-本机", Caption.Text); + Caption.Visible = 1; + + CtlIndex = 0; + OnActive = 0; + +} + +void TaBefore::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TaBefore::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TaBefore::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); +} + +void TaBefore::Show(void) +{ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + +} + +void TaBefore::FullRedraw(int Prm) +{ + if(Prm == 0){ + RenderBackGround(); + DrawSelf(); + Caption.Show(); + aPanel->Show(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } + +} + + +//______________________________________________________________________________________________________________________________ + +void TaBefore::Check4Selected(void) +{ + unsigned int i; + for(i=0; i<3;i++)aPanel->Edit[i].Selected = 0; + for(i=0; i<1;i++)aPanel->Btn[i].Selected = 0; + if(1){ + switch(CtlIndex){ + case 0: + aPanel->Edit[0].Selected = 1; + break; + case 1: + aPanel->Edit[1].Selected = 1; + break; + case 2: + aPanel->Edit[2].Selected = 1; + break; + case 3: + aPanel->Btn[0].Selected = 1; + break; + default: + + break; + } + } +} + +//_____________________________________________________________________________________________________________________________ + +TGuiMsgReturn TaBefore::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + TGuiMsgReturn MBoxMsg = guiMsgNone; + int iVal; + + switch(aKey){ + case VK_DELETE: + case VK_0: + case VK_1: + case VK_2: + case VK_3: + case VK_4: + case VK_5: + case VK_6: + case VK_7: + case VK_8: + case VK_9: + case VK_LEFT: + case VK_RIGHT: + if(CtlIndex <3){ + if(aPanel->Edit[CtlIndex].Enable){ + aPanel->Edit[CtlIndex].KeyIn(aKey); + aPanel->Edit[CtlIndex].ReDraw(); + } + } + break; + case VK_UP: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <3){ + CtlIndex++; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + break; + case VK_EXECUTE: + //Save Data Here + if(CtlIndex == 4){ + + } + break; + case VK_RETURN: + aMsg = guiMsgReturn; + break; + } + + return aMsg; +} + +void TaBefore::InitPanel(void) +{ + int x,y,x2,y2,i; + + y = y+6; + + aPanel->Init(130,120,540,200,0,0,clFrmFace, bvRaised); + aPanel->Caption.Init(131,121, 540-3 ,32,0,0,clFrmFace,clFrmFace); + + x = aPanel->Bound.Left; + y = aPanel->Bound.Top; + + aPanel->SText[0].Init(6,7,102,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(6,39,102,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(6,71,102,30,x,y,clNearBlack,clFrmFace); + + TMyString::sFromStr("实施许可码1", aPanel->SText[0].Text); + TMyString::sFromStr("实施许可码2", aPanel->SText[1].Text); + TMyString::sFromStr("试用延长天数 1~60", aPanel->SText[2].Text); + + aPanel->Edit[0].Init(230,7,306,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[1].Init(230,39,306,30,x,y,clNearBlack,clNearWhite); + aPanel->Edit[2].Init(230,71,306,30,x,y,clNearBlack,clNearWhite); + + for(i=0; i<3;i++){ + aPanel->Edit[i].Enable = 1; + aPanel->Edit[i].Visible = 1; + aPanel->Edit[i].SetInputMaskEn(); + aPanel->Edit[i].Str.FromStr("20"); + } + + aPanel->Edit[0].Str.FromStr("1"); + aPanel->Edit[1].Str.FromStr("1"); + aPanel->Edit[2].Str.FromStr("10"); + aPanel->Edit[0].SetMaxLen(24); + aPanel->Edit[1].SetMaxLen(24); + aPanel->Edit[2].SetMaxLen(2); + aPanel->Edit[0].SetPstTail(); + aPanel->Edit[1].SetPstTail(); + aPanel->Edit[2].SetPstTail(); + + aPanel->Btn[0].Init(146,150,200,36,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr(" 执行设置 "); + + for(i=0; i<1;i++){ + aPanel->Btn[i].Enable = 1; + aPanel->Btn[i].Visible = 1; + aPanel->Btn[i].SetCaptionLeftSpacing(2); + aPanel->Btn[i].SelectedColor = clBlue; + } + + aPanel->Caption.Visible = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); +} + + + + + + + + diff --git a/MyCode/Gui/aBefore.h b/MyCode/Gui/aBefore.h new file mode 100644 index 0000000..53fcf3c --- /dev/null +++ b/MyCode/Gui/aBefore.h @@ -0,0 +1,57 @@ +#ifndef ABEFORE_H_ +#define ABEFORE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" +#include "ProtoInnerCan.h" + +class TaBefore{ + public: + unsigned int OnActive; + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + + u32 Color; + + int TabOrder; + + TRect Bound; + TRect Content; + + unsigned int CtlIndex; + + public: + TaBefore(){}; + TaBefore(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + + void Show(void); + void FullRedraw(int Prm); + void ReDraw(void); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(); + void Check4Selected(void); + + int ExtRequst(unsigned char Prm){return 0;} +}; + + + +#endif + diff --git a/MyCode/Gui/asc_8x16.cpp b/MyCode/Gui/asc_8x16.cpp new file mode 100644 index 0000000..c25a691 --- /dev/null +++ b/MyCode/Gui/asc_8x16.cpp @@ -0,0 +1,100 @@ +#include"my_font.h" + +const unsigned char ascii_8x16[1536] = { +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00, 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+1,34 @@ +#ifndef EXTERN_C_INCLUDE_H_ +#define EXTERN_C_INCLUDE_H_ + +extern void LTDC_Draw_Point(unsigned short x,unsigned short y,unsigned int color); + +//D2d +extern void LTDC_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned int color); +extern void LTDC_Color_Fill(unsigned short sx,unsigned short sy,unsigned short ex,unsigned short ey,unsigned short *color); + + + +#endif + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/Gui/fNetworkReg.cpp b/MyCode/Gui/fNetworkReg.cpp new file mode 100644 index 0000000..39cc92c --- /dev/null +++ b/MyCode/Gui/fNetworkReg.cpp @@ -0,0 +1,1846 @@ +#include "fNetworkReg.h" +#include "ProtoC2C.h" +#include "Runtime.h" +#include "server.h" + +#define dDescpOffSet 0x1000 + + +#define dAddrSdRam_TypeList (dAddrSdRam_Commom) +#define dAddrSdRam_DescpGotList (dAddrSdRam_Commom + 256) +#define dAddrSdRam_DescpContent (dAddrSdRam_Commom + 1024) +#define dAddrSdRam_ExistTable (dAddrSdRam_Commom + 0x80000) + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "task.h" +} + +void TfNetworkReg::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left, Top, Width, CH, 0, 0, clWhite, clMaroon); + SText.Init (429, Top, 370, CH, 0, 0, clWhite, clMaroon); + + Content.Set(Left, Top+CH, Right, Bottom); + + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + + IsShowing = 0; + IsOnGoing = 0; + LoadingIndex = 0; + IsLoadingDescp = 0; + IsViewList = 0; + CtlIndex = 1; + Done = 0; + + DescpGo.IsStart = 0; +} + +void TfNetworkReg::sDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickShow(); + if(IsLoadingDescp){ + if(DescpGo.IsStart){ + ShowDescpState(); + } + }else{ + DrawListStatic(); + } + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + aPanel->Show(); + if(IsLoadingDescp){ + if(DescpGo.IsStart){ + ShowDescpState(); + } + }else{ + DrawListStatic(); + } + } +} + +void TfNetworkReg::ShowCaption() +{ + TMyString::sFromStr("系统设置->组网机器自动注册", Caption.Text); + Caption.Show(); +} + +void TfNetworkReg::SetPanelCaptionColor() +{ + if(IsViewList == 0){ + aPanel->Caption.Color = clDeepBlue; + aPanel->Caption.TextColor = clNearWhite; + }else{ + aPanel->Caption.Color = clMedGray; + aPanel->Caption.TextColor = clNearWhite; + } +} + +//______________________________________________________________________________________________________________________________ +void TfNetworkReg::InitPanel(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + ClearData(); + LoadData(); + + if(aPanel == nullptr)return; + + aPanel->Init(100,6,600,74,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("搜索组网机器", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->Btn[0].Init(60,4,220,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(340,4,220,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr(" 开始搜索 "); + aPanel->Btn[1].Caption.FromStr("加载区域机描述字"); + + aPanel->Btn[0].Visible = 1; + aPanel->Btn[1].Visible = 1; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 1; + + aPanel->Btn[0].SetCaptionLeftSpacing(6); + aPanel->Btn[1].SetCaptionLeftSpacing(6); + + if(MainCtl.fData.Split.NetworkMode != 1) + aPanel->Btn[1].Enable = 0; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + DrawList(); +} + +void TfNetworkReg::InitPanel4Going(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + ClearData(); + + if(aPanel == nullptr)return; + + aPanel->Init(100,6,600,74,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("正在搜索组网机器", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->SText[0].Init(32,4,110,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("正在搜索", aPanel->SText[0].Text); + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->SText[1].Init(2,4,30,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].TextClear(); + TMyString::sAddOn2Dg(1, aPanel->SText[1].Text); + + aPanel->SText[2].Init(446,4,102,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("机器数量", aPanel->SText[2].Text); + aPanel->SText[2].TextColor = clNearBlack; + + //aPanel->SText[3].Init(130,4,60,30,x,y,clNearBlack,clFrmFace); + //aPanel->SText[3].TextClear(); + //TMyString::sFromStr("搜索完成", aPanel->SText[3].Text); + + aPanel->Edit[0].Init(550,4,40,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[0].Str.FromStr("00"); + aPanel->Edit[0].Enable =0; + aPanel->Edit[0].Visible =1; + + RenderBackGround(); + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + DrawList(); +} + + +void TfNetworkReg::InitPanel4LoadDescp(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + ClearData(); + LoadData(); + + if(aPanel == nullptr)return; + + aPanel->Init(100,6,600,74,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("加载描述字", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->Btn[0].Init(60,4,160,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(340,4,160,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr(" 全部加载 "); + aPanel->Btn[1].Caption.FromStr("按区域机加载"); + + aPanel->Btn[0].Visible = 1; + aPanel->Btn[1].Visible = 1; + aPanel->Btn[0].Enable = 1; + aPanel->Btn[1].Enable = 1; + + aPanel->Btn[0].SetCaptionLeftSpacing(6); + aPanel->Btn[1].SetCaptionLeftSpacing(6); + + aPanel->Edit[0].Init(290,4,40,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[0].Enable = 1; + aPanel->Edit[0].Visible = 1; + if(ProtoC2C.SlaveCount >0){ + LoadingIndex = 0; + LoadingNum = ProtoC2C.SlaveList[LoadingIndex]; + aPanel->Edit[0].Str.FromUInt2Dg(LoadingNum); + }else{ + LoadingNum = 0xFF; + aPanel->Edit[0].Str.FromStr("xx"); + aPanel->Btn[1].Enable = 0; + } + RenderBackGround(); + aPanel->Show(); + CtlIndex = 2; + Check4SelectedInDescp(); + aPanel->ReDrawItems(); + +} + +//_____________________________________________________________________________________________________________________________ + +void TfNetworkReg::ClearData() +{ + int i,x; + unsigned int aAddr; + //Clear + for(i=0; i<64; i++){ + *(volatile unsigned char *)(dAddrSdRam_TypeList + i) = 0; + *(volatile unsigned char *)(dAddrSdRam_DescpGotList + i) = 0; + *(volatile unsigned char *)(dAddrSdRam_ExistTable +i) =0; + } + for(i=0; i<64; i++){ + aAddr = dAddrSdRam_DescpContent + i*32; + for(x=0; x<32; x++){ + *(volatile unsigned char *)(aAddr + x) = 0; + } + } + FoundIndex = 0; + aNewGot = 0; + SearchNumExist = 0; + + SearchingNum =1; + SearchingTick =0; + Done = 0; +} + +void TfNetworkReg::ShowSearchCompleted() +{ + int x, pNum; + unsigned int aAddr; + + IncMaster = 0; + for(x=0; xSText[0].Text); + }else{ + TMyString::sFromStr("请确保网络内只有一个集中机", aPanel->SText[0].Text); + } + }else{ + TMyString::sFromStr("搜索完成,只有集中机可操作保存", aPanel->SText[0].Text); + } + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->SText[1].TextClear(); + + aPanel->SText[0].Show(); + aPanel->SText[1].Show(); +} + +void TfNetworkReg::ShowDescpState() +{ + TextRender_string24 (18, 160 , clNearBlack, Color, "正在加载机器号: "); + if(DescpGo.P0 <= dPORT_MAX_COUNT) TextRender_string24 (18, 200 , clNearBlack, Color, "正在加载回路号:"); + else TextRender_string24 (18, 200 , clNearBlack, Color, "正在加载多线盘 "); + + TextRender_string24 (18, 240 , clNearBlack, "剩余处理数:"); + TextRender_string24 (18, 280 , clNearBlack, "未注册或空白数:"); + TextRender_string24 (18, 320 , clNearBlack, "已传输数:"); + TextRender_string24 (18, 360 , clNearBlack, "有效条目数:"); + + + TextDigitRender3_24 (210, 160 , clNearBlack, Color, DescpGo.pNum); + if(DescpGo.P0 <= dPORT_MAX_COUNT)TextDigitRender3_24 (210, 200 , clNearBlack, Color, DescpGo.P0); + else TextDigitRender3_24 (210, 200 , clNearBlack, Color, 0); + + TextDigitRender3_24 (210, 240 , clNearBlack, Color, DescpGo.RemainCount); + TextDigitRender3_24 (210, 280 , clNearBlack, Color, DescpGo.EmptyCount ); + if(DescpGo.P0 <= dPORT_MAX_COUNT)TextDigitRender3_24 (210, 320 , clNearBlack, Color, 250 - DescpGo.RemainCount); + else TextDigitRender3_24 (210, 320 , clNearBlack, Color, 160 - DescpGo.RemainCount); + TextDigitRender5Left24 (210, 360 , clNearBlack, Color, DescpGo.AvaEntry); + + if(DescpGo.Err){ + TextRender_string24 (18, 400 , clNearBlack, Color, "传输错误, 请退出 "); + }else + if(DescpGo.IsSaving){ + if(DescpGo.P0 <= dPORT_MAX_COUNT) TextRender_string24 (18, 400 , clNearBlack, Color, "正在保存回路,请等待 "); + else TextRender_string24 (18, 400 , clNearBlack, Color, "正在保存多线盘,请等待"); + }else + if(DescpGo.IsSaveOk){ + if(DescpGo.P0 <= dPORT_MAX_COUNT) TextRender_string24 (18, 400 , clNearBlack, Color, "回路保存完成,请等待 "); + else TextRender_string24 (18, 400 , clNearBlack, Color, "多线盘保存完成,请等待"); + }else + if(DescpGo.Completed){ + TextRender_string24 (18, 400 , clNearBlack, Color, "操作完成, 请退出 "); + } +} + + +void TfNetworkReg::ShowSaveOk() +{ + TMyString::sFromStr("保存成功", aPanel->SText[0].Text); + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->SText[1].TextClear(); + + aPanel->SText[0].Show(); + aPanel->SText[1].Show(); +} + +void TfNetworkReg::ShowSaveNotOk() +{ + TMyString::sFromStr("写入失败", aPanel->SText[0].Text); + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->SText[1].TextClear(); + + aPanel->SText[0].Show(); + aPanel->SText[1].Show(); +} + +void TfNetworkReg::LoadData() +{ + int i,x; + unsigned int aAddr; + //Load Here + Count = 0; + + //Clac + PageCount = Count / 10; + if(Count % 10){ + PageCount++; + } + PageIndex = 0; +} + +void TfNetworkReg::LoadData2Last() +{ + int i,x; + unsigned int aAddr; + //Load Here + Count = 0; + for(i=0; i=10)break; + } + + sInx = PageIndex * 10; + TVScrollBar::sDrawByPoint(767, 190, 786, 428, aClr, clGray, Count, 14, sInx); +} + +void TfNetworkReg::DrawListStatic() +{ + int x, y, z; + unsigned char aP0, aMcType; + unsigned int aClr, aAddr, wc; + unsigned int fInx,sInx, fCount, pNum; + + if(IsViewList)aClr = clBlue; else aClr = clDeepGray; + + RectFillRender (13, 159, 786, 188, aClr); + TextRender_string24 (18, 161 , clNearWhite, "机器列表"); + + RectFillRender(6,152,10,430,aClr); + RectFillRender(6,152,792,156,aClr); + RectFillRender(6,430,792,434,aClr); + RectFillRender(788,152,792,434,aClr); + + RectFillRender(11,189,787,429,clMoneyGreen); + + wc =0; + fInx = PageIndex * 10; + for(; fInx=10)break; + } + + sInx = PageIndex * 10; + TVScrollBar::sDrawByPoint(767, 190, 786, 428, aClr, clGray, Count, 14, sInx); +} + +void TfNetworkReg::ClearOutText() +{ + TMyString::sClear(aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TfNetworkReg::Check4Selected() +{ + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + if(IsOnGoing == 0){ + if(IsViewList ==0){ + if(CtlIndex == 0){ + aPanel->Btn[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Btn[1].Selected = 1; + } + } + } +} + +void TfNetworkReg::Check4SelectedInDescp() +{ + aPanel->Btn[0].Selected = 0; + aPanel->Edit[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + + if(CtlIndex == 0){ + aPanel->Btn[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Edit[0].Selected = 1; + } + if(CtlIndex == 2){ + aPanel->Btn[1].Selected = 1; + } +} + +void TfNetworkReg::SendNwList() +{ + //First Pkg + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Identification =0; + ProtoC2C.TxMsg.Data.Priority = 1; + + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 4; + ProtoC2C.TxMsg.Data.Data[0] =0; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + + ProtoC2C.oBufInsert(); + + //2th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =1; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[0]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[1]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[2]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[3]; + + ProtoC2C.oBufInsert(); + + //3th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =2; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[4]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[5]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[6]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[7]; + + ProtoC2C.oBufInsert(); + + //4th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =3; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[8]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[9]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[10]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[11]; + + ProtoC2C.oBufInsert(); + + //5th Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =4; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[12]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[13]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[14]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[15]; + + ProtoC2C.oBufInsert(); +} + + + +TGuiMsgReturn TfNetworkReg::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aCh; + unsigned int aAddr; + TDMix aFullPath; + + if(IsOnGoing){ + switch(aKey){ + case VK_EXECUTE: + if(Done){ + //Do Save Here + if( (MainCtl.fData.Split.NetworkMode == 1) && (IncMaster == 0) ){ + ProtoC2C.MasterNum = MainCtl.fData.Split.MyNum; + Count = GetCtlCount(); + ProtoC2C.SlaveCount = Count; + for(x=0; x0){ + CtlIndex--; + Check4SelectedInDescp(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + } + break; + case VK_RIGHT: + if(DescpGo.IsStart == 0){ + if(CtlIndex <2){ + CtlIndex++; + Check4SelectedInDescp(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + } + break; + case VK_UP: + if(DescpGo.IsStart == 0){ + if(ProtoC2C.SlaveCount == 0){ + LoadingNum = 0xFF; + }else{ + if(CtlIndex == 1){ + if(LoadingIndex < (ProtoC2C.SlaveCount-1)){ + LoadingIndex++; + LoadingNum = ProtoC2C.SlaveList[LoadingIndex]; + aPanel->Edit[0].Str.FromUInt2Dg(LoadingNum); + aPanel->Edit[0].Show(); + } + } + } + } + break; + case VK_DOWN: + if(DescpGo.IsStart == 0){ + if(ProtoC2C.SlaveCount == 0){ + LoadingNum = 0xFF; + }else{ + if(CtlIndex == 1){ + if(LoadingIndex >0){ + LoadingIndex--; + LoadingNum = ProtoC2C.SlaveList[LoadingIndex]; + aPanel->Edit[0].Str.FromUInt2Dg(LoadingNum); + aPanel->Edit[0].Show(); + } + } + } + } + break; + case VK_EXECUTE: + if(DescpGo.IsStart == 0){ + if(CtlIndex ==0){ + if(ProtoC2C.SlaveCount){ + ClearDescpGoData(); + DescpGo.BusyTick = 0; + DescpGo.IsBusy = 1; + RectFillRender(16,160,760,429,clMoneyGreen); + TextRender_string24 (18, 160 , clNearBlack, "等待区域机预加载"); + DescpGo.IsAll = 1; + DescpGo.IsStart = 1; + } + }else + if(CtlIndex ==2){ + if(ProtoC2C.SlaveCount){ + //Get pNum + if( (LoadingNum >0) && (LoadingNum <= dNETWORK_MACHINE_COUNT) ){ + ClearDescpGoData(); + DescpGo.BusyTick = 0; + DescpGo.IsBusy = 1; + RectFillRender(16,160,760,429,clMoneyGreen); + TextRender_string24 (18, 160 , clNearBlack, "等待区域机预加载"); + DescpGo.pNum = LoadingNum; + DescpGo.IsAll = 0; + DescpGo.IsStart = 1; + } + } + } + } + break; + case VK_RETURN: + IsLoadingDescp = 0; + DescpGo.IsStart = 0; + InitPanel(); + break; + } + }else{ + if(IsViewList){ + switch(aKey){ + case VK_UP: + if(PageIndex >0){ + PageIndex--; + DrawList(); + } + break; + case VK_DOWN: + if(PageIndex <(PageCount-1)){ + PageIndex++; + DrawList(); + } + break; + case VK_TAB: + IsViewList = 0; + DrawList(); + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case VK_LEFT: + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + aPanel->ReDrawItems(); + } + break; + case VK_RIGHT: + if(CtlIndex <1){ + CtlIndex++; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + IsViewList = 1; + DrawList(); + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + ClearData(); + IsOnGoing = 1; + IsViewList = 1; + InitPanel4Going(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex == 1){ + IsLoadingDescp = 1; + InitPanel4LoadDescp(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + } + + return aMsg; +} + +void TfNetworkReg::SendfNetMsg(unsigned char aSubCmd, unsigned char *data, int Len) +{ + +} + +void TfNetworkReg::PushfNetMsg(unsigned char aSubCmd, unsigned char *data, int Len) +{ + //In Ext CAN + //Cmd=251, D0=CTLBYTE, D1=SubCmd, D2=CtlNum, D3=(Type,Index,IndexCompleted), D4..7=Text + + //In Uart + //CmdC2C_RpyExist : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=Exist (0xFF) + //CmdC2C_RpyType : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=Type (Master or Slave, See Define) + //CmdC2C_RpyNameLen : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=NameLen (0x) + //CmdC2C_RpyNameContent : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=Index (Index X, D4=ThisPkgByteLen, D7..10=Char[0..3]) + //CmdC2C_RpyNameContent : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=Index (When Index = 0xFF, Completed) + int i,x, aLen; + unsigned int aAddr; + unsigned char ada; + unsigned char aP0; + + RecBlock = 1; + Path = data[1]; + ada = data[3]; + switch(aSubCmd){ + case CmdC2C_RpyExist: + break; + case CmdC2C_RpyType: + if( (ada == dNetworkTypeMaster) || (ada == dNetworkTypeSlave) ){ + aP0 = Path; + if( (aP0) && (aP0 <=dNETWORK_MACHINE_COUNT) ){ + SearchNumExist = 1; + aAddr = dAddrSdRam_TypeList + aP0; + *(volatile unsigned char *)(aAddr)= ada; + aAddr = dAddrSdRam_ExistTable + FoundIndex; + *(volatile unsigned char *)(aAddr)= aP0; + if(FoundIndex <=dNETWORK_MACHINE_COUNT) + FoundIndex++; + Count++; + } + } + break; + case CmdC2C_RpyNameLen: + + break; + case CmdC2C_RpyNameContent: + if(ada == 0xFF){ + aP0 = Path -1; + if(aP0 <64){ + aNewGot = 1; + aAddr = dAddrSdRam_DescpGotList + aP0; + *(volatile unsigned char *)(aAddr)= 1; + } + }else{ + if(ada < 8){ + x = ada * 4; + aLen = data[4]; + aP0 = Path -1; + if( (aLen < 5) && (aP0 < 64) ){ + aAddr = dAddrSdRam_DescpContent + aP0 * 32; + for(i=0; iEdit[0].Str.FromInt(Count); + aPanel->Edit[0].Show(); +} + +void TfNetworkReg::SendAskType(unsigned char aNum) +{ + //CmdC2C_RpyType : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=Type (Master or Slave, See Define) + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Identification =0; + ProtoC2C.TxMsg.Data.Priority = 1; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 4; + ProtoC2C.TxMsg.Data.Data[0] =0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_AskType; + ProtoC2C.TxMsg.Data.Data[3] = aNum; + + ProtoC2C.oBufInsert(); +} + +void TfNetworkReg::SendAskDescp(unsigned char aNum) +{ + //CmdC2C_RpyNameContent : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=Index (Index X, D4=ThisPkgByteLen, D7..10=Char[0..3]) + + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Identification =0; + ProtoC2C.TxMsg.Data.Priority = 1; + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 4; + ProtoC2C.TxMsg.Data.Data[0] =0; + ProtoC2C.TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_AskNameContent; + ProtoC2C.TxMsg.Data.Data[3] = aNum ; + + ProtoC2C.oBufInsert(); +} + +void TfNetworkReg::SavePortDescp(unsigned char aPNum, unsigned char aP0) +{ + unsigned int fAddr, sdAddr; + unsigned int i,m; + volatile unsigned int x, Sta, xy, inx, inx2; + unsigned int P0; + + if(aPNum == 0)return; + if(aPNum > dNETWORK_MACHINE_COUNT)return; + if(aP0 ==0)return; + if(aP0 >= dPORT_MAX_COUNT)return; + + P0 = aP0-1; + do{ + sDelayMs(5); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + + //Erase 2 * 4K Blocks + for(x=0; x<2; x++){ + do{ + sDelayMs(20); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + fAddr = NwDescpUsingFlashAddr[aPNum] + (SizeOf4K * (P0 * 2 + x) ); + nor_erase_sector_4k(NwDescpUsingChip[aPNum],fAddr); + do{ + sDelayMs(50); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + } + + for(x=0; x<32; x++){ + fAddr = NwDescpUsingFlashAddr[aPNum] + (SizeOf4K * (P0 * 2)) + (x * 256); + for(xy=0; xy<8; xy++){ + inx = x*8 + xy; + for(i=0; i<8;i++){ + inx2 = xy*8 + i; + ReadWriteData.D32[inx2] = PortDevDescp.Body[inx].D32[i]; + } + } + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + nor_write_page(NwDescpUsingChip[aPNum], fAddr, ReadWriteData.D8); + do{ + sDelayMs(5); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + } +} + +void TfNetworkReg::ReadPortDescp(unsigned char aPNum, unsigned char aP0) +{ + unsigned int fAddr, sdAddr; + unsigned int i,m; + volatile unsigned int x, Sta; + unsigned int Pr, P0; + + if(aPNum == 0)return; + if(aPNum > dNETWORK_MACHINE_COUNT)return; + if(aP0 ==0)return; + if(aP0 >=dPORT_MAX_COUNT)return; + + SysLoopTick = 0; + Pr = aPNum -1; + P0 = aP0-1; + do{ + sDelayMs(5); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + + for(x=0; x<32; x++){ + + SysLoopTick = 0; + fAddr = NwDescpUsingFlashAddr[aPNum] + (SizeOf4K * (P0 * 2)) + (x * 256); + sdAddr = dAddrSdRam_DescpNw + (Pr * dONE_CTRL_DESCP_BYTES) + (P0 * 8192) + (x * 256); + nor_read_page(NwDescpUsingChip[aPNum], fAddr, ReadWriteData.D8); + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + sdAddr = dAddrSdRam_DescpNw + (Pr * dONE_CTRL_DESCP_BYTES) + (P0 * 8192) + (x * 256); + for(i=0; i<64;i++){ + *(volatile unsigned int *)(sdAddr + i*4) = ReadWriteData.D32[i]; + } + sys_error_led_task(); + } +} + + +void TfNetworkReg::SaveDirectPadDescp(unsigned char aPNum) +{ + unsigned int fAddr, sdAddr; + unsigned int i,m; + volatile unsigned int x, Sta, xy, inx, inx2; + + if(aPNum == 0)return; + if(aPNum > dNETWORK_MACHINE_COUNT)return; + + do{ + sDelayMs(5); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + + //Erase 2 * 4K Blocks + for(x=0; x<2; x++){ + do{ + sDelayMs(20); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + fAddr = NwDescpUsingFlashAddr[aPNum] + 327680 + (x * 4096); + nor_erase_sector_4k(NwDescpUsingChip[aPNum],fAddr); + do{ + sDelayMs(50); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + } + + for(x=0; x<32; x++){ + fAddr = NwDescpUsingFlashAddr[aPNum] + 327680 + (x * 256); + for(xy=0; xy<8; xy++){ + inx = x*8 + xy; + for(i=0; i<8;i++){ + inx2 = xy*8 + i; + ReadWriteData.D32[inx2] = PortDevDescp.Body[inx].D32[i]; + } + } + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + nor_write_page(NwDescpUsingChip[aPNum], fAddr, ReadWriteData.D8); + do{ + sDelayMs(5); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + } +} + +void TfNetworkReg::ReadDirectPadDescp(unsigned char aPNum) +{ + unsigned int fAddr, sdAddr; + unsigned int i,m; + volatile unsigned int x, Sta; + unsigned int Pr; + + if(aPNum == 0)return; + if(aPNum > dNETWORK_MACHINE_COUNT)return; + + Pr = aPNum -1; + + SysLoopTick = 0; + do{ + sDelayMs(5); + Sta = nor_get_busy_state(NwDescpUsingChip[aPNum]); + }while(Sta); + + for(x=0; x<32; x++){ + SysLoopTick = 0; + fAddr = NwDescpUsingFlashAddr[aPNum] + 327680 + (x * 256); + sdAddr = dAddrSdRam_DescpNw + (Pr * dONE_CTRL_DESCP_BYTES) + 327680 + (x * 256); + nor_read_page(NwDescpUsingChip[aPNum], fAddr, ReadWriteData.D8); + + if(ReadWriteData.D32[0] == 0xFFFFFFFF)ReadWriteData.D32[0] = 0; + if(ReadWriteData.D32[8] == 0xFFFFFFFF)ReadWriteData.D32[8] = 0; + if(ReadWriteData.D32[16] == 0xFFFFFFFF)ReadWriteData.D32[16] = 0; + if(ReadWriteData.D32[24] == 0xFFFFFFFF)ReadWriteData.D32[24] = 0; + if(ReadWriteData.D32[32] == 0xFFFFFFFF)ReadWriteData.D32[32] = 0; + if(ReadWriteData.D32[40] == 0xFFFFFFFF)ReadWriteData.D32[40] = 0; + if(ReadWriteData.D32[48] == 0xFFFFFFFF)ReadWriteData.D32[48] = 0; + if(ReadWriteData.D32[56] == 0xFFFFFFFF)ReadWriteData.D32[56] = 0; + + for(i=0; i<64;i++){ + *(volatile unsigned int *)(sdAddr + i*4) = ReadWriteData.D32[i]; + } + sys_error_led_task(); + } +} + +void TfNetworkReg::Task1000Ms() +{ + if(IsShowing){ + if(IsOnGoing){ + PreventPermissionDown(); + PreventEventShow(); + if(Done){ + + }else{ + if(SearchingTick >(dNETWORK_MACHINE_COUNT +4)){ + SearchingTick = (dNETWORK_MACHINE_COUNT +4); + Count = GetCtlCount(); + DrawCount(); + LoadData2Last(); + DrawListStatic(); + //ShowSearchCompleted(); + Done = 1; + }else + if( (SearchingTick) && (SearchingTick <= dNETWORK_MACHINE_COUNT) ){ + SearchingNum = SearchingTick; + SendAskType(SearchingNum); + aPanel->SText[1].TextClear(); + TMyString::sAddOn2Dg(SearchingNum, aPanel->SText[1].Text); + aPanel->SText[1].Show(); + + Count = GetCtlCount(); + DrawCount(); + LoadData2Last(); + DrawListStatic(); + }else{ + Count = GetCtlCount(); + DrawCount(); + LoadData2Last(); + DrawListStatic(); + } + + SearchingTick++; + } + } + } +} + +void TfNetworkReg::PortExistGet(unsigned char aNum, unsigned char aP0, unsigned char aExist) +{ + if(DescpGo.pNum == aNum){ + if( (aP0) && (aP0 <= (dPORT_MAX_COUNT +1)) ){ + DescpGo.P0ExistTable[aP0] = aExist; + } + } +} + +void TfNetworkReg::DescpListGet(unsigned char aNum, unsigned char aP0, unsigned char Addr, unsigned char *Data) +{ + unsigned char Inx = Data[0]; + unsigned int Pst; + if( (aNum == DescpGo.pNum) && (aP0 == DescpGo.P0) ){ + if( Inx <8 ){ + DescpGo.P1GetTable[Addr] |= 1<< (Inx); + Pst = Inx * 4; + PortDevDescp.Body[Addr].D8[Pst++] = Data[4]; + PortDevDescp.Body[Addr].D8[Pst++] = Data[5]; + PortDevDescp.Body[Addr].D8[Pst++] = Data[6]; + PortDevDescp.Body[Addr].D8[Pst] = Data[7]; + }else + if( Inx == 0x33 ){ + DescpGo.P1GetTable[Addr] = 0x80; + } + } + DescpGo.BusyTick=0; +} + +void TfNetworkReg::ClearDescpContent() +{ + int i,x; + for(i=0; i<256; i++){ + for(x=0; x<8; x++){ + PortDevDescp.Body[i].D32[x] = 0; + } + } +} + +void TfNetworkReg::ClearDescpGoData() +{ + int x; + DescpGo.pNumInx =0; + DescpGo.NoUpdateTick =0; + DescpGo.WaitTimeOutTick = 0; + DescpGo.ExistPortAskRetryTimes = 0; + DescpGo.P0State =0; + DescpGo.P1State =0; + DescpGo.P0 = 1; + DescpGo.P1 = 1; + DescpGo.IsAll =0; + DescpGo.Tick =0; + DescpGo.Err =0; + DescpGo.IsSaving =0; + DescpGo.IsSaveOk =0; + DescpGo.Completed =0; + DescpGo.AvaEntry = 0; + for(x=0; x<42; x++)DescpGo.P0ExistTable[x] = 0; + for(x=0; x<255; x++)DescpGo.P1GetTable[x] = 0; + ClearDescpContent(); +} + + +void TfNetworkReg::DescpGoAll() +{ + int i, P1LostCount, aLt; + unsigned int aAddr; + PreventPermissionDown(); + PreventEventShow(); + if(DescpGo.pNumInx < ProtoC2C.SlaveCount){ + if(DescpGo.P0State == 0){ + //Send Ask is This Port Exist + DescpGo.pNum = ProtoC2C.SlaveList[DescpGo.pNumInx]; + ProtoC2C.PortExistAsk(DescpGo.pNum, DescpGo.P0); + DescpGo.WaitTimeOutTick = 0; + DescpGo.ExistPortAskRetryTimes = 0; + DescpGo.P0State = 1; + if(DescpGo.P0 <= dPORT_MAX_COUNT)DescpGo.RemainCount = 250; + else DescpGo.RemainCount = 160; + ShowDescpState(); + }else + if(DescpGo.P0State == 1){ + //Try Get Is Exist + if(DescpGo.P0ExistTable[DescpGo.P0] == 0xFF){ + for(i=0; i<255; i++)DescpGo.P1GetTable[i] = 0; + DescpGo.P0State = 2; + ProtoC2C.DescpOnePortAsk(DescpGo.pNum, DescpGo.P0); + if(DescpGo.P0 <= dPORT_MAX_COUNT)DescpGo.RemainCount = 250; + else DescpGo.RemainCount = 160; + DescpGo.Tick = 0; + }else + if(DescpGo.P0ExistTable[DescpGo.P0] == 0x10){ + if(DescpGo.P0 < (dPORT_MAX_COUNT +1)){ + DescpGo.P0++; + DescpGo.P0State = 0; + }else{ + DescpGo.pNumInx++; + DescpGo.P0 =1; + DescpGo.P0State = 0; + } + }else{ + DescpGo.WaitTimeOutTick++; + if(DescpGo.WaitTimeOutTick > 200){ + DescpGo.WaitTimeOutTick=0; + DescpGo.ExistPortAskRetryTimes++; + if(DescpGo.ExistPortAskRetryTimes >3){ + if(DescpGo.P0 < (dPORT_MAX_COUNT+1)){ + DescpGo.P0++; + __nop(); + DescpGo.P0State = 0; + }else{ + DescpGo.pNumInx++; + DescpGo.P0 =1; + DescpGo.P0State = 0; + } + }else{ + ProtoC2C.PortExistAsk(DescpGo.pNum, DescpGo.P0); + DescpGo.WaitTimeOutTick = 0; + } + } + } + }else + if(DescpGo.P0State == 2){ + DescpGo.Tick++; + DescpGo.NoUpdateTick++; + if(DescpGo.Tick < 5000){ + if( (DescpGo.Tick % 100) == 99){ + //check Ok + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + P1LostCount = 0; + DescpGo.EmptyCount = 0; + if(DescpGo.P0 <= dPORT_MAX_COUNT){ + for(i=1; i<251; i++){ + if(DescpGo.P1GetTable[i] == 0){ + P1LostCount++; + } + if(DescpGo.P1GetTable[i] == 0x80){ + DescpGo.EmptyCount++; + } + } + }else{ + for(i=1; i<161; i++){ + if(DescpGo.P1GetTable[i] == 0){ + P1LostCount++; + } + if(DescpGo.P1GetTable[i] == 0x80){ + DescpGo.EmptyCount++; + } + } + } + + if(P1LostCount == 0){ + if(DescpGo.P0 <= dPORT_MAX_COUNT){ + SavePortDescp(DescpGo.pNum, DescpGo.P0); + ReadPortDescp(DescpGo.pNum, DescpGo.P0); + DescpGo.AvaEntry += (250 - DescpGo.EmptyCount); + DescpGo.RemainCount = 0; + }else{ + SaveDirectPadDescp(DescpGo.pNum); + ReadDirectPadDescp(DescpGo.pNum); + DescpGo.AvaEntry += (160 - DescpGo.EmptyCount); + DescpGo.RemainCount = 0; + } + + if(DescpGo.P0 < (dPORT_MAX_COUNT +1) ){ + DescpGo.P0++; + DescpGo.P0State = 0; + ClearDescpContent(); + }else{ + DescpGo.pNumInx++; + DescpGo.P0 = 1; + DescpGo.P0State = 0; + ClearDescpContent(); + } + DescpGo.IsSaveOk = 1; + ShowDescpState(); + return; + } + if(DescpGo.RemainCount != P1LostCount){ + DescpGo.NoUpdateTick = 0; + DescpGo.RemainCount = P1LostCount; + } + if(DescpGo.NoUpdateTick >200){ + DescpGo.NoUpdateTick = 0; + if(P1LostCount < 13){ + //Retry Lost P1 + aLt = 0; + for(i=0; i<12; i++)DescpGo.RetryP1[i] =0; + if(DescpGo.P0 <= dPORT_MAX_COUNT){ + for(i=1; i<251; i++){ + if( (DescpGo.P1GetTable[i] != 0xFF) && (DescpGo.P1GetTable[i] != 0x80) ){ + DescpGo.RetryP1[aLt] = i; + aLt++; + if(aLt >= 12)break; + } + } + }else{ + for(i=1; i<161; i++){ + if( (DescpGo.P1GetTable[i] != 0xFF) && (DescpGo.P1GetTable[i] != 0x80) ){ + DescpGo.RetryP1[aLt] = i; + aLt++; + if(aLt >= 12)break; + } + } + } + if(DescpGo.RetryP1[0]) + ProtoC2C.DescpListAsk(DescpGo.pNum, DescpGo.P0, 1, &DescpGo.RetryP1[0]); + if(DescpGo.RetryP1[4]) + ProtoC2C.DescpListAsk(DescpGo.pNum, DescpGo.P0, 2, &DescpGo.RetryP1[4]); + if(DescpGo.RetryP1[8]) + ProtoC2C.DescpListAsk(DescpGo.pNum, DescpGo.P0, 3, &DescpGo.RetryP1[8]); + }else{ + //It's Too Many Lost , Show Err, exit + DescpGo.Err =1; + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + DescpGo.IsStart = 0; + } + } + ShowDescpState(); + } + }else{ + //Show Err, exit + DescpGo.Err =1; + DescpGo.IsStart = 0; + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + ShowDescpState(); + } + } + }else{ + //Show Completed + DescpGo.IsStart = 0; + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + DescpGo.Completed = 1; + ShowDescpState(); + } +} + + +void TfNetworkReg::DescpGoOneCtl() +{ + int i, P1LostCount, aLt; + unsigned int aAddr; + int Cmpl; + + PreventPermissionDown(); + PreventEventShow(); + Cmpl = 0; + + if(DescpGo.P0State == 0){ + //Send Ask is This Port Exist + ProtoC2C.PortExistAsk(DescpGo.pNum, DescpGo.P0); + DescpGo.WaitTimeOutTick = 0; + DescpGo.ExistPortAskRetryTimes = 0; + DescpGo.P0State = 1; + ShowDescpState(); + }else + if(DescpGo.P0State == 1){ + //Try Get Is Exist + if(DescpGo.P0ExistTable[DescpGo.P0] == 0xFF){ + for(i=0; i<255; i++)DescpGo.P1GetTable[i] = 0; + DescpGo.P0State = 2; + ProtoC2C.DescpOnePortAsk(DescpGo.pNum, DescpGo.P0); + if(DescpGo.P0 <= dPORT_MAX_COUNT)DescpGo.RemainCount = 250; + else DescpGo.RemainCount = 160; + DescpGo.Tick = 0; + }else + if(DescpGo.P0ExistTable[DescpGo.P0] == 0x10){ + if(DescpGo.P0 < (dPORT_MAX_COUNT +1)){ + DescpGo.P0++; + DescpGo.P0State = 0; + }else{ + DescpGo.pNumInx++; + DescpGo.P0 =1; + DescpGo.P0State = 0; + } + }else{ + DescpGo.WaitTimeOutTick++; + if(DescpGo.WaitTimeOutTick > 200){ + DescpGo.WaitTimeOutTick=0; + DescpGo.ExistPortAskRetryTimes++; + if(DescpGo.ExistPortAskRetryTimes >3){ + if(DescpGo.P0 < (dPORT_MAX_COUNT+1)){ + DescpGo.P0++; + __nop(); + DescpGo.P0State = 0; + }else{ + DescpGo.pNumInx++; + DescpGo.P0 =1; + DescpGo.P0State = 0; + } + }else{ + ProtoC2C.PortExistAsk(DescpGo.pNum, DescpGo.P0); + DescpGo.WaitTimeOutTick = 0; + } + } + } + }else + if(DescpGo.P0State == 2){ + DescpGo.Tick++; + DescpGo.NoUpdateTick++; + if(DescpGo.Tick < 5000){ + if( (DescpGo.Tick % 100) == 99){ + //check Ok + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + P1LostCount = 0; + DescpGo.EmptyCount = 0; + if(DescpGo.P0 <= dPORT_MAX_COUNT){ + for(i=1; i<251; i++){ + if(DescpGo.P1GetTable[i] == 0){ + P1LostCount++; + } + if(DescpGo.P1GetTable[i] == 0x80){ + DescpGo.EmptyCount++; + } + } + }else{ + for(i=1; i<161; i++){ + if(DescpGo.P1GetTable[i] == 0){ + P1LostCount++; + } + if(DescpGo.P1GetTable[i] == 0x80){ + DescpGo.EmptyCount++; + } + } + } + + if(P1LostCount == 0){ + if(DescpGo.P0 <= dPORT_MAX_COUNT){ + SavePortDescp(DescpGo.pNum, DescpGo.P0); + ReadPortDescp(DescpGo.pNum, DescpGo.P0); + DescpGo.AvaEntry += (250 - DescpGo.EmptyCount); + DescpGo.RemainCount = 0; + }else{ + SaveDirectPadDescp(DescpGo.pNum); + ReadDirectPadDescp(DescpGo.pNum); + DescpGo.AvaEntry += (160 - DescpGo.EmptyCount); + DescpGo.RemainCount = 0; + } + + if(DescpGo.P0 < (dPORT_MAX_COUNT +1) ){ + DescpGo.P0++; + DescpGo.P0State = 0; + ClearDescpContent(); + }else{ + Cmpl = 1; + } + DescpGo.IsSaveOk = 1; + ShowDescpState(); + if(Cmpl){ + DescpGo.IsStart = 0; + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + DescpGo.Completed = 1; + ShowDescpState(); + } + return; + } + if(DescpGo.RemainCount != P1LostCount){ + DescpGo.NoUpdateTick = 0; + DescpGo.RemainCount = P1LostCount; + } + if(DescpGo.NoUpdateTick >200){ + DescpGo.NoUpdateTick = 0; + if(P1LostCount < 13){ + //Retry Lost P1 + aLt = 0; + for(i=0; i<12; i++)DescpGo.RetryP1[i] =0; + if(DescpGo.P0 <= dPORT_MAX_COUNT){ + for(i=1; i<251; i++){ + if( (DescpGo.P1GetTable[i] != 0xFF) && (DescpGo.P1GetTable[i] != 0x80) ){ + DescpGo.RetryP1[aLt] = i; + aLt++; + if(aLt >= 12)break; + } + } + }else{ + for(i=1; i<161; i++){ + if( (DescpGo.P1GetTable[i] != 0xFF) && (DescpGo.P1GetTable[i] != 0x80) ){ + DescpGo.RetryP1[aLt] = i; + aLt++; + if(aLt >= 12)break; + } + } + } + if(DescpGo.RetryP1[0]) + ProtoC2C.DescpListAsk(DescpGo.pNum, DescpGo.P0, 1, &DescpGo.RetryP1[0]); + if(DescpGo.RetryP1[4]) + ProtoC2C.DescpListAsk(DescpGo.pNum, DescpGo.P0, 2, &DescpGo.RetryP1[4]); + if(DescpGo.RetryP1[8]) + ProtoC2C.DescpListAsk(DescpGo.pNum, DescpGo.P0, 3, &DescpGo.RetryP1[8]); + }else{ + //It's Too Many Lost , Show Err, exit + DescpGo.Err =1; + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + DescpGo.IsStart = 0; + } + } + ShowDescpState(); + } + }else{ + //Show Err, exit + DescpGo.Err =1; + DescpGo.IsStart = 0; + DescpGo.IsSaveOk = 0; + DescpGo.IsSaving = 0; + ShowDescpState(); + } + } +} + + +void TfNetworkReg::Task10Ms() +{ + if(IsShowing){ + if(DescpGo.IsStart){ + if(DescpGo.IsAll){ + if(DescpGo.IsBusy){ + DescpGo.BusyTick++; + if(DescpGo.BusyTick > 500){ + DescpGo.IsBusy = 0; + } + }else{ + DescpGoAll(); + } + }else{ + if(DescpGo.IsBusy){ + DescpGo.BusyTick++; + if(DescpGo.BusyTick > 500){ + DescpGo.IsBusy = 0; + } + }else{ + DescpGoOneCtl(); + } + } + } + } +} + +void TfNetworkReg::sRecoverSetDefaultNetworkDescp() +{ + unsigned int fAddr; + unsigned int i,m; + volatile unsigned int x, Sta; + + unsigned char tPNum, tPn; + + //Erase 2 * 4K Blocks + for(tPNum =1; tPNum 0) && (ProtoC2C.MasterNum <=dNETWORK_MACHINE_COUNT) ) + TextDigitRender2Right24(x ,332,clNearBlack, Color, ProtoC2C.MasterNum); + } +} + + +void TfNetworkRegManual::ShowTip() +{ + if(MainCtl.fData.Split.NetworkMode == 1){ + TextRender_string24(20,240,clNearBlack, Color, "本机为集中机 "); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TextRender_string24(20,240,clNearBlack, Color, "本机为区域机 "); + }else + if(MainCtl.fData.Split.NetworkMode == 0){ + TextRender_string24(20,240,clNearBlack, Color, "本机为单机 "); + }else{ + TextRender_string24(20,240,clNearBlack, Color, "本机网络设定不正确, 请重新设定"); + } + + TextRender_string24(20,370,clNearBlack,"1.设置键向左选择,查询键向右选择,上下键在添加栏与删除栏之间切换"); + TextRender_string24(20,406,clNearBlack,"2.机器号范围: 1~32"); +} + +void TfNetworkRegManual::ShowActionResult(int aSta) +{ + Sta = aSta; + ShowActionResult(); +} + + +void TfNetworkRegManual::SendNwList() +{ + //First Pkg + ProtoC2C.TxMsg.Data.CarryByte =255; + ProtoC2C.TxMsg.Data.Routing =0; + ProtoC2C.TxMsg.Data.Identification =0; + ProtoC2C.TxMsg.Data.Priority = 1; + + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 4; + ProtoC2C.TxMsg.Data.Data[0] =0; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + + ProtoC2C.oBufInsert(); + + //First Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =1; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[0]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[1]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[2]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[3]; + + ProtoC2C.oBufInsert(); + + //First Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =2; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[4]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[5]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[6]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[7]; + + ProtoC2C.oBufInsert(); + + //First Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =3; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[8]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[9]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[10]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[11]; + + ProtoC2C.oBufInsert(); + + //First Pkg + ProtoC2C.TxMsg.Data.Cmd = dNetworkCmd; + ProtoC2C.TxMsg.Data.Len = 8; + ProtoC2C.TxMsg.Data.Data[0] =4; + ProtoC2C.TxMsg.Data.Data[1] = ProtoC2C.MasterNum; + ProtoC2C.TxMsg.Data.Data[2] = CmdC2C_SaveData; + ProtoC2C.TxMsg.Data.Data[3] = ProtoC2C.SlaveCount; + ProtoC2C.TxMsg.Data.Data[4] = ProtoC2C.SlaveList[12]; + ProtoC2C.TxMsg.Data.Data[5] = ProtoC2C.SlaveList[13]; + ProtoC2C.TxMsg.Data.Data[6] = ProtoC2C.SlaveList[14]; + ProtoC2C.TxMsg.Data.Data[7] = ProtoC2C.SlaveList[15]; + + ProtoC2C.oBufInsert(); +} + + +void TfNetworkRegManual::TryAddRemoveSlave(int IsAdd) +{ + int iVal,i, Found,x, IsWriteOK; + if(IsAdd){ + iVal = aPanel->Edit[0].Str.ToInteger(); + if( (iVal >0) && (iVal dNETWORK_MACHINE_COUNT){ + ShowActionResult(-5); + return; + } + for(i=0; iEdit[1].Str.ToInteger(); + if( (iVal >0) && (iVal <= dNETWORK_MACHINE_COUNT) ){ + ProtoC2C.MasterNum = MainCtl.fData.Split.MyNum; + Found = 0; + if(ProtoC2C.SlaveCount >dNETWORK_MACHINE_COUNT)ProtoC2C.SlaveCount =dNETWORK_MACHINE_COUNT; + for(i=0; iEdit[0].Str.ToInteger(); + if( (iVal >0) && (iVal Show(); + //DrawList(); + JustShowSlaveListNum(); + }else + if(Prm == 1){ + RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + ShowTip(); + + aPanel->Show(); + //DrawList(); + JustShowSlaveListNum(); + } +} + +void TfNetworkRegManual::ShowCaption() +{ + TMyString::sFromStr("系统设置->组网机器手动注册", Caption.Text); + Caption.Show(); +} + +void TfNetworkRegManual::SetPanelCaptionColor() +{ + if(IsViewList == 0){ + aPanel->Caption.Color = clDeepBlue; + aPanel->Caption.TextColor = clNearWhite; + }else{ + aPanel->Caption.Color = clMedGray; + aPanel->Caption.TextColor = clNearWhite; + } +} + +//______________________________________________________________________________________________________________________________ +void TfNetworkRegManual::InitPanel4Master(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + //ClearData(); + //LoadData(); + + if(aPanel == nullptr)return; + + aPanel->Init(10,3,772,123,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("添加或删除组网机器", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->SText[0].Init(4,6,80,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("机器号", aPanel->SText[0].Text); + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->SText[1].Init(4,50,80,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("机器号", aPanel->SText[1].Text); + aPanel->SText[1].TextColor = clNearBlack; + + aPanel->Edit[0].Init(86,6,40,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[1].Init(130,6,400,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[2].Init(86,50,40,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[3].Init(130,50,400,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[0].Str.FromStr("00"); + aPanel->Edit[1].Str.FromStr("要添加的机器号"); + aPanel->Edit[2].Str.FromStr("00"); + aPanel->Edit[3].Str.FromStr("要删除的机器号"); + aPanel->Edit[0].Enable =1; + aPanel->Edit[0].Visible =1; + aPanel->Edit[1].Enable =0; + aPanel->Edit[1].Visible =1; + aPanel->Edit[2].Enable =1; + aPanel->Edit[2].Visible =1; + aPanel->Edit[3].Enable =0; + aPanel->Edit[3].Visible =1; + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[1].SetMaxLen(32); + aPanel->Edit[2].SetMaxLen(2); + aPanel->Edit[3].SetMaxLen(32); + + aPanel->Btn[0].Init(536,6,160,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(704,6,60,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[2].Init(704,50,60,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("远程获取描述"); + aPanel->Btn[1].Caption.FromStr("添加"); + aPanel->Btn[2].Caption.FromStr("删除"); + + aPanel->Btn[0].SetCaptionLeftSpacing(2); + aPanel->Btn[1].SetCaptionLeftSpacing(2); + aPanel->Btn[2].SetCaptionLeftSpacing(2); + + aPanel->Btn[0].Visible = 1; + aPanel->Btn[1].Visible = 1; + aPanel->Btn[2].Visible = 1; + aPanel->Btn[0].Enable = 0; + aPanel->Btn[1].Enable = 1; + aPanel->Btn[2].Enable = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + RectFillRender(20,149,779,150,clGray); + + //DrawList(); + + JustShowSlaveListNum(); +} + +void TfNetworkRegManual::InitPanel4Slave(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + //ClearData(); + //LoadData(); + + if(aPanel == nullptr)return; + + aPanel->Init(10,3,772,123,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("设定要连接的集中机号", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->SText[0].Init(4,6,80,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("机器号", aPanel->SText[0].Text); + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->Edit[0].Init(86,6,40,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[1].Init(130,6,400,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[2].Init(86,50,40,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[3].Init(130,50,400,32,x,y,clNearBlack,clFrmFace); + aPanel->Edit[0].Str.FromStr("00"); + aPanel->Edit[1].Str.FromStr("集中机号"); + aPanel->Edit[2].Str.FromStr(" "); + aPanel->Edit[3].Str.FromStr(" "); + aPanel->Edit[0].Enable =1; + aPanel->Edit[0].Visible =1; + aPanel->Edit[1].Enable =0; + aPanel->Edit[1].Visible =1; + aPanel->Edit[2].Enable =1; + aPanel->Edit[2].Visible =0; + aPanel->Edit[3].Enable =0; + aPanel->Edit[3].Visible =0; + aPanel->Edit[0].SetMaxLen(2); + aPanel->Edit[1].SetMaxLen(32); + aPanel->Edit[2].SetMaxLen(2); + aPanel->Edit[3].SetMaxLen(32); + + aPanel->Btn[0].Init(536,6,160,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[1].Init(540,6,216,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[2].Init(540,50,216,30,x,y,clNearBlack,clFrmFace); + aPanel->Btn[0].Caption.FromStr("远程获取描述"); + aPanel->Btn[1].Caption.FromStr(" 集中机连接 "); + aPanel->Btn[2].Caption.FromStr(" 删除集中机连接"); + + aPanel->Btn[0].SetCaptionLeftSpacing(2); + aPanel->Btn[1].SetCaptionLeftSpacing(2); + aPanel->Btn[2].SetCaptionLeftSpacing(2); + + aPanel->Btn[0].Visible = 0; + aPanel->Btn[1].Visible = 1; + aPanel->Btn[2].Visible = 1; + aPanel->Btn[0].Enable = 0; + aPanel->Btn[1].Enable = 1; + aPanel->Btn[2].Enable = 1; + + aPanel->Show(); + Check4Selected(); + aPanel->ReDrawItems(); + + RectFillRender(20,149,779,150,clGray); + + //DrawList(); + + JustShowSlaveListNum(); +} + + +void TfNetworkRegManual::InitPanel4None(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + //ClearData(); + //LoadData(); + + if(aPanel == nullptr)return; + + aPanel->Init(10,3,772,123,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("本机为单机,请返回", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->SText[0].Init(4,6,80,30,x,y,clNearBlack,clFrmFace); + TMyString::sFromStr("请返回", aPanel->SText[0].Text); + aPanel->SText[0].TextColor = clNearBlack; + + aPanel->Show(); + + RectFillRender(20,149,779,150,clGray); +} + +void TfNetworkRegManual::InitPanel(void) +{ + if(MainCtl.fData.Split.NetworkMode == 1){ + InitPanel4Master(); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + InitPanel4Slave(); + }else{ + InitPanel4None(); + } +} + +//_____________________________________________________________________________________________________________________________ + +void TfNetworkRegManual::ClearData() +{ + int i,x; + unsigned int aAddr; + //Clear + for(i=0; i<64; i++){ + aAddr = dAddrSdRam_Register + i*4; + *(volatile unsigned int *)(aAddr) = 0; + } + for(i=0; i<64; i++){ + for(x=0; x<64; x++){ + aAddr = dAddrSdRam_Register + dDescpOffSet + i*64 + x; + *(volatile unsigned int *)(aAddr) = 0; + } + } +} + +void TfNetworkRegManual::LoadData() +{ + int i,x; + unsigned int aAddr; + //Load Here + Count = 0; + + //Clac + PageCount = Count / 10; + if(Count % 10){ + PageCount++; + } + PageIndex = 0; +} + +void TfNetworkRegManual::DrawList() +{ + int i, x, y, z; + unsigned char aP0; + unsigned int aClr, aAddr, wc; + + if(IsViewList)aClr = clBlue; else aClr = clDeepGray; + + RectFillRender (13, 239, 786, 268, aClr); + TextRender_string24 (18, 241 , clNearWhite, "机器列表 数量:"); + TextDigitRender2Right24 (200,241 , clNearWhite, Count); + + RectFillRender(6,232,10,430,aClr); + RectFillRender(6,232,792,236,aClr); + RectFillRender(6,430,792,434,aClr); + RectFillRender(788,232,792,434,aClr); + + RectFillRender(11,269,787,429,clMoneyGreen); + + i = PageIndex * 10; + wc =0; + for(; i= 10)break; + } + i = PageIndex * 10; + TVScrollBar::sDrawByPoint(767, 270, 786, 428, aClr, clGray, Count, 14, i); +} + +void TfNetworkRegManual::ClearOutText() +{ + TMyString::sClear(aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TfNetworkRegManual::Task1000Ms() +{ + if(IsShowing){ + + } +} + +void TfNetworkRegManual::Check4Selected() +{ + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[2].Selected = 0; + + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + + /*if(IsViewList ==0){ + if(CtlIndex == 0){ + aPanel->Edit[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Edit[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Btn[0].Selected = 1; + }else + if(CtlIndex == 3){ + aPanel->Btn[1].Selected = 1; + }else + if(CtlIndex == 4){ + aPanel->Edit[2].Selected = 1; + }else + if(CtlIndex == 5){ + aPanel->Btn[2].Selected = 1; + } + }*/ + + if(IsViewList ==0){ + if(CtlIndex == 0){ + aPanel->Edit[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Btn[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Edit[2].Selected = 1; + }else + if(CtlIndex == 3){ + aPanel->Btn[2].Selected = 1; + } + } +} + +void TfNetworkRegManual::Check4Selected4Slave() +{ + aPanel->Btn[0].Selected = 0; + aPanel->Btn[1].Selected = 0; + aPanel->Btn[2].Selected = 0; + + aPanel->Edit[0].Selected = 0; + aPanel->Edit[1].Selected = 0; + aPanel->Edit[2].Selected = 0; + + /*if(IsViewList ==0){ + if(CtlIndex == 0){ + aPanel->Edit[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Edit[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Btn[0].Selected = 1; + }else + if(CtlIndex == 3){ + aPanel->Btn[1].Selected = 1; + }else + if(CtlIndex == 4){ + aPanel->Edit[2].Selected = 1; + }else + if(CtlIndex == 5){ + aPanel->Btn[2].Selected = 1; + } + }*/ + + if(IsViewList ==0){ + if(CtlIndex == 0){ + aPanel->Edit[0].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Btn[1].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Btn[2].Selected = 1; + } + } +} + +TGuiMsgReturn TfNetworkRegManual::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aLen; + TDMix aFullPath; + + //if(IsViewList){ + if(0){ + switch(aKey){ + case VK_UP: + if(PageIndex >0){ + PageIndex--; + DrawList(); + } + break; + case VK_DOWN: + if(PageIndex <(PageCount-1)){ + PageIndex++; + DrawList(); + } + break; + case VK_TAB: + IsViewList = 0; + DrawList(); + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + if(MainCtl.fData.Split.NetworkMode == 1){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + if(CtlIndex == 0){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + }else + if(CtlIndex == 2){ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + } + break; + case VK_LEFT: + if(CtlIndex == 0){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + }else + if(CtlIndex == 1){ + //if(aPanel->Edit[1].Pst <0){ + if(1){ + CtlIndex = 0; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 2){ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + //CtlIndex--; + //Check4Selected(); + //SetPanelCaptionColor(); + //aPanel->ReDrawItems(); + }else + if(CtlIndex == 3){ + CtlIndex--; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex == 4){ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + }else + if(CtlIndex == 5){ + CtlIndex--; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_RIGHT: + if(CtlIndex == 0){ + if(aPanel->Edit[0].Pst >0){ + CtlIndex++; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + } + }else + if(CtlIndex == 1){ + //aLen = aPanel->Edit[1].Str.GetEndPst(); + //if(aPanel->Edit[1].Pst >=aLen){ + // CtlIndex++; + // Check4Selected(); + // SetPanelCaptionColor(); + // aPanel->ReDrawItems(); + //}else{ + // aPanel->Edit[1].KeyIn(aKey); + // aPanel->Edit[1].Show(); + //} + }else + if(CtlIndex == 2){ + if(aPanel->Edit[2].Pst >0){ + CtlIndex++; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + } + + //CtlIndex++; + //Check4Selected(); + //SetPanelCaptionColor(); + //aPanel->ReDrawItems(); + }else + if(CtlIndex == 3){ + + }else + if(CtlIndex == 4){ + if(aPanel->Edit[2].Pst >0){ + CtlIndex++; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + } + } + break; + case VK_UP: + if(CtlIndex == 2){ + CtlIndex = 0; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex == 3){ + CtlIndex = 1; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <1){ + CtlIndex = 2; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex <2){ + CtlIndex = 3; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case dfKEY_SETUP: + if(CtlIndex <4){ + if(CtlIndex >0){ + CtlIndex--; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + }else + if(CtlIndex == 5){ + CtlIndex = 4; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case dfKEY_QUERY: + /*if(CtlIndex <4){ + if(CtlIndex <3){ + CtlIndex++; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + }else + if(CtlIndex == 4){ + CtlIndex = 5; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }*/ + break; + case VK_TAB: + //IsViewList = 1; + //DrawList(); + //Check4Selected(); + //SetPanelCaptionColor(); + //aPanel->ReDrawItems(); + break; + case VK_EXECUTE: + if(CtlIndex == 1){ + TryAddRemoveSlave(1); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + JustShowSlaveListNum(); + }else + if(CtlIndex == 3){ + TryAddRemoveSlave(0); + JustShowSlaveListNum(); + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + if(CtlIndex == 0){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + } + break; + case VK_LEFT: + if(CtlIndex == 0){ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + }else + if(CtlIndex == 1){ + //if(aPanel->Edit[1].Pst <0){ + if(1){ + CtlIndex = 0; + Check4Selected4Slave(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[1].KeyIn(aKey); + aPanel->Edit[1].Show(); + } + }else + if(CtlIndex == 2){ + CtlIndex = 0; + Check4Selected4Slave(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_RIGHT: + if(CtlIndex == 0){ + if(aPanel->Edit[0].Pst >0){ + CtlIndex++; + Check4Selected4Slave(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[0].KeyIn(aKey); + aPanel->Edit[0].Show(); + } + } + break; + case VK_UP: + if(CtlIndex == 2){ + CtlIndex = 1; + Check4Selected4Slave(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex <2){ + CtlIndex = 2; + Check4Selected4Slave(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case dfKEY_SETUP: + break; + case dfKEY_QUERY: + break; + case VK_TAB: + break; + case VK_EXECUTE: + if(CtlIndex == 1){ + TryAddRemoveMaster(1); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex == 2){ + TryAddRemoveMaster(0); + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + } + return aMsg; +} + +void TfNetworkRegManual::SendfNetMsg(int Len) +{ + +} + +void TfNetworkRegManual::PushfNetMsg(unsigned char aCubCmd, unsigned char *data, int Len) +{ + +} + +int TfNetworkRegManual::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} + diff --git a/MyCode/Gui/fNetworkRegManual.h b/MyCode/Gui/fNetworkRegManual.h new file mode 100644 index 0000000..2703927 --- /dev/null +++ b/MyCode/Gui/fNetworkRegManual.h @@ -0,0 +1,100 @@ +#ifndef FNETWORKREGMANUAL_H_ +#define FNETWORKREGMANUAL_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TfNetworkRegManual{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + u32 Color; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + TMyString Str; + + int IsShowing; + unsigned char IsViewList; + unsigned char CtlIndex; + + unsigned char Count; + unsigned char PageIndex; + unsigned char PageCount; + unsigned char Done; + + char dText[64]; + unsigned char Data[12]; + unsigned char RecData[12]; + unsigned char pNumList[24]; + + int Sta; + + unsigned char aMasterNum; + unsigned char aSlaveCount; + unsigned char aNumList[16]; + + + public: + TfNetworkRegManual(){}; + TfNetworkRegManual(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void ClearOutText(); + void JustShowSlaveListNum(); + void ShowTip(); + void ShowActionResult(); + void ShowActionResult(int aSta); + + void Show(void); + void ShowCaption(); + void ReDraw(void); + void FullRedraw(int Prm); + void DrawCaption2(void); + void DrawList(); + void SetPanelCaptionColor(); + void ClearData(); + void LoadData(); + void TryAddRemoveSlave(int IsAdd); + void TryAddRemoveMaster(int IsAdd); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel4Master(void); + void InitPanel4Slave(void); + void InitPanel4None(); + void InitPanel(void); + void Check4Selected(void); + void Check4Selected4Slave(); + + void Task1000Ms(); + + void SendNwList(); + void SendfNetMsg(int Len); + void PushfNetMsg(unsigned char aCubCmd, unsigned char *data, int Len); + + int ExtRequst(unsigned char Prm); + +}; + + + +#endif + diff --git a/MyCode/Gui/fNetworkRegRemove.cpp b/MyCode/Gui/fNetworkRegRemove.cpp new file mode 100644 index 0000000..ac6565f --- /dev/null +++ b/MyCode/Gui/fNetworkRegRemove.cpp @@ -0,0 +1,543 @@ +#include "fNetworkRegRemove.h" +#include "runtime.h" + +#define dDescpOffSet 0x1000 + +void TfNetworkRegRemove::Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor) +{ + #define CH 30 //Caption Height + unsigned short Left,Right, Top, Bottom, Width, Height, i; + Bound.SetBySize(OwnerX + x1, OwnerY + y1, aW, aH); + Left = Bound.Left +3; + Top = Bound.Top+3; + Width = aW - 7; + Height = aH - 7; + Right = Bound.Right -4; + Bottom = Bound.Bottom -4; + Caption.Init(Left, Top, Width, CH, 0, 0, clWhite, clMaroon); + SText.Init (429, Top, 370, CH, 0, 0, clWhite, clMaroon); + + Content.Set(Left, Top+CH, Right, Bottom); + + Color = aColor; + #undef CH + + Caption.Border.Color = clGray; + + IsShowing = 0; + IsViewList = 0; + CtlIndex = 1; + Done = 0; + + Sta = 0; +} + +void TfNetworkRegRemove::RenderBackGround(void) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, Color); +} + +void TfNetworkRegRemove::RenderBackGround(unsigned int aClr) +{ + RectFillRender(Content.Left, Content.Top, Content.Right, Content.Bottom, aClr); +} + +void TfNetworkRegRemove::DrawSelf(void) +{ + unsigned int x, y, x2, y2, w, h; + + VertLineRender(Bound.Left, Bound.Top, Bound.Height -1, 0xFFFFFFFF); + VertLineRender(Bound.Right -1, Bound.Top +1, Bound.Height -2, 0xFF808080); + VertLineRender(Bound.Right, Bound.Top, Bound.Height, 0xFF404040); + + HorizLineRender(Bound.Left, Bound.Top, Bound.Width - 1, 0xFFFFFFFF); + HorizLineRender(Bound.Left +1, Bound.Bottom -1, Bound.Width - 2, 0xFF808080); + HorizLineRender(Bound.Left, Bound.Bottom, Bound.Width, 0xFF404040); + + x = Bound.Left +2 ; + x2 = Bound.Right -2; + y = Bound.Top +2; + y2 = Bound.Bottom - 2; + w = Bound.Width -4; + h = Bound.Height - 4; + VertLineRender (x, y, h-1, 0xFF808080); + HorizLineRender (x, y, w-1, 0xFF808080); + + VertLineRender (x+1, y+1, h-2, 0xFF404040); + HorizLineRender (x+1, y+1, w-2, 0xFF404040); + + VertLineRender (x2-1, y+1, h-2, 0xFFD4D0C8); + HorizLineRender (x+1, y2-1, w-2, 0xFFD4D0C8); + + VertLineRender (x2, y, h, 0xFFFFFFFF); + HorizLineRender (x, y2, w, 0xFFFFFFFF); + + RenderBackGround(); +} + + +void TfNetworkRegRemove::DrawCaption2(void) +{ + TMyString::sFromStr("TAB键在面板与机器列表之间切换", SText.Text); + SText.Show(); +} + +void TfNetworkRegRemove::Show(void) +{ + IsShowing = 1; + RenderBackGround(); + DrawSelf(); + ShowCaption(); + DrawCaption2(); + + //TextRender_string24(42,200,clNearBlack,"设置键向左选择,查询键向右选择,上下键在添加栏与删除栏之间切换"); +} + +void TfNetworkRegRemove::FullRedraw(int Prm) +{ + if(Prm == 0){ + IsShowing = 1; + RenderBackGround(); + DrawSelf(); + ShowCaption(); + DrawCaption2(); + //TextRender_string24(20,200,clNearBlack,"设置键向左选择,查询键向右选择,上下键在添加栏与删除栏之间切换"); + + aPanel->Show(); + ShowResult(); + //DrawList(); + }else + if(Prm == 1){ + //RectFillRender(GuiRedrawDataList[1][0], GuiRedrawDataList[1][1], GuiRedrawDataList[1][2], GuiRedrawDataList[1][3], Color); + //TextRender_string24(20,200,clNearBlack,"设置键向左选择,查询键向右选择,上下键在添加栏与删除栏之间切换"); + + aPanel->Show(); + ShowResult(); + //DrawList(); + + //if(IsPermission)PmsIntervene4Gui.ReDraw4GuiRecall(); + } +} + +void TfNetworkRegRemove::ShowCaption() +{ + TMyString::sFromStr("系统安装->清除组网配置", Caption.Text); + Caption.Show(); +} + +void TfNetworkRegRemove::SetPanelCaptionColor() +{ + if(IsViewList == 0){ + aPanel->Caption.Color = clDeepBlue; + aPanel->Caption.TextColor = clNearWhite; + }else{ + aPanel->Caption.Color = clMedGray; + aPanel->Caption.TextColor = clNearWhite; + } +} + +//______________________________________________________________________________________________________________________________ +void TfNetworkRegRemove::InitPanel(void) +{ + int i,x,y,x2,y2, aW,aH; + unsigned int aClr, bClr; + x = Content.Left; + y = Content.Top; + x2 = Content.Right; + y2 = Content.Bottom; + aW = Content.Width; + aH = Content.Height; + + //ClearData(); + //LoadData(); + + if(aPanel == nullptr)return; + + aPanel->Init(60,3,676,310,x,y,clFrmFace, bvRaised); + TMyString::sFromStr("清除组网配置", aPanel->Caption.Text); + aPanel->Caption.Visible = 1; + aPanel->Caption.Enable = 1; + + x = aPanel->Content.Left; + y = aPanel->Content.Top; + + aPanel->SText[0].Init(200,10,80,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[1].Init(10,60,80,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[2].Init(10,100,80,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[3].Init(10,140,80,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[4].Init(10,180,80,30,x,y,clNearBlack,clFrmFace); + aPanel->SText[5].Init(10,240,80,30,x,y,clNearBlack,clFrmFace); + + for(i=0; i<6; i++) + aPanel->SText[i].TextColor = clNearBlack; + aPanel->SText[i].SetText(" ", 24); + + aPanel->Show(); + ShowDetail(); + ShowResult(0); + + //Check4Selected(); + //aPanel->ReDrawItems(); + + //RectFillRender(80,149,646,150,clGray); + //DrawList(); +} + +//_____________________________________________________________________________________________________________________________ + +void TfNetworkRegRemove::ClearData() +{ + int i,x; + unsigned int aAddr; + //Clear + for(i=0; i<64; i++){ + aAddr = dAddrSdRam_Register + i*4; + *(volatile unsigned int *)(aAddr) = 0; + } + for(i=0; i<64; i++){ + for(x=0; x<64; x++){ + aAddr = dAddrSdRam_Register + dDescpOffSet + i*64 + x; + *(volatile unsigned int *)(aAddr) = 0; + } + } +} + +void TfNetworkRegRemove::LoadData() +{ + int i,x; + unsigned int aAddr; + //Load Here + Count = 0; + + //Clac + PageCount = Count / 10; + if(Count % 10){ + PageCount++; + } + PageIndex = 0; +} + +void TfNetworkRegRemove::DrawList() +{ + int i, x, y, z; + unsigned char aP0; + unsigned int aClr, aAddr, wc; + + if(IsViewList)aClr = clBlue; else aClr = clDeepGray; + + RectFillRender (13, 239, 786, 268, aClr); + TextRender_string24 (18, 241 , clNearWhite, "机器列表 数量:"); + TextDigitRender2Right24 (200,241 , clNearWhite, Count); + + RectFillRender(6,232,10,430,aClr); + RectFillRender(6,232,792,236,aClr); + RectFillRender(6,430,792,434,aClr); + RectFillRender(788,232,792,434,aClr); + + RectFillRender(11,269,787,429,clMoneyGreen); + + i = PageIndex * 10; + wc =0; + for(; i= 10)break; + } + i = PageIndex * 10; + TVScrollBar::sDrawByPoint(767, 270, 786, 428, aClr, clGray, Count, 14, i); +} + +void TfNetworkRegRemove::ShowDetail() +{ + int i; + if(MainCtl.fData.Split.NetworkMode == 1){ + aPanel->SText[1].SetText("本机为集中机", 24); + aPanel->SText[2].SetText("本机机器号:", 24); + TMyString::sAddOn2Dg(MainCtl.fData.Split.MyNum, aPanel->SText[2].Text); + aPanel->SText[3].SetText("区域机号列表:", 24); + aPanel->SText[4].SetText(" ", 24); + for(i=0; iSText[4].Text); + } + + aPanel->SText[5].SetText("按确认键清除区域机列表", 24); + ShowResult(1); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + aPanel->SText[1].SetText("本机为区域机", 24); + aPanel->SText[2].SetText("本机机器号:", 24); + TMyString::sAddOn2Dg(MainCtl.fData.Split.MyNum, aPanel->SText[2].Text); + aPanel->SText[3].SetText("挂载的集中机号:", 24); + aPanel->SText[4].SetText(" ", 24); + if(ProtoC2C.MasterNum)TMyString::sAddOn2Dg(ProtoC2C.MasterNum, aPanel->SText[4].Text); + aPanel->SText[5].SetText("按确认键清除挂载集中机", 24); + ShowResult(1); + }else{ + aPanel->SText[1].SetText("本机为单机", 24); + aPanel->SText[2].SetText("本机机器号:", 24); + TMyString::sAddOn2Dg(MainCtl.fData.Split.MyNum, aPanel->SText[2].Text); + aPanel->SText[3].SetText(" ", 24); + aPanel->SText[4].SetText(" ", 24); + aPanel->SText[5].SetText("无可用操作", 24); + ShowResult(-1); + } + + aPanel->Show(); +} + +void TfNetworkRegRemove::ShowResult() +{ + if(Sta == 0){ + aPanel->SText[0].SetText(" ",24); + }else + if(Sta == 1){ + aPanel->SText[0].SetText("清除成功",24); + }else + if(Sta == -1){ + aPanel->SText[0].SetText("操作失败",24); + } + aPanel->SText[0].Show(); +} + +void TfNetworkRegRemove::ShowResult(int aSta) +{ + Sta = aSta; + ShowResult(); +} + +void TfNetworkRegRemove::ClearOutText() +{ + TMyString::sClear(aPanel->SText[0].Text); + aPanel->SText[0].Show(); +} + +void TfNetworkRegRemove::Task1000Ms() +{ + if(IsShowing){ + + } +} + +void TfNetworkRegRemove::Check4Selected() +{ + aPanel->Btn[1].Selected = 0; + aPanel->Btn[2].Selected = 0; + aPanel->Edit[2].Selected = 0; + + if(IsViewList ==0){ + if(CtlIndex == 0){ + aPanel->Btn[1].Selected = 1; + }else + if(CtlIndex == 1){ + aPanel->Edit[2].Selected = 1; + }else + if(CtlIndex == 2){ + aPanel->Btn[2].Selected = 1; + } + } + +} + +TGuiMsgReturn TfNetworkRegRemove::KeyIn(unsigned char aKey) +{ + TGuiMsgReturn aMsg = guiMsgNone; + unsigned char aP0,aP1,Err; + unsigned char x,y,aLen; + TDMix aFullPath; + + switch(aKey){ + case VK_EXECUTE: + if( (MainCtl.fData.Split.NetworkMode == 1) || (MainCtl.fData.Split.NetworkMode == 2) ){ + ProtoC2C.MasterNum = 0; + ProtoC2C.SlaveCount = 0; + for(x=0; x0){ + PageIndex--; + DrawList(); + } + break; + case VK_DOWN: + if(PageIndex <(PageCount-1)){ + PageIndex++; + DrawList(); + } + break; + case VK_TAB: + IsViewList = 0; + DrawList(); + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + }else{ + switch(aKey){ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case VK_DELETE: + if(CtlIndex == 1){ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + } + break; + case VK_LEFT: + if(CtlIndex == 0){ + CtlIndex = 1; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex == 1){ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + }else + if(CtlIndex == 2){ + CtlIndex--; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_RIGHT: + if(CtlIndex == 1){ + if(aPanel->Edit[2].Pst > 0){ + CtlIndex++; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else{ + aPanel->Edit[2].KeyIn(aKey); + aPanel->Edit[2].Show(); + } + } + break; + case VK_UP: + if(CtlIndex == 1){ + CtlIndex = 0; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex == 2){ + CtlIndex = 0; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_DOWN: + if(CtlIndex == 0){ + CtlIndex = 2; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case dfKEY_SETUP: + if(CtlIndex != 1){ + CtlIndex = 1; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case dfKEY_QUERY: + if(CtlIndex == 1){ + CtlIndex++; + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + } + break; + case VK_TAB: + IsViewList = 1; + DrawList(); + Check4Selected(); + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + break; + case VK_EXECUTE: + if(CtlIndex == 0){ + IsViewList = 1; + SetPanelCaptionColor(); + aPanel->ReDrawItems(); + }else + if(CtlIndex == 1){ + IsShowing = 0; + aMsg = guiMsgReturn; + } + break; + case VK_RETURN: + IsShowing = 0; + aMsg = guiMsgReturn; + break; + } + } + return aMsg; +} + +void TfNetworkRegRemove::SendfNetMsg(int Len) +{ + +} + +void TfNetworkRegRemove::PushfNetMsg(unsigned char *data, int Len) +{ + +} + +int TfNetworkRegRemove::ExtRequst(unsigned char Prm) +{ + IsShowing = 0; + return 0; +} + diff --git a/MyCode/Gui/fNetworkRegRemove.h b/MyCode/Gui/fNetworkRegRemove.h new file mode 100644 index 0000000..db00035 --- /dev/null +++ b/MyCode/Gui/fNetworkRegRemove.h @@ -0,0 +1,85 @@ +#ifndef FNETWORKREGREMOVE_H_ +#define FNETWORKREGREMOVE_H_ + +#include "gType.h" +#include "GraphBase.h" +#include "string.h" +#include "my_string.h" +#include "Device.h" +#include "EpDevice.h" +#include "StaticText.h" +#include "CtlPanel1.h" + +class TfNetworkRegRemove{ + public: + TCtlPanel1 *aPanel; + public: + TStaticText Caption; + TStaticText SText; + u32 Color; + + int TabOrder; + + TPoint OwnerLeftTop; //ParrentLeftTop; + TRect Bound; + TRect Content; + TMyString Str; + + int IsShowing; + unsigned char IsViewList; + unsigned char CtlIndex; + + unsigned char Count; + unsigned char PageIndex; + unsigned char PageCount; + unsigned char Done; + + char dText[64]; + unsigned char Data[12]; + unsigned char RecData[12]; + + int Sta; + public: + TfNetworkRegRemove(){}; + TfNetworkRegRemove(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor){ + Init(x1, y1, aW, aH, OwnerX, OwnerY, aColor); + } + void Init(int x1, int y1, int aW, int aH, int OwnerX, int OwnerY, u32 aColor); + + void SetAndShowCaption(unsigned char aType); + void RenderBackGround(void); + void RenderBackGround(unsigned int aClr); + void DrawSelf(void); + void ClearOutText(); + void ShowDetail(); + void ShowResult(); + void ShowResult(int aSta); + + void Show(void); + void FullRedraw(int Prm); + void ShowCaption(); + void ReDraw(void); + void DrawCaption2(void); + void DrawList(); + void SetPanelCaptionColor(); + void ClearData(); + void LoadData(); + + TGuiMsgReturn KeyIn(unsigned char aKey); + + void InitPanel(void); + void Check4Selected(void); + + void Task1000Ms(); + + void SendfNetMsg(int Len); + void PushfNetMsg(unsigned char *data, int Len); + + int ExtRequst(unsigned char Prm); + +}; + + + +#endif + diff --git a/MyCode/Gui/font_11x16.cpp b/MyCode/Gui/font_11x16.cpp new file mode 100644 index 0000000..9661430 --- /dev/null +++ b/MyCode/Gui/font_11x16.cpp @@ -0,0 +1,1840 @@ +/** + ****************************************************************************** + * @file font16.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text font16 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text font16 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +// +// Font data for Courier New 12pt +// + +#include"my_font.h" + +const unsigned char ascii_11x16_table[] = +{ + // @0 ' ' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @32 '!' (11 pixels wide) + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @64 '"' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1D, 0xC0, // ### ### + 0x1D, 0xC0, // ### ### + 0x08, 0x80, // # # + 0x08, 0x80, // # # + 0x08, 0x80, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @96 '#' (11 pixels wide) + 0x00, 0x00, // + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x3F, 0xC0, // ######## + 0x1B, 0x00, // ## ## + 0x3F, 0xC0, // ######## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @128 '$' (11 pixels wide) + 0x04, 0x00, // # + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x38, 0x00, // ### + 0x1E, 0x00, // #### + 0x0F, 0x00, // #### + 0x03, 0x80, // ### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @160 '%' (11 pixels wide) + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x24, 0x00, // # # + 0x24, 0x00, // # # + 0x18, 0xC0, // ## ## + 0x07, 0x80, // #### + 0x1E, 0x00, // #### + 0x31, 0x80, // ## ## + 0x02, 0x40, // # # + 0x02, 0x40, // # # + 0x01, 0x80, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @192 '&' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x1D, 0x80, // ### ## + 0x37, 0x00, // ## ### + 0x33, 0x00, // ## ## + 0x1D, 0x80, // ### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @224 ''' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x02, 0x00, // # + 0x02, 0x00, // # + 0x02, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @256 '(' (11 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0E, 0x00, // ### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0E, 0x00, // ### + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @288 ')' (11 pixels wide) + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x1C, 0x00, // ### + 0x18, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @320 '*' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x3F, 0xC0, // ######## + 0x0F, 0x00, // #### + 0x1F, 0x80, // ###### + 0x19, 0x80, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @352 '+' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x3F, 0x80, // ####### + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @384 ',' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x0C, 0x00, // ## + 0x08, 0x00, // # + 0x08, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + + // @416 '-' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @448 '.' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @480 '/' (11 pixels wide) + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @512 '0' (11 pixels wide) + 0x00, 0x00, // + 0x0E, 0x00, // ### + 0x1B, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @544 '1' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x3E, 0x00, // ##### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @576 '2' (11 pixels wide) + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x19, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x30, 0x00, // ## + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @608 '3' (11 pixels wide) + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x61, 0x80, // ## ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x1F, 0x00, // ##### + 0x03, 0x80, // ### + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x61, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @640 '4' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x0F, 0x00, // #### + 0x0B, 0x00, // # ## + 0x1B, 0x00, // ## ## + 0x13, 0x00, // # ## + 0x33, 0x00, // ## ## + 0x3F, 0x80, // ####### + 0x03, 0x00, // ## + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @672 '5' (11 pixels wide) + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1F, 0x00, // ##### + 0x11, 0x80, // # ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x21, 0x80, // # ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @704 '6' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x1C, 0x00, // ### + 0x18, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x00, // ## ### + 0x39, 0x80, // ### ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x19, 0x80, // ## ## + 0x0F, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @736 '7' (11 pixels wide) + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x43, 0x00, // # ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @768 '8' (11 pixels wide) + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @800 '9' (11 pixels wide) + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x33, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0x80, // ### ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x07, 0x00, // ### + 0x3C, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @832 ':' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @864 ';' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x08, 0x00, // # + 0x08, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @896 '<' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0xC0, // ## + 0x03, 0x00, // ## + 0x04, 0x00, // # + 0x18, 0x00, // ## + 0x60, 0x00, // ## + 0x18, 0x00, // ## + 0x04, 0x00, // # + 0x03, 0x00, // ## + 0x00, 0xC0, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @928 '=' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xC0, // ######### + 0x00, 0x00, // + 0x7F, 0xC0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @960 '>' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x60, 0x00, // ## + 0x18, 0x00, // ## + 0x04, 0x00, // # + 0x03, 0x00, // ## + 0x00, 0xC0, // ## + 0x03, 0x00, // ## + 0x04, 0x00, // # + 0x18, 0x00, // ## + 0x60, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @992 '?' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x01, 0x80, // ## + 0x07, 0x00, // ### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1024 '@' (11 pixels wide) + 0x00, 0x00, // + 0x0E, 0x00, // ### + 0x11, 0x00, // # # + 0x21, 0x00, // # # + 0x21, 0x00, // # # + 0x27, 0x00, // # ### + 0x29, 0x00, // # # # + 0x29, 0x00, // # # # + 0x27, 0x00, // # ### + 0x20, 0x00, // # + 0x11, 0x00, // # # + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1056 'A' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x0F, 0x00, // #### + 0x09, 0x00, // # # + 0x19, 0x80, // ## ## + 0x19, 0x80, // ## ## + 0x1F, 0x80, // ###### + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x79, 0xE0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1088 'B' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1120 'C' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x40, // ##### # + 0x30, 0xC0, // ## ## + 0x60, 0x40, // ## # + 0x60, 0x00, // ## + 0x60, 0x00, // ## + 0x60, 0x00, // ## + 0x60, 0x40, // ## # + 0x30, 0x80, // ## # + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1152 'D' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1184 'E' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x30, 0x80, // ## # + 0x30, 0x80, // ## # + 0x32, 0x00, // ## # + 0x3E, 0x00, // ##### + 0x32, 0x00, // ## # + 0x30, 0x80, // ## # + 0x30, 0x80, // ## # + 0x7F, 0x80, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1216 'F' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xC0, // ######### + 0x30, 0x40, // ## # + 0x30, 0x40, // ## # + 0x32, 0x00, // ## # + 0x3E, 0x00, // ##### + 0x32, 0x00, // ## # + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7C, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1248 'G' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1E, 0x80, // #### # + 0x31, 0x80, // ## ## + 0x60, 0x80, // ## # + 0x60, 0x00, // ## + 0x60, 0x00, // ## + 0x67, 0xC0, // ## ##### + 0x61, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1280 'H' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x80, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1312 'I' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xC0, // ######## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1344 'J' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xC0, // ####### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x63, 0x00, // ## ## + 0x63, 0x00, // ## ## + 0x63, 0x00, // ## ## + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1376 'K' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x33, 0x00, // ## ## + 0x36, 0x00, // ## ## + 0x3C, 0x00, // #### + 0x3E, 0x00, // ##### + 0x33, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x79, 0xC0, // #### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1408 'L' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7E, 0x00, // ###### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x40, // ## # + 0x18, 0x40, // ## # + 0x18, 0x40, // ## # + 0x7F, 0xC0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1440 'M' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0xE0, 0xE0, // ### ### + 0x60, 0xC0, // ## ## + 0x71, 0xC0, // ### ### + 0x7B, 0xC0, // #### #### + 0x6A, 0xC0, // ## # # ## + 0x6E, 0xC0, // ## ### ## + 0x64, 0xC0, // ## # ## + 0x60, 0xC0, // ## ## + 0xFB, 0xE0, // ##### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1472 'N' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x73, 0xC0, // ### #### + 0x31, 0x80, // ## ## + 0x39, 0x80, // ### ## + 0x3D, 0x80, // #### ## + 0x35, 0x80, // ## # ## + 0x37, 0x80, // ## #### + 0x33, 0x80, // ## ### + 0x31, 0x80, // ## ## + 0x79, 0x80, // #### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1504 'O' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1536 'P' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7E, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1568 'Q' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x0C, 0xC0, // ## ## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1600 'R' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x00, // ####### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3E, 0x00, // ##### + 0x33, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7C, 0xE0, // ##### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1632 'S' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x38, 0x00, // ### + 0x1F, 0x00, // ##### + 0x03, 0x80, // ### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1664 'T' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x4C, 0x80, // # ## # + 0x4C, 0x80, // # ## # + 0x4C, 0x80, // # ## # + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1696 'U' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1728 'V' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x0A, 0x00, // # # + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1760 'W' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0xFB, 0xE0, // ##### ##### + 0x60, 0xC0, // ## ## + 0x64, 0xC0, // ## # ## + 0x6E, 0xC0, // ## ### ## + 0x6E, 0xC0, // ## ### ## + 0x2A, 0x80, // # # # # + 0x3B, 0x80, // ### ### + 0x3B, 0x80, // ### ### + 0x31, 0x80, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1792 'X' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x1B, 0x00, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1824 'Y' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x79, 0xE0, // #### #### + 0x30, 0xC0, // ## ## + 0x19, 0x80, // ## ## + 0x0F, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1856 'Z' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x21, 0x80, // # ## + 0x23, 0x00, // # ## + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x0C, 0x00, // ## + 0x18, 0x80, // ## # + 0x30, 0x80, // ## # + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1888 '[' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1920 '\' (11 pixels wide) + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1952 ']' (11 pixels wide) + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1E, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1984 '^' (11 pixels wide) + 0x04, 0x00, // # + 0x0A, 0x00, // # # + 0x0A, 0x00, // # # + 0x11, 0x00, // # # + 0x20, 0x80, // # # + 0x20, 0x80, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2016 '_' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0xFF, 0xE0, // ########### + + // @2048 '`' (11 pixels wide) + 0x08, 0x00, // # + 0x04, 0x00, // # + 0x02, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2080 'a' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0xC0, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2112 'b' (11 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x00, // ## ### + 0x39, 0x80, // ### ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x39, 0x80, // ### ## + 0x77, 0x00, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2144 'c' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1E, 0x80, // #### # + 0x31, 0x80, // ## ## + 0x60, 0x80, // ## # + 0x60, 0x00, // ## + 0x60, 0x80, // ## # + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2176 'd' (11 pixels wide) + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x1D, 0x80, // ### ## + 0x33, 0x80, // ## ### + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0xC0, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2208 'e' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x7F, 0xC0, // ######### + 0x60, 0x00, // ## + 0x30, 0xC0, // ## ## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2240 'f' (11 pixels wide) + 0x00, 0x00, // + 0x07, 0xE0, // ###### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0x80, // ####### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2272 'g' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1D, 0xC0, // ### ### + 0x33, 0x80, // ## ### + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0x80, // ### ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2304 'h' (11 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x00, // ## ### + 0x39, 0x80, // ### ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2336 'i' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2368 'j' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2400 'k' (11 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x80, // ## #### + 0x36, 0x00, // ## ## + 0x3C, 0x00, // #### + 0x3C, 0x00, // #### + 0x36, 0x00, // ## ## + 0x33, 0x00, // ## ## + 0x77, 0xC0, // ### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2432 'l' (11 pixels wide) + 0x00, 0x00, // + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2464 'm' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x36, 0xC0, // ## ## ## + 0x76, 0xE0, // ### ## ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2496 'n' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x77, 0x00, // ### ### + 0x39, 0x80, // ### ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2528 'o' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x31, 0x80, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x60, 0xC0, // ## ## + 0x31, 0x80, // ## ## + 0x1F, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2560 'p' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x77, 0x00, // ### ### + 0x39, 0x80, // ### ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x39, 0x80, // ### ## + 0x37, 0x00, // ## ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7C, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2592 'q' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1D, 0xC0, // ### ### + 0x33, 0x80, // ## ### + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x61, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0x80, // ### ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2624 'r' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0x80, // #### ### + 0x1C, 0xC0, // ### ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2656 's' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x31, 0x80, // ## ## + 0x3C, 0x00, // #### + 0x1F, 0x00, // ##### + 0x03, 0x80, // ### + 0x31, 0x80, // ## ## + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2688 't' (11 pixels wide) + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x7F, 0x00, // ####### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x80, // ## # + 0x0F, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2720 'u' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x73, 0x80, // ### ### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x33, 0x80, // ## ### + 0x1D, 0xC0, // ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2752 'v' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x31, 0x80, // ## ## + 0x31, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2784 'w' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0xF1, 0xE0, // #### #### + 0x60, 0xC0, // ## ## + 0x64, 0xC0, // ## # ## + 0x6E, 0xC0, // ## ### ## + 0x3B, 0x80, // ### ### + 0x3B, 0x80, // ### ### + 0x31, 0x80, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2816 'x' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7B, 0xC0, // #### #### + 0x1B, 0x00, // ## ## + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x0E, 0x00, // ### + 0x1B, 0x00, // ## ## + 0x7B, 0xC0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2848 'y' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x79, 0xE0, // #### #### + 0x30, 0xC0, // ## ## + 0x19, 0x80, // ## ## + 0x19, 0x80, // ## ## + 0x0B, 0x00, // # ## + 0x0F, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2880 'z' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x21, 0x80, // # ## + 0x03, 0x00, // ## + 0x0E, 0x00, // ### + 0x18, 0x00, // ## + 0x30, 0x80, // ## # + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2912 '{' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2944 '|' (11 pixels wide) + 0x00, 0x00, // + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2976 '}' (11 pixels wide) + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3008 '~' (11 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x18, 0x00, // ## + 0x24, 0x80, // # # # + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // +}; + + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/MyCode/Gui/font_14x20.cpp b/MyCode/Gui/font_14x20.cpp new file mode 100644 index 0000000..9137967 --- /dev/null +++ b/MyCode/Gui/font_14x20.cpp @@ -0,0 +1,2216 @@ +/** + ****************************************************************************** + * @file font20.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text font20 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text font20 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +#include"my_font.h" +// Character bitmaps for Courier New 15pt +const unsigned char ascii_14x20_table[] = +{ + // @0 ' ' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @40 '!' (14 pixels wide) + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x02, 0x00, // # + 0x02, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @80 '"' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1C, 0xE0, // ### ### + 0x1C, 0xE0, // ### ### + 0x1C, 0xE0, // ### ### + 0x08, 0x40, // # # + 0x08, 0x40, // # # + 0x08, 0x40, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @120 '#' (14 pixels wide) + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @160 '$' (14 pixels wide) + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x07, 0xE0, // ###### + 0x0F, 0xE0, // ####### + 0x18, 0x60, // ## ## + 0x18, 0x00, // ## + 0x1F, 0x00, // ##### + 0x0F, 0xC0, // ###### + 0x00, 0xE0, // ### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xC0, // ####### + 0x1F, 0x80, // ###### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @200 '%' (14 pixels wide) + 0x00, 0x00, // + 0x1C, 0x00, // ### + 0x22, 0x00, // # # + 0x22, 0x00, // # # + 0x22, 0x00, // # # + 0x1C, 0x60, // ### ## + 0x01, 0xE0, // #### + 0x0F, 0x80, // ##### + 0x3C, 0x00, // #### + 0x31, 0xC0, // ## ### + 0x02, 0x20, // # # + 0x02, 0x20, // # # + 0x02, 0x20, // # # + 0x01, 0xC0, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @240 '&' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0xE0, // ##### + 0x0F, 0xE0, // ####### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x0F, 0x30, // #### ## + 0x1F, 0xF0, // ######### + 0x19, 0xE0, // ## #### + 0x18, 0xC0, // ## ## + 0x1F, 0xF0, // ######### + 0x07, 0xB0, // #### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @280 ''' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x01, 0x00, // # + 0x01, 0x00, // # + 0x01, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @320 '(' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @360 ')' (14 pixels wide) + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @400 '*' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1B, 0x60, // ## ## ## + 0x1F, 0xE0, // ######## + 0x07, 0x80, // #### + 0x07, 0x80, // #### + 0x0F, 0xC0, // ###### + 0x0C, 0xC0, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @440 '+' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @480 ',' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @520 '-' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @560 '.' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @600 '/' (14 pixels wide) + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @640 '0' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x18, 0xC0, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x1F, 0xC0, // ####### + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @680 '1' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x1F, 0x00, // ##### + 0x1F, 0x00, // ##### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @720 '2' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x00, 0x60, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x18, 0x00, // ## + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @760 '3' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x3F, 0xC0, // ######## + 0x30, 0xE0, // ## ### + 0x00, 0x60, // ## + 0x00, 0xE0, // ### + 0x07, 0xC0, // ##### + 0x07, 0xC0, // ##### + 0x00, 0xE0, // ### + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x60, 0xE0, // ## ### + 0x7F, 0xC0, // ######### + 0x3F, 0x80, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @800 '4' (14 pixels wide) + 0x00, 0x00, // + 0x01, 0xC0, // ### + 0x03, 0xC0, // #### + 0x03, 0xC0, // #### + 0x06, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x30, 0xC0, // ## ## + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x00, 0xC0, // ## + 0x03, 0xE0, // ##### + 0x03, 0xE0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @840 '5' (14 pixels wide) + 0x00, 0x00, // + 0x1F, 0xC0, // ####### + 0x1F, 0xC0, // ####### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1F, 0x80, // ###### + 0x1F, 0xC0, // ####### + 0x18, 0xE0, // ## ### + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x30, 0xE0, // ## ### + 0x3F, 0xC0, // ######## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @880 '6' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0xE0, // ##### + 0x0F, 0xE0, // ####### + 0x1E, 0x00, // #### + 0x18, 0x00, // ## + 0x38, 0x00, // ### + 0x37, 0x80, // ## #### + 0x3F, 0xC0, // ######## + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x18, 0xE0, // ## ### + 0x1F, 0xC0, // ####### + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @920 '7' (14 pixels wide) + 0x00, 0x00, // + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x30, 0x60, // ## ## + 0x00, 0x60, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @960 '8' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x38, 0xE0, // ### ### + 0x1F, 0xC0, // ####### + 0x1F, 0xC0, // ####### + 0x38, 0xE0, // ### ### + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x38, 0xE0, // ### ### + 0x1F, 0xC0, // ####### + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1000 '9' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x1F, 0xC0, // ####### + 0x38, 0xC0, // ### ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x38, 0xE0, // ### ### + 0x1F, 0xE0, // ######## + 0x0F, 0x60, // #### ## + 0x00, 0xE0, // ### + 0x00, 0xC0, // ## + 0x03, 0xC0, // #### + 0x3F, 0x80, // ####### + 0x3E, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1040 ':' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x03, 0x80, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1080 ';' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x01, 0xC0, // ### + 0x01, 0xC0, // ### + 0x01, 0xC0, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x04, 0x00, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1120 '<' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x30, // ## + 0x00, 0xF0, // #### + 0x03, 0xC0, // #### + 0x07, 0x00, // ### + 0x1C, 0x00, // ### + 0x78, 0x00, // #### + 0x1C, 0x00, // ### + 0x07, 0x00, // ### + 0x03, 0xC0, // #### + 0x00, 0xF0, // #### + 0x00, 0x30, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1160 '=' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xF0, // ########### + 0x7F, 0xF0, // ########### + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0xF0, // ########### + 0x7F, 0xF0, // ########### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1200 '>' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x30, 0x00, // ## + 0x3C, 0x00, // #### + 0x0F, 0x00, // #### + 0x03, 0x80, // ### + 0x00, 0xE0, // ### + 0x00, 0x78, // #### + 0x00, 0xE0, // ### + 0x03, 0x80, // ### + 0x0F, 0x00, // #### + 0x3C, 0x00, // #### + 0x30, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1240 '?' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0x80, // ##### + 0x1F, 0xC0, // ####### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x00, 0x60, // ## + 0x01, 0xC0, // ### + 0x03, 0x80, // ### + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1280 '@' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x80, // ### + 0x0C, 0x80, // ## # + 0x08, 0x40, // # # + 0x10, 0x40, // # # + 0x10, 0x40, // # # + 0x11, 0xC0, // # ### + 0x12, 0x40, // # # # + 0x12, 0x40, // # # # + 0x12, 0x40, // # # # + 0x11, 0xC0, // # ### + 0x10, 0x00, // # + 0x08, 0x00, // # + 0x08, 0x40, // # # + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1320 'A' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x80, // ###### + 0x1F, 0x80, // ###### + 0x03, 0x80, // ### + 0x06, 0xC0, // ## ## + 0x06, 0xC0, // ## ## + 0x0C, 0xC0, // ## ## + 0x0C, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x30, 0x30, // ## ## + 0x78, 0x78, // #### #### + 0x78, 0x78, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1360 'B' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x80, // ####### + 0x3F, 0xC0, // ######## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0xE0, // ## ### + 0x1F, 0xC0, // ####### + 0x1F, 0xE0, // ######## + 0x18, 0x70, // ## ### + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xE0, // ######### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1400 'C' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB0, // #### ## + 0x0F, 0xF0, // ######## + 0x1C, 0x70, // ### ### + 0x38, 0x30, // ### ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x38, 0x30, // ### ## + 0x1C, 0x70, // ### ### + 0x0F, 0xE0, // ####### + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1440 'D' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7F, 0x80, // ######## + 0x7F, 0xC0, // ######### + 0x30, 0xE0, // ## ### + 0x30, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x70, // ## ### + 0x30, 0xE0, // ## ### + 0x7F, 0xC0, // ######### + 0x7F, 0x80, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1480 'E' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x19, 0x80, // ## ## + 0x1F, 0x80, // ###### + 0x1F, 0x80, // ###### + 0x19, 0x80, // ## ## + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1520 'F' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x19, 0x80, // ## ## + 0x1F, 0x80, // ###### + 0x1F, 0x80, // ###### + 0x19, 0x80, // ## ## + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x3F, 0x00, // ###### + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1560 'G' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB0, // #### ## + 0x1F, 0xF0, // ######### + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x31, 0xF8, // ## ###### + 0x31, 0xF8, // ## ###### + 0x30, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x1F, 0xF0, // ######### + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1600 'H' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1640 'I' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1680 'J' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x03, 0xF8, // ####### + 0x03, 0xF8, // ####### + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x30, 0xE0, // ## ### + 0x3F, 0xC0, // ######## + 0x0F, 0x80, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1720 'K' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3E, 0xF8, // ##### ##### + 0x3E, 0xF8, // ##### ##### + 0x18, 0xE0, // ## ### + 0x19, 0x80, // ## ## + 0x1B, 0x00, // ## ## + 0x1F, 0x00, // ##### + 0x1D, 0x80, // ### ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0x60, // ## ## + 0x3E, 0x78, // ##### #### + 0x3E, 0x38, // ##### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1760 'L' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0x00, // ###### + 0x3F, 0x00, // ###### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x30, // ## ## + 0x0C, 0x30, // ## ## + 0x0C, 0x30, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1800 'M' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0x78, // #### #### + 0x78, 0x78, // #### #### + 0x38, 0x70, // ### ### + 0x3C, 0xF0, // #### #### + 0x34, 0xB0, // ## # # ## + 0x37, 0xB0, // ## #### ## + 0x37, 0xB0, // ## #### ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x30, 0x30, // ## ## + 0x7C, 0xF8, // ##### ##### + 0x7C, 0xF8, // ##### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1840 'N' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x39, 0xF0, // ### ##### + 0x3D, 0xF0, // #### ##### + 0x1C, 0x60, // ### ## + 0x1E, 0x60, // #### ## + 0x1E, 0x60, // #### ## + 0x1B, 0x60, // ## ## ## + 0x1B, 0x60, // ## ## ## + 0x19, 0xE0, // ## #### + 0x19, 0xE0, // ## #### + 0x18, 0xE0, // ## ### + 0x3E, 0xE0, // ##### ### + 0x3E, 0x60, // ##### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1880 'O' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x0F, 0xC0, // ###### + 0x1C, 0xE0, // ### ### + 0x38, 0x70, // ### ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x1C, 0xE0, // ### ### + 0x0F, 0xC0, // ###### + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1920 'P' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xC0, // ######## + 0x3F, 0xE0, // ######### + 0x18, 0x70, // ## ### + 0x18, 0x30, // ## ## + 0x18, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xE0, // ######## + 0x1F, 0xC0, // ####### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x3F, 0x00, // ###### + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @1960 'Q' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x0F, 0xC0, // ###### + 0x1C, 0xE0, // ### ### + 0x38, 0x70, // ### ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x1C, 0xE0, // ### ### + 0x0F, 0xC0, // ###### + 0x07, 0x80, // #### + 0x07, 0xB0, // #### ## + 0x0F, 0xF0, // ######## + 0x0C, 0xE0, // ## ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2000 'R' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xC0, // ######## + 0x3F, 0xE0, // ######### + 0x18, 0x70, // ## ### + 0x18, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xE0, // ######## + 0x1F, 0xC0, // ####### + 0x18, 0xE0, // ## ### + 0x18, 0x60, // ## ## + 0x18, 0x70, // ## ### + 0x3E, 0x38, // ##### ### + 0x3E, 0x18, // ##### ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2040 'S' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0xB0, // ##### ## + 0x1F, 0xF0, // ######### + 0x38, 0x70, // ### ### + 0x30, 0x30, // ## ## + 0x38, 0x00, // ### + 0x1F, 0x80, // ###### + 0x07, 0xE0, // ###### + 0x00, 0x70, // ### + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x3F, 0xE0, // ######### + 0x37, 0xC0, // ## ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2080 'T' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x0F, 0xC0, // ###### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2120 'U' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1C, 0xE0, // ### ### + 0x0F, 0xC0, // ###### + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2160 'V' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2200 'W' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x7C, 0x7C, // ##### ##### + 0x7C, 0x7C, // ##### ##### + 0x30, 0x18, // ## ## + 0x33, 0x98, // ## ### ## + 0x33, 0x98, // ## ### ## + 0x33, 0x98, // ## ### ## + 0x36, 0xD8, // ## ## ## ## + 0x16, 0xD0, // # ## ## # + 0x1C, 0x70, // ### ### + 0x1C, 0x70, // ### ### + 0x1C, 0x70, // ### ### + 0x18, 0x30, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2240 'X' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x0D, 0x80, // ## ## + 0x18, 0xC0, // ## ## + 0x30, 0x60, // ## ## + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2280 'Y' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x18, 0x60, // ## ## + 0x0C, 0xC0, // ## ## + 0x07, 0x80, // #### + 0x07, 0x80, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x0F, 0xC0, // ###### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2320 'Z' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2360 '[' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0xC0, // #### + 0x03, 0xC0, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0xC0, // #### + 0x03, 0xC0, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2400 '\' (14 pixels wide) + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x01, 0x80, // ## + 0x01, 0x80, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0x60, // ## + 0x00, 0x60, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2440 ']' (14 pixels wide) + 0x00, 0x00, // + 0x0F, 0x00, // #### + 0x0F, 0x00, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x0F, 0x00, // #### + 0x0F, 0x00, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2480 '^' (14 pixels wide) + 0x00, 0x00, // + 0x02, 0x00, // # + 0x07, 0x00, // ### + 0x0D, 0x80, // ## ## + 0x18, 0xC0, // ## ## + 0x30, 0x60, // ## ## + 0x20, 0x20, // # # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2520 '_' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0xFF, 0xFC, // ############## + 0xFF, 0xFC, // ############## + + // @2560 '`' (14 pixels wide) + 0x00, 0x00, // + 0x04, 0x00, // # + 0x03, 0x00, // ## + 0x00, 0x80, // # + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2600 'a' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0F, 0xC0, // ###### + 0x1F, 0xE0, // ######## + 0x00, 0x60, // ## + 0x0F, 0xE0, // ####### + 0x1F, 0xE0, // ######## + 0x38, 0x60, // ### ## + 0x30, 0xE0, // ## ### + 0x3F, 0xF0, // ########## + 0x1F, 0x70, // ##### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2640 'b' (14 pixels wide) + 0x00, 0x00, // + 0x70, 0x00, // ### + 0x70, 0x00, // ### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x37, 0x80, // ## #### + 0x3F, 0xE0, // ######### + 0x38, 0x60, // ### ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x60, // ### ## + 0x7F, 0xE0, // ########## + 0x77, 0x80, // ### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2680 'c' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB0, // #### ## + 0x1F, 0xF0, // ######### + 0x18, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x38, 0x30, // ### ## + 0x1F, 0xF0, // ######### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2720 'd' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x70, // ### + 0x00, 0x70, // ### + 0x00, 0x30, // ## + 0x00, 0x30, // ## + 0x07, 0xB0, // #### ## + 0x1F, 0xF0, // ######### + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x70, // ### ### + 0x1F, 0xF8, // ########## + 0x07, 0xB8, // #### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2760 'e' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x3F, 0xF0, // ########## + 0x3F, 0xF0, // ########## + 0x30, 0x00, // ## + 0x18, 0x30, // ## ## + 0x1F, 0xF0, // ######### + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2800 'f' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0xF0, // ###### + 0x07, 0xF0, // ####### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2840 'g' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB8, // #### ### + 0x1F, 0xF8, // ########## + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xF0, // ######### + 0x07, 0xB0, // #### ## + 0x00, 0x30, // ## + 0x00, 0x70, // ### + 0x0F, 0xE0, // ####### + 0x0F, 0xC0, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + + // @2880 'h' (14 pixels wide) + 0x00, 0x00, // + 0x38, 0x00, // ### + 0x38, 0x00, // ### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1B, 0xC0, // ## #### + 0x1F, 0xE0, // ######## + 0x1C, 0x60, // ### ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2920 'i' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x1F, 0x00, // ##### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @2960 'j' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xC0, // ####### + 0x1F, 0xC0, // ####### + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x00, 0xC0, // ## + 0x01, 0xC0, // ### + 0x3F, 0x80, // ####### + 0x3F, 0x00, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3000 'k' (14 pixels wide) + 0x00, 0x00, // + 0x38, 0x00, // ### + 0x38, 0x00, // ### + 0x18, 0x00, // ## + 0x18, 0x00, // ## + 0x1B, 0xE0, // ## ##### + 0x1B, 0xE0, // ## ##### + 0x1B, 0x00, // ## ## + 0x1E, 0x00, // #### + 0x1E, 0x00, // #### + 0x1B, 0x00, // ## ## + 0x19, 0x80, // ## ## + 0x39, 0xF0, // ### ##### + 0x39, 0xF0, // ### ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3040 'l' (14 pixels wide) + 0x00, 0x00, // + 0x1F, 0x00, // ##### + 0x1F, 0x00, // ##### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3080 'm' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x7E, 0xE0, // ###### ### + 0x7F, 0xF0, // ########### + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x33, 0x30, // ## ## ## + 0x7B, 0xB8, // #### ### ### + 0x7B, 0xB8, // #### ### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3120 'n' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3B, 0xC0, // ### #### + 0x3F, 0xE0, // ######### + 0x1C, 0x60, // ### ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3160 'o' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0x80, // #### + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x07, 0x80, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3200 'p' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x77, 0x80, // ### #### + 0x7F, 0xE0, // ########## + 0x38, 0x60, // ### ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x38, 0x60, // ### ## + 0x3F, 0xE0, // ######### + 0x37, 0x80, // ## #### + 0x30, 0x00, // ## + 0x30, 0x00, // ## + 0x7C, 0x00, // ##### + 0x7C, 0x00, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3240 'q' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xB8, // #### ### + 0x1F, 0xF8, // ########## + 0x18, 0x70, // ## ### + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x30, 0x30, // ## ## + 0x18, 0x70, // ## ### + 0x1F, 0xF0, // ######### + 0x07, 0xB0, // #### ## + 0x00, 0x30, // ## + 0x00, 0x30, // ## + 0x00, 0xF8, // ##### + 0x00, 0xF8, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3280 'r' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xE0, // #### ### + 0x3D, 0xF0, // #### ##### + 0x0F, 0x30, // #### ## + 0x0E, 0x00, // ### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0xC0, // ######## + 0x3F, 0xC0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3320 's' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x07, 0xE0, // ###### + 0x1F, 0xE0, // ######## + 0x18, 0x60, // ## ## + 0x1E, 0x00, // #### + 0x0F, 0xC0, // ###### + 0x01, 0xE0, // #### + 0x18, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0x80, // ###### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3360 't' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x3F, 0xE0, // ######### + 0x3F, 0xE0, // ######### + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x00, // ## + 0x0C, 0x30, // ## ## + 0x0F, 0xF0, // ######## + 0x07, 0xC0, // ##### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3400 'u' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x38, 0xE0, // ### ### + 0x38, 0xE0, // ### ### + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0x60, // ## ## + 0x18, 0xE0, // ## ### + 0x1F, 0xF0, // ######### + 0x0F, 0x70, // #### ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3440 'v' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x0D, 0x80, // ## ## + 0x07, 0x00, // ### + 0x07, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3480 'w' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x32, 0x60, // ## # ## + 0x32, 0x60, // ## # ## + 0x37, 0xE0, // ## ###### + 0x1D, 0xC0, // ### ### + 0x1D, 0xC0, // ### ### + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3520 'x' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x0C, 0xC0, // ## ## + 0x07, 0x80, // #### + 0x03, 0x00, // ## + 0x07, 0x80, // #### + 0x0C, 0xC0, // ## ## + 0x3C, 0xF0, // #### #### + 0x3C, 0xF0, // #### #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3560 'y' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x78, 0xF0, // #### #### + 0x78, 0xF0, // #### #### + 0x30, 0x60, // ## ## + 0x18, 0xC0, // ## ## + 0x18, 0xC0, // ## ## + 0x0D, 0x80, // ## ## + 0x0F, 0x80, // ##### + 0x07, 0x00, // ### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x00, // ## + 0x7F, 0x00, // ####### + 0x7F, 0x00, // ####### + 0x00, 0x00, // + 0x00, 0x00, // + + // @3600 'z' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x18, 0xC0, // ## ## + 0x01, 0x80, // ## + 0x03, 0x00, // ## + 0x06, 0x00, // ## + 0x0C, 0x60, // ## ## + 0x1F, 0xE0, // ######## + 0x1F, 0xE0, // ######## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3640 '{' (14 pixels wide) + 0x00, 0x00, // + 0x01, 0xC0, // ### + 0x03, 0xC0, // #### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x07, 0x00, // ### + 0x0E, 0x00, // ### + 0x07, 0x00, // ### + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0xC0, // #### + 0x01, 0xC0, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3680 '|' (14 pixels wide) + 0x00, 0x00, // + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x03, 0x00, // ## + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3720 '}' (14 pixels wide) + 0x00, 0x00, // + 0x1C, 0x00, // ### + 0x1E, 0x00, // #### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x07, 0x00, // ### + 0x03, 0x80, // ### + 0x07, 0x00, // ### + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x06, 0x00, // ## + 0x1E, 0x00, // #### + 0x1C, 0x00, // ### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + + // @3760 '~' (14 pixels wide) + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x0E, 0x00, // ### + 0x3F, 0x30, // ###### ## + 0x33, 0xF0, // ## ###### + 0x01, 0xE0, // #### + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // + 0x00, 0x00, // +}; + + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/MyCode/Gui/font_17x24.cpp b/MyCode/Gui/font_17x24.cpp new file mode 100644 index 0000000..993b3b6 --- /dev/null +++ b/MyCode/Gui/font_17x24.cpp @@ -0,0 +1,2593 @@ +/** + ****************************************************************************** + * @file font24.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text font24 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text font24 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + +#include"my_font.h" +/** @defgroup FONTS_Private_Variables + * @{ + */ +const unsigned char ascii_17x24_table [] = +{ + // @0 ' ' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @72 '!' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @144 '"' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0E, 0x70, 0x00, // ### ### + 0x0E, 0x70, 0x00, // ### ### + 0x0E, 0x70, 0x00, // ### ### + 0x04, 0x20, 0x00, // # # + 0x04, 0x20, 0x00, // # # + 0x04, 0x20, 0x00, // # # + 0x04, 0x20, 0x00, // # # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @216 '#' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @288 '$' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x07, 0xB0, 0x00, // #### ## + 0x0F, 0xF0, 0x00, // ######## + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x70, 0x00, // ## ### + 0x1C, 0x00, 0x00, // ### + 0x0F, 0x80, 0x00, // ##### + 0x07, 0xE0, 0x00, // ###### + 0x00, 0xF0, 0x00, // #### + 0x18, 0x30, 0x00, // ## ## + 0x1C, 0x30, 0x00, // ### ## + 0x1C, 0x70, 0x00, // ### ### + 0x1F, 0xE0, 0x00, // ######## + 0x1B, 0xC0, 0x00, // ## #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @360 '%' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0x80, 0x00, // #### + 0x0F, 0xC0, 0x00, // ###### + 0x1C, 0xE0, 0x00, // ### ### + 0x18, 0x60, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x1C, 0xE0, 0x00, // ### ### + 0x0F, 0xF8, 0x00, // ######### + 0x07, 0xE0, 0x00, // ###### + 0x1F, 0xF0, 0x00, // ######### + 0x07, 0x38, 0x00, // ### ### + 0x06, 0x18, 0x00, // ## ## + 0x06, 0x18, 0x00, // ## ## + 0x07, 0x38, 0x00, // ### ### + 0x03, 0xF0, 0x00, // ###### + 0x01, 0xE0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @432 '&' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xF0, 0x00, // ###### + 0x07, 0xF0, 0x00, // ####### + 0x0C, 0x60, 0x00, // ## ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x07, 0x00, 0x00, // ### + 0x0F, 0x9C, 0x00, // ##### ### + 0x1D, 0xFC, 0x00, // ### ####### + 0x18, 0xF0, 0x00, // ## #### + 0x18, 0x70, 0x00, // ## ### + 0x0F, 0xFC, 0x00, // ########## + 0x07, 0xDC, 0x00, // ##### ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @504 ''' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x01, 0x00, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @576 '(' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x18, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x00, 0x70, 0x00, // ### + 0x00, 0xF0, 0x00, // #### + 0x00, 0xE0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x70, 0x00, // ### + 0x00, 0x70, 0x00, // ### + 0x00, 0x38, 0x00, // ### + 0x00, 0x18, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @648 ')' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x18, 0x00, 0x00, // ## + 0x1C, 0x00, 0x00, // ### + 0x0E, 0x00, 0x00, // ### + 0x0E, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x0F, 0x00, 0x00, // #### + 0x0E, 0x00, 0x00, // ### + 0x1C, 0x00, 0x00, // ### + 0x18, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @720 '*' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x1D, 0xB8, 0x00, // ### ## ### + 0x1F, 0xF8, 0x00, // ########## + 0x07, 0xE0, 0x00, // ###### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @792 '+' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @864 ',' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x00, 0xC0, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @936 '-' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1008 '.' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1080 '/' (17 pixels wide) + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0x60, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x0E, 0x00, 0x00, // ### + 0x0C, 0x00, 0x00, // ## + 0x1C, 0x00, 0x00, // ### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1152 '0' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x07, 0xE0, 0x00, // ###### + 0x0C, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x07, 0xE0, 0x00, // ###### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1224 '1' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x80, 0x00, // # + 0x07, 0x80, 0x00, // #### + 0x1F, 0x80, 0x00, // ###### + 0x1D, 0x80, 0x00, // ### ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1296 '2' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xC0, 0x00, // ##### + 0x1F, 0xF0, 0x00, // ######### + 0x38, 0x30, 0x00, // ### ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x06, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1368 '3' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xE0, 0x00, // ####### + 0x0C, 0x70, 0x00, // ## ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x03, 0xC0, 0x00, // #### + 0x03, 0xE0, 0x00, // ##### + 0x00, 0x70, 0x00, // ### + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x0F, 0xC0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1440 '4' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x01, 0xE0, 0x00, // #### + 0x01, 0xE0, 0x00, // #### + 0x03, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0x60, 0x00, // ## ## + 0x0C, 0x60, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x30, 0x60, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x00, 0x60, 0x00, // ## + 0x03, 0xF8, 0x00, // ####### + 0x03, 0xF8, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1512 '5' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xF0, 0x00, // ######### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xC0, 0x00, // ## #### + 0x1F, 0xF0, 0x00, // ######### + 0x1C, 0x30, 0x00, // ### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x30, 0x30, 0x00, // ## ## + 0x3F, 0xF0, 0x00, // ########## + 0x0F, 0xC0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1584 '6' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xF8, 0x00, // ##### + 0x03, 0xF8, 0x00, // ####### + 0x07, 0x00, 0x00, // ### + 0x0E, 0x00, 0x00, // ### + 0x0C, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xC0, 0x00, // ## #### + 0x1F, 0xF0, 0x00, // ######### + 0x1C, 0x30, 0x00, // ### ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x38, 0x00, // ## ### + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xE0, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1656 '7' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0x60, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0xE0, 0x00, // ### + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1728 '8' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xE0, 0x00, // ###### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x07, 0xE0, 0x00, // ###### + 0x07, 0xE0, 0x00, // ###### + 0x0C, 0x30, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x07, 0xE0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1800 '9' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xC0, 0x00, // ##### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x30, 0x00, // ### ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x38, 0x00, // ## ### + 0x0F, 0xF8, 0x00, // ######### + 0x03, 0xD8, 0x00, // #### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x1F, 0xC0, 0x00, // ####### + 0x1F, 0x00, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1872 ':' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @1944 ';' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xF0, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x02, 0x00, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2016 '<' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x1C, 0x00, // ### + 0x00, 0x3C, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x0F, 0x00, 0x00, // #### + 0x3C, 0x00, 0x00, // #### + 0xF0, 0x00, 0x00, // #### + 0x3C, 0x00, 0x00, // #### + 0x0F, 0x00, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0xF0, 0x00, // #### + 0x00, 0x3C, 0x00, // #### + 0x00, 0x1C, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2088 '=' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xFC, 0x00, // ############# + 0x7F, 0xFC, 0x00, // ############# + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xFC, 0x00, // ############# + 0x7F, 0xFC, 0x00, // ############# + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2160 '>' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x70, 0x00, 0x00, // ### + 0x78, 0x00, 0x00, // #### + 0x1E, 0x00, 0x00, // #### + 0x07, 0x80, 0x00, // #### + 0x01, 0xE0, 0x00, // #### + 0x00, 0x78, 0x00, // #### + 0x00, 0x1E, 0x00, // #### + 0x00, 0x78, 0x00, // #### + 0x01, 0xE0, 0x00, // #### + 0x07, 0x80, 0x00, // #### + 0x1E, 0x00, 0x00, // #### + 0x78, 0x00, 0x00, // #### + 0x70, 0x00, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2232 '?' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xC0, 0x00, // ##### + 0x0F, 0xE0, 0x00, // ####### + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x30, 0x00, // ## ## + 0x00, 0x70, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x03, 0xC0, 0x00, // #### + 0x03, 0x80, 0x00, // ### + 0x03, 0x00, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0x00, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2304 '@' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xE0, 0x00, // ##### + 0x07, 0xF0, 0x00, // ####### + 0x0E, 0x38, 0x00, // ### ### + 0x0C, 0x18, 0x00, // ## ## + 0x18, 0x78, 0x00, // ## #### + 0x18, 0xF8, 0x00, // ## ##### + 0x19, 0xD8, 0x00, // ## ### ## + 0x19, 0x98, 0x00, // ## ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x18, 0xF8, 0x00, // ## ##### + 0x18, 0x78, 0x00, // ## #### + 0x18, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0E, 0x18, 0x00, // ### ## + 0x07, 0xF8, 0x00, // ######## + 0x03, 0xE0, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2376 'A' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0xC0, 0x00, // ####### + 0x01, 0xC0, 0x00, // ### + 0x03, 0x60, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0F, 0xF8, 0x00, // ######### + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0xFC, 0x7F, 0x00, // ###### ####### + 0xFC, 0x7F, 0x00, // ###### ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2448 'B' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xE0, 0x00, // ########## + 0x7F, 0xF0, 0x00, // ########### + 0x18, 0x38, 0x00, // ## ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x1C, 0x00, // ## ### + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x7F, 0xF8, 0x00, // ############ + 0x7F, 0xF0, 0x00, // ########### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2520 'C' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xEC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x1C, 0x1C, 0x00, // ### ### + 0x18, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x18, 0x0C, 0x00, // ## ## + 0x1C, 0x1C, 0x00, // ### ### + 0x0F, 0xF8, 0x00, // ######### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2592 'D' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xC0, 0x00, // ######### + 0x7F, 0xF0, 0x00, // ########### + 0x18, 0x38, 0x00, // ## ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0xF0, 0x00, // ########### + 0x7F, 0xE0, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2664 'E' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xF8, 0x00, // ############ + 0x7F, 0xF8, 0x00, // ############ + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x19, 0x80, 0x00, // ## ## + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0x80, 0x00, // ###### + 0x19, 0x80, 0x00, // ## ## + 0x19, 0x98, 0x00, // ## ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7F, 0xF8, 0x00, // ############ + 0x7F, 0xF8, 0x00, // ############ + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2736 'F' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0xCC, 0x00, // ## ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0F, 0xC0, 0x00, // ###### + 0x0F, 0xC0, 0x00, // ###### + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0xC0, 0x00, // ## ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x3F, 0xC0, 0x00, // ######## + 0x3F, 0xC0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2808 'G' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xEC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x1C, 0x1C, 0x00, // ### ### + 0x18, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x30, 0xFE, 0x00, // ## ####### + 0x30, 0xFE, 0x00, // ## ####### + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x0C, 0x00, // ### ## + 0x1C, 0x1C, 0x00, // ### ### + 0x0F, 0xFC, 0x00, // ########## + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2880 'H' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @2952 'I' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3024 'J' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xFE, 0x00, // ########## + 0x07, 0xFE, 0x00, // ########## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x60, 0x00, // ## ## + 0x3F, 0xE0, 0x00, // ######### + 0x0F, 0x80, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3096 'K' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0x3E, 0x00, // ####### ##### + 0x7F, 0x3E, 0x00, // ####### ##### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x18, 0xC0, 0x00, // ## ## + 0x19, 0x80, 0x00, // ## ## + 0x1B, 0x80, 0x00, // ## ### + 0x1F, 0xC0, 0x00, // ####### + 0x1C, 0xE0, 0x00, // ### ### + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0x1F, 0x00, // ####### ##### + 0x7F, 0x1F, 0x00, // ####### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3168 'L' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0x80, 0x00, // ######## + 0x7F, 0x80, 0x00, // ######## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x7F, 0xFC, 0x00, // ############# + 0x7F, 0xFC, 0x00, // ############# + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3240 'M' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xF0, 0x0F, 0x00, // #### #### + 0xF8, 0x1F, 0x00, // ##### ##### + 0x38, 0x1C, 0x00, // ### ### + 0x3C, 0x3C, 0x00, // #### #### + 0x3C, 0x3C, 0x00, // #### #### + 0x36, 0x6C, 0x00, // ## ## ## ## + 0x36, 0x6C, 0x00, // ## ## ## ## + 0x33, 0xCC, 0x00, // ## #### ## + 0x33, 0xCC, 0x00, // ## #### ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0xFE, 0x7F, 0x00, // ####### ####### + 0xFE, 0x7F, 0x00, // ####### ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3312 'N' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0xFE, 0x00, // #### ####### + 0x78, 0xFE, 0x00, // #### ####### + 0x1C, 0x18, 0x00, // ### ## + 0x1E, 0x18, 0x00, // #### ## + 0x1F, 0x18, 0x00, // ##### ## + 0x1B, 0x18, 0x00, // ## ## ## + 0x1B, 0x98, 0x00, // ## ### ## + 0x19, 0xD8, 0x00, // ## ### ## + 0x18, 0xD8, 0x00, // ## ## ## + 0x18, 0xF8, 0x00, // ## ##### + 0x18, 0x78, 0x00, // ## #### + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0x18, 0x00, // ####### ## + 0x7F, 0x18, 0x00, // ####### ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3384 'O' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3456 'P' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF8, 0x00, // ########### + 0x0C, 0x1C, 0x00, // ## ### + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x0C, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0F, 0xF8, 0x00, // ######### + 0x0F, 0xE0, 0x00, // ####### + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x3F, 0xC0, 0x00, // ######## + 0x3F, 0xC0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3528 'Q' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x07, 0xC0, 0x00, // ##### + 0x07, 0xCC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x0C, 0x38, 0x00, // ## ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3600 'R' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0xE0, 0x00, // ########## + 0x7F, 0xF0, 0x00, // ########### + 0x18, 0x38, 0x00, // ## ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xC0, 0x00, // ####### + 0x18, 0xE0, 0x00, // ## ### + 0x18, 0x70, 0x00, // ## ### + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x7F, 0x1E, 0x00, // ####### #### + 0x7F, 0x0E, 0x00, // ####### ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3672 'S' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xD8, 0x00, // ##### ## + 0x0F, 0xF8, 0x00, // ######### + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1E, 0x00, 0x00, // #### + 0x0F, 0xC0, 0x00, // ###### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x78, 0x00, // #### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1C, 0x38, 0x00, // ### ### + 0x1F, 0xF0, 0x00, // ######### + 0x1B, 0xE0, 0x00, // ## ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3744 'T' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x0F, 0xF0, 0x00, // ######## + 0x0F, 0xF0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3816 'U' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3888 'V' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7F, 0x7F, 0x00, // ####### ####### + 0x7F, 0x7F, 0x00, // ####### ####### + 0x18, 0x0C, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x01, 0xC0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x00, 0x80, 0x00, // # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @3960 'W' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xFE, 0x3F, 0x80, // ####### ####### + 0xFE, 0x3F, 0x80, // ####### ####### + 0x30, 0x06, 0x00, // ## ## + 0x30, 0x06, 0x00, // ## ## + 0x30, 0x86, 0x00, // ## # ## + 0x19, 0xCC, 0x00, // ## ### ## + 0x19, 0xCC, 0x00, // ## ### ## + 0x1B, 0x6C, 0x00, // ## ## ## ## + 0x1B, 0x6C, 0x00, // ## ## ## ## + 0x1E, 0x7C, 0x00, // #### ##### + 0x0E, 0x38, 0x00, // ### ### + 0x0E, 0x38, 0x00, // ### ### + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4032 'X' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x03, 0xC0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0xC0, 0x00, // #### + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4104 'Y' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7C, 0x7E, 0x00, // ##### ###### + 0x7C, 0x7E, 0x00, // ##### ###### + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x03, 0xC0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x0F, 0xF0, 0x00, // ######## + 0x0F, 0xF0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4176 'Z' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x18, 0xC0, 0x00, // ## ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x06, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4248 '[' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0xF0, 0x00, // ##### + 0x01, 0xF0, 0x00, // ##### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0xF0, 0x00, // ##### + 0x01, 0xF0, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4320 '\' (17 pixels wide) + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1C, 0x00, 0x00, // ### + 0x0C, 0x00, 0x00, // ## + 0x0E, 0x00, 0x00, // ### + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0x60, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x00, 0x30, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4392 ']' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0F, 0x80, 0x00, // ##### + 0x0F, 0x80, 0x00, // ##### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x0F, 0x80, 0x00, // ##### + 0x0F, 0x80, 0x00, // ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4464 '^' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x80, 0x00, // # + 0x01, 0xC0, 0x00, // ### + 0x03, 0xE0, 0x00, // ##### + 0x07, 0x70, 0x00, // ### ### + 0x06, 0x30, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x10, 0x04, 0x00, // # # + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4536 '_' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xFF, 0xFF, 0x00, // ################ + 0xFF, 0xFF, 0x00, // ################ + + // @4608 '`' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x03, 0x00, 0x00, // ## + 0x03, 0x80, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x60, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4680 'a' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0F, 0xC0, 0x00, // ###### + 0x1F, 0xE0, 0x00, // ######## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x07, 0xF0, 0x00, // ####### + 0x1F, 0xF0, 0x00, // ######### + 0x38, 0x30, 0x00, // ### ## + 0x30, 0x30, 0x00, // ## ## + 0x30, 0x70, 0x00, // ## ### + 0x1F, 0xFC, 0x00, // ########### + 0x0F, 0xBC, 0x00, // ##### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4752 'b' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x00, 0x00, // #### + 0x78, 0x00, 0x00, // #### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xE0, 0x00, // ## ##### + 0x1F, 0xF8, 0x00, // ########## + 0x1C, 0x18, 0x00, // ### ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x1C, 0x18, 0x00, // ### ## + 0x7F, 0xF8, 0x00, // ############ + 0x7B, 0xE0, 0x00, // #### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4824 'c' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xEC, 0x00, // ##### ## + 0x0F, 0xFC, 0x00, // ########## + 0x1C, 0x1C, 0x00, // ### ### + 0x38, 0x0C, 0x00, // ### ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x38, 0x0C, 0x00, // ### ## + 0x1C, 0x1C, 0x00, // ### ### + 0x0F, 0xF8, 0x00, // ######### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4896 'd' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x78, 0x00, // #### + 0x00, 0x78, 0x00, // #### + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x07, 0xD8, 0x00, // ##### ## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x38, 0x00, // ## ### + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xFE, 0x00, // ############ + 0x07, 0xDE, 0x00, // ##### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @4968 'e' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xE0, 0x00, // ###### + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x18, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x30, 0x00, 0x00, // ## + 0x30, 0x00, 0x00, // ## + 0x18, 0x0C, 0x00, // ## ## + 0x1F, 0xFC, 0x00, // ########### + 0x07, 0xF0, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5040 'f' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0xFC, 0x00, // ####### + 0x03, 0xFC, 0x00, // ######## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x3F, 0xF8, 0x00, // ########### + 0x3F, 0xF8, 0x00, // ########### + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF0, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5112 'g' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xDE, 0x00, // ##### #### + 0x1F, 0xFE, 0x00, // ############ + 0x18, 0x38, 0x00, // ## ### + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF8, 0x00, // ########## + 0x07, 0xD8, 0x00, // ##### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x38, 0x00, // ### + 0x0F, 0xF0, 0x00, // ######## + 0x0F, 0xC0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5184 'h' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x00, 0x00, // #### + 0x78, 0x00, 0x00, // #### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x1B, 0xE0, 0x00, // ## ##### + 0x1F, 0xF0, 0x00, // ######### + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5256 'i' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0x80, 0x00, // ###### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5328 'j' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xC0, 0x00, // ## + 0x00, 0xC0, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xF0, 0x00, // ######### + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x30, 0x00, // ## + 0x00, 0x70, 0x00, // ### + 0x1F, 0xE0, 0x00, // ######## + 0x1F, 0x80, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5400 'k' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3C, 0x00, 0x00, // #### + 0x3C, 0x00, 0x00, // #### + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0xF8, 0x00, // ## ##### + 0x0C, 0xF8, 0x00, // ## ##### + 0x0C, 0xC0, 0x00, // ## ## + 0x0D, 0x80, 0x00, // ## ## + 0x0F, 0x80, 0x00, // ##### + 0x0F, 0x00, 0x00, // #### + 0x0F, 0x80, 0x00, // ##### + 0x0D, 0xC0, 0x00, // ## ### + 0x0C, 0xE0, 0x00, // ## ### + 0x3C, 0x7C, 0x00, // #### ##### + 0x3C, 0x7C, 0x00, // #### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5472 'l' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0x80, 0x00, // ###### + 0x1F, 0x80, 0x00, // ###### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x3F, 0xFC, 0x00, // ############ + 0x3F, 0xFC, 0x00, // ############ + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5544 'm' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0xF7, 0x78, 0x00, // #### ### #### + 0xFF, 0xFC, 0x00, // ############## + 0x39, 0xCC, 0x00, // ### ### ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0x31, 0x8C, 0x00, // ## ## ## + 0xFD, 0xEF, 0x00, // ###### #### #### + 0xFD, 0xEF, 0x00, // ###### #### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5616 'n' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7B, 0xE0, 0x00, // #### ##### + 0x7F, 0xF0, 0x00, // ########### + 0x1C, 0x38, 0x00, // ### ### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x7E, 0x7E, 0x00, // ###### ###### + 0x7E, 0x7E, 0x00, // ###### ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5688 'o' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x03, 0xC0, 0x00, // #### + 0x0F, 0xF0, 0x00, // ######## + 0x1C, 0x38, 0x00, // ### ### + 0x38, 0x1C, 0x00, // ### ### + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x30, 0x0C, 0x00, // ## ## + 0x38, 0x1C, 0x00, // ### ### + 0x1C, 0x38, 0x00, // ### ### + 0x0F, 0xF0, 0x00, // ######## + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5760 'p' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7B, 0xE0, 0x00, // #### ##### + 0x7F, 0xF8, 0x00, // ############ + 0x1C, 0x18, 0x00, // ### ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x18, 0x0C, 0x00, // ## ## + 0x1C, 0x18, 0x00, // ### ## + 0x1F, 0xF8, 0x00, // ########## + 0x1B, 0xE0, 0x00, // ## ##### + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x18, 0x00, 0x00, // ## + 0x7F, 0x00, 0x00, // ####### + 0x7F, 0x00, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5832 'q' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xDE, 0x00, // ##### #### + 0x1F, 0xFE, 0x00, // ############ + 0x18, 0x38, 0x00, // ## ### + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x30, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF8, 0x00, // ########## + 0x07, 0xD8, 0x00, // ##### ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0x18, 0x00, // ## + 0x00, 0xFE, 0x00, // ####### + 0x00, 0xFE, 0x00, // ####### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5904 'r' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3E, 0x78, 0x00, // ##### #### + 0x3E, 0xFC, 0x00, // ##### ###### + 0x07, 0xCC, 0x00, // ##### ## + 0x07, 0x00, 0x00, // ### + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x06, 0x00, 0x00, // ## + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF0, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @5976 's' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0xF8, 0x00, // ######## + 0x0F, 0xF8, 0x00, // ######### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x1F, 0x80, 0x00, // ###### + 0x0F, 0xF0, 0x00, // ######## + 0x00, 0xF8, 0x00, // ##### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x1F, 0xF0, 0x00, // ######### + 0x1F, 0xE0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6048 't' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x3F, 0xF0, 0x00, // ########## + 0x3F, 0xF0, 0x00, // ########## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x00, 0x00, // ## + 0x0C, 0x1C, 0x00, // ## ### + 0x07, 0xFC, 0x00, // ######### + 0x03, 0xF0, 0x00, // ###### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6120 'u' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x78, 0x00, // #### #### + 0x78, 0x78, 0x00, // #### #### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x38, 0x00, // ## ### + 0x0F, 0xFE, 0x00, // ########### + 0x07, 0xDE, 0x00, // ##### #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6192 'v' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7C, 0x3E, 0x00, // ##### ##### + 0x7C, 0x3E, 0x00, // ##### ##### + 0x18, 0x18, 0x00, // ## ## + 0x18, 0x18, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x07, 0xE0, 0x00, // ###### + 0x03, 0xC0, 0x00, // #### + 0x03, 0xC0, 0x00, // #### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6264 'w' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x78, 0x3C, 0x00, // #### #### + 0x78, 0x3C, 0x00, // #### #### + 0x31, 0x18, 0x00, // ## # ## + 0x33, 0x98, 0x00, // ## ### ## + 0x33, 0x98, 0x00, // ## ### ## + 0x1A, 0xB0, 0x00, // ## # # ## + 0x1E, 0xF0, 0x00, // #### #### + 0x1E, 0xF0, 0x00, // #### #### + 0x1C, 0x60, 0x00, // ### ## + 0x0C, 0x60, 0x00, // ## ## + 0x0C, 0x60, 0x00, // ## ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6336 'x' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x3E, 0x7C, 0x00, // ##### ##### + 0x3E, 0x7C, 0x00, // ##### ##### + 0x0C, 0x30, 0x00, // ## ## + 0x06, 0x60, 0x00, // ## ## + 0x03, 0xC0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x03, 0xC0, 0x00, // #### + 0x06, 0x60, 0x00, // ## ## + 0x0C, 0x30, 0x00, // ## ## + 0x3E, 0x7C, 0x00, // ##### ##### + 0x3E, 0x7C, 0x00, // ##### ##### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6408 'y' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x7E, 0x1F, 0x00, // ###### ##### + 0x7E, 0x1F, 0x00, // ###### ##### + 0x18, 0x0C, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x06, 0x30, 0x00, // ## ## + 0x03, 0x60, 0x00, // ## ## + 0x03, 0xE0, 0x00, // ##### + 0x01, 0xC0, 0x00, // ### + 0x00, 0xC0, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x3F, 0xC0, 0x00, // ######## + 0x3F, 0xC0, 0x00, // ######## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6480 'z' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x18, 0x30, 0x00, // ## ## + 0x18, 0x60, 0x00, // ## ## + 0x00, 0xC0, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x00, 0x00, // ## + 0x06, 0x18, 0x00, // ## ## + 0x0C, 0x18, 0x00, // ## ## + 0x1F, 0xF8, 0x00, // ########## + 0x1F, 0xF8, 0x00, // ########## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6552 '{' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0xE0, 0x00, // ### + 0x01, 0xE0, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x03, 0x80, 0x00, // ### + 0x07, 0x00, 0x00, // ### + 0x03, 0x80, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0xE0, 0x00, // #### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6624 '|' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6696 '}' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x07, 0x00, 0x00, // ### + 0x07, 0x80, 0x00, // #### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0xC0, 0x00, // ### + 0x00, 0xE0, 0x00, // ### + 0x01, 0xC0, 0x00, // ### + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x01, 0x80, 0x00, // ## + 0x07, 0x80, 0x00, // #### + 0x07, 0x00, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + + // @6768 '~' (17 pixels wide) + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x0E, 0x00, 0x00, // ### + 0x1F, 0x18, 0x00, // ##### ## + 0x3B, 0xB8, 0x00, // ### ### ### + 0x31, 0xF0, 0x00, // ## ##### + 0x00, 0xE0, 0x00, // ### + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // + 0x00, 0x00, 0x00, // +}; + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/MyCode/Gui/font_5x8.cpp b/MyCode/Gui/font_5x8.cpp new file mode 100644 index 0000000..dd695db --- /dev/null +++ b/MyCode/Gui/font_5x8.cpp @@ -0,0 +1,1078 @@ +/** + ****************************************************************************** + * @file Font8.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text Font8 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text Font8 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +// +// Font data for Courier New 12pt +// + +const unsigned char font_5x8_table[] = +{ + // @0 ' ' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @8 '!' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @16 '"' (5 pixels wide) + 0x50, // # # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @24 '#' (5 pixels wide) + 0x28, // # # + 0x50, // # # + 0xF8, // ##### + 0x50, // # # + 0xF8, // ##### + 0x50, // # # + 0xA0, // # # + 0x00, // + + // @32 '$' (5 pixels wide) + 0x20, // # + 0x30, // ## + 0x60, // ## + 0x30, // ## + 0x10, // # + 0x60, // ## + 0x20, // # + 0x00, // + + // @40 '%' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x18, // ## + 0x60, // ## + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + + // @48 '&' (5 pixels wide) + 0x00, // + 0x38, // ### + 0x20, // # + 0x60, // ## + 0x50, // # # + 0x78, // #### + 0x00, // + 0x00, // + + // @56 ''' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @64 '(' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x10, // # + 0x00, // + + // @72 ')' (5 pixels wide) + 0x40, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x40, // # + 0x00, // + + // @80 '*' (5 pixels wide) + 0x20, // # + 0x70, // ### + 0x20, // # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @88 '+' (5 pixels wide) + 0x00, // + 0x20, // # + 0x20, // # + 0xF8, // ##### + 0x20, // # + 0x20, // # + 0x00, // + 0x00, // + + // @96 ',' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x10, // # + 0x20, // # + 0x20, // # + 0x00, // + + // @104 '-' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @112 '.' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @120 '/' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x40, // # + 0x40, // # + 0x80, // # + 0x00, // + + // @128 '0' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x50, // # # + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @136 '1' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0xF8, // ##### + 0x00, // + 0x00, // + + // @144 '2' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x20, // # + 0x20, // # + 0x40, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @152 '3' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x10, // # + 0x20, // # + 0x10, // # + 0x60, // ## + 0x00, // + 0x00, // + + // @160 '4' (5 pixels wide) + 0x10, // # + 0x30, // ## + 0x50, // # # + 0x78, // #### + 0x10, // # + 0x38, // ### + 0x00, // + 0x00, // + + // @168 '5' (5 pixels wide) + 0x70, // ### + 0x40, // # + 0x60, // ## + 0x10, // # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @176 '6' (5 pixels wide) + 0x30, // ## + 0x40, // # + 0x60, // ## + 0x50, // # # + 0x50, // # # + 0x60, // ## + 0x00, // + 0x00, // + + // @184 '7' (5 pixels wide) + 0x70, // ### + 0x50, // # # + 0x10, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + 0x00, // + + // @192 '8' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x20, // # + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @200 '9' (5 pixels wide) + 0x30, // ## + 0x50, // # # + 0x50, // # # + 0x30, // ## + 0x10, // # + 0x60, // ## + 0x00, // + 0x00, // + + // @208 ':' (5 pixels wide) + 0x00, // + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @216 ';' (5 pixels wide) + 0x00, // + 0x00, // + 0x10, // # + 0x00, // + 0x10, // # + 0x20, // # + 0x00, // + 0x00, // + + // @224 '<' (5 pixels wide) + 0x00, // + 0x10, // # + 0x20, // # + 0xC0, // ## + 0x20, // # + 0x10, // # + 0x00, // + 0x00, // + + // @232 '=' (5 pixels wide) + 0x00, // + 0x70, // ### + 0x00, // + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @240 '>' (5 pixels wide) + 0x00, // + 0x40, // # + 0x20, // # + 0x18, // ## + 0x20, // # + 0x40, // # + 0x00, // + 0x00, // + + // @248 '?' (5 pixels wide) + 0x20, // # + 0x50, // # # + 0x10, // # + 0x20, // # + 0x00, // + 0x20, // # + 0x00, // + 0x00, // + + // @256 '@' (5 pixels wide) + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x58, // # ## + 0x48, // # # + 0x40, // # + 0x38, // ### + 0x00, // + + // @264 'A' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x50, // # # + 0x70, // ### + 0x88, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @272 'B' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x70, // ### + 0x48, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + + // @280 'C' (5 pixels wide) + 0x70, // ### + 0x50, // # # + 0x40, // # + 0x40, // # + 0x40, // # + 0x30, // ## + 0x00, // + 0x00, // + + // @288 'D' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + + // @296 'E' (5 pixels wide) + 0xF8, // ##### + 0x48, // # # + 0x60, // ## + 0x40, // # + 0x48, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + + // @304 'F' (5 pixels wide) + 0xF8, // ##### + 0x48, // # # + 0x60, // ## + 0x40, // # + 0x40, // # + 0xE0, // ### + 0x00, // + 0x00, // + + // @312 'G' (5 pixels wide) + 0x70, // ### + 0x40, // # + 0x40, // # + 0x58, // # ## + 0x50, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @320 'H' (5 pixels wide) + 0xE8, // ### # + 0x48, // # # + 0x78, // #### + 0x48, // # # + 0x48, // # # + 0xE8, // ### # + 0x00, // + 0x00, // + + // @328 'I' (5 pixels wide) + 0x70, // ### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @336 'J' (5 pixels wide) + 0x38, // ### + 0x10, // # + 0x10, // # + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x00, // + 0x00, // + + // @344 'K' (5 pixels wide) + 0xD8, // ## ## + 0x50, // # # + 0x60, // ## + 0x70, // ### + 0x50, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @352 'L' (5 pixels wide) + 0xE0, // ### + 0x40, // # + 0x40, // # + 0x40, // # + 0x48, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + + // @360 'M' (5 pixels wide) + 0xD8, // ## ## + 0xD8, // ## ## + 0xD8, // ## ## + 0xA8, // # # # + 0x88, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @368 'N' (5 pixels wide) + 0xD8, // ## ## + 0x68, // ## # + 0x68, // ## # + 0x58, // # ## + 0x58, // # ## + 0xE8, // ### # + 0x00, // + 0x00, // + + // @376 'O' (5 pixels wide) + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @384 'P' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x70, // ### + 0x40, // # + 0xE0, // ### + 0x00, // + 0x00, // + + // @392 'Q' (5 pixels wide) + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x18, // ## + 0x00, // + + // @400 'R' (5 pixels wide) + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x70, // ### + 0x48, // # # + 0xE8, // ### # + 0x00, // + 0x00, // + + // @408 'S' (5 pixels wide) + 0x70, // ### + 0x50, // # # + 0x20, // # + 0x10, // # + 0x50, // # # + 0x70, // ### + 0x00, // + 0x00, // + + // @416 'T' (5 pixels wide) + 0xF8, // ##### + 0xA8, // # # # + 0x20, // # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @424 'U' (5 pixels wide) + 0xD8, // ## ## + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @432 'V' (5 pixels wide) + 0xD8, // ## ## + 0x88, // # # + 0x48, // # # + 0x50, // # # + 0x50, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @440 'W' (5 pixels wide) + 0xD8, // ## ## + 0x88, // # # + 0xA8, // # # # + 0xA8, // # # # + 0xA8, // # # # + 0x50, // # # + 0x00, // + 0x00, // + + // @448 'X' (5 pixels wide) + 0xD8, // ## ## + 0x50, // # # + 0x20, // # + 0x20, // # + 0x50, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @456 'Y' (5 pixels wide) + 0xD8, // ## ## + 0x88, // # # + 0x50, // # # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @464 'Z' (5 pixels wide) + 0x78, // #### + 0x48, // # # + 0x10, // # + 0x20, // # + 0x48, // # # + 0x78, // #### + 0x00, // + 0x00, // + + // @472 '[' (5 pixels wide) + 0x30, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x30, // ## + 0x00, // + + // @480 '\' (5 pixels wide) + 0x80, // # + 0x40, // # + 0x40, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x10, // # + 0x00, // + + // @488 ']' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x60, // ## + 0x00, // + + // @496 '^' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @504 '_' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0xF8, // ##### + + // @512 '`' (5 pixels wide) + 0x20, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @520 'a' (5 pixels wide) + 0x00, // + 0x00, // + 0x30, // ## + 0x10, // # + 0x70, // ### + 0x78, // #### + 0x00, // + 0x00, // + + // @528 'b' (5 pixels wide) + 0xC0, // ## + 0x40, // # + 0x70, // ### + 0x48, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + + // @536 'c' (5 pixels wide) + 0x00, // + 0x00, // + 0x70, // ### + 0x40, // # + 0x40, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @544 'd' (5 pixels wide) + 0x18, // ## + 0x08, // # + 0x38, // ### + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x00, // + 0x00, // + + // @552 'e' (5 pixels wide) + 0x00, // + 0x00, // + 0x70, // ### + 0x70, // ### + 0x40, // # + 0x30, // ## + 0x00, // + 0x00, // + + // @560 'f' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x70, // ### + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @568 'g' (5 pixels wide) + 0x00, // + 0x00, // + 0x38, // ### + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x08, // # + 0x30, // ## + + // @576 'h' (5 pixels wide) + 0xC0, // ## + 0x40, // # + 0x70, // ### + 0x48, // # # + 0x48, // # # + 0xE8, // ### # + 0x00, // + 0x00, // + + // @584 'i' (5 pixels wide) + 0x20, // # + 0x00, // + 0x60, // ## + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @592 'j' (5 pixels wide) + 0x20, // # + 0x00, // + 0x70, // ### + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x70, // ### + + // @600 'k' (5 pixels wide) + 0xC0, // ## + 0x40, // # + 0x58, // # ## + 0x70, // ### + 0x50, // # # + 0xD8, // ## ## + 0x00, // + 0x00, // + + // @608 'l' (5 pixels wide) + 0x60, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @616 'm' (5 pixels wide) + 0x00, // + 0x00, // + 0xD0, // ## # + 0xA8, // # # # + 0xA8, // # # # + 0xA8, // # # # + 0x00, // + 0x00, // + + // @624 'n' (5 pixels wide) + 0x00, // + 0x00, // + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0xC8, // ## # + 0x00, // + 0x00, // + + // @632 'o' (5 pixels wide) + 0x00, // + 0x00, // + 0x30, // ## + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @640 'p' (5 pixels wide) + 0x00, // + 0x00, // + 0xF0, // #### + 0x48, // # # + 0x48, // # # + 0x70, // ### + 0x40, // # + 0xE0, // ### + + // @648 'q' (5 pixels wide) + 0x00, // + 0x00, // + 0x38, // ### + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x08, // # + 0x18, // ## + + // @656 'r' (5 pixels wide) + 0x00, // + 0x00, // + 0x78, // #### + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + + // @664 's' (5 pixels wide) + 0x00, // + 0x00, // + 0x30, // ## + 0x20, // # + 0x10, // # + 0x60, // ## + 0x00, // + 0x00, // + + // @672 't' (5 pixels wide) + 0x00, // + 0x40, // # + 0xF0, // #### + 0x40, // # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + + // @680 'u' (5 pixels wide) + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x48, // # # + 0x48, // # # + 0x38, // ### + 0x00, // + 0x00, // + + // @688 'v' (5 pixels wide) + 0x00, // + 0x00, // + 0xC8, // ## # + 0x48, // # # + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + + // @696 'w' (5 pixels wide) + 0x00, // + 0x00, // + 0xD8, // ## ## + 0xA8, // # # # + 0xA8, // # # # + 0x50, // # # + 0x00, // + 0x00, // + + // @704 'x' (5 pixels wide) + 0x00, // + 0x00, // + 0x48, // # # + 0x30, // ## + 0x30, // ## + 0x48, // # # + 0x00, // + 0x00, // + + // @712 'y' (5 pixels wide) + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x50, // # # + 0x50, // # # + 0x20, // # + 0x20, // # + 0x60, // ## + + // @720 'z' (5 pixels wide) + 0x00, // + 0x00, // + 0x78, // #### + 0x50, // # # + 0x28, // # # + 0x78, // #### + 0x00, // + 0x00, // + + // @728 '{' (5 pixels wide) + 0x10, // # + 0x20, // # + 0x20, // # + 0x60, // ## + 0x20, // # + 0x20, // # + 0x10, // # + 0x00, // + + // @736 '|' (5 pixels wide) + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x00, // + + // @744 '}' (5 pixels wide) + 0x40, // # + 0x20, // # + 0x20, // # + 0x30, // ## + 0x20, // # + 0x20, // # + 0x40, // # + 0x00, // + + // @752 '~' (5 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x28, // # # + 0x50, // # # + 0x00, // + 0x00, // + 0x00, // +}; + + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/MyCode/Gui/font_7x12.cpp b/MyCode/Gui/font_7x12.cpp new file mode 100644 index 0000000..6f01a0c --- /dev/null +++ b/MyCode/Gui/font_7x12.cpp @@ -0,0 +1,1459 @@ +/** + ****************************************************************************** + * @file Font12.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-February-2014 + * @brief This file provides text Font12 for STM32xx-EVAL's LCD driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ + + +/** @addtogroup Utilities + * @{ + */ + +/** @addtogroup STM32_EVAL + * @{ + */ + +/** @addtogroup Common + * @{ + */ + +/** @addtogroup FONTS + * @brief This file provides text Font12 for STM32xx-EVAL's LCD driver. + * @{ + */ + +/** @defgroup FONTS_Private_Types + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Defines + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Macros + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Variables + * @{ + */ +// +// Font data for Courier New 12pt +// +#include"my_font.h" +const unsigned char ascii_7x12_table[] = +{ + // @0 ' ' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @12 '!' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @24 '"' (7 pixels wide) + 0x00, // + 0x6C, // ## ## + 0x48, // # # + 0x48, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @36 '#' (7 pixels wide) + 0x00, // + 0x14, // # # + 0x14, // # # + 0x28, // # # + 0x7C, // ##### + 0x28, // # # + 0x7C, // ##### + 0x28, // # # + 0x50, // # # + 0x50, // # # + 0x00, // + 0x00, // + + // @48 '$' (7 pixels wide) + 0x00, // + 0x10, // # + 0x38, // ### + 0x40, // # + 0x40, // # + 0x38, // ### + 0x48, // # # + 0x70, // ### + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + + // @60 '%' (7 pixels wide) + 0x00, // + 0x20, // # + 0x50, // # # + 0x20, // # + 0x0C, // ## + 0x70, // ### + 0x08, // # + 0x14, // # # + 0x08, // # + 0x00, // + 0x00, // + 0x00, // + + // @72 '&' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x18, // ## + 0x20, // # + 0x20, // # + 0x54, // # # # + 0x48, // # # + 0x34, // ## # + 0x00, // + 0x00, // + 0x00, // + + // @84 ''' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @96 '(' (7 pixels wide) + 0x00, // + 0x08, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x08, // # + 0x00, // + + // @108 ')' (7 pixels wide) + 0x00, // + 0x20, // # + 0x20, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x20, // # + 0x00, // + + // @120 '*' (7 pixels wide) + 0x00, // + 0x10, // # + 0x7C, // ##### + 0x10, // # + 0x28, // # # + 0x28, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @132 '+' (7 pixels wide) + 0x00, // + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0xFE, // ####### + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @144 ',' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x18, // ## + 0x10, // # + 0x30, // ## + 0x20, // # + 0x00, // + + // @156 '-' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @168 '.' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @180 '/' (7 pixels wide) + 0x00, // + 0x04, // # + 0x04, // # + 0x08, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x20, // # + 0x40, // # + 0x00, // + 0x00, // + + // @192 '0' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @204 '1' (7 pixels wide) + 0x00, // + 0x30, // ## + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @216 '2' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x04, // # + 0x08, // # + 0x10, // # + 0x20, // # + 0x44, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @228 '3' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x04, // # + 0x18, // ## + 0x04, // # + 0x04, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @240 '4' (7 pixels wide) + 0x00, // + 0x0C, // ## + 0x14, // # # + 0x14, // # # + 0x24, // # # + 0x44, // # # + 0x7E, // ###### + 0x04, // # + 0x0E, // ### + 0x00, // + 0x00, // + 0x00, // + + // @252 '5' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x20, // # + 0x20, // # + 0x38, // ### + 0x04, // # + 0x04, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @264 '6' (7 pixels wide) + 0x00, // + 0x1C, // ### + 0x20, // # + 0x40, // # + 0x78, // #### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @276 '7' (7 pixels wide) + 0x00, // + 0x7C, // ##### + 0x44, // # # + 0x04, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @288 '8' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @300 '9' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3C, // #### + 0x04, // # + 0x08, // # + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + + // @312 ':' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + 0x30, // ## + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @324 ';' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x18, // ## + 0x18, // ## + 0x00, // + 0x00, // + 0x18, // ## + 0x30, // ## + 0x20, // # + 0x00, // + 0x00, // + + // @336 '<' (7 pixels wide) + 0x00, // + 0x00, // + 0x0C, // ## + 0x10, // # + 0x60, // ## + 0x80, // # + 0x60, // ## + 0x10, // # + 0x0C, // ## + 0x00, // + 0x00, // + 0x00, // + + // @348 '=' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x7C, // ##### + 0x00, // + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @360 '>' (7 pixels wide) + 0x00, // + 0x00, // + 0xC0, // ## + 0x20, // # + 0x18, // ## + 0x04, // # + 0x18, // ## + 0x20, // # + 0xC0, // ## + 0x00, // + 0x00, // + 0x00, // + + // @372 '?' (7 pixels wide) + 0x00, // + 0x00, // + 0x18, // ## + 0x24, // # # + 0x04, // # + 0x08, // # + 0x10, // # + 0x00, // + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @384 '@' (7 pixels wide) + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x4C, // # ## + 0x54, // # # # + 0x54, // # # # + 0x4C, // # ## + 0x40, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + + // @396 'A' (7 pixels wide) + 0x00, // + 0x30, // ## + 0x10, // # + 0x28, // # # + 0x28, // # # + 0x28, // # # + 0x7C, // ##### + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @408 'B' (7 pixels wide) + 0x00, // + 0xF8, // ##### + 0x44, // # # + 0x44, // # # + 0x78, // #### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @420 'C' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x40, // # + 0x40, // # + 0x40, // # + 0x40, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @432 'D' (7 pixels wide) + 0x00, // + 0xF0, // #### + 0x48, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x48, // # # + 0xF0, // #### + 0x00, // + 0x00, // + 0x00, // + + // @444 'E' (7 pixels wide) + 0x00, // + 0xFC, // ###### + 0x44, // # # + 0x50, // # # + 0x70, // ### + 0x50, // # # + 0x40, // # + 0x44, // # # + 0xFC, // ###### + 0x00, // + 0x00, // + 0x00, // + + // @456 'F' (7 pixels wide) + 0x00, // + 0x7E, // ###### + 0x22, // # # + 0x28, // # # + 0x38, // ### + 0x28, // # # + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + + // @468 'G' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x40, // # + 0x40, // # + 0x4E, // # ### + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @480 'H' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x7C, // ##### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @492 'I' (7 pixels wide) + 0x00, // + 0x7C, // ##### + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @504 'J' (7 pixels wide) + 0x00, // + 0x3C, // #### + 0x08, // # + 0x08, // # + 0x08, // # + 0x48, // # # + 0x48, // # # + 0x48, // # # + 0x30, // ## + 0x00, // + 0x00, // + 0x00, // + + // @516 'K' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x48, // # # + 0x50, // # # + 0x70, // ### + 0x48, // # # + 0x44, // # # + 0xE6, // ### ## + 0x00, // + 0x00, // + 0x00, // + + // @528 'L' (7 pixels wide) + 0x00, // + 0x70, // ### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x24, // # # + 0x24, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @540 'M' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x6C, // ## ## + 0x6C, // ## ## + 0x54, // # # # + 0x54, // # # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @552 'N' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x64, // ## # + 0x64, // ## # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x4C, // # ## + 0xEC, // ### ## + 0x00, // + 0x00, // + 0x00, // + + // @564 'O' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @576 'P' (7 pixels wide) + 0x00, // + 0x78, // #### + 0x24, // # # + 0x24, // # # + 0x24, // # # + 0x38, // ### + 0x20, // # + 0x20, // # + 0x70, // ### + 0x00, // + 0x00, // + 0x00, // + + // @588 'Q' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x1C, // ### + 0x00, // + 0x00, // + + // @600 'R' (7 pixels wide) + 0x00, // + 0xF8, // ##### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x78, // #### + 0x48, // # # + 0x44, // # # + 0xE2, // ### # + 0x00, // + 0x00, // + 0x00, // + + // @612 'S' (7 pixels wide) + 0x00, // + 0x34, // ## # + 0x4C, // # ## + 0x40, // # + 0x38, // ### + 0x04, // # + 0x04, // # + 0x64, // ## # + 0x58, // # ## + 0x00, // + 0x00, // + 0x00, // + + // @624 'T' (7 pixels wide) + 0x00, // + 0xFE, // ####### + 0x92, // # # # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @636 'U' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @648 'V' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x28, // # # + 0x28, // # # + 0x28, // # # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @660 'W' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x28, // # # + 0x00, // + 0x00, // + 0x00, // + + // @672 'X' (7 pixels wide) + 0x00, // + 0xC6, // ## ## + 0x44, // # # + 0x28, // # # + 0x10, // # + 0x10, // # + 0x28, // # # + 0x44, // # # + 0xC6, // ## ## + 0x00, // + 0x00, // + 0x00, // + + // @684 'Y' (7 pixels wide) + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x28, // # # + 0x28, // # # + 0x10, // # + 0x10, // # + 0x10, // # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @696 'Z' (7 pixels wide) + 0x00, // + 0x7C, // ##### + 0x44, // # # + 0x08, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x44, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @708 '[' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x38, // ### + 0x00, // + + // @720 '\' (7 pixels wide) + 0x00, // + 0x40, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x00, // + 0x00, // + + // @732 ']' (7 pixels wide) + 0x00, // + 0x38, // ### + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x38, // ### + 0x00, // + + // @744 '^' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x28, // # # + 0x44, // # # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @756 '_' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0xFE, // ####### + + // @768 '`' (7 pixels wide) + 0x00, // + 0x10, // # + 0x08, // # + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + + // @780 'a' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x38, // ### + 0x44, // # # + 0x3C, // #### + 0x44, // # # + 0x44, // # # + 0x3E, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @792 'b' (7 pixels wide) + 0x00, // + 0xC0, // ## + 0x40, // # + 0x58, // # ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xF8, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @804 'c' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x40, // # + 0x40, // # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @816 'd' (7 pixels wide) + 0x00, // + 0x0C, // ## + 0x04, // # + 0x34, // ## # + 0x4C, // # ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3E, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @828 'e' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x38, // ### + 0x44, // # # + 0x7C, // ##### + 0x40, // # + 0x40, // # + 0x3C, // #### + 0x00, // + 0x00, // + 0x00, // + + // @840 'f' (7 pixels wide) + 0x00, // + 0x1C, // ### + 0x20, // # + 0x7C, // ##### + 0x20, // # + 0x20, // # + 0x20, // # + 0x20, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @852 'g' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x36, // ## ## + 0x4C, // # ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3C, // #### + 0x04, // # + 0x38, // ### + 0x00, // + + // @864 'h' (7 pixels wide) + 0x00, // + 0xC0, // ## + 0x40, // # + 0x58, // # ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @876 'i' (7 pixels wide) + 0x00, // + 0x10, // # + 0x00, // + 0x70, // ### + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @888 'j' (7 pixels wide) + 0x00, // + 0x10, // # + 0x00, // + 0x78, // #### + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x08, // # + 0x70, // ### + 0x00, // + + // @900 'k' (7 pixels wide) + 0x00, // + 0xC0, // ## + 0x40, // # + 0x5C, // # ### + 0x48, // # # + 0x70, // ### + 0x50, // # # + 0x48, // # # + 0xDC, // ## ### + 0x00, // + 0x00, // + 0x00, // + + // @912 'l' (7 pixels wide) + 0x00, // + 0x30, // ## + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @924 'm' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xE8, // ### # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0xFE, // ####### + 0x00, // + 0x00, // + 0x00, // + + // @936 'n' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0xEE, // ### ### + 0x00, // + 0x00, // + 0x00, // + + // @948 'o' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x38, // ### + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x38, // ### + 0x00, // + 0x00, // + 0x00, // + + // @960 'p' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xD8, // ## ## + 0x64, // ## # + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x78, // #### + 0x40, // # + 0xE0, // ### + 0x00, // + + // @972 'q' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x36, // ## ## + 0x4C, // # ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x3C, // #### + 0x04, // # + 0x0E, // ### + 0x00, // + + // @984 'r' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x6C, // ## ## + 0x30, // ## + 0x20, // # + 0x20, // # + 0x20, // # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @996 's' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x3C, // #### + 0x44, // # # + 0x38, // ### + 0x04, // # + 0x44, // # # + 0x78, // #### + 0x00, // + 0x00, // + 0x00, // + + // @1008 't' (7 pixels wide) + 0x00, // + 0x00, // + 0x20, // # + 0x7C, // ##### + 0x20, // # + 0x20, // # + 0x20, // # + 0x22, // # # + 0x1C, // ### + 0x00, // + 0x00, // + 0x00, // + + // @1020 'u' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xCC, // ## ## + 0x44, // # # + 0x44, // # # + 0x44, // # # + 0x4C, // # ## + 0x36, // ## ## + 0x00, // + 0x00, // + 0x00, // + + // @1032 'v' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x44, // # # + 0x28, // # # + 0x28, // # # + 0x10, // # + 0x00, // + 0x00, // + 0x00, // + + // @1044 'w' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x54, // # # # + 0x54, // # # # + 0x54, // # # # + 0x28, // # # + 0x00, // + 0x00, // + 0x00, // + + // @1056 'x' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xCC, // ## ## + 0x48, // # # + 0x30, // ## + 0x30, // ## + 0x48, // # # + 0xCC, // ## ## + 0x00, // + 0x00, // + 0x00, // + + // @1068 'y' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0xEE, // ### ### + 0x44, // # # + 0x24, // # # + 0x28, // # # + 0x18, // ## + 0x10, // # + 0x10, // # + 0x78, // #### + 0x00, // + + // @1080 'z' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x7C, // ##### + 0x48, // # # + 0x10, // # + 0x20, // # + 0x44, // # # + 0x7C, // ##### + 0x00, // + 0x00, // + 0x00, // + + // @1092 '{' (7 pixels wide) + 0x00, // + 0x08, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x00, // + + // @1104 '|' (7 pixels wide) + 0x00, // + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x00, // + 0x00, // + + // @1116 '}' (7 pixels wide) + 0x00, // + 0x20, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x08, // # + 0x10, // # + 0x10, // # + 0x10, // # + 0x20, // # + 0x00, // + + // @1128 '~' (7 pixels wide) + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x24, // # # + 0x58, // # ## + 0x00, // + 0x00, // + 0x00, // + 0x00, // + 0x00, // +}; + + +/** + * @} + */ + + +/** @defgroup FONTS_Private_Function_Prototypes + * @{ + */ +/** + * @} + */ + + +/** @defgroup FONTS_Private_Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/MyCode/Gui/gvalue.c b/MyCode/Gui/gvalue.c new file mode 100644 index 0000000..3f0afb2 --- /dev/null +++ b/MyCode/Gui/gvalue.c @@ -0,0 +1,2039 @@ +#include "gvalue.h" + + +TUartBuf uart1; + +TGuiState GuiState, GuiStateBAK; +unsigned char ActList_0; +unsigned char ActList_1; +unsigned char ActList_2; +unsigned char ActList_3; +unsigned char ActList_4; +unsigned char ActList_5; +unsigned char ActList_6; +unsigned char ActList_7; +unsigned char ActList_8; +unsigned char ActList_9; +unsigned char ActList_10; + +void Clear(void) +{ + uart1.Rx.Rdy=0; +} + +void GlobalValue_init(void) +{ + GuiState = guiIdle; + GuiStateBAK = guiIdle; + + //ActList_0 = +} + +const char CharLinkage[16] = {' ', 'Y', '=', '(', '-', ')', '+', '&', 'S', '*', ' '}; +const char CharBusPadProgram[16] = {' ', 'Y', '=', '(', '-', ')', '+', '&', 'S', '*', ' '}; + +const char StrHwType[256][32]= { +//0 + "未定义", // 0 国标预留 + "未定义",// 1 + "未定义", // 2 + "未定义", // 3 + "未定义", // 4 国标预留 + "未定义", // 5 未使用 + "未定义", // 6 未使用 + "未定义", // 7 未使用 + "未定义", // 8 未使用 + "未定义", // 9 未使用 + "火灾显示盘", // 10 + "未定义", // 11 + "未定义", // 12 + "未定义", // 13 + "未定义", // 14 + "未定义", // 15 + "未定义", // 16 + "未定义", // 17 + "未定义", // 18 + "未定义", // 19 国标预留 + "未定义", // 20 + "未定义", // 21 + "未定义", // 22 + "点型光电烟感", // 23 + "未定义", // 24 + "未定义", // 25 + "未定义", // 26 国标预留 + "未定义", // 27 未使用 + "未定义", // 28 未使用 + "未定义", // 29 未使用 + "未定义", // 30 + "点型温感", // 31 + "未定义", // 32 + "未定义", // 33 + "未定义", // 34 + "未定义", // 35 + "未定义", // 36 国标预留 + "未定义", // 37 未使用 + "未定义", // 38 未使用 + "未定义", // 39 未使用 + "未定义", // 40 + "未定义", // 41 + "未定义", // 42 + "未定义", // 43 + "未定义", // 44 国标预留 + "未定义", // 45 未使用 + "未定义", // 46 未使用 + "未定义", // 47 未使用 + "未定义", // 48 未使用 + "未定义", // 49 未使用 + "未定义", // 50 + "未定义", // 51 + "未定义", // 52 + "未定义", // 53 + "未定义", // 54 国标预留 + "未定义", // 55 未使用 + "未定义", // 56 未使用 + "未定义", // 57 未使用 + "未定义", // 58 未使用 + "未定义", // 59 未使用 + "未定义", // 60 未使用 + "手动报警按钮", // 61 + "消火栓按钮", // 62 + "未定义", // 63 + "未定义", // 64 + "未定义", // 65 国标预留 + "未定义", // 66 未使用 + "未定义", // 67 未使用 + "未定义", // 68 未使用 + "未定义", // 69 未使用 + "未定义", // 70 未使用 + "未定义", // 71 + "输入模块", // 72 + "输出模块", // 73 + "输入输出模块", // 74 + "中继模块", // 75 + "未定义", // 76 + "未定义", // 77 国标预留 + "未定义", // 78 未使用 + "未定义", // 79 未使用 + "未定义", // 80 未使用 + "未定义", // 81 + "声光警报器", // 82 + "未定义", // 83 + "未定义", // 84 + "未定义", // 85 + "未定义", // 86 + "未定义", // 87 国标预留 + "未定义", // 88 未使用 + "未定义", // 89 未使用 + "未定义", // 90 未使用 + "未定义", // 91 未使用 + "未定义", // 92 未使用 + "未定义", // 93 未使用 + "未定义", // 94 未使用 + "未定义", // 95 未使用 + "未定义", // 96 未使用 + "未定义", // 97 未使用 + "未定义", // 98 未使用 + "未定义", // 99 未使用 + "未定义", // 100 + "未定义", // 101 + "未定义", // 102 + "未定义", // 103 + "未定义", // 104 国标预留 + "未定义", // 105 未使用 + "未定义", // 106 未使用 + "未定义", // 107 未使用 + "未定义", // 108 未使用 + "未定义", // 109 未使用 + "未定义", // 110 + "未定义", // 111 + "未定义", // 112 + "未定义", // 113 + "未定义", // 114 + "未定义", // 115 国标预留 + "未定义", // 116 未使用 + "未定义", // 117 未使用 + "未定义", // 118 未使用 + "未定义", // 119 未使用 + "未定义", // 120 + "未定义", // 121 + "未定义", // 122 + "未定义", // 123 + "未定义", // 124 + "未定义", // 125 国标预留 + "未定义", // 126 未使用 + "未定义", // 127 未使用 + "未定义", // 128 未使用 + "未定义", // 129 未使用 + "未定义", // 130 + "未定义", // 131 + "未定义", // 132 + "未定义", // 133 + "未定义", // 134 + "未定义", // 135 + "未定义", // 136 国标预留 + "未定义", // 137 未使用 + "未定义", // 138 未使用 + "未定义", // 139 未使用 + "未定义", // 140 + "未定义", // 141 + "未定义", // 142 + "未定义",// 143 + "未定义", // 144 国标预留 + "未定义", // 145 未使用 + "未定义", // 146 未使用 + "未定义", // 147 未使用 + "未定义", // 148 未使用 + "未定义", // 149 未使用 + "未定义", // 150 + "未定义", // 151 + "未定义", // 152 + "未定义", // 153 + "未定义", // 154 + "未定义", // 155 + "未定义", // 156 + "未定义", // 157 + "未定义", // 158 + "未定义", // 159 + "未定义",// 160 + "未定义", // 161 + "未定义", // 162 + "未定义", // 163 + "未定义", // 164 国标预留 + "未定义", // 165 未使用 + "未定义", // 166 未使用 + "未定义", // 167 未使用 + "未定义", // 168 未使用 + "未定义", // 169 未使用 + "未定义", // 170 未使用 + "未定义", // 171 未使用 + "未定义", // 172 未使用 + "未定义", // 173 未使用 + "未定义", // 174 未使用 + "未定义", // 175 未使用 + "未定义", // 176 未使用 + "未定义", // 177 未使用 + "未定义", // 178 未使用 + "未定义", // 179 + "未定义", // 180 + "未定义", // 181 + "未定义", // 182 + "未定义", // 183 + "未定义", // 184 + "未定义", // 185 + "未定义", // 186 + "未定义", // 187 + "未定义", // 188 + "未定义", // 189 + "未定义", // 190 + "未定义", // 191 + "未定义", // 192 + "未定义", // 193 + "未定义", // 194 + "未定义", // 195 + "未定义", // 196 + "未定义", // 197 + "未定义", // 198 + "未定义", // 199 + "未定义", // 200 + "未定义", // 201 + "未定义", // 202 + "未定义", // 203 + "未定义", // 204 + "未定义", // 205 + "未定义", // 206 + "未定义", // 207 + "未定义", // 208 + "未定义", // 209 + "未定义", // 210 + "未定义", // 211 未使用 + "未定义", // 212 未使用 + "未定义", // 213 未使用 + "未定义", // 214 未使用 + "未定义", // 215 未使用 + "未定义", // 216 未使用 + "未定义", // 217 未使用 + "未定义", // 218 未使用 + "未定义", // 219 未使用 + "未定义", // 220 未使用 + "未定义", // 221 + "未定义", // 222 + "未定义", // 223 + "未定义", // 224 + "烟温一体", // 225 + "未定义", // 226 + "未定义", // 227 + "未定义", // 228 + "未定义", // 229 + "有源输入输出", // 230 + "未定义", // 231 + "未定义", // 232 + "未定义", // 233 + "未定义", // 234 + "未定义", // 235 + "未定义", // 236 + "未定义", // 237 + "未定义", // 238 + "未定义", // 239 + "未定义", // 240 + "未定义", // 241 + "未定义", // 242 + "未定义", // 243 + "未定义", // 244 + "联动电源", // 245 + "未定义", // 246 + "未定义", // 247 + "未定义", // 248 + "未定义", // 249 + "未定义", // 250 + "未定义", // 251 未使用 + "未定义", // 252 未使用 + "未定义", // 253 未使用 + "未定义", // 254 未使用 + "未定义" // 255 未使用 +}; + +const char StrHwTypeEn[256][32] = { + "undefine", // 0 国标预留 + "undefine", // 1 + "undefine", // 2 + "undefine", // 3 + "undefine", // 4 国标预留 + "undefine", // 5 未使用 + "undefine", // 6 未使用 + "undefine", // 7 未使用 + "undefine", // 8 未使用 + "undefine", // 9 未使用 + "FireDisplay", // 10 火灾显示盘 + "undefine", // 11 + "undefine", // 12 + "undefine", // 13 + "undefine", // 14 + "undefine", // 15 + "undefine", // 16 + "undefine", // 17 + "undefine", // 18 + "undefine", // 19 国标预留 + "undefine", // 20 + "undefine", // 21 + "undefine", // 22 + "SmokeDet", // 23 点型光电烟感 + "undefine", // 24 + "undefine", // 25 + "undefine", // 26 国标预留 + "undefine", // 27 未使用 + "undefine", // 28 未使用 + "undefine", // 29 未使用 + "undefine", // 30 + "TempeDet", // 31 点型温感 + "undefine", // 32 + "undefine", // 33 + "undefine", // 34 + "undefine", // 35 + "undefine", // 36 国标预留 + "undefine", // 37 未使用 + "undefine", // 38 未使用 + "undefine", // 39 未使用 + "undefine", // 40 + "undefine", // 41 + "undefine", // 42 + "undefine", // 43 + "undefine", // 44 国标预留 + "undefine", // 45 未使用 + "undefine", // 46 未使用 + "undefine", // 47 未使用 + "undefine", // 48 未使用 + "undefine", // 49 未使用 + "undefine", // 50 + "undefine", // 51 + "undefine", // 52 + "undefine", // 53 + "undefine", // 54 国标预留 + "undefine", // 55 未使用 + "undefine", // 56 未使用 + "undefine", // 57 未使用 + "undefine", // 58 未使用 + "undefine", // 59 未使用 + "undefine", // 60 未使用 + "AlarmBtn", // 61 手动报警按钮 + "HydrantBtn", // 62 消火栓按钮 + "undefine", // 63 + "undefine", // 64 + "undefine", // 65 国标预留 + "undefine", // 66 未使用 + "undefine", // 67 未使用 + "undefine", // 68 未使用 + "undefine", // 69 未使用 + "undefine", // 70 未使用 + "undefine", // 71 + "InputModule", // 72 输入模块 + "OutputModule", // 73 输出模块 + "In/OutModule", // 74 输入输出模块 + "RelayModule", // 75 中继模块 + "undefine", // 76 + "undefine", // 77 国标预留 + "undefine", // 78 未使用 + "undefine", // 79 未使用 + "undefine", // 80 未使用 + "undefine", // 81 + "Acoustooptic", // 82 火灾声光警报器 + "undefine", // 83 + "undefine", // 84 + "undefine", // 85 + "undefine", // 86 + "undefine", // 87 国标预留 + "undefine", // 88 未使用 + "undefine", // 89 未使用 + "undefine", // 90 未使用 + "undefine", // 91 未使用 + "undefine", // 92 未使用 + "undefine", // 93 未使用 + "undefine", // 94 未使用 + "undefine", // 95 未使用 + "undefine", // 96 未使用 + "undefine", // 97 未使用 + "undefine", // 98 未使用 + "undefine", // 99 未使用 + "undefine", // 100 + "undefine", // 101 + "undefine", // 102 + "undefine", // 103 + "undefine", // 104 国标预留 + "undefine", // 105 未使用 + "undefine", // 106 未使用 + "undefine", // 107 未使用 + "undefine", // 108 未使用 + "undefine", // 109 未使用 + "undefine", // 110 + "undefine", // 111 + "undefine", // 112 + "undefine", // 113 + "undefine", // 114 + "undefine", // 115 国标预留 + "undefine", // 116 未使用 + "undefine", // 117 未使用 + "undefine", // 118 未使用 + "undefine", // 119 未使用 + "undefine", // 120 + "undefine", // 121 + "undefine", // 122 + "undefine", // 123 + "undefine", // 124 + "undefine", // 125 国标预留 + "undefine", // 126 未使用 + "undefine", // 127 未使用 + "undefine", // 128 未使用 + "undefine", // 129 未使用 + "undefine", // 130 + "undefine", // 131 + "undefine", // 132 + "undefine", // 133 + "undefine", // 134 + "undefine", // 135 + "undefine", // 136 国标预留 + "undefine", // 137 未使用 + "undefine", // 138 未使用 + "undefine", // 139 未使用 + "undefine", // 140 + "undefine", // 141 + "undefine", // 142 + "undefine", // 143 + "undefine", // 144 国标预留 + "undefine", // 145 未使用 + "undefine", // 146 未使用 + "undefine", // 147 未使用 + "undefine", // 148 未使用 + "undefine", // 149 未使用 + "undefine", // 150 + "undefine", // 151 + "undefine", // 152 + "undefine", // 153 + "undefine", // 154 + "undefine", // 155 + "undefine", // 156 + "undefine", // 157 + "undefine", // 158 + "undefine", // 159 + "undefine", // 160 + "undefine", // 161 + "undefine", // 162 + "undefine", // 163 + "undefine", // 164 国标预留 + "undefine", // 165 未使用 + "undefine", // 166 未使用 + "undefine", // 167 未使用 + "undefine", // 168 未使用 + "undefine", // 169 未使用 + "undefine", // 170 未使用 + "undefine", // 171 未使用 + "undefine", // 172 未使用 + "undefine", // 173 未使用 + "undefine", // 174 未使用 + "undefine", // 175 未使用 + "undefine", // 176 未使用 + "undefine", // 177 未使用 + "undefine", // 178 未使用 + "undefine", // 179 + "undefine", // 180 + "undefine", // 181 + "undefine", // 182 + "undefine", // 183 + "undefine", // 184 + "undefine", // 185 + "undefine", // 186 + "undefine", // 187 + "undefine", // 188 + "undefine", // 189 + "undefine", // 190 + "undefine", // 191 + "undefine", // 192 + "undefine", // 193 + "undefine", // 194 + "undefine", // 195 + "undefine", // 196 + "undefine", // 197 + "undefine", // 198 + "undefine", // 199 + "undefine", // 200 + "undefine", // 201 + "undefine", // 202 + "undefine", // 203 + "undefine", // 204 + "undefine", // 205 + "undefine", // 206 + "undefine", // 207 + "undefine", // 208 + "undefine", // 209 + "undefine", // 210 + "undefine", // 211 未使用 + "undefine", // 212 未使用 + "undefine", // 213 未使用 + "undefine", // 214 未使用 + "undefine", // 215 未使用 + "undefine", // 216 未使用 + "undefine", // 217 未使用 + "undefine", // 218 未使用 + "undefine", // 219 未使用 + "undefine", // 220 未使用 + "undefine", // 221 + "undefine", // 222 + "undefine", // 223 + "undefine", // 224 + "SmokeHeatDet", // 225 烟温一体 + "undefine", // 226 + "undefine", // 227 + "undefine", // 228 + "undefine", // 229 + "SrcInOutMdl", // 230 + "undefine", // 231 + "undefine", // 232 + "undefine", // 233 + "undefine", // 234 + "undefine", // 235 + "undefine", // 236 + "undefine", // 237 + "undefine", // 238 + "undefine", // 239 + "undefine", // 240 + "undefine", // 241 + "undefine", // 242 + "undefine", // 243 + "undefine", // 244 + "LinkPower", // 245 联动电源 + "undefine", // 246 + "undefine", // 247 + "undefine", // 248 + "undefine", // 249 + "undefine", // 250 + "undefine", // 251 未使用 + "undefine", // 252 未使用 + "undefine", // 253 未使用 + "undefine", // 254 未使用 + "undefine" // 255 未使用 +}; + + +const char StrRootType[16][32] ={ + "未定义", + "回路", + "总线盘", + "多线盘", + "回路母板", + "通信模块", + "未定义1", + "未定义2", + + "未定义3", + "未定义2", + "未定义4", + "未定义5", + "未定义6", + "未定义7", + "未定义8", + "未定义9" +}; + +const char StrType[256][32]= { + //0 + "未定义", // 0 国标预留 + "控制器",// 1 + "消防联动控制器", // 2 + "消防图形显示装置", // 3 + "未定义", // 4 国标预留 + "未定义", // 5 未使用 + "未定义", // 6 未使用 + "未定义", // 7 未使用 + "未定义", // 8 未使用 + "未定义", // 9 未使用 + "火灾显示盘", // 10 + "探测回路", // 11 + "控制回路", // 12 + "探测与控制复合回路", // 13 + "主电源", // 14 + "备用电源", // 15 + "充电电路", // 16 + "声光警报回路", // 17 + "运行数据存储单元", // 18 + "未定义", // 19 国标预留 + "火灾探测器", // 20 + "感烟火灾探测器", // 21 + "点型离子感烟火灾探测器", // 22 + "点型光电感烟火灾探测器", // 23 + "线型光束感烟火灾探测器", // 24 + "吸气式感烟火灾探测器", // 25 + "未定义", // 26 国标预留 + "未定义", // 27 未使用 + "未定义", // 28 未使用 + "未定义", // 29 未使用 + "感温火灾探测器", // 30 + "点型感温火灾探测器", // 31 + "线型感温火灾探测器", // 32 + "缆式线型火灾探测器", // 33 + "空气管式线型火灾探测器", // 34 + "线型光纤感温火灾探测器", // 35 + "未定义", // 36 国标预留 + "未定义", // 37 未使用 + "未定义", // 38 未使用 + "未定义", // 39 未使用 + "火焰探测器", // 40 + "点型红外火焰探测器", // 41 + "点型紫外火焰探测器", // 42 + "点型红外紫外火焰探测器", // 43 + "未定义", // 44 国标预留 + "未定义", // 45 未使用 + "未定义", // 46 未使用 + "未定义", // 47 未使用 + "未定义", // 48 未使用 + "未定义", // 49 未使用 + "多传感复合探测器", // 50 + "感光火灾探测器", // 51 + "图像型火灾探测器", // 52 + "点型CO火灾探测器", // 53 + "未定义", // 54 国标预留 + "未定义", // 55 未使用 + "未定义", // 56 未使用 + "未定义", // 57 未使用 + "未定义", // 58 未使用 + "未定义", // 59 未使用 + "未定义", // 60 未使用 + "手动火灾报警按钮", // 61 + "消火栓按钮", // 62 + "紧急启动按钮", // 63 + "紧急停止按钮", // 64 + "未定义", // 65 国标预留 + "未定义", // 66 未使用 + "未定义", // 67 未使用 + "未定义", // 68 未使用 + "未定义", // 69 未使用 + "未定义", // 70 未使用 + "模块", // 71 + "输入模块", // 72 + "输出模块", // 73 + "输入/输出模块", // 74 + "中继模块", // 75 + "短路隔离器", // 76 + "未定义", // 77 国标预留 + "未定义", // 78 未使用 + "未定义", // 79 未使用 + "未定义", // 80 未使用 + "火灾警报装置", // 81 + "火灾声光警报器", // 82 + "火灾声警报器", // 83 + "火灾光警报器", // 84 + "气体释放警报器", // 85 + "警铃", // 86 + "未定义", // 87 国标预留 + "未定义", // 88 未使用 + "未定义", // 89 未使用 + "未定义", // 90 未使用 + "未定义", // 91 未使用 + "未定义", // 92 未使用 + "未定义", // 93 未使用 + "未定义", // 94 未使用 + "未定义", // 95 未使用 + "未定义", // 96 未使用 + "未定义", // 97 未使用 + "未定义", // 98 未使用 + "未定义", // 99 未使用 + "可燃气体报警控制器", // 100 + "可燃气体探测器", // 101 + "点型可燃气体探测器", // 102 + "线型可燃气体探测器", // 103 + "未定义", // 104 国标预留 + "未定义", // 105 未使用 + "未定义", // 106 未使用 + "未定义", // 107 未使用 + "未定义", // 108 未使用 + "未定义", // 109 未使用 + "电气火灾监控设备", // 110 + "电气火灾监控探测器", // 111 + "剩余电流式电气监控探测器", // 112 + "测温式电气火灾监控探测器", // 113 + "故障电弧探测装置", // 114 + "未定义", // 115 国标预留 + "未定义", // 116 未使用 + "未定义", // 117 未使用 + "未定义", // 118 未使用 + "未定义", // 119 未使用 + "应急照明控制器", // 120 + "消防应急标志灯具", // 121 + "消防应急照明灯具", // 122 + "消防应急灯专用应急电源", // 123 + "应急照明分配电装置", // 124 + "未定义", // 125 国标预留 + "未定义", // 126 未使用 + "未定义", // 127 未使用 + "未定义", // 128 未使用 + "未定义", // 129 未使用 + "防火门监控器", // 130 + "常闭防火门", // 131 + "常开防火门", // 132 + "防火门电动闭门器", // 133 + "防火门电磁释放器", // 134 + "防火门门磁开关", // 135 + "未定义", // 136 国标预留 + "未定义", // 137 未使用 + "未定义", // 138 未使用 + "未定义", // 139 未使用 + "消防设备电源监控器", // 140 + "消防设备电源电压传感器", // 141 + "消防设备电源电流传感器", // 142 + "设备电源电压/电流传感器",// 143 + "未定义", // 144 国标预留 + "未定义", // 145 未使用 + "未定义", // 146 未使用 + "未定义", // 147 未使用 + "未定义", // 148 未使用 + "未定义", // 149 未使用 + "气体灭火控制器", // 150 + "泡沫灭火系统", // 151 + "干粉灭火系统", // 152 + "防烟排烟系统", // 153 + "防火卷帘控制器", // 154 + "挡烟垂壁控制装置", // 155 + "消防应急广播系统", // 156 + "消防电话主机", // 157 + "消防设备应急电源", // 158 + "传输设备", // 159 + "家用火灾控制中心监控设备",// 160 + "消防水位监视器", // 161 + "消防电梯", // 162 + "消防电气控制装置", // 163 + "未定义", // 164 国标预留 + "未定义", // 165 未使用 + "未定义", // 166 未使用 + "未定义", // 167 未使用 + "未定义", // 168 未使用 + "未定义", // 169 未使用 + "未定义", // 170 未使用 + "未定义", // 171 未使用 + "未定义", // 172 未使用 + "未定义", // 173 未使用 + "未定义", // 174 未使用 + "未定义", // 175 未使用 + "未定义", // 176 未使用 + "未定义", // 177 未使用 + "未定义", // 178 未使用 + "消防泵控制器", // 179 + "消防栓泵", // 180 + "水喷雾泵", // 181 + "细水雾泵", // 182 + "稳压泵", // 183 + "喷淋泵", // 184 + "雨淋泵", // 185 + "泡沫液泵", // 186 + "水流指示器", // 187 + "报警阀", // 188 + "压力开关", // 189 + "流量开关", // 190 + "阀驱动装置", // 191 + "电动防火阀", // 192 + "70℃防火阀", // 193 + "280℃防火阀", // 194 + "通风空调", // 195 + "管网电磁阀", // 196 + "防烟排烟风机", // 197 + "电动排烟防火阀", // 198 + "常闭送风口", // 199 + "排烟口", // 200 + "消防水炮", // 201 + "电动门", // 202 + "排烟机", // 203 + "送风机", // 204 + "电磁阀", // 205 + "照明配电", // 206 + "动力配电", // 207 + "空压机", // 208 + "阀门", // 209 + "配电箱", // 210 + "未定义", // 211 未使用 + "未定义", // 212 未使用 + "未定义", // 213 未使用 + "未定义", // 214 未使用 + "未定义", // 215 未使用 + "未定义", // 216 未使用 + "未定义", // 217 未使用 + "未定义", // 218 未使用 + "未定义", // 219 未使用 + "未定义", // 220 未使用 + "甲烷气体探测", // 221 + "丙烷气体探测", // 222 + "甲烷+CO探测", // 223 + "硫化氢气体探测", // 224 + "烟温一体", // 225 + "烟 CO复合", // 226 + "蜂鸣器底座", // 227 + "单门输入模块", // 228 + "双门输入模块", // 229 + "有源输入输出模块", // 230 + "广播模块", // 231 + "编码消防电话模块", // 232 + "编码防盗探测器接口", // 233 + "自动接口工业模块", // 234 + "门灯", // 235 + "防爆编码接口箱", // 236 + "感温电缆数据处理器", // 237 + "单路感温电气火灾报警器", // 238 + "1路感温+1路剩余电流", // 239 + "消防电源-三相监控", // 240 + "消防电源-两相监控", // 241 + "余压控制器", // 242 + "余压探测器", // 243 + "信号阀", // 244 + "联动电源", // 245 + "手动/自动状态指示灯", // 246 + "紧急启停按钮", // 247 + "多线控制盘", // 248 + "总线控制盘", // 249 + "气灭控制盘", // 250 + "联网接口卡", // 251 未使用 + "未定义", // 252 未使用 + "未定义", // 253 未使用 + "未定义", // 254 未使用 + "未定义" // 255 未使用 +}; + + +const char StrTypeShortName[256][32]= { +//0 + "未定义", // 0 国标预留 + "控制器",// 1 + "联动控制器", // 2 + "图形显示装置", // 3 + "未定义", // 4 国标预留 + "未定义", // 5 未使用 + "未定义", // 6 未使用 + "未定义", // 7 未使用 + "未定义", // 8 未使用 + "未定义", // 9 未使用 + "火灾显示盘", // 10 + "探测回路", // 11 + "控制回路", // 12 + "探测控制回路", // 13 + "主电源", // 14 + "备用电源", // 15 + "充电电路", // 16 + "声光警报回路", // 17 + "数据存储单元", // 18 + "未定义", // 19 国标预留 + "火灾探测器", // 20 + "感烟探测器", // 21 + "点型离子烟感", // 22 + "点型光电烟感", // 23 + "线型光束烟感", // 24 + "吸气式烟感", // 25 + "未定义", // 26 国标预留 + "未定义", // 27 未使用 + "未定义", // 28 未使用 + "未定义", // 29 未使用 + "感温探测器", // 30 + "点型温感", // 31 + "线型温感", // 32 + "缆式线型探测", // 33 + "空气管式探测", // 34 + "线型光纤温感", // 35 + "未定义", // 36 国标预留 + "未定义", // 37 未使用 + "未定义", // 38 未使用 + "未定义", // 39 未使用 + "火焰探测器", // 40 + "点型红外火探", // 41 + "点型紫外火探", // 42 + "点型红紫外探", // 43 + "未定义", // 44 国标预留 + "未定义", // 45 未使用 + "未定义", // 46 未使用 + "未定义", // 47 未使用 + "未定义", // 48 未使用 + "未定义", // 49 未使用 + "多传感探测器", // 50 + "感光探测器", // 51 + "图像型探测器", // 52 + "点型CO探测器", // 53 + "未定义", // 54 国标预留 + "未定义", // 55 未使用 + "未定义", // 56 未使用 + "未定义", // 57 未使用 + "未定义", // 58 未使用 + "未定义", // 59 未使用 + "未定义", // 60 未使用 + "手动报警按钮", // 61 + "消火栓按钮", // 62 + "紧急启动按钮", // 63 + "紧急停止按钮", // 64 + "未定义", // 65 国标预留 + "未定义", // 66 未使用 + "未定义", // 67 未使用 + "未定义", // 68 未使用 + "未定义", // 69 未使用 + "未定义", // 70 未使用 + "模块", // 71 + "输入模块", // 72 + "输出模块", // 73 + "输入输出模块", // 74 + "中继模块", // 75 + "短路隔离器", // 76 + "未定义", // 77 国标预留 + "未定义", // 78 未使用 + "未定义", // 79 未使用 + "未定义", // 80 未使用 + "火灾警报装置", // 81 + "声光警报器", // 82 + "火灾声警报器", // 83 + "火灾光警报器", // 84 + "气体释放警报", // 85 + "警铃", // 86 + "未定义", // 87 国标预留 + "未定义", // 88 未使用 + "未定义", // 89 未使用 + "未定义", // 90 未使用 + "未定义", // 91 未使用 + "未定义", // 92 未使用 + "未定义", // 93 未使用 + "未定义", // 94 未使用 + "未定义", // 95 未使用 + "未定义", // 96 未使用 + "未定义", // 97 未使用 + "未定义", // 98 未使用 + "未定义", // 99 未使用 + "可燃气体报警", // 100 + "可燃气体探测", // 101 + "点型可燃气探", // 102 + "线型可燃气探", // 103 + "未定义", // 104 国标预留 + "未定义", // 105 未使用 + "未定义", // 106 未使用 + "未定义", // 107 未使用 + "未定义", // 108 未使用 + "未定义", // 109 未使用 + "电气监控设备", // 110 + "电气监控探测", // 111 + "剩余电流探测", // 112 + "测温电气探测", // 113 + "故障电弧探测", // 114 + "未定义", // 115 国标预留 + "未定义", // 116 未使用 + "未定义", // 117 未使用 + "未定义", // 118 未使用 + "未定义", // 119 未使用 + "应急照明控制", // 120 + "应急标志灯具", // 121 + "应急照明灯具", // 122 + "应急灯电源", // 123 + "应急照明分电", // 124 + "未定义", // 125 国标预留 + "未定义", // 126 未使用 + "未定义", // 127 未使用 + "未定义", // 128 未使用 + "未定义", // 129 未使用 + "防火门监控器", // 130 + "常闭防火门", // 131 + "常开防火门", // 132 + "防火门闭门器", // 133 + "防火门释放器", // 134 + "防火门磁开关", // 135 + "未定义", // 136 国标预留 + "未定义", // 137 未使用 + "未定义", // 138 未使用 + "未定义", // 139 未使用 + "设备电源监控", // 140 + "设备电压传感", // 141 + "设备电流传感", // 142 + "电压电流传感",// 143 + "未定义", // 144 国标预留 + "未定义", // 145 未使用 + "未定义", // 146 未使用 + "未定义", // 147 未使用 + "未定义", // 148 未使用 + "未定义", // 149 未使用 + "气体灭火控制", // 150 + "泡沫灭火系统", // 151 + "干粉灭火系统", // 152 + "防烟排烟系统", // 153 + "防火卷帘控制", // 154 + "挡烟垂壁装置", // 155 + "应急广播系统", // 156 + "消防电话主机", // 157 + "设备应急电源", // 158 + "传输设备", // 159 + "家用监控设备",// 160 + "消防水位监视", // 161 + "消防电梯", // 162 + "电气控制装置", // 163 + "未定义", // 164 国标预留 + "未定义", // 165 未使用 + "未定义", // 166 未使用 + "未定义", // 167 未使用 + "未定义", // 168 未使用 + "未定义", // 169 未使用 + "未定义", // 170 未使用 + "未定义", // 171 未使用 + "未定义", // 172 未使用 + "未定义", // 173 未使用 + "未定义", // 174 未使用 + "未定义", // 175 未使用 + "未定义", // 176 未使用 + "未定义", // 177 未使用 + "未定义", // 178 未使用 + "消防泵控制器", // 179 + "消防栓泵", // 180 + "水喷雾泵", // 181 + "细水雾泵", // 182 + "稳压泵", // 183 + "喷淋泵", // 184 + "雨淋泵", // 185 + "泡沫液泵", // 186 + "水流指示器", // 187 + "报警阀", // 188 + "压力开关", // 189 + "流量开关", // 190 + "阀驱动装置", // 191 + "电动防火阀", // 192 + "70℃防火阀", // 193 + "280℃防火阀", // 194 + "通风空调", // 195 + "管网电磁阀", // 196 + "防烟排烟风机", // 197 + "排烟防火阀", // 198 + "常闭送风口", // 199 + "排烟口", // 200 + "消防水炮", // 201 + "电动门", // 202 + "排烟机", // 203 + "送风机", // 204 + "电磁阀", // 205 + "照明配电", // 206 + "动力配电", // 207 + "空压机", // 208 + "阀门", // 209 + "配电箱", // 210 + "未定义", // 211 未使用 + "未定义", // 212 未使用 + "未定义", // 213 未使用 + "未定义", // 214 未使用 + "未定义", // 215 未使用 + "未定义", // 216 未使用 + "未定义", // 217 未使用 + "未定义", // 218 未使用 + "未定义", // 219 未使用 + "未定义", // 220 未使用 + "甲烷气体探测", // 221 + "丙烷气体探测", // 222 + "甲烷+CO探测", // 223 + "H2S气体探测", // 224 + "烟温一体", // 225 + "烟 CO复合", // 226 + "蜂鸣器底座", // 227 + "单门输入模块", // 228 + "双门输入模块", // 229 + "有源输入输出", // 230 + "广播模块", // 231 + "编码电话模块", // 232 + "防盗探测接口", // 233 + "自动接口模块", // 234 + "门灯", // 235 + "防爆编码接口", // 236 + "感温电缆处理", // 237 + "单路感温报警", // 238 + "感温剩余电流", // 239 + "电源三相监控", // 240 + "电源两相监控", // 241 + "余压控制器", // 242 + "余压探测器", // 243 + "信号阀", // 244 + "联动电源", // 245 + "手自动指示灯", // 246 + "紧急启停按钮", // 247 + "多线控制盘", // 248 + "总线控制盘", // 249 + "气灭控制盘", // 250 + "联网接口卡", // 251 未使用 + "未定义", // 252 未使用 + "未定义", // 253 未使用 + "未定义", // 254 未使用 + "未定义" // 255 未使用 +}; + + +const char StrTypeShortNameEn[256][32]= { +// 0 + "undefine", // 0 + "Controller", // 1 + "LinkController", // 2 + "DisplayDevice", // 3 + "undefine", // 4 + "undefine", // 5 + "undefine", // 6 + "undefine", // 7 + "undefine", // 8 + "undefine", // 9 + "FireDisplay", // 10 + "DetectLoop", // 11 + "ControlLoop", // 12 + "DetCtrlLoop", // 13 + "MainPower", // 14 + "BackupPower", // 15 + "ChargeCircuit", // 16 + "SoundLightLoop", // 17 + "DataStorage", // 18 + "undefine", // 19 + "FireDetector", // 20 + "SmokeDetector", // 21 + "IonSmoke", // 22 + "SmokeDet", // 23 + "BeamSmoke", // 24 + "AspirateSmoke", // 25 + "undefine", // 26 + "undefine", // 27 + "undefine", // 28 + "undefine", // 29 + "HeatDetector", // 30 + "TempeDet", // 31 + "LineHeat", // 32 + "CableDetector", // 33 + "AirTubeDet", // 34 + "FiberHeat", // 35 + "undefine", // 36 + "undefine", // 37 + "undefine", // 38 + "undefine", // 39 + "FlameDetector", // 40 + "IRFlame", // 41 + "UVFlame", // 42 + "IRUVFlame", // 43 + "undefine", // 44 + "undefine", // 45 + "undefine", // 46 + "undefine", // 47 + "undefine", // 48 + "undefine", // 49 + "MultiDetector", // 50 + "LightDetector", // 51 + "ImageDetector", // 52 + "CODetector", // 53 + "undefine", // 54 + "undefine", // 55 + "undefine", // 56 + "undefine", // 57 + "undefine", // 58 + "undefine", // 59 + "undefine", // 60 + "AlarmBtn", // 61 + "HydrantBtn", // 62 + "EmergencyStart", // 63 + "EmergencyStop", // 64 + "undefine", // 65 + "undefine", // 66 + "undefine", // 67 + "undefine", // 68 + "undefine", // 69 + "undefine", // 70 + "Module", // 71 + "InputModule", // 72 + "OutputModule", // 73 + "In/OutModule", // 74 + "RelayModule", // 75 + "ShortIsolator", // 76 + "undefine", // 77 + "undefine", // 78 + "undefine", // 79 + "undefine", // 80 + "FireAlarmDev", // 81 + "Acoustooptic", // 82 + "SoundAlarm", // 83 + "LightAlarm", // 84 + "GasReleaseAlm", // 85 + "AlarmBell", // 86 + "undefine", // 87 + "undefine", // 88 + "undefine", // 89 + "undefine", // 90 + "undefine", // 91 + "undefine", // 92 + "undefine", // 93 + "undefine", // 94 + "undefine", // 95 + "undefine", // 96 + "undefine", // 97 + "undefine", // 98 + "undefine", // 99 + "GasAlarmCtrl", // 100 + "GasDetector", // 101 + "PointGas", // 102 + "LineGas", // 103 + "undefine", // 104 + "undefine", // 105 + "undefine", // 106 + "undefine", // 107 + "undefine", // 108 + "undefine", // 109 + "ElecMonitorDev", // 110 + "ElecMonitorDet", // 111 + "LeakageDet", // 112 + "TempElecDet", // 113 + "ArcDetector", // 114 + "undefine", // 115 + "undefine", // 116 + "undefine", // 117 + "undefine", // 118 + "undefine", // 119 + "EmerLightCtrl", // 120 + "EmerSignLight", // 121 + "EmerIllumLight", // 122 + "EmerLightPower", // 123 + "EmerLightDist", // 124 + "undefine", // 125 + "undefine", // 126 + "undefine", // 127 + "undefine", // 128 + "undefine", // 129 + "DoorMonitor", // 130 + "NCFireDoor", // 131 + "NOFireDoor", // 132 + "DoorCloser", // 133 + "DoorRelease", // 134 + "DoorMagSwitch", // 135 + "undefine", // 136 + "undefine", // 137 + "undefine", // 138 + "undefine", // 139 + "PowerMonitor", // 140 + "VoltSensor", // 141 + "CurrSensor", // 142 + "VoltCurrSensor", // 143 + "undefine", // 144 + "undefine", // 145 + "undefine", // 146 + "undefine", // 147 + "undefine", // 148 + "undefine", // 149 + "GasExtCtrl", // 150 + "FoamSystem", // 151 + "PowderSystem", // 152 + "SmokePESystem", // 153 + "ShutterCtrl", // 154 + "SmokeBarrier", // 155 + "EmerBroadcast", // 156 + "FireTelMain", // 157 + "DevEmerPower", // 158 + "TransmitDev", // 159 + "HomeMonitor", // 160 + "WaterLevelMon", // 161 + "FireElevator", // 162 + "ElecControlDev", // 163 + "undefine", // 164 + "undefine", // 165 + "undefine", // 166 + "undefine", // 167 + "undefine", // 168 + "undefine", // 169 + "undefine", // 170 + "undefine", // 171 + "undefine", // 172 + "undefine", // 173 + "undefine", // 174 + "undefine", // 175 + "undefine", // 176 + "undefine", // 177 + "undefine", // 178 + "FirePumpCtrl", // 179 + "HydrantPump", // 180 + "WaterSprayPump", // 181 + "FineWaterPump", // 182 + "StablePump", // 183 + "SprayPump", // 184 + "DelugePump", // 185 + "FoamPump", // 186 + "FlowIndicator", // 187 + "AlarmValve", // 188 + "PressSwitch", // 189 + "FlowSwitch", // 190 + "ValveDrive", // 191 + "ElecFireValve", // 192 + "70^CFireValve", // 193 + "280^CFireValve", // 194 + "AirCondition", // 195 + "PipeSolValve", // 196 + "SmokeFan", // 197 + "ExhaustValve", // 198 + "NCAirInlet", // 199 + "ExhaustOutlet", // 200 + "WaterCannon", // 201 + "ElectricDoor", // 202 + "ExhaustFan", // 203 + "AirSupplyFan", // 204 + "SolenoidValve", // 205 + "LightPowerDist", // 206 + "PowerDist", // 207 + "AirCompressor", // 208 + "Valve", // 209 + "PowerBox", // 210 + "undefine", // 211 + "undefine", // 212 + "undefine", // 213 + "undefine", // 214 + "undefine", // 215 + "undefine", // 216 + "undefine", // 217 + "undefine", // 218 + "undefine", // 219 + "undefine", // 220 + "CH4GasDetect", // 221 + "C3H8GasDetect", // 222 + "CH4_CO_Detect", // 223 + "H2SGasDetect", // 224 + "SmokeHeatDet", // 225 + "Smoke_CO_Com", // 226 + "BuzzerBase", // 227 + "SingleDoorIn", // 228 + "DoubleDoorIn", // 229 + "ActiveInOut", // 230 + "BroadcastMdl", // 231 + "CodeTelModule", // 232 + "AntiTheftDetIF", // 233 + "AutoIFModule", // 234 + "DoorLight", // 235 + "ExCodeIFBox", // 236 + "HeatCableProc", // 237 + "SingleHeatAlm", // 238 + "Heat_Leakage", // 239 + "Power_3Phase", // 240 + "Power_2Phase", // 241 + "PressCtrl", // 242 + "PressDetector", // 243 + "SignalValve", // 244 + "LinkPower", // 245 + "AutoManualLED", // 246 + "EmerStartStop", // 247 + "MultiLinePanel", // 248 + "BusPanel", // 249 + "GasExtPanel", // 250 + "NetIFCard", // 251 + "undefine", // 252 + "undefine", // 253 + "undefine", // 254 + "undefine" // 255 +}; + + +/* +#define dAssign_iType_Undefine 0 +#define dAssign_iType_ExtSmoke 1 +#define dAssign_iType_ExtTempe 2 +#define dAssign_iType_ExtHandReport 3 +#define dAssign_iType_PowerLost 4 +#define dAssign_iType_PressureLow 5 +#define dAssign_iType_FlowRateLow 6 +#define dAssign_iType_HydrantActive 7 +#define dAssign_iType_NullMax 8 */ +const char StrAssign_iType[60][32]= { +//0~4 + "未定义", + "外接烟感", + "外接温感", + "外接手报", + "失去电力", + "水压低", + "流量过少", + "消火栓激活", + "未定义8", + "未定义9", + "未定义10", + "未定义11", + "未定义12", + + "未定义13", + "未定义14", + "未定义15", + + "未定义16", + "未定义17", + "未定义18", + "未定义19", + "未定义20", + "未定义21", + "未定义22", + "未定义23", + "未定义24", + "未定义25", + "未定义26", + + "未定义27", + "未定义28", + "未定义29", + "未定义30", + "未定义31", + "未定义32", + "未定义33", + "未定义34", + + "未定义35", + "未定义36" +}; + +//#define dAssign_oType_Undefine 0 +//#define dAssign_oType_Watering 1 +//#define dAssign_oType_WaterPumpStart 2 +//#define dAssign_oType_FireDoorAction 3 +//#define dAssign_oType_FireDoorOpen 4 +//#define dAssign_oType_FireDoorClose 5 +//#define dAssign_oType_SoundOn 6 +//#define dAssign_oType_VisibleOn 7 +//#define dAssign_oType_SoundVisibleOn 8 +//#define dAssign_oType_FireElevatorOn 9 +//#define dAssign_oType_SmokeExhaustOn 10 +//#define dAssign_oType_FireRollerShutterOn 11 +const char StrAssign_oType[60][32]= { +//0~4 + "未定义0", + "启动淋水", + "启动水泵", + "防火门动作", + "打开防火门", + "关闭防火门", + "启动警报声", + "启动警报光", + "启动警报声光", + "开启消防电梯", + "开启排烟设备", + "开启卷帘", + "关闭卷帘", + + "未定义13", + "未定义14", + "未定义15", + + "未定义16", + "未定义17", + "未定义18", + "未定义19", + "未定义20", + "未定义21", + "未定义22", + "未定义23", + "未定义24", + "未定义25", + "未定义26", + + "未定义27", + "未定义28", + "未定义29", + "未定义30", + "未定义31", + "未定义32", + "未定义33", + "未定义34", + + "未定义35", + "未定义36" +}; + +const char StrEpFaultType[16][24] = { + "故障", + "污染故障", + "传感故障",//"传感器故障", + "寿命故障",//"传感器寿命故障", + "输出故障",//"输出断线故障", + "输入故障",//"输入断线故障", + "主电故障", + "备电故障", + + "电池故障", + "未定义1", + "未定义2", + "未定义3", + "未定义4", + "未定义5", + "未定义6", + "未定义7", +}; + +const char StrEpFaultTypeEn[16][24] = { + "Fault", + "Pollution", + "Sens Fault",//"传感器故障", + "Sens Life Fault",//"传感器寿命故障", + "Output Fault",//"输出断线故障", + "Input Fault",//"输入断线故障", + "Main Power", + "Spare Power", + + "Battery Fail", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", +}; + +const char StrBrdFaultType[dBoardFaultTypeMax][24] = { + "故障", + "回路板故障", + "总线盘故障", + "多线盘故障", + "联网接口卡故障", + "主电故障", + "备电故障", + "24V故障", + + "充电故障", + "图显通信故障", + "回路母板离线", + "注册数据错误", + "屏蔽数据错误", + "存储类型错误", + "存储辅助码错误", + "存储区域号错误", + + "存储指派类型错误", + "存储输入类型错误", + "存储联动表达错误", + "存储联动表达错误", + "存储联动表达错误", + "存储联动表达错误", + "存储联动表达错误", + "存储联动表达错误", + + "存储联动表达错误", + "存储联动表达错误", + "存储联动表达错误", + "存储多线盘错误", + "存储回路列表错误", + "存储回路层显配置", + "存储总线盘配置", + "存储屏蔽数据错误", + + //32 + "记录主键号将溢出", + "未定义23", + "未定义22", + "未定义23", + "未定义22", + "未定义23", + "未定义22", + "未定义23", + + "未定义22", + "未定义23", + "未定义22", + "未定义23", + "未定义22", + "未定义23", + "未定义22", + "未定义23", +}; + +const char StrBrdFaultTypeEn[dBoardFaultTypeMax][24] = { + "Fault", + "Loop Board Fault", + "Bus Pad Fault", + "Direct Pad Fault", + "Comm Brd Fault", + "Prima Power Fault", + "Spare Power Fault", + "24V Fault", + + "Charge Fault", + "CRT Comm Fault", + "Mother Board OffLine", + "Registered List Err", + "Blocking List Err", + "Storage DType Err", + "Storage AuxId Err", + "Storage AreaId Err", + + "Storage AssigType", + "Storage SignalType", + "Storage LinkExp", + "Storage LinkExp", + "Storage LinkExp", + "Storage LinkExp", + "Storage LinkExp", + "Storage LinkExp", + + "Storage LinkExp", + "Storage LinkExp", + "Storage LinkExp", + "Storage DictPad Cfg", + "Storage Loop List", + "Storage Loop DpSet", + "Storage BusPad Cfg", + "Storage Mask Data", + + //32 + "Record PRIMARY KEY", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", + "undefine", +}; + +const char StrDevFaultType[32][24] = { + //0 + "未知类型", + "故障", + "回路板故障", + "总线盘故障", + "多线盘故障", + "主板存储故障", + "存储单元故障", + "主电故障", + + //8 + "电源通讯故障", + "备电故障", + "电池故障", + "网络通讯故障", + "区域通讯故障", + "图显通信故障", + "系统故障", + "到集中机 ", + + //16 + "到区域机 ", + "打印机离线或缺纸", + "打印机缺纸 ", + "副电源市电故障", + "副电源备电故障", + "副电源通讯故障", + "主电源24V输出故障", + "副电源24V输出故障", + + //24 + "主电源电池1欠压", + "主电源电池2欠压", + "副电源电池1欠压", + "副电源电池2欠压", + "未定义12", + "未定义13", + "未定义14", + "未定义15", +}; + +const char StrDevFaultTypeEn[32][24] = { + //0 + "undefine", + "Fault", + "Loop Board Fault", + "Bus Pad Fault", + "Direct Pad Fault", + "Onboard Memory Fault", + "Extend Memory Fault", + "Main Power Fault", + + //8 + "Power Offline", + "Spare Power Fault", + "Bat Fault", + "LAN Fault", + "Zone Dev Offline", + "CRT Comm Fault", + "System Fault", + "Master Offline", + + //16 + "Slaver Offline", + "Printer Fault", + "Printer No Paper ", + "SCPS MP Fault", + "SCPS SP Fault", + "SCPS Comm Fault", + "Prima 24V Out Fault", + "Sub 24V Out Fault", + + //24 + "Prima Bat1 UV", + "Prima Bat2 UV", + "Sub Bat1 UV", + "Sub Bat2 UV", + "undefine", + "undefine", + "undefine", + "undefine", +}; + + +const char StrType_Unknown[] = {"未知设备"};//"未知设备"; +const char StrType_PowerBoard[] = "未知设备";//"电源板"; +const char StrType_GuiPc[] = "图形显示装置";//"图形显示装置"; +const char StrType_3[] = "CAN通讯板"; +const char StrType_4[] = "多用途通讯板"; +const char StrType_5[] = "LCD显示"; +const char StrType_6[] = "标准键盘板"; +const char StrType_7[] = "键盘板"; +const char StrType_8[] = "总线盘"; +const char StrType_9[] = "多线盘"; + +const char StrType_10[] = "点型烟感I"; +const char StrType_11[] = "点型烟感II"; +const char StrType_12[] = "点型温感I"; +const char StrType_13[] = "点型温感II"; +const char StrType_14[] = "烟温复合感应I"; +const char StrType_15[] = "烟温复合感应II"; +const char StrType_16[] = "震动感应I"; +const char StrType_17[] = "震动感应II"; + +const char StrType_18[] = "雷达感应I"; +const char StrType_19[] = "雷达感应II"; + +const char TextAdjust[16] = "正在调试"; +const char TextAuto[16] = "允许自动"; +const char TextAllAuto[16] = "全部自动"; +const char TextManual[16] = "允许手动"; +const char TextSplash[16] = "允许喷洒"; +const char TextPrint[16] = "允许打印"; + +const char TextAdjustNot[16] = "正在调试";//"非调试"; +const char TextAutoNot[16] = "正在调试";//"禁止自动"; +const char TextAllAutoNot[16] = "非全自动"; +const char TextManualNot[16] = "禁止手动"; +const char TextSplashNot[16] = "禁止喷洒"; +const char TextPrintNot[16] = "禁止打印"; + +const unsigned int GuiRedrawDataList[6][4] = { +3,3,794,474, +170, 100, 630, 246, + + + + +}; + +const unsigned char TypeToIconIndex[256] = { + 0,//"未知设备", + 0,//"未知设备", + 0,//"点型温感", + 0,//"点型烟感", + 0,//"未知设备", + 0,//"未知设备", + 0,//"烟温一体", + 0,//"烟CO一体", + 0,//"未知设备", + 0,//"线型光束烟感", + 0,//"红外火焰探测", + 0,//"未知设备", + 0,//"紫外火焰探测", + 0,//"未知设备2", + 0,//"吸气时感烟", + 0,//"未知设备", +//0x10 + 0,//"甲烷气体探测", + 0,//"丙烷气体探测", + 0,//"CO气体探测", + 0,//"甲烷+CO探测", + 0,//"硫化氢气体探测", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", + 0,//"未知设备", +//0x20 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0x30 + 0,//"手动报警按钮", + 0,//"消火栓按钮", + 0,//"声光警报器", + 0,//"声警报器", + 0,//"光警报器", + 0,//"蜂鸣器底座", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0x40 + 0,//"输入模块", + 0,//"单门输入模块", + 0,//"双门输入模块", + 0,//"未定义4", + 0,//"无源输入输出模块", + 0,//"有源输入输出模块", + 0,//"广播模块", + 0,//"一体式闭门器", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"编址中继模块", + 0,//"编址隔离模块", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0x50 + 0,//"火灾显示盘", + 0,//"未定义2", + 0,//"编码消防电话模块", + 0,//"编码防盗探测器接口", + 0,//"门灯", + 0,//"防爆编码接口箱", + 0,//"自动接口工业模块", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0x60 + 0,//"单路感温电气火灾报警器", + 0,//"1路感温+1路剩余电流", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"消防电源-三相监控", + 0,//"消防电源-两相监控", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0x70 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0x80 + 0,//"余压控制器", + 0,//"余压探测器", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0x90 + 0,//"感温电缆数据处理器", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0xA0 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0xB0 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0xC0 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0xD0 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0xE0 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0,//"未定义16", +//0xF0 + 0,//"未定义1", + 0,//"未定义2", + 0,//"未定义3", + 0,//"未定义4", + 0,//"未定义5", + 0,//"未定义6", + 0,//"未定义7", + 0,//"未定义8", + 0,//"未定义9", + 0,//"未定义10", + 0,//"未定义11", + 0,//"未定义12", + 0,//"未定义13", + 0,//"未定义14", + 0,//"未定义15", + 0//"未定义16" +}; + + + + + + + + + + + + diff --git a/MyCode/Gui/gvalue.h b/MyCode/Gui/gvalue.h new file mode 100644 index 0000000..c184138 --- /dev/null +++ b/MyCode/Gui/gvalue.h @@ -0,0 +1,344 @@ +#ifndef GVALUE_H_ +#define GVALUE_H_ + +#include "gType.h" + +#define dBIT_UPDATE 0x01 +#define dBIT_CHECK 0x02 +#define dBIT_FOUND 0x04 + +#define dPORT_COUNT_USING 40 + +#define dNETWORK_MACHINE_COUNT 32 +#define dNETWORK_MACHINE_MASTER_COUNT 8 + +#define dEP_MAX_COUNT_PER_PORT 250 +#define dPORT_MAX_COUNT 40 + +#define dHANDCTL_MAX_COUNT 20 +#define dHANDCTL_KEY_MAX_COUNT 128 + +#define dDIRECTCTL_MAX_COUNT 20 +#define dDIRECTCTL_KEY_MAX_COUNT 8 + +#define dMOTHERBOARD_MAX_COUNT 8 +#define dCOMMBOARD_MAX_COUNT 8 + +#define dFIREPUMP_ASSIGN_TYPE 180 + +#define dDISPLAYPAD_MAX_COUNT 16 //for One Circuit + +#define dLINKAGE_MAX_COUNT 2048 + +#define dAreaCountMax 1024 + +#define dADDR_OFFSET_PORT 1 +#define dADDR_OFFSET_DIRECTCTL 66 +#define dADDR_DIRECTPAD_START 66 +#define dADDR_DIRECTPAD_END 85 +#define dADDR_HANDPAD_START 101 +#define dADDR_HANDPAD_END 120 +#define dADDR_OFFSET_MOTHERBOARD 65 + +#define dONE_CTRL_DESCP_BYTES 360000 + +#define dAddrSdRam_BackScreen 0xC3E80000 + +//see the excel xls File +#define dAddrSdRam_NetEpState 0xC0B00000 + +#define dAddrSdram_C2cOutEntryFireBuf (0xC1900000) +#define dAddrSdram_C2cOutEntrySvBuf (0xC1900000 + 0x00060000) +#define dAddrSdram_C2cOutEntryLinkBuf (0xC1900000 + 0x00090000) +#define dAddrSdram_C2cOutBuf (0xC1900000 + 0x000C0000) +#define dAddrSdram_C2cOutEntryFaultBuf (0xC1A00000) +#define dAddrSdram_C2cOutEntryNormalBuf (0xC1A00000 + 0x00080000) +#define dAddrSdram_C2cOutEntryBasicServiceBuf (0xC1A00000 + 0x000E0000) + +#define dAddrSdram_NwFireIdf 0xC1B00000 +#define dAddrSdram_NwDelayStart 0xC1C00000 +#define dAddrSdram_RuntimeCheck 0xC1EA0000 +#define dAddrSdram_NwUserCodeAbs 0xC1F00000 + +#define dAddrSdram_CrtTxBuf 0xC2000000 +#define dAddrSdram_CrtRxBuf 0xC2100000 +#define dAddrSdram_InnerCan 0xC2200000 +#define dAddrSdram_InnerCanFastOut 0xC22C4000 +#define dAddrSdram_FECStdBuf 0xC2300000 +#define dAddrSdram_CfgBuf 0xC2400000 + + +#define dAddrSdram_PrintBuf 0xC2500000 + +#define dAddrSdRam_Commom 0xC3A00000 +#define dAddrSdRam_Register dAddrSdRam_Commom +#define dAddrSdRam_CtrlInf dAddrSdRam_Commom +#define dAddrSdRam_DupCheck dAddrSdRam_Commom +#define dAddrSdRam_HwInf dAddrSdRam_Commom + +#define dAddrSdRam_Descp 0xC3B00000 +#define dAddrSdRam_4Area 0xC3B90000 //128k +#define dAddrSdRam_4UserCodeMatch 0xC3BC0000 //128k +#define dAddrSdRam_DescpNw 0xC0D00000 + +#define HOTKEY_FIRE_ALRAM 0x72 +#define HOTKEY_LINKAGE_START 0x73 +#define HOTKEY_INF_CONF 0x74 +#define HOTKEY_SELF_CHECK 0x75 +#define HOTKEY_MUTE 0x76 +#define HOTKEY_RESET 0xE9 +#define HOTKEY_CHECK 0x77 +#define HOTKEY_AUTO_ALLOW 243 +#define HOTKEY_MANUAL_ALLOW 244 + +#define dfKEY_ASTERISK 0x6E // Key value for * asterisk +#define dfKEY_SIG 0xBF // Key value for # +#define dfKEY_SETUP 0x70 // Key value for SETUP +#define dfKEY_QUERY 0x71 // Key value for QUERY +#define dfKEY_ENCN 0x10 // Key value for EN/CN + +#define dgTYPE_NoType 0 +#define dgTYPE_SMOKE_DETECTOR 23 +#define dgTYPE_TEMPE_DETECTOR 31 +#define dgTYPE_HAND_REPORT 61 +#define dgTYPE_FIRE_HydrantKp 62 +#define dgTYPE_IN_MODULE 72 +#define dgTYPE_OUT_MODULE 73 +#define dgTYPE_INOUT_MODULE_NonSource 74 +#define dgType_VAALRAM 82 +#define dgTYPE_DISPLAY_PAD 10 +#define dgTYPE_SMOKE_TEMPE_DETECTOR 225 +#define dgTYPE_INOUT_MODULE_Source 230 +#define dgTYPE_LINKAGE_POWERSUPLY 245 + +#define dASSIGN_TYPE_Broadcast 231 + + +/* +typedef enum{ + ActLoginII = 0, + ActLogoutII = 1, + ActLoginIII, + ActLogoutIII +}TGuiActionMenu_0; + +typedef enum{ + ActQueDevice = 0, + ActQueRegAddr , + ActQueMaskDevice, + ActQueConfig, + ActQueInterLink, + ActQueInterLink4Pad, + ActQueNetwork, + ActNull1 +}TGuiActionMenu_1; + +typedef enum{ + ActQueMsgAll = 0, + ActQueMsgAlarm, + ActQueMsgFault , + ActQueMsgSuperVi, + ActQueMsgOperator, + ActQueMsgLinkage , + ActNull2 +}TGuiActionMenu_2; + +typedef enum{ + Actxx0 = 0, + ActNull3 +}TGuiActionMenu_3; + +typedef enum{ + ActDeviceSetup = 0, + ActNull4 +}TGuiActionMenu_4; + +typedef enum{ + Actxx3 = 0, + ActNull5 +}TGuiActionMenu_5; + +typedef enum{ + ActNewRegister = 0, + ActAddRegister = 1, + ActManualAddRegister = 2, + ActManualRemoveRegister = 3, +}TGuiActionMenu_6; + +typedef enum{ + Actxx5 = 0, + ActNull7 +}TGuiActionMenu_7; + +typedef enum{ + Actxx6 = 0, + ActNull8 +}TGuiActionMenu_8; + +typedef enum{ + ActAboutUs = 0, +}TGuiActionMenu_9; + +typedef enum{ + PermissonSet_I = 0, + PermissonSet_II = 1, +}TGuiActionMenu_10; +*/ +typedef enum { + guiIdle = 0, + + //menu + guiMenu , + guiShowEvent, + + guiDeviceCheck , + guiDeviceSetup , + guiUserSetup , + guiDeviceMask , + guiDeviceExercise , + guiCheckNormal, + + guiStateGiveBack, + guiStateOccupy, + guiStateRemote, + + guiTipPopup, +}TGuiState; + +typedef enum{ + guiMsgNone = 0, + guiMsgReturn, + guiMsgPrev, + guiMsgNext, + guiMsgChanged, + guiMsgOkAndReturn, + guiMsgSel1AndReturn, + guiMsgSel2AndReturn, +}TGuiMsgReturn; + +typedef struct{ + struct{ + unsigned char data[24]; + unsigned int Index; + unsigned int Limited; + unsigned int Rdy; + }Rx,Tx; +}TUartBuf; + +typedef enum{ + piMemo = 0, + piChart = 1, + piEdit = 2, + +}TPanelItemType; + +typedef struct{ + int Left; + int Top; + int Width; + int Heigh; + int Right; + int Bottom; +}TContentGeometry; + +typedef struct{ + struct{ + int Left; + int Top; + int Width; + int Heigh; + int Right; + int Bottom; + }Caption; + struct{ + int Left[12]; + int Top[12]; + int Right[12]; + int Bottom[12]; + int UsingCount; + }Grid; + struct{ + int Left; + int Top; + int Width; + int Heigh; + int Right; + int Bottom; + TPanelItemType ItemType; + int Active; + }Panel; + struct{ + int Left; + int Top; + int Width; + int Heigh; + int Right; + int Bottom; + TPanelItemType ItemType; + int Active; + }PanelSmall; +}TLv; + +extern TGuiState GuiState, GuiStateBAK; +extern unsigned char ActList_0; +extern unsigned char ActList_1; +extern unsigned char ActList_2; +extern unsigned char ActList_3; +extern unsigned char ActList_4; +extern unsigned char ActList_5; +extern unsigned char ActList_6; +extern unsigned char ActList_7; +extern unsigned char ActList_8; +extern unsigned char ActList_9; +extern unsigned char ActList_10; + +extern TUartBuf uart1; + +extern const char CharLinkage[16]; +extern const char CharBusPadProgram[16]; +extern const char StrHwType[256][32]; +extern const char StrHwTypeEn[256][32]; +extern const char StrRootType[16][32]; +extern const char StrType[256][32]; +extern const char StrTypeShortName[256][32]; + +extern const char StrAssign_iType[60][32]; +extern const char StrAssign_oType[60][32]; +extern const char StrType_Unknown[]; +extern const char StrType_PowerBoard[]; +extern const unsigned char TypeToIconIndex[256]; + +extern const char StrEpFaultType[16][24]; +extern const char StrBrdFaultType[dBoardFaultTypeMax][24]; +extern const char StrDevFaultType[32][24]; + +extern const char TextAdjust[16]; +extern const char TextAuto[16]; +extern const char TextAllAuto[16]; +extern const char TextManual[16]; +extern const char TextSplash[16]; +extern const char TextPrint[16]; + +extern const char TextAdjustNot[16]; +extern const char TextAutoNot[16]; +extern const char TextAllAutoNot[16]; +extern const char TextManualNot[16]; +extern const char TextSplashNot[16]; +extern const char TextPrintNot[16] ; + +extern const unsigned int GuiRedrawDataList[6][4]; + +//EN + +extern const char StrTypeShortNameEn[256][32]; +extern const char StrDevFaultTypeEn[32][24]; +extern const char StrEpFaultTypeEn[16][24]; +extern const char StrBrdFaultTypeEn[dBoardFaultTypeMax][24]; + +extern void GlobalValue_init(void); +extern void Clear(void); +extern void StateBarReflash(); + + +#endif + diff --git a/MyCode/Gui/my_font.h b/MyCode/Gui/my_font.h new file mode 100644 index 0000000..d495f8f --- /dev/null +++ b/MyCode/Gui/my_font.h @@ -0,0 +1,17 @@ +#ifndef MY_FONT_H_ +#define MY_FONT_H_ + +//extern const unsigned char ascii_5x8_table[]; +//extern const unsigned char ascii_7x12_table[]; +extern const unsigned char ascii_8x16[1536]; +extern const unsigned char ascii_11x16_table[]; +extern const unsigned char ascii_14x20_table[]; +extern const unsigned char ascii_17x24_table[]; + + +#endif + + + + + diff --git a/MyCode/Gui/my_string.cpp b/MyCode/Gui/my_string.cpp new file mode 100644 index 0000000..2b61bf7 --- /dev/null +++ b/MyCode/Gui/my_string.cpp @@ -0,0 +1,1446 @@ +#include "math.h" +#include "my_font.h" +#include "my_string.h" + +static void reverse(char *str, int n) +{ + int p = 0, q = n-1; + char t; + while (p < q) { + t = str[p]; + str[p] = str[q]; + str[q] = t; + p++; + q--; + } +} + +void TMyString::Clear(void) +{ + Text[0] = '\0'; + Text[1] = '\0'; + Text[2] = '\0'; +} + +int TMyString::Insert(const char *source, int Pst) +{ + //dMYSTRING_LENGTH + int i,x; + unsigned int ilen, len; + int sp; + const char *aP = source; + + x = GetEndPst(); + if(x <= Pst){ + AddOnStr(source); + sp = GetEndPst(); + return sp; + } + + for(i=0; i0){ + e = d % 10; + TmpChar[i] = e + '0'; + i++; + d /= 10; + } + if(sig){ + d = i; + while(i>0){ + Text[d-i] = TmpChar[i-1]; + i--; + } + Text[d] = 0; + }else{ + d = i; + while(i>0){ + Text[d-i+1] = TmpChar[i-1]; + i--; + } + Text[0] = '-'; + Text[d+1] = 0; + } + } +} + +void TMyString::FromUInt(unsigned int data) +{ + unsigned int i; + unsigned int sig; + unsigned int d,e; + + for(i=0;i<32;i++)TmpChar[i] = 0; + + if(data < 0){ + sig = 0; + d = (unsigned int)(0 - data); + }else{ + sig = 1; + d = (unsigned int)data; + } + + if(d == 0){ + Text[0] = '0'; + Text[1] = 0; + }else{ + i = 0; + while(d>0){ + e = d % 10; + TmpChar[i] = e + '0'; + i++; + d /= 10; + } + if(sig){ + d = i; + while(i>0){ + Text[d-i] = TmpChar[i-1]; + i--; + } + Text[d] = 0; + }else{ + d = i; + while(i>0){ + Text[d-i+1] = TmpChar[i-1]; + i--; + } + Text[0] = '-'; + Text[d+1] = 0; + } + } +} + +void TMyString::sFromUInt(unsigned int data, unsigned char *Text) +{ + unsigned int i; + unsigned int sig; + unsigned int d,e; + char aTmpChar[32]; + + for(i=0;i<32;i++)aTmpChar[i] = 0; + + sig = 1; + d = data; + + + if(d == 0){ + Text[0] = '0'; + Text[1] = 0; + }else{ + i = 0; + while(d>0){ + e = d % 10; + aTmpChar[i] = e + '0'; + i++; + d /= 10; + } + if(sig){ + d = i; + e = i; + while(i>0){ + Text[e-i] = aTmpChar[i-1]; + i--; + } + Text[d] = 0; + } + } +} + +void TMyString::FromUInt4Dg(unsigned int data) +{ + unsigned int d,e; + + d = data/1000; + e = d % 10; + Text[0] = e + '0'; + + d = data/100; + e = d % 10; + Text[1] = e + '0'; + + d = data/10; + e = d % 10; + Text[2] = e + '0'; + + e = data % 10; + Text[3] = e + '0'; + + Text[4] = 0; +} + +void TMyString::FromUInt6Dg(unsigned int data) +{ + unsigned int d,e; + + d = data/100000; + e = d % 10; + Text[0] = e + '0'; + + d = data/10000; + e = d % 10; + Text[1] = e + '0'; + + d = data/1000; + e = d % 10; + Text[2] = e + '0'; + + d = data/100; + e = d % 10; + Text[3] = e + '0'; + + d = data/10; + e = d % 10; + Text[4] = e + '0'; + + e = data % 10; + Text[5] = e + '0'; + + Text[6] = 0; +} + +void TMyString::FromUInt8Dg(unsigned int data) +{ + unsigned int d,e; + + d = data/10000000; + e = d % 10; + Text[0] = e + '0'; + + d = data/1000000; + e = d % 10; + Text[1] = e + '0'; + + d = data/100000; + e = d % 10; + Text[2] = e + '0'; + + d = data/10000; + e = d % 10; + Text[3] = e + '0'; + + d = data/1000; + e = d % 10; + Text[4] = e + '0'; + + d = data/100; + e = d % 10; + Text[5] = e + '0'; + + d = data/10; + e = d % 10; + Text[6] = e + '0'; + + e = data % 10; + Text[7] = e + '0'; + + Text[8] = 0; +} + + +void TMyString::AddOnDgMax6(unsigned int data) +{ + unsigned int d,e,i,pst, IsFound; + pst = GetEndPst() +1; + if(pst > (dMYSTRING_LENGTH - 8))return; + + IsFound = 0; + + d = data/100000; + e = d % 10; + if(e>0){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10000; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/1000; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/100; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10; + e = d % 10; + if((e>0)||(IsFound)){ + Text[pst] = e + '0'; + pst++; + IsFound = 1; + } + + e = data % 10; + Text[pst++] = e + '0'; + + Text[pst++] = 0; + Text[pst++] = 0; +} + +void TMyString::AddOn8Dg(unsigned int data) +{ + unsigned int d,e,i,pst; + pst = GetEndPst() +1; + if(pst > (dMYSTRING_LENGTH - 10))return; + + d = data/10000000; + e = d % 10; + Text[pst] = e + '0'; + + d = data/1000000; + e = d % 10; + Text[pst+1] = e + '0'; + + d = data/100000; + e = d % 10; + Text[pst+2] = e + '0'; + + d = data/10000; + e = d % 10; + Text[pst+3] = e + '0'; + + d = data/1000; + e = d % 10; + Text[pst+4] = e + '0'; + + d = data/100; + e = d % 10; + Text[pst+5] = e + '0'; + + d = data/10; + e = d % 10; + Text[pst+6] = e + '0'; + + e = data % 10; + Text[pst+7] = e + '0'; + + Text[pst+8] = 0; +} + +void TMyString::AddOn6Dg(unsigned int data) +{ + unsigned int d,e,i,pst; + pst = GetEndPst() +1; + if(pst > (dMYSTRING_LENGTH - 8))return; + + d = data/100000; + e = d % 10; + Text[pst] = e + '0'; + + d = data/10000; + e = d % 10; + Text[pst+1] = e + '0'; + + d = data/1000; + e = d % 10; + Text[pst+2] = e + '0'; + + d = data/100; + e = d % 10; + Text[pst+3] = e + '0'; + + d = data/10; + e = d % 10; + Text[pst+4] = e + '0'; + + e = data % 10; + Text[pst+5] = e + '0'; + + Text[pst+6] = 0; +} + +void TMyString::AddOn4Dg(unsigned int data) +{ + unsigned int d,e,i,pst; + pst = GetEndPst() +1; + if(pst > (dMYSTRING_LENGTH - 6))return; + + d = data/1000; + e = d % 10; + Text[pst] = e + '0'; + + d = data/100; + e = d % 10; + Text[pst+1] = e + '0'; + + d = data/10; + e = d % 10; + Text[pst+2] = e + '0'; + + e = data % 10; + Text[pst+3] = e + '0'; + + Text[pst+4] = 0; +} + +void TMyString::FromUInt3Dg(unsigned int data) +{ + unsigned int i; + unsigned int d,e; + + d = data/100; + e = d % 10; + Text[0] = e + '0'; + + d = data/10; + e = d % 10; + Text[1] = e + '0'; + + e = data % 10; + Text[2] = e + '0'; + + Text[3] = 0; + Text[4] = 0; +} + +void TMyString::AddOn3Dg(unsigned int data) +{ + unsigned int i,pst; + unsigned int d,e; + + pst = GetEndPst() +1; + if(pst > (dMYSTRING_LENGTH - 5))return; + + d = data/100; + e = d % 10; + Text[pst] = e + '0'; + + d = data/10; + e = d % 10; + Text[pst+1] = e + '0'; + + e = data % 10; + Text[pst+2] = e + '0'; + + Text[pst+3] = 0; + Text[pst+4] = 0; +} + +void TMyString::FromUInt2Dg(unsigned int data) +{ + unsigned int i; + unsigned int d,e; + + d = data/10; + Text[0] = d + '0'; + + e = data % 10; + Text[1] = e + '0'; + + Text[2] = 0; + Text[3] = 0; +} + +void TMyString::AddOn2Dg(unsigned int data) +{ + unsigned int i,pst; + unsigned int d,e; + + pst = GetEndPst() +1; + if(pst > (dMYSTRING_LENGTH - 4))return; + + d = data/10; + Text[pst] = d + '0'; + + e = data % 10; + Text[pst+1] = e + '0'; + + Text[pst+2] = 0; + Text[pst+3] = 0; +} + +void TMyString::FormFloat(float fd) +{ + //unsigned int ava_bit = 0; + float f = fd; + unsigned int sig; + signed int i = 0; + signed int n = (int)f; + + if(f < 0){ + sig = 0; + f *= -1; + }else{ + sig = 1; + } + n = (unsigned int)f; + f -= n; + i = 0; + do{ + Text[i++] = n % 10 + '0'; + n /= 10; + }while(n > 0); + if(0 == sig) Text[i++] = '-'; + + reverse(Text , i); + Text[i++] = '.'; + n = 0; + do{ + int t = (int)(f * 10); + Text[i++] = t + '0'; + f = f * 10 - t; + n++; + }while(f > 0 && n < 9); + Text[i] = '\0'; +} + +int TMyString::ToInteger(void) +{ + signed int Result; + unsigned int i; + unsigned int sig; + + if(Text[0] == '-'){ + sig = 0; + i = 1; + }else{ + sig = 1; + i = 0; + } + Result = 0; + while(1){ + if(Text[i] < '0' || Text[i] > '9'){ + if(Text[i] == 0) break; + Result = 0; + break; + }else{ + Result *= 10; + Result += Text[i] - '0'; + } + i++; + } + if(sig == 0) Result = 0 - Result; + return Result; + +} + +float TMyString::ToFloat(void) +{ + float Result; + + float f; + unsigned int i; + unsigned int sig; + unsigned int dot_found = 0; + signed int Decimal_counts = 0; + unsigned int valid_char_counts = 0; + if(Text[0] == '-'){ + sig = 0; + i = 1; + }else{ + sig = 1; + i = 0; + } + Result = 0; + dot_found = 0; + Decimal_counts = 0; + while(1){ + if((Text[i] < '0' || Text[i] > '9') && (Text[i] != '.')){ + if(Text[i] != 0){ + Result = 0; + break; + }else{ + break; + } + }else{ + if(Text[i] == '.'){ + dot_found++; + }else{ + if(Text[i] == '0'){ + if(valid_char_counts)valid_char_counts++; + }else{ + valid_char_counts++; + } + + if(dot_found == 0){ + Result *= 10; + Result += Text[i] - '0'; + }else if(dot_found == 1){ + Decimal_counts -=1; + if(valid_char_counts > 12)break; +// f = (Text[i] - '0') * pow(10,Decimal_counts); + Result += f; + }else{ + // error '0.0.' more then one dot found + Result = 0; + break; + } + } + } + i++; + } + if(sig == 0) Result *= -1; + return Result; + +} + + +//Static function----------------> +void TMyString::sFromStr(char *source, char *dest) +{ + unsigned int i; + unsigned int len; + len = dMYSTRING_LENGTH -1; + for(i=0; i= 32)break; + dest[i]=source[d]; + if(source[d] == 0)break; + d++; + s++; + } + dest[i] = '\0'; +} + +void TMyString::sAddOnStrL32(char *source, char *dest) +{ + unsigned int s; + unsigned int i; + unsigned int d=0; + int len = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)len++; + else break; + } + s = 0; + for(i=len; i<(dMYSTRING_LENGTH-1); i++){ + if(s >= 32)break; + dest[i]=source[d]; + if(source[d] == 0)break; + d++; + s++; + } + dest[i] = '\0'; +} + +void TMyString::sAddOnDgMax6(unsigned int data, char *dest) +{ + unsigned int d,e,i,pst, IsFound; + pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 8))return; + + IsFound = 0; + + d = data/100000; + e = d % 10; + if(e>0){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10000; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/1000; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/100; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + d = data/10; + e = d % 10; + if((e>0)||(IsFound)){ + dest[pst] = e + '0'; + pst++; + IsFound = 1; + } + + e = data % 10; + dest[pst++] = e + '0'; + + dest[pst++] = 0; + dest[pst++] = 0; +} + +void TMyString::sAddOn8Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 10))return; + + d = data/10000000; + e = d % 10; + dest[pst] = e + '0'; + + d = data/1000000; + e = d % 10; + dest[pst+1] = e + '0'; + + d = data/100000; + e = d % 10; + dest[pst+2] = e + '0'; + + d = data/10000; + e = d % 10; + dest[pst+3] = e + '0'; + + d = data/1000; + e = d % 10; + dest[pst+4] = e + '0'; + + d = data/100; + e = d % 10; + dest[pst+5] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+6] = e + '0'; + + e = data % 10; + dest[pst+7] = e + '0'; + + dest[pst+8] = 0; +} + +void TMyString::sAddOn7Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 9))return; + + d = data/1000000; + e = d % 10; + dest[pst] = e + '0'; + + d = data/100000; + e = d % 10; + dest[pst+1] = e + '0'; + + d = data/10000; + e = d % 10; + dest[pst+2] = e + '0'; + + d = data/1000; + e = d % 10; + dest[pst+3] = e + '0'; + + d = data/100; + e = d % 10; + dest[pst+4] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+5] = e + '0'; + + e = data % 10; + dest[pst+6] = e + '0'; + + dest[pst+7] = 0; +} + +void TMyString::sAddOn6Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 8))return; + + d = data/100000; + e = d % 10; + dest[pst] = e + '0'; + + d = data/10000; + e = d % 10; + dest[pst+1] = e + '0'; + + d = data/1000; + e = d % 10; + dest[pst+2] = e + '0'; + + d = data/100; + e = d % 10; + dest[pst+3] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+4] = e + '0'; + + e = data % 10; + dest[pst+5] = e + '0'; + + dest[pst+6] = 0; +} + + +void TMyString::sAddOn5Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 7))return; + + d = data/10000; + e = d % 10; + dest[pst] = e + '0'; + + d = data/1000; + e = d % 10; + dest[pst+1] = e + '0'; + + d = data/100; + e = d % 10; + dest[pst+2] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+3] = e + '0'; + + e = data % 10; + dest[pst+4] = e + '0'; + + dest[pst+5] = 0; +} + + +void TMyString::sAddOn4Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 7))return; + + d = data/1000; + e = d % 10; + dest[pst] = e + '0'; + + d = data/100; + e = d % 10; + dest[pst+1] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+2] = e + '0'; + + e = data % 10; + dest[pst+3] = e + '0'; + + dest[pst+4] = 0; +} + + +void TMyString::sAddOn3Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 5))return; + + d = data/100; + e = d % 10; + dest[pst] = e + '0'; + + d = data/10; + e = d % 10; + dest[pst+1] = e + '0'; + + e = data % 10; + dest[pst+2] = e + '0'; + + dest[pst+3] = 0; +} + +void TMyString::sAddOn1Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 5))return; + + e = data % 10; + dest[pst] = e + '0'; + + dest[pst+1] = 0; +} + +void TMyString::sAddOn_N_Dg(int aN, unsigned int d, char *dest) +{ + switch(aN){ + case 1: sAddOn1Dg(d,dest);break; + case 2: sAddOn2Dg(d,dest);break; + case 3: sAddOn3Dg(d,dest);break; + case 4: sAddOn4Dg(d,dest);break; + case 5: sAddOn5Dg(d,dest);break; + case 6: sAddOn6Dg(d,dest);break; + case 7: sAddOn7Dg(d,dest);break; + case 8: sAddOn8Dg(d,dest);break; + } +} + +void TMyString::sAddOn2Dg(unsigned int data, char *dest) +{ + unsigned int i; + unsigned int d,e; + int pst = 0; + for(i=0; i<(dMYSTRING_LENGTH-1); i++){ + if(dest[i] != 0)pst++; + else break; + } + pst; + if(pst > (dMYSTRING_LENGTH - 5))return; + + d = data/10; + e = d % 10; + dest[pst] = e + '0'; + + e = data % 10; + dest[pst+1] = e + '0'; + + dest[pst+2] = 0; +} + +int TMyString::sGetLen(char *source) +{ + int i,aLen; + aLen = 0; + for(i=0; i<1024; i++){ + if(*source !=0 ){ + aLen++; + }else{ + break; + } + source++; + } + return aLen; +} + +void TMyString::FillFixLen(unsigned int aLen) +{ + unsigned int len, i; + len = sGetLen(Text); + for(i=len; i< aLen; i++){ + Text[i] = ' '; + } + Text[aLen] = 0; +} + +void TMyString::sFillFixLen(char *source, unsigned int aLen) +{ + unsigned int len, i; + len = sGetLen(source); + for(i=len; i< aLen; i++){ + source[i] = ' '; + } + source[aLen] = 0; +} + + +void TMyString::BrokeFixLen(int aLen) +{ + int i; + int aFirst; + int FoundCnStart; + aFirst = 0; + FoundCnStart = 0; + for(i=0; i-1){ + Text[i] = 0; + } + } +} + +void TMyString::sBrokeFixLen(char *source, int aLen) +{ + int i; + int aFirst; + int FoundCnStart; + aFirst = 0; + FoundCnStart = 0; + for(i=0; i-1){ + source[i] = 0; + } + } +} + +void TMyString::sClear(char *dest) +{ + dest[0] = 0; + dest[1] = 0; + dest[2] = 0; + dest[3] = 0; +} + +int TMyString::sToInteger(char *Src) +{ + signed int Result; + unsigned int i; + unsigned int sig; + + if(Src[0] == '-'){ + sig = 0; + i = 1; + }else{ + sig = 1; + i = 0; + } + Result = 0; + while(1){ + if(Src[i] < '0' || Src[i] > '9'){ + if(Src[i] == 0) break; + Result = 0; + break; + }else{ + Result *= 10; + Result += Src[i] - '0'; + } + i++; + } + if(sig == 0) Result = 0 - Result; + return Result; +} + +int TMyString::sCompStr32Char(char *pStr1, char *pStr2) +{ + for(int i=0; i<32; i++){ + if(pStr1[i] != pStr2[i])return -1; + if(pStr1[i] == 0){ + break; + } + } + return 0; +} + + + + + + + + + + + diff --git a/MyCode/Gui/my_string.h b/MyCode/Gui/my_string.h new file mode 100644 index 0000000..bad4c46 --- /dev/null +++ b/MyCode/Gui/my_string.h @@ -0,0 +1,91 @@ +#ifndef MY_STRING_H_ +#define MY_STRING_H_ + +#include"GraphBase.h" + +#define dMYSTRING_LENGTH 68 + +class TMyString{ + private: + char TmpChar[dMYSTRING_LENGTH]; + public: + char Text[dMYSTRING_LENGTH]; + public: + void Clear(void); + + void FromInt(int d); + void FromUInt(unsigned int d); + + void FromUInt8Dg(unsigned int data); + void FromUInt6Dg(unsigned int data); + void FromUInt4Dg(unsigned int data); + void FromUInt3Dg(unsigned int data); + void FromUInt2Dg(unsigned int data); + + int GetLength(void); + int GetEndPst(void); + void AddOnDgMax6(unsigned int data); + void AddOn8Dg(unsigned int data); + void AddOn6Dg(unsigned int data); + void AddOn4Dg(unsigned int data); + void AddOn3Dg(unsigned int data); + void AddOn2Dg(unsigned int data); + + void FormFloat(float fd); + int ToInteger(void); + float ToFloat(void); + + + void FromStr(const char *source); + void FromStr( char *source); + void FromStr(unsigned char *source); + void AddOnStr(const char *source); + void AddOnStr( char *source); + void ToStr(char *Dest, unsigned int len); + int Insert(const char *source, int Pst); + int Insert(char *source, int Pst); + unsigned int Delete(int Pst); + + void FillFixLen(unsigned int aLen); + void BrokeFixLen(int aLen); + + static void sClear(char *dest); + static void sFromStr(char *source, char *dest); + static void sFromStr(const char *source, char *dest); + static void sAddOnChar(char aCr, char *dest); + static void sAddOnStrL32(unsigned char *source, char *dest); + static void sAddOnStrL32(char *source, char *dest); + static void sFrom2Dg(unsigned int d, char *dest); + static void sFrom3Dg(unsigned int d, char *dest); + static void sFrom4Dg(unsigned int d, char *dest); + static void sFromUInt(unsigned int data, unsigned char *Text); + static void sAddOnStr(const char *source, char *dest); + static void sAddOnStr(unsigned char *source, char *dest); + static void sAddOnDgMax6(unsigned int data, char *dest); + static void sAddOn8Dg(unsigned int d, char *dest); + static void sAddOn7Dg(unsigned int d, char *dest); + static void sAddOn6Dg(unsigned int d, char *dest); + static void sAddOn5Dg(unsigned int d, char *dest); + static void sAddOn4Dg(unsigned int d, char *dest); + static void sAddOn3Dg(unsigned int d, char *dest); + static void sAddOn2Dg(unsigned int d, char *dest); + static void sAddOn1Dg(unsigned int d, char *dest); + static void sAddOn_N_Dg(int aN, unsigned int d, char *dest); + static int sGetLen(char *source); + static void sFillFixLen(char *source, unsigned int aLen); + static void sBrokeFixLen(char *source, int aLen); + static int sToInteger(char *Src); + static int sCompStr32Char(char *pStr1, char *pStr2); +}; + + +#endif + + + + + + + + + diff --git a/MyCode/Gui/uInportExport.cpp b/MyCode/Gui/uInportExport.cpp new file mode 100644 index 0000000..41cb08d --- /dev/null +++ b/MyCode/Gui/uInportExport.cpp @@ -0,0 +1,500 @@ +#include "RuntimeData.h" +#include "uInportExport.h" + + + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "uart_key_drv.h" + #include "HW_config.h" +} + +#define dWdClr clSkyBlue +#define dWdDisabelClr clNearWhite + +#define dWWidth 24 +#define dWHeigh 24 +#define dRoundR 7 + +const int xFirst = 10; +const int xSec = 150; +const int xThi = 290; +const int xFourth = 430; +const int xFifth = 570; + +void TuInportExport::Init() +{ + CtlIndex = 0; + IsShowing = 0; + IsOnGoing = 0; + ReadWrite =0; + + State.Connection = Config.usbConState; + State.Rsv0 =0; + State.Rsv0 =1; + State.Rsv0 =2; + + IsPermission =0; +} + +void TuInportExport::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; TickU盘导入导出"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "U盘连接"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "配置数据导入"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "配置数据导出"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "历史数据导出"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[1] + 36, 120, 30, 7, clNearWhite, "全部", 38, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[1] + 36, 120, 30, 7, clNearWhite, "回路数据", 12, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[1] + 36, 120, 30, 7, clNearWhite, "联动数据", 12, clNearBlack); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[2] + 36, 120, 30, 7, clNearWhite, "全部", 38, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[2] + 36, 120, 30, 7, clNearWhite, "回路数据", 12, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[2] + 36, 120, 30, 7, clNearWhite, "联动数据", 12, clNearBlack); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "全部", 38, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "报警记录", 12, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "故障记录", 12, clNearBlack); + TRoundRect::sDrawBySize(xFourth, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "操作记录", 12, clNearBlack); + TRoundRect::sDrawBySize(xFifth, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "监管记录", 12, clNearBlack); + }else{ + TextRender_string24(Lv.Caption.Left + 10, Lv.Caption.Top +4, clNearWhite, CaptionColor, "Data Transmission->U-Disk"); + TextRender_string24(Lv.Grid.Left[0] + 10, Lv.Grid.Top[0] +6, clNearWhite, "U-Disk Connection"); + TextRender_string24(Lv.Grid.Left[1] + 10, Lv.Grid.Top[1] +6, clNearWhite, "Inport Configuration"); + TextRender_string24(Lv.Grid.Left[2] + 10, Lv.Grid.Top[2] +6, clNearWhite, "Export Configuration"); + TextRender_string24(Lv.Grid.Left[3] + 10, Lv.Grid.Top[3] +6, clNearWhite, "Export Record"); + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[1] + 36, 120, 30, 7, clNearWhite, "All", 38, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[1] + 36, 120, 30, 7, clNearWhite, "Loop Cfg", 12, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[1] + 36, 120, 30, 7, clNearWhite, "Link-Exp", 12, clNearBlack); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[2] + 36, 120, 30, 7, clNearWhite, "All", 38, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[2] + 36, 120, 30, 7, clNearWhite, "Loop Cfg", 12, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[2] + 36, 120, 30, 7, clNearWhite, "Link-Exp", 12, clNearBlack); + + TRoundRect::sDrawBySize(xFirst, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "All", 38, clNearBlack); + TRoundRect::sDrawBySize(xSec, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "Fire ALM", 12, clNearBlack); + TRoundRect::sDrawBySize(xThi, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, " Fault ", 12, clNearBlack); + TRoundRect::sDrawBySize(xFourth, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "Operating", 6, clNearBlack); + TRoundRect::sDrawBySize(xFifth, Lv.Grid.Top[3] + 36, 120, 30, 7, clNearWhite, "supervi ", 12, clNearBlack); + } +} + +void TuInportExport::DrawSelf(void) +{ + RenderBackGround(); + RectFillRender(Lv.Caption.Left, Lv.Caption.Top, Lv.Caption.Right, Lv.Caption.Bottom, CaptionColor); + + for(int i=0; iInitBackEnd(); + + PrintInf.pMsg->MsgFire = &QueryMessageFire; + PrintInf.pMsg->MsgLinkage = &QueryMsgLinkage; + PrintInf.pMsg->MsgSv = &QueryMsgSv; + PrintInf.pMsg->MsgFault = &QueryMsgFault; + PrintInf.pMsg->MsgOperate = &QueryMsgOperate; + + PrintInf.pMsg->MsgFire->InitBackEnd(); + PrintInf.pMsg->MsgLinkage->InitBackEnd(); + PrintInf.pMsg->MsgSv->InitBackEnd(); + PrintInf.pMsg->MsgFault->InitBackEnd(); + PrintInf.pMsg->MsgOperate->InitBackEnd(); + + PrintInf.Show(); + return 1; + } + return 0; +} + +unsigned int ActList_2_Call(unsigned char aActList) +{ + if(aActList == 0){ + //设置工程名称 + ProjectSet.Init(); + ProjectSet.pDpt = &DesignPrmSet; + ProjectSet.aPanel = &CommonPanel; + ProjectSet.Show(); + ProjectSet.pDpt->Init(); + ProjectSet.ShowDesignedCount(); + return 1; + }else + if(aActList == 1){ + Maintain.Init() ; + Maintain.aPanel = &CommonPanel; + Maintain.InitPanel(); + Maintain.Show(); + Maintain.LoadData(); + return 1; + }else + if(aActList == 2){ + //设置运行模式 + RunModeCfg.Init() ; + RunModeCfg.aPanel = &CommonPanel; + RunModeCfg.InitPanel(); + RunModeCfg.Show(); + RunModeCfg.LoadData(); + return 1; + }else + if(aActList == 3){ + DevAuthorize.Init() ; + DevAuthorize.aPanel = &CommonPanel; + DevAuthorize.Show(); + DevAuthorize.InitPanel(); + DevAuthorize.LoadData(); + return 1; + }else + if(aActList == 4){ + //设计数量 + DesignPrmSet.Init() ; + DesignPrmSet.IconList = &ImageList; + DesignPrmSet.aPanel = &CommonPanel; + DesignPrmSet.LoadBaseTypeList(); + DesignPrmSet.Show(); + DesignPrmSet.InitPanel(); + return 1; + }else + if(aActList == 5){ + DevOutputCfg.Init(); + DevOutputCfg.IList = &ItemList; + DevOutputCfg.KeepOnMeJustEnter = KeepInUiJustEnter; + DevOutputCfg.KeepUiOnMe = KeepInUiOperating; + DevOutputCfg.Show(); + return 1; + }else + if(aActList == 6){ + DevSensitiveCfg.Init(); + DevSensitiveCfg.IList = &ItemList; + DevSensitiveCfg.KeepOnMeJustEnter = KeepInUiJustEnter; + DevSensitiveCfg.KeepUiOnMe = KeepInUiOperating; + DevSensitiveCfg.Show(); + return 1; + }else + if(aActList == 7){ + DevVaCfg.Init(); + DevVaCfg.IList = &ItemList; + DevVaCfg.KeepOnMeJustEnter = KeepInUiJustEnter; + DevVaCfg.KeepUiOnMe = KeepInUiOperating; + DevVaCfg.Show(); + return 1; + }else + if(aActList == 8){ + DisplayPadDescpDownload.pPanel = &CommonPanel; + DisplayPadDescpDownload.Show(); + return 1; + } + return 0; +} + +unsigned int ActList_3_Call(unsigned char aActList) +{ + if(aActList == 0){ + ListViewDevice.Init(); + ListViewDevice.ClearPath(); + ListViewDevice.ViewPath = 0; + ListViewDevice.LoadPath0(); + ListViewDevice.LoadPath0Item(); + ListViewDevice.aPanel = &CommonPanel; + ListViewDevice.IList = &ItemList; + ListViewDevice.DevProperty = &DevProperty; + ListViewDevice.Show(); + return 1; + }else + if(aActList == 1){ + LiteIconOverViewDev.Init(0, 36, 800, 406, 0, 0, clNearWhite); + LiteIconOverViewDev.SetIconPosition(); + LiteIconOverViewDev.ClearPath(); + LiteIconOverViewDev.LoadPath0(); + LiteIconOverViewDev.ViewPath = 0; + LiteIconOverViewDev.Show(); + return 1; + }else + if(aActList == 2){ + DevProperty.Init(TDevProperty::htNoType, 0); + DevProperty.aPanel = &CommonPanel; + DevProperty.IList = &ItemList; + DevProperty.IList->RealtimeData.Reset(); + DevProperty.IList->TextOutClear(); + DevProperty.SetPath(MainCtl.fData.Split.MyNum, 1, 1); + DevProperty.Show(); + DevProperty.Init4DType(); + DevProperty.DrawCommonInfTitle(); + DevProperty.RenewCommonInf(); + + //CircuitCfg.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + //CircuitCfg.aPanel = &CommonPanel; + //CircuitCfg.Show(); + //CircuitCfg.InitPanel(); + return 1; + }else + if(aActList == 3){ + DevStartStop.Init(TDevProperty::htNoType, 0) ; + DevStartStop.aPanel = &CommonPanel; + DevStartStop.IList = &ItemList; + DevStartStop.IList->RealtimeData.Reset(); + DevStartStop.IList->TextOutClear(); + DevStartStop.SetPath(MainCtl.fData.Split.MyNum, 1, 1); + DevStartStop.Show(); + DevStartStop.Init4DType(); + DevStartStop.DrawCommonInfTitle(); + DevStartStop.RenewCommonInf(); + return 1; + }else + if(aActList == 4){ + //回路设备自动注册 + Register.Init() ; + Register.IList = &ItemList; + Register.aMc = &MainCtlReg; + Register.Show(); + //Register.aMc->Init(); + return 1; + }else + if(aActList == 5){ + //回路设备手动注册 + RegisterManual.Init() ; + RegisterManual.IList = &ItemList; + RegisterManual.Show(); + return 1; + }else + if(aActList == 6){ + //设置设备屏蔽 + DevMask.Init(); + DevMask.IList = &ItemList; + DevMask.Show(); + return 1; + }else + if(aActList == 7){ + DuplicateCheck.Init() ; + DuplicateCheck.KeepOnMeJustEnter = KeepInUiJustEnter; + DuplicateCheck.KeepUiOnMe = KeepInUiOperating; + DuplicateCheck.Show(); + return 1; + }else + if(aActList == 8){ + DevCount.Init(); + DevCount.Show(); + return 1; + } + if(aActList == 9){ + //注释设置 + DescpWrite.Init(); + DescpWrite.aPanel = &CommonPanel; + DescpWrite.IList = &ItemList; + DescpWrite.IList->RealtimeData.Reset(); + DescpWrite.IList->TextOutClear(); + DescpWrite.Show(); + return 1; + } + + return 0; +} + +unsigned int ActList_4_Call(unsigned char aActList) +{ + if(aActList == 0){ + PadInf.Init(); + PadInf.BusPad = &BusPadLnk; + PadInf.DirectPad = &DirectPadCfg; + PadInf.LoadItem(); + PadInf.Show(); + return 1; + }else + if(aActList == 1){ + //设置多线盘 + DirectPadCfg.Init(0); + DirectPadCfg.aPanel = &CommonPanel; + DirectPadCfg.IList = &ItemList; + DirectPadCfg.Show(); + DirectPadCfg.SetPath(0,1,1); + return 1; + }else + if(aActList == 2){ + //设置总线盘联动编程 + BusPadLnk.Init(0); + BusPadLnk.aPanel = &CommonPanel; + BusPadLnk.IList = &ItemList; + BusPadLnk.Show(); + BusPadLnk.SetPath(0,1,1); + return 1; + } + return 0; +} + + +unsigned int ActList_5_Call(unsigned char aActList) +{ + if(aActList == 0){ + //设置联动编程 + LinkageList.Init(); + LinkageList.Show(); + return 1; + }else + if(aActList == 1){ + //设置联动编程 + LinkageProgram.Init(); + LinkageProgram.EnterMethod = 0; + LinkageProgram.Show(); + //LinkageProgram.DrawTip(); + LinkageProgram.InitPanel(); + return 1; + }else + if(aActList == 2){ + //声光与广播交替 + BroadcastCfg.Init(); + BroadcastCfg.IList = &ItemList; + BroadcastCfg.Show(); + BroadcastCfg.InitPanel(); + return 1; + }else + if(aActList == 3){ + //允许与禁止 + Allow.Init(0, 36, 800, 406, 0, 0, clNearWhite); + Allow.IList = &ItemList; + Allow.Show(); + Allow.InitPanel(); + return 1; + }else + if(aActList == 4){ + return 0; + //FECBus + LnkFecBusCfg.Init() ; + LnkFecBusCfg.Show(); + LnkFecBusCfg.InitPanel(); + return 1; + }else + if(aActList == 5){ + //Area Assign + AreaCfg.Init(); + AreaCfg.IList = &ItemList; + AreaCfg.aPanel = &CommonPanel; + AreaCfg.Show(); + AreaCfg.LoadData(); + return 1; + //清除组网机器 + //PowerSuplyCfg.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + //PowerSuplyCfg.aPanel = &CommonPanel; + //PowerSuplyCfg.Show(); + //PowerSuplyCfg.InitPanel(); + //return 1; + }else + if(aActList == 6){ + //用户码设置 + //DeviceSetup.Init(0, 36, 800, 406, 0, 0, clMoneyGreen); + //DeviceSetup.aPanel = &CommonPanel; + //DeviceSetup.Show(); + //DeviceSetup.InitPanel(); + UserCodeSet.Init(); + UserCodeSet.IList = &ItemList; + UserCodeSet.aPanel = &CommonPanel; + UserCodeSet.Show(); + UserCodeSet.LoadData(); + return 1; + }else + if(aActList == 7){ + UserCodeSetByArea.Init(); + UserCodeSetByArea.IList = &ItemList; + UserCodeSetByArea.aPanel = &CommonPanel; + UserCodeSetByArea.Show(); + UserCodeSetByArea.LoadData(); + return 1; + } + + return 0; +} + +unsigned int ActList_6_Call(unsigned char aActList) +{ + if(aActList == 0){ + //ECanNetwork.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + //ECanNetwork.LoadSysCfg(); + //ECanNetwork.Show(); + //ECanNetwork.aPanel = &CommonPanel; + //ECanNetwork.InitPanel(); + //ECanNetwork.DrawAllItems(); + CanNetworkInf.Init(); + CanNetworkInf.Show(); + return 1; + } + if(aActList == 1){ + //组网机器自动注册 + //fNetworkReg.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + //fNetworkReg.aPanel = &CommonPanel; + //fNetworkReg.Show(); + //fNetworkReg.InitPanel(); + CanNetworkRegister.Init(); + CanNetworkRegister.IList = &ItemList; + CanNetworkRegister.Show(); + return 1; + } + if(aActList == 2){ + CanNetworkMask.Init(); + CanNetworkMask.IList = &ItemList; + CanNetworkMask.Show(); + return 1; + } + if(aActList == 3){ + //图形显示装置配置 + GraphDevCfg.Init(); + GraphDevCfg.IList = &ItemList; + GraphDevCfg.Show(); + return 1; + } + return 0; +} + +unsigned int ActList_7_Call(unsigned char aActList) +{ + if(aActList == 0){ + //在线系统安装调试 + OnlineCtrl.Init(); + OnlineCtrl.Show(); + return 1; + }else + if(aActList == 1){ + //U盘 + uInportExport.Init() ; + uInportExport.Show(); + return 1; + }else + if(aActList == 2){ + BlueTooth.Init() ; + BlueTooth.Show(); + return 1; + }else + if(aActList == 3){ + //AuthorizeState.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + //AuthorizeState.Show(); + //return 1; + WifiConn.Init() ; + WifiConn.Show(); + return 1; + }else + if(aActList == 4){ + //aBefore.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + //aBefore.aPanel = &CommonPanel; + //aBefore.Show(); + //aBefore.InitPanel(); + //return 1; + TransmiteDev.Init(); + TransmiteDev.Show(); + return 1; + }else + if(aActList == 5){ + FwUpgrade.Init() ; + FwUpgrade.Show(); + return 1; + } + return 0; +} + +unsigned int ActList_8_Call(unsigned char aActList) +{ + if(aActList == 0){ + ClearRegistedInf.Init() ; + ClearRegistedInf.sIList = &ItemList; + ClearRegistedInf.Show(); + return 1; + }else + if(aActList == 1){ + ClearLinkageCfg.Init(); + ClearLinkageCfg.sIList = &ItemList; + ClearLinkageCfg.Show(); + return 1; + }else + if(aActList == 2){ + ClearDescp.Init(); + ClearDescp.Show(); + return 1; + }else + if(aActList == 3){ + RecoverAll.Init(); + RecoverAll.DoRecover = SysDoRecover; + RecoverAll.Show(); + return 1; + }else + if(aActList == 4){ + + } + return 0; +} + +unsigned int ActList_9_Call(unsigned char aActList) +{ + if(aActList == 0){ + AboutUs.Init(0, 36, 800, 406, 0, 0, clMoneyGreen) ; + AboutUs.Show(); + return 1; + } + if(aActList == 1){ + + } + if(aActList == 2){ + + } + if(aActList == 3){ + + } + return 0; +} + +//_________________________________________________________________________________________ +/*/ +TGuiMsgReturn ActList_0_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + + if(ActList_0 == 0){ + aGMR = CommonPanel.GuiLoginII_KeyIn(aKey); + CommonPanel.Edit[0].Show(); + if(aGMR == guiMsgOkAndReturn){ + SystemPermission = 2; + MainMenu.LoadPermission(SystemPermission); + aGMR = guiMsgReturn; + } + }else + if(ActList_0 == 1){ + aGMR = CommonPanel.GuiLoginIII_KeyIn(aKey); + CommonPanel.Edit[0].Show(); + if(aGMR == guiMsgOkAndReturn){ + SystemPermission = 3; + MainMenu.LoadPermission(SystemPermission); + aGMR = guiMsgReturn; + } + }else + if(ActList_0 == 2){ + aGMR = MessageBox.KeyIn(aKey); + if(aGMR == guiMsgOkAndReturn){ + SystemPermission = 1; + MainMenu.LoadPermission(SystemPermission); + aGMR = guiMsgReturn; + } + } + return aGMR; +} +*/ +/* + + //回路设备运行电压 + aGMR = RootDevVoltage.KeyIn(aKey); + + aGMR = RealTimeData.KeyIn(aKey); + + //探测器模拟曲线 + aGMR = DetectorCurve.KeyIn(aKey); + + + aGMR = SimRun.KeyIn(aKey); + + + + + //楼层显示 + aGMR = DisplayPadCfg.KeyIn(aKey); + + + + + //查询注释 + aGMR = DescpWrite.KeyIn(aKey); + //aGMR = UserSet.KeyIn(aKey); + + + //查询本机配置 + aGMR = QueryCfg.KeyIn(aKey); + + + //查询网络配置 + aGMR = QueryCfg.KeyIn(aKey); + + aGMR = aBefore.KeyIn(aKey); + aGMR = AuthorizeState.KeyIn(aKey); +*/ + +TGuiMsgReturn ActList_0_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_0 == 0){ + aGMR = HwInf.KeyIn(aKey); + }else + if(ActList_0 == 1){ + aGMR = PowerSuplyInf.KeyIn(aKey); + }else + if(ActList_0 == 2){ + //设置打印机 + //设置打印事件 + aGMR = PrinterSet.KeyIn(aKey); + }else + if(ActList_0 == 3){ + aGMR = DateTimeCfg.KeyIn(aKey); + }else + if(ActList_0 == 4){ + aGMR = PasswdChange.KeyIn(aKey); + }else + if(ActList_0 == 5){ + //设置屏保时间 + aGMR = ScreenSaveCfg.KeyIn(aKey); + }else + if(ActList_0 == 6){ + //Language + aGMR = LanguageCfg.KeyIn(aKey); + } + return aGMR; +} + +TGuiMsgReturn ActList_1_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_1 == 0){ + aGMR = QueryMsg.KeyIn(aKey); + }else + if(ActList_1 == 1){ + aGMR = QueryMessageFire.KeyIn(aKey); + }else + if(ActList_1 == 2){ + aGMR = QueryMsgLinkage.KeyIn(aKey); + }else + if(ActList_1 == 3){ + aGMR = QueryMsgSv.KeyIn(aKey); + }else + if(ActList_1 == 4){ + aGMR = QueryMsgFault.KeyIn(aKey); + }else + if(ActList_1 == 5){ + aGMR = QueryMsgOperate.KeyIn(aKey); + }else + if(ActList_1 == 6){ + aGMR = PrintInf.KeyIn(aKey); + } + return aGMR; +} + +TGuiMsgReturn ActList_2_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_2 == 0){ + //设置工程 + aGMR = ProjectSet.KeyIn(aKey); + }else + if(ActList_2 == 1){ + aGMR = Maintain.KeyIn(aKey); + }else + if(ActList_2 == 2){ + //设置运行模式 + aGMR = RunModeCfg.KeyIn(aKey); + }else + if(ActList_2 == 3){ + aGMR = DevAuthorize.KeyIn(aKey); + }else + if(ActList_2 == 4){ + aGMR = DesignPrmSet.KeyIn(aKey); + }else + if(ActList_2 == 5){ + aGMR = DevOutputCfg.KeyIn(aKey); + }else + if(ActList_2 == 6){ + aGMR = DevSensitiveCfg.KeyIn(aKey); + }else + if(ActList_2 == 7){ + aGMR = DevVaCfg.KeyIn(aKey); + }else + if(ActList_2 == 8){ + aGMR = DisplayPadDescpDownload.KeyIn(aKey); + } + + return aGMR; +} + +TGuiMsgReturn ActList_3_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_3 == 0){ + aGMR = ListViewDevice.KeyIn(aKey); + }else + if(ActList_3 == 1){ + aGMR = LiteIconOverViewDev.KeyIn(aKey); + }else + if(ActList_3 == 2){ + //回路设备在线配置 + aGMR = DevProperty.KeyIn(aKey); + //aGMR = CircuitCfg.KeyIn(aKey); + }else + if(ActList_3 == 3){ + aGMR = DevStartStop.KeyIn(aKey); + }else + if(ActList_3 == 4){ + aGMR = Register.KeyIn(aKey); + }else + if(ActList_3 == 5){ + aGMR = RegisterManual.KeyIn(aKey); + }else + if(ActList_3 == 6){ + aGMR = DevMask.KeyIn(aKey); + }else + if(ActList_3 == 7){ + //回路重号检测 + aGMR = DuplicateCheck.KeyIn(aKey); + }else + if(ActList_3 == 8){ + aGMR = DevCount.KeyIn(aKey); + }else + if(ActList_3 == 9){ + aGMR = DescpWrite.KeyIn(aKey); + } + return aGMR; +} + +TGuiMsgReturn ActList_4_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_4 == 0){ + aGMR = PadInf.KeyIn(aKey); + }else + if(ActList_4 == 1){ + aGMR = DirectPadCfg.KeyIn(aKey); + }else + if(ActList_4 == 2){ + aGMR = BusPadLnk.KeyIn(aKey); + } + return aGMR; +} + + + +TGuiMsgReturn ActList_5_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_5 == 0){ + //查询联动编程 + aGMR = LinkageList.KeyIn(aKey); + }else + if(ActList_5 == 1){ + //联动编程 + aGMR = LinkageProgram.KeyIn(aKey); + }else + if(ActList_5 == 2){ + //声光与广播交替 + aGMR = BroadcastCfg.KeyIn(aKey); + }else + if(ActList_5 == 3){ + //允许与禁止 + aGMR = Allow.KeyIn(aKey); + }else + if(ActList_5 == 4){ + aGMR = LnkFecBusCfg.KeyIn(aKey); + }else + if(ActList_5 == 5){ + aGMR = AreaCfg.KeyIn(aKey); + }else + if(ActList_5 == 6){ + //aGMR = DeviceSetup.KeyIn(aKey); + //aGMR = uInportExport.KeyIn(aKey); + aGMR = UserCodeSet.KeyIn(aKey); + }else + if(ActList_5 == 7){ + //aGMR = DeviceSetup.KeyIn(aKey); + //aGMR = uInportExport.KeyIn(aKey); + aGMR = UserCodeSetByArea.KeyIn(aKey); + }else + if(ActList_5 == 8){ + //清除处理 + aGMR = CleanUp.KeyIn(aKey); + } + return aGMR; +} + +TGuiMsgReturn ActList_6_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_6 == 0){ + //aGMR = ECanNetwork.KeyIn(aKey); + aGMR = CanNetworkInf.KeyIn(aKey); + }else + if(ActList_6 == 1){ + aGMR = CanNetworkRegister.KeyIn(aKey); + }else + if(ActList_6 == 2){ + aGMR = CanNetworkMask.KeyIn(aKey); + }else + if(ActList_6 == 3){ + aGMR = GraphDevCfg.KeyIn(aKey); + } + return aGMR; +} + +TGuiMsgReturn ActList_7_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + if(ActList_7 == 0){ + aGMR = OnlineCtrl.KeyIn(aKey); + }else + if(ActList_7 == 1){ + aGMR = uInportExport.KeyIn(aKey); + }else + if(ActList_7 == 2){ + aGMR = BlueTooth.KeyIn(aKey); + }else + if(ActList_7 == 3){ + aGMR = WifiConn.KeyIn(aKey); + }else + if(ActList_7 == 4){ + aGMR = TransmiteDev.KeyIn(aKey); + }else + if(ActList_7 == 5){ + aGMR = FwUpgrade.KeyIn(aKey); + } + return aGMR; +} + +TGuiMsgReturn ActList_8_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + + if(ActList_8 == 0){ + aGMR = ClearRegistedInf.KeyIn(aKey); + }else + if(ActList_8 == 1){ + aGMR = ClearLinkageCfg.KeyIn(aKey); + }else + if(ActList_8 == 2){ + aGMR = ClearDescp.KeyIn(aKey); + }else + if(ActList_8 == 3){ + aGMR = RecoverAll.KeyIn(aKey); + }else + if(ActList_8 == 4){ + //aGMR = ClearRegistedInf.KeyIn(aKey); + } + return aGMR; +} + + +TGuiMsgReturn ActList_9_ToDo(unsigned char aKey) +{ + TGuiMsgReturn aGMR = guiMsgNone; + + if(ActList_9 == 0){ + + }else + if(ActList_9 == 1){ + + }else + if(ActList_9 == 2){ + + }else + if(ActList_9 == 3){ + + } + return aGMR; +} + +/* + + + //探测器模拟曲线 + aRb = DetectorCurve.ExtRequst(Prm); + + aRb = RealTimeData.ExtRequst(Prm); + + + + + + + + + //查询注释 + aRb = DescpWrite.ExtRequst(Prm); + + + + + + //楼层显示 + aRb = DisplayPadCfg.ExtRequst(Prm); + + + + + + //查询本机配置 + aRb = QueryCfg.ExtRequst(Prm); + + //查询网络配置 + aRb = QueryCfg.ExtRequst(Prm); + + aRb = AuthorizeState.ExtRequst(Prm); + aRb = aBefore.ExtRequst(Prm); +*/ + +int ActList_0_CallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_0 == 0){ + aRb = HwInf.ExtRequst(Prm); + }else + if(ActList_0 == 1){ + aRb = PowerSuplyInf.ExtRequst(Prm); + }else + if(ActList_0 == 2){ + //设置打印机 + //设置打印事件 + aRb = PrinterSet.ExtRequst(Prm); + }else + if(ActList_0 == 3){ + aRb = DateTimeCfg.ExtRequst(Prm); + }else + if(ActList_0 == 4){ + aRb = PasswdChange.ExtRequst(Prm); + }else + if(ActList_0 == 5){ + //设置屏保时间 + aRb = ScreenSaveCfg.ExtRequst(Prm); + }else + if(ActList_0 == 6){ + aRb = LanguageCfg.ExtRequst(Prm); + } + return aRb; +} + +int ActList_1_CallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_1 == 0){ + aRb = QueryMsg.ExtRequst(Prm); + }else + if(ActList_1 == 1){ + aRb = QueryMessageFire.ExtRequst(Prm); + }else + if(ActList_1 == 2){ + aRb = QueryMsgLinkage.ExtRequst(Prm); + }else + if(ActList_1 == 3){ + aRb = QueryMsgSv.ExtRequst(Prm); + }else + if(ActList_1 == 4){ + aRb = QueryMsgFault.ExtRequst(Prm); + }else + if(ActList_1 == 5){ + aRb = QueryMsgOperate.ExtRequst(Prm); + }else + if(ActList_1 == 6){ + aRb = PrintInf.ExtRequst(Prm); + } + return aRb; +} + +int ActList_2_CallBack(unsigned char Prm) +{ + int aRb =-1; + if(ActList_2 == 0){ + //设置工程 + aRb = ProjectSet.ExtRequst(Prm); + }else + if(ActList_2 == 1){ + aRb = Maintain.ExtRequst(Prm); + }else + if(ActList_2 == 2){ + aRb = RunModeCfg.ExtRequst(Prm); + }else + if(ActList_2 == 3){ + + aRb = DevAuthorize.ExtRequst(Prm); + }else + if(ActList_2 == 4){ + aRb = DesignPrmSet.ExtRequst(Prm); + }else + if(ActList_2 == 5){ + aRb = DevOutputCfg.ExtRequst(Prm); + }else + if(ActList_2 == 6){ + aRb = DevSensitiveCfg.ExtRequst(Prm); + }else + if(ActList_2 == 7){ + aRb = DevVaCfg.ExtRequst(Prm); + }else + if(ActList_2 == 8){ + aRb = DisplayPadDescpDownload.ExtRequst(Prm); + } + + + return aRb; +} + +// aRb = SimRun.ExtRequst(Prm); +// //设备地址变更 + //aRb = AddrAssign.ExtRequst(Prm); +// + //回路设备运行电压 + //aRb = RootDevVoltage.ExtRequst(Prm); + +int ActList_3_CallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_3 == 0){ + aRb = ListViewDevice.ExtRequst(Prm); + }else + if(ActList_3 == 1){ + aRb = LiteIconOverViewDev.ExtRequst(Prm); + }else + if(ActList_3 == 2){ + //回路设备在线配置 + aRb = DevProperty.ExtRequst(Prm); + //aRb = CircuitCfg.ExtRequst(Prm); + }else + if(ActList_3 == 3){ + aRb = DevStartStop.ExtRequst(Prm); + }else + if(ActList_3 == 4){ + aRb = Register.ExtRequst(Prm); + }else + if(ActList_3 == 5){ + aRb = RegisterManual.ExtRequst(Prm); + }else + if(ActList_3 == 6){ + aRb = DevMask.ExtRequst(Prm); + }else + if(ActList_3 == 7){ + //回路重号检测 + aRb = DuplicateCheck.ExtRequst(Prm); + }else + if(ActList_3 == 8){ + aRb = DevCount.ExtRequst(Prm); + }else + if(ActList_3 == 9){ + aRb = DescpWrite.ExtRequst(Prm); + } + return aRb; +} + +int ActList_4_CallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_4 == 0){ + aRb = PadInf.ExtRequst(Prm); + }else + if(ActList_4 == 1){ + aRb = DirectPadCfg.ExtRequst(Prm); + }else + if(ActList_4 == 2){ + aRb = BusPadLnk.ExtRequst(Prm); + } + return aRb; +} + +int ActList_5_CallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_5 == 0){ + //查询联动编程 + aRb = LinkageList.ExtRequst(Prm); + }else + if(ActList_5 == 1){ + //联动编程 + aRb = LinkageProgram.ExtRequst(Prm); + }else + if(ActList_5 == 2){ + //声光与广播交替 + aRb = BroadcastCfg.ExtRequst(Prm); + }else + if(ActList_5 == 3){ + //允许与禁止 + aRb = Allow.ExtRequst(Prm); + }else + if(ActList_5 == 4){ + aRb =LnkFecBusCfg.ExtRequst(Prm); + }else + if(ActList_5 == 5){ + aRb =AreaCfg.ExtRequst(Prm); + }else + if(ActList_5 == 6){ + //aRb = DeviceSetup.ExtRequst(Prm); + //aRb = uInportExport.ExtRequst(Prm); + aRb =UserCodeSet.ExtRequst(Prm); + }else + if(ActList_5 == 7){ + //aRb = DeviceSetup.ExtRequst(Prm); + //aRb = uInportExport.ExtRequst(Prm); + aRb =UserCodeSetByArea.ExtRequst(Prm); + }else + if(ActList_5 == 8){ + //清除处理 + aRb = CleanUp.ExtRequst(Prm); + } + return aRb; +} + +int ActList_6_CallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_6 == 0){ + //aRb = ECanNetwork.ExtRequst(Prm); + aRb = CanNetworkInf.ExtRequst(Prm); + }else + if(ActList_6 == 1){ + aRb = CanNetworkRegister.ExtRequst(Prm); + }else + if(ActList_6 == 2){ + aRb = CanNetworkMask.ExtRequst(Prm); + }else + if(ActList_6 == 3){ + aRb = GraphDevCfg.ExtRequst(Prm); + } + return aRb; +} + +int ActList_7_CallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_7 == 0){ + aRb = OnlineCtrl.ExtRequst(Prm); + }else + if(ActList_7 == 1){ + aRb = uInportExport.ExtRequst(Prm); + }else + if(ActList_7 == 2){ + aRb = BlueTooth.ExtRequst(Prm); + }else + if(ActList_7 == 3){ + aRb = WifiConn.ExtRequst(Prm); + }else + if(ActList_7 == 4){ + aRb = TransmiteDev.ExtRequst(Prm); + }else + if(ActList_7 == 5){ + aRb = FwUpgrade.ExtRequst(Prm); + } + return aRb; +} + +int ActList_8_CallBack(unsigned char Prm) +{ + int aRb = -1; + + if(ActList_8 == 0){ + aRb = ClearRegistedInf.ExtRequst(Prm); + }else + if(ActList_8 == 1){ + aRb = ClearLinkageCfg.ExtRequst(Prm); + }else + if(ActList_8 == 2){ + aRb = ClearDescp.ExtRequst(Prm); + }else + if(ActList_8 == 3){ + aRb = RecoverAll.ExtRequst(Prm); + }else + if(ActList_8 == 4){ + aRb = -1; + } + return aRb; +} + +int ActList_9_CallBack(unsigned char Prm) +{ + int aRb = -1; + + if(ActList_9 == 0){ + + }else + if(ActList_9 == 1){ + + }else + if(ActList_9 == 2){ + + }else + if(ActList_9 == 3){ + + } + return aRb; +} + +/* + + RealTimeData.FullRedraw(Prm); + + + //探测器模拟曲线 + DetectorCurve.FullRedraw(Prm); + + + + + //查询本机配置 + QueryCfg.FullRedraw(Prm); + + + + + //楼层显示 + DisplayPadCfg.FullRedraw(Prm); + +AuthorizeState.FullRedraw(Prm); + aBefore.FullRedraw(Prm); + +*/ + +int ActList_0_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_0 == 0){ + HwInf.FullRedraw(Prm); + }else + if(ActList_0 == 1){ + PowerSuplyInf.FullRedraw(Prm); + }else + if(ActList_0 == 2){ + //设置打印机 + //设置打印事件 + PrinterSet.FullRedraw(Prm); + }else + if(ActList_0 == 3){ + DateTimeCfg.FullRedraw(Prm); + }else + if(ActList_0 == 4){ + PasswdChange.FullRedraw(Prm); + }else + if(ActList_0 == 5){ + //设置屏保时间 + ScreenSaveCfg.FullRedraw(Prm); + }else + if(ActList_0 == 6){ + LanguageCfg.FullRedraw(Prm); + } + return aRb; +} + +int ActList_1_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_1 == 0){ + QueryMsg.FullRedraw(Prm); + }else + if(ActList_1 == 1){ + QueryMessageFire.FullRedraw(Prm); + }else + if(ActList_1 == 2){ + QueryMsgLinkage.FullRedraw(Prm); + }else + if(ActList_1 == 3){ + QueryMsgSv.FullRedraw(Prm); + }else + if(ActList_1 == 4){ + QueryMsgFault.FullRedraw(Prm); + }else + if(ActList_1 == 5){ + QueryMsgOperate.FullRedraw(Prm); + }else + if(ActList_1 == 6){ + PrintInf.FullRedraw(Prm); + } + return aRb; +} + +int ActList_2_RedrawCallBack(unsigned char Prm) +{ + int aRb =-1; + if(ActList_2 == 0){ + //设置工程名称 + ProjectSet.FullRedraw(Prm); + }else + if(ActList_2 == 1){ + Maintain.FullRedraw(Prm); + }else + if(ActList_2 == 2){ + //设置运行模式 + RunModeCfg.FullRedraw(Prm); + }else + if(ActList_2 == 3){ + DevAuthorize.FullRedraw(Prm); + }else + if(ActList_2 == 4){ + DesignPrmSet.FullRedraw(Prm); + }else + if(ActList_2 == 5){ + DevOutputCfg.FullRedraw(Prm); + } else + if(ActList_2 == 6){ + DevSensitiveCfg.FullRedraw(Prm); + }else + if(ActList_2 == 7){ + DevSensitiveCfg.FullRedraw(Prm); + }else + if(ActList_2 == 8){ + DisplayPadDescpDownload.FullRedraw(Prm); + } + + + return aRb; +} + + +int ActList_3_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_3 == 0){ + ListViewDevice.FullRedraw(Prm); + }else + if(ActList_3 == 1){ + LiteIconOverViewDev.FullRedraw(Prm); + }else + if(ActList_3 == 2){ + //回路设备在线配置 + DevProperty.FullRedraw(Prm); + //CircuitCfg.FullRedraw(Prm); + }else + if(ActList_3 == 3){ + DevStartStop.FullRedraw(Prm); + }else + if(ActList_3 == 4){ + Register.FullRedraw(Prm); + }else + if(ActList_3 == 5){ + RegisterManual.FullRedraw(Prm); + }else + if(ActList_3 == 6){ + DevMask.FullRedraw(Prm); + }else + if(ActList_3 == 7){ + //回路重号检测 + DuplicateCheck.FullRedraw(Prm); + }else + if(ActList_3 == 8){ + //SimRun.FullRedraw(Prm); + DevCount.FullRedraw(Prm); + }else + if(ActList_3 == 9){ + //SimRun.FullRedraw(Prm); + DescpWrite.FullRedraw(Prm); + } + return aRb; +} + +int ActList_4_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_4 == 0){ + PadInf.FullRedraw(Prm); + }else + if(ActList_4 == 1){ + DirectPadCfg.FullRedraw(Prm); + }else + if(ActList_4 == 2){ + BusPadLnk.FullRedraw(Prm); + } + return aRb; +} + +int ActList_5_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_5 == 0){ + //查询联动编程 + LinkageList.FullRedraw(Prm); + }else + if(ActList_5 == 1){ + //联动编程 + LinkageProgram.FullRedraw(Prm); + }else + if(ActList_5 == 2){ + //声光与广播交替 + BroadcastCfg.FullRedraw(Prm); + }else + if(ActList_5 == 3){ + //允许与禁止 + Allow.FullRedraw(Prm); + }else + if(ActList_5 == 4){ + LnkFecBusCfg.FullRedraw(Prm); + }else + if(ActList_5 == 5){ + AreaCfg.FullRedraw(Prm); + }else + if(ActList_5 == 6){ + //DeviceSetup.FullRedraw(Prm); + //uInportExport.FullRedraw(Prm); + UserCodeSet.FullRedraw(Prm); + }else + if(ActList_5 == 7){ + //DeviceSetup.FullRedraw(Prm); + //uInportExport.FullRedraw(Prm); + UserCodeSetByArea.FullRedraw(Prm); + } + return aRb; +} + +int ActList_6_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_6 == 0){ + //ECanNetwork.FullRedraw(Prm); + CanNetworkInf.FullRedraw(Prm); + }else + if(ActList_6 == 1){ + CanNetworkRegister.FullRedraw(Prm); + }else + if(ActList_6 == 2){ + CanNetworkMask.FullRedraw(Prm); + }else + if(ActList_6 == 3){ + GraphDevCfg.FullRedraw(Prm); + } + return aRb; +} + +int ActList_7_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + if(ActList_7 == 0){ + OnlineCtrl.FullRedraw(Prm); + }else + if(ActList_7 == 1){ + uInportExport.FullRedraw(Prm); + }else + if(ActList_7 == 2){ + BlueTooth.FullRedraw(Prm); + }else + if(ActList_7 == 3){ + WifiConn.FullRedraw(Prm); + }else + if(ActList_7 == 4){ + TransmiteDev.FullRedraw(Prm); + }else + if(ActList_7 == 5){ + FwUpgrade.FullRedraw(Prm); + } + return aRb; +} + +int ActList_8_RedrawCallBack(unsigned char Prm) +{ + int aRb = -1; + + if(ActList_8 == 0){ + //清除处理 + ClearRegistedInf.FullRedraw(Prm); + //AboutUs.FullRedraw(Prm); + }else + if(ActList_8 == 1){ + //清除处理 + ClearLinkageCfg.FullRedraw(Prm); + }else + if(ActList_8 == 2){ + //清除处理 + ClearDescp.FullRedraw(Prm); + }else + if(ActList_8 == 3){ + //恢复出厂设置 + RecoverAll.FullRedraw(Prm); + + } + + return aRb; +} + + +int ActList_9_RedrawCallBack(unsigned char Prm) +{ + int aRb; + + if(ActList_9 == 0){ + + }else + if(ActList_9 == 1){ + + }else + if(ActList_9 == 2){ + + }else + if(ActList_9 == 3){ + + } + return aRb; +} + diff --git a/MyCode/src/ActionListCall.h b/MyCode/src/ActionListCall.h new file mode 100644 index 0000000..77d3eed --- /dev/null +++ b/MyCode/src/ActionListCall.h @@ -0,0 +1,71 @@ +#ifndef ACTIONLISTCALL_H_ +#define ACTIONLISTCALL_H_ + +#include "Gui.h" +#include "RuntimeData.h" +#include "Runtime.h" + + +extern unsigned int ActList_0_Call(unsigned char aActList); +extern unsigned int ActList_1_Call(unsigned char aActList); +extern unsigned int ActList_2_Call(unsigned char aActList); +extern unsigned int ActList_3_Call(unsigned char aActList); +extern unsigned int ActList_4_Call(unsigned char aActList); +extern unsigned int ActList_5_Call(unsigned char aActList); +extern unsigned int ActList_6_Call(unsigned char aActList); +extern unsigned int ActList_7_Call(unsigned char aActList); +extern unsigned int ActList_8_Call(unsigned char aActList); +extern unsigned int ActList_9_Call(unsigned char aActList); +extern unsigned int ActList_10_Call(unsigned char aActList); + +extern TGuiMsgReturn ActList_0_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_1_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_2_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_3_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_4_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_5_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_6_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_7_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_8_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_9_ToDo(unsigned char aKey); +extern TGuiMsgReturn ActList_10_ToDo(unsigned char aKey); + + +extern int ActList_0_CallBack(unsigned char Prm); +extern int ActList_1_CallBack(unsigned char Prm); +extern int ActList_2_CallBack(unsigned char Prm); +extern int ActList_3_CallBack(unsigned char Prm); +extern int ActList_4_CallBack(unsigned char Prm); +extern int ActList_5_CallBack(unsigned char Prm); +extern int ActList_6_CallBack(unsigned char Prm); +extern int ActList_7_CallBack(unsigned char Prm); +extern int ActList_8_CallBack(unsigned char Prm); +extern int ActList_9_CallBack(unsigned char Prm); + + +extern int ActList_0_RedrawCallBack(unsigned char Prm); +extern int ActList_1_RedrawCallBack(unsigned char Prm); +extern int ActList_2_RedrawCallBack(unsigned char Prm); +extern int ActList_3_RedrawCallBack(unsigned char Prm); +extern int ActList_4_RedrawCallBack(unsigned char Prm); +extern int ActList_5_RedrawCallBack(unsigned char Prm); +extern int ActList_6_RedrawCallBack(unsigned char Prm); +extern int ActList_7_RedrawCallBack(unsigned char Prm); +extern int ActList_8_RedrawCallBack(unsigned char Prm); +extern int ActList_9_RedrawCallBack(unsigned char Prm); + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/CnCpp.cpp b/MyCode/src/CnCpp.cpp new file mode 100644 index 0000000..394a394 --- /dev/null +++ b/MyCode/src/CnCpp.cpp @@ -0,0 +1,497 @@ +//#include "Gui.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "server.h" +#include "rtc.h" + +unsigned int Sys_1s_Rdy = 0; +unsigned int KeyRdy = 0; +unsigned char KeyValue; +unsigned char TimeUpdata = 0; + + +unsigned char NewBatState; + +extern "C" unsigned int GetSystemErrorState(void) +{ + return IsSystemError; +} + +extern "C" void Sys_1s_Load_Rdy(void) +{ + Sys_1s_Rdy = 1; + Record.Task1000Ms(); +} + +extern "C" void LcdTopCover(unsigned int aClr) +{ + //LcdTopFill(aClr); +} + +extern "C" void SystemDataTimeUpdata(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec) +{ + DateTime.Date.Split.Year = aY; + DateTime.Date.Split.Month = aM; + DateTime.Date.Split.Day = aD; + + DateTime.Time.Split.Hour = aH; + DateTime.Time.Split.Minute = aMin; + DateTime.Time.Split.Second = aSec; + + TimeUpdata = 1; +} + +extern "C" void LoadPsBatStateViaKeyPad(unsigned char *p) +{ + int i; + for(i=0; i<12; i++){ + PsBatData.D8[i] = p[i]; + } + PsBatData.Body.HasUpdate = 1; +} + +extern "C" void LoadPsBatStateViaKeyPadSub1(unsigned char *p) +{ + int i; + unsigned char ErrByte; + ErrByte = p[0]; + for(i=0; i<12; i++){ + PowerPrmValue.Sub1.D8[i] = p[i+1]; + } + if(ErrByte & 0x01){ + if(PowerPrmValue.Sub1.Body.PowerLineFault == 0){ + CtlCenter.ieAddDevFault(19, 1); + PowerPrmValue.Sub1.Body.PowerLineFault =1; + } + }else{ + if(PowerPrmValue.Sub1.Body.PowerLineFault){ + CtlCenter.ieAddDevFaultCancel(19, 1); + PowerPrmValue.Sub1.Body.PowerLineFault =0; + } + } + + if(ErrByte & 0x02){ + if(PowerPrmValue.Sub1.Body.BatFault == 0){ + CtlCenter.ieAddDevFault(20, 1); + PowerPrmValue.Sub1.Body.BatFault =1; + } + }else{ + if(PowerPrmValue.Sub1.Body.BatFault){ + CtlCenter.ieAddDevFaultCancel(20, 1); + PowerPrmValue.Sub1.Body.BatFault =0; + } + } + + if(ErrByte & 0x04){ + if(PowerPrmValue.Sub1.Body.OutputFault == 0){ + CtlCenter.ieAddDevFault(23, 1); + PowerPrmValue.Sub1.Body.OutputFault =1; + } + }else{ + if(PowerPrmValue.Sub1.Body.OutputFault){ + CtlCenter.ieAddDevFaultCancel(23, 1); + PowerPrmValue.Sub1.Body.OutputFault =0; + } + } + + if(ErrByte & 0x10){ + if(PowerPrmValue.Sub1.Body.Bat1VoltageLow == 0){ + CtlCenter.ieAddDevFault(26,1); + PowerPrmValue.Sub1.Body.Bat1VoltageLow =1; + } + }else{ + if(PowerPrmValue.Sub1.Body.Bat1VoltageLow){ + CtlCenter.ieAddDevFaultCancel(26,1); + PowerPrmValue.Sub1.Body.Bat1VoltageLow =0; + } + } + + if(ErrByte & 0x20){ + if(PowerPrmValue.Sub1.Body.Bat2VoltageLow == 0){ + CtlCenter.ieAddDevFault(27,1); + PowerPrmValue.Sub1.Body.Bat2VoltageLow =1; + } + }else{ + if(PowerPrmValue.Sub1.Body.Bat2VoltageLow){ + CtlCenter.ieAddDevFaultCancel(27,1); + PowerPrmValue.Sub1.Body.Bat2VoltageLow =0; + } + } + + if(ErrByte & 0x80){ + if(PowerPrmValue.Sub1.Body.OfflineFault == 0){ + CtlCenter.ieAddDevFault(21, 1); + PowerPrmValue.Sub1.Body.OfflineFault =1; + } + }else{ + if(PowerPrmValue.Sub1.Body.OfflineFault){ + CtlCenter.ieAddDevFaultCancel(21, 1); + PowerPrmValue.Sub1.Body.OfflineFault =0; + } + } +} + +extern "C" void LoadPsBatStateViaKeyPadSub2(unsigned char *p) +{ + int i; + unsigned char ErrByte; + ErrByte = p[0]; + for(i=0; i<12; i++){ + PowerPrmValue.Sub2.D8[i] = p[i+1]; + } + if(ErrByte & 0x01){ + if(PowerPrmValue.Sub2.Body.PowerLineFault == 0){ + CtlCenter.ieAddDevFault(19, 2); + PowerPrmValue.Sub2.Body.PowerLineFault =1; + } + }else{ + if(PowerPrmValue.Sub2.Body.PowerLineFault){ + CtlCenter.ieAddDevFaultCancel(19, 2); + PowerPrmValue.Sub2.Body.PowerLineFault =0; + } + } + + if(ErrByte & 0x02){ + if(PowerPrmValue.Sub2.Body.BatFault == 0){ + CtlCenter.ieAddDevFault(20, 2); + PowerPrmValue.Sub2.Body.BatFault =1; + } + }else{ + if(PowerPrmValue.Sub2.Body.BatFault){ + CtlCenter.ieAddDevFaultCancel(20, 2); + PowerPrmValue.Sub2.Body.BatFault =0; + } + } + + if(ErrByte & 0x04){ + if(PowerPrmValue.Sub2.Body.OutputFault == 0){ + CtlCenter.ieAddDevFault(23, 2); + PowerPrmValue.Sub2.Body.OutputFault =1; + } + }else{ + if(PowerPrmValue.Sub2.Body.OutputFault){ + CtlCenter.ieAddDevFaultCancel(23, 2); + PowerPrmValue.Sub2.Body.OutputFault =0; + } + } + + if(ErrByte & 0x10){ + if(PowerPrmValue.Sub2.Body.Bat1VoltageLow == 0){ + CtlCenter.ieAddDevFault(24,2); + PowerPrmValue.Sub2.Body.Bat1VoltageLow =1; + } + }else{ + if(PowerPrmValue.Sub2.Body.Bat1VoltageLow){ + CtlCenter.ieAddDevFaultCancel(24,2); + PowerPrmValue.Sub2.Body.Bat1VoltageLow =0; + } + } + + if(ErrByte & 0x20){ + if(PowerPrmValue.Sub2.Body.Bat2VoltageLow == 0){ + CtlCenter.ieAddDevFault(25,2); + PowerPrmValue.Sub2.Body.Bat2VoltageLow =1; + } + }else{ + if(PowerPrmValue.Sub2.Body.Bat2VoltageLow){ + CtlCenter.ieAddDevFaultCancel(25,2); + PowerPrmValue.Sub2.Body.Bat2VoltageLow =0; + } + } + + if(ErrByte & 0x80){ + if(PowerPrmValue.Sub2.Body.OfflineFault == 0){ + CtlCenter.ieAddDevFault(21, 2); + PowerPrmValue.Sub2.Body.OfflineFault =1; + } + }else{ + if(PowerPrmValue.Sub2.Body.OfflineFault){ + CtlCenter.ieAddDevFaultCancel(21, 2); + PowerPrmValue.Sub2.Body.OfflineFault =0; + } + } +} + +extern "C" void KeyPadAskPowerCount() +{ + KeyPad.IsSendPowerSuplyCount = 1; +} + +extern "C" void LoadBatStateViaKeyPad(unsigned char aBatSatte) +{ + KeyPadData.BatState = aBatSatte; + PowerSuplyState = aBatSatte & 0x01; + PowerBkState = aBatSatte & 0x02; + PowerSuplyOutput = aBatSatte & 0x04; + BatState = aBatSatte & 0x40; + PowerSuplyComm = aBatSatte & 0x80; + KeyPadData.HasUpdate = 1; +} + +extern "C" void SetOuterCanTxMsgState(unsigned char aSatte) +{ + OuterCanTxState = aSatte; +} + +extern "C" void LoadOuterCanRxMsg(unsigned int aIde, unsigned char *p, unsigned char Len) +{ + unsigned int c; + if(Len >8)return; + ProtoC2C.iBuf.WriteIndex++; + if(ProtoC2C.iBuf.WriteIndex >= dNetworkInBufMaxLength)ProtoC2C.iBuf.WriteIndex = 0; + + ProtoC2C.iBuf.Body[ProtoC2C.iBuf.WriteIndex].D32[0] = aIde; + ProtoC2C.iBuf.Body[ProtoC2C.iBuf.WriteIndex].Data.Len = Len; + ProtoC2C.iBuf.Body[ProtoC2C.iBuf.WriteIndex].Data.Identification = static_cast((aIde >> 24) & 0x00000001); + ProtoC2C.iBuf.Body[ProtoC2C.iBuf.WriteIndex].Data.Routing = static_cast((aIde >> 25) & 0x00000003); + ProtoC2C.iBuf.Body[ProtoC2C.iBuf.WriteIndex].Data.Priority = static_cast((aIde >> 27) & 0x00000003); + for(c=0; c8)return; + InnerCanRxBuf.WriteIndex++; + if(InnerCanRxBuf.WriteIndex > (dInnerCanRxBufMaxCount -1))InnerCanRxBuf.WriteIndex = 0; + + InnerCanRxBuf.Body[InnerCanRxBuf.WriteIndex].Ide.D32 = aIde; + InnerCanRxBuf.Body[InnerCanRxBuf.WriteIndex].Len = Len; + for(c=0; c 32)return; + ExRecord.RxGetFlag = 1; + ExRecord.RxMsg.D8[0] = *p; + p++; + ExRecord.RxMsg.D8[1] = *p; + p++; + for(i=0;i 20)return; + FecStd.SetDebug.Flag = 1; + for(i=0;i 8)||(section > 127))return; + len+=8; + + if(section){ + FecStd.RxMsg.UsingMsgIndex = 1; + FecStd.RxMsg.FrmCount = section; + }else{ + FecStd.RxGetFlag = 1; + FecStd.RxMsgState = ackRecDataCorrect; + } + + for(i=0;i 8)||(section > 3))return; + len+=8; + + if(section){ + FecBusCRT.RxMsg.Prm.UsingMsgIndex = 1; + }else{ + FecBusCRT.RxGetFlag = 1; + FecBusCRT.RxMsgState = ackRecDataCorrect; + } + + for(i=0;iprm.data; + pConfigLoopDataTX = (TConfigLoopData *)pCfgTxPkg->prm.data; + pConfigLoopDispDataTX = (TConfigLoopDispData *)pCfgTxPkg->prm.data; + pConfigBusDataTX = (TConfigBusPanelData *)pCfgTxPkg->prm.data; + pConfigDirDataTX = (TConfigDirPanelData *)pCfgTxPkg->prm.data; + pConfigAreaDataTX = (TConfigAreaData *)pCfgTxPkg->prm.data; + + uartRxFlag = 0; + usbCdcRxFlag = 0; + fileAnalysisErr = 0; + dataAnalysisErr = 0; + + iLinkBufIndex = 0; + oLinkBufIndex = 0; + + for(i=0; i= dLinkCfg_BufCount_Tx)iLinkBufIndex = 0; + + aAddr = dAddrSdram_LinkCfgTxBuf + (iLinkBufIndex * dLinkCfg_BufEntrySize_Tx); + for(x = 0;x<(dLinkCfg_BufEntrySize_Tx/4);x++){ + *(volatile unsigned int *)(aAddr + (x*4)) = *(volatile unsigned int *)pData; + pData+=4; + } +} + +void TConfig::oLinkTXBuf() +{ + unsigned int x,aAddr,len; + + if(iLinkBufIndex != oLinkBufIndex){ + oLinkBufIndex++; + if(oLinkBufIndex >= dLinkCfg_BufCount_Tx)oLinkBufIndex = 0; + + aAddr = dAddrSdram_LinkCfgTxBuf + (oLinkBufIndex * dLinkCfg_BufEntrySize_Tx); + for(x = 0;x<(dLinkCfg_BufEntrySize_Tx/4);x++){ + pCfgTxPkg->D32[x] = *(volatile unsigned int *)(aAddr + (x*4)); + } + + oBufProcess(); + } +} + +void TConfig::oBufProcess() +{ + //set_test_tx_data(pCfgTxPkg->D8, (pCfgTxPkg->prm.len + 4)); + usb_cdc_tx(pCfgTxPkg->D8, (pCfgTxPkg->prm.len + 4)); +} + +void TConfig::WaitChipIdle(unsigned int aCnt) +{ + volatile unsigned int Sta; + do{ + DelayMs(aCnt); + Sta = nor_get_busy_state(dFlashLinkageExpChipX); + }while(Sta); +} + +unsigned short TConfig::Crc16Data(unsigned char * apData,unsigned int aLen) +{ + return 1; +} + +unsigned int TConfig::CheckCrc16(unsigned char * apData,unsigned int aLen) +{ + return 1; +} + +unsigned int TConfig::AsiiToData(unsigned char * apResult, char * apData,unsigned int aLen) +{ + unsigned char value = 0; + unsigned int i; + + if(aLen > 3)return 1; + + for(i=0;i'9')||(apData[i]<'0')){ + return 1; + }else{ + value = value * 10; + value += apData[i] - '0'; + } + } + *apResult = value; + return 0; +} + +unsigned int TConfig::AsiiToData(unsigned short * apResult, char* apData,unsigned int aLen) +{ + unsigned short value = 0; + unsigned int i; + + if(aLen > 5)return 1; + + for(i=0;i'9')||(apData[i]<'0')){ + return 1; + }else{ + value = value * 10; + value += apData[i] - '0'; + } + } + *apResult = value; + return 0; +} + +unsigned int TConfig::AsiiToData(unsigned int * apResult, char * apData,unsigned int aLen) +{ + unsigned int value = 0; + unsigned int i; + + if(aLen > 10)return 1; + + for(i=0;i'9')||(apData[i]<'0')){ + return 1; + }else{ + value = value * 10; + value += apData[i] - '0'; + } + } + *apResult = value; + return 0; +} + +unsigned int TConfig::AsiiToData(__UINT64_TYPE__ * apResult, char* apData,unsigned int aLen) +{ + __UINT64_TYPE__ value = 0; + unsigned int i; + + if(aLen > 20)return 1; + + for(i=0;i'9')||(apData[i]<'0')){ + return 1; + }else{ + value = value * 10; + value += apData[i] - '0'; + } + } + *apResult = value; + return 0; +} + +void TConfig::GetDesc16(char * apSetData, char * apGetData) +{ + unsigned int i; + + for(i=0;i<16;i++){ + apSetData[i] = apGetData[i]; + if(NULL == apGetData[i]){ + return; + } + } +} + +void TConfig::GetDesc16(char * apSetData, unsigned char * apGetData) +{ + unsigned int i; + + for(i=0;i<16;i++){ + apSetData[i] = apGetData[i]; + if(NULL == apGetData[i]){ + return; + } + } +} + +void TConfig::GetDesc32(char * apSetData, char * apGetData) +{ + unsigned int i; + + for(i=0;i<32;i++){ + apSetData[i] = apGetData[i]; + if(NULL == apGetData[i]){ + return; + } + } +} + +void TConfig::GetDesc32(char * apSetData, unsigned char * apGetData) +{ + unsigned int i; + + for(i=0;i<32;i++){ + apSetData[i] = apGetData[i]; + if(NULL == apGetData[i]){ + return; + } + } +} + +unsigned int TConfig::GetUsbState(void) +{ + return 1; +} + +int TConfig::ReadFile(char* apName) +{ + int x; + fileSize = load_file_to_sdramcache((const TCHAR*) apName, pSectorTmpAddr, &x); + return x; +} + +void TConfig::GetFileLine() +{ + unsigned char * pDataAddr; + unsigned char * pGetDataAddr; + unsigned int i,x,a; + unsigned int pGet; + unsigned int getLen; + unsigned int count; + + pDataAddr = (unsigned char *)pSectorTmpAddr; + pGetDataAddr = (unsigned char *)SDRAM_BUF_DATA_ADDRESS; + count = 0; + pGet = 0; + a = 0; + + if(fileSize){ + for(i=0;i 32)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(1 == ord){ + dataAnalysisErr = AsiiToData(&ctlPrm.cfg.busPanelCount,&pData[sP],len); + if(ctlPrm.cfg.busPanelCount > BusCountMax)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(2 == ord){ + dataAnalysisErr = AsiiToData(&ctlPrm.cfg.dirPanelCount,&pData[sP],len); + if(ctlPrm.cfg.dirPanelCount > DirCountMax)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(3 == ord){ + dataAnalysisErr = AsiiToData(&ctlPrm.cfg.areaCount,&pData[sP],len); + if(ctlPrm.cfg.areaCount > AreaCountMax)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(4 == ord){ + dataAnalysisErr = AsiiToData(&ctlPrm.cfg.linkCount,&pData[sP],len); + if(ctlPrm.cfg.linkCount > LinkCountMax)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(5 == ord){ + dataAnalysisErr = AsiiToData(&ctlPrm.cfg.loopCfgTab,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(6 == ord){ + dataAnalysisErr = AsiiToData(&ctlPrm.cfg.busCfgTab,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(7 == ord){ + dataAnalysisErr = AsiiToData(&ctlPrm.cfg.dirCfgTab,&pData[sP],len); + len = 0; + sP = i+1; + if((*((unsigned int *)(pData + CFG_FILE_LINE_BUF_SIZE - 4))) < sP)dataAnalysisErr = 1; + for(a=0;a<32;a++)loopPrm.cfg.desc[a] = 0; + GetDesc32(ctlPrm.cfg.desc,&pData[sP]); + } + ord++; + if(dataAnalysisErr)return; + }else + if(NULL == pData[i]){ + if(ord < 7)dataAnalysisErr = 1; + return; + } + } +} + +void TConfig::GetLoopCfgDevPrm(unsigned int aLineNum) +{ + char * pData; + unsigned int ord = 0,i = 0,sP = 0,a; + unsigned int len = 0; + + if(!aLineNum)return; + + pData = (char *)(SDRAM_BUF_DATA_ADDRESS + (aLineNum * CFG_FILE_LINE_BUF_SIZE)); + + for(i=0;i LoopCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(1 == ord){ + dataAnalysisErr = AsiiToData(&loopPrm.cfg.devId,&pData[sP],len); + if((loopPrm.cfg.devId < 1)||(loopPrm.cfg.id > DevInLoopCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(2 == ord){ + dataAnalysisErr = AsiiToData(&loopPrm.cfg.devType,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(3 == ord){ + dataAnalysisErr = AsiiToData(&loopPrm.cfg.assignType,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(4 == ord){ + dataAnalysisErr = AsiiToData(&loopPrm.cfg.devProperty,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(5 == ord){ + dataAnalysisErr = AsiiToData(&loopPrm.cfg.areaId,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(6 == ord){ + dataAnalysisErr = AsiiToData(&loopPrm.cfg.delayTime,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(7 == ord){ + dataAnalysisErr = AsiiToData(&loopPrm.cfg.devNum,&pData[sP],len); + sP = i+1; + if((*((unsigned int *)(pData + CFG_FILE_LINE_BUF_SIZE - 4))) < sP)dataAnalysisErr = 1; + for(a=0;a<32;a++)loopPrm.cfg.desc[a] = 0; + GetDesc32(loopPrm.cfg.desc,&pData[sP]); + loopCfgDevTab[loopPrm.cfg.devId - 1] = 1; + } + ord++; + if(dataAnalysisErr)return; + }else + if(NULL == pData[i]){ + if(ord < 7)dataAnalysisErr = 1; + return; + } + } +} + +void TConfig::GetLoopCfgDispPrm(unsigned int aLineNum) +{ + char * pData; + unsigned int ord = 0,i = 0,sP = 0,a,b; + unsigned int len = 0; + unsigned int ser_char; + + if(!aLineNum)return; + + pData = (char *)(SDRAM_BUF_DATA_ADDRESS + (aLineNum * CFG_FILE_LINE_BUF_SIZE)); + + for(i=0;i LoopCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(1 == ord){ + dataAnalysisErr = AsiiToData(&loopDispPrm.cfg.devId,&pData[sP],len); + if((loopDispPrm.cfg.devId < 1)||(loopDispPrm.cfg.id > DevInLoopCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(2 == ord){ + dataAnalysisErr = AsiiToData(&loopDispPrm.cfg.devType,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(3 == ord){ + dataAnalysisErr = AsiiToData(&loopDispPrm.cfg.dispMode,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(4 == ord){ + for(a=0;a<3;a++){ + loopDispPrm.cfg.areaId[a] = 0; + loopDispPrm.cfg.devNum[a] = 0; + } + a=0; + + if((':' != pData[sP+a])||(':' != pData[sP+a+5])||(':' != pData[sP+a+10])||(15 != len)){ + dataAnalysisErr = 1; + }else{ + dataAnalysisErr = AsiiToData(&loopDispPrm.cfg.areaId[0],&pData[sP+a+1],4); + dataAnalysisErr = AsiiToData(&loopDispPrm.cfg.areaId[1],&pData[sP+a+1+5],4); + dataAnalysisErr = AsiiToData(&loopDispPrm.cfg.areaId[2],&pData[sP+a+1+10],4); + + sP+=(15+1); + if((*((unsigned int *)(pData + CFG_FILE_LINE_BUF_SIZE - 4))) < sP){ + dataAnalysisErr = 1; + }else{ + len = (*((unsigned int *)(pData + CFG_FILE_LINE_BUF_SIZE - 4))) - sP; + if((':' != pData[sP+0])||(':' != pData[sP+9])||(18 != len)){ + dataAnalysisErr = 1; + }else{ + sP++; + for(a=0;a<8;a++){ + if(!(((pData[sP+a] >= '0')&&(pData[sP+a] <= '9'))||(pData[sP+a] == '*'))){ + dataAnalysisErr = 1; + }else{ + if(pData[sP+a] == '*'){ + ser_char = 0x0A; + }else{ + ser_char = pData[sP+a] - '0'; + } + loopDispPrm.cfg.devNum[0] |= (ser_char<<((8 - a -1)*4)); + } + } + sP+=9; + for(a=0;a<8;a++){ + if(!(((pData[sP+a] >= '0')&&(pData[sP+a] <= '9'))||(pData[sP+a] == '*'))){ + dataAnalysisErr = 1; + }else{ + if(pData[sP+a] == '*'){ + ser_char = 0x0A; + }else{ + ser_char = pData[sP+a] - '0'; + } + loopDispPrm.cfg.devNum[1] |= (ser_char<<((8 - a -1)*4)); + } + } + loopDispPrm.cfg.ord++; + } + } + } + len = 0; + sP = i+1; + } + ord++; + if(dataAnalysisErr)return; + }else + if(NULL == pData[i]){ + if(ord < 4)dataAnalysisErr = 1; + return; + } + } +} + +void TConfig::GetBusCfgKeyPrm(unsigned int aLineNum) +{ + char * pData; + unsigned int ord = 0,i = 0,sP = 0,a; + unsigned int len = 0; + unsigned int ser_char; + + if(!aLineNum)return; + + pData = (char *)(SDRAM_BUF_DATA_ADDRESS + (aLineNum * CFG_FILE_LINE_BUF_SIZE)); + + for(i=0;i BusCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(1 == ord){ + dataAnalysisErr = AsiiToData(&busPrm.cfg.keyId,&pData[sP],len); + if((busPrm.cfg.keyId < 1)||(busPrm.cfg.keyId > KeyInBusCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(2 == ord){ + dataAnalysisErr = AsiiToData(&busPrm.cfg.ctlMode,&pData[sP],len); + if(busPrm.cfg.ctlMode > 2)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(3 == ord){ + if((!len)||(len > 8))dataAnalysisErr = 1; + else{ + busPrm.cfg.serNum = 0; + for(a=0;a= '0')&&(pData[sP+a] <= '9'))||(pData[sP+a] == '*'))){ + dataAnalysisErr = 1; + }else{ + if(pData[sP+a] == '*'){ + ser_char = 0x0A; + }else{ + ser_char = pData[sP+a] - '0'; + } + busPrm.cfg.serNum |= (ser_char<<((len - a -1)*4)); + } + } + } + len = 0; + sP = i+1; + }else + if(4 == ord){ + dataAnalysisErr = AsiiToData(&busPrm.cfg.areaId,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(5 == ord){ + dataAnalysisErr = AsiiToData(&busPrm.cfg.devType,&pData[sP],len); + sP = i+1; + if((*((unsigned int *)(CFG_FILE_LINE_BUF_SIZE - 4))) < sP)dataAnalysisErr = 1; + for(a=0;a<32;a++)busPrm.cfg.desc[a] = 0; + GetDesc32(busPrm.cfg.desc,&pData[sP]); + busCfgKeyTab[busPrm.cfg.keyId - 1] = 1; + } + ord++; + if(dataAnalysisErr)return; + }else + if(NULL == pData[i]){ + if(ord < 5)dataAnalysisErr = 1; + return; + } + } +} + +void TConfig::GetDirCfgKeyPrm(unsigned int aLineNum) +{ + char * pData; + unsigned int ord = 0,i = 0,sP = 0,a; + unsigned int len = 0; + + if(!aLineNum)return; + + pData = (char *)(SDRAM_BUF_DATA_ADDRESS + (aLineNum * CFG_FILE_LINE_BUF_SIZE)); + + for(i=0;i DirCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(1 == ord){ + dataAnalysisErr = AsiiToData(&dirPrm.cfg.keyId,&pData[sP],len); + if((dirPrm.cfg.keyId < 1)||(dirPrm.cfg.keyId > KeyInDirCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(2 == ord){ + dataAnalysisErr = AsiiToData(&dirPrm.cfg.isAble,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(3 == ord){ + dataAnalysisErr = AsiiToData(&dirPrm.cfg.errDetFlag,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(4 == ord){ + dataAnalysisErr = AsiiToData(&dirPrm.cfg.outProp,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(5 == ord){ + dataAnalysisErr = AsiiToData(&dirPrm.cfg.ctlDevType,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(6 == ord){ + dataAnalysisErr = AsiiToData(&dirPrm.cfg.areaId,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(7 == ord){ + dataAnalysisErr = AsiiToData(&dirPrm.cfg.serNum,&pData[sP],len); + sP = i+1; + if((*((unsigned int *)(CFG_FILE_LINE_BUF_SIZE - 4))) < sP)dataAnalysisErr = 1; + for(a=0;a<32;a++)dirPrm.cfg.desc[a] = 0; + GetDesc32(dirPrm.cfg.desc,&pData[sP]); + dirCfgKeyTab[dirPrm.cfg.keyId - 1] = 1; + } + ord++; + if(dataAnalysisErr)return; + }else + if(NULL == pData[i]){ + if(ord < 7)dataAnalysisErr = 1; + return; + } + } +} + +void TConfig::GetAreaCfgPrm(unsigned int aLineNum) +{ + char * pData; + unsigned int ord = 0,i = 0,sP = 0,a; + unsigned int len = 0; + + if(!aLineNum)return; + + pData = (char *)(SDRAM_BUF_DATA_ADDRESS + (aLineNum * CFG_FILE_LINE_BUF_SIZE)); + + for(i=0;i AreaCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(1 == ord){ + dataAnalysisErr = AsiiToData(&areaPrm.cfg.serNum,&pData[sP],len); + len = 0; + sP = i+1; + }else + if(2 == ord){ + if(len > 16)dataAnalysisErr = 1; + for(a=0;a<16;a++)areaPrm.cfg.profile[a] = 0; + for(a=0;a LinkCountMax))dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(1 == ord){ + dataAnalysisErr = AsiiToData(&linkPrm.cfg.isStop,&pData[sP],len); + if(linkPrm.cfg.isStop > 1)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(2 == ord){ + dataAnalysisErr = AsiiToData(&linkPrm.cfg.isMask,&pData[sP],len); + if(linkPrm.cfg.isMask > 1)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(3 == ord){ + dataAnalysisErr = AsiiToData(&linkPrm.cfg.isForceAutoExec,&pData[sP],len); + if(linkPrm.cfg.isForceAutoExec > 1)dataAnalysisErr = 1; + len = 0; + sP = i+1; + }else + if(4 == ord){ + dataAnalysisErr = AsiiToData(&linkPrm.cfg.inTab,&pData[sP],len); + for(a=0;a<16;a++){ + if(linkPrm.cfg.inTab & (1< 272)){ + dataAnalysisErr = 1; + }else{ + for(a=0;a<16;a++){ + for(b=0;b<16;b++){ + linkPrm.cfg.eqn.prm.inEqn[a][b] = 0; + } + } + formOrd = 0; + for(a=0;a 15)index = 15; + for(b=0;b<16;b++){ + if((a+1+b) >= len)break; + linkPrm.cfg.eqn.prm.inEqn[index][b] = pData[sP+a+1+b]; + } + linkPrm.cfg.eqn.prm.inEqn[index][8] = linkPrm.cfg.eqn.prm.inEqn[index][9]; + linkPrm.cfg.eqn.prm.inEqn[index][9] = linkPrm.cfg.eqn.prm.inEqn[index][10]; + linkPrm.cfg.eqn.prm.inEqn[index][10] = linkPrm.cfg.eqn.prm.inEqn[index][11]; + linkPrm.cfg.eqn.prm.inEqn[index][11] = linkPrm.cfg.eqn.prm.inEqn[index][13]; + linkPrm.cfg.eqn.prm.inEqn[index][12] = linkPrm.cfg.eqn.prm.inEqn[index][14]; + linkPrm.cfg.eqn.prm.inEqn[index][13] = linkPrm.cfg.eqn.prm.inEqn[index][15]; + linkPrm.cfg.eqn.prm.inEqn[index][14] = 0; + linkPrm.cfg.eqn.prm.inEqn[index][15] = 0; + + //linkPrm.cfg.inTab |= (1<=272)||(sP+a > (*((unsigned int *)(pData + CFG_FILE_LINE_BUF_SIZE - 4))))){ + for(index = formOrd;index < 16;index++){ + if(linkPrm.cfg.outTab & (1< 15)index = 15; + for(b=0;b<16;b++){ + linkPrm.cfg.eqn.prm.outEqn[index][b] = pData[sP+a+1+b]; + } + linkPrm.cfg.eqn.prm.outEqn[index][8] = linkPrm.cfg.eqn.prm.outEqn[index][9]; + linkPrm.cfg.eqn.prm.outEqn[index][9] = linkPrm.cfg.eqn.prm.outEqn[index][10]; + linkPrm.cfg.eqn.prm.outEqn[index][10] = linkPrm.cfg.eqn.prm.outEqn[index][11]; + linkPrm.cfg.eqn.prm.outEqn[index][11] = linkPrm.cfg.eqn.prm.outEqn[index][13]; + linkPrm.cfg.eqn.prm.outEqn[index][12] = linkPrm.cfg.eqn.prm.outEqn[index][14]; + linkPrm.cfg.eqn.prm.outEqn[index][13] = linkPrm.cfg.eqn.prm.outEqn[index][15]; + linkPrm.cfg.eqn.prm.outEqn[index][14] = 0; + linkPrm.cfg.eqn.prm.outEqn[index][15] = 0; + + //linkPrm.cfg.outTab |= (1<D32[i]; + } +} + +unsigned int TConfig::WriteLoopDevPrmToSdram(TConfigLoopData * pLoopPrm) +{ + unsigned int aLoadAddr; + unsigned int x,y,i; + + if((pLoopPrm->cfg.id < 1)||(pLoopPrm->cfg.id > LoopCountMax))return 1; + if((pLoopPrm->cfg.devId < 1)||(pLoopPrm->cfg.devId > DevInLoopCountMax))return 1; + + y = pLoopPrm->cfg.id - 1; + x = pLoopPrm->cfg.devId - 1; + + aLoadAddr = LoopDevCfgBufAddr + (((y * DevInLoopCountMax) + x) * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i]; + } + + return 0; +} + +unsigned int TConfig::WriteLoopDevDispPrmToSdram(TConfigLoopDispData * pLoopDispPrm) +{ + unsigned int aLoadAddr; + unsigned int x,y,i; + + if((pLoopDispPrm->cfg.ord < 1)||(pLoopDispPrm->cfg.ord > 16))return 1; + if((pLoopDispPrm->cfg.id < 1)||(pLoopDispPrm->cfg.id > LoopCountMax))return 1; + if((pLoopDispPrm->cfg.devId < 1)||(pLoopDispPrm->cfg.devId > DevInLoopCountMax))return 1; + + y = pLoopDispPrm->cfg.id - 1; + x = pLoopDispPrm->cfg.ord - 1; + + aLoadAddr = LoopDispCfgBufAddr + (((y * DispInLoopCountMax) + x) * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i]; + } + + return 0; +} + +void TConfig::ClearLoopCfgDevTabInSdram(unsigned int aId) +{ + unsigned int aLoadAddr; + unsigned int x,i; + + if((!aId)||(aId > LoopCountMax))return; + x = aId - 1; + aLoadAddr = LoopDevCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i LoopCountMax))return; + x = aId - 1; + aLoadAddr = LoopDevCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i LoopCountMax))return; + if((0 == aDevId)||(aDevId > DevInLoopCountMax))return; + x = aId - 1; + y = aDevId - 1; + aLoadAddr = LoopDevCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + *(volatile unsigned char *)(aLoadAddr + y) = 1; +} + +unsigned int TConfig::WriteBusKeyPrmToSdram(TConfigBusPanelData * pBusPrm) +{ + unsigned int aLoadAddr; + unsigned int x,y,i; + + if((pBusPrm->cfg.id < 1)||(pBusPrm->cfg.id > BusCountMax))return 1; + if((pBusPrm->cfg.keyId < 1)||(pBusPrm->cfg.keyId > KeyInBusCountMax))return 1; + + y = pBusPrm->cfg.id - 1; + x = pBusPrm->cfg.keyId - 1; + + aLoadAddr = BusKeyCfgBufAddr + (((y * KeyInBusCountMax) + x) * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i]; + } + + return 0; +} + +void TConfig::ClearBusCfgKeyTabToSdram(unsigned int aId) +{ + unsigned int aLoadAddr; + unsigned int x,i; + + if((!aId)||(aId > BusCountMax))return; + x = aId - 1; + aLoadAddr = BusKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i BusCountMax))return; + x = aId - 1; + aLoadAddr = BusKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i LoopCountMax))return; + if((!aKeyId)||(aKeyId > KeyInBusCountMax))return; + x = aId - 1; + y = aKeyId - 1; + aLoadAddr = BusKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + *(volatile unsigned char *)(aLoadAddr + y) = 1; +} + +unsigned int TConfig::WriteDirKeyPrmToSdram(TConfigDirPanelData * pDirPrm) +{ + unsigned int aLoadAddr; + unsigned int x,y,i; + + if((pDirPrm->cfg.id < 1)||(pDirPrm->cfg.id > DirCountMax))return 1; + if((pDirPrm->cfg.keyId < 1)||(pDirPrm->cfg.keyId > KeyInDirCountMax))return 1; + + y = pDirPrm->cfg.id - 1; + x = pDirPrm->cfg.keyId - 1; + + aLoadAddr = DirKeyCfgBufAddr + ((y * KeyInDirCountMax + x) * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i]; + } + + return 0; +} + +void TConfig::ClearDirCfgKeyTabToSdram(unsigned int aId) +{ + unsigned int aLoadAddr; + unsigned int x,i; + + if((!aId)||(aId > DirCountMax))return; + x = aId - 1; + aLoadAddr = DirKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i DirCountMax))return; + x = aId - 1; + aLoadAddr = DirKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i DirCountMax))return; + if((!aKeyId)||(aKeyId > KeyInDirCountMax))return; + x = aId - 1; + y = aKeyId - 1; + aLoadAddr = DirKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + *(volatile unsigned char *)(aLoadAddr + y) = 1; +} + +unsigned int TConfig::WriteAreaPrmToSdram(TConfigAreaData * pAreaPrm) +{ + unsigned int aLoadAddr; + unsigned int x,i; + + if((pAreaPrm->cfg.id < 1)||(pAreaPrm->cfg.id > AreaCountMax))return 1; + + x = pAreaPrm->cfg.id - 1; + + aLoadAddr = AreaCfgBufAddr + (x * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i]; + } + + return 0; +} + +void TConfig::WriteAreaCfgTabToSdram(unsigned char * pAreaCfgTab) +{ + unsigned int aLoadAddr; + unsigned int i; +} + +//____________________________________________________________________________________________________________________ +void TConfig::ClearOneLinkCfgToSdram(unsigned int aId) +{ + unsigned int x; + unsigned int aInx; + unsigned int aLoadAddr; + + if((aId < 1)||(aId > LinkCountMax))return; + aInx = aId - 1; + + aLoadAddr = dSdAddrLinkageExp + (aInx * 1024); + + for(x = 0;x<64;x+=4){ + *(volatile unsigned int *)(aLoadAddr + (x * 4)) = 0; + } +} + +unsigned int TConfig::WriteLinkCfgToSdram(TConfigLinkData * pLinkPrm) +{ + unsigned int a,x; + unsigned int aInx; + unsigned int aLoadAddr; + + if((0 == pLinkPrm->cfg.id)||(pLinkPrm->cfg.id > LinkCountMax))return 1; + if(pLinkPrm->cfg.inCount > 16)return 1; + if(pLinkPrm->cfg.outCount > 16)return 1; + aInx = pLinkPrm->cfg.id - 1; + + aLoadAddr = dSdAddrLinkageExp + (aInx * 1024); + *(volatile unsigned char *)(aLoadAddr + 0) = 'T'; + *(volatile unsigned char *)(aLoadAddr + 1) = 'R'; + *(volatile unsigned char *)(aLoadAddr + 2) = 'U'; + *(volatile unsigned char *)(aLoadAddr + 3) = 'E'; + + if(pLinkPrm->cfg.isMask)(*(volatile unsigned char *)(aLoadAddr + 4)) = 'M'; + else (*(volatile unsigned char *)(aLoadAddr + 4)) = 0; + if(pLinkPrm->cfg.isStop)(*(volatile unsigned char *)(aLoadAddr + 5)) = 'S'; + else *(volatile unsigned char *)(aLoadAddr + 5) = 0; + if(pLinkPrm->cfg.isForceAutoExec)(*(volatile unsigned char *)(aLoadAddr + 6)) = 'F'; + else (*(volatile unsigned char *)(aLoadAddr + 6)) = 0; + + //------intput---Tab---- + for(x=0; x<16; x++){ + if(pLinkPrm->cfg.inTab & (1<cfg.eqn.D32[(x*4) + a]; + }else{ + for(a=0; a<4; a++) + *(volatile unsigned int *)(aLoadAddr + 16 + (x*16) + (a*4)) = 0; + } + } + + //------output---Tab---- + for(x=0; x<16; x++){ + if(pLinkPrm->cfg.outTab & (1<cfg.eqn.D32[(16*4) + (x*4) + a]; + }else{ + for(a=0; a<4; a++) + *(volatile unsigned int *)(aLoadAddr + 16 + (16*16) + (x*16) + (a*4)) = 0; + } + } + + return 0; +} + +void TConfig::Erase4LinkIndex(unsigned int aInx) +{ + unsigned int fAddr4K; + fAddr4K = dFlashAddrLinkageExp + ((aInx * 1024) & 0x00FFF000); + WaitChipIdle(5); + nor_erase_sector_4k(dFlashLinkageExpChipX,fAddr4K); + WaitChipIdle(20); +} + +void TConfig::Erase64LinkIndex(unsigned int aInx) +{ + unsigned int fAddr64K; + fAddr64K = dFlashAddrLinkageExp + ((aInx * 1024) & 0x00FF0000); + WaitChipIdle(5); + nor_erase_sector_64k(dFlashLinkageExpChipX,fAddr64K); + WaitChipIdle(100); +} + +void TConfig::Write4LinkIndex(unsigned int aInx) +{ + unsigned int fAddr4K; + unsigned int fAddr4Index; + unsigned int sAddr4K; + unsigned int SysLinkAddr; + int i,x, ord; + fAddr4K = dFlashAddrLinkageExp + ((aInx * 1024) & 0x00FF'F000); + sAddr4K = dSdAddrLinkageExp + ((aInx * 1024) & 0x00FFF000); + for(i=0; i<4; i++){ + + fAddr4Index = fAddr4K + (i * 1024); + SysLinkAddr = sAddr4K + (i * 1024); + + for(ord=0; ord<4; ord++){ + for(x=0; x<64; x++){ + nFlashPageData.D32[x] = *(volatile unsigned int *)(SysLinkAddr + (x * 4) ); + } + WaitChipIdle(5); + nor_write_page(dFlashLinkageExpChipX, fAddr4Index, nFlashPageData.D8); + fAddr4Index+=256; + SysLinkAddr+=256; + } + } +} + +void TConfig::Write1LinkIndex(unsigned int aInx) +{ + unsigned int fAddr1Index; + unsigned int sAddr; + unsigned int SysLinkAddr; + int i,x, ord; + fAddr1Index = dFlashAddrLinkageExp + (aInx * 1024); + sAddr = dSdAddrLinkageExp + (aInx * 1024); + + SysLinkAddr = sAddr; + + for(ord=0; ord<4; ord++){ + for(x=0; x<64; x++){ + nFlashPageData.D32[x] = *(volatile unsigned int *)(SysLinkAddr + (x * 4) ); + } + WaitChipIdle(5); + nor_write_page(dFlashLinkageExpChipX, fAddr1Index, nFlashPageData.D8); + fAddr1Index+=256; + SysLinkAddr+=256; + } +} + +void TConfig::Clear4Index(unsigned int aGroup) +{ + volatile unsigned int aFlashState; + unsigned int fAddr4K; + unsigned int fAddr4Index; + unsigned int sAddr4K; + unsigned int SysLinkAddr; + int i,x, ord; + TDMix tCrc; + unsigned int ToWriteInx = aGroup * 4; + + ItemList.ReadWriteData.Reset(); + + fAddr4K = dFlashAddrLinkageExp + ((ToWriteInx * 1024) & 0x00FF'F000); + for(i=0; i<4; i++){ + Crc32Reset(); + fAddr4Index = fAddr4K + (i * 1024); + SysLinkAddr = sAddr4K + (i * 1024); + for(ord=0; ord<4; ord++){ + for(x=0; x<64; x++){ + ItemList.ReadWriteData.D32[x] = *(volatile unsigned int *)(SysLinkAddr + (x * 4) ); + if(ord<3 or x<63)Crc32Feed(ItemList.ReadWriteData.D32[x]); + } + if(ord==3)ItemList.ReadWriteData.D32[63]=Crc32GetResult(); + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(dFlashLinkageExpChipX); + }while(aFlashState); + nor_write_page(dFlashLinkageExpChipX, fAddr4Index, ItemList.ReadWriteData.D8); + fAddr4Index+=256; + SysLinkAddr+=256; + } + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(dFlashLinkageExpChipX); + }while(aFlashState); + InterLink.CheckStorageCrc(ToWriteInx+1); + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(dFlashLinkageExpChipX); + }while(aFlashState); + ToWriteInx++; + LoopCheck1S(); + } +} + +void TConfig::WriteAllLinkCfgToNorFlash() +{ + unsigned int x,a,SysLinkAddr,isExist; + Tint Val; + + for(x = 0;x < LinkCountMax;x+=4){ + if((1 == linkCfgTab[x])||(1 == linkCfgTab[x+1])||(1 == linkCfgTab[x+2])||(1 == linkCfgTab[x+3])){ + LinkageProgram.Erase4Index(x); + if(0 == linkCfgTab[x]){ + ClearOneLinkCfgToSdram(x+1); + } + if(0 == linkCfgTab[x+1]){ + ClearOneLinkCfgToSdram(x+2); + } + if(0 == linkCfgTab[x+2]){ + ClearOneLinkCfgToSdram(x+3); + } + if(0 == linkCfgTab[x+3]){ + ClearOneLinkCfgToSdram(x+4); + } + LinkageProgram.Write4Index(x); + }else{ + isExist = 0; + for(a=0;a<4;a++){ + SysLinkAddr = dSdAddrLinkageExp + ((x+a)*1024); + Val.D32 = *(volatile unsigned int *)(SysLinkAddr); + if((Val.D8[0] == 'T') && (Val.D8[1] == 'R') && (Val.D8[2] == 'U') && (Val.D8[3] == 'E')){ + ClearOneLinkCfgToSdram(x+a); + isExist = 1; + } + } + if(isExist){ + LinkageProgram.Erase4Index(x); + Clear4Index(x/4); + } + } + } + LinkageProgram.ReScanExpViaRam(); + InterLink.ReScanExpViaRam(); +} + +void TConfig::WriteOneLinkCfgToNorFlash(unsigned int aLinkId) +{ + if((aLinkId < 1)||(aLinkId > LinkCountMax))return; + + unsigned int x = aLinkId - 1; + + LinkageProgram.Erase4Index(x - (x%4)); + LinkageProgram.Write4Index(x); + + LinkageProgram.ReScanExpViaRam(); + InterLink.ReScanExpViaRam(); +} + +//---------------------------------read--------------------------------------------------------------------------- +unsigned int TConfig::ReadCtlPrmFromSdram(TConfigCtlData * pCtlPrm) +{ + unsigned int aLoadAddr; + unsigned int i; + + aLoadAddr = CtlCfgBufAddr; + for(i=0; iD32[i] = *(volatile unsigned int *)(aLoadAddr + (i*4)); + } + + if(pCtlPrm->cfg.loopCount > LoopCountMax)return 1; + if(pCtlPrm->cfg.busPanelCount > BusCountMax)return 1; + if(pCtlPrm->cfg.dirPanelCount > DirCountMax)return 1; + if(pCtlPrm->cfg.areaCount > AreaCountMax)return 1; + + return 0; +} + +unsigned int TConfig::ReadLoopDevPrmFromSdram(unsigned char aId, unsigned char aDevId, TConfigLoopData * pLoopPrm) +{ + unsigned int aGetAddr; + unsigned int x,y,i; + + if((aId < 1)||(aId > LoopCountMax))return 1 ; + if((aDevId < 1)||(aDevId > DevInLoopCountMax))return 1; + + y = aId - 1; + x = aDevId - 1; + + aGetAddr = LoopDevCfgBufAddr + (((y * DevInLoopCountMax) + x) * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i] = *(volatile unsigned int *)(aGetAddr + (i*4)); + } + + if((aId != pLoopPrm->cfg.id)||(aDevId != pLoopPrm->cfg.devId))return 1; + + return 0; +} + +void TConfig::ReadLoopCfgDevTabFromSdram(unsigned int ord, unsigned char * pLoopCfgDevTab) +{ + unsigned int aGetAddr; + unsigned int x,y,i; + + if((!ord)||(ord > LoopCountMax))return; + x = ord - 1; + aGetAddr = LoopDevCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i BusCountMax))return; + x = ord - 1; + aGetAddr = BusKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i DirCountMax))return; + x = ord - 1; + aGetAddr = DirKeyCfgTabAddr + (x * CFG_TAB_BUF_SIZE); + for(i=0; i BusCountMax))return 1 ; + if((aKeyId < 1)||(aKeyId > KeyInBusCountMax))return 1; + + y = aId - 1; + x = aKeyId - 1; + + aGetAddr = BusKeyCfgBufAddr + (((y * KeyInBusCountMax) + x) * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i] = *(volatile unsigned int *)(aGetAddr + (i*4)); + } + + if((aId != pBusPrm->cfg.id)||(aKeyId != pBusPrm->cfg.keyId))return 1; + + return 0; +} + +unsigned int TConfig::ReadDirKeyPrmFromSdram(unsigned char aId, unsigned char aKeyId, TConfigDirPanelData * pDirPrm) +{ + unsigned int aGetAddr; + unsigned int x,y,i; + + if((aId < 1)||(aId > DirCountMax))return 1; + if((aKeyId < 1)||(aKeyId > KeyInDirCountMax))return 1; + + y = aId - 1; + x = aKeyId - 1; + + aGetAddr = DirKeyCfgBufAddr + (((y * KeyInDirCountMax) + x) * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i] = *(volatile unsigned int *)(aGetAddr + (i*4)); + } + + if((aId != pDirPrm->cfg.id)||(aKeyId != pDirPrm->cfg.keyId))return 1; + + return 0; +} + +unsigned int TConfig::ReadAreaPrmFromSdram(unsigned int aId, TConfigAreaData * pAreaPrm) +{ + unsigned int aLoadAddr; + unsigned int i; + unsigned int x; + + if((aId < 1)||(aId > AreaCountMax))return 1; + + x = aId - 1; + + aLoadAddr = AreaCfgBufAddr + (x * CFG_LOAD_BUF_SIZE); + for(i=0; iD32[i] = *(volatile unsigned int *)(aLoadAddr + (i*4)); + } + + if(aId != pAreaPrm->cfg.id)return 1; + + return 0; +} + +int TConfig::LoadCfgFile() +{ + unsigned int i,ord; + unsigned int a; + int tSta =0; + int tTmpSta; + + CfgPrmInit(); + + //----------------ctl prm----------------------------- + readPath[3] = '0' + (MainCtl.fData.Split.MyNum/10);//cfg01/ctl.csv + readPath[4] = '0' + (MainCtl.fData.Split.MyNum%10); + readPath[6] = 'c'; + readPath[7] = 't'; + readPath[8] = 'l'; + readPath[9] = '.'; + readPath[10]= 'c'; + readPath[11]= 's'; + readPath[12]= 'v'; + readPath[13]= 0; + tTmpSta = ReadFile(readPath); + if(tSta==0)tSta=tTmpSta; + GetFileLine(); + GetCtlCfgPrm(); + WriteCtlPrmToSdram(&ctlPrm); + + //----------------loop prm----------------------------- + readPath[6] = 'l';//loop01.csv + readPath[7] = 'o'; + readPath[8] = 'o'; + readPath[9] = 'p'; + readPath[10]= '0'; + readPath[11]= '1'; + readPath[12]= '.'; + readPath[13]= 'c'; + readPath[14]= 's'; + readPath[15]= 'v'; + readPath[16]= 0; + i=0; + ord =0; + while(i < ctlPrm.cfg.loopCount){ + if(ctlPrm.cfg.loopCfgTab & (((__UINT64_TYPE__)1)< 16)fileAnalysisErr = 1; + if(fileAnalysisErr)break; + + for(a = 1;a <= loopDevDispCount[ord+1];a++){ + GetLoopCfgDispPrm(a);//return loop num of dev prm + WriteLoopDevDispPrmToSdram(&loopDispPrm);//write prm to sdram + } + } + if(ord < 32)ord++; + else break; + } + + //----------------bus prm----------------------------- + readPath[6] = 'b';//bus01.csv + readPath[7] = 'u'; + readPath[8] = 's'; + readPath[9] = '0'; + readPath[10] = '1'; + readPath[11] = '.'; + readPath[12]= 'c'; + readPath[13]= 's'; + readPath[14]= 'v'; + readPath[15]= 0; + i=0; + ord =0; + while(i < ctlPrm.cfg.busPanelCount){ + if(ctlPrm.cfg.busCfgTab & (1<cfg.devId; + Port[aP0].DisplayPadSet[m].CfgBits = pLoopDispData->cfg.dispMode; + Port[aP0].DisplayPadSet[m].AreaEx[0] = pLoopDispData->cfg.areaId[0]; + Port[aP0].DisplayPadSet[m].AreaEx[1] = pLoopDispData->cfg.areaId[1]; + Port[aP0].DisplayPadSet[m].AreaEx[2] = pLoopDispData->cfg.areaId[2]; + Port[aP0].DisplayPadSet[m].UcList[0].Full = pLoopDispData->cfg.devNum[0]; + Port[aP0].DisplayPadSet[m].UcList[1].Full = pLoopDispData->cfg.devNum[1]; + } + Port[aP0].SortDisplayPad(); + } + + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + //Erase + norFlashAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * i) + (256 * 0); + nor_erase_sector_4k(dFlashRegisterDataChip,norFlashAddr); + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + TRegister::sIList = &this->ItemList; + TRegister::sWriteOnePort(aP0+1); + + //Read Back + Record.ReadRegisterDataOnePort(aP0+1); + } + } + + for(m=0; m<256; m++){ + nFlashPageData.D8[m] = 0; + } + //----------------config loop table on APP---------------------------------- + /* + for(m=0; mItemList; + TRegister::sWritePortList(); + + Record.ReadRegisterData(); + Record.ReadDisplayPadSet(); +} + +void TConfig::WriteLoopCfgAllDisp() +{ + unsigned int i,m; + unsigned char aP0,aP1; + volatile unsigned int aFlashState; + volatile unsigned short dType; + TConfigLoopDispData * pLoopDispData; + + for(i = 0; i < LoopCountMax; i++){ + aP0 = i; + + if(loopCfgDevDispExistTab[aP0]){ + for(m = 0;mcfg.devId; + Port[aP0].DisplayPadSet[m].CfgBits = pLoopDispData->cfg.dispMode; + Port[aP0].DisplayPadSet[m].AreaEx[0] = pLoopDispData->cfg.areaId[0]; + Port[aP0].DisplayPadSet[m].AreaEx[1] = pLoopDispData->cfg.areaId[1]; + Port[aP0].DisplayPadSet[m].AreaEx[2] = pLoopDispData->cfg.areaId[2]; + Port[aP0].DisplayPadSet[m].UcList[0].Full = pLoopDispData->cfg.devNum[0]; + Port[aP0].DisplayPadSet[m].UcList[1].Full = pLoopDispData->cfg.devNum[1]; + } + } + + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + //Erase + norFlashAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * i) + (256 * 0); + nor_erase_sector_4k(dFlashRegisterDataChip,norFlashAddr); + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + TRegister::sIList = &this->ItemList; + TRegister::sWriteOnePort(aP0+1); + + //Read Back + Record.ReadRegisterDataOnePort(aP0+1); + } + + TRegister::sIList = &this->ItemList; + TRegister::sWritePortList(); + + Record.ReadRegisterData(); + Record.ReadDisplayPadSet(); +} + +void TConfig::WriteLoopCfgOneDisp(unsigned int aLoopId, unsigned int aDispId) +{ + unsigned char aP0,aP1; + volatile unsigned int aFlashState; + TConfigLoopDispData * pLoopDispData; + + if((aLoopId < 1)||(aLoopId > LoopCountMax))return; + if((aDispId < 1)||(aDispId > DispInLoopCountMax))return; + + aP0 = aLoopId - 1; + aP1 = aDispId - 1; + + pLoopDispData = (TConfigLoopDispData *)(LoopDispCfgBufAddr + (((aP0 * DispInLoopCountMax) + aP1) * CFG_LOAD_BUF_SIZE)); + Port[aP0].DisplayPadSet[aP1].Addr = pLoopDispData->cfg.devId; + Port[aP0].DisplayPadSet[aP1].CfgBits = pLoopDispData->cfg.dispMode; + Port[aP0].DisplayPadSet[aP1].AreaEx[0] = pLoopDispData->cfg.areaId[0]; + Port[aP0].DisplayPadSet[aP1].AreaEx[1] = pLoopDispData->cfg.areaId[1]; + Port[aP0].DisplayPadSet[aP1].AreaEx[2] = pLoopDispData->cfg.areaId[2]; + Port[aP0].DisplayPadSet[aP1].UcList[0].Full = pLoopDispData->cfg.devNum[0]; + Port[aP0].DisplayPadSet[aP1].UcList[1].Full = pLoopDispData->cfg.devNum[1]; + + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + //Erase + norFlashAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * aP0) + (256 * 0); + nor_erase_sector_4k(dFlashRegisterDataChip,norFlashAddr); + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + TRegister::sIList = &this->ItemList; + TRegister::sWriteOnePort(aP0+1); + + //Read Back + Record.ReadRegisterDataOnePort(aP0+1); + + TRegister::sIList = &this->ItemList; + TRegister::sWritePortList(); + + Record.ReadRegisterData(); + Record.ReadDisplayPadSet(); +} + +void TConfig::WriteLoopDevUserCodeAssignType() +{ + volatile unsigned int i, x; + unsigned char aP0, aP1; + + for(i=0; iItemList; + TDevProperty::sWriteAuxIdAssignTypeSignalType(aP0 + 1); + } + } + + Record.ReadDevUserSet(); +} + +void TConfig::WriteLoopOneDevUserCodeAssignType(unsigned int aLoopId, unsigned int aDevId) +{ + unsigned char aP0, aP1; + + if((aLoopId < 1)||(aLoopId > LoopCountMax))return; + if((aDevId < 1)||(aDevId > DevInLoopCountMax))return; + + aP0 = aLoopId - 1; + aP1 = aDevId - 1; + + ReadLoopCfgDevTabFromSdram((aP0+1), loopCfgDevTab); + + if(1 == loopCfgDevTab[aP1]){ + ReadLoopDevPrmFromSdram((aP0+1),(aP1+1),&loopPrm); + Port[aP0].UcList[aP1].Full = loopPrm.cfg.devNum; + Port[aP0].AssignType[aP1] = (loopPrm.cfg.assignType&0xFF); + Port[aP0].FuncSetByte[aP1] = (loopPrm.cfg.devProperty&0xFF); + + TDevProperty::sIList = &this->ItemList; + TDevProperty::sWriteAuxIdAssignTypeSignalType(aP0 + 1); + + Record.ReadDevUserSet(); + } +} + +void TConfig::WriteOneLoopDevUserCodeAssignType(unsigned int aLoopId) +{ + volatile unsigned int x; + unsigned char aP0, aP1; + + if((aLoopId < 1)||(aLoopId > LoopCountMax))return; + + aP0 = aLoopId - 1; + + ReadLoopCfgDevTabFromSdram((aP0+1), loopCfgDevTab); + for(x = 0;xItemList; + TDevProperty::sWriteAuxIdAssignTypeSignalType(aP0 + 1); + + Record.ReadDevUserSet(); +} + +void TConfig::WriteLoopDevArea() +{ + volatile unsigned int i, x; + unsigned char aP0, aP1; + + for(i=0; iItemList; + TDevProperty::sWriteAreaNumOnePort(aP0+1); + } + } +} + +void TConfig::WriteLoopOneDevArea(unsigned int aLoopId, unsigned int aDevId) +{ + unsigned char aP0, aP1; + + if((aLoopId < 1)||(aLoopId > LoopCountMax))return; + if((aDevId < 1)||(aDevId > DevInLoopCountMax))return; + + aP0 = aLoopId - 1; + aP1 = aDevId - 1; + + ReadLoopCfgDevTabFromSdram((aP0+1), loopCfgDevTab); + if(1 == loopCfgDevTab[aP1]){ + ReadLoopDevPrmFromSdram((aP0+1),(aP1+1),&loopPrm); + Port[aP0].Area[aP1] = loopPrm.cfg.areaId; + } + + TDevProperty::sIList = &this->ItemList; + TDevProperty::sWriteAreaNumOnePort(aP0+1); +} + +void TConfig::WriteOneLoopDevArea(unsigned int aLoopId) +{ + volatile unsigned int x; + unsigned char aP0, aP1; + + if((aLoopId < 1)||(aLoopId > LoopCountMax))return; + + aP0 = aLoopId - 1; + + ReadLoopCfgDevTabFromSdram((aP0+1), loopCfgDevTab); + for(x = 0;xItemList; + TDevProperty::sWriteAreaNumOnePort(aP0+1); +} + +void TConfig::WriteLoopDevDescp() +{ + unsigned int a,b,i; + unsigned int cfgDescpSdramAddr; + unsigned int cfgLoopSdramAddr; + + cfgDescpSdramAddr = dAddrSdRam_Descp; + cfgLoopSdramAddr = LoopDevCfgBufAddr + 16;//descp start 16th + + for(a=1;a<=LoopCountMax;a++){ + if(ctlPrm.cfg.loopCfgTab & (((__UINT64_TYPE__)1)<<(a-1))){ + ReadLoopCfgDevTabFromSdram(a, loopCfgDevTab); + for(b=0;b LoopCountMax))return; + if((aDevId < 1)||(aDevId > DevInLoopCountMax))return; + + a = aLoopId; + b = aDevId - 1; + + cfgDescpSdramAddr = dAddrSdRam_Descp; + cfgLoopSdramAddr = LoopDevCfgBufAddr + 16;//descp start 16th + + ReadLoopCfgDevTabFromSdram(a, loopCfgDevTab); + if(1 == loopCfgDevTab[b]){ + for(i=0;i<(32/4);i++){ + *(volatile unsigned int *)(cfgDescpSdramAddr + (((a-1)*256+b)*32) + (i*4)) = \ + *(volatile unsigned int *)(cfgLoopSdramAddr + (((a-1)*DevInLoopCountMax+b)*CFG_LOAD_BUF_SIZE) + (i*4)); + } + }else{ + for(i=0;i<(32/4);i++){ + *(volatile unsigned int *)(cfgDescpSdramAddr + (((a-1)*256+b)*32) + (i*4)) = 0; + } + } + TDescpWrite::sWrite2Flash(a); +} + +void TConfig::WriteOneLoopDevDescp(unsigned int aLoopId) +{ + unsigned int a,b,i; + unsigned int cfgDescpSdramAddr; + unsigned int cfgLoopSdramAddr; + + if((aLoopId < 1)||(aLoopId > LoopCountMax))return; + + a = aLoopId; + + cfgDescpSdramAddr = dAddrSdRam_Descp; + cfgLoopSdramAddr = LoopDevCfgBufAddr + 16;//descp start 16th + + ReadLoopCfgDevTabFromSdram(a, loopCfgDevTab); + for(b=0;bItemList; + TBusPadLnk::sWriteOnePad(aP0 + 1); + } + } +} + +void TConfig::WriteBusOneKeyNormal(unsigned int aBusId, unsigned int aKeyId) +{ + unsigned char aP0, aP1; + + if((aBusId < 1)||(aBusId > BusCountMax))return; + if((aKeyId < 1)||(aKeyId > KeyInBusCountMax))return; + + aP0 = aBusId - 1; + aP1 = aKeyId - 1; + + ReadBusCfgKeyTabFromSdram((aP0+1), busCfgKeyTab); + + if(1 == busCfgKeyTab[aP1]){ + ReadBusKeyPrmFromSdram((aP0+1),(aP1+1),&busPrm); + HandCtlBoard[aP0].UcList[aP1].Full = busPrm.cfg.serNum; + HandCtlBoard[aP0].AssignType[aP1] = busPrm.cfg.devType; + HandCtlBoard[aP0].IsMatchAreaAssign[aP1] = busPrm.cfg.ctlMode; + HandCtlBoard[aP0].Area[aP1] = busPrm.cfg.areaId; + + TBusPadLnk::sIList = &this->ItemList; + TBusPadLnk::sWriteOnePad(aP0 + 1); + } +} + +void TConfig::WriteOneBusKeyNormal(unsigned int aBusId) +{ + unsigned int x; + unsigned char aP0, aP1; + + if((aBusId < 1)||(aBusId > BusCountMax))return; + + aP0 = aBusId - 1; + + ReadBusCfgKeyTabFromSdram((aP0+1), busCfgKeyTab); + for(x = 0;xItemList; + TBusPadLnk::sWriteOnePad(aP0 + 1); +} + +void TConfig::WriteDirCfgKeyNormal() +{ + unsigned int fAddr; + volatile unsigned int i, x, a, b, GetSta; + unsigned char aP0, aP1; + + for(i=0; iItemList; + TDirectPadCfg::sWrite2Flash(aP0 + 1); + + DirectCtlBoard[aP0].SendPadCfg2Pad(aP0); + } + } +} + +void TConfig::WriteDirOneKeyNormal(unsigned int aDirId, unsigned int aKeyId) +{ + unsigned char aP0, aP1; + + if((aDirId < 1)||(aDirId > DirCountMax))return; + if((aKeyId < 1)||(aKeyId > KeyInDirCountMax))return; + + aP0 = aDirId - 1; + aP1 = aKeyId - 1; + + ReadDirCfgKeyTabFromSdram((aP0+1), dirCfgKeyTab); + if(1 == dirCfgKeyTab[aP1]){ + ReadDirKeyPrmFromSdram((aP0+1),(aP1+1),&dirPrm); + DirectCtlBoard[aP0].IsRegisted[aP1] = dirPrm.cfg.isAble; + DirectCtlBoard[aP0].IsCheckError[aP1] = dirPrm.cfg.errDetFlag; + DirectCtlBoard[aP0].IsOutputState[aP1] = 0; + //DirectCtlBoard[aP0].PadIsProhibit = 1; + } + + TDirectPadCfg::sIList = &this->ItemList; + TDirectPadCfg::sWrite2Flash(aP0 + 1); + + DirectCtlBoard[aP0].SendPadCfg2Pad(aP0); +} + +void TConfig::WriteOneDirKeyNormal(unsigned int aDirId) +{ + volatile unsigned int x; + unsigned char aP0, aP1; + + if((aDirId < 1)||(aDirId > DirCountMax))return; + + aP0 = aDirId - 1; + + ReadDirCfgKeyTabFromSdram((aP0+1), dirCfgKeyTab); + for(x = 0;xItemList; + TDirectPadCfg::sWrite2Flash(aP0 + 1); + + DirectCtlBoard[aP0].SendPadCfg2Pad(aP0); +} + +void TConfig::WriteDirKeyUserCodeAssignType() +{ + unsigned int fAddr; + volatile unsigned int i, x, a, b, GetSta; + unsigned char aP0, aP1; + + for(i=0; iItemList; + TDirectPadCfg::sWriteUserCodeAssignType(aP0 + 1); + } + } + + Record.ReadDirectPadUserSet(); +} + +void TConfig::WriteDirOneKeyUserCodeAssignType(unsigned int aDirId, unsigned int aKeyId) +{ + unsigned char aP0, aP1; + + if((aDirId < 1)||(aDirId > DirCountMax))return; + if((aKeyId < 1)||(aKeyId > KeyInDirCountMax))return; + + aP0 = aDirId - 1; + aP1 = aKeyId - 1; + + ReadDirCfgKeyTabFromSdram((aP0+1), dirCfgKeyTab); + if(1 == dirCfgKeyTab[aP1]){ + ReadDirKeyPrmFromSdram((aP0+1),(aP1+1),&dirPrm); + DirectCtlBoard[aP0].UcList[aP1].Full = dirPrm.cfg.serNum; + DirectCtlBoard[aP0].AssignType[aP1] = (dirPrm.cfg.ctlDevType&0xFF); + } + + TDirectPadCfg::sIList = &this->ItemList; + TDirectPadCfg::sWriteUserCodeAssignType(aP0 + 1); + + Record.ReadDirectPadUserSet(aP0 + 1); +} + +void TConfig::WriteOneDirKeyUserCodeAssignType(unsigned int aDirId) +{ + volatile unsigned int x; + unsigned char aP0, aP1; + + if((aDirId < 1)||(aDirId > DirCountMax))return; + + aP0 = aDirId - 1; + + ReadDirCfgKeyTabFromSdram((aP0+1), dirCfgKeyTab); + for(x = 0;xItemList; + TDirectPadCfg::sWriteUserCodeAssignType(aP0 + 1); + + Record.ReadDirectPadUserSet(aP0 + 1); +} + +void TConfig::WriteDirKeyArea() +{ + unsigned int fAddr; + volatile unsigned int i, x, a, b, GetSta; + unsigned char aP0, aP1; + + for(i=0; iItemList; + TDirectPadCfg::sWriteAreaNum(); +} + +void TConfig::WriteDirOneKeyArea(unsigned int aDirId, unsigned int aKeyId) +{ + unsigned char aP0, aP1; + + if((aDirId < 1)||(aDirId > DirCountMax))return; + if((aKeyId < 1)||(aKeyId > KeyInDirCountMax))return; + + aP0 = aDirId - 1; + aP1 = aKeyId - 1; + + ReadDirCfgKeyTabFromSdram((aP0+1), dirCfgKeyTab); + if(1 == dirCfgKeyTab[aP1]){ + ReadDirKeyPrmFromSdram((aP0+1),(aP1+1),&dirPrm); + DirectCtlBoard[aP0].Area[aP1] = dirPrm.cfg.areaId; + } + + TDirectPadCfg::sIList = &this->ItemList; + TDirectPadCfg::sWriteAreaNum(); +} + +void TConfig::WriteOneDirKeyArea(unsigned int aDirId) +{ + volatile unsigned int x; + unsigned char aP0, aP1; + + if((aDirId < 1)||(aDirId > DirCountMax))return; + + aP0 = aDirId - 1; + + ReadDirCfgKeyTabFromSdram((aP0+1), dirCfgKeyTab); + for(x = 0;xItemList; + TDirectPadCfg::sWriteAreaNum(); +} + +void TConfig::WriteDirCfgDescp() +{ + unsigned int a,b,i; + unsigned int cfgDescpSdramAddr; + unsigned int cfgDirSdramAddr; + + cfgDescpSdramAddr = dAddrSdRam_Descp + 40 * 8192; + cfgDirSdramAddr = DirKeyCfgBufAddr + 12;//descp start 12th + + for(a=1;a<=DirCountMax;a++){ + if(ctlPrm.cfg.dirCfgTab & (1<<(a-1))){ + ReadDirCfgKeyTabFromSdram(a, dirCfgKeyTab); + for(b=0;b DirCountMax))return; + if((aKeyId < 1)||(aKeyId > KeyInDirCountMax))return; + + a = aDirId; + b = aKeyId - 1; + + cfgDescpSdramAddr = dAddrSdRam_Descp + 40 * 8192; + cfgDirSdramAddr = DirKeyCfgBufAddr + 12;//descp start 12th + + ReadDirCfgKeyTabFromSdram(a, dirCfgKeyTab); + if(1 == dirCfgKeyTab[b]){ + for(i=0;i<(32/4);i++){ + *(volatile unsigned int *)(cfgDescpSdramAddr + (((a-1)*8+b+1)*32) + (i*4)) = \ + *(volatile unsigned int *)(cfgDirSdramAddr + (((a-1)*KeyInDirCountMax+b)*CFG_LOAD_BUF_SIZE) + (i*4)); + } + }else{ + for(i=0;i<(32/4);i++){ + *(volatile unsigned int *)(cfgDescpSdramAddr + (((a-1)*8+b+1)*32) + (i*4)) = 0; + } + } + + TDescpWrite::sWrite2Flash(66); +} + +void TConfig::WriteOneDirDescp(unsigned int aDirId) +{ + unsigned int a,b,i; + unsigned int cfgDescpSdramAddr; + unsigned int cfgDirSdramAddr; + + if((aDirId < 1)||(aDirId > DirCountMax))return; + + a = aDirId; + + cfgDescpSdramAddr = dAddrSdRam_Descp + 40 * 8192; + cfgDirSdramAddr = DirKeyCfgBufAddr + 12;//descp start 12th + + ReadDirCfgKeyTabFromSdram(a, dirCfgKeyTab); + for(b=0;bprm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + pCfgTxPkg->prm.data[2] = 0; + + oBufProcess(); +} + +void TConfig::rpyData(unsigned char * pData, unsigned int len) +{ + unsigned int i; + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = len; + + for(i=0;iprm.data[i] = pData[i]; + + oBufProcess(); +} + +void TConfig::rpyCmd09() +{ + unsigned int i = 0,a = 0; + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = dCtlCFG_BufCount; + + pConfigCtlDataTX->cfg.ctlAddr = MainCtl.fData.Split.MyNum; + + pConfigCtlDataTX->cfg.loopCount = 0; + pConfigCtlDataTX->cfg.loopCfgTab = 0; + for(i=0; icfg.loopCfgTab |= (((__UINT64_TYPE__)1)<cfg.loopCount++; + } + } + + pConfigCtlDataTX->cfg.busCfgTab = 0; + pConfigCtlDataTX->cfg.busPanelCount = 0; + for(i=0; icfg.busCfgTab |= (1<cfg.busPanelCount++; + break; + } + } + } + + pConfigCtlDataTX->cfg.dirCfgTab = 0; + pConfigCtlDataTX->cfg.dirPanelCount = 0; + for(i=0; icfg.dirCfgTab |= (1<cfg.dirPanelCount++; + break; + } + } + } + + pConfigCtlDataTX->cfg.areaCount = AreaSetting.Count; + pConfigCtlDataTX->cfg.linkCount = InterLink.LinkCount; + + for(i=0;i<32;i++) + pConfigCtlDataTX->cfg.desc[i] = PrjName[i]; + + oBufProcess(); +} + +void TConfig::rpyCmd12() +{ + unsigned int aId,aDevId,i; + + aId = pCfgRxPkg->prm.data[0] - 1; + aDevId = pCfgRxPkg->prm.data[1] - 1; + + if((aId >= LoopCountMax) || (aDevId >= DevInLoopCountMax)){ + rpyNoData(); + }else + if((MainCtl.fData.Split.ExistTablePort[aId])&&((Port[aId].UcList[aDevId].Full))||(Port[aId].dTypeTable[aDevId])||(Port[aId].AssignType[aDevId])){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 48; + + pConfigLoopDataTX->cfg.id = pCfgRxPkg->prm.data[0]; + pConfigLoopDataTX->cfg.devId = pCfgRxPkg->prm.data[1]; + pConfigLoopDataTX->cfg.devType = Port[aId].dTypeTable[aDevId]; + pConfigLoopDataTX->cfg.assignType = Port[aId].AssignType[aDevId]; + pConfigLoopDataTX->cfg.devProperty = Port[aId].FuncSetByte[aDevId]; + pConfigLoopDataTX->cfg.areaId = Port[aId].Area[aDevId]; + pConfigLoopDataTX->cfg.delayTime = 0; + pConfigLoopDataTX->cfg.devNum = Port[aId].UcList[aDevId].Full; + + for(i=0;i<(32/4);i++){ + pConfigLoopDataTX->D32[4+i] = *(volatile unsigned int *)(dAddrSdRam_Descp + ((aId*256+aDevId)*32) + (i*4)); + } + + oBufProcess(); + }else{ + rpyNoData(); + } +} + +void TConfig::rpyCmd22() +{ + unsigned int aId,aKeyId,i; + + aId = pCfgRxPkg->prm.data[0] - 1; + aKeyId = pCfgRxPkg->prm.data[1] - 1; + + if((aId >= BusCountMax) || (aKeyId >= KeyInBusCountMax)){ + pCfgRxPkg->prm.data[2] = 0; + pCfgRxPkg->prm.data[3] = HandCtlBoard[aId].KeyCount; + rpyData(pCfgRxPkg->prm.data, 4); + }else + if((1 == HandCtlBoard[aId].IsMatchAreaAssign[aKeyId])||(HandCtlBoard[aId].Area[aKeyId]) || \ + (HandCtlBoard[aId].UcList[aKeyId].Full)){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = dBusKeyCFG_BufCount; + + pConfigBusDataTX->cfg.id = pCfgRxPkg->prm.data[0]; + pConfigBusDataTX->cfg.keyId = pCfgRxPkg->prm.data[1]; + pConfigBusDataTX->cfg.keyCount = HandCtlBoard[aId].KeyCount; + pConfigBusDataTX->cfg.ctlMode = HandCtlBoard[aId].IsMatchAreaAssign[aKeyId]; + pConfigBusDataTX->cfg.devType = HandCtlBoard[aId].AssignType[aKeyId]; + pConfigBusDataTX->cfg.areaId = HandCtlBoard[aId].Area[aKeyId]; + pConfigBusDataTX->cfg.serNum = HandCtlBoard[aId].UcList[aKeyId].Full; + + for(i=0;i<32;i++){ + pConfigBusDataTX->cfg.desc[i] = 0; + } + + oBufProcess(); + }else{ + pCfgRxPkg->prm.data[2] = 0; + pCfgRxPkg->prm.data[3] = HandCtlBoard[aId].KeyCount; + rpyData(pCfgRxPkg->prm.data, 4); + } +} + +void TConfig::rpyCmd32() +{ + unsigned int aId,aKeyId,i; + + aId = pCfgRxPkg->prm.data[0] - 1; + aKeyId = pCfgRxPkg->prm.data[1] - 1; + + if((aId >= DirCountMax) || (aKeyId >= KeyInDirCountMax)){ + rpyNoData(); + }else + if(DirectCtlBoard[aId].UcList[aKeyId].Full){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = dDirKeyCFG_BufCount; + + pConfigDirDataTX->cfg.id = pCfgRxPkg->prm.data[0]; + pConfigDirDataTX->cfg.keyId = pCfgRxPkg->prm.data[1]; + pConfigDirDataTX->cfg.isAble = DirectCtlBoard[aId].IsRegisted[aKeyId]; + pConfigDirDataTX->cfg.errDetFlag = DirectCtlBoard[aId].IsCheckError[aKeyId]; + pConfigDirDataTX->cfg.outProp = 0;//DirectCtlBoard[aId].IsOutputState[aKeyId]; + pConfigDirDataTX->cfg.ctlDevType = DirectCtlBoard[aId].AssignType[aKeyId]; + pConfigDirDataTX->cfg.areaId = DirectCtlBoard[aId].Area[aKeyId]; + pConfigDirDataTX->cfg.serNum = DirectCtlBoard[aId].UcList[aKeyId].Full; + + for(i=0;i<(32/4);i++){ + pConfigDirDataTX->D32[3+i] = \ + *(volatile unsigned int *)((dAddrSdRam_Descp + 40 * 8192) + ((aId*8+aKeyId+1)*32) + (i*4)); + } + + oBufProcess(); + }else{ + rpyNoData(); + } +} + +void TConfig::rpyCmd42() +{ + unsigned int aId,aIdf,sAddr,i; + + aId = pCfgRxPkg->prm.data[1]; + aId<<=8; + aId |= pCfgRxPkg->prm.data[0]; + + if((0 == aId)||(aId > AreaCountMax)){ + rpyNoData(); + return; + } + + aId = aId - 1; + sAddr = dAddrSdRam_4Area + (aId * 64); + aIdf = *(volatile unsigned int *)(sAddr); + + if(aIdf == 0xA8A7A6A5){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 56; + + pConfigAreaDataTX->cfg.id = aId + 1; + sAddr = dAddrSdRam_4Area + (aId * 64) + 4; + AsiiToData(&pConfigAreaDataTX->cfg.serNum, ((char *)sAddr), 8); + + sAddr = dAddrSdRam_4Area + (aId * 64) + 16; + for(i=0;i<16;i++){ + pConfigAreaDataTX->cfg.profile[i] = *(volatile unsigned char *)(sAddr + i); + } + + sAddr = dAddrSdRam_4Area + (aId * 64) + 32; + for(i=0;i<32;i++){ + pConfigAreaDataTX->cfg.desc[i] = *(volatile unsigned char *)(sAddr + i); + } + + oBufProcess(); + }else{ + rpyNoData(); + } +} + +void TConfig::rpyCmd52() +{ + unsigned int aId,aInx,sAddr,i,m; + unsigned char aInCount = 0,aOutCount = 0; + unsigned int onceFlag = 1; + + aId = pCfgRxPkg->prm.data[1]; + aId<<=8; + aId |= pCfgRxPkg->prm.data[0]; + + if((0 == aId)||(aId > LinkCountMax)){ + rpyNoData(); + return; + } + + aInx = aId - 1; + + sAddr = dSdAddrLinkageExp + (aInx * 1024); + if(((*(volatile unsigned char *)(sAddr + 0)) == 'T') && ((*(volatile unsigned char *)(sAddr + 1)) == 'R') && \ + ((*(volatile unsigned char *)(sAddr + 2)) == 'U') && ((*(volatile unsigned char *)(sAddr + 3)) == 'E')){ + + pUartCfgLinkDataTX.cfg.head = TEST_UART_HEAD; + pUartCfgLinkDataTX.cfg.cmd = pCfgRxPkg->prm.cmd; + pUartCfgLinkDataTX.cfg.count = 0; + pUartCfgLinkDataTX.cfg.id = aId; + + pLinkEquationTX = (TEquation *)(sAddr + 16); + + //--------------------input-------------------------------- + pUartCfgLinkDataTX.cfg.len = 20; + + for(i=0;i<16;i++){ + if((0 != pLinkEquationTX->prm.inEqn[i][0])&&(0 != pLinkEquationTX->prm.inEqn[i][1])){ + if(onceFlag){ + onceFlag = 0; + pUartCfgLinkDataTX.formula.isInput = 0x5A; + }else{ + pUartCfgLinkDataTX.formula.isInput = 0x51; + } + + pUartCfgLinkDataTX.formula.ord = i; + for(m=0;m<8;m++){ + pUartCfgLinkDataTX.formula.eqn[m] = pLinkEquationTX->prm.inEqn[i][m]; + } + pUartCfgLinkDataTX.formula.eqn[8] = ' '; + pUartCfgLinkDataTX.formula.eqn[9] = pLinkEquationTX->prm.inEqn[i][8]; + pUartCfgLinkDataTX.formula.eqn[10] = pLinkEquationTX->prm.inEqn[i][9]; + pUartCfgLinkDataTX.formula.eqn[11] = pLinkEquationTX->prm.inEqn[i][10]; + pUartCfgLinkDataTX.formula.eqn[12] = ' '; + pUartCfgLinkDataTX.formula.eqn[13] = pLinkEquationTX->prm.inEqn[i][11]; + pUartCfgLinkDataTX.formula.eqn[14] = pLinkEquationTX->prm.inEqn[i][12]; + pUartCfgLinkDataTX.formula.eqn[15] = pLinkEquationTX->prm.inEqn[i][13]; + aInCount++; + iLinkTXBuf(pUartCfgLinkDataTX.D8); + } + } + if(onceFlag){ + onceFlag = 0; + pUartCfgLinkDataTX.formula.ord = 16; + pUartCfgLinkDataTX.formula.isInput = 0x5A; + for(m=0;m<16;m++){ + pUartCfgLinkDataTX.formula.eqn[m] = 0; + } + iLinkTXBuf(pUartCfgLinkDataTX.D8); + } + + //--------------------output-------------------------------- + pUartCfgLinkDataTX.cfg.len = 20; + pUartCfgLinkDataTX.formula.isInput = 0x15; + for(i=0;i<16;i++){ + if((0 != pLinkEquationTX->prm.outEqn[i][0])&&(0 != pLinkEquationTX->prm.outEqn[i][1])){ + pUartCfgLinkDataTX.formula.ord = i; + for(m=0;m<8;m++){ + pUartCfgLinkDataTX.formula.eqn[m] = pLinkEquationTX->prm.outEqn[i][m]; + } + pUartCfgLinkDataTX.formula.eqn[8] = ' '; + pUartCfgLinkDataTX.formula.eqn[9] = pLinkEquationTX->prm.outEqn[i][8]; + pUartCfgLinkDataTX.formula.eqn[10] = pLinkEquationTX->prm.outEqn[i][9]; + pUartCfgLinkDataTX.formula.eqn[11] = pLinkEquationTX->prm.outEqn[i][10]; + pUartCfgLinkDataTX.formula.eqn[12] = ' '; + pUartCfgLinkDataTX.formula.eqn[13] = pLinkEquationTX->prm.outEqn[i][11]; + pUartCfgLinkDataTX.formula.eqn[14] = pLinkEquationTX->prm.outEqn[i][12]; + pUartCfgLinkDataTX.formula.eqn[15] = pLinkEquationTX->prm.outEqn[i][13]; + aOutCount++; + iLinkTXBuf(pUartCfgLinkDataTX.D8); + } + } + + //--------------------send end-------------------------------- + pUartCfgLinkDataTX.cfg.len = 8; + pUartCfgLinkDataTX.cfg.endFlag = 0xA0; + pUartCfgLinkDataTX.cfg.inCount = aInCount; + pUartCfgLinkDataTX.cfg.outCount = aOutCount; + if((*(volatile unsigned char *)(sAddr + 4)) == 'M'){ + pUartCfgLinkDataTX.cfg.isMask = 1; + }else{ + pUartCfgLinkDataTX.cfg.isMask = 0; + } + + if((*(volatile unsigned char *)(sAddr + 5)) == 'S'){ + pUartCfgLinkDataTX.cfg.isStop = 1; + }else{ + pUartCfgLinkDataTX.cfg.isStop = 0; + } + + if((*(volatile unsigned char *)(sAddr + 6)) == 'F'){ + pUartCfgLinkDataTX.cfg.isForceAutoExec = 1; + }else{ + pUartCfgLinkDataTX.cfg.isForceAutoExec = 0; + } + iLinkTXBuf(pUartCfgLinkDataTX.D8); + }else{ + rpyNoData(); + } +} + +void TConfig::rpyCmd62() +{ + unsigned int aId,aDevId,i,m; + + aId = pCfgRxPkg->prm.data[0] - 1; + aDevId = pCfgRxPkg->prm.data[1] - 1; + + if((aId >= LoopCountMax) || (aDevId >= DevInLoopCountMax)){ + rpyNoData(); + }else + if((MainCtl.fData.Split.ExistTablePort[aId] && Port[aId].ExistTable[aDevId]) && (DevDispType == Port[aId].dTypeTable[aDevId])){//是层显 + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 20; + + for(m=0;m<16;m++){ + if(Port[aId].DisplayPadSet[m].Addr == pCfgRxPkg->prm.data[1]){ + break; + } + } + if(16 == m){ + rpyNoData(); + }else{ + pConfigLoopDispDataTX->cfg.id = pCfgRxPkg->prm.data[0]; + pConfigLoopDispDataTX->cfg.devId = pCfgRxPkg->prm.data[1]; + pConfigLoopDispDataTX->cfg.devType = DevDispType; + pConfigLoopDispDataTX->cfg.ord = m+1; + pConfigLoopDispDataTX->cfg.dispMode = Port[aId].DisplayPadSet[m].CfgBits; + pConfigLoopDispDataTX->cfg.areaId[0] = Port[aId].DisplayPadSet[m].AreaEx[0]; + pConfigLoopDispDataTX->cfg.areaId[1] = Port[aId].DisplayPadSet[m].AreaEx[1]; + pConfigLoopDispDataTX->cfg.areaId[2] = Port[aId].DisplayPadSet[m].AreaEx[2]; + pConfigLoopDispDataTX->cfg.devNum[0] = Port[aId].DisplayPadSet[m].UcList[0].Full; + pConfigLoopDispDataTX->cfg.devNum[1] = Port[aId].DisplayPadSet[m].UcList[1].Full; + + oBufProcess(); + } + }else{ + rpyNoData(); + } +} + + +void TConfig::iBufProcess() +{ + unsigned int i,a,b; + unsigned int desCount; + unsigned int aLinkCount; + unsigned int aCNum,aP0,aP1; + + //if(uartRxFlag){ + //uartRxFlag = 0; + + if(usbCdcRxFlag){ + usbCdcRxFlag = 0; + + switch(pCfgRxPkg->prm.cmd){ + case cfgCMD04: + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 0; + + oBufProcess(); + break; + + case cfgCMD07://save cfg + WriteAllLinkCfgToNorFlash(); + WriteAllUartCfg(); + + haveSaveCfgFlag = 1; + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 1; + + oBufProcess(); + break; + + case cfgCMD08: + if(pCfgRxPkg->prm.len > dCtlCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + + CfgPrmInit(); + + for(i=0;iprm.len;i++){ + ctlPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 1; + } + + oBufProcess(); + break; + + case cfgCMD09: + rpyCmd09(); + break; + + case cfgCMD11: + if(pCfgRxPkg->prm.len > dLoopDevCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + loopPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteLoopDevPrmToSdram(&loopPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + WriteLoopCfgOneDevInTabToSdram(loopPrm.cfg.id, loopPrm.cfg.devId); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD12: + rpyCmd12(); + break; + + case cfgCMD15://save loop one dev cfg + if(pCfgRxPkg->prm.len > dLoopDevCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + loopPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteLoopDevPrmToSdram(&loopPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + WriteLoopCfgOneDevInTabToSdram(loopPrm.cfg.id, loopPrm.cfg.devId); + + WriteLoopOneDevUserCodeAssignType(loopPrm.cfg.id, loopPrm.cfg.devId); + WriteLoopOneDevArea(loopPrm.cfg.id, loopPrm.cfg.devId); + WriteLoopOneDevDescp(loopPrm.cfg.id, loopPrm.cfg.devId); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD17://save loop cfg + if((pCfgRxPkg->prm.data[0] > 0)&&(pCfgRxPkg->prm.data[0] <= LoopCountMax)){ + WriteOneLoopDevUserCodeAssignType(pCfgRxPkg->prm.data[0]); + WriteOneLoopDevArea(pCfgRxPkg->prm.data[0]); + WriteOneLoopDevDescp(pCfgRxPkg->prm.data[0]); + + pCfgTxPkg->prm.data[2] = 0x01; + }else + if(0 == pCfgRxPkg->prm.data[0]){ + WriteLoopDevUserCodeAssignType(); + WriteLoopDevArea(); + WriteLoopDevDescp(); + + pCfgTxPkg->prm.data[2] = 0x01; + }else{ + pCfgTxPkg->prm.data[2] = 0x00; + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + + oBufProcess(); + break; + + case cfgCMD21: + if(pCfgRxPkg->prm.len > dBusKeyCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + busPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteBusKeyPrmToSdram(&busPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + WriteBusCfgOneKeyInTabToSdram(busPrm.cfg.id, busPrm.cfg.keyId); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD22: + rpyCmd22(); + break; + + case cfgCMD25://save bus one key cfg + if(pCfgRxPkg->prm.len > dBusKeyCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + busPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteBusKeyPrmToSdram(&busPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + WriteBusCfgOneKeyInTabToSdram(busPrm.cfg.id, busPrm.cfg.keyId); + + WriteBusOneKeyNormal(busPrm.cfg.id, busPrm.cfg.keyId); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD27://save bus cfg + if((pCfgRxPkg->prm.data[0] > 0)&&(pCfgRxPkg->prm.data[0] <= BusCountMax)){ + WriteOneBusKeyNormal(pCfgRxPkg->prm.data[0]); + + pCfgTxPkg->prm.data[2] = 0x01; + }else + if(0 == pCfgRxPkg->prm.data[0]){ + WriteBusCfgKeyNormal(); + + pCfgTxPkg->prm.data[2] = 0x01; + }else{ + pCfgTxPkg->prm.data[2] = 0x00; + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + + oBufProcess(); + break; + + case cfgCMD31: + if(pCfgRxPkg->prm.len > dDirKeyCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + dirPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteDirKeyPrmToSdram(&dirPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + WriteDirCfgOneKeyInTabToSdram(dirPrm.cfg.id, dirPrm.cfg.keyId); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD32: + rpyCmd32(); + break; + + case cfgCMD35://save dir one key cfg + if(pCfgRxPkg->prm.len > dDirKeyCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + dirPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteDirKeyPrmToSdram(&dirPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + WriteDirCfgOneKeyInTabToSdram(dirPrm.cfg.id, dirPrm.cfg.keyId); + + WriteDirOneKeyNormal(dirPrm.cfg.id, dirPrm.cfg.keyId); + WriteDirOneKeyUserCodeAssignType(dirPrm.cfg.id, dirPrm.cfg.keyId); + WriteDirOneKeyArea(dirPrm.cfg.id, dirPrm.cfg.keyId); + WriteDirOneDescp(dirPrm.cfg.id, dirPrm.cfg.keyId); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD37://save dir cfg + if((pCfgRxPkg->prm.data[0] > 0)&&(pCfgRxPkg->prm.data[0] <= DirCountMax)){ + WriteOneDirKeyNormal(pCfgRxPkg->prm.data[0]); + WriteOneDirKeyUserCodeAssignType(pCfgRxPkg->prm.data[0]); + WriteOneDirKeyArea(pCfgRxPkg->prm.data[0]); + WriteOneDirDescp(pCfgRxPkg->prm.data[0]); + + pCfgTxPkg->prm.data[2] = 0x01; + }else + if(0 == pCfgRxPkg->prm.data[0]){ + WriteDirCfgKeyNormal(); + WriteDirKeyUserCodeAssignType(); + WriteDirKeyArea(); + WriteDirCfgDescp(); + + pCfgTxPkg->prm.data[2] = 0x01; + }else{ + pCfgTxPkg->prm.data[2] = 0x00; + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + + oBufProcess(); + break; + + case cfgCMD41: + if(pCfgRxPkg->prm.len > dAreaCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + areaPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteAreaPrmToSdram(&areaPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + areaCfgTab[areaPrm.cfg.id - 1] = 1; + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD42: + rpyCmd42(); + break; + + case cfgCMD51: + if(pCfgRxPkg->prm.len > dLinkUartCFG_BufCount){ + linkPrm.cfg.uartFlag = 1; + } + + if((0x51 == pUartCfgLinkDataRX->formula.isInput)||(0x5A == pUartCfgLinkDataRX->formula.isInput)){//input + if(0x5A == pUartCfgLinkDataRX->formula.isInput){ + linkPrm.cfg.inTab = 0; + linkPrm.cfg.outTab = 0; + } + if(16 == pUartCfgLinkDataRX->formula.ord){ + __nop(); + }else + if(pUartCfgLinkDataRX->formula.ord < 16){ + linkPrm.cfg.inTab |= (1<formula.ord); + for(b=0;b<16;b++){ + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][b] = pUartCfgLinkDataRX->formula.eqn[b]; + } + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][8] = linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][9]; + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][9] = linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][10]; + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][10] = linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][11]; + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][11] = linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][13]; + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][12] = linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][14]; + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][13] = linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][15]; + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][14] = 0; + linkPrm.cfg.eqn.prm.inEqn[pUartCfgLinkDataRX->formula.ord][15] = 0; + }else{ + linkPrm.cfg.uartFlag = 1; + } + }else + if(0x15 == pUartCfgLinkDataRX->formula.isInput){//output + if(pUartCfgLinkDataRX->formula.ord < 16){ + linkPrm.cfg.outTab |= (1<formula.ord); + for(b=0;b<16;b++){ + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][b] = pUartCfgLinkDataRX->formula.eqn[b]; + } + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][8] = linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][9]; + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][9] = linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][10]; + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][10] = linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][11]; + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][11] = linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][13]; + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][12] = linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][14]; + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][13] = linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][15]; + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][14] = 0; + linkPrm.cfg.eqn.prm.outEqn[pUartCfgLinkDataRX->formula.ord][15] = 0; + }else{ + linkPrm.cfg.uartFlag = 1; + } + }else + if((0xA0 == pUartCfgLinkDataRX->cfg.endFlag)||(0xA5 == pUartCfgLinkDataRX->cfg.endFlag)){//结束或保存 + if((pUartCfgLinkDataRX->cfg.inCount > 16)||(pUartCfgLinkDataRX->cfg.outCount > 16)){ + linkPrm.cfg.uartFlag = 1; + }else{ + aLinkCount = 0; + for(i=0;i<16;i++){ + if(linkPrm.cfg.inTab & (1<cfg.inCount)linkPrm.cfg.uartFlag = 1; + + aLinkCount = 0; + for(i=0;i<16;i++){ + if(linkPrm.cfg.outTab & (1<cfg.outCount)linkPrm.cfg.uartFlag = 1; + + linkPrm.cfg.inCount = pUartCfgLinkDataRX->cfg.inCount; + linkPrm.cfg.outCount = pUartCfgLinkDataRX->cfg.outCount; + + linkPrm.cfg.id = pUartCfgLinkDataRX->cfg.id; + linkPrm.cfg.isStop = pUartCfgLinkDataRX->cfg.isStop; + linkPrm.cfg.isMask = pUartCfgLinkDataRX->cfg.isMask; + linkPrm.cfg.isForceAutoExec = pUartCfgLinkDataRX->cfg.isForceAutoExec; + } + + if(linkPrm.cfg.uartFlag){//串口配置错误 + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + if((0 == linkPrm.cfg.id)||(linkPrm.cfg.id > LinkCountMax)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + if(WriteLinkCfgToSdram(&linkPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + + linkCfgTab[linkPrm.cfg.id - 1] = 1; + + if(0xA5 == pUartCfgLinkDataRX->cfg.endFlag){//保存 + WriteOneLinkCfgToNorFlash(linkPrm.cfg.id); + } + } + } + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = (linkPrm.cfg.id & 0xFF); + pCfgTxPkg->prm.data[1] = ((linkPrm.cfg.id>>8) & 0xFF); + + oBufProcess(); + + linkPrm.cfg.uartFlag = 0; + } + + break; + + case cfgCMD52: + rpyCmd52(); + break; + + case cfgCMD57://save link cfg + if(0xCC == pCfgRxPkg->prm.data[0]){//start send + for(i = 0;iprm.data[2] = 0x01; + }else + if(0xA5 == pCfgRxPkg->prm.data[0]){//end send and save + WriteAllLinkCfgToNorFlash(); + + pCfgTxPkg->prm.data[2] = 0x01; + }else{ + pCfgTxPkg->prm.data[2] = 0x00; + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + + oBufProcess(); + break; + + case cfgCMD61: + if(pCfgRxPkg->prm.len > dLoopDispCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + loopDispPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteLoopDevDispPrmToSdram(&loopDispPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + loopDevDispCount[loopDispPrm.cfg.id]++; + loopCfgDevDispExistTab[loopDispPrm.cfg.id - 1] = 1; + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD62: + rpyCmd62(); + break; + + case cfgCMD65: + if(pCfgRxPkg->prm.len > dLoopDispCFG_BufCount){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[2] = 0; + }else{ + for(i=0;iprm.len;i++){ + loopDispPrm.D8[i] = pCfgRxPkg->prm.data[i]; + } + + if(WriteLoopDevDispPrmToSdram(&loopDispPrm)){ + pCfgTxPkg->prm.data[2] = 0x00; + }else{ + pCfgTxPkg->prm.data[2] = 0x01; + + loopCfgDevDispExistTab[loopDispPrm.cfg.id - 1] = 1; + + WriteLoopCfgOneDisp(loopDispPrm.cfg.id, loopDispPrm.cfg.ord); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[1]; + } + + oBufProcess(); + break; + + case cfgCMD67: + if(0xCC == pCfgRxPkg->prm.data[0]){//start send + for(i = 0;i <= LoopCountMax;i++){ + loopDevDispCount[i] = 0; + loopCfgDevDispExistTab[i] = 0; + } + + pCfgTxPkg->prm.data[2] = 0x01; + }else + if(0xA5 == pCfgRxPkg->prm.data[0]){//end send and save + WriteLoopCfgAllDisp(); + + pCfgTxPkg->prm.data[2] = 0x01; + }else{ + pCfgTxPkg->prm.data[2] = 0x00; + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[0]; + + oBufProcess(); + break; + + case cfgCMD71: + aCNum = pCfgRxPkg->prm.data[0]; + aP0 = pCfgRxPkg->prm.data[1]; + aP1 = pCfgRxPkg->prm.data[2]; + + if((pCfgRxPkg->prm.len > 36) || (aCNum > dNETWORK_MACHINE_COUNT) || (0 == aCNum) || (0 == aP0) || (0 == aP1)){ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[1]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[2]; + pCfgTxPkg->prm.data[2] = 0; + }else{ + //aP1 = aP1 - 1; + if((aP0 <= LoopCountMax) && (aP1 <= DevInLoopCountMax)){ + if(0xA5 == pCfgRxPkg->prm.data[3]){ + for(i=0;i<256;i++){ + fNetworkReg.PortDevDescp.Body[i].D32[0] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[1] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[2] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[3] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[4] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[5] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[6] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[7] = 0; + } + } + for(i=0;i<(pCfgRxPkg->prm.len - 4);i++){ + fNetworkReg.PortDevDescp.Body[aP1].D8[i] = pCfgRxPkg->prm.data[i+4]; + } + for(i = (pCfgRxPkg->prm.len - 4);i < 32; i++){ + fNetworkReg.PortDevDescp.Body[aP1].D8[pCfgRxPkg->prm.len - 4] = 0; + } + if(0x5C == pCfgRxPkg->prm.data[3]){ + fNetworkReg.SavePortDescp(aCNum, aP0); + fNetworkReg.ReadPortDescp(aCNum, aP0); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[1]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[2]; + pCfgTxPkg->prm.data[2] = 1; + }else + if((aP0 >= 66) && (aP0 < (66 + DirCountMax)) && (aP1 <= KeyInDirCountMax)){ + aP0 = aP0 - 66; + if(0xA5 == pCfgRxPkg->prm.data[3]){ + for(i=0;i<256;i++){ + fNetworkReg.PortDevDescp.Body[i].D32[0] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[1] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[2] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[3] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[4] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[5] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[6] = 0; + fNetworkReg.PortDevDescp.Body[i].D32[7] = 0; + } + } + for(i=0;i<(pCfgRxPkg->prm.len - 4);i++){ + fNetworkReg.PortDevDescp.Body[aP0*KeyInDirCountMax + aP1].D8[i] = pCfgRxPkg->prm.data[i+4]; + } + if((pCfgRxPkg->prm.len - 4) < 32){ + fNetworkReg.PortDevDescp.Body[aP0*KeyInDirCountMax + aP1].D8[pCfgRxPkg->prm.len - 4] = 0; + } + if(0x35 == pCfgRxPkg->prm.data[3]){ + fNetworkReg.SaveDirectPadDescp(aCNum); + fNetworkReg.ReadDirectPadDescp(aCNum); + } + + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[1]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[2]; + pCfgTxPkg->prm.data[2] = 1; + }else{ + pCfgTxPkg->prm.head = TEST_UART_HEAD; + pCfgTxPkg->prm.cmd = pCfgRxPkg->prm.cmd; + pCfgTxPkg->prm.count = 0; + pCfgTxPkg->prm.len = 4; + pCfgTxPkg->prm.data[0] = pCfgRxPkg->prm.data[1]; + pCfgTxPkg->prm.data[1] = pCfgRxPkg->prm.data[2]; + pCfgTxPkg->prm.data[2] = 0; + } + } + + oBufProcess(); + break; + + case cfgCMD77: + //(void)LoadCfgFile(); + break; + + case cfgCMD7F://restart ctl + if(haveSaveCfgFlag){ + haveSaveCfgFlag = 0; + HAL_Delay(500); + UserRequestReset = 0x12345678; + } + while(1); + + default: + break; + } + } +} + +void TConfig::Task10Ms() +{ + static unsigned int tick = 0; + tick++; + if(tick > 2){ + tick = 0; + oLinkTXBuf(); + } +} + +void TConfig::Task1000Ms() +{ + ; +} + +void TConfig::OperationTask() +{ + iBufProcess(); +} diff --git a/MyCode/src/Config.h b/MyCode/src/Config.h new file mode 100644 index 0000000..4082f09 --- /dev/null +++ b/MyCode/src/Config.h @@ -0,0 +1,410 @@ +#ifndef CONFIG_H_ +#define CONFIG_H_ + +#include "ItemList.h" + +#define DevDispType 10 + +typedef union{ + unsigned char D8[88]; + unsigned int D32[22]; + struct{ + unsigned char head; + unsigned char cmd; + unsigned char count; + unsigned char len; + unsigned char data[84]; + }prm; +}TUartConfigInfo; + +typedef enum { + cfgCMD04 = 0x04, + cfgCMD07 = 0x07, + cfgCMD08 = 0x08, + cfgCMD09 = 0x09, +//loop + cfgCMD11 = 0x11, + cfgCMD12 = 0x12, + cfgCMD15 = 0x15, + cfgCMD17 = 0x17, +//bus + cfgCMD21 = 0x21, + cfgCMD22 = 0x22, + cfgCMD25 = 0x25, + cfgCMD27 = 0x27, +//dir + cfgCMD31 = 0x31, + cfgCMD32 = 0x32, + cfgCMD35 = 0x35, + cfgCMD37 = 0x37, +//area + cfgCMD41 = 0x41, + cfgCMD42 = 0x42, + cfgCMD45 = 0x45, + cfgCMD47 = 0x47, +//link + cfgCMD51 = 0x51, + cfgCMD52 = 0x52, + cfgCMD57 = 0x57, +//disp + cfgCMD61 = 0x61, + cfgCMD62 = 0x62, + cfgCMD65 = 0x65, + cfgCMD67 = 0x67, +//all desc + cfgCMD71 = 0x71, +//load cfg file + cfgCMD77 = 0x77, +//restart + cfgCMD7F = 0x7F, +}TcfgUartCmd; + +typedef union{ + unsigned char D8[56]; + unsigned int D32[14]; + struct{ + unsigned char ctlAddr; + unsigned char loopCount; + unsigned char busPanelCount; + unsigned char dirPanelCount; + + unsigned short areaCount; + unsigned short linkCount; + __UINT64_TYPE__ loopCfgTab; + unsigned int busCfgTab; + unsigned int dirCfgTab; + char desc[32]; + }cfg; +}TConfigCtlData; + +typedef union{ + unsigned char D8[48]; + unsigned int D32[12]; + struct{ + unsigned char id; + unsigned char devId; + unsigned short devType; + unsigned short assignType; + unsigned short devProperty; + unsigned short areaId; + unsigned short delayTime; + unsigned int devNum; + char desc[32]; + }cfg; +}TConfigLoopData; + +typedef union{ + unsigned char D8[24]; + unsigned int D32[6]; + struct{ + unsigned char id; + unsigned char devId; + unsigned short devType; + unsigned char ord; + unsigned char dispMode; + unsigned short areaId[3]; + unsigned int devNum[3]; + }cfg; +}TConfigLoopDispData; + +typedef union{ + unsigned char D8[44]; + unsigned int D32[11]; + struct{ + unsigned char id; + unsigned char keyId; + unsigned char keyCount; + unsigned char ctlMode; + unsigned short devType; + unsigned short areaId; + unsigned int serNum; + char desc[32]; + }cfg; +}TConfigBusPanelData; + +typedef union{ + unsigned char D8[44]; + unsigned int D32[11]; + struct{ + unsigned char id; + unsigned char keyId; + unsigned char isAble; + unsigned char errDetFlag; + unsigned char outProp; + unsigned char ctlDevType; + unsigned short areaId; + unsigned int serNum; + char desc[32]; + }cfg; +}TConfigDirPanelData; + +typedef union{ + unsigned char D8[56]; + unsigned int D32[14]; + struct{ + unsigned short id; + unsigned short rsv2; + unsigned int serNum; + char profile[16]; + char desc[32]; + }cfg; +}TConfigAreaData; + +typedef union{ + unsigned char D8[512]; + unsigned int D32[128]; + struct{ + char inEqn[16][16]; + char outEqn[16][16]; + }prm; +}TEquation; + +typedef union{ + unsigned char D8[524]; + unsigned int D32[131]; + struct{ + unsigned char inCount; + unsigned char outCount; + unsigned short inTab; + unsigned short outTab; + unsigned short id; + unsigned char isStop; + unsigned char isMask; + unsigned char isForceAutoExec; + unsigned char uartFlag; + TEquation eqn; + }cfg; +}TConfigLinkData; + +typedef union{ + unsigned char D8[24]; + unsigned int D32[6]; + struct{ + unsigned char head; + unsigned char cmd; + unsigned char count; + unsigned char len; + unsigned short id; + unsigned char isInput; + unsigned char ord; + char eqn[16]; + }formula; + struct{ + unsigned char head; + unsigned char cmd; + unsigned char count; + unsigned char len; + unsigned short id; + unsigned char endFlag; + unsigned char inCount; + unsigned char outCount; + unsigned char isStop; + unsigned char isMask; + unsigned char isForceAutoExec; + char rsv[12]; + }cfg; +}TUartCfgLinkData; + +typedef union{ + unsigned char D8[256]; + unsigned short D16[128]; + unsigned int D32[64]; +}TNorFlashPageData; + +typedef union{ + unsigned char D8[4]; + unsigned int D32; +}Tint; + +class TConfig{ + public: + unsigned int iLinkBufIndex; + unsigned int oLinkBufIndex; + + unsigned int usbConState; + unsigned int loadProgress; + + unsigned int uartRxFlag; + unsigned int usbCdcRxFlag; + TUartConfigInfo * pCfgTxPkg; + TUartConfigInfo * pCfgRxPkg; + unsigned char cfgRpyBuf[128]; + + unsigned int pSectorTmpAddr; + unsigned int fileSize; + unsigned int fileAnalysisErr; + unsigned int dataAnalysisErr; + + unsigned int loopDevCount[48]; + unsigned int loopDevDispCount[48]; + unsigned int busKeyCount[24]; + unsigned int dirKeyCount[24]; + unsigned int areaCount; + unsigned int linkCount; + + TConfigCtlData ctlPrm; + TConfigLoopData loopPrm; + TConfigLoopDispData loopDispPrm; + TConfigBusPanelData busPrm; + TConfigDirPanelData dirPrm; + TConfigAreaData areaPrm; + TConfigLinkData linkPrm; + + unsigned char loopCfgDevDispExistTab[48]; + unsigned char loopCfgDevTab[256]; + unsigned char busCfgKeyTab[128]; + unsigned char dirCfgKeyTab[8]; + unsigned char areaCfgTab[1024]; + unsigned char linkCfgTab[2048]; + + TNorFlashPageData nFlashPageData; + unsigned int norFlashAddr; + + //class TItemList *IList; + class TItemList ItemList; + + public: + TConfig(){}; + void Init(); + + void iLinkTXBuf(unsigned char * pData); + void oLinkTXBuf(); + + void WaitChipIdle(unsigned int aCnt); + + void CfgPrmInit(); + + void DelayMs(unsigned int aMs); + + unsigned short Crc16Data(unsigned char* apData,unsigned int aLen); + unsigned int CheckCrc16(unsigned char* apData,unsigned int aLen); + + unsigned int AsiiToData(unsigned char * apResult, char* apData,unsigned int aLen); + unsigned int AsiiToData(unsigned short * apResult, char* apData,unsigned int aLen); + unsigned int AsiiToData(unsigned int * apResult, char* apData,unsigned int aLen); + unsigned int AsiiToData(__UINT64_TYPE__ * apResult, char* apData,unsigned int aLen); + void GetDesc16(char * apSetData, char * apGetData); + void GetDesc16(char * apSetData, unsigned char * apGetData); + void GetDesc32(char * apSetData, char * apGetData); + void GetDesc32(char * apSetData, unsigned char * apGetData); + + unsigned int GetUsbState(void); + int ReadFile(char* apName); + void GetFileLine(); + void GetFileLine(unsigned int * apItemCount); + + void GetCtlCfgPrm(); + + void GetLoopCfgDevPrm(unsigned int aLineNum); + void GetBusCfgKeyPrm(unsigned int aLineNum); + void GetDirCfgKeyPrm(unsigned int aLineNum); + void GetAreaCfgPrm(unsigned int aLineNum); + void GetLinkCfgPrm(unsigned int aLineNum); + void GetLoopCfgDispPrm(unsigned int aLineNum); + + int LoadCfgFile(); + + void WriteProjectName(); + + void WriteLoopCfgDevTabTypeDisp(); + void WriteLoopCfgAllDisp(); + void WriteLoopCfgOneDisp(unsigned int aLoopId, unsigned int aDispId); + void WriteLoopDevUserCodeAssignType(); + void WriteLoopOneDevUserCodeAssignType(unsigned int aLoopId, unsigned int aDevId); + void WriteOneLoopDevUserCodeAssignType(unsigned int aLoopId); + void WriteLoopDevArea(); + void WriteLoopOneDevArea(unsigned int aLoopId, unsigned int aDevId); + void WriteOneLoopDevArea(unsigned int aLoopId); + void WriteLoopDevDescp(); + void WriteLoopOneDevDescp(unsigned int aLoopId, unsigned int aDevId); + void WriteOneLoopDevDescp(unsigned int aLoopId); + + void WriteBusCfgKeyNormal(); + void WriteBusOneKeyNormal(unsigned int aBusId, unsigned int aKeyId); + void WriteOneBusKeyNormal(unsigned int aBusId); + + void WriteDirCfgKeyNormal(); + void WriteDirOneKeyNormal(unsigned int aDirId, unsigned int aKeyId); + void WriteOneDirKeyNormal(unsigned int aDirId); + void WriteDirKeyUserCodeAssignType(); + void WriteDirOneKeyUserCodeAssignType(unsigned int aDirId, unsigned int aKeyId); + void WriteOneDirKeyUserCodeAssignType(unsigned int aDirId); + void WriteDirKeyArea(); + void WriteDirOneKeyArea(unsigned int aDirId, unsigned int aKeyId); + void WriteOneDirKeyArea(unsigned int aDirId); + void WriteDirCfgDescp(); + void WriteDirOneDescp(unsigned int aDirId, unsigned int aKeyId); + void WriteOneDirDescp(unsigned int aDirId); + + void WriteAreaCfg(); + + unsigned int WriteLinkPrmToNorFlash(TConfigLinkData * pLinkPrm); + void Erase4LinkIndex(unsigned int aInx); + void Erase64LinkIndex(unsigned int aInx); + void Write1LinkIndex(unsigned int aInx); + void Write4LinkIndex(unsigned int aInx); + void WriteAllLinkCfgToNorFlash(); + void WriteOneLinkCfgToNorFlash(unsigned int aLinkId); + void Clear4Index(unsigned int aGroup); + + void WriteAllUsbCfg(); + void WriteAllUartCfg(); + + //---------------------write to sdram--------------------------------------------------------- + void WriteCtlPrmToSdram(TConfigCtlData * pCtlPrm); + + unsigned int WriteLoopDevPrmToSdram(TConfigLoopData * pLoopPrm); + unsigned int WriteLoopDevDispPrmToSdram(TConfigLoopDispData * pLoopDispPrm); + void ClearLoopCfgDevTabInSdram(unsigned int aId); + void WriteLoopCfgDevTabToSdram(unsigned int aId, unsigned char * pLoopCfgDevTab); + void WriteLoopCfgOneDevInTabToSdram(unsigned int aId, unsigned int aDevId); + + unsigned int WriteBusKeyPrmToSdram(TConfigBusPanelData * pBusPrm); + void ClearBusCfgKeyTabToSdram(unsigned int aId); + void WriteBusCfgKeyTabToSdram(unsigned int aId, unsigned char * pBusCfgKeyTab); + void WriteBusCfgOneKeyInTabToSdram(unsigned int aId, unsigned int aKeyId); + + unsigned int WriteDirKeyPrmToSdram(TConfigDirPanelData * pDirPrm); + void ClearDirCfgKeyTabToSdram(unsigned int aId); + void WriteDirCfgKeyTabToSdram(unsigned int aId, unsigned char * pDirCfgKeyTab); + void WriteDirCfgOneKeyInTabToSdram(unsigned int aId, unsigned int aKeyId); + + unsigned int WriteAreaPrmToSdram(TConfigAreaData * pAreaPrm); + void WriteAreaCfgTabToSdram(unsigned char * pAreaCfgTab); + + void ClearOneLinkCfgToSdram(unsigned int aId); + unsigned int WriteLinkCfgToSdram(TConfigLinkData * pLinkPrm); + + //---------------------read from sdram--------------------------------------------------------- + unsigned int ReadCtlPrmFromSdram(TConfigCtlData * pCtlPrm); + unsigned int ReadLoopDevPrmFromSdram(unsigned char aId, unsigned char aDevId, TConfigLoopData * pLoopPrm); + void ReadLoopCfgDevTabFromSdram(unsigned int ord, unsigned char * pLoopCfgDevTab); + unsigned int ReadBusKeyPrmFromSdram(unsigned char aId, unsigned char aKeyId, TConfigBusPanelData * pBusPrm); + void ReadBusCfgKeyTabFromSdram(unsigned int ord, unsigned char * pBusCfgKeyTab); + unsigned int ReadDirKeyPrmFromSdram(unsigned char aId, unsigned char aKeyId, TConfigDirPanelData * pDirPrm); + void ReadDirCfgKeyTabFromSdram(unsigned int ord, unsigned char * pDirCfgKeyTab); + + unsigned int ReadAreaPrmFromSdram(unsigned int aId, TConfigAreaData * pAreaPrm); + + //----------------------rpy------------------------------------------------------------- + void rpyNoData(); + void rpyData(unsigned char * pData, unsigned int len); + void rpyCmd09(); + void rpyCmd12(); + void rpyCmd22(); + void rpyCmd32(); + void rpyCmd42(); + void rpyCmd52(); + void rpyCmd62(); + + //------------------------------------------------------------------------------------------ + void iBufProcess(); + void oBufProcess(); + + void Task10Ms(); + void Task1000Ms(); + + void OperationTask(); +}; + +#endif diff --git a/MyCode/src/ControlCenter.cpp b/MyCode/src/ControlCenter.cpp new file mode 100644 index 0000000..71983e2 --- /dev/null +++ b/MyCode/src/ControlCenter.cpp @@ -0,0 +1,3697 @@ +#include "ControlCenter.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "fdcan_task.h" + #include "task.h" + #include "HW_config.h" +} + +enum{ + ieStateNull = 0, + ieStateActive = 0xAA, +}; + +void TControlCenter::Init() +{ + ieMsgFire.WriteIndex = 0; + ieMsgFire.ReflashIndex = 0; + ieMsgLinkage.ReflashIndex = 0; + ieMsgSv.ReflashIndex = 0; + ieMsgFault.ReflashIndex = 0; + + SysFreeTick1Ms =0; + + MsgReset(); + + IsSendResetToPad =0; + IsSendSelfCheckToPad = 0; + + PassWordII.Ava = 0; + PassWordIII.Ava = 0; + + PsBatUpDateTick = 0; +} + +void TControlCenter::MsgReset() +{ + unsigned int i; + unsigned int AddrSd; + + hydrantKpFbHasSend = 0; + + ieGot = 0; + ieIndexMsgFault =0; + ieIndexMsgStart =0; + ieIndexMsgFeedBack =0; + + ieMsgFire.WriteIndex = 0; + + ieMsgFire.Count = 0; + ieMsgFire.ActualCount =0; + ieMsgFault.Count = 0; + ieMsgFault.VaCount = 0; + ieMsgSv.Count = 0; + ieMsgLinkage.SatrtHasBennActive = 0; + ieMsgLinkage.Count = 0; + ieMsgLinkage.FbCount = 0; + ieMsgLinkage.PumpFbCount =0; + ieMsgLinkage.PumpFbLocalCount =0; + ieMsgLinkage.MissingCount = 0; + ieMsgLinkage.StartCount = 0; + ieMsgLinkage.VaCount = 0; + ieMsgLinkage.VaCountOld = 0; + ieMsgLinkage.BroadcastCount =0; + ieMsgLinkage.BroadcastCountOld =0; + ieMsgLinkage.IsBroadcastAndVa =0; + ieMsgLinkage.HydrantPadCount =0; + ieMsgLinkage.HydrantPadCountOld =0; + ieMsgLinkage.HydrantPadNewActive = 0; + ieMsgLinkage.DelayCount = 0; + ieMsgLinkage.DelayCountOld = 0; + ieMsgLinkage.StopCount = 0; + + + for(i=0; i= (ieMSG_FIRE_MAX_COUNT)){ + ieMsgFire.WriteIndex = ieMSG_FIRE_MAX_COUNT; + aWriteIndex = ieMSG_FIRE_MAX_COUNT -1; + ieMsgFire.isMore = 1; + for(i=1; i<(ieMSG_FIRE_MAX_COUNT-1); i++){ + z = i+1; + FireGetViaPath(i+1); + FireMsgCopyOne(i); + } + }else{ + ieMsgFire.isMore = 0; + aWriteIndex = ieMsgFire.WriteIndex; + ieMsgFire.WriteIndex++; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.Data0 = LinkInputTypeFire; + if(ieMsgFire.Count == 0)MsgReadTmp.Splite.Data1 = 1; + else MsgReadTmp.Splite.Data1 = 0; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.State = ieStateActive; + MsgReadTmp.Splite.P2 =0; + FireMsgCopyOne(aWriteIndex); + + const unsigned int tInx = FiredUserCode.Count; + FiredUserCode.uCode[tInx] = aIm.Splite.UserCode; + FiredUserCode.AreaNum[tInx] = aIm.Splite.AreaNum; + FiredUserCode.dType[tInx] = aIm.Splite.dType; + FiredUserCode.AssignType[tInx] = 0; + FiredUserCode.eType[tInx] = LinkInputTypeFire; + if( FiredUserCode.Count < (dLINK_INPUT_MAX_COUNT -2) )FiredUserCode.Count++; + + ieMsgFire.Count = ieMsgFire.WriteIndex; + if(MsgReadTmp.Splite.Data0 != TControlCenter::LinkInputTypeFireSimulate){ + ieMsgFire.ActualCount++; + } + ieMsgFire.ReflashIndex++; + ieMsgFire.Lock = 0; + AlarmSoundWhat = 0; + + IsMuteFire = 0; + IsMute = 0; + + + /*if(FireVaTrenOned == 0){ + //Turn On Va + FireVaTrenOned =1; + FireTurnOnVa(); + }*/ + + ieGot = 1; +} + +int TControlCenter::iePushOneMsgFireSimulate(TRecordCommon aIm, unsigned int auC) +{ + int i,z,y, isMore; + int x, aWriteIndex; + unsigned char aCn, aP0, aP1, aAssignType; + TDMix mVal; + + aCn = aIm.Splite.PCtlNum; + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + aAssignType = 0; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aCn == MainCtl.fData.Split.MyNum){ + aAssignType = Port[aP0].AssignType[aP1]; + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return 0; + }else{ + //Port[aP0].StateTable[aP1] |= dEpStateBitFire; + } + }else{ + aCn--; + if( (aCn < dNETWORK_MACHINE_COUNT) && (aP0 < dPORT_MAX_COUNT) ){ + if(aP1 >= dEP_MAX_COUNT_PER_PORT)return 0; + //mVal.D32 = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + //mVal.D8[0] |= dEpStateBitFire; + //mVal.D8[1] = aIm.Splite.dType; + + //SetNetworkEpData(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, mVal.D16[0]); + } + } + }else{ + return 0; + } + ieMsgFire.RequestRead =0; + ieMsgFire.Lock = 1; + + if(ieMsgFire.WriteIndex >= (ieMSG_FIRE_MAX_COUNT)){ + ieMsgFire.WriteIndex = ieMSG_FIRE_MAX_COUNT; + aWriteIndex = ieMSG_FIRE_MAX_COUNT -1; + ieMsgFire.isMore = 1; + for(i=1; i<(ieMSG_FIRE_MAX_COUNT-1); i++){ + z = i+1; + FireGetViaPath(i+1); + FireMsgCopyOne(i); + } + }else{ + ieMsgFire.isMore = 0; + aWriteIndex = ieMsgFire.WriteIndex; + ieMsgFire.WriteIndex++; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.Data0 = LinkInputTypeFireSimulate; + if(ieMsgFire.Count == 0)MsgReadTmp.Splite.Data1 = 1; + else MsgReadTmp.Splite.Data1 = 0; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.State = ieStateActive; + MsgReadTmp.Splite.P2 =0; + FireMsgCopyOne(aWriteIndex); + + const unsigned int tInx = FiredUserCode.Count; + FiredUserCode.uCode[tInx] = aIm.Splite.UserCode; + FiredUserCode.AreaNum[tInx] = aIm.Splite.AreaNum; + FiredUserCode.dType[tInx] = aIm.Splite.dType; + FiredUserCode.AssignType[tInx] = 0; + FiredUserCode.eType[tInx] = LinkInputTypeFireSimulate; + if(FiredUserCode.Count < (dLINK_INPUT_MAX_COUNT -2))FiredUserCode.Count++; + + ieMsgFire.Count = ieMsgFire.WriteIndex; + ieMsgFire.ReflashIndex++; + ieMsgFire.Lock = 0; + + AlarmSoundWhat = 0; + + IsMuteFire = 0; + IsMute = 0; + + + /*if(FireVaTrenOned == 0){ + //Turn On Va + FireVaTrenOned =1; + FireTurnOnVa(); + }*/ + + ieGot = 1; + + return 1; +} + +void TControlCenter::LinkageGetViaPath(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgLinkage + (aIndex * 24); + MsgReadTmp.D32[0] = *(volatile unsigned int*)(AddrSd); + MsgReadTmp.D32[1] = *(volatile unsigned int*)(AddrSd + 4); + MsgReadTmp.D32[2] = *(volatile unsigned int*)(AddrSd + 8); + MsgReadTmp.D32[3] = *(volatile unsigned int*)(AddrSd + 12); + MsgReadTmp.D32[4] = *(volatile unsigned int*)(AddrSd + 16); + MsgReadTmp.D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::LinkageMsgClearOne(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgLinkage + (aIndex * 24); + *(volatile unsigned int*)(AddrSd + 0) = 0; + *(volatile unsigned int*)(AddrSd + 4) = 0; + *(volatile unsigned int*)(AddrSd + 8) = 0; + *(volatile unsigned int*)(AddrSd + 12) = 0; + *(volatile unsigned int*)(AddrSd + 16) = 0; + *(volatile unsigned int*)(AddrSd + 20) = 0; +} + +void TControlCenter::LinkageMsgCopyOne(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgLinkage + (aIndex * 24); + *(volatile unsigned int*)(AddrSd + 0) = MsgReadTmp.D32[0]; + *(volatile unsigned int*)(AddrSd + 4) = MsgReadTmp.D32[1]; + *(volatile unsigned int*)(AddrSd + 8) = MsgReadTmp.D32[2]; + *(volatile unsigned int*)(AddrSd + 12) = MsgReadTmp.D32[3]; + *(volatile unsigned int*)(AddrSd + 16) = MsgReadTmp.D32[4]; + *(volatile unsigned int*)(AddrSd + 20) = MsgReadTmp.D32[5]; +} + +void TControlCenter::LinkageMsgExtGet(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgLinkage + (aIndex * 24); + MsgExtGet.D32[0] = *(volatile unsigned int*)(AddrSd + 0); + MsgExtGet.D32[1] = *(volatile unsigned int*)(AddrSd + 4); + MsgExtGet.D32[2] = *(volatile unsigned int*)(AddrSd + 8); + MsgExtGet.D32[3] = *(volatile unsigned int*)(AddrSd + 12); + MsgExtGet.D32[4] = *(volatile unsigned int*)(AddrSd + 16); + MsgExtGet.D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::SvGetViaPath(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgSv + (aIndex * 24); + MsgReadTmp.D32[0] = *(volatile unsigned int*)(AddrSd); + MsgReadTmp.D32[1] = *(volatile unsigned int*)(AddrSd + 4); + MsgReadTmp.D32[2] = *(volatile unsigned int*)(AddrSd + 8); + MsgReadTmp.D32[3] = *(volatile unsigned int*)(AddrSd + 12); + MsgReadTmp.D32[4] = *(volatile unsigned int*)(AddrSd + 16); + MsgReadTmp.D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::SvMsgClearOne(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgSv + (aIndex * 24); + *(volatile unsigned int*)(AddrSd + 0) = 0; + *(volatile unsigned int*)(AddrSd + 4) = 0; + *(volatile unsigned int*)(AddrSd + 8) = 0; + *(volatile unsigned int*)(AddrSd + 12) = 0; + *(volatile unsigned int*)(AddrSd + 16) = 0; + *(volatile unsigned int*)(AddrSd + 20) = 0; +} + +void TControlCenter::SvMsgCopyOne(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgSv + (aIndex * 24); + *(volatile unsigned int*)(AddrSd + 0) = MsgReadTmp.D32[0]; + *(volatile unsigned int*)(AddrSd + 4) = MsgReadTmp.D32[1]; + *(volatile unsigned int*)(AddrSd + 8) = MsgReadTmp.D32[2]; + *(volatile unsigned int*)(AddrSd + 12) = MsgReadTmp.D32[3]; + *(volatile unsigned int*)(AddrSd + 16) = MsgReadTmp.D32[4]; + *(volatile unsigned int*)(AddrSd + 20) = MsgReadTmp.D32[5]; +} + +void TControlCenter::SvMsgExtGet(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgSv + (aIndex * 24); + MsgExtGet.D32[0] = *(volatile unsigned int*)(AddrSd + 0); + MsgExtGet.D32[1] = *(volatile unsigned int*)(AddrSd + 4); + MsgExtGet.D32[2] = *(volatile unsigned int*)(AddrSd + 8); + MsgExtGet.D32[3] = *(volatile unsigned int*)(AddrSd + 12); + MsgExtGet.D32[4] = *(volatile unsigned int*)(AddrSd + 16); + MsgExtGet.D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::FaultGetViaPath(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgFault + (aIndex * 24); + MsgReadTmp.D32[0] = *(volatile unsigned int*)(AddrSd); + MsgReadTmp.D32[1] = *(volatile unsigned int*)(AddrSd + 4); + MsgReadTmp.D32[2] = *(volatile unsigned int*)(AddrSd + 8); + MsgReadTmp.D32[3] = *(volatile unsigned int*)(AddrSd + 12); + MsgReadTmp.D32[4] = *(volatile unsigned int*)(AddrSd + 16); + MsgReadTmp.D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::FaultMsgClearOne(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgFault + (aIndex * 24); + *(volatile unsigned int*)(AddrSd + 0) = 0; + *(volatile unsigned int*)(AddrSd + 4) = 0; + *(volatile unsigned int*)(AddrSd + 8) = 0; + *(volatile unsigned int*)(AddrSd + 12) = 0; + *(volatile unsigned int*)(AddrSd + 16) = 0; + *(volatile unsigned int*)(AddrSd + 20) = 0; +} + +void TControlCenter::FaultMsgCopyOne(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgFault + (aIndex * 24); + *(volatile unsigned int*)(AddrSd + 0) = MsgReadTmp.D32[0]; + *(volatile unsigned int*)(AddrSd + 4) = MsgReadTmp.D32[1]; + *(volatile unsigned int*)(AddrSd + 8) = MsgReadTmp.D32[2]; + *(volatile unsigned int*)(AddrSd + 12) = MsgReadTmp.D32[3]; + *(volatile unsigned int*)(AddrSd + 16) = MsgReadTmp.D32[4]; + *(volatile unsigned int*)(AddrSd + 20) = MsgReadTmp.D32[5]; +} + +void TControlCenter::FaultMsgExtGet(unsigned int aIndex) +{ + volatile unsigned int AddrSd = dAddrSdRam_MsgFault + (aIndex * 24); + MsgExtGet.D32[0] = *(volatile unsigned int*)(AddrSd + 0); + MsgExtGet.D32[1] = *(volatile unsigned int*)(AddrSd + 4); + MsgExtGet.D32[2] = *(volatile unsigned int*)(AddrSd + 8); + MsgExtGet.D32[3] = *(volatile unsigned int*)(AddrSd + 12); + MsgExtGet.D32[4] = *(volatile unsigned int*)(AddrSd + 16); + MsgExtGet.D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::iePushOneMsgLinkageStart(TRecordCommon aIm) +{ + unsigned char aCn, aP0, aP1, EpSta, aAssignType; + int i,Cnt, FirstNullIndex, WritePst; + int aStartCount, aFbCount, aMsCount, aVaCount, aHP; + int aDelayCount, aStopCount, aBroadcastCount; + + aCn = aIm.Splite.PCtlNum; + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + if( (aIm.Splite.P0) && (aIm.Splite.P0 <= dPORT_MAX_COUNT )){ + if(aP1 >= dEP_MAX_COUNT_PER_PORT)return; + if(aCn == MainCtl.fData.Split.MyNum){ + aAssignType = Port[aP0].AssignType[aP1]; + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A))){ + Port[aP0].DelayTick[aP1] = 0; + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] |= dEpStateBitStart; + } + } + }else{ + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A))){ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta |= dEpStateBitStart; + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + }else + if( (aIm.Splite.P0 >= dADDR_DIRECTPAD_START) && (aIm.Splite.P0 <= dADDR_DIRECTPAD_END )){ + if(aCn == MainCtl.fData.Split.MyNum){ + if(aP1 >= dDIRECTCTL_KEY_MAX_COUNT)return; + aP0 = aIm.Splite.P0 -dADDR_DIRECTPAD_START; + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A)))DirectCtlBoard[aP0].DelayTick[aP1] = 0; + } + }else{ + return; + } + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aStartCount = 0; + aFbCount = 0; + aMsCount = 0; + aVaCount = 0; + aBroadcastCount =0; + aHP = 0; + aDelayCount = 0; + aStopCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( (MsgReadTmp.D32[2] == aIm.D32[2]) && ( etLinkageStart == MsgReadTmp.Splite.mType) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageStart){ + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)){ + aDelayCount++; + }else + if(MsgReadTmp.Splite.Data0 == static_cast(0x09)){ + aStopCount++; + }else{ + aStartCount++; + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + } + }else + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_LINKAGE_MAX_COUNT){ + for(i=0; i< (ieMSG_LINKAGE_MAX_COUNT -1); i++){ + LinkageGetViaPath(i+1); + LinkageMsgCopyOne(i); + } + WritePst = ieMSG_LINKAGE_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.Data0 = aIm.Splite.iByte0; + MsgReadTmp.Splite.Data1 = 0; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.State = ieStateActive; + LinkageMsgCopyOne(WritePst); + + ieMsgLinkage.Count = WritePst +1; + + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)) + aDelayCount++; + else if(MsgReadTmp.Splite.Data0 == static_cast(0x09)) + aStopCount++; + else + aStartCount++; + + ieMsgLinkage.StartCount = aStartCount; + ieMsgLinkage.DelayCount = aDelayCount; + ieMsgLinkage.StopCount = aStopCount; + if(ieMsgLinkage.StartCount > 0)ieMsgLinkage.SatrtHasBennActive = 1; + + ieMsgLinkage.FbCount = aFbCount; + ieMsgLinkage.MissingCount = aMsCount; + if( (MsgReadTmp.Splite.Data0 != static_cast(0x09)) && ((MsgReadTmp.Splite.Data0 != static_cast(0x0A))) ){ + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + ieMsgLinkage.HydrantPadNewActive =1; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + } + + ieMsgLinkage.VaCount = aVaCount; + ieMsgLinkage.BroadcastCount = aBroadcastCount; + ieMsgLinkage.HydrantPadCount = aHP; + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + BroadcastAlternatingUpdate(); + + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + if( (MsgReadTmp.Splite.Data0 != static_cast(0x0A)) && (MsgReadTmp.Splite.Data0 != static_cast(0x09)) ){ + const unsigned int tInx = FiredUserCode.Count; + FiredUserCode.uCode[tInx] = aIm.Splite.UserCode; + FiredUserCode.AreaNum[tInx] = aIm.Splite.AreaNum; + FiredUserCode.dType[tInx] = aIm.Splite.dType; + FiredUserCode.AssignType[tInx] = 0; + FiredUserCode.eType[tInx] = LinkInputTypeHydrant; + if(FiredUserCode.Count < (dLINK_INPUT_MAX_COUNT -2))FiredUserCode.Count++; + } + } + + if(AlarmSoundWhat > 1)AlarmSoundWhat = 1; + + IsMuteLnk = 0; + IsMute = 0; + + ieGot = 1; +} + +int TControlCenter::iePushOneMsgLinkageStartSimulate(TRecordCommon aIm) +{ + unsigned char aCn, aP0, aP1, EpSta, aAssignType; + int i,Cnt, FirstNullIndex, WritePst; + int aStartCount, aFbCount, aMsCount, aVaCount, aHP; + int aDelayCount, aStopCount, aBroadcastCount; + + aCn = aIm.Splite.PCtlNum; + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + + for(i=0; i= dEP_MAX_COUNT_PER_PORT)return 0; + if(aCn == MainCtl.fData.Split.MyNum){ + aAssignType = Port[aP0].AssignType[aP1]; + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A))){ + if(Port[aP0].DelayToDoEventType[aP1])Port[aP0].DelayTick[aP1] = 0; + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return 0; + }else{ + //Port[aP0].StateTable[aP1] |= dEpStateBitStart; + } + } + }else{ + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A))){ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta |= dEpStateBitStart; + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + }else + if( (aIm.Splite.P0 >= dADDR_DIRECTPAD_START) && (aIm.Splite.P0 <= dADDR_DIRECTPAD_END )){ + if(aCn == MainCtl.fData.Split.MyNum){ + if(aP1 >= dDIRECTCTL_KEY_MAX_COUNT)return 0; + aP0 = aIm.Splite.P0 -dADDR_DIRECTPAD_START; + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A))){ + if(DirectCtlBoard[aP0].DelayToDoEventType[aP1]){ + DirectCtlBoard[aP0].DelayTick[aP1] = 0; + } + } + } + }else{ + return 0; + } + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aStartCount = 0; + aFbCount = 0; + aMsCount = 0; + aVaCount = 0; + aBroadcastCount =0; + aHP = 0; + aDelayCount = 0; + aStopCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( (MsgReadTmp.D32[2] == aIm.D32[2]) && ( etLinkageStart == MsgReadTmp.Splite.mType) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageStart){ + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)){ + aDelayCount++; + }else + if(MsgReadTmp.Splite.Data0 == static_cast(0x09)){ + aStopCount++; + }else{ + aStartCount++; + ///if(MsgReadTmp.Splite.Data1 == StartTypeSimulate){ + + ///}else{ + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + ///} + } + }else + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_LINKAGE_MAX_COUNT){ + for(i=0; i< (ieMSG_LINKAGE_MAX_COUNT -1); i++){ + LinkageGetViaPath(i+1); + LinkageMsgCopyOne(i); + } + WritePst = ieMSG_LINKAGE_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.Data1 = StartTypeSimulate; + MsgReadTmp.Splite.Data0 = aIm.Splite.iByte0; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.State = ieStateActive; + LinkageMsgCopyOne(WritePst); + + ieMsgLinkage.Count = WritePst +1; + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)) + aDelayCount ++; + else if(MsgReadTmp.Splite.Data0 == static_cast(0x09)) + aStopCount++; + else + aStartCount++; + + ieMsgLinkage.StartCount = aStartCount; + ieMsgLinkage.DelayCount = aDelayCount; + ieMsgLinkage.StopCount = aStopCount; + if(ieMsgLinkage.StartCount > 0)ieMsgLinkage.SatrtHasBennActive = 1; + + ieMsgLinkage.FbCount = aFbCount; + ieMsgLinkage.MissingCount = aMsCount; + if( (MsgReadTmp.Splite.Data0 != static_cast(0x09)) && ((MsgReadTmp.Splite.Data0 != static_cast(0x0A))) ){ + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + ieMsgLinkage.HydrantPadNewActive =1; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + } + + ieMsgLinkage.VaCount = aVaCount; + ieMsgLinkage.BroadcastCount = aBroadcastCount; + ieMsgLinkage.HydrantPadCount = aHP; + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + BroadcastAlternatingUpdate(); + + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + if( (MsgReadTmp.Splite.Data0 != static_cast(0x0A)) && (MsgReadTmp.Splite.Data0 != static_cast(0x09)) ){ + const unsigned int tInx = FiredUserCode.Count; + FiredUserCode.uCode[tInx] = aIm.Splite.UserCode; + FiredUserCode.AreaNum[tInx] = aIm.Splite.AreaNum; + FiredUserCode.dType[tInx] = aIm.Splite.dType; + FiredUserCode.AssignType[tInx] = 0; + FiredUserCode.eType[tInx] = LinkInputTypeHydrantSimulate; + if(FiredUserCode.Count < (dLINK_INPUT_MAX_COUNT -2))FiredUserCode.Count++; + } + } + + if(AlarmSoundWhat > 1)AlarmSoundWhat = 1; + + IsMuteLnk = 0; + IsMute = 0; + + ieGot = 1; + + return 1; +} + +void TControlCenter::ieManualPushOneMsgLinkageStart(TRecordCommon aIm) +{ + unsigned char aCn, aP0, aP1, EpSta, aAssignType; + int i,Cnt, FirstNullIndex, WritePst; + int aStartCount, aFbCount, aMsCount, aVaCount, aHP; + int aDelayCount, aStopCount, aBroadcastCount; + + aCn = aIm.Splite.PCtlNum; + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + aAssignType = 0; + if( (aIm.Splite.P0) && (aIm.Splite.P0 <= dPORT_MAX_COUNT )){ + if(aP1 >= dEP_MAX_COUNT_PER_PORT)return; + if(aCn == MainCtl.fData.Split.MyNum){ + aAssignType = Port[aP0].AssignType[aP1]; + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A))){ + Port[aP0].DelayTick[aP1] = 0; + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] |= dEpStateBitStart; + } + } + }else{ + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A))){ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta |= dEpStateBitStart; + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + }else + if( (aIm.Splite.P0 >= dADDR_DIRECTPAD_START) && (aIm.Splite.P0 <= dADDR_DIRECTPAD_END )){ + if(aCn == MainCtl.fData.Split.MyNum){ + if(aP1 >= dDIRECTCTL_KEY_MAX_COUNT)return; + aP0 = aIm.Splite.P0 -dADDR_DIRECTPAD_START; + if( (aIm.Splite.iByte0 != static_cast(0x09)) && (aIm.Splite.iByte0 != static_cast(0x0A)))DirectCtlBoard[aP0].DelayTick[aP1] = 0; + } + }else{ + return; + } + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aStartCount = 0; + aFbCount = 0; + aMsCount = 0; + aVaCount = 0; + aBroadcastCount =0; + aHP =0; + aDelayCount = 0; + aStopCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( (MsgReadTmp.D32[2] == aIm.D32[2]) && ( etLinkageStart == MsgReadTmp.Splite.mType) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageStart){ + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)){ + aDelayCount++; + }else + if(MsgReadTmp.Splite.Data0 == static_cast(0x09)){ + aStopCount++; + }else{ + aStartCount++; + //if(MsgReadTmp.Splite.Data1 == StartTypeSimulate){ + + //}else{ + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + //} + } + }else + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_LINKAGE_MAX_COUNT){ + for(i=0; i< (ieMSG_LINKAGE_MAX_COUNT -1); i++){ + LinkageGetViaPath(i+1); + LinkageMsgCopyOne(i); + } + WritePst = ieMSG_LINKAGE_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.Data0 = aIm.Splite.iByte0; + MsgReadTmp.Splite.Data1 = 0; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.State = ieStateActive; + LinkageMsgCopyOne(WritePst); + + ieMsgLinkage.Count = WritePst +1; + + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)) + aDelayCount++; + else if(MsgReadTmp.Splite.Data0 == static_cast(0x09)) + aStopCount++; + else + aStartCount++; + + ieMsgLinkage.StartCount = aStartCount; + ieMsgLinkage.DelayCount = aDelayCount; + ieMsgLinkage.StopCount = aStopCount; + if(ieMsgLinkage.StartCount > 0)ieMsgLinkage.SatrtHasBennActive = 1; + + ieMsgLinkage.FbCount = aFbCount; + ieMsgLinkage.MissingCount = aMsCount; + if( (MsgReadTmp.Splite.Data0 != static_cast(0x09)) && (MsgReadTmp.Splite.Data0 != static_cast(0x0A)) ){ + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + ieMsgLinkage.HydrantPadNewActive =1; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + } + ieMsgLinkage.VaCount = aVaCount; + ieMsgLinkage.BroadcastCount = aBroadcastCount; + ieMsgLinkage.HydrantPadCount = aHP; + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + BroadcastAlternatingUpdate(); + + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + if( (MsgReadTmp.Splite.Data0 != static_cast(0x09)) && (MsgReadTmp.Splite.Data0 != static_cast(0x0A)) ){ + const unsigned int tInx = FiredUserCode.Count; + FiredUserCode.uCode[tInx] = aIm.Splite.UserCode; + FiredUserCode.AreaNum[tInx] = aIm.Splite.AreaNum; + FiredUserCode.dType[tInx] = aIm.Splite.dType; + FiredUserCode.AssignType[tInx] = 0; + FiredUserCode.eType[tInx] = LinkInputTypeSv; + + if(FiredUserCode.Count < (dLINK_INPUT_MAX_COUNT -2))FiredUserCode.Count++; + } + } + + if(AlarmSoundWhat > 1)AlarmSoundWhat = 1; + + IsMuteLnk = 0; + IsMute = 0; + + ieGot = 1; +} + +void TControlCenter::ieMsgLinkageStartDelayUpdate(unsigned int aFullPath, unsigned char aNewTime) +{ + /*unsigned char aP0, aP1, EpSta; + int i,Cnt, FirstNullIndex, WritePst; + int aStartCount, aFbCount, aMsCount, aVaCount, aHP; + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + + for(i=0; i0 ) && (aIm.Splite.P0 <= dPORT_MAX_COUNT) ){ + if(aP1 >= dEP_MAX_COUNT_PER_PORT)return; + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + Port[aP0].DelayTick[aP1] = 0; + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] &= ~(dEpStateBitStart); + } + }else{ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta &= ~(dEpStateBitStart); + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + }else + if( (aIm.Splite.P0 >= dADDR_DIRECTPAD_START) && (aIm.Splite.P0 <= dADDR_DIRECTPAD_END )){ + if(aP1 >= dDIRECTCTL_KEY_MAX_COUNT)return; + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = aIm.Splite.P0 -dADDR_DIRECTPAD_START; + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + DirectCtlBoard[aP0].DelayTick[aP1] = 0; + } + } + } + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + Cnt = 0; + i =0; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aStartCount = 0; + aFbCount = 0; + aMsCount = 0; + aVaCount = 0; + aBroadcastCount =0; + aHP =0; + aDelayCount = 0; + aStopCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( ( MsgReadTmp.D32[2] == aIm.D32[2]) && ( etLinkageStart == MsgReadTmp.Splite.mType ) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageStart){ + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)){ + aDelayCount++; + }else + if(MsgReadTmp.Splite.Data0 == static_cast(0x09)){ + aStopCount++; + }else{ + aStartCount++; + //if(MsgReadTmp.Splite.Data1 == StartTypeSimulate){ + + //}else{ + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + //} + } + }else + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + + ieMsgLinkage.Count = Cnt; + ieMsgLinkage.StartCount = aStartCount; + ieMsgLinkage.FbCount = aFbCount; + ieMsgLinkage.MissingCount = aMsCount; + ieMsgLinkage.VaCount = aVaCount; + ieMsgLinkage.BroadcastCount = aBroadcastCount; + ieMsgLinkage.HydrantPadCount = aHP; + ieMsgLinkage.DelayCount = aDelayCount; + ieMsgLinkage.StopCount = aStopCount; + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + BroadcastAlternatingUpdate(); + + if(IsMute == 0){ + if( (ieMsgLinkage.Count == 0) && (AlarmSoundWhat >0) ){ + if( (ieMsgSv.Count > 0) && (IsMuteSv == 0) ){ + AlarmSoundWhat = 2; + }else + if( (ieMsgFault.Count > 0) && (IsMuteFault == 0) ){ + AlarmSoundWhat = 3; + }else{ + AlarmSoundWhat = 7; + } + } + } + + ieGot = 1; +} + + +int TControlCenter::iePushOneMsgLinkageStartCancelSimulate(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aStartCount, aFbCount, aMsCount, aVaCount, aDelayCount, aStopCount, aHP, aBroadcastCount; + unsigned char aP0, aP1, EpSta; + int IsPadEvent; + + IsPadEvent = 0; + + for(i=0; i0 ) && (aIm.Splite.P0 <= dPORT_MAX_COUNT) ){ + if(aP1 >= dEP_MAX_COUNT_PER_PORT)return 0; + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[aP0].DelayToDoEventType[aP1])Port[aP0].DelayTick[aP1] = 0; + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return 0; + } + }else{ + //EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + //EpSta &= ~(dEpStateBitStart); + //SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + }else + if( (aIm.Splite.P0 >= dADDR_DIRECTPAD_START) && (aIm.Splite.P0 <= dADDR_DIRECTPAD_END )){ + if(aP1 >= dDIRECTCTL_KEY_MAX_COUNT)return 0; + aP0 = aIm.Splite.P0 -dADDR_DIRECTPAD_START; + IsPadEvent = 1; + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(DirectCtlBoard[aP0].DelayToDoEventType[aP1]){ + DirectCtlBoard[aP0].DelayTick[aP1] = 0; + } + } + } + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + Cnt = 0; + i =0; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aStartCount = 0; + aFbCount = 0; + aMsCount = 0; + aVaCount = 0; + aBroadcastCount =0; + aHP =0; + aDelayCount = 0; + aStopCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( ( MsgReadTmp.D32[2] == aIm.D32[2]) && ( etLinkageStart == MsgReadTmp.Splite.mType ) && (StartTypeSimulate == MsgReadTmp.Splite.Data1) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageStart){ + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)){ + aDelayCount++; + }else + if(MsgReadTmp.Splite.Data0 == static_cast(0x09)){ + aStopCount++; + }else{ + aStartCount++; + //if(MsgReadTmp.Splite.Data1 == StartTypeSimulate){ + + //}else{ + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + }else + if(MsgReadTmp.Splite.dType == dASSIGN_TYPE_Broadcast){ + aBroadcastCount++; + } + //} + } + }else + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + + ieMsgLinkage.Count = Cnt; + ieMsgLinkage.StartCount = aStartCount; + ieMsgLinkage.FbCount = aFbCount; + ieMsgLinkage.MissingCount = aMsCount; + ieMsgLinkage.VaCount = aVaCount; + ieMsgLinkage.BroadcastCount = aBroadcastCount; + ieMsgLinkage.HydrantPadCount = aHP; + ieMsgLinkage.DelayCount = aDelayCount; + ieMsgLinkage.StopCount = aStopCount; + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + BroadcastAlternatingUpdate(); + + if(IsMute == 0){ + if( (ieMsgLinkage.Count == 0) && (AlarmSoundWhat >0) ){ + if( (ieMsgSv.Count > 0) && (IsMuteSv == 0) ){ + AlarmSoundWhat = 2; + }else + if( (ieMsgFault.Count > 0) && (IsMuteFault == 0) ){ + AlarmSoundWhat = 3; + }else{ + AlarmSoundWhat = 7; + } + } + } + + ieGot = 1; + + if(IsPadEvent)return 1; + else return 0; +} + +void TControlCenter::iePushOneMsgLinkageFb(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aFbCount, aMsCount; + unsigned char aP0, aP1, EpSta; + int tPumpFbCnt, tPumpFbLocalCnt; + + tPumpFbCnt = 0; tPumpFbLocalCnt = 0; + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + if(aIm.Splite.iByte0 == 0x04){ + Port[aP0].StateTable[aP1] |= dEpStateBitFbMiss; + }else{ + Port[aP0].StateTable[aP1] |= dEpStateBitFeedBack; + } + } + }else{ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + if(aIm.Splite.iByte0 == 0x04){ + EpSta |= dEpStateBitFbMiss; + }else{ + EpSta |= dEpStateBitFeedBack; + } + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aFbCount = 0; + aMsCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( (MsgReadTmp.D32[2] == aIm.D32[2]) && (etLinkageFeedBack == MsgReadTmp.Splite.mType) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.dType == dFIREPUMP_ASSIGN_TYPE){ + if(MsgReadTmp.Splite.Data1 != StartTypeSimulate){ + tPumpFbCnt++; + if(MsgReadTmp.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + tPumpFbLocalCnt++; + } + } + } + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_LINKAGE_MAX_COUNT){ + for(i=0; i< (ieMSG_LINKAGE_MAX_COUNT -1); i++){ + LinkageGetViaPath(i+1); + LinkageMsgCopyOne(i); + } + WritePst = ieMSG_LINKAGE_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + if(MsgReadTmp.Splite.dType == dFIREPUMP_ASSIGN_TYPE){ + tPumpFbCnt++; + if(MsgReadTmp.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + tPumpFbLocalCnt++; + } + } + + MsgReadTmp.Splite.mType = etLinkageFeedBack; + MsgReadTmp.Splite.Data0 = aIm.Splite.iByte0; + MsgReadTmp.Splite.Data1 = 0; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.State = ieStateActive; + LinkageMsgCopyOne(WritePst); + + ieMsgLinkage.Count = WritePst +1; + ieMsgLinkage.FbCount = aFbCount +1; + ieMsgLinkage.PumpFbCount = tPumpFbCnt; + ieMsgLinkage.PumpFbLocalCount = tPumpFbLocalCnt; + if(aIm.Splite.iByte0 == 0x04){ + ieMsgLinkage.MissingCount = aMsCount +1; + }else{ + ieMsgLinkage.MissingCount = aMsCount; + } + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + if(AlarmSoundWhat > 1)AlarmSoundWhat = 1; + + IsMuteLnk = 0; + IsMute = 0; + + ieGot = 1; +} + +int TControlCenter::iePushOneMsgLinkageFbSimulate(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aFbCount, aMsCount; + unsigned char aP0, aP1, EpSta; + int tPumpFbCnt, tPumpFbLocalCnt; + + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( (MsgReadTmp.D32[2] == aIm.D32[2]) && (etLinkageFeedBack == MsgReadTmp.Splite.mType)){ + if(MsgReadTmp.Splite.Data1 != StartTypeSimulate){ + return 0; + } + } + } + + tPumpFbCnt = 0; tPumpFbLocalCnt=0; + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return 0; + }else{ + if(aIm.Splite.iByte0 == 0x04){ + //Port[aP0].StateTable[aP1] |= dEpStateBitFbMiss; + }else{ + //Port[aP0].StateTable[aP1] |= dEpStateBitFeedBack; + } + } + }else{ + //EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + if(aIm.Splite.iByte0 == 0x04){ + //EpSta |= dEpStateBitFbMiss; + }else{ + //EpSta |= dEpStateBitFeedBack; + } + //SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aFbCount = 0; + aMsCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( (MsgReadTmp.D32[2] == aIm.D32[2]) && (etLinkageFeedBack == MsgReadTmp.Splite.mType) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.dType == dFIREPUMP_ASSIGN_TYPE){ + if(MsgReadTmp.Splite.Data1 != StartTypeSimulate){ + tPumpFbCnt++; + if(MsgReadTmp.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + tPumpFbLocalCnt++; + } + } + } + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_LINKAGE_MAX_COUNT){ + for(i=0; i< (ieMSG_LINKAGE_MAX_COUNT -1); i++){ + LinkageGetViaPath(i+1); + LinkageMsgCopyOne(i); + } + WritePst = ieMSG_LINKAGE_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + //Is Simulate + //if(MsgReadTmp.Splite.dType == dFIREPUMP_ASSIGN_TYPE){ + // tPumpFbCnt++; + //} + MsgReadTmp.Splite.mType = etLinkageFeedBack; + MsgReadTmp.Splite.Data0 = aIm.Splite.iByte0; + MsgReadTmp.Splite.Data1 = StartTypeSimulate; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.State = ieStateActive; + LinkageMsgCopyOne(WritePst); + + ieMsgLinkage.Count = WritePst +1; + ieMsgLinkage.FbCount = aFbCount +1; + ieMsgLinkage.PumpFbCount = tPumpFbCnt; + ieMsgLinkage.PumpFbLocalCount = tPumpFbLocalCnt; + + if(aIm.Splite.iByte0 == 0x04){ + ieMsgLinkage.MissingCount = aMsCount +1; + }else{ + ieMsgLinkage.MissingCount = aMsCount; + } + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + if(AlarmSoundWhat > 1)AlarmSoundWhat = 1; + + IsMuteLnk = 0; + IsMute = 0; + + ieGot = 1; + return 1; +} + +void TControlCenter::ieManualPushOneMsgLinkageFb(TRecordCommon aIm) +{ + iePushOneMsgLinkageFb(aIm); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); +} + +void TControlCenter::iePushOneMsgLinkageFbCancel(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aFbCount, aMsCount; + unsigned char aP0, aP1, EpSta; + int tPumpFbCnt, tPumpFbLocalCnt;; + + tPumpFbCnt = 0; tPumpFbLocalCnt =0; + + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] &= ~(dEpStateBitFeedBack + dEpStateBitFbMiss); + } + }else{ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta &= ~(dEpStateBitFeedBack + dEpStateBitFbMiss); + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aFbCount = 0; + aMsCount = 0; + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( (MsgReadTmp.D32[2] == aIm.D32[2]) && (etLinkageFeedBack == MsgReadTmp.Splite.mType) ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.dType == dFIREPUMP_ASSIGN_TYPE){ + if(MsgReadTmp.Splite.Data1 != StartTypeSimulate){ + tPumpFbCnt++; + if(MsgReadTmp.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + tPumpFbLocalCnt++; + } + } + } + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + + + ieMsgLinkage.Count = Cnt; + ieMsgLinkage.FbCount = aFbCount; + ieMsgLinkage.PumpFbCount = tPumpFbCnt; + ieMsgLinkage.PumpFbLocalCount = tPumpFbLocalCnt; + if(aIm.Splite.iByte0 == 0x04) + ieMsgLinkage.MissingCount = aMsCount +1; + else + ieMsgLinkage.MissingCount = aMsCount; + ieMsgLinkage.ReflashIndex++; + ieMsgLinkage.Lock = 0; + + if(IsMute == 0){ + if( (ieMsgLinkage.Count == 0) && (AlarmSoundWhat >0) ){ + if( (ieMsgSv.Count > 0) && (IsMuteSv == 0) ){ + AlarmSoundWhat = 2; + }else + if( (ieMsgFault.Count > 0) && (IsMuteFault == 0) ){ + AlarmSoundWhat = 3; + }else{ + AlarmSoundWhat = 7; + } + } + } + + ieGot = 1; +} + +void TControlCenter::iePushOneMsgFault(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aVaCount, aFbCount, aMsCount; + volatile unsigned char aP0, aP1, EpSta; + + aP0 = aIm.Splite.P0; + aP1 = aIm.Splite.P1; + aP0--; + aP1--; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] |= dEpStateBitFault; + } + }else{ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta |= dEpStateBitFault; + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + + ieMsgFault.RequestRead =0; + ieMsgFault.Lock = 1; + + FirstNullIndex = ieMSG_FAULT_MAX_COUNT +1000; + Cnt = 0; + aVaCount = 0; + for(i=0; i ieMSG_FAULT_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.D32[2] == aIm.D32[2]){ + FaultMsgClearOne(i); + if(FirstNullIndex > ieMSG_FAULT_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_FAULT_MAX_COUNT){ + FaultMsgCopyOne(FirstNullIndex); + FaultMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + } + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_FAULT_MAX_COUNT){ + for(i=0; i< (ieMSG_FAULT_MAX_COUNT -1); i++){ + FaultGetViaPath(i+1); + FaultMsgCopyOne(i); + } + WritePst = ieMSG_FAULT_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + __nop(); + __nop(); + MsgReadTmp.Splite.State = ieStateActive; + __nop(); + __nop(); + FaultMsgCopyOne(WritePst); + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + } + } + ieMsgFault.VaCount = aVaCount; + + ieMsgFault.Count = WritePst +1; + ieMsgFault.ReflashIndex++; + ieMsgFault.Lock = 0; + + ExRecord.SetStateCodeFault(); + FecBusCRT.SetStateCodeFault(); + + if(AlarmSoundWhat > 3)AlarmSoundWhat = 3; + IsMuteFault = 0; + IsMute = 0; + + ieGot = 1; +} + +void TControlCenter::iePushOneMsgFaultCancel(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aVaCount; + unsigned char aP0, aP1, EpSta; + + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] &= ~dEpStateBitFault; + } + }else{ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta &= ~dEpStateBitFault; + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + + ieMsgFault.RequestRead =0; + ieMsgFault.Lock = 1; + + FirstNullIndex = ieMSG_FAULT_MAX_COUNT +1000; + Cnt = 0; + aVaCount = 0; + for(i=0; i ieMSG_FAULT_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.D32[2] == aIm.D32[2]){ + FaultMsgClearOne(i); + if(FirstNullIndex > ieMSG_FAULT_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_FAULT_MAX_COUNT){ + FaultMsgCopyOne(FirstNullIndex); + FaultMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + } + } + } + } + + ieMsgFault.Count = Cnt; + ieMsgFault.VaCount = aVaCount; + ieMsgFault.ReflashIndex++; + ieMsgFault.Lock = 0; + + ExRecord.SetStateCodeFault(); + FecBusCRT.SetStateCodeFault(); + + if(IsMute == 0){ + if( (ieMsgFault.Count == 0) && (AlarmSoundWhat >2) ){ + AlarmSoundWhat = 7; + } + } + + ieGot = 1; +} + + +void TControlCenter::iePushOneMsgSv(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + unsigned char aP0, aP1, EpSta, aAssignType; + + aP0 = aIm.Splite.P0; + aP1 = aIm.Splite.P1; + aP0--; + aP1--; + aAssignType =0; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aAssignType = Port[aP0].AssignType[aP1]; + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] |= dEpStateBitSv; + } + }else{ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta |= dEpStateBitSv; + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + + ieMsgSv.RequestRead =0; + ieMsgSv.Lock = 1; + + FirstNullIndex = ieMSG_SV_MAX_COUNT +1000; + Cnt = 0; + for(i=0; i ieMSG_SV_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.D32[2] == aIm.D32[2]){ + SvMsgClearOne(i); + if(FirstNullIndex > ieMSG_SV_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_SV_MAX_COUNT){ + SvMsgCopyOne(FirstNullIndex); + SvMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_SV_MAX_COUNT){ + for(i=0; i< (ieMSG_SV_MAX_COUNT -1); i++){ + SvGetViaPath(i+1); + SvMsgCopyOne(i); + } + WritePst = ieMSG_SV_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.Data1 = 0; + __nop(); + __nop(); + MsgReadTmp.Splite.State = ieStateActive; + __nop(); + __nop(); + SvMsgCopyOne(WritePst); + + const unsigned int tInx = FiredUserCode.Count; + FiredUserCode.uCode[tInx] = aIm.Splite.UserCode; + FiredUserCode.AreaNum[tInx] = aIm.Splite.AreaNum; + FiredUserCode.dType[tInx] = aIm.Splite.dType; + FiredUserCode.AssignType[tInx] = 0; + FiredUserCode.eType[tInx] = LinkInputTypeSv; + if(FiredUserCode.Count < (dLINK_INPUT_MAX_COUNT -2))FiredUserCode.Count++; + + ieMsgSv.Count = WritePst +1; + ieMsgSv.ReflashIndex++; + ieMsgSv.Lock = 0; + + if(AlarmSoundWhat > 2)AlarmSoundWhat = 2; + + IsMuteSv = 0; + IsMute = 0; + + ieGot = 1; +} + +int TControlCenter::iePushOneMsgSvSimulate(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + unsigned char aP0, aP1, EpSta, aAssignType; + + for(i=0; i ieMSG_SV_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.D32[2] == aIm.D32[2]){ + SvMsgClearOne(i); + if(FirstNullIndex > ieMSG_SV_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_SV_MAX_COUNT){ + SvMsgCopyOne(FirstNullIndex); + SvMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + } + } + WritePst = Cnt; + if(Cnt >= ieMSG_SV_MAX_COUNT){ + for(i=0; i< (ieMSG_SV_MAX_COUNT -1); i++){ + SvGetViaPath(i+1); + SvMsgCopyOne(i); + } + WritePst = ieMSG_SV_MAX_COUNT -1; + } + + MsgReadTmp.D32[0] = aIm.D32[0]; + MsgReadTmp.D32[1] = aIm.D32[1]; + MsgReadTmp.D32[2] = aIm.D32[2]; + MsgReadTmp.D32[3] = aIm.D32[3]; + MsgReadTmp.D32[4] = aIm.D32[4]; + MsgReadTmp.D32[5] = aIm.D32[5]; + MsgReadTmp.Splite.iByte0 = 0; //is UnRead + MsgReadTmp.Splite.Data1 = StartTypeSimulate; + MsgReadTmp.Splite.State = ieStateActive; + SvMsgCopyOne(WritePst); + + const unsigned int tInx = FiredUserCode.Count; + FiredUserCode.uCode[tInx] = aIm.Splite.UserCode; + FiredUserCode.AreaNum[tInx] = aIm.Splite.AreaNum; + FiredUserCode.dType[tInx] = aIm.Splite.dType; + FiredUserCode.AssignType[tInx] = 0; + FiredUserCode.eType[tInx] = LinkInputTypeSvSimulate; + if(FiredUserCode.Count < (dLINK_INPUT_MAX_COUNT -2))FiredUserCode.Count++; + + ieMsgSv.Count = WritePst +1; + ieMsgSv.ReflashIndex++; + ieMsgSv.Lock = 0; + + if(AlarmSoundWhat > 2)AlarmSoundWhat = 2; + + IsMuteSv = 0; + IsMute = 0; + + ieGot = 1; + return 1; +} + + +void TControlCenter::iePushOneMsgSvCancel(TRecordCommon aIm) +{ + int i,Cnt, FirstNullIndex, WritePst; + unsigned char aP0, aP1, EpSta; + + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + if( (aP0 < dPORT_MAX_COUNT) && (aP1 < dEP_MAX_COUNT_PER_PORT) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + return; + }else{ + Port[aP0].StateTable[aP1] &= ~dEpStateBitSv; + } + }else{ + EpSta = GetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1); + EpSta &= ~dEpStateBitSv; + SetNetworkEpState(aIm.Splite.PCtlNum, aIm.Splite.P0, aIm.Splite.P1, EpSta); + } + } + + ieMsgSv.RequestRead =0; + ieMsgSv.Lock = 1; + + FirstNullIndex = ieMSG_SV_MAX_COUNT +1000; + Cnt = 0; + for(i=0; i ieMSG_SV_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.D32[2] == aIm.D32[2]){ + SvMsgClearOne(i); + if(FirstNullIndex > ieMSG_SV_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_SV_MAX_COUNT){ + SvMsgCopyOne(FirstNullIndex); + SvMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + } + } + + ieMsgSv.Count = Cnt; + ieMsgSv.ReflashIndex++; + ieMsgSv.Lock = 0; + + if(IsMute == 0){ + if( (ieMsgSv.Count == 0) && (AlarmSoundWhat >1) ){ + if( (ieMsgFault.Count > 0) && (IsMuteFault == 0) ){ + AlarmSoundWhat = 3; + }else{ + AlarmSoundWhat = 7; + } + } + } + + ieGot = 1; +} + +void TControlCenter::LoadCurrentDateTime2RecordCommon(TRecordCommon *pIm) +{ + pIm->Splite.Year = DateTime.Date.Split.Year; + pIm->Splite.Month = DateTime.Date.Split.Month; + pIm->Splite.Day = DateTime.Date.Split.Day; + pIm->Splite.Hour = DateTime.Time.Split.Hour; + pIm->Splite.Minute = DateTime.Time.Split.Minute; + pIm->Splite.Second = DateTime.Time.Split.Second; +} + +void TControlCenter::ieAddDevFault(unsigned char aDevFaultType, unsigned char DevIndex) +{ + TRecordCommon aIm; + + LoadCurrentDateTime2RecordCommon(&aIm); + aIm.Splite.mType = CmdActiveDefaultSet[cmOtherErr][7]; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + aIm.Splite.P0 = 0xD0; //Board Index + aIm.Splite.P1 = DevIndex; + aIm.Splite.P2 = aDevFaultType; //Fault Type + aIm.Splite.dType = 0; + aIm.Splite.Data0 = aDevFaultType; //Fault Type + aIm.Splite.Data1 = 0xD1;//Is Set=1 Recover=0 + aIm.Splite.iByte0 = CmdActiveDefaultSet[cmOtherErr][8]; + + iePushOneMsgFault(aIm); + Record.FaultAdd(aIm); + + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.oBufMsgInsertFault(aIm, cmOtherErr); +} + +void TControlCenter::ieAddDevFaultCancel(unsigned char aDevFaultType, unsigned char DevIndex) +{ + TRecordCommon aIm; + + LoadCurrentDateTime2RecordCommon(&aIm); + aIm.Splite.mType = CmdActiveDefaultSet[cmOtherErr][7]; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + aIm.Splite.P0 = 0xD0; //Board Index + aIm.Splite.P1 = DevIndex; + aIm.Splite.P2 = aDevFaultType; //Fault Type + aIm.Splite.dType = 0; + aIm.Splite.Data0 = aDevFaultType; //Fault Type + aIm.Splite.Data1 = 0xD0;//Is Set=1 Recover=0 + aIm.Splite.iByte0 = CmdActiveDefaultSet[cmOtherErr][8]; + + iePushOneMsgFaultCancel(aIm); + Record.FaultAdd(aIm); + + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.oBufMsgInsertFault(aIm, cmOtherErr); +} + +void TControlCenter::ieAddPadFault(unsigned char aP0, unsigned char aFaultType) +{ + TRecordCommon aIm; + + LoadCurrentDateTime2RecordCommon(&aIm); + aIm.Splite.mType = CmdActiveDefaultSet[cmOtherErr][7]; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + aIm.Splite.P0 = 0xC0; //Pad's Type + aIm.Splite.P1 = aP0; + aIm.Splite.P2 = aFaultType; //Fault Type + aIm.Splite.dType = 0; + aIm.Splite.Data0 = aFaultType; //Fault Type + aIm.Splite.Data1 = 0xC1; //Is Set=1 Recover=0 + aIm.Splite.iByte0 = CmdActiveDefaultSet[cmOtherErr][8]; + + iePushOneMsgFault(aIm); + Record.FaultAdd(aIm); + + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.oBufMsgInsertFault(aIm, cmOtherErr); +} + +void TControlCenter::ieAddPadFaultCancel(unsigned char aP0, unsigned char aFaultType) +{ + TRecordCommon aIm; + + LoadCurrentDateTime2RecordCommon(&aIm); + aIm.Splite.mType = CmdActiveDefaultSet[cmOtherErr][7]; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + aIm.Splite.P0 = 0xC0; //Board Index + aIm.Splite.P1 = aP0; //Pad Addr + aIm.Splite.P2 = aFaultType; //Fault Type + aIm.Splite.dType = 0; + aIm.Splite.Data0 = aFaultType; //Fault Type + aIm.Splite.Data1 = 0xC0;//Is Set=1 Recover=0 + aIm.Splite.iByte0 = CmdActiveDefaultSet[cmOtherErr][8]; + + iePushOneMsgFaultCancel(aIm); + Record.FaultAdd(aIm); + + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.oBufMsgInsertFault(aIm, cmOtherErr); +} + +void TControlCenter::iePushOneMsg(TRecordCommon aIm, unsigned char aCmd) +{ + unsigned char aCtlNum, aP0, aP1; + unsigned int ReturnByMask = 0; + unsigned int CheckPathOK =0; + aCtlNum = aIm.Splite.PCtlNum; + if(aCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = aIm.Splite.P0 -1; + aP1 = aIm.Splite.P1 -1; + if(aP0 < dPORT_MAX_COUNT){ + if(Port[aP0].StateTable[aP1] & dEpStateBitMask){ + ReturnByMask = 1; + } + } + } + if(aIm.Splite.mType == etFire){ + if(ReturnByMask)return; + if(aCmd == cmPublishAlram){ + if(IsMsgReseting == 0){ + iePushOneMsgFire(aIm,0); + //ProtoC2C.MasterDoPublishFire(aCtlNum, aIm.Splite.P0, aIm.Splite.P1, aIm.Splite.dType); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtFire); + ExRecord.SetStateCodeFire(); + FecBusCRT.SetStateCodeFire(); + Record.FireAdd(aIm); + } + }else + if(aCmd == cmConfirmAlram){ + if(IsMsgReseting == 0){ + iePushOneMsgFire(aIm,0); + ExRecord.SetStateCodeFire(); + FecBusCRT.SetStateCodeFire(); + //ProtoC2C.MasterDoPublishFire(aCtlNum, aIm.Splite.P0, aIm.Splite.P1, aIm.Splite.dType); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtNormal); + } + }else + if(aCmd == cmPublishPreAlramResume){ + if(IsMsgReseting == 0); + } + }else + if(aIm.Splite.mType == etFault){ + if(aCmd == cmPortModuleErr){ + if(ReturnByMask)return; + if(IsMsgReseting == 0){ + iePushOneMsgFault(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtFault); + Record.FaultAdd(aIm); + } + }else + if(aCmd == cmCircuitErr){ + if(aIm.Splite.Data1 & 0x01){ + iePushOneMsgFault(aIm); + }else{ + iePushOneMsgFaultCancel(aIm); + } + Record.FaultAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtFault); + }else + if(aCmd == cmOtherErr){ + if(aIm.Splite.Data1 & 0x01){ + iePushOneMsgFault(aIm); + }else{ + iePushOneMsgFaultCancel(aIm); + } + Record.FaultAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtFault); + } + }else + if(aIm.Splite.mType == etFaultCancel){ + if(ReturnByMask)return; + if(aCmd == cmPortModuleErrRecover){ + if(IsMsgReseting == 0){ + iePushOneMsgFaultCancel(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtFault); + Record.FaultAdd(aIm); + } + } + }else + if(aIm.Splite.mType == etSuperVi){ + if(ReturnByMask)return; + if(aCmd == cmTakeChargeAlram){ + iePushOneMsgSv(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtSv); + ExRecord.SetStateCodeSv(); + FecBusCRT.SetStateCodeSv(); + Record.SvAdd(aIm); + } + }else + if(aIm.Splite.mType == etSuperViCancel){ + if(ReturnByMask)return; + if(aCmd == cmTakeChargeAlramResume){ + //iePushOneMsgSvCancel(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtSv); + ExRecord.SetStateCodeSv(); + FecBusCRT.SetStateCodeSv(); + Record.SvAdd(aIm); + } + } + if(aIm.Splite.mType == etLinkageStart){ + if(IsMsgReseting == 0){ + if((aIm.Splite.P0==0)||(aIm.Splite.P1==0))return; + if(aIm.Splite.P0<=dPORT_MAX_COUNT){ + if(aIm.Splite.P1<=dEP_MAX_COUNT_PER_PORT) + CheckPathOK =1; + } + if( (aIm.Splite.P0>=dADDR_DIRECTPAD_START) && (aIm.Splite.P0<=dADDR_DIRECTPAD_END) ){ + if(aIm.Splite.P1 <= dDIRECTCTL_KEY_MAX_COUNT) + CheckPathOK =1; + } + if(CheckPathOK==0)return; + if(aCmd == cmManualStart){ + iePushOneMsgLinkageStart(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + }else + if(aCmd == cmAutoStart){ + iePushOneMsgLinkageStart(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + }else + if(aCmd == cmVAAlramStart){ + //From Ctl + iePushOneMsgLinkageStart(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + } + CheckHydrantKpAction(); + } + }else + if(aIm.Splite.mType == etLinkageStartCancel){ + //Record.StartAdd(aIm); + if(IsMsgReseting == 0){ + if(aCmd == cmManualStop){ + iePushOneMsgLinkageStartCancel(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + + aIm.Splite.iByte0 = 0xB1; + Record.LinkageAdd(aIm); + }else + if(aCmd == cmAutoStop){ + iePushOneMsgLinkageStartCancel(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + + aIm.Splite.iByte0 = 0xB1; + Record.LinkageAdd(aIm); + }else + if(aCmd == cmVAAlramStop){ + //From Ctl + iePushOneMsgLinkageStartCancel(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + } + CheckHydrantKpAction(); + } + }else + if(aIm.Splite.mType == etLinkageFeedBack){ + if(IsMsgReseting == 0){ + if(aCmd == cmAck){ + int HasPrc =0; + if(aCtlNum == MainCtl.fData.Split.MyNum){ + if( (aIm.Splite.P0) && (aIm.Splite.P1) ){ + if( (aIm.Splite.P0 <= dPORT_MAX_COUNT) && (aIm.Splite.P1 <= dEP_MAX_COUNT_PER_PORT) ){ + unsigned char tP0, tP1, tFbits; + tP0=aIm.Splite.P0-1; tP1=aIm.Splite.P1-1; + if( (Port[aP0].dTypeTable[tP1] == dgTYPE_IN_MODULE) || + (Port[aP0].dTypeTable[tP1] == dgTYPE_INOUT_MODULE_NonSource) || + (Port[aP0].dTypeTable[tP1] == dgTYPE_INOUT_MODULE_Source) ){ + //0x01 FeedBack 0x02 Fire 0x04 SV + if( (Port[tP0].FuncSetByte[tP1] & 0x07) == 0x02){ + if(ReturnByMask == 0){ + for(int i=0; i<6; i++)aImForceConvert.D32[i] = aIm.D32[i]; + aImForceConvert.Splite.mType = etFire; + iePushOneMsgFire(aImForceConvert,0); + //ProtoC2C.MasterDoPublishFire(aCtlNum, aIm.Splite.P0, aIm.Splite.P1, aIm.Splite.dType); + ProtoC2C.SlaveDoSend2MasterMachine(aImForceConvert, cmPublishAlram, TProtoC2C::mtFire); + ExRecord.SetStateCodeFire(); + FecBusCRT.SetStateCodeFire(); + Record.FireAdd(aImForceConvert); + } + HasPrc =1; + }else + if( (Port[tP0].FuncSetByte[tP1] & 0x07) == 0x04){ + if(ReturnByMask == 0){ + for(int i=0; i<6; i++)aImForceConvert.D32[i] = aIm.D32[i]; + aImForceConvert.Splite.mType = etSuperVi; + iePushOneMsgSv(aImForceConvert); + ProtoC2C.SlaveDoSend2MasterMachine(aImForceConvert, cmTakeChargeAlram, TProtoC2C::mtSv); + ExRecord.SetStateCodeSv(); + FecBusCRT.SetStateCodeSv(); + Record.SvAdd(aImForceConvert); + } + HasPrc =1; + } + } + } + } + } + if(HasPrc == 0){ + iePushOneMsgLinkageFb(aIm); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); + Record.LinkageAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + } + }else + if(aCmd == cmAckMiss){ + iePushOneMsgLinkageFb(aIm); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); + Record.LinkageAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + } + } + }else + if(aIm.Splite.mType == etLinkageFeedBackCancel){ + if(IsMsgReseting == 0){ + if(aCmd == cmAckStop){ + int HasPrc =0; + if(aCtlNum == MainCtl.fData.Split.MyNum){ + if( (aIm.Splite.P0) && (aIm.Splite.P1) ){ + if( (aIm.Splite.P0 <= dPORT_MAX_COUNT) && (aIm.Splite.P1 <= dEP_MAX_COUNT_PER_PORT) ){ + unsigned char tP0, tP1, tFbits; + tP0=aIm.Splite.P0-1; tP1=aIm.Splite.P1-1; + if( (Port[aP0].dTypeTable[tP1] == dgTYPE_IN_MODULE) || + (Port[aP0].dTypeTable[tP1] == dgTYPE_INOUT_MODULE_NonSource) || + (Port[aP0].dTypeTable[tP1] == dgTYPE_INOUT_MODULE_Source) ){ + //0x01 FeedBack 0x02 Fire 0x04 SV + if( (Port[tP0].FuncSetByte[tP1] & 0x07) == 0x02){ + if(ReturnByMask == 0){ + //Fire with No Cancel + } + HasPrc =1; + } + if( (Port[tP0].FuncSetByte[tP1] & 0x07) == 0x04){ + if(ReturnByMask == 0){ + //SV with No Cancel + } + HasPrc =1; + } + } + } + } + } + if(HasPrc == 0){ + iePushOneMsgLinkageFbCancel(aIm); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, aCmd, TProtoC2C::mtLink); + } + } + } + }else + if(aIm.Splite.mType == etReport){ + if(aCmd == cmPortRegistFinished){ + Register.iePushOneMsgReport(aIm, aCmd); + }else + if(aCmd == cmPortRegistProgress){ + Register.iePushOneMsgReport(aIm, aCmd); + }else + if(aCmd == cmQueryPortReg){ + CtrlStartUp.iePushOneMsgReport(aIm, aCmd); + Register.iePushOneMsgReport(aIm, aCmd); + } + } +} + +unsigned int TControlCenter::ieFireMsgConfAddr(unsigned int FullPath) +{ + unsigned int tUc; + int i; + tUc = 100000000; + if(ieMsgFire.Count >ieMSG_FIRE_MAX_COUNT)ieMsgFire.Count = ieMSG_FIRE_MAX_COUNT; + for(i=0; iieMSG_FAULT_MAX_COUNT)ieMsgFault.Count = ieMSG_FAULT_MAX_COUNT; + for(i=0; i 39){ + //Check State First + InspecDataCheck(); + InspecDataRestart(); + InspecData.IsStartCheck = 1; + InspecData.tick = 0; + + tData[1] =0; tData[1] =0; + tData[2] =0; tData[3] =0; tData[4] =0; tData[5] =0; tData[6] =0; tData[7] =0; + InnerCan.OBufInsert(1, cmInspection, tData, 1); + } +} + +void TControlCenter::PushInspecRpy(unsigned char Path0, unsigned char Prm) +{ + unsigned char aHpPath; + if( (Path0 >= dADDR_HANDPAD_START) && (Path0 <= dADDR_HANDPAD_END) ){ + aHpPath = Path0 - dADDR_HANDPAD_START; + InspecData.BusPad[aHpPath] = 1; + }else + if( (Path0 >= dADDR_DIRECTPAD_START) && (Path0 <= dADDR_DIRECTPAD_END) ){ + aHpPath = Path0 - dADDR_DIRECTPAD_START; + InspecData.DirectPad[aHpPath] = 1; + } +} + +void TControlCenter::CheckBatUpdate() +{ + if(PsBatData.Body.HasUpdate){ + PsBatData.Body.HasUpdate = 0; + if( (PsBatData.Body.BatVoltage1.D16 != PsBatDataOld.Body.BatVoltage1.D16) || + (PsBatData.Body.BatVoltage2.D16 != PsBatDataOld.Body.BatVoltage2.D16) || + (PsBatData.Body.BatEnerger1 != PsBatDataOld.Body.BatEnerger1) || + (PsBatData.Body.BatEnerger2 != PsBatDataOld.Body.BatEnerger2) || + (PsBatDataAva == 0) ){ + PsBatDataOld.Body.BatVoltage1.D16 = PsBatData.Body.BatVoltage1.D16; + PsBatDataOld.Body.BatVoltage2.D16 = PsBatData.Body.BatVoltage2.D16; + PsBatDataOld.Body.BatEnerger1 = PsBatData.Body.BatEnerger1; + PsBatDataOld.Body.BatEnerger2 = PsBatData.Body.BatEnerger2; + StateBarUpDateBat(1); + } + PsBatUpDateTick = 0; + }else{ + PsBatUpDateTick++; + if(PsBatUpDateTick > 20){ + PsBatUpDateTick = 30; + StateBarUpDateBat(0); + } + } +} + +void TControlCenter::MaskCountSet(int aCnt) +{ + ieMsgMask.Count = aCnt; + EventShow.MsgList[4].Count = ieMsgMask.Count; + EventShow.MsgList[4].NewCount = ieMsgMask.Count; + EventShow.TryGetMaskData(2,20240428); + CtlCenter.ieMsgMask.ReflashIndex ++; + CtlCenter.ieGot = 1; + + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); +} + +void TControlCenter::SingleCtlModeSendMaskInf2Crt() +{ + volatile int i, x; + volatile unsigned int sAddr, MaskCount, suExit; + TRecordCommon aRC; + for(i=0; i dDISPLAYPAD_MAX_COUNT)Port[Ord].DisplayPadCount = dDISPLAYPAD_MAX_COUNT; + for(i=0; i dNETWORK_MACHINE_COUNT)continue; + //if(DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].CtlNum == 0)continue; + //if(DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].P0 > dPORT_MAX_COUNT)continue; + //if(DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].P0 == 0)continue; + Trigger = 0; + for(x=0; x<3; x++){ + //aCn = DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].CtlNum; + //aP0 = DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].P0; + //BeginAddr = DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].BeginAddr; + //EndAddr = DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].EndAddr; + aP0--; + BeginAddr--; + EndAddr--; + if(aCn == MainCtl.fData.Split.MyNum){ + for(iA=BeginAddr; iA= dDiplayPadCtlBufMaxCount)DisplayPadBuf.WriteIndex = 0; + + //DisplayPadBuf.Body[DisplayPadBuf.WriteIndex].P0 = Ord; + //DisplayPadBuf.Body[DisplayPadBuf.WriteIndex].P1 = Port[Ord].DisplayPadAddr[i]; + + //DisplayPadBuf.Source[DisplayPadBuf.WriteIndex].CtlNum = DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].CtlNum;; + //DisplayPadBuf.Source[DisplayPadBuf.WriteIndex].P0 = DisplayPadRt.Entry[Ord][i].Spl.UsingPath[x].P0; + //DisplayPadBuf.Source[DisplayPadBuf.WriteIndex].P1 = iA +1;; + //DisplayPadBuf.Source[DisplayPadBuf.WriteIndex].dType = mVal.D8[1]; + break; + } + } + } + } +} + +void TControlCenter::DisplayPadCheckByIndex() +{ + int ex, AreaGot; + unsigned char tP0, tP1; + unsigned short cArea; + unsigned int Addr_Sd; + TUserCodeStr tCode, tCodeNot; + TUserCodeStr cCode, cmpCode; + if(DisplayPadPrcFireIndex < ieMsgFire.Count){ + FireGetViaPath(DisplayPadPrcFireIndex); + cArea = MsgReadTmp.Splite.AreaNum; + cCode.Spl.BcdText_7 = this->MsgReadTmp.Splite.UserCode / 10000000 % 10; + cCode.Spl.BcdText_6 = this->MsgReadTmp.Splite.UserCode / 1000000 % 10; + cCode.Spl.BcdText_5 = this->MsgReadTmp.Splite.UserCode / 100000 % 10; + cCode.Spl.BcdText_4 = this->MsgReadTmp.Splite.UserCode / 10000 % 10; + cCode.Spl.BcdText_3 = this->MsgReadTmp.Splite.UserCode / 1000 % 10; + cCode.Spl.BcdText_2 = this->MsgReadTmp.Splite.UserCode / 100 % 10; + cCode.Spl.BcdText_1 = this->MsgReadTmp.Splite.UserCode / 10 % 10; + cCode.Spl.BcdText_0 = this->MsgReadTmp.Splite.UserCode / 1 % 10; + for(tP0=0; tP0= dDiplayPadCtlBufMaxCount)DisplayPadBuf.WriteIndex = 0; + DisplayPadBuf.BodyTmp.Body.P0 = tP0 +1; + DisplayPadBuf.BodyTmp.Body.P1 = tP1 +1; + DisplayPadBuf.BodyTmp.Body.SourceInx = DisplayPadPrcFireIndex; + Addr_Sd = dAddrSdRam_DisplayPadBuf + (DisplayPadBuf.WriteIndex * 8); + *(volatile unsigned int*)(Addr_Sd + 0) = DisplayPadBuf.BodyTmp.D32[0]; + *(volatile int*)(Addr_Sd + 4) = DisplayPadBuf.BodyTmp.D32[1]; + AreaGot =1; + } + } + if( (Port[tP0].DisplayPadSet[ex].CfgBits & TPort::DisplayPadUsingAreaEx1) && (Port[tP0].DisplayPadSet[ex].AreaEx[1] != 0) ){ + //Area Num 1 + if( (cArea == Port[tP0].DisplayPadSet[ex].AreaEx[1]) && (AreaGot == 0) ){ + DisplayPadBuf.WriteIndex++; + if(DisplayPadBuf.WriteIndex >= dDiplayPadCtlBufMaxCount)DisplayPadBuf.WriteIndex = 0; + DisplayPadBuf.BodyTmp.Body.P0 = tP0 +1; + DisplayPadBuf.BodyTmp.Body.P1 = tP1 +1; + DisplayPadBuf.BodyTmp.Body.SourceInx = DisplayPadPrcFireIndex; + Addr_Sd = dAddrSdRam_DisplayPadBuf + (DisplayPadBuf.WriteIndex * 8); + *(volatile unsigned int*)(Addr_Sd + 0) = DisplayPadBuf.BodyTmp.D32[0]; + *(volatile int*)(Addr_Sd + 4) = DisplayPadBuf.BodyTmp.D32[1]; + AreaGot =1; + } + } + if( (Port[tP0].DisplayPadSet[ex].CfgBits & TPort::DisplayPadUsingAreaEx2) && (Port[tP0].DisplayPadSet[ex].AreaEx[2] != 0) ){ + //Area Num 2 + if( (cArea == Port[tP0].DisplayPadSet[ex].AreaEx[2]) && (AreaGot == 0) ){ + DisplayPadBuf.WriteIndex++; + if(DisplayPadBuf.WriteIndex >= dDiplayPadCtlBufMaxCount)DisplayPadBuf.WriteIndex = 0; + DisplayPadBuf.BodyTmp.Body.P0 = tP0 +1; + DisplayPadBuf.BodyTmp.Body.P1 = tP1 +1; + DisplayPadBuf.BodyTmp.Body.SourceInx = DisplayPadPrcFireIndex; + Addr_Sd = dAddrSdRam_DisplayPadBuf + (DisplayPadBuf.WriteIndex * 8); + *(volatile unsigned int*)(Addr_Sd + 0) = DisplayPadBuf.BodyTmp.D32[0]; + *(volatile int*)(Addr_Sd + 4) = DisplayPadBuf.BodyTmp.D32[1]; + } + } + }else{ + if( (Port[tP0].DisplayPadSet[ex].CfgBits & TPort::DisplayPadUsingUcEx0) && (Port[tP0].DisplayPadSet[ex].UcList[0].Full != 0) ){ + //User Code 0 + tCode.Full = Port[tP0].DisplayPadSet[ex].UcList[0].Full; + tCodeNot.Full =0; + if(tCode.Spl.BcdText_0 == 10){tCode.Spl.BcdText_0 = 0xF; tCodeNot.Spl.BcdText_0 = 0xF;} + if(tCode.Spl.BcdText_1 == 10){tCode.Spl.BcdText_1 = 0xF; tCodeNot.Spl.BcdText_1 = 0xF;} + if(tCode.Spl.BcdText_2 == 10){tCode.Spl.BcdText_2 = 0xF; tCodeNot.Spl.BcdText_2 = 0xF;} + if(tCode.Spl.BcdText_3 == 10){tCode.Spl.BcdText_3 = 0xF; tCodeNot.Spl.BcdText_3 = 0xF;} + if(tCode.Spl.BcdText_4 == 10){tCode.Spl.BcdText_4 = 0xF; tCodeNot.Spl.BcdText_4 = 0xF;} + if(tCode.Spl.BcdText_5 == 10){tCode.Spl.BcdText_5 = 0xF; tCodeNot.Spl.BcdText_5 = 0xF;} + if(tCode.Spl.BcdText_6 == 10){tCode.Spl.BcdText_6 = 0xF; tCodeNot.Spl.BcdText_6 = 0xF;} + if(tCode.Spl.BcdText_7 == 10){tCode.Spl.BcdText_7 = 0xF; tCodeNot.Spl.BcdText_7 = 0xF;} + cmpCode.Full = cCode.Full | tCodeNot.Full; + if(cmpCode.Full == tCode.Full){ + DisplayPadBuf.WriteIndex++; + if(DisplayPadBuf.WriteIndex >= dDiplayPadCtlBufMaxCount)DisplayPadBuf.WriteIndex = 0; + DisplayPadBuf.BodyTmp.Body.P0 = tP0 +1; + DisplayPadBuf.BodyTmp.Body.P1 = tP1 +1; + DisplayPadBuf.BodyTmp.Body.SourceInx = DisplayPadPrcFireIndex; + Addr_Sd = dAddrSdRam_DisplayPadBuf + (DisplayPadBuf.WriteIndex * 8); + *(volatile unsigned int*)(Addr_Sd + 0) = DisplayPadBuf.BodyTmp.D32[0]; + *(volatile int*)(Addr_Sd + 4) = DisplayPadBuf.BodyTmp.D32[1]; + } + } + if( (Port[tP0].DisplayPadSet[ex].CfgBits & TPort::DisplayPadUsingUcEx1) && (Port[tP0].DisplayPadSet[ex].UcList[1].Full != 0) ){ + //User Code 1 + tCode.Full = Port[tP0].DisplayPadSet[ex].UcList[1].Full; + tCodeNot.Full =0; + if(tCode.Spl.BcdText_0 == 10){tCode.Spl.BcdText_0 = 0xF; tCodeNot.Spl.BcdText_0 = 0xF;} + if(tCode.Spl.BcdText_1 == 10){tCode.Spl.BcdText_1 = 0xF; tCodeNot.Spl.BcdText_1 = 0xF;} + if(tCode.Spl.BcdText_2 == 10){tCode.Spl.BcdText_2 = 0xF; tCodeNot.Spl.BcdText_2 = 0xF;} + if(tCode.Spl.BcdText_3 == 10){tCode.Spl.BcdText_3 = 0xF; tCodeNot.Spl.BcdText_3 = 0xF;} + if(tCode.Spl.BcdText_4 == 10){tCode.Spl.BcdText_4 = 0xF; tCodeNot.Spl.BcdText_4 = 0xF;} + if(tCode.Spl.BcdText_5 == 10){tCode.Spl.BcdText_5 = 0xF; tCodeNot.Spl.BcdText_5 = 0xF;} + if(tCode.Spl.BcdText_6 == 10){tCode.Spl.BcdText_6 = 0xF; tCodeNot.Spl.BcdText_6 = 0xF;} + if(tCode.Spl.BcdText_7 == 10){tCode.Spl.BcdText_7 = 0xF; tCodeNot.Spl.BcdText_7 = 0xF;} + cmpCode.Full = cCode.Full | tCodeNot.Full; + if(cmpCode.Full == tCode.Full){ + DisplayPadBuf.WriteIndex++; + if(DisplayPadBuf.WriteIndex >= dDiplayPadCtlBufMaxCount)DisplayPadBuf.WriteIndex = 0; + DisplayPadBuf.BodyTmp.Body.P0 = tP0 +1; + DisplayPadBuf.BodyTmp.Body.P1 = tP1 +1; + DisplayPadBuf.BodyTmp.Body.SourceInx = DisplayPadPrcFireIndex; + Addr_Sd = dAddrSdRam_DisplayPadBuf + (DisplayPadBuf.WriteIndex * 8); + *(volatile unsigned int*)(Addr_Sd + 0) = DisplayPadBuf.BodyTmp.D32[0]; + *(volatile int*)(Addr_Sd + 4) = DisplayPadBuf.BodyTmp.D32[1]; + } + } + } + } + } + } + + } + } + } + DisplayPadPrcFireIndex++; + } +} + +int TControlCenter::DipalayPadSendPathType() +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + if(get_can_tx_complete() == 0)return 0; + + Len =8; + + aIde.BitF.Cmd = cmSendDisplayPadInf; + for(i=0; i<8; i++){ + tData[i] = 0; + } + + tData[0] = 0; + tData[1] = DisplayPadPath.P0; + tData[2] = DisplayPadPath.P1; + tData[3] = 1; + tData[4] = DisplayPadTriggerSource.CtlNum; + tData[5] = DisplayPadTriggerSource.P0; + tData[6] = DisplayPadTriggerSource.P1; + tData[7] = DisplayPadTriggerSource.dType; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, tData, Len); + return 1; +} + +int TControlCenter::DipalayPadSendYearMonth() +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + + if(get_can_tx_complete() == 0)return 0; + Len =6; + aIde.BitF.Cmd = cmSendDisplayPadInf; + for(i=0; i<8; i++){ + tData[i] = 0; + } + tData[0] = 0; + tData[1] = DisplayPadPath.P0; + tData[2] = DisplayPadPath.P1; + tData[3] = 2; + tData[4] = DisplayYearMonth.D8[1]; + tData[5] = DisplayYearMonth.D8[0]; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, tData, Len); + return 1; +} + +int TControlCenter::DipalayPadSendDayTime() +{ + TCanHeaderID aIde; + unsigned int i; + unsigned int Len; + + if(get_can_tx_complete() == 0)return 0; + + Len =8; + + aIde.BitF.Cmd = cmSendDisplayPadInf; + for(i=0; i<8; i++){ + tData[i] = 0; + } + + tData[0] = 0; + tData[1] = DisplayPadPath.P0; + tData[2] = DisplayPadPath.P1; + tData[3] = 3; + tData[4] = DisplayDayTime.D8[3]; + tData[5] = DisplayDayTime.D8[2]; + tData[6] = DisplayDayTime.D8[1]; + tData[7] = DisplayDayTime.D8[0]; + + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, tData, Len); + + return 1; +} + +void TControlCenter::DisplayPadGoSend() +{ + if(DisplaySendingWhat == 1){ + if(get_can_tx_complete()){ + //0:ACK 1:回路号 2:地址号 3:分帧号 4:机器号 5:回路号 6:地址 7:类型 + if(DipalayPadSendPathType()) + DisplaySendingWhat ++; + } + }else + if(DisplaySendingWhat == 2){ + //dAddrSdram_FireTime + if(get_can_tx_complete()){ + //0:ACK 1:回路号 2:地址号 3:分帧号 4:年 5:月 + if(DipalayPadSendYearMonth()) + DisplaySendingWhat++; + } + }else + if(DisplaySendingWhat >2) { + if(get_can_tx_complete()){ + //0:ACK 1:回路号 2:地址号 3:分帧号 4:日 5:时 6:分 7:秒 + if(DipalayPadSendDayTime()) + DisplaySendingWhat = 0; + } + } +} + +void TControlCenter::DisplayPadCheckToSend() +{ + unsigned int Addr_Sd; + if(DisplayPadBuf.WriteIndex != DisplayPadBuf.ReadIndex){ + if(0 == DisplaySendingWhat){ + DisplayPadBuf.ReadIndex++; + if(DisplayPadBuf.ReadIndex >= dDiplayPadCtlBufMaxCount)DisplayPadBuf.ReadIndex = 0; + Addr_Sd = dAddrSdRam_DisplayPadBuf + (DisplayPadBuf.ReadIndex * 8); + DisplayPadBuf.BodyTmp.D32[0] = *(volatile unsigned int*)(Addr_Sd + 0); + DisplayPadBuf.BodyTmp.D32[1] = *(volatile int*)(Addr_Sd + 4); + DisplayPadPath.P0 = DisplayPadBuf.BodyTmp.Body.P0; + DisplayPadPath.P1 = DisplayPadBuf.BodyTmp.Body.P1; + FireGet4DisplayPadViaIndex(DisplayPadBuf.BodyTmp.Body.SourceInx); + DisplayPadTriggerSource.CtlNum = DisplayPadMsg.Splite.PCtlNum; + DisplayPadTriggerSource.P0 = DisplayPadMsg.Splite.P0; + DisplayPadTriggerSource.P1 = DisplayPadMsg.Splite.P1; + DisplayPadTriggerSource.dType = DisplayPadMsg.Splite.dType; + DisplayDayTime.D32 = DisplayPadMsg.D32[0]; + DisplayYearMonth.D32 = DisplayPadMsg.D32[1]; + DisplaySendingWhat = 1; + } + } +} + +void TControlCenter::ModuleInOutCountDown() +{ + +} + +void TControlCenter::CheckFeedBackMiss() +{ + int i,x; + unsigned char aInx; + FeedBackMissCount = 0; + for(i=0; i= dADDR_HANDPAD_START) && (aPrm <= dADDR_HANDPAD_END) ){ + aP0 = aPrm - dADDR_HANDPAD_START; + HandCtlBoard[aP0].SendPadCfg2Pad(aP0); + if(HandCtlBoard[aP0].PadIsProhibit == 0){ + InspecData.BusPad[aP0] = 1; + if(InspecData.ErrBusPad[aP0]){ + //Cancel Err Msg + InspecData.ErrBusPad[aP0] = 0; + ieAddPadFaultCancel(aP0 + dADDR_HANDPAD_START, 2); + } + } + } + } + }else + if(aCmd == cmDirectPadConfigReq){ + if(aReq == 0){ + if( (aPrm >= dADDR_DIRECTPAD_START) && (aPrm <= dADDR_DIRECTPAD_END) ){ + aP0 = aPrm - dADDR_DIRECTPAD_START; + DirectCtlBoard[aP0].SendPadCfg2Pad(aP0); + if(DirectCtlBoard[aP0].PadIsProhibit == 0){ + InspecData.DirectPad[aP0] = 1; + if(InspecData.ErrDirectPad[aP0]){ + //Cancel Err Msg + InspecData.ErrDirectPad[aP0] = 0; + ieAddPadFaultCancel(aP0 + dADDR_DIRECTPAD_START, 2); + } + } + } + } + } +} + +void TControlCenter::CheckHydrantKpAction() +{ + int i,x; + TCanHeaderID aIde; + if(ieMsgLinkage.HydrantPadCount >0){ + if(ieMsgLinkage.HydrantPadNewActive){ + //Make Pump On + ieMsgLinkage.HydrantPadNewActive = 0; + ieMsgLinkage.HydrantPadCountOld = ieMsgLinkage.HydrantPadCount; + + for(i=0; i0){ + if(hydrantKpFbHasSend == 0){ + hydrantKpFbHasSend =1; + //Send Ack to Hudrant + tData[0] = 0; + InnerCan.OBufInsert(1, cmAckHydrantCommon, tData, 1); + } + }else{ + if(hydrantKpFbHasSend){ + hydrantKpFbHasSend =0; + //Send NotAck to Hudrant + tData[0] = 0; + InnerCan.OBufInsert(1, cmAckHydrantCancel, tData, 1); + } + } +} + + +void TControlCenter::Task1000Ms(void) +{ + PrcBroadcastAlternating(); + RelayTask(); + PortSyncTask(); + CheckPumpFeedBack(); + + if(IsSendResetToPad){ + KeyPad.SendResetCmd(); + IsSendResetToPad = 0; + }else + if(IsSendSelfCheckToPad){ + KeyPad.SendSelfCheckCmd(); + IsSendSelfCheckToPad =0; + }else + if(KeyPad.IsSendPowerSuplyCount){ + KeyPad.SendPowerSuplyCount(); + KeyPad.IsSendPowerSuplyCount =0; + }else{ + if(IsSelfChecking == 0){ + InspecTask(); + SelfCheckCountDown(); + ModuleInOutCountDown(); + CheckFeedBackMiss(); + CheckDelayStart(); + //Mute + if( (ieMsgFire.Count <1) && (ieMsgLinkage.Count <1) && + (ieMsgSv.Count <1) && (ieMsgFault.Count <1) ){ + IsMute =0; + IsMuteFire = 0; + IsMuteLnk= 0; + IsMuteSv= 0; + IsMuteFault= 0; + } + if(IsMute == 0xA5){ + TKeyPad::sKeyPadLedSetMute(&cState, FullOn); + }else{ + TKeyPad::sKeyPadLedSetMute(&cState, Off); + } + TKeyPad::sKeyPadLedSetBuz(&cState,static_cast(AlarmSoundWhat)); + //Fire + if(ieMsgFire.Count >0){ + TKeyPad::sKeyPadLedSetAlarm(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetAlarm(&cState,Off); + } + //Linkage + if(ieMsgLinkage.FbCount){ + TKeyPad::sKeyPadLedSetFeedBack(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetFeedBack(&cState,Off); + } + if(ieMsgLinkage.DelayCount){ + TKeyPad::sKeyPadLedSetStartDelay(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetStartDelay(&cState,Off); + } + + //Sv + if(ieMsgSv.Count >0){ + TKeyPad::sKeyPadLedSetSuperSv(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetSuperSv(&cState,Off); + } + //Fault + if(ieMsgFault.Count >0){ + TKeyPad::sKeyPadLedSetFault(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetFault(&cState,Off); + } + //Mask + if(ieMsgMask.Count >0){ + TKeyPad::sKeyPadLedSetMask(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetMask(&cState,Off); + } + + //Alram Start + if(ieMsgLinkage.VaCount>0){ + //Don't Care AlramVaOnOff + TKeyPad::sKeyPadLedSetAlarmStart(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetAlarmStart(&cState,Off); + } + + //Alram Fault + if(ieMsgFault.VaCount){ + TKeyPad::sKeyPadLedSetAlarmFault(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetAlarmFault(&cState,Off); + } + + //Load Allow State + if(AllowAuto){ + TKeyPad::sKeyPadLedSetAutoAllowState(&cState,1); + }else{ + TKeyPad::sKeyPadLedSetAutoAllowState(&cState,0); + } + + if(AllowManual){ + TKeyPad::sKeyPadLedSetManualAllowState(&cState,1); + }else{ + TKeyPad::sKeyPadLedSetManualAllowState(&cState,0); + } + + //Screen Save + if(GeneralDev.LcdScreenSaving){ + //TKeyPad::sKeyPadLedSetScreenSaveState(&cState,FullOn); + TKeyPad::sKeyPadLedSetScreenSaveState(&cState,Off); + }else{ + TKeyPad::sKeyPadLedSetScreenSaveState(&cState,Off); + } + + if(MainCtl.fData.Split.NetworkMode ==1){ + if(ieMsgLinkage.StartCount >0){ + if( (FeedBackMissCount) || (NwIsFbMiss) )TKeyPad::sKeyPadLedSetStart(&cState,Flicker); + else TKeyPad::sKeyPadLedSetStart(&cState,FullOn); + }else{ + if(ieMsgLinkage.SatrtHasBennActive) + TKeyPad::sKeyPadLedSetStart(&cState,Flicker); + else + TKeyPad::sKeyPadLedSetStart(&cState,Off); + } + + + if( ( IsSelfChecking ) || (NwIsSelfCheck) ){ + TKeyPad::sKeyPadLedSetSelfCheck(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetSelfCheck(&cState,Off); + } + + if( (CheckNormal.IsShowing) || (NwIsNormalCheck) ){ + TKeyPad::sKeyPadLedSetNormalCheck(&cState, FullOn); + }else{ + TKeyPad::sKeyPadLedSetNormalCheck(&cState, Off); + } + + //if( (IsStartDelay) || (NwIsStartDelay) ){ + if(ieMsgLinkage.DelayCount >0){ + TKeyPad::sKeyPadLedSetStartDelay(&cState, FullOn); + }else{ + TKeyPad::sKeyPadLedSetStartDelay(&cState, Off); + } + }else + if(MainCtl.fData.Split.NetworkMode ==2){ + if(ieMsgLinkage.StartCount >0){ + if(FeedBackMissCount)TKeyPad::sKeyPadLedSetStart(&cState,Flicker); + else TKeyPad::sKeyPadLedSetStart(&cState,FullOn); + }else{ + if(ieMsgLinkage.SatrtHasBennActive) + TKeyPad::sKeyPadLedSetStart(&cState,Flicker); + else + TKeyPad::sKeyPadLedSetStart(&cState,Off); + } + + if( IsSelfChecking ){ + TKeyPad::sKeyPadLedSetSelfCheck(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetSelfCheck(&cState,Off); + } + + if( (CheckNormal.IsShowing) ){ + TKeyPad::sKeyPadLedSetNormalCheck(&cState, FullOn); + }else{ + TKeyPad::sKeyPadLedSetNormalCheck(&cState, Off); + } + + //if( IsStartDelay ){ + if(ieMsgLinkage.DelayCount >0){ + TKeyPad::sKeyPadLedSetStartDelay(&cState, FullOn); + }else{ + TKeyPad::sKeyPadLedSetStartDelay(&cState, Off); + } + + if(FeedBackMissCount){ + if(KeyPad.FbMissCountOld == 0){ + ProtoC2C.SlaveReportFbMissCount(1); + KeyPad.FbMissCountOld = 1; + } + }else{ + if(KeyPad.FbMissCountOld){ + ProtoC2C.SlaveReportFbMissCount(0); + KeyPad.FbMissCountOld = 0; + } + } + }else{ + if(ieMsgLinkage.StartCount >0){ + if(FeedBackMissCount)TKeyPad::sKeyPadLedSetStart(&cState,Flicker); + else TKeyPad::sKeyPadLedSetStart(&cState,FullOn); + }else{ + if(ieMsgLinkage.SatrtHasBennActive) + TKeyPad::sKeyPadLedSetStart(&cState,Flicker); + else + TKeyPad::sKeyPadLedSetStart(&cState,Off); + } + + if( IsSelfChecking ){ + TKeyPad::sKeyPadLedSetSelfCheck(&cState,FullOn); + }else{ + TKeyPad::sKeyPadLedSetSelfCheck(&cState,Off); + } + + if( (CheckNormal.IsShowing) ){ + TKeyPad::sKeyPadLedSetNormalCheck(&cState, FullOn); + }else{ + TKeyPad::sKeyPadLedSetNormalCheck(&cState, Off); + } + + //if( IsStartDelay ){ + if(ieMsgLinkage.DelayCount >0){ + TKeyPad::sKeyPadLedSetStartDelay(&cState, FullOn); + }else{ + TKeyPad::sKeyPadLedSetStartDelay(&cState, Off); + } + + KeyPad.FbMissCountOld = FeedBackMissCount; + } + + KeyPad.SetLedStateViaInteger(cState.D32); + + } + } +} + + +void TControlCenter::Task10Ms(void) +{ + TaskDiplayPad(); + DisplayPadCheckToSend(); + DisplayPadGoSend(); +} + + + + + + + + + diff --git a/MyCode/src/ControlCenter.h b/MyCode/src/ControlCenter.h new file mode 100644 index 0000000..689c991 --- /dev/null +++ b/MyCode/src/ControlCenter.h @@ -0,0 +1,456 @@ +#ifndef CONTROLCENTER_H_ +#define CONTROLCENTER_H_ + +#include "gvalue.h" +#include "ProtoInnerCan.h" +#include "record.h" +#include "KeyPad.h" +#include "ProtoC2C.h" + +#define ieMSG_FIRE_MAX_COUNT 10000 +#define ieMSG_LINKAGE_MAX_COUNT 10000 +#define ieMSG_SV_MAX_COUNT 1000 +#define ieMSG_FAULT_MAX_COUNT 10000 +#define ieMSG_MASK_MAX_COUNT 10000 + +#define dLINK_INPUT_MAX_COUNT 6000 + +#define dAddrSdRam_MsgFire 0xC3C00000 +#define dAddrSdRam_MsgLinkage 0xC3C3C000 +#define dAddrSdRam_MsgSv 0xC3C78000 +#define dAddrSdRam_MsgFault 0xC3C7E000 +#define dAddrSdRam_MsgMask 0xC3CBA000 + +#define dAddrSdRam_DisplayPadBuf 0xC3900000 +#define dDiplayPadCtlBufMaxCount 100000 + +#define dDevFaultNormal 0x01 +#define dDevFaultCircuit 0x02 +#define dDevFaultBusPad 0x03 +#define dDevFaultDirectPad 0x04 +#define dDevFaultStroge 0x05 +#define dDevFaultExStroge 0x06 +#define dDevFaultPowerSuply 0x07 + +#define dDevFaultPowerSuplyComm 0x08 +#define dDevFaultPowerBk 0x09 +#define dDevFaultBat 0x0A +#define dDevFaultCommEth 0x0B +#define dDevFaultCommFNet 0x0C +#define dDevFaultCommGraphic 0x0D +#define dDevFaultSys 0x0E + +typedef enum{ + ioNone = 0, + io +}TInnerOperatingCode; + +/*typedef union{ + unsigned int D32[4]; + unsigned short D16[8]; + unsigned char D8[16]; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char iByte0; + unsigned char iByte1; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char mType; + unsigned char dType; + unsigned char Data0; + unsigned char Data1; + }Splite; +}TRecordCommon;*/ + +typedef union{ + unsigned int D32[6]; + unsigned char D8[24]; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char iByte0; + unsigned char State; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char mType; + unsigned char dType; + unsigned char Data0; + unsigned char Data1; + + unsigned int UserCode; + unsigned short AreaNum; + unsigned short DumpShort; + }Splite; +}TEventMsg; + + +typedef struct{ + int Count; + int WriteIndex; + int ReadIndex; + union{ + struct{ + unsigned char P0; + unsigned char P1; + unsigned char Dump0; + unsigned char Dump1; + int SourceInx; + }Body; + unsigned int D32[2]; + }BodyTmp; +}TDPOutputBuf; + +typedef struct{ + unsigned int Ava; + unsigned int Len; + unsigned char Content[32]; +}TPassWord; + + +class TControlCenter{ + public: + static const unsigned char LinkInputTypeFire = 1; + static const unsigned char LinkInputTypeSv = 2; + static const unsigned char LinkInputTypeHydrant = 3; + static const unsigned char LinkInputTypeAvaEdge = 10; + static const unsigned char LinkInputTypeFireSimulate =11; + static const unsigned char LinkInputTypeSvSimulate = 12; + static const unsigned char LinkInputTypeHydrantSimulate = 13; + + + static const unsigned char StartTypeSimulate = 1; + + unsigned int ieIsNeedMsgSVCheckCancle; + unsigned int IsMsgSVOldestOverride; + + short ieRearrangeIndexSv; + short ieIndexMsgSVOldest; + + short ieIndexMsgSV; + short ieIndexMsgFault; + short ieIndexMsgStart; + short ieIndexMsgFeedBack; + + unsigned int FeedBackMissCount; + + unsigned int IsMsgReseting; + + unsigned int ieGot; + unsigned int SysFreeTick1Ms; + unsigned int BatShowOrder; + + TSys_State_Struct cState; + + struct{ + int Count; + int ActualCount; + unsigned int Lock; + unsigned int RequestRead; + int WriteIndex; + int ReflashIndex; + unsigned int isMore; + }ieMsgFire; + struct{ + int SatrtHasBennActive; + int StartCount; + int MissingCount; + int FbCount; + int PumpFbCount; + int PumpFbLocalCount; + int VaCount; + int VaCountOld; + int BroadcastCount; + int BroadcastCountOld; + int IsBroadcastAndVa; + int Count; + int HydrantPadCount; + int HydrantPadCountOld; + int HydrantPadNewActive; + int DelayCount; + int DelayCountOld; + int StopCount; + unsigned int SdAddr; + unsigned int Lock; + unsigned int RequestRead; + int ReflashIndex; + unsigned int isMore; + }ieMsgLinkage; + struct{ + int Count; + TEventMsg Body[ieMSG_SV_MAX_COUNT]; + unsigned int Lock; + unsigned int RequestRead; + int ReflashIndex; + }ieMsgSv; + struct{ + int Count; + int VaCount; + unsigned int SdAddr; + unsigned int Lock; + unsigned int RequestRead; + int ReflashIndex; + }ieMsgFault; + struct{ + int Count; + unsigned int Lock; + unsigned int RequestRead; + int ReflashIndex; + unsigned int isMore; + }ieMsgMask; + + TRecordMaskMsg MaskMsg; + TRecordCommon aImForceConvert; + + TEventMsg MsgReadTmp; + //TInnerEventMsg MsgWriteTmp; + TEventMsg MsgExtGet; + + + int BufFireCount; + int BufLinkageCount; + int BufSvCount; + int BufFaultCount; + unsigned char IsSendResetToPad; + unsigned char IsSendSelfCheckToPad; + + union{ + unsigned char D8[256]; + unsigned int D32[64]; + }ReadWriteData; + + int DisplayPadPrcFireIndex; + TDPOutputBuf DisplayPadBuf; + TEventMsg DisplayPadMsg; + struct{ + unsigned char CtlNum; + unsigned char P0; + unsigned char P1; + unsigned char dType; + }DisplayPadTriggerSource; + struct{ + unsigned char P0; + unsigned char P1; + }DisplayPadPath; + TDMix DisplayDayTime; + TDMix DisplayYearMonth; + unsigned char tData[8]; + unsigned int DisplaySendingWhat; + + unsigned int InspecTick; + unsigned char OnlineBusPadCount; + unsigned char OnlineBusPad[dHANDCTL_MAX_COUNT]; + unsigned char OnlineDirectPadCount; + unsigned char OnlineDirectPad[dHANDCTL_MAX_COUNT]; + unsigned char hydrantKpFbHasSend; + + TC2CBufBody NetSendBuf; + union{ + unsigned int D32[8]; + unsigned char D8[32]; + }DescpBuf; + + TPassWord PassWordII; + TPassWord PassWordIII; + TPassWord PassWordTemp; + + unsigned int PsBatUpDateTick; + + struct { + unsigned int Count; + unsigned int uCode[dLINK_INPUT_MAX_COUNT]; + unsigned short AreaNum[dLINK_INPUT_MAX_COUNT]; + unsigned char dType[dLINK_INPUT_MAX_COUNT]; + unsigned char AssignType[dLINK_INPUT_MAX_COUNT]; + unsigned char eType[dLINK_INPUT_MAX_COUNT]; + }FiredUserCode; + unsigned int CrcMask; + struct{ + unsigned char Mask; + unsigned char Dump0; + unsigned char Dump1; + unsigned char Dump2; + void Clear(){ + Mask =0; + Dump0 =0; + Dump1 =0; + Dump2 =0; + } + }CrcFlag; + public: + TControlCenter(){CrcFlag.Clear();} + void Init(); + void MsgReset(); + void DelayMs(unsigned int aMs); + + void FireGetViaPath(unsigned int aIndex); + void FireMsgClearOne(unsigned int aIndex); + void FireMsgCopyOne(unsigned int aIndex); + void FireMsgExtGet(unsigned int aIndex); + static void sFireGetViaIndex(unsigned int aIndex, TEventMsg *aMsg); + + void iePushOneMsgFire(TRecordCommon aIm, unsigned int auC); + int iePushOneMsgFireSimulate(TRecordCommon aIm, unsigned int auC); + + void LinkageGetViaPath(unsigned int aIndex); + void LinkageMsgClearOne(unsigned int aIndex); + void LinkageMsgCopyOne(unsigned int aIndex); + void LinkageMsgExtGet(unsigned int aIndex); + static void sLinkageGetViaIndex(unsigned int aIndex, TEventMsg *aMsg); + + void SvGetViaPath(unsigned int aIndex); + void SvMsgClearOne(unsigned int aIndex); + void SvMsgCopyOne(unsigned int aIndex); + void SvMsgExtGet(unsigned int aIndex); + static void sSvGetViaIndex(unsigned int aIndex, TEventMsg *aMsg); + + void FaultGetViaPath(unsigned int aIndex); + void FaultMsgClearOne(unsigned int aIndex); + void FaultMsgCopyOne(unsigned int aIndex); + void FaultMsgExtGet(unsigned int aIndex); + static void sFaultGetViaIndex(unsigned int aIndex, TEventMsg *aMsg); + + static void sMaskGetViaIndex(unsigned int aIndex, TEventMsg *aMsg); + + void LoadCurrentDateTime2RecordCommon(TRecordCommon *pIm); + void iePushOneMsgLinkageStart (TRecordCommon aIm); + void iePushOneMsgLinkageStartCancel (TRecordCommon aIm); + void iePushOneMsgLinkageFb (TRecordCommon aIm); + void iePushOneMsgLinkageFbCancel (TRecordCommon aIm); + + void ieManualPushOneMsgLinkageStart (TRecordCommon aIm); + void ieManualPushOneMsgLinkageStartCancel (TRecordCommon aIm); + void ieManualPushOneMsgLinkageFb (TRecordCommon aIm); + void ieManualPushOneMsgLinkageFbCancel (TRecordCommon aIm); + + int iePushOneMsgLinkageStartSimulate(TRecordCommon aIm); + int iePushOneMsgLinkageStartCancelSimulate(TRecordCommon aIm); + int iePushOneMsgLinkageFbSimulate(TRecordCommon aIm); + + void ieMsgLinkageStartDelayUpdate(unsigned int aFullPath, unsigned char aNewTime); + + void iePushOneMsgFault(TRecordCommon aIm); + void iePushOneMsgFaultCancel(TRecordCommon aIm); + + unsigned int ieFireMsgConfAddr(unsigned int FullPath); + void ieLinkageMsgStartConfAddr(unsigned int FullPath); + void ieLinkageMsgFbConfAddr(unsigned int FullPath); + unsigned int ieFaultMsgFaultConfAddr(unsigned int FullPath); + + void iePushOneMsgSv(TRecordCommon aIm); + void iePushOneMsgSvCancel(TRecordCommon aIm); + int iePushOneMsgSvSimulate(TRecordCommon aIm); + + void iePushOneMsgMask (TRecordCommon aIm); + void iePushOneMsgMaskCancel (TRecordCommon aIm); + + void iePushOneMsg(TRecordCommon aIm, unsigned char aCmd); + void iePushOneRecord(TRecordCommon aIm, unsigned char aCmd); + + void ieManageMsgFire(void); + void ieManageMsgSv(void); + void PushInspecRpy(unsigned char Path0, unsigned char Prm); + + void DeviceRequest(unsigned char aCmd, unsigned char aReq, unsigned char aPrm); + + void InspecDataCheck(); + void InspecTask(); + void TaskFreeRun(void); + void Task1000Ms(void); + void Task10Ms(void); + + void ieAddDevFault(unsigned char aDevFaultType, unsigned char DevIndex); + void ieAddDevFaultCancel(unsigned char aDevFaultType, unsigned char DevIndex); + void ieAddPadFault(unsigned char aP0, unsigned char aDevFaultType); + void ieAddPadFaultCancel(unsigned char aP0, unsigned char aDevFaultType); + void ieAddBrdFault(unsigned char aP1, unsigned char aDevFaultType); + void ieAddBrdFaultCancel(unsigned char aP1, unsigned char aDevFaultType); + void ieAddBrdFaultLinkageStorage(unsigned short aInx); + void ieAddBrdFaultCancelLinkageStorage(unsigned short aInx); + + void LoadOneFbMiss(); + + void FireGet4DisplayPadViaIndex(unsigned int aIndex); + int DipalayPadSendPathType(); + int DipalayPadSendYearMonth(); + int DipalayPadSendDayTime(); + void DisplayPadCheckCircuit(int Ord); + void DisplayPadCheckByIndex(); + void DisplayPadGoSend(); + void DisplayPadCheckToSend(); + void TaskDiplayPad(); + + void CheckBatUpdate(); + void ModuleInOutCountDown(); + void CheckFeedBackMiss(); + void CheckDelayStart(); + + void CheckHydrantKpAction(); + void CheckHydrantKpActionForce(); + void CheckPumpFeedBack(); + + void WaitChipIdle(unsigned int ChipX); + void MaskCountSet(int aCnt); + + int PassWordII_ReadWrite(int IsRead, TPassWord *pPsw); + int PassWordIII_ReadWrite(int IsRead, TPassWord *pPsw); + + void NwMachineStateClear(unsigned int aCtlNum); + void NwMachineMsgFireClear(unsigned int aCtlNum); + void NwMachineMsgLinkageClear(unsigned int aCtlNum); + void NwMachineMsgSvClear(unsigned int aCtlNum); + void NwMachineMsgFaultClear(unsigned int aCtlNum); + + void CheckSoundFire(); + void CheckSoundLinkage(); + void CheckSoundSv(); + void CheckSoundFault(); + + void SingleCtlModeSendMaskInf2Crt(); + + void BroadcastAlternatingUpdate(); + void PrcBroadcastAlternating(); + + void FireTurnOnVa(void); + + static void sSimFireGot(TRecordCommon *aRc); + static void sSimStartGot(TRecordCommon *aRc); + static void sSimStartCancelGot(TRecordCommon *aRc); + static void sSimSvGot(TRecordCommon *aRc); + static void sSimFeedBackGot(TRecordCommon *aRc); + + void RelaySetFireOnOff(unsigned char IsOnOff); + void RelaySetFaultOnOff(unsigned char IsOnOff); + void RelayTask(); + + void ProcPortSyncCmd(unsigned char aCmd, unsigned char aP0, unsigned char AnAck); + void PortSyncTask(); + + void Task1Ms(void); +}; + + +#endif + + + + + diff --git a/MyCode/src/ControlCenterII.cpp b/MyCode/src/ControlCenterII.cpp new file mode 100644 index 0000000..d51da02 --- /dev/null +++ b/MyCode/src/ControlCenterII.cpp @@ -0,0 +1,896 @@ +#include "ControlCenter.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "record.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "fdcan_task.h" + #include "relay_task.h" + #include "uart_key_drv.h" +} + +void TControlCenter::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick ieMSG_FIRE_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.Splite.PCtlNum == aCtlNum ){ + FireMsgClearOne(i); + if(FirstNullIndex > ieMSG_FIRE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_FIRE_MAX_COUNT){ + FireMsgCopyOne(FirstNullIndex); + FireMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + } + } + + ieMsgFire.Count = Cnt; + ieMsgFire.WriteIndex = Cnt; + ieMsgFire.ReflashIndex++; + + ieMsgFire.Lock = 0; + + if(IsMute == 0){ + if(ieMsgFire.Count == 0){ + if( (ieMsgLinkage.Count > 0) && (AlarmSoundWhat > 0) ){ + if(IsMuteLnk == 0)AlarmSoundWhat = 1; + } + if( (ieMsgSv.Count > 0) && (AlarmSoundWhat > 1) ){ + if(IsMuteSv == 0)AlarmSoundWhat = 2; + } + if( (ieMsgFault.Count > 0) && (AlarmSoundWhat > 2) ){ + if(IsMuteFault == 0)AlarmSoundWhat = 3; + } + } + } + + ieGot = 1; +} + + +void TControlCenter::NwMachineMsgLinkageClear(unsigned int aCtlNum) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aStartCount, aFbCount, aMsCount, aVaCount, aHP; + unsigned char aP0, aP1, EpSta; + int aDelayCount, aStopCount; + + if( (aCtlNum == 0) || (aCtlNum == MainCtl.fData.Split.MyNum) )return; + + ieMsgLinkage.RequestRead =0; + ieMsgLinkage.Lock = 1; + Cnt = 0; + i =0; + + FirstNullIndex = ieMSG_LINKAGE_MAX_COUNT +1000; + Cnt = 0; + aStartCount = 0; + aFbCount = 0; + aMsCount = 0; + aVaCount = 0; + aHP =0; + aDelayCount = 0; + aStopCount = 0; + + for(i=0; i ieMSG_LINKAGE_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.Splite.PCtlNum == aCtlNum ){ + LinkageMsgClearOne(i); + if(FirstNullIndex > ieMSG_LINKAGE_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_LINKAGE_MAX_COUNT){ + LinkageMsgCopyOne(FirstNullIndex); + LinkageMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.mType == etLinkageStart){ + if( (MsgReadTmp.Splite.Data0 != static_cast(0x09)) && (MsgReadTmp.Splite.Data0 != static_cast(0x0A))) aStartCount++; + + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + //if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + //} + }else + if(MsgReadTmp.Splite.dType == dgTYPE_FIRE_HydrantKp){ + aHP++; + } + if(MsgReadTmp.Splite.Data0 == static_cast(0x0A)){ + aDelayCount++; + }else + if(MsgReadTmp.Splite.Data0 == static_cast(0x09)){ + aStopCount++; + } + }else + if(MsgReadTmp.Splite.mType == etLinkageFeedBack){ + aFbCount ++; + if(MsgReadTmp.Splite.Data0 == 0x04){ + aMsCount++; + } + } + } + } + + ieMsgLinkage.Count = Cnt; + ieMsgLinkage.StartCount = aStartCount; + ieMsgLinkage.FbCount = aFbCount; + ieMsgLinkage.MissingCount = aMsCount; + ieMsgLinkage.VaCount = aVaCount; + ieMsgLinkage.HydrantPadCount = aHP; + ieMsgLinkage.DelayCount = aDelayCount; + ieMsgLinkage.StopCount = aStopCount; + ieMsgLinkage.ReflashIndex++; + + ieMsgLinkage.Lock = 0; + + if(IsMute == 0){ + if(ieMsgLinkage.Count == 0){ + if( (ieMsgSv.Count > 0) && (AlarmSoundWhat > 1) ){ + if(IsMuteSv == 0)AlarmSoundWhat = 2; + } + if( (ieMsgFault.Count > 0) && (AlarmSoundWhat > 2) ){ + if(IsMuteFault == 0)AlarmSoundWhat = 3; + } + } + } + + ieGot = 1; +} + +void TControlCenter::NwMachineMsgSvClear(unsigned int aCtlNum) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aVaCount; + unsigned char aP0, aP1, EpSta; + + if( (aCtlNum == 0) || (aCtlNum == MainCtl.fData.Split.MyNum) )return; + + ieMsgSv.RequestRead =0; + ieMsgSv.Lock = 1; + + FirstNullIndex = ieMSG_SV_MAX_COUNT +1000; + Cnt = 0; + aVaCount = 0; + for(i=0; i ieMSG_SV_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.Splite.PCtlNum == aCtlNum){ + SvMsgClearOne(i); + if(FirstNullIndex > ieMSG_SV_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_SV_MAX_COUNT){ + SvMsgCopyOne(FirstNullIndex); + SvMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + } + } + + ieMsgSv.Count = Cnt; + ieMsgSv.ReflashIndex++; + ieMsgSv.Lock = 0; + + if(IsMute == 0){ + if(ieMsgSv.Count == 0){ + if( (ieMsgFault.Count > 0) && (AlarmSoundWhat > 2) ){ + if(IsMuteFault == 0)AlarmSoundWhat = 3; + } + } + } + + ieGot = 1; +} + + + +void TControlCenter::NwMachineMsgFaultClear(unsigned int aCtlNum) +{ + int i,Cnt, FirstNullIndex, WritePst; + int aVaCount; + unsigned char aP0, aP1, EpSta; + + if( (aCtlNum == 0) || (aCtlNum == MainCtl.fData.Split.MyNum) )return; + + ieMsgFault.RequestRead =0; + ieMsgFault.Lock = 1; + + FirstNullIndex = ieMSG_FAULT_MAX_COUNT +1000; + Cnt = 0; + aVaCount = 0; + for(i=0; i ieMSG_FAULT_MAX_COUNT)FirstNullIndex = i; + }else + if( MsgReadTmp.Splite.PCtlNum == aCtlNum){ + FaultMsgClearOne(i); + if(FirstNullIndex > ieMSG_FAULT_MAX_COUNT){ + FirstNullIndex = i; + } + }else{ + if(FirstNullIndex < ieMSG_FAULT_MAX_COUNT){ + FaultMsgCopyOne(FirstNullIndex); + FaultMsgClearOne(i); + FirstNullIndex++; + } + Cnt++; + if(MsgReadTmp.Splite.dType == dgType_VAALRAM){ + if( (MsgReadTmp.Splite.P0 >0 ) && (MsgReadTmp.Splite.P0 <= dPORT_MAX_COUNT) ) { + aVaCount++; + } + } + } + } + + ieMsgFault.Count = Cnt; + ieMsgFault.VaCount = aVaCount; + ieMsgFault.ReflashIndex++; + ieMsgFault.Lock = 0; + + if( (ieMsgFault.Count == 0) && (AlarmSoundWhat > 2) ){ + AlarmSoundWhat = 0x07; + } + + ieGot = 1; +} + +int TControlCenter::PassWordII_ReadWrite(int IsRead, TPassWord *pPsw) +{ + unsigned int aAddr, CheckOk; + volatile unsigned int aWait; + int i; + //Read ExistTable + aAddr = dEepAddrPassWordII; + CheckOk = 1; + if(IsRead){ + DelayMs(10); + eeprom_read_byte(0, aAddr, PassWordTemp.Content, 16); + DelayMs(10); + for(i=0;i<16;i++){ + if( (PassWordTemp.Content[i] < '0') || (PassWordTemp.Content[i] > '9') ){ + break; + } + } + if( (i<6)|| (i > 12) )CheckOk = 0; + else PassWordTemp.Len = i; + if(CheckOk){ + PassWordII.Len = PassWordTemp.Len; + PassWordII.Ava = 1; + for(i=0;iContent, 16); + DelayMs(10); + aAddr = dEepAddrPassWordII; + DelayMs(10); + eeprom_read_byte(0, aAddr, PassWordTemp.Content, 16); + DelayMs(10); + CheckOk = 1; + for(i=0;i<16;i++){ + if( PassWordTemp.Content[i] != pPsw->Content[i]){ + CheckOk = 0; + } + } + if(CheckOk){ + for(i=0;i<16;i++){ + if( (PassWordTemp.Content[i] < '0') || (PassWordTemp.Content[i] > '9') ){ + CheckOk = 0; + } + } + PassWordTemp.Len = i; + PassWordII.Len = PassWordTemp.Len; + PassWordII.Ava = 1; + for(i=0;i '9') ){ + break; + } + } + if( (i<6)|| (i > 12) )CheckOk = 0; + else PassWordTemp.Len = i; + if(CheckOk){ + PassWordIII.Len = PassWordTemp.Len; + PassWordIII.Ava = 1; + for(i=0;iContent, 16); + DelayMs(10); + aAddr = dEepAddrPassWordIII; + DelayMs(10); + eeprom_read_byte(0, aAddr, PassWordTemp.Content, 16); + DelayMs(10); + CheckOk = 1; + for(i=0;i<16;i++){ + if( PassWordTemp.Content[i] != pPsw->Content[i]){ + CheckOk = 0; + } + } + if(CheckOk){ + for(i=0;i<16;i++){ + if( (PassWordTemp.Content[i] < '0') || (PassWordTemp.Content[i] > '9') ){ + CheckOk = 0; + } + } + PassWordTemp.Len = i; + PassWordIII.Len = PassWordTemp.Len; + PassWordIII.Ava = 1; + for(i=0;idLinkageOutputBufMaxCOunt)return; + aP0 = aInx % 256; + aDevFaultType = (aInx / 256) + static_cast(TBoardFaultType::StorageLinkExpressionPart1); + + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.mType = CmdActiveDefaultSet[cmOtherErr][7]; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + aIm.Splite.P0 = 0xE0; //Board Idf + aIm.Splite.P1 = aP0; + aIm.Splite.P2 = aDevFaultType; //Fault Type + aIm.Splite.dType = 0; + aIm.Splite.Data0 = aDevFaultType; //Fault Type + aIm.Splite.Data1 = 0xF1;//Is Set=1 Recover=0 + aIm.Splite.iByte0 = CmdActiveDefaultSet[cmOtherErr][8]; + + iePushOneMsgFault(aIm); + Record.FaultAdd(aIm); + + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.oBufMsgInsertFault(aIm, cmOtherErr); +} + +void TControlCenter::ieAddBrdFaultCancelLinkageStorage(unsigned short aInx) +{ + unsigned char aP0; + unsigned char aDevFaultType; + TRecordCommon aIm; + + if(aInx ==0)return; + if(aInx>dLinkageOutputBufMaxCOunt)return; + aP0 = aInx % 256; + aDevFaultType = (aInx / 256) + static_cast(TBoardFaultType::StorageLinkExpressionPart1); + + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.mType = CmdActiveDefaultSet[cmOtherErr][7]; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + aIm.Splite.P0 = 0xE0; //Board Index + aIm.Splite.P1 = aP0; + aIm.Splite.P2 = aDevFaultType; //Fault Type + aIm.Splite.dType = 0; + aIm.Splite.Data0 = aDevFaultType; //Fault Type + aIm.Splite.Data1 = 0xF0;//Is Set=1 Recover=0 + aIm.Splite.iByte0 = CmdActiveDefaultSet[cmOtherErr][8]; + + iePushOneMsgFaultCancel(aIm); + Record.FaultAdd(aIm); + + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.oBufMsgInsertFault(aIm, cmOtherErr); +} + +void TControlCenter::CheckSoundFire() +{ + if(IsMute == 0){ + if( (ieMsgFire.Count == 0) && (AlarmSoundWhat ==0) ){ + if( (ieMsgLinkage.Count > 0) && (IsMuteLnk == 0)){ + AlarmSoundWhat = 1; + }else + if( (ieMsgSv.Count > 0) && (IsMuteSv == 0) ){ + AlarmSoundWhat = 2; + }else + if( (ieMsgFault.Count > 0) && (IsMuteFault == 0) ){ + AlarmSoundWhat = 3; + }else{ + AlarmSoundWhat = 7; + } + } + } +} + +void TControlCenter::CheckSoundLinkage() +{ + if(IsMute == 0){ + if( (ieMsgLinkage.Count == 0) && (AlarmSoundWhat >0) ){ + if( (ieMsgSv.Count > 0) && (IsMuteSv == 0) ){ + AlarmSoundWhat = 2; + }else + if( (ieMsgFault.Count > 0) && (IsMuteFault == 0) ){ + AlarmSoundWhat = 3; + }else{ + AlarmSoundWhat = 7; + } + } + } +} + +void TControlCenter::CheckSoundSv() +{ + if(IsMute == 0){ + if( (ieMsgSv.Count == 0) && (AlarmSoundWhat >1) ){ + if( (ieMsgFault.Count > 0) && (IsMuteFault == 0) ){ + AlarmSoundWhat = 3; + }else{ + AlarmSoundWhat = 7; + } + } + } +} + +void TControlCenter::CheckSoundFault() +{ + if(IsMute == 0){ + if( (ieMsgFault.Count == 0) && (AlarmSoundWhat >2) ){ + AlarmSoundWhat = 7; + } + } +} + +void TControlCenter::sFireGetViaIndex(unsigned int aIndex, TEventMsg *aMsg) +{ + unsigned int AddrSd = dAddrSdRam_MsgFire + (aIndex * 24); + aMsg->D32[0] = *(volatile unsigned int*)(AddrSd); + aMsg->D32[1] = *(volatile unsigned int*)(AddrSd + 4); + aMsg->D32[2] = *(volatile unsigned int*)(AddrSd + 8); + aMsg->D32[3] = *(volatile unsigned int*)(AddrSd + 12); + aMsg->D32[4] = *(volatile unsigned int*)(AddrSd + 16); + aMsg->D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::sLinkageGetViaIndex(unsigned int aIndex, TEventMsg *aMsg) +{ + unsigned int AddrSd = dAddrSdRam_MsgLinkage + (aIndex * 24); + aMsg->D32[0] = *(volatile unsigned int*)(AddrSd); + aMsg->D32[1] = *(volatile unsigned int*)(AddrSd + 4); + aMsg->D32[2] = *(volatile unsigned int*)(AddrSd + 8); + aMsg->D32[3] = *(volatile unsigned int*)(AddrSd + 12); + aMsg->D32[4] = *(volatile unsigned int*)(AddrSd + 16); + aMsg->D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::sSvGetViaIndex(unsigned int aIndex, TEventMsg *aMsg) +{ + unsigned int AddrSd = dAddrSdRam_MsgSv + (aIndex * 24); + aMsg->D32[0] = *(volatile unsigned int*)(AddrSd); + aMsg->D32[1] = *(volatile unsigned int*)(AddrSd + 4); + aMsg->D32[2] = *(volatile unsigned int*)(AddrSd + 8); + aMsg->D32[3] = *(volatile unsigned int*)(AddrSd + 12); + aMsg->D32[4] = *(volatile unsigned int*)(AddrSd + 16); + aMsg->D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::sFaultGetViaIndex(unsigned int aIndex, TEventMsg *aMsg) +{ + unsigned int AddrSd = dAddrSdRam_MsgFault + (aIndex * 24); + aMsg->D32[0] = *(volatile unsigned int*)(AddrSd); + aMsg->D32[1] = *(volatile unsigned int*)(AddrSd + 4); + aMsg->D32[2] = *(volatile unsigned int*)(AddrSd + 8); + aMsg->D32[3] = *(volatile unsigned int*)(AddrSd + 12); + aMsg->D32[4] = *(volatile unsigned int*)(AddrSd + 16); + aMsg->D32[5] = *(volatile unsigned int*)(AddrSd + 20); +} + +void TControlCenter::sMaskGetViaIndex(unsigned int aIndex, TEventMsg *aMsg) +{ + unsigned int sAddr = dAddrSdRam_MsgMask + aIndex *24; + aMsg->D32[0] = *(volatile unsigned int *)(sAddr + 0); + aMsg->D32[1] = *(volatile unsigned int *)(sAddr + 4); + aMsg->D32[2] = *(volatile unsigned int *)(sAddr + 8); + aMsg->D32[3] = *(volatile unsigned int *)(sAddr + 12); + aMsg->D32[4] = *(volatile unsigned int *)(sAddr + 16); + aMsg->D32[5] = *(volatile unsigned int *)(sAddr + 20); +} + +void TControlCenter::BroadcastAlternatingUpdate() +{ + if(Broadcast.SyncMode){ + if( (ieMsgLinkage.BroadcastCount) && (ieMsgLinkage.VaCount) ){ + if(ieMsgLinkage.IsBroadcastAndVa == 0){ + if(ieMsgLinkage.BroadcastCountOld == 0){ + BroadcastAlramAlternating.InBroadcast =1; + BroadcastAlramAlternating.Tick =0; + InnerCan.SendCmdBroadcastFast(1); + }else{ + BroadcastAlramAlternating.InBroadcast =0; + BroadcastAlramAlternating.Tick =0; + InnerCan.SendCmdBroadcastFast(0); + } + ieMsgLinkage.IsBroadcastAndVa = 1; + } + }else{ + if(ieMsgLinkage.IsBroadcastAndVa){ + InnerCan.SendCmdBroadcastFast(2); + ieMsgLinkage.IsBroadcastAndVa = 0; + } + } + ieMsgLinkage.VaCountOld = ieMsgLinkage.VaCount; + ieMsgLinkage.BroadcastCountOld = ieMsgLinkage.BroadcastCount; + } +} + +void TControlCenter::PrcBroadcastAlternating() +{ + //SyncMode == 0 并行 + if(Broadcast.SyncMode){ + if(ieMsgLinkage.IsBroadcastAndVa){ + if(BroadcastAlramAlternating.InBroadcast){ + BroadcastAlramAlternating.Tick++; + if(BroadcastAlramAlternating.Tick > Broadcast.BroadcastTime){ + BroadcastAlramAlternating.InBroadcast =0; + BroadcastAlramAlternating.Tick =0; + InnerCan.SendCmdBroadcastFast(0); + } + }else{ + BroadcastAlramAlternating.Tick++; + if(BroadcastAlramAlternating.Tick > Broadcast.VaTime){ + BroadcastAlramAlternating.InBroadcast =1; + BroadcastAlramAlternating.Tick =0; + InnerCan.SendCmdBroadcastFast(1); + } + } + } + } +} + +void TControlCenter::sSimFireGot(TRecordCommon *aRc) +{ + if(Register.IsDevRegisting != 0x00A5A5A5){ + aRc->Splite.P2 = 0; + if(CtlCenter.ieMsgFire.Count <1)aRc->Splite.Data1 = 1; + else aRc->Splite.Data1 = 0; + + aRc->Splite.Data0 = TControlCenter::LinkInputTypeFireSimulate; + + if(CtlCenter.IsMsgReseting == 0){ + if(CtlCenter.iePushOneMsgFireSimulate(*aRc,0)){ + Record.FireAdd(*aRc); + } + } + } +} + +void TControlCenter::sSimStartGot(TRecordCommon *aRc) +{ + if(Register.IsDevRegisting != 0x00A5A5A5){ + aRc->Splite.mType = etLinkageStart; + aRc->Splite.iByte0 = 0x01; + aRc->Splite.P2 = 0; + if(CtlCenter.iePushOneMsgLinkageStartSimulate(*aRc)){ + aRc->Splite.Data1 = StartTypeSimulate; + Record.LinkageAdd(*aRc); + //this will been call in InterLink Running, so send to Master + ProtoC2C.SlaveDoSend2MasterMachine(*aRc, cmVIrtualStart, TProtoC2C::mtLink); + } + } +} + +void TControlCenter::sSimStartCancelGot(TRecordCommon *aRc) +{ + if(Register.IsDevRegisting != 0x00A5A5A5){ + aRc->Splite.P2 = 0; + aRc->Splite.mType = etLinkageStartCancel; + if(CtlCenter.iePushOneMsgLinkageStartCancelSimulate(*aRc)){ + //Record.LinkageAdd(*aRc); + //this will been call in InterLink Running, so send to Master + ProtoC2C.SlaveDoSend2MasterMachine(*aRc, smVIrtualStop, TProtoC2C::mtLink); + } + } +} + +void TControlCenter::sSimSvGot(TRecordCommon *aRc) +{ + if(Register.IsDevRegisting != 0x00A5A5A5){ + aRc->Splite.P2 = 0; + if(CtlCenter.iePushOneMsgSvSimulate(*aRc)){ + Record.SvAdd(*aRc); + } + } +} + +void TControlCenter::sSimFeedBackGot(TRecordCommon *aRc) +{ + if(Register.IsDevRegisting != 0x00A5A5A5){ + aRc->Splite.P2 = 0; + aRc->Splite.mType = etLinkageFeedBack; + aRc->Splite.iByte0 = 0x03; + if(CtlCenter.iePushOneMsgLinkageFbSimulate(*aRc)){ + aRc->Splite.Data1 = StartTypeSimulate; + Record.LinkageAdd(*aRc); + } + } +} + +void TControlCenter::RelaySetFireOnOff(unsigned char IsOnOff) +{ + set_Relay_alarm_state(IsOnOff); +} + +void TControlCenter::RelaySetFaultOnOff(unsigned char IsOnOff) +{ + set_Relay_fault_state(IsOnOff); +} + +void TControlCenter::RelayTask() +{ + if(ieMsgFire.ActualCount >0){ + RelaySetFireOnOff(1); + }else{ + RelaySetFireOnOff(0); + } + if(ieMsgFault.Count >0){ + RelaySetFaultOnOff(1); + }else{ + RelaySetFaultOnOff(0); + } +} + +void TControlCenter::ProcPortSyncCmd(unsigned char aCmd, unsigned char aP0, unsigned char AnAck) +{ + //cmBusDataSyncRegisterReq, + //cmBusDataSyncRegister, + //cmBusDataSyncRegisterRes, + //cmBusDataSyncIsolationReq, + //cmBusDataSyncIsolation, + //cmBusDataSyncIsolationRes, + unsigned char tP0; + TPort *pPort; + + if(StartUpCompleted == 0)return; + if(aP0 == 0)return; + if(aP0 >dPORT_MAX_COUNT)return; + + tP0 = aP0-1; + pPort = &Port[tP0]; + pPort->Num = aP0; + if(aCmd == cmBusDataSyncRegisterReq){ + if(AnAck == 1){ + //Req Start + TPort::sRpyRegDataSyncReqStart(pPort); + }else + if(AnAck == 3){ + //Start to Send Data + TPort::sSendRegDataSync(pPort); + } + }else + if(aCmd == cmBusDataSyncRegisterRes){ + //Got Result + unsigned char tP0 = aP0-1; + if(AnAck == 0){ + Port[tP0].SyncRegisterResult = 2; + }else + if(AnAck ==1){ + Port[tP0].SyncRegisterResult = 1; + } + }else + if(aCmd == cmBusDataSyncIsolationReq){ + if(AnAck == 1){ + //Req Start + TPort::sRpyMaskDataSyncReqStart(pPort); + }else + if(AnAck == 3){ + //Start to Send Data + TPort::sSnedMaskDataSync(pPort); + } + }else + if(aCmd == cmBusDataSyncIsolationRes){ + //Got Result + unsigned char tP0 = aP0-1; + if(AnAck == 0){ + Port[tP0].SyncMaskResult = 2; + }else + if(AnAck ==1){ + Port[tP0].SyncMaskResult = 1; + } + } +} + +void TControlCenter::PortSyncTask() +{ + int i; + for(i=0; iClear(); + Str1->Clear(); + Str2->Clear(); + + Str0->AddOn6Dg(fData.Common.UserCode); + Str1->AddOn3Dg(fData.Common.Id); + Str2->FromStr(StrType[fData.Common.dType]); +} + +void TRootDevice::PrintAttribute(TMyString *Str0, TMyString *Str1) +{ + Str0->FromUInt3Dg(fData.Port.ResistedCount); + Str1->FromUInt4Dg(fData.Port.Ver); +} + +void TRootDevice::PrintDynamicsData(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5, TMyString *Str6, TMyString *Str7) +{ + switch(fData.Common.dType){ + case dgTYPE_PORT: + Str0->FromUInt4Dg(fData.Port.Voltage); + Str1->FromUInt4Dg(fData.Port.Current); + Str2->FromUInt3Dg(fData.Port.OnlineCount); + Str3->FromUInt3Dg(fData.Port.Tempe); + break; + case dgTYPE_HAND_CTL: + Str0->FromUInt4Dg(fData.HandCtl.Voltage); + Str1->FromUInt4Dg(fData.HandCtl.Current); + Str2->FromUInt3Dg(fData.HandCtl.OnlineCount); + Str3->FromUInt3Dg(fData.HandCtl.Tempe); + break; + case dgTYPE_DIRECT_CTL: + Str0->FromUInt4Dg(fData.DirectCtl.Voltage); + Str1->FromUInt4Dg(fData.DirectCtl.Current); + Str2->FromUInt3Dg(fData.DirectCtl.OnlineCount); + Str3->FromUInt3Dg(fData.DirectCtl.Tempe); + break; + case dgTYPE_COMM_CAN: + Str0->FromUInt4Dg(fData.CommBoard.iLinkSpeed); + Str0->AddOnStr(cK); + Str1->FromUInt4Dg(fData.CommBoard.oLinkSpeed); + Str1->AddOnStr(cK); + Str2->FromUInt3Dg(fData.CommBoard.LinkCount); + + case dgTYPE_COMM_MULTI: + if(fData.MultiCommBoard.oLinkType & 0x01) + Str0->FromStr(cCAN); + if(fData.MultiCommBoard.oLinkType & 0x02) + Str3->FromStr(cRS485); + if(fData.MultiCommBoard.oLinkType & 0x04) + Str4->FromStr(cEth); + break; + case dgTYPE_MOTHER_BOARD: + Str0->FromUInt4Dg(fData.MotherBoard.Voltage); + Str1->FromUInt4Dg(fData.MotherBoard.Current); + Str2->FromUInt3Dg(fData.MotherBoard.OnlineCount); + Str3->FromUInt3Dg(fData.MotherBoard.Tempe); + break; + default:break; + } +} + +void TRootDevice::PrintPortIDnActiveCount(TMyString *Str0, TMyString *Str1) +{ + Str0->FromUInt3Dg(fData.Common.Id); + Str1->FromUInt3Dg(fData.Port.OnlineCount); +} + +void TRootDevice::PrintActiveCount(TMyString *Str0) +{ + Str0->FromUInt3Dg(fData.Port.OnlineCount); +} + +void TRootDevice::PrintCarryCount(TMyString *Str0) +{ + Str0->FromUInt3Dg(fData.Port.ResistedCount); +} + + +void TRootDevice::PrintAllPrm(TMyString *StrKey[12], TMyString *StrVal[12]) +{ + unsigned int i; + for(i=0;i<12;i++){ StrKey[i]->Clear(); StrVal[i]->Clear(); } + + switch(fData.Common.dType){ + case dgTYPE_PORT: + StrKey[0]->FromStr(cVoltage); + StrVal[0]->AddOn4Dg(fData.Port.Voltage); + StrKey[1]->FromStr(cCurrent); + StrVal[1]->AddOn4Dg(fData.Port.Current); + StrKey[2]->FromStr(cAvtive); + StrVal[2]->AddOn3Dg(fData.Port.OnlineCount); + StrKey[3]->FromStr(cCarry); + StrVal[3]->AddOn3Dg(fData.Port.ResistedCount); + StrKey[4]->FromStr(cTempe); + StrVal[4]->AddOn3Dg(fData.Port.Tempe); + StrKey[5]->FromStr(cVer); + StrVal[5]->AddOn6Dg(fData.Port.Ver); + break; + case dgTYPE_HAND_CTL: + StrKey[0]->FromStr(cVoltage); + StrVal[0]->AddOn4Dg(fData.HandCtl.Voltage); + StrKey[1]->FromStr(cCurrent); + StrVal[1]->AddOn4Dg(fData.HandCtl.Current); + StrKey[2]->FromStr(cAvtive); + StrVal[2]->AddOn3Dg(fData.HandCtl.OnlineCount); + StrKey[3]->FromStr(cCarry); + StrVal[3]->AddOn3Dg(fData.HandCtl.ResistedCount); + StrKey[4]->FromStr(cTempe); + StrVal[4]->AddOn3Dg(fData.HandCtl.Tempe); + StrKey[5]->FromStr(cVer); + StrVal[5]->AddOn6Dg(fData.HandCtl.Ver); + break; + case dgTYPE_DIRECT_CTL: + StrKey[0]->FromStr(cVoltage); + StrVal[0]->AddOn4Dg(fData.DirectCtl.Voltage); + StrKey[1]->FromStr(cCurrent); + StrVal[1]->AddOn4Dg(fData.DirectCtl.Current); + StrKey[2]->FromStr(cAvtive); + StrVal[2]->AddOn3Dg(fData.DirectCtl.OnlineCount); + StrKey[3]->FromStr(cCarry); + StrVal[3]->AddOn3Dg(fData.DirectCtl.ResistedCount); + StrKey[4]->FromStr(cTempe); + StrVal[4]->AddOn3Dg(fData.DirectCtl.Tempe); + StrKey[5]->FromStr(cVer); + StrVal[5]->AddOn6Dg(fData.DirectCtl.Ver); + break; + case dgTYPE_COMM_CAN: + + case dgTYPE_COMM_MULTI: + + break; + case dgTYPE_MOTHER_BOARD: + + break; + default:break; + } +} + +void TRootDevice::GetDescp(TMyString *StrGot) +{ + +} + +void TRootDevice::SetDescp(TMyString *StrPut) +{ + +} + + +void TPort::ResetCallBack() +{ + int i; + for(i=0; i<256; i++){ + StateTable[i] &= dEpStateBitMask; + LnkRdyGo[i] =0; + HasSetLightOn[i] = 0; + DelayTick[i] = 0; + DelayToDoEventType[i] =0; + } + SyncRegisterReqStart =0; + SyncMaskReqStart =0; + SyncRegisterOnGo =0; + SyncRegisterHasReportError =0; + SyncMaskOnGo =0; + SyncMaskHasReportError =0; +} + +void TPort::InterLinkGoStartDev(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType) +{ + InterLink.oBuf.WriteIndex++; + if(InterLink.oBuf.WriteIndex >= dLinkageOutputBufMaxCOunt)InterLink.oBuf.WriteIndex = 0; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.CtlNum = aCtlNum; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.P0 = aP0; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.P1 = aP1; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.Action = dLNKSTART; +} + +void TPort::AddRemoveMsgDelayStart(unsigned int IsAdd, unsigned char aP0, unsigned char aP1, unsigned char aType) +{ + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0; + aIm.Splite.P1 = aP1; + aIm.Splite.P2 = 0; + aIm.Splite.dType = aType; + + if(IsAdd){ + aIm.Splite.UserCode =0; + aIm.Splite.AreaNum =0; + if( aP0 && aP1 ){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + if(aP1 <= dEP_MAX_COUNT_PER_PORT){ + aP1--; + aIm.Splite.UserCode = Port[aP0].UcList[aP1].Full; + aIm.Splite.AreaNum = Port[aP0].Area[aP1]; + } + } + } + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.iByte0 = 0x0A; + aIm.Splite.Data1 = 0; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterDelayStart(aIm, cmAutoStart); + } + }else{ + aIm.Splite.mType = etLinkageStartCancel; + aIm.Splite.iByte0 = 0x0A; + aIm.Splite.Data1 = 0; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartCancel(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterDelayStart(aIm, cmAutoStop); + } + } +} + +void TPort::AddRemoveMsgDelayStartSimulate(unsigned int IsAdd, unsigned char aP0, unsigned char aP1, unsigned char aType) +{ + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0; + aIm.Splite.P1 = aP1; + aIm.Splite.P2 = 0; + aIm.Splite.dType = aType; + + if(IsAdd){ + aIm.Splite.UserCode =0; + aIm.Splite.AreaNum =0; + if( aP0 && aP1 ){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + if(aP1 <= dEP_MAX_COUNT_PER_PORT){ + aP1--; + aIm.Splite.UserCode = Port[aP0].UcList[aP1].Full; + aIm.Splite.AreaNum = Port[aP0].Area[aP1]; + } + } + } + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.iByte0 = 0x0A; + aIm.Splite.Data1 = TControlCenter::StartTypeSimulate; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartSimulate(aIm); + ProtoC2C.SlaveDoSend2MasterDelayStartSimulate(aIm, cmVIrtualStart); + } + }else{ + aIm.Splite.mType = etLinkageStartCancel; + aIm.Splite.iByte0 = 0x0A; + aIm.Splite.Data1 = TControlCenter::StartTypeSimulate; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartCancelSimulate(aIm); + ProtoC2C.SlaveDoSend2MasterDelayStartSimulate(aIm, smVIrtualStop); + } + } +} + +void TPort::SortDisplayPad() +{ + int i, PadInx, Found; + unsigned char tAddr; + for(i=0; i= 16)break; + } + } +} + +void TPort::SetOneDisplayPadSetting(unsigned char *pByte) +{ + int Found =0; + if(pByte[0] <1)return; + for(int x=0; xNum; + Data[2] = 2; //Ack 2 + Data[3] = 0; + Data[4] = 0; + Data[5] = 0; + Data[6] = 0; + Data[7] = 0; + InnerCan.OBufInsert(2, cmBusDataSyncRegisterReq, Data, 3); +} + +void TPort::sRpyMaskDataSyncReqStart(class TPort *pPort) +{ + unsigned char Data[8]; + + if (pPort == nullptr)return; + Data[0] = 0; + Data[1] = pPort->Num; + Data[2] = 2; //Ack 2 + Data[3] = 0; + Data[4] = 0; + Data[5] = 0; + Data[6] = 0; + Data[7] = 0; + InnerCan.OBufInsert(2, cmBusDataSyncIsolationReq, Data, 3); +} + +void TPort::sSendRegDataSync(class TPort *pPort) +{ + unsigned char Data[8]; + unsigned char tP0; + if(pPort == nullptr)return; + pPort->SyncRegisterOnGo = 1; + pPort->SyncRegisterTick = 0; + pPort->SyncRegisterResult = 0; + + Data[0] = 0; + Data[1] = pPort->Num; + + for(int i=0; i<50; i++){ + Data[2] = i+1; + tP0 = i*5; + int dInx=3; + for(int x=0; x<5; x++){ + if(pPort->ExistTable[tP0] == 0xA5){ + Data[dInx] = pPort->dTypeTable[tP0]; + }else{ + Data[dInx] = 0; + } + dInx++; + tP0++; + } + InnerCan.OBufInsert(2, cmBusDataSyncRegister, Data, 8); + } +} + +void TPort::sSnedMaskDataSync(class TPort *pPort) +{ + unsigned char Data[8]; + unsigned char tP0; + pPort->SyncMaskOnGo = 1; + pPort->SyncMaskTick = 0; + pPort->SyncMaskResult = 0; + + Data[0] = 0; + Data[1] = pPort->Num; + + for(int i=0; i<50; i++){ + Data[2] = i+1; + tP0 = i*5; + int dInx=3; + for(int x=0; x<5; x++){ + if(pPort->StateTable[tP0] & dEpStateBitMask){ + Data[dInx] = 1; + }else{ + Data[dInx] = 0; + } + dInx++; + tP0++; + } + InnerCan.OBufInsert(2, cmBusDataSyncIsolation, Data, 8); + } +} + +void TPort::SyncTaskIntv1000Ms() +{ + //CtlCenter.ieAddBrdFaultCancel(i+1, 10); + //CtlCenter.ieAddBrdFault(i+1, 10); + if(SyncRegisterOnGo){ + if(SyncRegisterResult){ + if(SyncRegisterResult == 1){ + //Sync Ok + if(SyncRegisterHasReportError){ + //Cancel Fault Msg + CtlCenter.ieAddBrdFaultCancel(Num, TBoardFaultType::RegisteredData); + SyncRegisterHasReportError =0; + } + }else + if(SyncRegisterResult == 2){ + //Sync Bad Data + if(SyncRegisterHasReportError == 0){ + //Add Fault Msg + CtlCenter.ieAddBrdFault(Num, TBoardFaultType::RegisteredData); + SyncRegisterHasReportError =1; + } + } + SyncRegisterOnGo = 0; + }else{ + if(SyncRegisterTick > 180){ + //Sync Time out + if(SyncRegisterHasReportError == 0){ + //Add Fault Msg + CtlCenter.ieAddBrdFault(Num, TBoardFaultType::RegisteredData); + SyncRegisterHasReportError =1; + } + SyncRegisterOnGo =0; + } + } + if(SyncRegisterTick <200){ + SyncRegisterTick++; + } + } + if(SyncMaskOnGo){ + if(SyncMaskResult){ + if(SyncMaskResult == 1){ + //Sync Ok + if(SyncMaskHasReportError){ + //Cancel Fault Msg + CtlCenter.ieAddBrdFaultCancel(Num, TBoardFaultType::MaskedData); + SyncMaskHasReportError =0; + } + }else + if(SyncMaskResult == 2){ + //Sync Bad Data + if(SyncMaskHasReportError == 0){ + //Add Fault Msg + CtlCenter.ieAddBrdFault(Num, TBoardFaultType::MaskedData); + SyncMaskHasReportError =1; + } + } + SyncMaskOnGo = 0; + }else{ + if(SyncMaskTick > 180){ + //Sync Time out + if(SyncMaskHasReportError == 0){ + //Add Fault Msg + CtlCenter.ieAddBrdFault(Num, TBoardFaultType::MaskedData); + SyncMaskHasReportError =1; + } + SyncMaskOnGo =0; + } + } + if(SyncMaskTick <200){ + SyncMaskTick++; + } + } +} + +void TPort::sRecallCrcFaultMsg(unsigned char aPort) +{ + int x, m; + if(Port[aPort].CrcFlag.DevType){ + CtlCenter.ieAddBrdFault(aPort+1, TBoardFaultType::StorageEpDType); + } + if(Port[aPort].CrcFlag.CrcDisplayPad){ + CtlCenter.ieAddBrdFault(aPort+1,TBoardFaultType::StoragePortDpSet); + } + if(Port[aPort].CrcFlag.AuxId){ + CtlCenter.ieAddBrdFault(aPort+1, TBoardFaultType::StorageEpAuxId); + } + if(Port[aPort].CrcFlag.AssignedType){ + CtlCenter.ieAddBrdFault(aPort+1, TBoardFaultType::StorageEpAssignedType); + } + if(Port[aPort].CrcFlag.SignalType){ + CtlCenter.ieAddBrdFault(aPort+1, TBoardFaultType::StorageEpSignalType); + } + if(Port[aPort].CrcFlag.Area){ + CtlCenter.ieAddBrdFault(aPort+1,TBoardFaultType::StorageEpArea); + } +} + +void THandCtlBoard::SetOutputStateViaUserCode(unsigned char aPadNum, unsigned char aKeyNum, unsigned char aDType, unsigned char aCtlNum, unsigned int aDoStop) +{ + unsigned int i, x; + volatile unsigned int tAddr; + TUserCodeStr tCode; + TUserCodeStr cCode; + + if( (aDType == 0) || (aDType == 255) )return; + + tCode.Full = HandCtlBoard[aPadNum].UcList[aKeyNum].Full; + if(tCode.Spl.BcdText_0 == 10)tCode.Spl.BcdText_0 = 0xF; + if(tCode.Spl.BcdText_1 == 10)tCode.Spl.BcdText_1 = 0xF; + if(tCode.Spl.BcdText_2 == 10)tCode.Spl.BcdText_2 = 0xF; + if(tCode.Spl.BcdText_3 == 10)tCode.Spl.BcdText_3 = 0xF; + if(tCode.Spl.BcdText_4 == 10)tCode.Spl.BcdText_4 = 0xF; + if(tCode.Spl.BcdText_6 == 10)tCode.Spl.BcdText_6 = 0xF; + if(tCode.Spl.BcdText_7 == 10)tCode.Spl.BcdText_7 = 0xF; + + for(i=0; i= dHANDCTL_MAX_COUNT)return; + if(aKeyInx >= KeyCount)return; + if(aKeyInx >= dHANDCTL_KEY_MAX_COUNT)return; + + if(KeyHasConfig[aKeyInx]){ + + if(KeyState[aKeyInx] == 0){ + aCmd = cmAutoStart; + Record.OperateAdd_BusPadOn(MainCtl.fData.Split.MyNum, aPadInx +1, aKeyInx+1); + if(IsMatchAreaAssign[aKeyInx]){ + SetOutputStateViaAreaNum(aPadInx, aKeyInx, HandCtlBoard[aPadInx].AssignType[aKeyInx], aCtlNum, 0); + }else{ + SetOutputStateViaUserCode(aPadInx, aKeyInx, HandCtlBoard[aPadInx].AssignType[aKeyInx], aCtlNum, 0); + } + }else{ + aCmd = cmAutoStop; + Record.OperateAdd_BusPadOff(MainCtl.fData.Split.MyNum, aPadInx +1, aKeyInx+1); + if(IsMatchAreaAssign[aKeyInx]){ + SetOutputStateViaAreaNum(aPadInx, aKeyInx, HandCtlBoard[aPadInx].AssignType[aKeyInx], aCtlNum, 1); + }else{ + SetOutputStateViaUserCode(aPadInx, aKeyInx, HandCtlBoard[aPadInx].AssignType[aKeyInx], aCtlNum, 1); + } + } + } +} + +void THandCtlBoard::KeyPress(unsigned char aCtlNum, unsigned char aPadNum, unsigned char aKeyNum) +{ + unsigned char aPn,aKn; + + if(aPadNum == 0)return; + if(aPadNum > dHANDCTL_MAX_COUNT)return; + if(aKeyNum == 0)return; + if(aKeyNum > KeyCount)return; + if(aKeyNum > dHANDCTL_KEY_MAX_COUNT)return; + + aPn = aPadNum; + aKn = aKeyNum; + aPn--; + aKn--; + + KeyAction(aCtlNum, aPn, aKn); +} + +void THandCtlBoard::CheckKeyState(unsigned char aCtlNum, unsigned char aPadNum) +{ + unsigned int i,m,z,x; + unsigned int FbTimes, NoFbTimes; + unsigned char NewFbState; + unsigned int NewStartTimes, NewStopTimes; + unsigned char NewStartState; + unsigned char NewLnkRdyState; + volatile unsigned int tAddr; + + unsigned short tArea, cArea; + + TUserCodeStr tCode; + TUserCodeStr cCode; + + + int NeedToUpdata; + + if(aPadNum >= dHANDCTL_MAX_COUNT)return; + + if(KeyCount >dHANDCTL_KEY_MAX_COUNT)KeyCount = dHANDCTL_KEY_MAX_COUNT; + for(i=0; iAssignType[i] && (this->AssignType[i] != 255) ){ + FbTimes = 0; + NoFbTimes = 0; + NewLnkRdyState = 0; + NewStartTimes = 0; + NewStopTimes = 0; + + if(IsMatchAreaAssign[i]){ + tArea = this->Area[i]; + for(z=0; zAssignType[i]) || (Port[z].AssignType[x] == this->AssignType[i])){ + cArea = Port[z].Area[x]; + if( tArea && (tArea == cArea) ){ + if( (Port[z].StateTable[x] & dEpStateBitMask) == 0){ + if(Port[z].LnkRdyGo[x]){ + NewLnkRdyState = 1; + } + if(Port[z].StateTable[x] & dEpStateBitStart){ + NewStartTimes ++; + }else{ + NewStopTimes ++; + } + } + if( (Port[z].StateTable[x] & dEpStateBitMask) == 0){ + if(Port[z].StateTable[x] & dEpStateBitFeedBack){ + FbTimes++; + }else{ + NoFbTimes++; + } + } + } + } + } + } + } + } + }else{ + tCode.Full = HandCtlBoard[aPadNum].UcList[i].Full; + if(tCode.Spl.BcdText_0 == 10)tCode.Spl.BcdText_0 = 0xF; + if(tCode.Spl.BcdText_1 == 10)tCode.Spl.BcdText_1 = 0xF; + if(tCode.Spl.BcdText_2 == 10)tCode.Spl.BcdText_2 = 0xF; + if(tCode.Spl.BcdText_3 == 10)tCode.Spl.BcdText_3 = 0xF; + if(tCode.Spl.BcdText_4 == 10)tCode.Spl.BcdText_4 = 0xF; + if(tCode.Spl.BcdText_5 == 10)tCode.Spl.BcdText_5 = 0xF; + if(tCode.Spl.BcdText_6 == 10)tCode.Spl.BcdText_6 = 0xF; + if(tCode.Spl.BcdText_7 == 10)tCode.Spl.BcdText_7 = 0xF; + + for(z=0; zAssignType[i]) || (Port[z].AssignType[x] == this->AssignType[i])){ + tAddr = dAddrSdRam_4UserCodeMatch + (z * 1024) + (x * 4); + cCode.Full = *(volatile unsigned int *)(tAddr); + cCode.Full |= HandCtlBoard[aPadNum].UcListNotAnd[i].Full; + if(cCode.Full == tCode.Full){ + if( (Port[z].StateTable[x] & dEpStateBitMask) == 0){ + if(Port[z].LnkRdyGo[x]){ + NewLnkRdyState = 1; + } + if(Port[z].StateTable[x] & dEpStateBitStart){ + NewStartTimes ++; + }else{ + NewStopTimes ++; + } + } + if( (Port[z].StateTable[x] & dEpStateBitMask) == 0){ + if(Port[z].StateTable[x] & dEpStateBitFeedBack){ + FbTimes++; + }else{ + NoFbTimes++; + } + } + } + } + } + } + } + } + } + + NeedToUpdata = 0; + //Check Start Modify + if(NewStartTimes) NewStartState =2; else NewStartState =0; + if(NewStartTimes && NewStopTimes)NewStartState = 1; + if(KeyState[i] != NewStartState){ + NeedToUpdata = 1; + KeyState[i] = NewStartState; + } + //Check FeedBack Modify + if(1){ + if(FbTimes) NewFbState =2; else NewFbState =0; + if(FbTimes && NoFbTimes)NewFbState = 1; + + if(KeyFbState[i] != NewFbState){ + NeedToUpdata = 1; + KeyFbState[i] = NewFbState; + } + }else{ + KeyFbState[i] = 3; + } + //Check Linkage Rdy Modify + if(LnkRdyGo[i] != NewLnkRdyState){ + NeedToUpdata = 1; + LnkRdyGo[i] = NewLnkRdyState; + } + //Check Modify To Send + if(NeedToUpdata){ + tData[0] = 0; + tData[1] = aCtlNum; + tData[2] = aPadNum + dADDR_HANDPAD_START; + tData[3] = i +1; + tData[4] = KeyState[i]; + tData[5] = KeyFbState[i]; + tData[6] = LnkRdyGo[i]; + InnerCan.OBufInsert(1, cmBusCtlPadState, tData, 7); + } + } + } +} + +void THandCtlBoard::SendPadCfg2Pad(unsigned char aPadNum) +{ + int i,x,p, Pst, Piece; + unsigned char Val; + + tData[1] = aPadNum + dADDR_HANDPAD_START; + + if(KeyCount == 48)Piece = 1; + else if(KeyCount == 64)Piece = 2; + else if(KeyCount == 128)Piece = 3; + else Piece = 0; + + for(p=0; p= dDIRECTCTL_KEY_MAX_COUNT)return; + //if(IsRegisted[aNode] == 0)return; + + //Add Record Here + if(aSta & 0x01){ + NewOutputStaate = 1; + }else{ + NewOutputStaate = 0; + } + + if(aSta & 0x02){ + NewFbState = 1; + }else{ + NewFbState = 0; + } + + if(aSta & 0x04){ + NewFaultState = 1; + }else{ + NewFaultState = 0; + } + + if(OutputState[aNode] != NewOutputStaate){ + OutputState[aNode] = NewOutputStaate; + if(OutputState[aNode]){ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 + dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode +1; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.dType = 0; + + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + + if(aSta & 0x08){ + aIm.Splite.iByte0 = 0x05; + }else{ + aIm.Splite.iByte0 = 0x01; + } + aIm.Splite.Data1 = 0; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(aIm); + } + }else{ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 + dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode +1; + aIm.Splite.P2 = 0; + aIm.Splite.dType = 0; + aIm.Splite.Data1 = 0; + + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + + if(CtlCenter.IsMsgReseting == 0){ + aIm.Splite.mType = etLinkageStart; + aIm.Splite.iByte0 = 0x09; + CtlCenter.iePushOneMsgLinkageStart(aIm); + + aIm.Splite.mType = etLinkageStartCancel; + if(aSta & 0x08){ + aIm.Splite.iByte0 = 0xB5; + }else{ + aIm.Splite.iByte0 = 0xB1; + } + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(aIm); + } + } + if( (CtlCenter.IsMsgReseting == 0) && (MainCtl.fData.Split.NetworkMode == 2) ){ + tData.D8[0] = 0; + tData.D8[1] = aIm.Splite.PCtlNum; + tData.D8[2] = aIm.Splite.P0; + tData.D8[3] = aIm.Splite.P1; + tData.D8[4] = 0; + tData.D8[5] = 0; + tData.D8[6] = aSta; + tData.D8[7] = 0; + if(OutputState[aNode]) + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmAutoStart, TProtoC2C::mtLink); + else + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmAutoStop, TProtoC2C::mtLink); + } + } + if(FeedbackState[aNode] != NewFbState){ + FeedbackState[aNode] = NewFbState; + if(FeedbackState[aNode]){ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 +dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode +1; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageFeedBack; + aIm.Splite.dType = 0; + aIm.Splite.iByte0 = 0x03; + aIm.Splite.Data1 = 0; + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageFb(aIm); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); + Record.LinkageAdd(aIm); + } + }else{ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 +dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode +1; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageFeedBack; + aIm.Splite.dType = 0; + aIm.Splite.iByte0 = 0xB3; + aIm.Splite.Data1 = 0; + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageFbCancel(aIm); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); + Record.LinkageAdd(aIm); + } + } + if( (CtlCenter.IsMsgReseting == 0) && (MainCtl.fData.Split.NetworkMode == 2) ){ + tData.D8[0] = 0; + tData.D8[1] = aIm.Splite.PCtlNum; + tData.D8[2] = aIm.Splite.P0; + tData.D8[3] = aIm.Splite.P1; + tData.D8[4] = 0; + tData.D8[5] = 0; + tData.D8[6] = 0; + tData.D8[7] = 0; + if(FeedbackState[aNode]) + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmAck, TProtoC2C::mtLink); + else + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmAckStop, TProtoC2C::mtLink); + } + } + if(FaultState[aNode] != NewFaultState){ + FaultState[aNode] = NewFaultState; + if(FaultState[aNode]){ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 +dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode +1; + aIm.Splite.P2 = 5; + + aIm.Splite.mType = etFault; + aIm.Splite.dType = 0; + aIm.Splite.iByte0 = 0x01; + aIm.Splite.Data0 = 5; + aIm.Splite.Data1 = 0x1; + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgFault(aIm); + Record.FaultAdd(aIm); + } + }else{ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 +dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode +1; + aIm.Splite.P2 = 5; + + aIm.Splite.mType = etFault; + aIm.Splite.dType = 0; + aIm.Splite.iByte0 = 0x01; + aIm.Splite.Data0 = 5; + aIm.Splite.Data1 = 0x0; + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgFaultCancel(aIm); + Record.FaultAdd(aIm); + } + } + if( (CtlCenter.IsMsgReseting == 0) && (MainCtl.fData.Split.NetworkMode == 2) ){ + tData.D8[0] = 0; + tData.D8[1] = aIm.Splite.PCtlNum; + tData.D8[2] = aIm.Splite.P0; + tData.D8[3] = aIm.Splite.P1; + tData.D8[4] = 5; + tData.D8[5] = 0; + tData.D8[6] = 5; + tData.D8[7] = aIm.Splite.Data1; + if(FaultState[aNode]) + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmPortModuleErr, TProtoC2C::mtFault); + else + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmPortModuleErrRecover, TProtoC2C::mtFault); + } + } +} + +void TDirectCtlBoard::AddStartStopSimulate(unsigned int IsStart, unsigned char aP0, unsigned char aNode) +{ + if(aP0 >= dDIRECTCTL_MAX_COUNT)return; + if(aNode == 0)return; + if(aNode > dDIRECTCTL_KEY_MAX_COUNT)return; + if(IsStart){ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 + dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.dType = 0; + + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + + aIm.Splite.iByte0 = 0x01; + aIm.Splite.Data1 = TControlCenter::StartTypeSimulate; + if(CtlCenter.IsMsgReseting == 0){ + if(CtlCenter.iePushOneMsgLinkageStartSimulate(aIm)){ + Record.LinkageAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmVIrtualStart, TProtoC2C::mtLink); + } + } + }else{ + aImAddDateTime(); + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0 + dADDR_DIRECTPAD_START; + aIm.Splite.P1 = aNode; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.dType = 0; + + GetUserCodeAreaNumDevType(aIm.Splite.P0, aIm.Splite.P1, &aIm.Splite.UserCode, &aIm.Splite.AreaNum, &aIm.Splite.dType); + + aIm.Splite.iByte0 = 0x09; + aIm.Splite.Data1 = TControlCenter::StartTypeSimulate; + if(CtlCenter.IsMsgReseting == 0){ + if(CtlCenter.iePushOneMsgLinkageStartSimulate(aIm)){ + Record.LinkageAdd(aIm); + ProtoC2C.SlaveDoSend2MasterMachine(aIm, cmVIrtualStart, TProtoC2C::mtLink); + } + } + } +} + +void TDirectCtlBoard::SendPadCfg2Pad(unsigned char aPadNum) +{ + int i,xst; + if(18){ + tData.D8[0] = 0xF0; + if(PadIsProhibit == 0)tData.D8[0] |= 0x01; + if(AllowManual)tData.D8[0] |= 0x02; + tData.D8[1] = aPadNum + dADDR_DIRECTPAD_START; + tData.D8[2] =0; tData.D8[3] =0; tData.D8[4] =0; tData.D8[5] =0; tData.D8[6] =0; tData.D8[7] =0; + for(i=0; i<8; i++){ + if(IsRegisted[i])tData.D8[2] |= 1<= dLinkageOutputBufMaxCOunt)InterLink.oBuf.WriteIndex = 0; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.CtlNum = aCtlNum; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.P0 = aP0; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.P1 = aP1; + InterLink.oBuf.Body[InterLink.oBuf.WriteIndex].Spl.Action = dLNKSTART; +} + +void TDirectCtlBoard::AddRemoveMsgDelayStart(unsigned int IsAdd, unsigned char aP0, unsigned char aP1) +{ + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0; + aIm.Splite.P1 = aP1; + aIm.Splite.P2 = 0; + aIm.Splite.dType = 0; + + if(IsAdd){ + aIm.Splite.UserCode =0; + aIm.Splite.AreaNum =0; + //#define dADDR_DIRECTPAD_START 66 + //#define dADDR_DIRECTPAD_END 85 + if( aP0 && aP1 ){ + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0-=dADDR_DIRECTPAD_START; + if(aP1 <= dDIRECTCTL_KEY_MAX_COUNT){ + aP1--; + aIm.Splite.UserCode = DirectCtlBoard[aP0].UcList[aP1].Full; + aIm.Splite.AreaNum = DirectCtlBoard[aP0].Area[aP1]; + aIm.Splite.dType = DirectCtlBoard[aP0].AssignType[aP1]; + } + } + } + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.iByte0 = 0x0A; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterDelayStart(aIm, cmAutoStart); + } + }else{ + aIm.Splite.mType = etLinkageStartCancel; + aIm.Splite.iByte0 = 0x0A; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartCancel(aIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterDelayStart(aIm, cmAutoStop); + } + } +} + + +void TDirectCtlBoard::AddRemoveMsgDelayStartSimulate(unsigned int IsAdd, unsigned char aP0, unsigned char aP1) +{ + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + aIm.Splite.P0 = aP0; + aIm.Splite.P1 = aP1; + aIm.Splite.P2 = 0; + aIm.Splite.dType = 0; + + if(IsAdd){ + aIm.Splite.UserCode =0; + aIm.Splite.AreaNum =0; + //#define dADDR_DIRECTPAD_START 66 + //#define dADDR_DIRECTPAD_END 85 + if( aP0 && aP1 ){ + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0-=dADDR_DIRECTPAD_START; + if(aP1 <= dDIRECTCTL_KEY_MAX_COUNT){ + aP1--; + aIm.Splite.UserCode = DirectCtlBoard[aP0].UcList[aP1].Full; + aIm.Splite.AreaNum = DirectCtlBoard[aP0].Area[aP1]; + aIm.Splite.dType = DirectCtlBoard[aP0].AssignType[aP1]; + } + } + } + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.iByte0 = 0x0A; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartSimulate(aIm); + ProtoC2C.SlaveDoSend2MasterDelayStartSimulate(aIm, cmAutoStart); + } + }else{ + aIm.Splite.mType = etLinkageStartCancel; + aIm.Splite.iByte0 = 0x0A; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartCancel(aIm); + //ExRecord.SetStateCodeStart(); + //FecBusCRT.SetStateCodeStart(); + ProtoC2C.SlaveDoSend2MasterDelayStartSimulate(aIm, cmAutoStop); + } + } +} + +void TDirectCtlBoard::GetUserCodeAreaNumDevType(unsigned char aP0, unsigned char aP1, unsigned int *pUc, unsigned short *pAreaNum, unsigned char *pDType) +{ + if(aP0 ==0){*pUc =0; *pAreaNum =0; *pDType =0; return;} + if(aP1 ==0){*pUc =0; *pAreaNum =0; *pDType =0; return;} + + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if(aP1 >dDIRECTCTL_KEY_MAX_COUNT){*pUc =0; *pAreaNum =0; *pDType =0; return;} + aP0-=dADDR_DIRECTPAD_START; aP1--; + *pUc = DirectCtlBoard[aP0].UcList[aP1].Full; + *pAreaNum = DirectCtlBoard[aP0].Area[aP1]; + *pDType = DirectCtlBoard[aP0].AssignType[aP1]; + }else{ + *pUc = 0; + *pAreaNum = 0; + *pDType =0; + } +} + +void TDirectCtlBoard::sRecallCrcFaultMsg(unsigned char aPad) +{ + if(DirectCtlBoard[aPad].CrcFlag.Config){ + CtlCenter.ieAddBrdFault(aPad+dADDR_DIRECTPAD_START, TBoardFaultType::StorageDirectPadCfg); + } + if(DirectCtlBoard[aPad].CrcFlag.AuxId){ + CtlCenter.ieAddBrdFault(aPad+dADDR_DIRECTPAD_START,TBoardFaultType::StorageEpAuxId); + } + if(DirectCtlBoard[aPad].CrcFlag.AssignedType){ + CtlCenter.ieAddBrdFault(aPad+dADDR_DIRECTPAD_START,TBoardFaultType::StorageEpAssignedType); + } + if(DirectCtlBoard[aPad].CrcFlag.Area){ + CtlCenter.ieAddBrdFault(aPad+dADDR_DIRECTPAD_START,TBoardFaultType::StorageEpArea); + } +} + +void TMotherBoard::CheckOnlineTask() +{ + int i; + for(i=0; i<3; i++){ + if(Exist[i]){ + if(NoReportTick[i] == 0){ + if(ErrorHasReport[i]){ + //Clear Error + ErrorHasReport[i] =0; + CtlCenter.ieAddBrdFaultCancel(i+1, 10); + } + }else + if(NoReportTick[i] > 50){ + if(ErrorHasReport[i] == 0){ + //Report Error + ErrorHasReport[i] = 1; + CtlCenter.ieAddBrdFault(i+1, 10); + } + NoReportTick[i] = 51; + } + NoReportTick[i]++; + } + } +} + +void TMotherBoard::ResetCallBack() +{ + unsigned int i; + for(i=0;i<8;i++){ + OffLine[i] =0; + NoReportTick[i] =0; + ErrorHasReport[i] =0; + } +} + +void TDevPrinter::AddRemoveMsgFaultOffline(int IsAdd) +{ + if(IsAdd) CtlCenter.ieAddDevFault(17,0); + else CtlCenter.ieAddDevFaultCancel(17,0); +} + +void TDevPrinter::AddRemoveMsgFaultNoPaper(int IsAdd) +{ + if(IsAdd) CtlCenter.ieAddDevFault(18,0); + else CtlCenter.ieAddDevFaultCancel(18,0); +} + +void TDevPrinter::SetState(int aOffline, int aNoPaper) +{ + if(sOffline != aOffline){ + if(aOffline){ + //AddRemoveMsgFaultOffline(1); + }else{ + //AddRemoveMsgFaultOffline(0); + } + sOffline = aOffline; + } + + /*if(sOffline == 0){ + if(sNoPaper != aNoPaper){ + if(aNoPaper){ + AddRemoveMsgFaultNoPaper(1); + }else{ + AddRemoveMsgFaultNoPaper(0); + } + sNoPaper = aNoPaper; + } + }*/ +} + +void TGeneralDev::LcdBlackLightSetOn() +{ + LcdCountDownTick = (static_cast(ScreenAndKeyLock.SaveTime)) * 60; + LcdScreenSaving = 0; + lcd_bl_on(); +} + +void TGeneralDev::LcdBlackLightSetOnStartUp() +{ + LcdCountDownTick = (static_cast(ScreenAndKeyLock.SaveTime)) * 60; + LcdScreenSaving = 0; + lcd_bl_on(); +} + +void TGeneralDev::LcdBlackLightSetOff() +{ + LcdScreenSaving = 1; + lcd_bl_off(); +} + +void TGeneralDev::Task1000Ms() +{ + if(ScreenAndKeyLock.SaveOn){ + if(LcdCountDownTick){ + LcdCountDownTick--; + if(LcdCountDownTick > 1200)LcdCountDownTick = 1200; + }else{ + //0x01 Fire; 0x02 Sv; 0x04 Fault + if( ( (ScreenAndKeyLock.IsKeyLock & 0x01) && (CtlCenter.ieMsgFire.Count >0) ) || + ( (ScreenAndKeyLock.IsKeyLock & 0x02) && (CtlCenter.ieMsgSv.Count >0) ) || + ( (ScreenAndKeyLock.IsKeyLock & 0x04) && (CtlCenter.ieMsgFault.Count >0) ) ){ + LcdCountDownTick = 10; + }else{ + LcdBlackLightSetOff(); + } + } + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/Device.h b/MyCode/src/Device.h new file mode 100644 index 0000000..57c75c0 --- /dev/null +++ b/MyCode/src/Device.h @@ -0,0 +1,578 @@ +#ifndef DEVICE_H_ +#define DEVICE_H_ + +#include "gType.h" +#include "my_string.h" +#include "gvalue.h" +#include "record.h" +#include "ProtoC2C.h" + +typedef union{ + unsigned char MemBytes[16]; + unsigned char MemD32[4]; + struct{ + unsigned char Addr; + unsigned char CfgBits; + unsigned short AreaEx[3]; + TUserCode UcList[2]; + }; +}TDisplayPadSetting; + +typedef union{ + unsigned int D32[8]; + unsigned char D8[32]; + struct{ + unsigned int Sn; + unsigned char dType; + unsigned char Id; + unsigned short Ver; + + unsigned int UserCode; + }Common; + + struct{ + unsigned int Sn; + unsigned char dType; + unsigned char Id; + unsigned short Ver; + + unsigned int UserCode; + + unsigned char OnlineCount; + unsigned char ResistedCount; + unsigned short Voltage; + + unsigned short Current; + unsigned char Tempe; + unsigned char MotherBoardID; + + unsigned char FBCZero; + unsigned char FBCFull; + unsigned char FBVZero; + unsigned char FBVFULL; + + unsigned char Flag; + }Port; + struct{ + unsigned int Sn; + unsigned char dType; + unsigned char Id; + unsigned short Ver; + + unsigned int UserCode; + + unsigned char OnlineCount; + unsigned char ResistedCount; + unsigned short Voltage; + + unsigned short Current; + unsigned short Tempe; + + unsigned char Flag; + }HandCtl; + struct{ + unsigned int Sn; + unsigned char dType; + unsigned char Id; + unsigned short Ver; + + unsigned int UserCode; + + unsigned char OnlineCount; + unsigned char ResistedCount; + unsigned short Voltage; + + unsigned short Current; + unsigned short Tempe; + + unsigned char Flag; + }DirectCtl; + struct{ + unsigned int Sn; + unsigned char dType; + unsigned char Id; + unsigned short Ver; + + unsigned int UserCode; + + unsigned char OnlineCount; + unsigned char ResistedCount; + + unsigned short Voltage; + unsigned short Current; + unsigned short Tempe; + + unsigned char PortOnlineList[8]; + unsigned char PortCarryList[8]; + + unsigned char Flag; + }MotherBoard; + struct{ + unsigned int Sn; + unsigned char dType; + unsigned char Id; + unsigned short Ver; + + unsigned int UserCode; + + unsigned char iLinkType; + unsigned char oLinkType; + + unsigned short iLinkSpeed; + unsigned short oLinkSpeed; + + unsigned char LinkCount; + unsigned char EnableBit; //0x01:En1; 0x02:En2; 0x04:En3; 0x08:En4; + + unsigned char Flag; + }CommBoard; + struct{ + unsigned int Sn; + unsigned char dType; + unsigned char Id; + unsigned short Ver; + + unsigned int UserCode; + + unsigned char iLinkType; + unsigned char oLinkType; //0x01=CAN 0x02=RS485 0x04=Eth + + unsigned short iLinkSpeed; + unsigned short oLinkSpeed; + + unsigned char LinkCount; + unsigned char EnableBit; //0x01:En1; 0x02:En2; 0x04:En3; 0x08:En4; + + unsigned char Flag; + }MultiCommBoard; +}TRootDeviceData; + +class TRootDevice{ + public: + TRootDeviceData fData; + float fVoltage; + float fCurrent; + unsigned int DymState; + public: + TRootDevice(void){ + unsigned int i; + for(i=0;i<8;i++) fData.D32[i] = 0; + } + void GetDescp(TMyString *StrGot); + void SetDescp(TMyString *StrPut); + + void PrintProperty (TMyString *Str0, TMyString *Str1, TMyString *Str2); //UserCode ID dType + void PrintAttribute (TMyString *Str0, TMyString *Str1); //CarryCount Ver + void PrintDynamicsData (TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5, TMyString *Str6, TMyString *Str7); + void PrintAllPrm (TMyString *StrKey[12], TMyString *StrVal[12]); + void PrintActiveCount(TMyString *Str0); + void PrintCarryCount(TMyString *Str0); + void PrintPortIDnActiveCount (TMyString *Str0, TMyString *Str1); +}; + +class TPort : public TRootDevice{ + public: + static const unsigned char DisplayPadByAreaModeBit = 0x80; + static const unsigned char DisplayPadUsingUcEx0 = 0x01; + static const unsigned char DisplayPadUsingUcEx1 = 0x02; + static const unsigned char DisplayPadUsingAreaEx0 = 0x04; + static const unsigned char DisplayPadUsingAreaEx1 = 0x08; + static const unsigned char DisplayPadUsingAreaEx2 = 0x10; + + static const unsigned char ModulaInputAsFeedBackBit = 0x01; + static const unsigned char MouilaInputAsFireBit = 0x02; + static const unsigned char MouilaInputAsSvBit = 0x04; + + static const unsigned char MouilaInOutAsFeedBackBit = 0x01; + static const unsigned char MouilaInOutAsFireBit = 0x02; + static const unsigned char MouilaInOutAsSvBit = 0x04; + static const unsigned char MouilaInOutAsPushDrvBit = 0x08; + + static const unsigned char VaAsLinkageBit = 0x01; + static const unsigned char VaSoundOnBit = 0x02; + static const unsigned char VaVisionOnBit = 0x04; + static const unsigned char VaSoundTypeBits= 0xF0; + + static TDisplayPadSetting tmpDisplayPadSet[dDISPLAYPAD_MAX_COUNT]; + public: + unsigned int LastUpdataTime; + unsigned char ExistTable[256]; + unsigned char dTypeTable[256]; + unsigned char StateTable[256]; + unsigned char LnkRdyGo[256]; + unsigned char DisplayPadAddr[dDISPLAYPAD_MAX_COUNT]; + unsigned int DisplayPadLastDayTime[dDISPLAYPAD_MAX_COUNT]; + unsigned int DisplayPadLastYearMonth[dDISPLAYPAD_MAX_COUNT]; + unsigned char NeedFeedBackAddr[256]; + unsigned char HasSetLightOn[256]; + unsigned int DelayTick[256]; + unsigned char DelayToDoEventType[256]; + unsigned char AssignType[256]; + unsigned char FuncSetByte[256]; + TUserCode UcList[256]; + unsigned short Area[256]; + + unsigned int NeedFeedBackCount; + unsigned char DisplayPadCount; + unsigned char IsIncludePump; + unsigned char Dump0; + unsigned char Dump1; + + unsigned char SyncRegisterReqStart; + unsigned char SyncMaskReqStart; + unsigned char SyncRegisterTick; + unsigned char SyncMaskTick; + unsigned char SyncRegisterOnGo; + unsigned char SyncMaskOnGo; + unsigned char SyncRegisterResult; + unsigned char SyncMaskResult; + unsigned char SyncRegisterHasReportError; + unsigned char SyncMaskHasReportError; + + unsigned int UserCodeMin; + unsigned int UserCodeMax; + + TDisplayPadSetting DisplayPadSet[dDISPLAYPAD_MAX_COUNT]; + + TCanHeaderID aIde; + unsigned char Data[8]; + + TRecordCommon aIm; + + unsigned char Num; + + unsigned int CrcDevType; + unsigned int CrcAuxId; + unsigned int CrcAssignedType; + unsigned int CrcSignalType; + unsigned int CrcArea; + unsigned int CrcDisplayPad; + unsigned int CrcRealAssignedType; + unsigned int CrcRealSignalType; + struct{ + unsigned char DevType; + unsigned char AuxId; + unsigned char AssignedType; + unsigned char SignalType; + unsigned char Area; + unsigned char CrcDisplayPad; + void Clear(){ + DevType=0; + AuxId=0; + AssignedType=0; + SignalType=0; + Area=0; + CrcDisplayPad =0; + } + }CrcFlag; + + //UserCodeMatch = SDRAM dAddrSdRam_4UserCodeMatch + public: + TPort(void){ + unsigned int i; + for(i=0;i<8;i++) fData.D32[i] = 0; + for(i=0;i<256;i++){ + StateTable[i] = 0; + LnkRdyGo[i] =0; + HasSetLightOn[i] =0; + DelayToDoEventType[i] =0; + } + SyncRegisterReqStart =0; + SyncMaskReqStart =0; + SyncRegisterOnGo =0; + SyncRegisterHasReportError =0; + SyncMaskOnGo =0; + SyncMaskHasReportError =0; + CrcFlag.Clear(); + } + void Init(void){ + unsigned int i; + for(i=0;i<8;i++) fData.D32[i] = 0; + for(i=0;i<256;i++){ + StateTable[i] = 0; + DelayTick[i] =0; + LnkRdyGo[i] =0; + HasSetLightOn[i] =0; + DelayToDoEventType[i] =0; + } + SyncRegisterReqStart =0; + SyncMaskReqStart =0; + SyncRegisterOnGo =0; + SyncRegisterHasReportError =0; + SyncMaskOnGo =0; + SyncMaskHasReportError =0; + for(i=0; i= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("总线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,PrintText.body.Msg); + TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("多线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,PrintText.body.Msg); + TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + } + }else{ + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("Bus Brd ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,PrintText.body.Msg); + TMyString::sAddOnStr(" Offline",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("Direct Brd ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,PrintText.body.Msg); + TMyString::sAddOnStr(" Offline",PrintText.body.Msg); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xD0){ + FillCtlNum(); + aType = EntryTmp.fData.Body.Splite.P2; + if(LanguageEnCn==0){ + TMyString::sAddOnStr("设备故障 ",PrintText.body.Msg); + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + } + }else{ + TMyString::sAddOnStr("Dev Fail ",PrintText.body.Msg); + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultTypeEn[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Unknown Type",PrintText.body.Msg); + } + } + + TMyString::sAddOnStr(" ",PrintText.body.Msg); + if( (aType == 15) || (aType == 16) ){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 通讯故障",PrintText.body.Msg); + else TMyString::sAddOnStr(" CommFail",PrintText.body.Msg); + //if(EntryTmp.fData.Body.Splite.mType > 200){ + // TMyString::sAddOnStr("通讯故障条目数:多于200",PrintText.body.Msg); + //}else{ + // TMyString::sAddOnStr("通讯故障条目数:",PrintText.body.Msg); + // TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.mType, PrintText.body.Msg); + //} + } + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xE0){ + FillCtlNum(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,PrintText.body.DateAddr); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("回路故障",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Loop Err",PrintText.body.Msg); + } + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("板卡故障 ",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("BoardErr ",PrintText.body.Msg); + } + aType = EntryTmp.fData.Body.Splite.P2; + if(aType == 10){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,PrintText.body.Msg); + TMyString::sAddOnStr(" ",PrintText.body.Msg); + } + if(LanguageEnCn==0){ + if(aType < 32){ + TMyString::sAddOnStr(StrBrdFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + } + }else{ + if(aType < 32){ + TMyString::sAddOnStr(StrBrdFaultTypeEn[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("-Unknown",PrintText.body.Msg); + } + } + }else{ + //EpError + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + TMyString::sAddOnStr(" ",PrintText.body.DateAddr); + + aType = EntryTmp.fData.Body.Splite.P2; + if(LanguageEnCn==0){ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知故障",PrintText.body.Msg); + } + }else{ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultTypeEn[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("-Unknown",PrintText.body.Msg); + } + } + } +} + +void TDoPrint::OperateAddConfirmMsg(int NeedDrawCfg) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + + if(NeedDrawCfg == 1){ + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",PrintText.body.Msg); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],PrintText.body.Msg); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + if(LanguageEnCn==0)TMyString::sAddOnStr("多线盘节点 ",PrintText.body.Msg); + else TMyString::sAddOnStr("Direct Node ",PrintText.body.Msg); + } + } + }else + if(NeedDrawCfg == 2){ + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0x0){ + TMyString::sAddOnStr(" ",PrintText.body.Msg); + aP0 = EntryTmp.fData.Body.Splite.P0; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],PrintText.body.Msg); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + if(LanguageEnCn==0)TMyString::sAddOnStr("多线盘节点 ",PrintText.body.Msg); + else TMyString::sAddOnStr("Direct Node ",PrintText.body.Msg); + } + } + } +} + +void TDoPrint::DescpTextBufInsert(TRecordCommon aEntryTmp, unsigned int Descp) +{ + unsigned int d; + + if(Descp){ + GetDescpEntry(aEntryTmp); + for(d=0;d<((15-7)*4);d++){ + PrintText.body.Dscp[d] = EntryTmp.D8[7*4+d]; + if(0 == PrintText.body.Dscp[d])break; + } + PrintText.body.Dscp[d] = '\n'; + PrintText.body.Dscp[d+1] = 0; + } +} + +void TDoPrint::DescpTextBufInsertByAssign(char *p) +{ + unsigned int d; + if(p != nullptr){ + for(d=0;d<((15-7)*4);d++){ + PrintText.body.Dscp[d] = p[d]; + if(0 == PrintText.body.Dscp[d])break; + } + PrintText.body.Dscp[d] = '\n'; + PrintText.body.Dscp[d+1] = 0; + } +} + +void TDoPrint::FillOperateText(TRecordCommon OperateEntryTmp, int aForce) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned int ExpsInx; + + int NeedDisplayDescp; + NeedDisplayDescp = 0; + + if(aForce ==0){ + if(PriterSetting.OnOff == 0)return; + if( (PriterSetting.PrintSelected & (0x0040 + 0x0001)) ==0 )return; + } + + + //Operate History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = OperateEntryTmp.D32[d]; + } + + if(EntryTmp.fData.Body.Splite.mType == etOperate){ + switch(EntryTmp.fData.Body.Splite.Data0){ + case otPowerOff: + FillText4PowerOff(); + break; + + case otPowerOn: + FillText4PowerUp(); + break; + + case otReset: + FillText4MsgReset(); + break; + + case otMute: + FillText4MsgMute(); + break; + + case otMask: + FillText4MsgMask(); + NeedDisplayDescp =1; + break; + + case otUnMask: + FillText4MsgUnMask(); + NeedDisplayDescp =1; + break; + + case otRegiste: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + if(LanguageEnCn==0)TMyString::sAddOnStr( "开始注册设备",PrintText.body.Msg); + else TMyString::sAddOnStr( "Dev Register",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + if(LanguageEnCn==0)TMyString::sAddOnStr( "设备注册成功",PrintText.body.Msg); + else TMyString::sAddOnStr( "Registered OK",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + if(LanguageEnCn==0)TMyString::sAddOnStr( "呼叫区域机注册",PrintText.body.Msg); + else TMyString::sAddOnStr( "Call Regional Reg",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + if(LanguageEnCn==0)TMyString::sAddOnStr( "集中机呼叫注册",PrintText.body.Msg); + else TMyString::sAddOnStr( "Reg By Master ",PrintText.body.Msg); + } + break; + + case otUnRegiste: + + break; + + case otSetCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + if(LanguageEnCn==0)TMyString::sAddOnStr( "设置本机为集中机:",PrintText.body.Msg); + else TMyString::sAddOnStr( "Set Local Master:",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + if(LanguageEnCn==0)TMyString::sAddOnStr( "设置本机为区域机:",PrintText.body.Msg); + else TMyString::sAddOnStr( "Set Local Regional:",PrintText.body.Msg); + }else{ + if(LanguageEnCn==0)TMyString::sAddOnStr( "设置本机为单机:",PrintText.body.Msg); + else TMyString::sAddOnStr( "Set Stand Alone:",PrintText.body.Msg); + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + break; + + case otCfgBoard: + + break; + + case otCfgCrt: + + break; + + case otCfgPriter: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("打印机关闭",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("打印机开启",PrintText.body.Msg); + } + if(1){ + TMyString::sAddOnStr("打印:",PrintText.body.Msg); + data = 0; + if(EntryTmp.fData.Body.Splite.P0 & 0x01){ + TMyString::sAddOnStr("全部",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x02){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("火警",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x04){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x08){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("监管",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x10){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("故障",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x20){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("屏蔽",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x40){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("操作",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x80){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("其他",PrintText.body.Msg); + data++; + } + if(data == 0){ + TMyString::sAddOnStr("全部类型信息不打印",PrintText.body.Msg); + } + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("Printer Off",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Printer On",PrintText.body.Msg); + } + if(1){ + TMyString::sAddOnStr("Print:",PrintText.body.Msg); + data = 0; + if(EntryTmp.fData.Body.Splite.P0 & 0x01){ + TMyString::sAddOnStr("All",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x02){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("Fire",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x04){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("Link",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x08){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("SUPV",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x10){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("Fail",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x20){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("Mask",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x40){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("OPR",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x80){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("Other",PrintText.body.Msg); + data++; + } + if(data == 0){ + TMyString::sAddOnStr("All Type Not Print",PrintText.body.Msg); + } + } + } + break; + + case otCfgDevice: + + NeedDisplayDescp = 1; + break; + + case otCfgDateTime: + FillText4MsgDateTimeSet(); + break; + + case otCfgPermissionAllow: + + break; + + case otAllowSet: + FillText4AllowSet(); + break; + + case otAlramSetOnOff: + FillText4AlramSetOnOff(); + break; + + case otBusPadOn: + FillText4BusPadOn(); + break; + + case otBusPadOff: + FillText4BusPadOff(); + break; + + case otDirectPadManualAllowOn: + FillText4DirectPadManualAllowOn(); + break; + + case otDirectPadManualAllowOff: + FillText4DirectPadManualAllowOff(); + break; + + case otDirectPadNodeOn: + FillText4DirectPadNodeOn(); + break; + + case otDirectPadNodeOff: + FillText4DirectPadNodeOff(); + break; + + case otUserCheck: + FillText4UserCheck(); + break; + + case otLinkageGo: + FillText4LinkageGo(EntryTmp.fData.Body.Splite.Data1); + break; + + case otSetNwTime: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr( "设置各区域机日期时间",PrintText.body.Msg); + else TMyString::sAddOnStr( "Set Regionals DateTime",PrintText.body.Msg); + break; + + case otReqNwTime: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr( "向集中机请求日期时间",PrintText.body.Msg); + else TMyString::sAddOnStr( "Get DateTime",PrintText.body.Msg); + break; + + case otSelfCheck: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("自检",PrintText.body.Msg); + else TMyString::sAddOnStr("Self-Check",PrintText.body.Msg); + break; + + case otSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许",PrintText.body.Msg); + else TMyString::sAddOnStr("手动禁止",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Manual Allow",PrintText.body.Msg); + else TMyString::sAddOnStr("Manual Prohibit",PrintText.body.Msg); + } + break; + + case otSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Auto Enabled",PrintText.body.Msg); + else TMyString::sAddOnStr("Auto Disabled",PrintText.body.Msg); + } + break; + + case otRemoteSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许-集中机呼叫执行",PrintText.body.Msg); + else TMyString::sAddOnStr("手动禁止--集中机呼叫执行",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Manual Allow-By Called",PrintText.body.Msg); + else TMyString::sAddOnStr("Manual Prohibit-By Called",PrintText.body.Msg); + } + break; + + case otRemoteSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许-集中机呼叫执行",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止--集中机呼叫执行",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Auto Enabled-By Called",PrintText.body.Msg); + else TMyString::sAddOnStr("Auto Disabled--By Called",PrintText.body.Msg); + } + break; + + case otReportManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许-区域机报告",PrintText.body.Msg); + else TMyString::sAddOnStr("手动禁止-区域机报告",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Manual Allow-Slaver",PrintText.body.Msg); + else TMyString::sAddOnStr("Manual Prohibit-Slaver",PrintText.body.Msg); + } + break; + + case otReportAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许-区域机报告",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止-区域机报告",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("Auto Enabled-Slaver",PrintText.body.Msg); + else TMyString::sAddOnStr("Manual Prohibit-Slaver",PrintText.body.Msg); + } + break; + + case otFireConfirm: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 火警确认 ",PrintText.body.Msg); + else TMyString::sAddOnStr(" Fire Confirm ",PrintText.body.Msg); + NeedDisplayDescp = 1; + OperateAddConfirmMsg(1); + break; + + case otFireRemoteConfirm: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + if(LanguageEnCn==0)TMyString::sAddOnStr(" 火警远程确认 ",PrintText.body.Msg); + else TMyString::sAddOnStr(" Fire Confirm Far ",PrintText.body.Msg); + //TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, PrintText); + NeedDisplayDescp = 1; + OperateAddConfirmMsg(1); + break; + + case otFaultConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + NeedDisplayDescp = 1; + } + AddOnFaultMsg(); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 故障确认 ",PrintText.body.Msg); + else TMyString::sAddOnStr(" Fail Confirm ",PrintText.body.Msg); + OperateAddConfirmMsg(2); + break; + + case otFaultRemoteConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 故障远程确认 ",PrintText.body.Msg); + else TMyString::sAddOnStr(" Fail Confirm Far ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P2, PrintText.body.Msg); + NeedDisplayDescp = 1; + OperateAddConfirmMsg(2); + }else{ + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 故障远程确认 ",PrintText.body.Msg); + else TMyString::sAddOnStr(" Fail Confirm Far ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P2, PrintText.body.Msg); + OperateAddConfirmMsg(2); + } + break; + + case otSetSmokeSensViaCircuit: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 低",PrintText.body.Msg); + TMyString::sAddOnStr(" 回路烟感设置敏感度为 标准",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 中",PrintText.body.Msg); + TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",PrintText.body.Msg); + TMyString::sAddOnStr(" 回路烟感设置敏感度为 未定义",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 未定义",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + //TMyString::sAddOnStr( " 回路烟感设置敏感度为 低",PrintText.body.Msg); + TMyString::sAddOnStr( " Set Loop Smoke Det:Std",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + //TMyString::sAddOnStr( " 回路烟感设置敏感度为 中",PrintText.body.Msg); + TMyString::sAddOnStr( " Set Loop Smoke Det:High",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + //TMyString::sAddOnStr( " 回路烟感设置敏感度为 高",PrintText.body.Msg); + TMyString::sAddOnStr( " Set Loop Smoke Det:----",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr( " Set Loop Smoke Det:----",PrintText.body.Msg); + } + } + break; + + case otSetSmokeSensViaAddr: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 低",PrintText.body.Msg); + TMyString::sAddOnStr(" 烟感设置敏感度为 标准",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 中",PrintText.body.Msg); + TMyString::sAddOnStr(" 烟感设置敏感度为 高",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + //TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",PrintText.body.Msg); + TMyString::sAddOnStr(" 烟感设置敏感度为 未定义",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" 烟感设置敏感度为 未定义",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + //TMyString::sAddOnStr( " 回路烟感设置敏感度为 低",PrintText.body.Msg); + TMyString::sAddOnStr( " Set Smoke Detector:Std",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + //TMyString::sAddOnStr( " 回路烟感设置敏感度为 中",PrintText.body.Msg); + TMyString::sAddOnStr( " Set Smoke Detector:High",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + //TMyString::sAddOnStr( " 回路烟感设置敏感度为 高",PrintText.body.Msg); + TMyString::sAddOnStr( " Set Smoke Detector:----",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr( " Set Smoke Detector:----",PrintText.body.Msg); + } + } + NeedDisplayDescp = 1; + break; + + case otCleanUp: + FillTextWithDateTime(); + FillCtlNum(); + //aPanel->Btn[0].Caption.FromStr(" 清除回路终端设备的登记 "); + //aPanel->Btn[1].Caption.FromStr(" 清除总线盘配置 "); + //aPanel->Btn[2].Caption.FromStr(" 清除多线盘配置 "); + //aPanel->Btn[3].Caption.FromStr(" 清除所有联动表达式 "); + //aPanel->Btn[4].Caption.FromStr(" 清除本机终端设备注释 "); + //aPanel->Btn[5].Caption.FromStr(" 清除组网配置 "); + //aPanel->Btn[6].Caption.FromStr(" 清除网络加载的设备注释 "); + //aPanel->Btn[7].Caption.FromStr(" 预设描述 "); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("清除回路注册",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("清除总线盘配置",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("清除多线盘配置",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("清除所有联动表达式 ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr("清除本机终端设备注释",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 5){ + TMyString::sAddOnStr("清除组网配置",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 6){ + TMyString::sAddOnStr("清除网络加载的设备注释",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 7){ + TMyString::sAddOnStr("清除用户码及指派类型",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF0){ + TMyString::sAddOnStr("清除回路注册-中途退出",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF3){ + TMyString::sAddOnStr("清除联动关系-中途退出",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF4){ + TMyString::sAddOnStr("清除注释-中途退出",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("Clear Loop Regist",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Clear Bus Pnl Config",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("Clear Direct Config",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("Clear All Linkage Expression ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr("Clear All Endpoint Description",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 5){ + TMyString::sAddOnStr("Clear LAN Config",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 6){ + TMyString::sAddOnStr("Clear LAN Description",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 7){ + TMyString::sAddOnStr("Clear Usercode & Assigntype",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF0){ + TMyString::sAddOnStr("Blocking,Clear Loop Regist",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF3){ + TMyString::sAddOnStr("Blocking,Clear All Linkage Expressions",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0xF4){ + TMyString::sAddOnStr("Blocking,Clear Descriptions",PrintText.body.Msg); + } + } + break; + + case otLinkageExpsSaveRemove: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("保存一个联动表达式 编号:",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("删除一个联动表达式 编号:",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("Save Linkage Expression:",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("Del Linkage Expression:",PrintText.body.Msg); + } + } + ExpsInx = EntryTmp.fData.Body.Splite.P0; + ExpsInx = ExpsInx * 256; + ExpsInx = ExpsInx + EntryTmp.fData.Body.Splite.P1; + TMyString::sAddOn4Dg(ExpsInx, PrintText.body.Msg); + break; + + case otBusPadModify: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("总线盘:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr(" 按键号:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + TMyString::sAddOnStr(" 配置",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Bus Brd:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr(" Keypad:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + TMyString::sAddOnStr(" Config",PrintText.body.Msg); + } + break; + + case otDirectPadModify: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("多线盘:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr(" 配置",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Direct Brd:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr(" Config",PrintText.body.Msg); + } + break; + + case otDescpModify: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + if(EntryTmp.fData.Body.Splite.P0 <= dPORT_MAX_COUNT){ + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + if(LanguageEnCn==0)TMyString::sAddOnStr( " 回路设备描述更改 ",PrintText.body.Msg); + else TMyString::sAddOnStr( " Changed Dev Descp",PrintText.body.Msg); + NeedDisplayDescp = 1; + }else + if( (EntryTmp.fData.Body.Splite.P0 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P0 <= dADDR_DIRECTPAD_END) ){ + if(LanguageEnCn==0){ + TMyString::sAddOnStr(" 多线盘:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0-dADDR_DIRECTPAD_START+1, PrintText.body.Msg); + TMyString::sAddOnStr(" 节点:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + TMyString::sAddOnStr(" 描述更改 ",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" Direct:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0-dADDR_DIRECTPAD_START+1, PrintText.body.Msg); + TMyString::sAddOnStr(" Node:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + TMyString::sAddOnStr(" Changed Descp",PrintText.body.Msg); + } + NeedDisplayDescp = 1; + } + break; + + case otPassWdModify: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 二级密码更改",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" 三级密码更改",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 12){ + TMyString::sAddOnStr(" 系统故障,二级密码写入失败",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 13){ + TMyString::sAddOnStr(" 系统故障,三级密码写入失败",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" Change Password II",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" Change Password III",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 12){ + TMyString::sAddOnStr(" Sys Fault,Fail Password II",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 13){ + TMyString::sAddOnStr(" Sys Fault,Fail Password III",PrintText.body.Msg); + } + } + break; + + case otRegisterByManual: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + TMyString::sAddOnStr("~",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P2, PrintText.body.DateAddr); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1){ + TMyString::sAddOnStr(" 手动注册,类型:",PrintText.body.Msg); + TMyString::sAddOnStr(StrTypeShortName[EntryTmp.fData.Body.Splite.dType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" 手动注册,删除",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1){ + TMyString::sAddOnStr(" Manual Reg Type:",PrintText.body.Msg); + TMyString::sAddOnStr(StrTypeShortNameEn[EntryTmp.fData.Body.Splite.dType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" Manual Reg Delete",PrintText.body.Msg); + } + } + break; + + case otAddRemoveNwCtl: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 手动添加区域机 ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 手动删除区域机 ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" 手动添加集中机 ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr(" 手动删除集中机 ",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" Manual Add Slaver ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" Manual Del Slaver ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" Manual Add Master ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr(" Manual Del Master ",PrintText.body.Msg); + } + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + break; + + case otRegCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("本集中机注册区域机数量:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("本集中机清除联机区域机",PrintText.body.Msg); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("本区域机联机注册,集中机号:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("本区域机联机清除,集中机号:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("设置网络共存集中机数量:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("清除网络共存集中机:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + } + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("Slaver Count In Master:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Cleared Slavers In Master",PrintText.body.Msg); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("Inject Num Of Master::",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Cleared Master Conection",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + } + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + if(EntryTmp.fData.Body.Splite.P1){ + TMyString::sAddOnStr("Set Master Count:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Clear iConnected Master",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + } + } + } + break; + + case otClearNetworkCfg: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 清除所有区域机",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 清除挂载的集中机",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" Clear All Slaver",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" Clear Link Master",PrintText.body.Msg); + } + } + break; + + case otBroadcastVa: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0)TMyString::sAddOnStr("设置广播与声光 路径:",PrintText.body.Msg); + else TMyString::sAddOnStr("Set BCT & SL Path:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr("-",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" 并行模式",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 交替模式",PrintText.body.Msg); + } + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" Parallel Mode",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" Alternate Mode",PrintText.body.Msg); + } + } + break; + case otSetAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("自动允许,手动允许",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动允许,手动禁止",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("自动禁止,手动允许",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止,手动禁止",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("En Auto,En Manual",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("En Auto,Dis Manual",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("Dis Auto,En Manual",PrintText.body.Msg); + else TMyString::sAddOnStr("Dis Auto,Dis Manual",PrintText.body.Msg); + } + break; + case otRemoteSetAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("自动允许-手动允许-集中机呼叫执行",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动允许-手动禁止-集中机呼叫执行",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("自动禁止-手动允许-集中机呼叫执行",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止-手动禁止-集中机呼叫执行",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("En Auto,En Manual(Master Call)",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("En Auto,Dis Manual(Master Call)",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 2)TMyString::sAddOnStr("Dis Auto,En Manual(Master Call)",PrintText.body.Msg); + else TMyString::sAddOnStr("Dis Auto,Dis Manual(Master Call)",PrintText.body.Msg); + } + break; + case otReportAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(LanguageEnCn==0){ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("自动允许-手动允许-区域机报告",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动允许-手动禁止-区域机报告",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("自动禁止-手动允许-区域机报告",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止-手动禁止-区域机报告",PrintText.body.Msg); + }else{ + if(EntryTmp.fData.Body.Splite.Data1 == 3)TMyString::sAddOnStr("En Auto,En Manual(Slaver Report)",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("En Auto,Dis Manual(Slaver Report)",PrintText.body.Msg); + else if(EntryTmp.fData.Body.Splite.Data1 == 1)TMyString::sAddOnStr("Dis Auto,En Manual(Slaver Report)",PrintText.body.Msg); + else TMyString::sAddOnStr("Dis Auto,Dis Manual(Slaver Report)",PrintText.body.Msg); + } + break; + + default : break; + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(OperateEntryTmp, NeedDisplayDescp); + SetBufInsert(); + } +} + +void TDoPrint::GetDescpEntry(TRecordCommon DescpEntryTmp) +{ + volatile unsigned int aAddr ,i , aCsum, iP0; + unsigned int aCn, aP0, aP1; + + if(DescpEntryTmp.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = DescpEntryTmp.Splite.P0; + aP1 = DescpEntryTmp.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=7; i<15; i++){ + EntryTmp.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryTmp.D32[i] = 0; + } + } + }else + if( (DescpEntryTmp.Splite.PCtlNum) && (DescpEntryTmp.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = EntryTmp.fData.Body.Splite.PCtlNum -1; + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + EntryTmp.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryTmp.D32[i] = 0; + } + } + }else{ + for(i=7; i<15; i++){ + EntryTmp.D32[i] = 0; + } + } +} + +void TDoPrint::FillFaultText(TRecordCommon FaultEntryTmp, int aForce) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + + NeedDisplayDescp = 0; + + if(aForce == 0){ + if(PriterSetting.OnOff ==0)return; + if( (PriterSetting.PrintSelected & (0x0010 + 0x0001)) ==0)return; + } + + + //Fault History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = FaultEntryTmp.D32[d]; + } + EntryTmp.fData.UserCode = FaultEntryTmp.Splite.UserCode; + + FillTextWithDateTime(); + + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + + /* + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + PrintText[18] = e + '0'; + e = data % 10; + PrintText[19] = e + '0'; + PrintText[20] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + PrintText[21] = e + '0'; + e = data % 10; + PrintText[22] = e + '0'; + PrintText[23] = '-'; + + PrintText[24] = '\0'; + */ + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xC0){ + if(LanguageEnCn==0){ + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("总线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + else TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("直线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + else TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + } + }else{ + TMyString::sAddOnStr("Fail ",PrintText.body.Msg); + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("BudPad Brd ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" Offline",PrintText.body.Msg); + else TMyString::sAddOnStr(" Recover",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("DirectPad Brd ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" Offline",PrintText.body.Msg); + else TMyString::sAddOnStr(" Recover",PrintText.body.Msg); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xD0){ + if(LanguageEnCn==0){ + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + TMyString::sAddOnStr("设备故障 ",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Fail ",PrintText.body.Msg); + TMyString::sAddOnStr("Dev Fail ",PrintText.body.Msg); + } + aType = EntryTmp.fData.Body.Splite.Data0; + if(aType < 32){ + if( (aType == 15) || (aType == 16) ){ + TMyString::sAddOn2Dg(MainCtl.fData.Split.MyNum, PrintText.body.Msg); + TMyString::sAddOnStr(" ", PrintText.body.Msg); + } + if(LanguageEnCn==0)TMyString::sAddOnStr(StrDevFaultType[aType],PrintText.body.Msg); + else TMyString::sAddOnStr(StrDevFaultTypeEn[aType],PrintText.body.Msg); + }else{ + if(LanguageEnCn==0)TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + else TMyString::sAddOnStr("Unknown",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + if( (aType == 15) || (aType == 16) ){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 通讯故障",PrintText.body.Msg); + else TMyString::sAddOnStr(" Comm Fail",PrintText.body.Msg); + }else + if( (aType == 19) || (aType == 20) || (aType == 21) ){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + } + if(LanguageEnCn==0)TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + else TMyString::sAddOnStr(" Recover",PrintText.body.Msg); + }else{ + if( (aType == 15) || (aType == 16) ){ + //TMyString::sAddOnStr(StrDevFaultType[aType],PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + if(LanguageEnCn==0)TMyString::sAddOnStr(" 通讯故障",PrintText.body.Msg); + else TMyString::sAddOnStr(" Comm Fail",PrintText.body.Msg); + //if(EntryTmp.fData.Body.Splite.mType > 200){ + // TMyString::sAddOnStr("通讯故障条目数:多于200",PrintText.body.Msg); + //}else{ + // TMyString::sAddOnStr("通讯故障条目数:",PrintText.body.Msg); + // TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.mType, PrintText.body.Msg); + //} + }else + if( (aType == 19) || (aType == 20) || (aType == 21) || (aType == 23) ){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xE0){ + //Cir Error + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + //TMyString::sAddOnStr("-",PrintText.body.DateAddr); + if(LanguageEnCn==0){ + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr("回路故障-恢复",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("回路故障",PrintText.body.Msg); + } + }else{ + TMyString::sAddOnStr("Fail ",PrintText.body.Msg); + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr("Loop Fail-Revocer",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Loop Fail",PrintText.body.Msg); + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + if(LanguageEnCn==0){ + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + TMyString::sAddOnStr("板卡故障 ",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Fail ",PrintText.body.Msg); + TMyString::sAddOnStr("Brd Fail ",PrintText.body.Msg); + } + aType = EntryTmp.fData.Body.Splite.Data0; + if( (aType == TBoardFaultType::LoopMotherBoard) || + (aType == TBoardFaultType::RegisteredData) || + (aType == TBoardFaultType::MaskedData) || + (aType == TBoardFaultType::StorageEpDType) || + (aType == TBoardFaultType::StorageEpAuxId) || + (aType == TBoardFaultType::StorageEpArea) || + (aType == TBoardFaultType::StorageEpAssignedType) || + (aType == TBoardFaultType::StorageEpSignalType) || + (aType == TBoardFaultType::StorageDirectPadCfg) || + (aType == TBoardFaultType::StoragePortDpSet) || + (aType == TBoardFaultType::StorageBusPadCfg) ){ + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1,PrintText.body.Msg); + TMyString::sAddOnStr(" ",PrintText.body.Msg); + }else + if( (aType == TBoardFaultType::StorageLinkExpressionPart1) || + (aType == TBoardFaultType::StorageLinkExpressionPart2) || + (aType == TBoardFaultType::StorageLinkExpressionPart3) || + (aType == TBoardFaultType::StorageLinkExpressionPart4) || + (aType == TBoardFaultType::StorageLinkExpressionPart5) || + (aType == TBoardFaultType::StorageLinkExpressionPart6) || + (aType == TBoardFaultType::StorageLinkExpressionPart7) || + (aType == TBoardFaultType::StorageLinkExpressionPart8) || + (aType == TBoardFaultType::StorageLinkExpressionPart9) ){ + unsigned short tInx = aType - static_cast(TBoardFaultType::StorageLinkExpressionPart1); + tInx = tInx * 256 + EntryTmp.fData.Body.Splite.P1; + TMyString::sAddOn4Dg(tInx % 10000,PrintText.body.Msg); + TMyString::sAddOnStr(" ",PrintText.body.Msg); + } + if(LanguageEnCn==0){ + if(aType < TBoardFaultType::MaxValue){ + TMyString::sAddOnStr(StrBrdFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + }else{ + //TMyString::sAddOnStr(" 发生",PrintText); + } + }else{ + if(aType < TBoardFaultType::MaxValue){ + TMyString::sAddOnStr(StrBrdFaultTypeEn[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Unknown",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr(" Revover",PrintText.body.Msg); + }else{ + //TMyString::sAddOnStr(" 发生",PrintText); + } + } + }else{ + //EpError + NeedDisplayDescp = 0; + + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + /* + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + PrintText[24] = e + '0'; + d = data/10; + e = d % 10; + PrintText[25] = e + '0'; + e = data % 10; + PrintText[26] = e + '0'; + PrintText[27] = ' '; + PrintText[28] = '\0'; + */ + if(LanguageEnCn==0)TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + else TMyString::sAddOnStr("Fail ",PrintText.body.Msg); + //TextAddPst = GetPrintTextLen(); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + data = 0; + if( (aP0 >0) && (aP0 <=40) ){ + //data = Port[aP0-1].UcList[aP1-1].Full; + data = EntryTmp.fData.UserCode; + TMyString::sAddOn8Dg(data, PrintText.body.Msg); + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0<=dADDR_DIRECTPAD_END) ){ + if( (aP1>=0) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + //data = DirectCtlBoard[aP0-dADDR_DIRECTPAD_START].UcList[aP1-1].Full; + data = EntryTmp.fData.UserCode; + TMyString::sAddOn8Dg(data, PrintText.body.Msg); + } + } + /* + d = data/10000; + e = d % 10; + PrintText[TextAddPst] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[TextAddPst+1] = e + '0'; + d = data/100; + e = d % 10; + PrintText[TextAddPst+2] = e + '0'; + d = data/10; + e = d % 10; + PrintText[TextAddPst+3] = e + '0'; + e = data % 10; + PrintText[TextAddPst+4] = e + '0'; + PrintText[TextAddPst+5] = ' '; + + PrintText[TextAddPst+6] = 0; + */ + TMyString::sAddOnStr(" ",PrintText.body.Msg); + + aType = EntryTmp.fData.Body.Splite.Data0; + if(LanguageEnCn==0){ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知故障",PrintText.body.Msg); + } + + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("-恢复",PrintText.body.Msg); + }else{ + //TMyString::sAddOnStr("-发生",PrintText); + } + }else{ + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultTypeEn[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Unknown",PrintText.body.Msg); + } + + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("-Revocer",PrintText.body.Msg); + }else{ + //TMyString::sAddOnStr("-发生",PrintText); + } + } + + NeedDisplayDescp = 1; + if(LanguageEnCn==0){ + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",PrintText.body.Msg); + } + }else{ + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortNameEn[aType],PrintText.body.Msg); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("Direct Keypad Node ",PrintText.body.Msg); + } + } + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(FaultEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::FillLinkageText(TRecordCommon LinkageEntryTmp, int aForce) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + + NeedDisplayDescp = 0; + + if(aForce ==0){ + if(PriterSetting.OnOff ==0)return; + if( (PriterSetting.PrintSelected & (0x0004 + 0x0001)) == 0)return; + } + + + //Linkage History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = LinkageEntryTmp.D32[d]; + } + EntryTmp.fData.UserCode = LinkageEntryTmp.Splite.UserCode; + + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + if(LanguageEnCn==0)TMyString::sAddOnStr("联动 ",PrintText.body.Msg); + else TMyString::sAddOnStr("Link ",PrintText.body.Msg); + //TextAddPst = GetPrintTextLen(); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + data = 0; + if( (aP0 >0) && (aP0 <=40) ){ + //data = Port[aP0-1].UcList[aP1-1].Full; + data = EntryTmp.fData.UserCode; + TMyString::sAddOn8Dg(data, PrintText.body.Msg); + }else + if( (aP0 >dADDR_DIRECTPAD_START) && (aP0<=dADDR_DIRECTPAD_END) ){ + if( (aP1>=0) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + //data = DirectCtlBoard[aP0-dADDR_DIRECTPAD_START].UcList[aP1-1].Full; + data = EntryTmp.fData.UserCode; + TMyString::sAddOn8Dg(data, PrintText.body.Msg); + } + } + /* + d = data/10000; + e = d % 10; + PrintText[TextAddPst] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[TextAddPst+1] = e + '0'; + d = data/100; + e = d % 10; + PrintText[TextAddPst+2] = e + '0'; + d = data/10; + e = d % 10; + PrintText[TextAddPst+3] = e + '0'; + e = data % 10; + PrintText[TextAddPst+4] = e + '0'; + PrintText[TextAddPst+5] = ' '; + + PrintText[TextAddPst+6] = 0; + */ + + aP0 = EntryTmp.fData.Body.Splite.P0; + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0){ + if( (aP0 >0) && (aP0 <=40) ){ + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + NeedDisplayDescp = 1; + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if(aType){ + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("多线盘节点",PrintText.body.Msg); + } + NeedDisplayDescp = 1; + } + }else{ + if( (aP0 >0) && (aP0 <=40) ){ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],PrintText.body.Msg); + NeedDisplayDescp = 1; + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + if(aType){ + TMyString::sAddOnStr(StrTypeShortNameEn[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("Direct Node",PrintText.body.Msg); + } + NeedDisplayDescp = 1; + } + } + + data = EntryTmp.fData.Body.Splite.iByte0; + if(LanguageEnCn==0){ + if(data == 0x01){ + TMyString::sAddOnStr("-启动",PrintText.body.Msg); + }else + if(data == 0x02){ + TMyString::sAddOnStr("-区声光启动",PrintText.body.Msg); + }else + if(data == 0x03){ + TMyString::sAddOnStr("-反馈",PrintText.body.Msg); + }else + if(data == 0x04){ + TMyString::sAddOnStr("-反馈缺失",PrintText.body.Msg); + }else + if(data == 0x05){ + TMyString::sAddOnStr("-启动",PrintText.body.Msg); + }else + if(data == 0x06){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-声光启动",PrintText.body.Msg); + }else + + if(data == 0x07){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-应答消钮",PrintText.body.Msg); + }else + if(data == 0xB1){ + TMyString::sAddOnStr("-停止",PrintText.body.Msg); + }else + if(data == 0xB3){ + TMyString::sAddOnStr("-反馈取消",PrintText.body.Msg); + }else + if(data == 0xB5){ + TMyString::sAddOnStr("-停止",PrintText.body.Msg); + }else + if(data == 0xB6){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-声光停止",PrintText.body.Msg); + }else + if(data == 0xB7){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-应答消钮取消",PrintText.body.Msg); + } + }else{ + if(data == 0x01){ + TMyString::sAddOnStr("-Act",PrintText.body.Msg); + }else + if(data == 0x02){ + TMyString::sAddOnStr("-Zone Alram On",PrintText.body.Msg); + }else + if(data == 0x03){ + TMyString::sAddOnStr("-FB",PrintText.body.Msg); + }else + if(data == 0x04){ + TMyString::sAddOnStr("-FB Miss",PrintText.body.Msg); + }else + if(data == 0x05){ + TMyString::sAddOnStr("-Act",PrintText.body.Msg); + }else + if(data == 0x06){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("Link",PrintText.body.Msg); + TMyString::sAddOnStr("-Alram On",PrintText.body.Msg); + }else + + if(data == 0x07){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("Link",PrintText.body.Msg); + TMyString::sAddOnStr("-Hydrant Ack",PrintText.body.Msg); + }else + if(data == 0xB1){ + TMyString::sAddOnStr("-Stop",PrintText.body.Msg); + }else + if(data == 0xB3){ + TMyString::sAddOnStr("-FB Cancel",PrintText.body.Msg); + }else + if(data == 0xB5){ + TMyString::sAddOnStr("-Stop",PrintText.body.Msg); + }else + if(data == 0xB6){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("Link",PrintText.body.Msg); + TMyString::sAddOnStr("-Alram Stop",PrintText.body.Msg); + }else + if(data == 0xB7){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("Link",PrintText.body.Msg); + TMyString::sAddOnStr("-Hydrant Ack Cancel",PrintText.body.Msg); + } + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(LinkageEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::FillFireText(TRecordCommon FireEntryTmp, int aForce) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + unsigned char IsFrist; + + NeedDisplayDescp = 0; + + if(aForce ==0){ + if(PriterSetting.OnOff == 0)return; + if( (PriterSetting.PrintSelected & (0x0002 + 0x0001)) ==0 )return; + } + + //Fire History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = FireEntryTmp.D32[d]; + } + EntryTmp.fData.UserCode = FireEntryTmp.Splite.UserCode; + + IsFrist = EntryTmp.fData.Body.Splite.Data1; + + FillTextWithDateTime(); + + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if((aP0)&&(aP0<=40)){ + + if(LanguageEnCn==0){ + if(IsFrist)TMyString::sAddOnStr("首火警 ",PrintText.body.Msg); + else TMyString::sAddOnStr("火警 ",PrintText.body.Msg); + }else{ + if(IsFrist)TMyString::sAddOnStr("FirstFire ",PrintText.body.Msg); + else TMyString::sAddOnStr("Fire ",PrintText.body.Msg); + } + //TextAddPst = GetPrintTextLen(); + + data = EntryTmp.fData.UserCode; + TMyString::sAddOn8Dg(data, PrintText.body.Msg); + + aP0--; + aP1--; + + NeedDisplayDescp = 1; + /* + d = data/10000; + e = d % 10; + PrintText[TextAddPst] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[TextAddPst+1] = e + '0'; + d = data/100; + e = d % 10; + PrintText[TextAddPst+2] = e + '0'; + d = data/10; + e = d % 10; + PrintText[TextAddPst+3] = e + '0'; + e = data % 10; + PrintText[TextAddPst+4] = e + '0'; + PrintText[TextAddPst+5] = ' '; + + PrintText[TextAddPst+6] = 0; + */ + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],PrintText.body.Msg); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && ( aP0 <= dADDR_DIRECTPAD_END)){ + NeedDisplayDescp = 1; + if( (aP1>=0) && (aP1<=dDIRECTCTL_KEY_MAX_COUNT) ){ + //data = DirectCtlBoard[aP0-dADDR_DIRECTPAD_START].UcList[aP1-1].Full; + data = EntryTmp.fData.UserCode; + TMyString::sAddOn8Dg(data, PrintText.body.Msg); + } + } + /* + if( (aP0 >0) && (aP0 < 64) ){ + if(aP1 >0){ + if(aP0 < 40){ + aP0--; + data = EpDev[aP0][aP1-1].fData.Split.UserCode; + }else + if(aP0 < 48){ + aP0-=41; + data = HandCtlBoard[aP0].UserCodeList[aP1-1]; + }else + if(aP0 < 56){ + aP0-=49; + data = 0;//DirectCtlBoard[aP0].UserCodeList[aP1-1]; + } + } + } + d = data/10000; + e = d % 10; + PrintText[28] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[29] = e + '0'; + d = data/100; + e = d % 10; + PrintText[30] = e + '0'; + d = data/10; + e = d % 10; + PrintText[31] = e + '0'; + e = data % 10; + PrintText[32] = e + '0'; + PrintText[33] = ' '; + + PrintText[34] = 0; + + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText); + */ + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(FireEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::FillSvText(TRecordCommon SvEntryTmp, int aForce) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + + NeedDisplayDescp = 0; + + if(aForce ==0){ + if(PriterSetting.OnOff == 0)return; + if( (PriterSetting.PrintSelected & (0x0008 + 0x0001)) ==0 )return; + } + + //Fire History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = SvEntryTmp.D32[d]; + } + EntryTmp.fData.UserCode = SvEntryTmp.Splite.UserCode; + + FillTextWithDateTime(); + + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + if(LanguageEnCn==0)TMyString::sAddOnStr("监管 ",PrintText.body.Msg); + else TMyString::sAddOnStr("SUPV ",PrintText.body.Msg); + //TextAddPst = GetPrintTextLen(); + + data = EntryTmp.fData.UserCode; + TMyString::sAddOn8Dg(data, PrintText.body.Msg); + + aType = EntryTmp.fData.Body.Splite.dType; + if(LanguageEnCn==0)TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + else TMyString::sAddOnStr(StrTypeShortNameEn[aType],PrintText.body.Msg); + + data = EntryTmp.fData.Body.Splite.iByte0; + if(data == 0x01){ + //TMyString::sAddOnStr("-启动",PrintText); + }else + if(data == 0x02){ + //TMyString::sAddOnStr("-区声光启动",PrintText); + }else + if(data == 0x03){ + //TMyString::sAddOnStr("-应答",PrintText); + }else + if(data == 0x04){ + //TMyString::sAddOnStr("-应答缺失",PrintText); + } + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + NeedDisplayDescp = 1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + NeedDisplayDescp = 1; + } + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(SvEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::Init() +{ + unsigned int i,a; + + State = 0; + //Buf.WriteInx = 0; + //Buf.ReadInx = 0; + + for(a=0;a<3;a++){ + for(i=0;i<128;i++){ + Buf.wEntry[a].D8[i] = 0; + } + } + for(i=0;i<64;i++){ + PrintText.body.DateAddr[i] = 0; + PrintText.body.Msg[i] = 0; + PrintText.body.Dscp[i] = 0; + } +} + +void TDoPrint::ReInit() +{ + unsigned int i,a; + + State = 0; + Buf.WriteInx = 0; + Buf.ReadInx = 0; + + for(a=0;a<3;a++){ + for(i=0;i<128;i++){ + Buf.wEntry[a].D8[i] = 0; + } + } + for(i=0;i<64;i++){ + PrintText.body.DateAddr[i] = 0; + PrintText.body.Msg[i] = 0; + PrintText.body.Dscp[i] = 0; + } +} + +void TDoPrint::ClearPrintText() +{ + unsigned int i; + + for(i=0;i<64;i++){ + PrintText.body.DateAddr[i] = 0; + PrintText.body.Msg[i] = 0; + PrintText.body.Dscp[i] = 0; + } +} + +void TDoPrint::Print() +{ + ; +} + +void TDoPrint::TryGetState() +{ + //Trigger to Sen a Read State Cmd +} + +unsigned int TDoPrint::GetPrintState() +{ + return printer_is_busy(); +} + +void TDoPrint::SetBufInsertSequence() +{ + volatile unsigned int i = 0,a = 0; + volatile unsigned int line = 0; + volatile unsigned int len = 0; + volatile unsigned int zh_num = 0; + + for(i=0;i<32;i++){ + Buf.wEntry[0].D32[i] = 0; + Buf.wEntry[1].D32[i] = 0; + Buf.wEntry[2].D32[i] = 0; + } + + for(a=0;a<3;a++){ + len = GetPrintTextLen(PrintText.Text[a]); + if(len){ + if(len%32) + line = len/32 + 1; + else + line = len/32; + + if(1 == line){ + for(i=0;i 0x7F)zh_num++; + else zh_num = 0; + } + if(zh_num & 0x01){ + for(i = 0;i < (len-32+1);i++) + PrintText.Text[a][len-i] = PrintText.Text[a][len-1-i]; + PrintText.Text[a][31] = ' '; + len+=1; + } + + if(64 == len){ + for(i=0;i<32;i++){ + Buf.wEntry[a].Body.Text[i] = PrintText.Text[a][i+32]; + } + for(i=0;i<32;i++){ + Buf.wEntry[a].Body.Text[i+32] = PrintText.Text[a][i]; + } + }else + if(len < 64){ + for(i=0;i<(len-32);i++){ + Buf.wEntry[a].Body.Text[i] = PrintText.Text[a][i+32]; + } + Buf.wEntry[a].Body.Text[len-32] = '\n'; + for(i=0;i<32;i++){ + Buf.wEntry[a].Body.Text[len-32+1+i] = PrintText.Text[a][i]; + } + len+=1; + } + Buf.wEntry[a].Body.Len = len; + Buf.wEntry[a].Body.Text[Buf.wEntry[a].Body.Len] = 0; + } + } + } +} + +void TDoPrint::BufInsert() +{ + volatile unsigned int aAddr, iLen, i; + //------------------------------------line 1------------------------------------------ + if(Buf.wEntry[2].Body.Len){ + Buf.WriteInx++; + + if(Buf.WriteInx >= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + iLen = Buf.wEntry[2].Body.Len / 4 + 1; + if(iLen >31)iLen = 31; + for(i=0; i= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + + iLen = Buf.wEntry[1].Body.Len / 4 + 1; + if(iLen >31)iLen = 31; + for(i=0; i= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + iLen = Buf.wEntry[0].Body.Len / 4 + 1; + if(iLen >31)iLen = 31; + for(i=0; i= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + iLen = 36 / 4; + if(iLen >31)iLen = 31; + for(i=0; i 16){ + set_print_text(&Buf.rEntry.Body.Text[Sections.DoingInx*16],16); + Buf.rEntry.Body.Len-=16; + }else{ + set_print_text(&Buf.rEntry.Body.Text[Sections.DoingInx*16],Buf.rEntry.Body.Len); + Buf.rEntry.Body.Len = 0; + } + + Sections.DoingInx++; + if(Sections.DoingInx >= Sections.sCount){ + Sections.oSequence = 0; + } + }else{ + Sections.oSequence = 0; + } +} + +void TDoPrint::BufFillPrintingBuf() +{ + unsigned int aAddr, i, iLen; + + Buf.ReadInx++; + if(Buf.ReadInx >= PrintBuf_Count)Buf.ReadInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.ReadInx * PrintEntry_Size); + + Sections.AllTextCount = *(volatile unsigned int *)(aAddr + (31*4)); + Buf.rEntry.Body.Len = Sections.AllTextCount; + + if(Sections.AllTextCount % 4){ + iLen = Sections.AllTextCount / 4 +1; + }else{ + iLen = Sections.AllTextCount / 4; + } + + if(iLen >30)iLen = 30; + for(i=0; i 9){//100ms + delay_tick = 0; + oProcess(); + } +} + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/DoPrint.h b/MyCode/src/DoPrint.h new file mode 100644 index 0000000..032e396 --- /dev/null +++ b/MyCode/src/DoPrint.h @@ -0,0 +1,129 @@ +#ifndef DOPRINT_H_ +#define DOPRINT_H_ + +#include "gvalue.h" +#include "record.h" + +//dAddrSdram_PrintBuf + +#define PrintEntry_Size 128 +#define PrintBuf_Count 8000 + +typedef union{ + unsigned int D32[32]; + unsigned char D8[PrintEntry_Size]; + struct{ + char Text[124]; + unsigned int Len; + }Body; +}TMsgEntry; + +typedef union{ + char Text[3][64]; + struct{ + char DateAddr[64]; + char Msg[64]; + char Dscp[64]; + }body; +}TPrintText; + +class TDoPrint{ + public: + TRecordEntry EntryTmp; + + unsigned char State; + TPrintText PrintText; + + struct{ + int WriteInx; + int ReadInx; + unsigned char Addr; + TMsgEntry wEntry[3]; + TMsgEntry rEntry; + int wEntryTextLen; + }Buf; + struct{ + int AllTextCount; + int sCount; + int DoingInx; + int oSequence; + }Sections; + + int IsTryGetState; + + unsigned char RecData[12]; + TDateTimeBytes DateTimeCovered; + public: + TDoPrint(){}; + void Init(); + void ReInit(); + + int GetPrintTextEndPst(char * pText); + unsigned int GetPrintTextLen(char * pText); + void StrcatText(char * pSrc,char * pAdd); + + void FillTextWithDateTime(); + void FillCtlNum(); + void FillCtlNumNoSpace(); + void FillTextWithPath(); + void FillTextWithDType(); + + void FillText4PowerOff(); + void FillText4PowerUp(); + void FillText4MsgReset(); + void FillText4MsgMute(); + void FillText4MsgMask(); + void FillText4MsgUnMask(); + void FillText4MsgDateTimeSet(); + void FillText4AllowSet(); + void FillText4AlramSetOnOff(); + void FillText4BusPadOn(); + void FillText4BusPadOff(); + void FillText4DirectPadManualAllowOn(); + void FillText4DirectPadManualAllowOff(); + void FillText4DirectPadNodeOn(); + void FillText4DirectPadNodeOff(); + void FillText4UserCheck(); + void FillText4LinkageGo(unsigned char Data1); + void AddOnFaultMsg(void); + void OperateAddConfirmMsg(int NeedDrawCfg); + + void FillOperateText(TRecordCommon OperateEntryTmp, int aForce =0); + void FillFaultText(TRecordCommon FaultEntryTmp, int aForce =0); + void FillLinkageText(TRecordCommon LinkageEntryTmp, int aForce =0); + void FillFireText(TRecordCommon FireEntryTmp, int aForce =0); + void FillSvText(TRecordCommon SvEntryTmp, int aForce =0); + + void GetDescpEntry(TRecordCommon DescpEntryTmp); + void DescpTextBufInsert(TRecordCommon aEntryTmp, unsigned int Descp); + + void ClearPrintText(); + void Print(); + void DescpTextBufInsertByAssign(char *p); + void PrintHistory(int MsgType, TRecordCommon aEntryTmp, char *pDescp); + + void TryGetState(); + unsigned int GetPrintState(); + + void SetBufInsertSequence(); + void BufInsert(); + void SetBufInsert(); + void PrintSection(); + void BufFillPrintingBuf(); + void oProcess(); + void iProcess(); + + void Task10Ms(); +}; + + + + + + + + + + + +#endif diff --git a/MyCode/src/DoPrint_.cpp b/MyCode/src/DoPrint_.cpp new file mode 100644 index 0000000..7d7b960 --- /dev/null +++ b/MyCode/src/DoPrint_.cpp @@ -0,0 +1,1842 @@ +#include "my_string.h" +#include "ProtoInnerCan.h" +#include "RuntimeData.h" +#include "DoPrint.h" + +extern "C"{ + #include "uart_printer_drv.h" +} + +//时间 地址 +//信息类型 用户码 设备类型 +//描述 + +const char TextHead[] = "\n--------------------------------\n\n\n\n"; + +int TDoPrint::GetPrintTextEndPst(char * pText) +{ + unsigned int i; + if(pText[0] == 0)return -1; + for(i=1;i= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("总线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,PrintText.body.Msg); + TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("多线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,PrintText.body.Msg); + TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xD0){ + FillCtlNum(); + TMyString::sAddOnStr("设备故障 ",PrintText.body.Msg); + aType = EntryTmp.fData.Body.Splite.P2; + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + } + + TMyString::sAddOnStr(" ",PrintText.body.Msg); + if( (aType == 15) || (aType == 16) ){ + TMyString::sAddOnStr(StrDevFaultType[aType],PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.mType > 200){ + TMyString::sAddOnStr("通讯故障条目数:多于200",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("通讯故障条目数:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.mType, PrintText.body.Msg); + } + } + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xE0){ + FillCtlNum(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0,PrintText.body.DateAddr); + TMyString::sAddOnStr("回路故障",PrintText.body.Msg); + + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + FillCtlNum(); + TMyString::sAddOnStr("板卡故障 ",PrintText.body.Msg); + aType = EntryTmp.fData.Body.Splite.P2; + if(aType < 32){ + TMyString::sAddOnStr(StrBrdFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + } + }else{ + //EpError + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + TMyString::sAddOnStr(" ",PrintText.body.DateAddr); + + aType = EntryTmp.fData.Body.Splite.P2; + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知故障",PrintText.body.Msg); + } + } +} + +void TDoPrint::DescpTextBufInsert(TRecordCommon aEntryTmp, unsigned int Descp) +{ + unsigned int d; + + if(Descp){ + GetDescpEntry(aEntryTmp); + for(d=0;d<((15-7)*4);d++){ + PrintText.body.Dscp[d] = EntryTmp.D8[7*4+d]; + if(0 == PrintText.body.Dscp[d])break; + } + PrintText.body.Dscp[d] = '\n'; + PrintText.body.Dscp[d+1] = 0; + } +} + +void TDoPrint::DescpTextBufInsertByAssign(char *p) +{ + unsigned int d; + if(p != nullptr){ + for(d=0;d<((15-7)*4);d++){ + PrintText.body.Dscp[d] = p[d]; + if(0 == PrintText.body.Dscp[d])break; + } + PrintText.body.Dscp[d] = '\n'; + PrintText.body.Dscp[d+1] = 0; + } +} + +void TDoPrint::FillOperateText(TRecordCommon OperateEntryTmp) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned int ExpsInx; + + int NeedDisplayDescp; + NeedDisplayDescp = 0; + + //Operate History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = OperateEntryTmp.D32[d]; + } + + if(EntryTmp.fData.Body.Splite.mType == etOperate){ + switch(EntryTmp.fData.Body.Splite.Data0){ + case otPowerOff: + FillText4PowerOff(); + break; + + case otPowerOn: + FillText4PowerUp(); + break; + + case otReset: + FillText4MsgReset(); + break; + + case otMute: + FillText4MsgMute(); + break; + + case otMask: + FillText4MsgMask(); + NeedDisplayDescp =1; + break; + + case otUnMask: + FillText4MsgUnMask(); + NeedDisplayDescp =1; + break; + + case otRegiste: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("开始注册设备",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("设备注册成功",PrintText.body.Msg); + } + break; + + case otUnRegiste: + + break; + + case otSetCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("设置本机为集中机:",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("设置本机为区域机:",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("设置本机为单机:",PrintText.body.Msg); + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + break; + + case otCfgBoard: + + break; + + case otCfgCrt: + + break; + + case otCfgPriter: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + if(EntryTmp.fData.Body.Splite.P0 == 0){ + TMyString::sAddOnStr("打印设置:禁止打印",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.P0 == 1){ + TMyString::sAddOnStr("打印设置:即时打印",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.P0 == 2){ + TMyString::sAddOnStr("打印设置:即时打印,不含电话",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.P0 == 3){ + TMyString::sAddOnStr("打印设置:即时打印,只火警打印",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.P0 == 4){ + TMyString::sAddOnStr("打印设置:手动打印",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("打印设置:无效设定,默认为即时打印",PrintText.body.Msg); + } + }else{ + TMyString::sAddOnStr("打印:",PrintText.body.Msg); + data = 0; + if(EntryTmp.fData.Body.Splite.P0 & 0x01){ + TMyString::sAddOnStr("火警",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x02){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("故障",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x04){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("监管",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x08){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("启动",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x10){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("反馈",PrintText.body.Msg); + data++; + } + if(EntryTmp.fData.Body.Splite.P0 & 0x20){ + if(data)TMyString::sAddOnStr("+",PrintText.body.Msg); + TMyString::sAddOnStr("操作",PrintText.body.Msg); + data++; + } + if(data == 0){ + TMyString::sAddOnStr("全部类型信息不打印",PrintText.body.Msg); + } + } + break; + + case otCfgDevice: + + NeedDisplayDescp = 1; + break; + + case otCfgDateTime: + FillText4MsgDateTimeSet(); + break; + + case otCfgPermissionAllow: + + break; + + case otAllowSet: + FillText4AllowSet(); + break; + + case otAlramSetOnOff: + FillText4AlramSetOnOff(); + break; + + case otBusPadOn: + FillText4BusPadOn(); + break; + + case otBusPadOff: + FillText4BusPadOff(); + break; + + case otDirectPadManualAllowOn: + FillText4DirectPadManualAllowOn(); + break; + + case otDirectPadManualAllowOff: + FillText4DirectPadManualAllowOff(); + break; + + case otDirectPadNodeOn: + FillText4DirectPadNodeOn(); + break; + + case otDirectPadNodeOff: + FillText4DirectPadNodeOff(); + break; + + case otUserCheck: + FillText4UserCheck(); + break; + + case otLinkageGo: + FillText4LinkageGo(EntryTmp.fData.Body.Splite.Data1); + break; + + case otSetNwTime: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("设置各区域机日期时间",PrintText.body.Msg); + break; + + case otReqNwTime: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("向集中机请求日期时间",PrintText.body.Msg); + break; + + case otSelfCheck: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("自检",PrintText.body.Msg); + break; + + case otSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许",PrintText.body.Msg); + else TMyString::sAddOnStr("手动禁止",PrintText.body.Msg); + break; + + case otSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止",PrintText.body.Msg); + break; + + case otRemoteSetManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许-集中机呼叫执行",PrintText.body.Msg); + else TMyString::sAddOnStr("手动禁止--集中机呼叫执行",PrintText.body.Msg); + break; + + case otRemoteSetAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许-集中机呼叫执行",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止--集中机呼叫执行",PrintText.body.Msg); + break; + + case otReportManualAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("手动允许-区域机报告",PrintText.body.Msg); + else TMyString::sAddOnStr("手动禁止-区域机报告",PrintText.body.Msg); + break; + + case otReportAutoAllowState: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1)TMyString::sAddOnStr("自动允许-区域机报告",PrintText.body.Msg); + else TMyString::sAddOnStr("自动禁止-区域机报告",PrintText.body.Msg); + break; + + case otFireConfirm: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + TMyString::sAddOnStr(" 火警确认 ",PrintText.body.Msg); + NeedDisplayDescp = 1; + break; + + case otFireRemoteConfirm: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + TMyString::sAddOnStr(" 火警远程确认 ",PrintText.body.Msg); + //TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.Data1, PrintText); + NeedDisplayDescp = 1; + break; + + case otFaultConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + NeedDisplayDescp = 1; + } + AddOnFaultMsg(); + break; + + case otFaultRemoteConfirm: + FillTextWithDateTime(); + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0){ + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + TMyString::sAddOnStr(" 故障远程确认 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P2, PrintText.body.Msg); + NeedDisplayDescp = 1; + }else{ + FillCtlNum(); + TMyString::sAddOnStr(" 故障远程确认 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P2, PrintText.body.Msg); + } + break; + + case otSetSmokeSensViaCircuit: + FillTextWithDateTime(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + FillCtlNumNoSpace(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 低",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 中",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 未定义",PrintText.body.Msg); + } + break; + + case otSetSmokeSensViaAddr: + FillTextWithDateTime(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + FillCtlNumNoSpace(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 低",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 中",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 高",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" 回路烟感设置敏感度为 未定义",PrintText.body.Msg); + } + NeedDisplayDescp = 1; + break; + + case otCleanUp: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("清除回路注册",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("清除总线盘配置",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr("清除多线盘配置",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr("清除本机注释",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr("清除网络加载的注释",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 5){ + TMyString::sAddOnStr("清除所有联动表达式",PrintText.body.Msg); + } + break; + + case otLinkageExpsSaveRemove: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr("保存一个联动表达式 编号:",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("删除一个联动表达式 编号:",PrintText.body.Msg); + } + ExpsInx = EntryTmp.fData.Body.Splite.P0; + ExpsInx = ExpsInx * 256; + ExpsInx = ExpsInx + EntryTmp.fData.Body.Splite.P1; + break; + + case otBusPadModify: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("总线盘:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr(" 按键号:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + TMyString::sAddOnStr(" 配置",PrintText.body.Msg); + break; + + case otDirectPadModify: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("多线盘:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr(" 配置",PrintText.body.Msg); + break; + + case otDescpModify: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + if(EntryTmp.fData.Body.Splite.P0 <= dPORT_MAX_COUNT){ + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + TMyString::sAddOnStr(" 回路设备描述更改 ",PrintText.body.Msg); + NeedDisplayDescp = 1; + }else + if( (EntryTmp.fData.Body.Splite.P0 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P0 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr(" 多线盘:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0-dADDR_DIRECTPAD_START+1, PrintText.body.Msg); + TMyString::sAddOnStr(" 节点:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + TMyString::sAddOnStr(" 描述更改 ",PrintText.body.Msg); + NeedDisplayDescp = 1; + } + break; + + case otPassWdModify: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 二级密码更改",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" 三级密码更改",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 12){ + TMyString::sAddOnStr(" 系统故障,二级密码写入失败",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 13){ + TMyString::sAddOnStr(" 系统故障,三级密码写入失败",PrintText.body.Msg); + } + break; + + case otRegisterByManual: + FillTextWithDateTime(); + FillCtlNumNoSpace(); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + TMyString::sAddOnStr("~",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P2, PrintText.body.DateAddr); + if(EntryTmp.fData.Body.Splite.Data1){ + TMyString::sAddOnStr(" 手动注册,类型:",PrintText.body.Msg); + TMyString::sAddOnStr(StrTypeShortName[EntryTmp.fData.Body.Splite.dType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr(" 手动注册,删除",PrintText.body.Msg); + } + break; + + case otAddRemoveNwCtl: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 手动添加区域机 ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 手动删除区域机 ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 3){ + TMyString::sAddOnStr(" 手动添加集中机 ",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 4){ + TMyString::sAddOnStr(" 手动删除集中机 ",PrintText.body.Msg); + } + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + break; + + case otRegCanNetwork: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 本集中机注册区域机数量:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 本区域机联机注册,集中机号:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + } + break; + + case otClearNetworkCfg: + FillTextWithDateTime(); + FillCtlNum(); + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 清除所有区域机",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 2){ + TMyString::sAddOnStr(" 清除挂载的集中机",PrintText.body.Msg); + } + break; + + case otBroadcastVa: + FillTextWithDateTime(); + FillCtlNum(); + TMyString::sAddOnStr("设置广播与声光 路径:",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.Msg); + TMyString::sAddOnStr("-",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr(" 并行模式",PrintText.body.Msg); + }else + if(EntryTmp.fData.Body.Splite.Data1 == 1){ + TMyString::sAddOnStr(" 交替模式",PrintText.body.Msg); + } + break; + + default : break; + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(OperateEntryTmp, NeedDisplayDescp); + SetBufInsert(); + } +} + +void TDoPrint::GetDescpEntry(TRecordCommon DescpEntryTmp) +{ + volatile unsigned int aAddr ,i , aCsum, iP0; + unsigned int aCn, aP0, aP1; + + if(DescpEntryTmp.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = DescpEntryTmp.Splite.P0; + aP1 = DescpEntryTmp.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=7; i<15; i++){ + EntryTmp.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryTmp.D32[i] = 0; + } + } + }else + if( (DescpEntryTmp.Splite.PCtlNum) && (DescpEntryTmp.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = EntryTmp.fData.Body.Splite.PCtlNum -1; + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*409600)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + EntryTmp.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryTmp.D32[i] = 0; + } + } + }else{ + for(i=7; i<15; i++){ + EntryTmp.D32[i] = 0; + } + } +} + +void TDoPrint::FillFaultText(TRecordCommon FaultEntryTmp) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + + NeedDisplayDescp = 0; + + //Fault History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = FaultEntryTmp.D32[d]; + } + + FillTextWithDateTime(); + + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + /* + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + + data = EntryTmp.fData.Body.Splite.PCtlNum; + d = data/10; + e = d % 10; + PrintText[18] = e + '0'; + e = data % 10; + PrintText[19] = e + '0'; + PrintText[20] = '-'; + + data = EntryTmp.fData.Body.Splite.P0; + d = data/10; + e = d % 10; + PrintText[21] = e + '0'; + e = data % 10; + PrintText[22] = e + '0'; + PrintText[23] = '-'; + + PrintText[24] = '\0'; + */ + if( (EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xC0){ + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_HANDPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_HANDPAD_END) ){ + TMyString::sAddOnStr("总线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_HANDPAD_START +1,PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + else TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.P1 >= dADDR_DIRECTPAD_START) && (EntryTmp.fData.Body.Splite.P1 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("直线盘 ",PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1 -dADDR_DIRECTPAD_START +1,PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.Data1 & 0x01)TMyString::sAddOnStr(" 离线",PrintText.body.Msg); + else TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xD0){ + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + TMyString::sAddOnStr("设备故障 ",PrintText.body.Msg); + aType = EntryTmp.fData.Body.Splite.Data0; + if(aType < 32){ + TMyString::sAddOnStr(StrDevFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + }else{ + if( (aType == 15) || (aType == 16) ){ + TMyString::sAddOnStr(StrDevFaultType[aType],PrintText.body.Msg); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.Msg); + if(EntryTmp.fData.Body.Splite.mType > 200){ + TMyString::sAddOnStr("通讯故障条目数:多于200",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("通讯故障条目数:",PrintText.body.Msg); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.mType, PrintText.body.Msg); + } + } + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xE0){ + //Cir Error + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + //TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr("回路故障-恢复",PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("回路故障",PrintText.body.Msg); + } + }else + if((EntryTmp.fData.Body.Splite.Data1 & 0xF0) == 0xF0){ + //Board Error + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + TMyString::sAddOnStr("板卡故障 ",PrintText.body.Msg); + aType = EntryTmp.fData.Body.Splite.Data0; + if(aType < 16){ + TMyString::sAddOnStr(StrBrdFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知类型",PrintText.body.Msg); + } + if( (EntryTmp.fData.Body.Splite.Data1 & 0x01) == 0){ + TMyString::sAddOnStr(" 恢复",PrintText.body.Msg); + }else{ + //TMyString::sAddOnStr(" 发生",PrintText); + } + }else{ + //EpError + NeedDisplayDescp = 0; + + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + /* + data = EntryTmp.fData.Body.Splite.P1; + d = data/100; + e = d % 10; + PrintText[24] = e + '0'; + d = data/10; + e = d % 10; + PrintText[25] = e + '0'; + e = data % 10; + PrintText[26] = e + '0'; + PrintText[27] = ' '; + PrintText[28] = '\0'; + */ + TMyString::sAddOnStr("故障 ",PrintText.body.Msg); + //TextAddPst = GetPrintTextLen(); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + data = 0; + if( (aP0 >0) && (aP0 <=40) ){ + data = EpDev[aP0 -1][aP1-1].fData.Split.UserCode; + } + TMyString::sAddOn5Dg(data, PrintText.body.Msg); + /* + d = data/10000; + e = d % 10; + PrintText[TextAddPst] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[TextAddPst+1] = e + '0'; + d = data/100; + e = d % 10; + PrintText[TextAddPst+2] = e + '0'; + d = data/10; + e = d % 10; + PrintText[TextAddPst+3] = e + '0'; + e = data % 10; + PrintText[TextAddPst+4] = e + '0'; + PrintText[TextAddPst+5] = ' '; + + PrintText[TextAddPst+6] = 0; + */ + TMyString::sAddOnStr(" ",PrintText.body.Msg); + + aType = EntryTmp.fData.Body.Splite.Data0; + if(aType < 16){ + TMyString::sAddOnStr(StrEpFaultType[aType],PrintText.body.Msg); + }else{ + TMyString::sAddOnStr("未知故障",PrintText.body.Msg); + } + + if(EntryTmp.fData.Body.Splite.Data1 == 0){ + TMyString::sAddOnStr("-恢复",PrintText.body.Msg); + }else{ + //TMyString::sAddOnStr("-发生",PrintText); + } + + NeedDisplayDescp = 1; + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <=dADDR_DIRECTPAD_START) ){ + TMyString::sAddOnStr("多线盘节点 ",PrintText.body.Msg); + } + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(FaultEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::FillLinkageText(TRecordCommon LinkageEntryTmp) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + + NeedDisplayDescp = 0; + + //Linkage History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = LinkageEntryTmp.D32[d]; + } + + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + TMyString::sAddOnStr("联动 ",PrintText.body.Msg); + //TextAddPst = GetPrintTextLen(); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + data = 0; + if( (aP0 >0) && (aP0 <=40) ){ + if(aP1 >0){ + aP0--; + data = EpDev[aP0][aP1-1].fData.Split.UserCode; + } + } + + TMyString::sAddOn5Dg(data, PrintText.body.Msg); + /* + d = data/10000; + e = d % 10; + PrintText[TextAddPst] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[TextAddPst+1] = e + '0'; + d = data/100; + e = d % 10; + PrintText[TextAddPst+2] = e + '0'; + d = data/10; + e = d % 10; + PrintText[TextAddPst+3] = e + '0'; + e = data % 10; + PrintText[TextAddPst+4] = e + '0'; + PrintText[TextAddPst+5] = ' '; + + PrintText[TextAddPst+6] = 0; + */ + if( (aP0 >0) && (aP0 <=40) ){ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + NeedDisplayDescp = 1; + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + TMyString::sAddOnStr("多线盘节点",PrintText.body.Msg); + NeedDisplayDescp = 1; + } + + data = EntryTmp.fData.Body.Splite.iByte0; + + if(data == 0x01){ + TMyString::sAddOnStr("-启动",PrintText.body.Msg); + }else + if(data == 0x02){ + TMyString::sAddOnStr("-区声光启动",PrintText.body.Msg); + }else + if(data == 0x03){ + TMyString::sAddOnStr("-反馈",PrintText.body.Msg); + }else + if(data == 0x04){ + TMyString::sAddOnStr("-反馈缺失",PrintText.body.Msg); + }else + if(data == 0x05){ + TMyString::sAddOnStr("-启动",PrintText.body.Msg); + }else + if(data == 0x06){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-声光启动",PrintText.body.Msg); + }else + + if(data == 0x07){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-应答消钮",PrintText.body.Msg); + }else + if(data == 0xB1){ + TMyString::sAddOnStr("-停止",PrintText.body.Msg); + }else + if(data == 0xB3){ + TMyString::sAddOnStr("-反馈取消",PrintText.body.Msg); + }else + if(data == 0xB5){ + TMyString::sAddOnStr("-停止",PrintText.body.Msg); + }else + if(data == 0xB6){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-声光停止",PrintText.body.Msg); + }else + if(data == 0xB7){ + ClearPrintText(); + FillTextWithDateTime(); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("联动",PrintText.body.Msg); + TMyString::sAddOnStr("-应答消钮取消",PrintText.body.Msg); + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(LinkageEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::FillFireText(TRecordCommon FireEntryTmp, int IsFirst) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + + NeedDisplayDescp = 0; + + //Fire History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = FireEntryTmp.D32[d]; + } + + FillTextWithDateTime(); + + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if((aP0)&&(aP0<=40)){ + aP0--; + aP1--; + + TMyString::sAddOnStr("火警 ",PrintText.body.Msg); + //TextAddPst = GetPrintTextLen(); + + data = EpDev[aP0][aP1-1].fData.Split.UserCode; + NeedDisplayDescp = 1; + + TMyString::sAddOn5Dg(data, PrintText.body.Msg); + /* + d = data/10000; + e = d % 10; + PrintText[TextAddPst] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[TextAddPst+1] = e + '0'; + d = data/100; + e = d % 10; + PrintText[TextAddPst+2] = e + '0'; + d = data/10; + e = d % 10; + PrintText[TextAddPst+3] = e + '0'; + e = data % 10; + PrintText[TextAddPst+4] = e + '0'; + PrintText[TextAddPst+5] = ' '; + + PrintText[TextAddPst+6] = 0; + */ + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && ( aP0 <= dADDR_DIRECTPAD_END)){ + NeedDisplayDescp = 1; + } + /* + if( (aP0 >0) && (aP0 < 64) ){ + if(aP1 >0){ + if(aP0 < 40){ + aP0--; + data = EpDev[aP0][aP1-1].fData.Split.UserCode; + }else + if(aP0 < 48){ + aP0-=41; + data = HandCtlBoard[aP0].UserCodeList[aP1-1]; + }else + if(aP0 < 56){ + aP0-=49; + data = 0;//DirectCtlBoard[aP0].UserCodeList[aP1-1]; + } + } + } + d = data/10000; + e = d % 10; + PrintText[28] = e + '0'; + d = data/1000; + e = d % 10; + PrintText[29] = e + '0'; + d = data/100; + e = d % 10; + PrintText[30] = e + '0'; + d = data/10; + e = d % 10; + PrintText[31] = e + '0'; + e = data % 10; + PrintText[32] = e + '0'; + PrintText[33] = ' '; + + PrintText[34] = 0; + + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText); + */ + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(FireEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::FillSvText(TRecordCommon SvEntryTmp) +{ + volatile unsigned int SdAddr, Addr; + unsigned int d,e; + unsigned int data; + unsigned char aP0; + unsigned char aP1; + unsigned char aType; + unsigned char len; + int NeedDisplayDescp; + unsigned int TextAddPst; + + NeedDisplayDescp = 0; + + //Fire History + for(d=0; d<4; d++){ + EntryTmp.fData.Body.D32[d] = SvEntryTmp.D32[d]; + } + + FillTextWithDateTime(); + + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.PCtlNum, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn2Dg(EntryTmp.fData.Body.Splite.P0, PrintText.body.DateAddr); + TMyString::sAddOnStr("-",PrintText.body.DateAddr); + TMyString::sAddOn3Dg(EntryTmp.fData.Body.Splite.P1, PrintText.body.DateAddr); + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + TMyString::sAddOnStr("监管 ",PrintText.body.Msg); + //TextAddPst = GetPrintTextLen(); + + if( (aP0 >0) && (aP0 < 64) ){ + if(aP1 >0){ + if(aP0 < 40){ + aP0--; + data = EpDev[aP0][aP1-1].fData.Split.UserCode; + }else + if(aP0 < 48){ + aP0-=41; + data = HandCtlBoard[aP0].UserCodeList[aP1-1]; + }else + if(aP0 < 56){ + aP0-=49; + data = 0;//DirectCtlBoard[aP0].UserCodeList[aP1-1]; + } + } + } + + TMyString::sAddOn5Dg(data, PrintText.body.Msg); + + aType = EntryTmp.fData.Body.Splite.dType; + TMyString::sAddOnStr(StrTypeShortName[aType],PrintText.body.Msg); + + data = EntryTmp.fData.Body.Splite.iByte0; + if(data == 0x01){ + //TMyString::sAddOnStr("-启动",PrintText); + }else + if(data == 0x02){ + //TMyString::sAddOnStr("-区声光启动",PrintText); + }else + if(data == 0x03){ + //TMyString::sAddOnStr("-应答",PrintText); + }else + if(data == 0x04){ + //TMyString::sAddOnStr("-应答缺失",PrintText); + } + + aP0 = EntryTmp.fData.Body.Splite.P0; + aP1 = EntryTmp.fData.Body.Splite.P1; + + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + NeedDisplayDescp = 1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + NeedDisplayDescp = 1; + } + } + + TMyString::sAddOnStr("\n",PrintText.body.Msg); + DescpTextBufInsert(SvEntryTmp, NeedDisplayDescp); + SetBufInsert(); +} + +void TDoPrint::FillFromNwText(TRecordCommon FromNwEntryTmp) +{ + ; +} + +void TDoPrint::Init() +{ + unsigned int i,a; + + State = 0; + //Buf.WriteInx = 0; + //Buf.ReadInx = 0; + + for(a=0;a<3;a++){ + for(i=0;i<128;i++){ + Buf.wEntry[a].D8[i] = 0; + } + } + for(i=0;i<64;i++){ + PrintText.body.DateAddr[i] = 0; + PrintText.body.Msg[i] = 0; + PrintText.body.Dscp[i] = 0; + } +} + +void TDoPrint::ClearPrintText() +{ + unsigned int i; + + for(i=0;i<64;i++){ + PrintText.body.DateAddr[i] = 0; + PrintText.body.Msg[i] = 0; + PrintText.body.Dscp[i] = 0; + } +} + +void TDoPrint::Print() +{ + ; +} + +void TDoPrint::TryGetState() +{ + //Triger to Sen a Read State Cmd +} + +unsigned int TDoPrint::GetPrintState() +{ + return printer_is_busy(); +} + +void TDoPrint::SetBufInsertSequence() +{ + volatile unsigned int i = 0,a = 0; + volatile unsigned int line = 0; + volatile unsigned int len = 0; + volatile unsigned int zh_num = 0; + + for(i=0;i<32;i++){ + Buf.wEntry[0].D32[i] = 0; + Buf.wEntry[1].D32[i] = 0; + Buf.wEntry[2].D32[i] = 0; + } + + for(a=0;a<3;a++){ + len = GetPrintTextLen(PrintText.Text[a]); + if(len){ + if(len%32) + line = len/32 + 1; + else + line = len/32; + + if(1 == line){ + for(i=0;i 0x7F)zh_num++; + else zh_num = 0; + } + if(zh_num & 0x01){ + for(i = 0;i < (len-32+1);i++) + PrintText.Text[a][len-i] = PrintText.Text[a][len-1-i]; + PrintText.Text[a][31] = ' '; + len+=1; + } + + if(64 == len){ + for(i=0;i<32;i++){ + Buf.wEntry[a].Body.Text[i] = PrintText.Text[a][i+32]; + } + for(i=0;i<32;i++){ + Buf.wEntry[a].Body.Text[i+32] = PrintText.Text[a][i]; + } + }else + if(len < 64){ + for(i=0;i<(len-32);i++){ + Buf.wEntry[a].Body.Text[i] = PrintText.Text[a][i+32]; + } + Buf.wEntry[a].Body.Text[len-32] = '\n'; + for(i=0;i<32;i++){ + Buf.wEntry[a].Body.Text[len-32+1+i] = PrintText.Text[a][i]; + } + len+=1; + } + Buf.wEntry[a].Body.Len = len; + Buf.wEntry[a].Body.Text[Buf.wEntry[a].Body.Len] = 0; + } + } + } +} + +void TDoPrint::BufInsert() +{ + volatile unsigned int aAddr, iLen, i; + //------------------------------------line 1------------------------------------------ + if(Buf.wEntry[2].Body.Len){ + Buf.WriteInx++; + + if(Buf.WriteInx >= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + iLen = Buf.wEntry[2].Body.Len / 4 + 1; + if(iLen >31)iLen = 31; + for(i=0; i= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + + iLen = Buf.wEntry[1].Body.Len / 4 + 1; + if(iLen >31)iLen = 31; + for(i=0; i= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + iLen = Buf.wEntry[0].Body.Len / 4 + 1; + if(iLen >31)iLen = 31; + for(i=0; i= PrintBuf_Count)Buf.WriteInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.WriteInx * PrintEntry_Size); + + iLen = 36 / 4; + if(iLen >31)iLen = 31; + for(i=0; i 16){ + set_print_text(&Buf.rEntry.Body.Text[Sections.DoingInx*16],16); + Buf.rEntry.Body.Len-=16; + }else{ + set_print_text(&Buf.rEntry.Body.Text[Sections.DoingInx*16],Buf.rEntry.Body.Len); + Buf.rEntry.Body.Len = 0; + } + + Sections.DoingInx++; + if(Sections.DoingInx >= Sections.sCount){ + Sections.oSequence = 0; + } + }else{ + Sections.oSequence = 0; + } +} + +void TDoPrint::BufFillPrintingBuf() +{ + unsigned int aAddr, i, iLen; + Buf.ReadInx++; + if(Buf.ReadInx >= PrintBuf_Count)Buf.ReadInx = 0; + aAddr = dAddrSdram_PrintBuf + (Buf.ReadInx * PrintEntry_Size); + + Sections.AllTextCount = *(volatile unsigned int *)(aAddr + (31*4)); + Buf.rEntry.Body.Len = Sections.AllTextCount; + iLen = Sections.AllTextCount / 4 +1; + if(iLen >30)iLen = 30; + for(i=0; itResult)tResult = *tPtr; + tPtr++; + } + return tResult; +} + +static int UnicodeToUTF8Inline(unsigned int CodePoint, char *Buf) +{ + int tResult; + if(CodePoint < 0x80){ + tResult =1; + Buf[0] = (char)((unsigned char)(CodePoint)); + }else + if(CodePoint < 0x800){ + tResult =2; + Buf[0] = (char)((unsigned char)(0xc0 | (CodePoint >> 6))); + Buf[1] = (char)((unsigned char)(0x80 | (CodePoint & 0x3f))); + }else + if(CodePoint < 0x10000){ + tResult =3; + Buf[0] = (char)((unsigned char)(0xe0 | (CodePoint >> 12))); + Buf[1] = (char)((unsigned char)((CodePoint >> 6) & 0x3f) | 0x80); + Buf[2] = (char)((unsigned char)(CodePoint & 0x3f) | 0x80); + }else + if(CodePoint < 0x110000){ + tResult =4; + Buf[0] = (char)((unsigned char)(0xf0 | (CodePoint >> 18))); + Buf[1] = (char)((unsigned char)((CodePoint >> 12) & 0x3f) | 0x80); + Buf[2] = (char)((unsigned char)((CodePoint >> 6) & 0x3f) | 0x80); + Buf[3] = (char)((unsigned char)(CodePoint & 0x3f) | 0x80); + }else{ + tResult =0; + } + return tResult; +} + +static unsigned short SearchTable(const unsigned short *CodePageArr, unsigned int id) +{ + int idMid; + int idLow, idHigh; + unsigned short tResult; + + idLow = 0; + //idHigh = GetHigh(); + idHigh = 22047; + while (idLow <= idHigh) { + if (idLow == idHigh){ + if( CodePageArr[idLow] == id){ + tResult = idLow; + }else{ + tResult = 0; + } + return tResult; + } + idMid = (idLow + idHigh) / 2; + if (CodePageArr[idMid] == id) { + tResult = idMid; + return tResult; + } + if (CodePageArr[idMid] > id ) + idHigh = idMid - 1; + if (CodePageArr[idMid] < id ) + idLow = idMid + 1; + } + tResult = 0; + return tResult; +} + + + +static int DBWSToUTF8(char *s, const unsigned short *ArrayUni, const unsigned short *ArrayCP, int CodeP, char *Rst) +{ + int len, l,i; + char *Src, *Dest; + char c;; + unsigned short code,code1; + unsigned char HByte,LByte; + unsigned int LimitedLen; + int utf8Bytes; + int ConvTimes; + + ConvTimes = 0; + + if(*s == '\0' ){ + *Rst++ = '\0'; + *Rst = '\0'; + return -1; + } + len = GetCharLen(s); + //SetLength(Result, len * 4);// Asia UTF-8 is at most 4 bytes + Src = s; + Dest = Rst; + while(1){ + c = *Src; + HByte = (unsigned char)(*Src); + Src++; + + if(c < 128){ + if( (c == '\0') && ((Src - s) >= len) )break; + *Dest = c; + Dest++; + }else{ + code = ((unsigned short)c) << 8; + c = *Src; + LByte = (unsigned char)(*Src); + if( (c== '\0') && ((Src- s) >=len) ) break; + code = code + (unsigned char)(c); + code1 = code; + Src++; + + code = ArrayUni[SearchTable(ArrayCP, code)]; + if (code == 0){ + if(CodeP == 936){ + if( (HByte >= 0xAA) && (HByte <= 0xAF) && (LByte >= 0xA1) && (LByte <= 0xFE) ){ + code = 0xe000 + (94 * (HByte-0xaa)) + (LByte-0xa1); + }else + if( (HByte >= 0xF8) && (HByte <= 0xFE) && (LByte >= 0xA1) && (LByte <= 0xFE) ){ + code = 0xe234 + (94 * (HByte-0xf8)) + (LByte-0xa1); + }else + if( (HByte >= 0xA1) && (HByte <= 0xA7) && (LByte >= 0x40) && (LByte <= 0xA0) ){ + code = 0xe4C6 + (97 * (HByte-0xA1)) + (LByte-0x40); + }else{ + LimitedLen = sizeof(cp936unodered) / 4; + for( i=0; i< LimitedLen; i++){ + if(code1 == cp936unodered[i]){ + code = cp936unoderedstart +i; + break; + } + } + } + }else{ + code = 0; + } + } + if (code>0){ + l =UnicodeToUTF8Inline(code,Dest); + Dest += l; + }else{ + switch(ConvErrorProcMode){ + case ConvError_Skip: + break; + case ConvError_Exception: + *Dest++ = '\0'; + *Dest = '\0'; + return -1; + break; + case ConvError_Replace: + *Dest = '?'; + Dest++; + break; + case ConvError_FillEmpty: + *Dest++ = ' '; + break; + } + } + } + ConvTimes++; + if(ConvTimes > 1023)break; + } + utf8Bytes = (unsigned int)(Dest) - (unsigned int)(Rst); + *Dest++ = '\0'; + *Dest = '\0'; + //SetLength(Result, {%H-}PtrUInt(Dest) - PtrUInt(Result)); + //SetCodePage(RawByteString(Result), CP_UTF8, False); + return utf8Bytes; +} + +//return UTF8 Bytes Length +int CP936ToUTF8(char *s, char *d) +{ + return DBWSToUTF8(s, Uni936C, CP936CC, 936, d); +} + +int UnicodeToCP936(unsigned int aUnicode) +{ + if(aUnicode < 128) + return aUnicode; + else + return CP936CU[SearchTable(Uni936U, aUnicode)]; +} + + + + + diff --git a/MyCode/src/EncodeConv.h b/MyCode/src/EncodeConv.h new file mode 100644 index 0000000..6230b95 --- /dev/null +++ b/MyCode/src/EncodeConv.h @@ -0,0 +1,10 @@ +#ifndef ENCODECONV_H_ +#define ENCODECONV_H_ + +//return UTF8 Bytes Length +extern int CP936ToUTF8(char *s, char *d); +extern int UnicodeToCP936(unsigned int aUnicode); + +#endif + + diff --git a/MyCode/src/EncodeCp936.cpp b/MyCode/src/EncodeCp936.cpp new file mode 100644 index 0000000..39fce9e --- /dev/null +++ b/MyCode/src/EncodeCp936.cpp @@ -0,0 +1,6805 @@ +#include "EncodeCp936.h" + + +const unsigned short CP936CC[22048] = { +0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12, +0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,0x20,0x21,0x22,0x23,0x24,0x25, +0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38, +0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B, +0x4C,0x4D,0x4E,0x4F,0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E, +0x5F,0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,0x70,0x71, +0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,0x80,0x81,0x82,0x83,0x84, +0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, +0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA, +0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD, +0xBE,0xBF,0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0, +0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF,0xE0,0xE1,0xE2,0xE3, +0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6, +0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF,0x8140,0x8141,0x8142,0x8143,0x8144,0x8145,0x8146, +0x8147,0x8148,0x8149,0x814A,0x814B,0x814C,0x814D,0x814E,0x814F,0x8150,0x8151,0x8152,0x8153, +0x8154,0x8155,0x8156,0x8157,0x8158,0x8159,0x815A,0x815B,0x815C,0x815D,0x815E,0x815F,0x8160, +0x8161,0x8162,0x8163,0x8164,0x8165,0x8166,0x8167,0x8168,0x8169,0x816A,0x816B,0x816C,0x816D, +0x816E,0x816F,0x8170,0x8171,0x8172,0x8173,0x8174,0x8175,0x8176,0x8177,0x8178,0x8179,0x817A, +0x817B,0x817C,0x817D,0x817E,0x8180,0x8181,0x8182,0x8183,0x8184,0x8185,0x8186,0x8187,0x8188, +0x8189,0x818A,0x818B,0x818C,0x818D,0x818E,0x818F,0x8190,0x8191,0x8192,0x8193,0x8194,0x8195, +0x8196,0x8197,0x8198,0x8199,0x819A,0x819B,0x819C,0x819D,0x819E,0x819F,0x81A0,0x81A1,0x81A2, +0x81A3,0x81A4,0x81A5,0x81A6,0x81A7,0x81A8,0x81A9,0x81AA,0x81AB,0x81AC,0x81AD,0x81AE,0x81AF, +0x81B0,0x81B1,0x81B2,0x81B3,0x81B4,0x81B5,0x81B6,0x81B7,0x81B8,0x81B9,0x81BA,0x81BB,0x81BC, +0x81BD,0x81BE,0x81BF,0x81C0,0x81C1,0x81C2,0x81C3,0x81C4,0x81C5,0x81C6,0x81C7,0x81C8,0x81C9, +0x81CA,0x81CB,0x81CC,0x81CD,0x81CE,0x81CF,0x81D0,0x81D1,0x81D2,0x81D3,0x81D4,0x81D5,0x81D6, +0x81D7,0x81D8,0x81D9,0x81DA,0x81DB,0x81DC,0x81DD,0x81DE,0x81DF,0x81E0,0x81E1,0x81E2,0x81E3, +0x81E4,0x81E5,0x81E6,0x81E7,0x81E8,0x81E9,0x81EA,0x81EB,0x81EC,0x81ED,0x81EE,0x81EF,0x81F0, +0x81F1,0x81F2,0x81F3,0x81F4,0x81F5,0x81F6,0x81F7,0x81F8,0x81F9,0x81FA,0x81FB,0x81FC,0x81FD, +0x81FE,0x8240,0x8241,0x8242,0x8243,0x8244,0x8245,0x8246,0x8247,0x8248,0x8249,0x824A,0x824B, +0x824C,0x824D,0x824E,0x824F,0x8250,0x8251,0x8252,0x8253,0x8254,0x8255,0x8256,0x8257,0x8258, +0x8259,0x825A,0x825B,0x825C,0x825D,0x825E,0x825F,0x8260,0x8261,0x8262,0x8263,0x8264,0x8265, +0x8266,0x8267,0x8268,0x8269,0x826A,0x826B,0x826C,0x826D,0x826E,0x826F,0x8270,0x8271,0x8272, +0x8273,0x8274,0x8275,0x8276,0x8277,0x8278,0x8279,0x827A,0x827B,0x827C,0x827D,0x827E,0x8280, +0x8281,0x8282,0x8283,0x8284,0x8285,0x8286,0x8287,0x8288,0x8289,0x828A,0x828B,0x828C,0x828D, +0x828E,0x828F,0x8290,0x8291,0x8292,0x8293,0x8294,0x8295,0x8296,0x8297,0x8298,0x8299,0x829A, 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+0xF788,0xF789,0xF78A,0xF78B,0xF78C,0xF78D,0xF78E,0xF78F,0xF790,0xF791,0xF792,0xF793,0xF794, +0xF795,0xF796,0xF797,0xF798,0xF799,0xF79A,0xF79B,0xF79C,0xF79D,0xF79E,0xF79F,0xF7A0,0xF7A1, +0xF7A2,0xF7A3,0xF7A4,0xF7A5,0xF7A6,0xF7A7,0xF7A8,0xF7A9,0xF7AA,0xF7AB,0xF7AC,0xF7AD,0xF7AE, +0xF7AF,0xF7B0,0xF7B1,0xF7B2,0xF7B3,0xF7B4,0xF7B5,0xF7B6,0xF7B7,0xF7B8,0xF7B9,0xF7BA,0xF7BB, +0xF7BC,0xF7BD,0xF7BE,0xF7BF,0xF7C0,0xF7C1,0xF7C2,0xF7C3,0xF7C4,0xF7C5,0xF7C6,0xF7C7,0xF7C8, +0xF7C9,0xF7CA,0xF7CB,0xF7CC,0xF7CD,0xF7CE,0xF7CF,0xF7D0,0xF7D1,0xF7D2,0xF7D3,0xF7D4,0xF7D5, +0xF7D6,0xF7D7,0xF7D8,0xF7D9,0xF7DA,0xF7DB,0xF7DC,0xF7DD,0xF7DE,0xF7DF,0xF7E0,0xF7E1,0xF7E2, +0xF7E3,0xF7E4,0xF7E5,0xF7E6,0xF7E7,0xF7E8,0xF7E9,0xF7EA,0xF7EB,0xF7EC,0xF7ED,0xF7EE,0xF7EF, +0xF7F0,0xF7F1,0xF7F2,0xF7F3,0xF7F4,0xF7F5,0xF7F6,0xF7F7,0xF7F8,0xF7F9,0xF7FA,0xF7FB,0xF7FC, +0xF7FD,0xF7FE,0xF840,0xF841,0xF842,0xF843,0xF844,0xF845,0xF846,0xF847,0xF848,0xF849,0xF84A, +0xF84B,0xF84C,0xF84D,0xF84E,0xF84F,0xF850,0xF851,0xF852,0xF853,0xF854,0xF855,0xF856,0xF857, +0xF858,0xF859,0xF85A,0xF85B,0xF85C,0xF85D,0xF85E,0xF85F,0xF860,0xF861,0xF862,0xF863,0xF864, +0xF865,0xF866,0xF867,0xF868,0xF869,0xF86A,0xF86B,0xF86C,0xF86D,0xF86E,0xF86F,0xF870,0xF871, +0xF872,0xF873,0xF874,0xF875,0xF876,0xF877,0xF878,0xF879,0xF87A,0xF87B,0xF87C,0xF87D,0xF87E, +0xF880,0xF881,0xF882,0xF883,0xF884,0xF885,0xF886,0xF887,0xF888,0xF889,0xF88A,0xF88B,0xF88C, +0xF88D,0xF88E,0xF88F,0xF890,0xF891,0xF892,0xF893,0xF894,0xF895,0xF896,0xF897,0xF898,0xF899, +0xF89A,0xF89B,0xF89C,0xF89D,0xF89E,0xF89F,0xF8A0,0xF940,0xF941,0xF942,0xF943,0xF944,0xF945, +0xF946,0xF947,0xF948,0xF949,0xF94A,0xF94B,0xF94C,0xF94D,0xF94E,0xF94F,0xF950,0xF951,0xF952, +0xF953,0xF954,0xF955,0xF956,0xF957,0xF958,0xF959,0xF95A,0xF95B,0xF95C,0xF95D,0xF95E,0xF95F, +0xF960,0xF961,0xF962,0xF963,0xF964,0xF965,0xF966,0xF967,0xF968,0xF969,0xF96A,0xF96B,0xF96C, +0xF96D,0xF96E,0xF96F,0xF970,0xF971,0xF972,0xF973,0xF974,0xF975,0xF976,0xF977,0xF978,0xF979, +0xF97A,0xF97B,0xF97C,0xF97D,0xF97E,0xF980,0xF981,0xF982,0xF983,0xF984,0xF985,0xF986,0xF987, +0xF988,0xF989,0xF98A,0xF98B,0xF98C,0xF98D,0xF98E,0xF98F,0xF990,0xF991,0xF992,0xF993,0xF994, +0xF995,0xF996,0xF997,0xF998,0xF999,0xF99A,0xF99B,0xF99C,0xF99D,0xF99E,0xF99F,0xF9A0,0xFA40, +0xFA41,0xFA42,0xFA43,0xFA44,0xFA45,0xFA46,0xFA47,0xFA48,0xFA49,0xFA4A,0xFA4B,0xFA4C,0xFA4D, +0xFA4E,0xFA4F,0xFA50,0xFA51,0xFA52,0xFA53,0xFA54,0xFA55,0xFA56,0xFA57,0xFA58,0xFA59,0xFA5A, +0xFA5B,0xFA5C,0xFA5D,0xFA5E,0xFA5F,0xFA60,0xFA61,0xFA62,0xFA63,0xFA64,0xFA65,0xFA66,0xFA67, +0xFA68,0xFA69,0xFA6A,0xFA6B,0xFA6C,0xFA6D,0xFA6E,0xFA6F,0xFA70,0xFA71,0xFA72,0xFA73,0xFA74, +0xFA75,0xFA76,0xFA77,0xFA78,0xFA79,0xFA7A,0xFA7B,0xFA7C,0xFA7D,0xFA7E,0xFA80,0xFA81,0xFA82, +0xFA83,0xFA84,0xFA85,0xFA86,0xFA87,0xFA88,0xFA89,0xFA8A,0xFA8B,0xFA8C,0xFA8D,0xFA8E,0xFA8F, +0xFA90,0xFA91,0xFA92,0xFA93,0xFA94,0xFA95,0xFA96,0xFA97,0xFA98,0xFA99,0xFA9A,0xFA9B,0xFA9C, +0xFA9D,0xFA9E,0xFA9F,0xFAA0,0xFB40,0xFB41,0xFB42,0xFB43,0xFB44,0xFB45,0xFB46,0xFB47,0xFB48, +0xFB49,0xFB4A,0xFB4B,0xFB4C,0xFB4D,0xFB4E,0xFB4F,0xFB50,0xFB51,0xFB52,0xFB53,0xFB54,0xFB55, +0xFB56,0xFB57,0xFB58,0xFB59,0xFB5A,0xFB5B,0xFB5C,0xFB5D,0xFB5E,0xFB5F,0xFB60,0xFB61,0xFB62, +0xFB63,0xFB64,0xFB65,0xFB66,0xFB67,0xFB68,0xFB69,0xFB6A,0xFB6B,0xFB6C,0xFB6D,0xFB6E,0xFB6F, +0xFB70,0xFB71,0xFB72,0xFB73,0xFB74,0xFB75,0xFB76,0xFB77,0xFB78,0xFB79,0xFB7A,0xFB7B,0xFB7C, +0xFB7D,0xFB7E,0xFB80,0xFB81,0xFB82,0xFB83,0xFB84,0xFB85,0xFB86,0xFB87,0xFB88,0xFB89,0xFB8A, +0xFB8B,0xFB8C,0xFB8D,0xFB8E,0xFB8F,0xFB90,0xFB91,0xFB92,0xFB93,0xFB94,0xFB95,0xFB96,0xFB97, +0xFB98,0xFB99,0xFB9A,0xFB9B,0xFB9C,0xFB9D,0xFB9E,0xFB9F,0xFBA0,0xFC40,0xFC41,0xFC42,0xFC43, +0xFC44,0xFC45,0xFC46,0xFC47,0xFC48,0xFC49,0xFC4A,0xFC4B,0xFC4C,0xFC4D,0xFC4E,0xFC4F,0xFC50, +0xFC51,0xFC52,0xFC53,0xFC54,0xFC55,0xFC56,0xFC57,0xFC58,0xFC59,0xFC5A,0xFC5B,0xFC5C,0xFC5D, +0xFC5E,0xFC5F,0xFC60,0xFC61,0xFC62,0xFC63,0xFC64,0xFC65,0xFC66,0xFC67,0xFC68,0xFC69,0xFC6A, +0xFC6B,0xFC6C,0xFC6D,0xFC6E,0xFC6F,0xFC70,0xFC71,0xFC72,0xFC73,0xFC74,0xFC75,0xFC76,0xFC77, +0xFC78,0xFC79,0xFC7A,0xFC7B,0xFC7C,0xFC7D,0xFC7E,0xFC80,0xFC81,0xFC82,0xFC83,0xFC84,0xFC85, +0xFC86,0xFC87,0xFC88,0xFC89,0xFC8A,0xFC8B,0xFC8C,0xFC8D,0xFC8E,0xFC8F,0xFC90,0xFC91,0xFC92, +0xFC93,0xFC94,0xFC95,0xFC96,0xFC97,0xFC98,0xFC99,0xFC9A,0xFC9B,0xFC9C,0xFC9D,0xFC9E,0xFC9F, +0xFCA0,0xFD40,0xFD41,0xFD42,0xFD43,0xFD44,0xFD45,0xFD46,0xFD47,0xFD48,0xFD49,0xFD4A,0xFD4B, +0xFD4C,0xFD4D,0xFD4E,0xFD4F,0xFD50,0xFD51,0xFD52,0xFD53,0xFD54,0xFD55,0xFD56,0xFD57,0xFD58, +0xFD59,0xFD5A,0xFD5B,0xFD5C,0xFD5D,0xFD5E,0xFD5F,0xFD60,0xFD61,0xFD62,0xFD63,0xFD64,0xFD65, +0xFD66,0xFD67,0xFD68,0xFD69,0xFD6A,0xFD6B,0xFD6C,0xFD6D,0xFD6E,0xFD6F,0xFD70,0xFD71,0xFD72, +0xFD73,0xFD74,0xFD75,0xFD76,0xFD77,0xFD78,0xFD79,0xFD7A,0xFD7B,0xFD7C,0xFD7D,0xFD7E,0xFD80, +0xFD81,0xFD82,0xFD83,0xFD84,0xFD85,0xFD86,0xFD87,0xFD88,0xFD89,0xFD8A,0xFD8B,0xFD8C,0xFD8D, +0xFD8E,0xFD8F,0xFD90,0xFD91,0xFD92,0xFD93,0xFD94,0xFD95,0xFD96,0xFD97,0xFD98,0xFD99,0xFD9A, +0xFD9B,0xFD9C,0xFD9D,0xFD9E,0xFD9F,0xFDA0,0xFE40,0xFE41,0xFE42,0xFE43,0xFE44,0xFE45,0xFE46, +0xFE47,0xFE48,0xFE49,0xFE4A,0xFE4B,0xFE4C,0xFE4D,0xFE4E,0xFE4F,0 +}; + +const unsigned short Uni936C[22048] = { +0x0000,0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C, +0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019, +0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026, +0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033, +0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040, +0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D, +0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A, +0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067, +0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074, +0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x20AC,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0x4E02,0x4E04,0x4E05,0x4E06,0x4E0F,0x4E12,0x4E17,0x4E1F,0x4E20,0x4E21,0x4E23,0x4E26, +0x4E29,0x4E2E,0x4E2F,0x4E31,0x4E33,0x4E35,0x4E37,0x4E3C,0x4E40,0x4E41,0x4E42,0x4E44,0x4E46, +0x4E4A,0x4E51,0x4E55,0x4E57,0x4E5A,0x4E5B,0x4E62,0x4E63,0x4E64,0x4E65,0x4E67,0x4E68,0x4E6A, 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+0x9D82,0x9D83,0x9D84,0x9D85,0x9D86,0x9D87,0x9D88,0x9D89,0x9D8A,0x9D8B,0x9D8C,0x9D8D,0x9D8E, +0x9D8F,0x9D90,0x9D91,0x9D92,0x9D93,0x9D94,0x9D95,0x9D96,0x9D97,0x9D98,0x9D99,0x9D9A,0x9D9B, +0x9D9C,0x9D9D,0x9D9E,0x9D9F,0x9DA0,0x9DA1,0x9DA2,0x9DA3,0x9DA4,0x9DA5,0x9DA6,0x9DA7,0x9DA8, +0x9DA9,0x9DAA,0x9DAB,0x9DAC,0x9DAD,0x9DAE,0x9DAF,0x9DB0,0x9DB1,0x9DB2,0x9DB3,0x9DB4,0x9DB5, +0x9DB6,0x9DB7,0x9DB8,0x9DB9,0x9DBA,0x9DBB,0x9DBC,0x9DBD,0x9DBE,0x9DBF,0x9DC0,0x9DC1,0x9DC2, +0x9DC3,0x9DC4,0x9DC5,0x9DC6,0x9DC7,0x9DC8,0x9DC9,0x9DCA,0x9DCB,0x9DCC,0x9DCD,0x9DCE,0x9DCF, +0x9DD0,0x9DD1,0x9DD2,0x9DD3,0x9DD4,0x9DD5,0x9DD6,0x9DD7,0x9DD8,0x9DD9,0x9DDA,0x9DDB,0x9DDC, +0x9DDD,0x9DDE,0x9DDF,0x9DE0,0x9DE1,0x9DE2,0x9DE3,0x9DE4,0x9DE5,0x9DE6,0x9DE7,0x9DE8,0x9DE9, +0x9DEA,0x9DEB,0x9DEC,0x9DED,0x9DEE,0x9DEF,0x9DF0,0x9DF1,0x9DF2,0x9DF3,0x9DF4,0x9DF5,0x9DF6, +0x9DF7,0x9DF8,0x9DF9,0x9DFA,0x9DFB,0x9DFC,0x9DFD,0x9DFE,0x9DFF,0x9E00,0x9E01,0x9E02,0x9E03, +0x9E04,0x9E05,0x9E06,0x9E07,0x9E08,0x9E09,0x9E0A,0x9E0B,0x9E0C,0x9E0D,0x9E0E,0x9E0F,0x9E10, +0x9E11,0x9E12,0x9E13,0x9E14,0x9E15,0x9E16,0x9E17,0x9E18,0x9E19,0x9E1A,0x9E1B,0x9E1C,0x9E1D, +0x9E1E,0x9E24,0x9E27,0x9E2E,0x9E30,0x9E34,0x9E3B,0x9E3C,0x9E40,0x9E4D,0x9E50,0x9E52,0x9E53, +0x9E54,0x9E56,0x9E59,0x9E5D,0x9E5F,0x9E60,0x9E61,0x9E62,0x9E65,0x9E6E,0x9E6F,0x9E72,0x9E74, +0x9E75,0x9E76,0x9E77,0x9E78,0x9E79,0x9E7A,0x9E7B,0x9E7C,0x9E7D,0x9E80,0x9E81,0x9E83,0x9E84, +0x9E85,0x9E86,0x9E89,0x9E8A,0x9E8C,0x9E8D,0x9E8E,0x9E8F,0x9E90,0x9E91,0x9E94,0x9E95,0x9E96, +0x9E97,0x9E98,0x9E99,0x9E9A,0x9E9B,0x9E9C,0x9E9E,0x9EA0,0x9EA1,0x9EA2,0x9EA3,0x9EA4,0x9EA5, +0x9EA7,0x9EA8,0x9EA9,0x9EAA,0x9EAB,0x9EAC,0x9EAD,0x9EAE,0x9EAF,0x9EB0,0x9EB1,0x9EB2,0x9EB3, +0x9EB5,0x9EB6,0x9EB7,0x9EB9,0x9EBA,0x9EBC,0x9EBF,0x9EC0,0x9EC1,0x9EC2,0x9EC3,0x9EC5,0x9EC6, +0x9EC7,0x9EC8,0x9ECA,0x9ECB,0x9ECC,0x9ED0,0x9ED2,0x9ED3,0x9ED5,0x9ED6,0x9ED7,0x9ED9,0x9EDA, +0x9EDE,0x9EE1,0x9EE3,0x9EE4,0x9EE6,0x9EE8,0x9EEB,0x9EEC,0x9EED,0x9EEE,0x9EF0,0x9EF1,0x9EF2, +0x9EF3,0x9EF4,0x9EF5,0x9EF6,0x9EF7,0x9EF8,0x9EFA,0x9EFD,0x9EFF,0x9F00,0x9F01,0x9F02,0x9F03, +0x9F04,0x9F05,0x9F06,0x9F07,0x9F08,0x9F09,0x9F0A,0x9F0C,0x9F0F,0x9F11,0x9F12,0x9F14,0x9F15, +0x9F16,0x9F18,0x9F1A,0x9F1B,0x9F1C,0x9F1D,0x9F1E,0x9F1F,0x9F21,0x9F23,0x9F24,0x9F25,0x9F26, +0x9F27,0x9F28,0x9F29,0x9F2A,0x9F2B,0x9F2D,0x9F2E,0x9F30,0x9F31,0x9F32,0x9F33,0x9F34,0x9F35, +0x9F36,0x9F38,0x9F3A,0x9F3C,0x9F3F,0x9F40,0x9F41,0x9F42,0x9F43,0x9F45,0x9F46,0x9F47,0x9F48, +0x9F49,0x9F4A,0x9F4B,0x9F4C,0x9F4D,0x9F4E,0x9F4F,0x9F52,0x9F53,0x9F54,0x9F55,0x9F56,0x9F57, +0x9F58,0x9F59,0x9F5A,0x9F5B,0x9F5C,0x9F5D,0x9F5E,0x9F5F,0x9F60,0x9F61,0x9F62,0x9F63,0x9F64, +0x9F65,0x9F66,0x9F67,0x9F68,0x9F69,0x9F6A,0x9F6B,0x9F6C,0x9F6D,0x9F6E,0x9F6F,0x9F70,0x9F71, +0x9F72,0x9F73,0x9F74,0x9F75,0x9F76,0x9F77,0x9F78,0x9F79,0x9F7A,0x9F7B,0x9F7C,0x9F7D,0x9F7E, +0x9F81,0x9F82,0x9F8D,0x9F8E,0x9F8F,0x9F90,0x9F91,0x9F92,0x9F93,0x9F94,0x9F95,0x9F96,0x9F97, +0x9F98,0x9F9C,0x9F9D,0x9F9E,0x9FA1,0x9FA2,0x9FA3,0x9FA4,0x9FA5,0xF92C,0xF979,0xF995,0xF9E7, +0xF9F1,0xFA0C,0xFA0D,0xFA0E,0xFA0F,0xFA11,0xFA13,0xFA14,0xFA18,0xFA1F,0xFA20,0xFA21,0xFA23, +0xFA24,0xFA27,0xFA28,0xFA29,0 +}; + +const unsigned short CP936CU[22047] = +{0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93, +0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6, +0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9, +0xBA,0xBB,0xBC,0xBD,0xBE,0xBF,0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC, +0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, +0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2, +0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF,0x00,0x01,0x02,0x03,0x04,0x05, +0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18, +0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B, +0x2C,0x2D,0x2E,0x2F,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E, +0x3F,0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F,0x50,0x51, +0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F,0x60,0x61,0x62,0x63,0x64, +0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, +0x78,0x79,0x7A,0x7B,0x7C,0x7D,0x7E,0x7F,0xA1E8,0xA1EC,0xA1A7,0xA1E3,0xA1C0,0xA1A4,0xA1C1,0xA8A4, +0xA8A2,0xA8A8,0xA8A6,0xA8BA,0xA8AC,0xA8AA,0xA8B0,0xA8AE,0xA1C2,0xA8B4,0xA8B2,0xA8B9,0xA8A1, +0xA8A5,0xA8A7,0xA8A9,0xA8BD,0xA8BE,0xA8AD,0xA8B1,0xA8A3,0xA8AB,0xA8AF,0xA8B3,0xA8B5,0xA8B6, +0xA8B7,0xA8B8,0xA8BB,0xA8C0,0xA1A6,0xA1A5,0xA840,0xA841,0xA842,0xA6A1,0xA6A2,0xA6A3,0xA6A4, +0xA6A5,0xA6A6,0xA6A7,0xA6A8,0xA6A9,0xA6AA,0xA6AB,0xA6AC,0xA6AD,0xA6AE,0xA6AF,0xA6B0,0xA6B1, +0xA6B2,0xA6B3,0xA6B4,0xA6B5,0xA6B6,0xA6B7,0xA6B8,0xA6C1,0xA6C2,0xA6C3,0xA6C4,0xA6C5,0xA6C6, +0xA6C7,0xA6C8,0xA6C9,0xA6CA,0xA6CB,0xA6CC,0xA6CD,0xA6CE,0xA6CF,0xA6D0,0xA6D1,0xA6D2,0xA6D3, +0xA6D4,0xA6D5,0xA6D6,0xA6D7,0xA6D8,0xA7A7,0xA7A1,0xA7A2,0xA7A3,0xA7A4,0xA7A5,0xA7A6,0xA7A8, +0xA7A9,0xA7AA,0xA7AB,0xA7AC,0xA7AD,0xA7AE,0xA7AF,0xA7B0,0xA7B1,0xA7B2,0xA7B3,0xA7B4,0xA7B5, +0xA7B6,0xA7B7,0xA7B8,0xA7B9,0xA7BA,0xA7BB,0xA7BC,0xA7BD,0xA7BE,0xA7BF,0xA7C0,0xA7C1,0xA7D1, +0xA7D2,0xA7D3,0xA7D4,0xA7D5,0xA7D6,0xA7D8,0xA7D9,0xA7DA,0xA7DB,0xA7DC,0xA7DD,0xA7DE,0xA7DF, +0xA7E0,0xA7E1,0xA7E2,0xA7E3,0xA7E4,0xA7E5,0xA7E6,0xA7E7,0xA7E8,0xA7E9,0xA7EA,0xA7EB,0xA7EC, +0xA7ED,0xA7EE,0xA7EF,0xA7F0,0xA7F1,0xA7D7,0xA95C,0xA843,0xA1AA,0xA844,0xA1AC,0xA1AE,0xA1AF, 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+0xF6DC,0xF78B,0xF78C,0xF78D,0xF78E,0xF6DD,0xF6DE,0xCFCA,0xF78F,0xF6DF,0xF6E0,0xF6E1,0xF6E2, +0xF6E3,0xF6E4,0xC0F0,0xF6E5,0xF6E6,0xF6E7,0xF6E8,0xF6E9,0xF790,0xF6EA,0xF791,0xF6EB,0xF6EC, +0xF792,0xF6ED,0xF6EE,0xF6EF,0xF6F0,0xF6F1,0xF6F2,0xF6F3,0xF6F4,0xBEA8,0xF793,0xF6F5,0xF6F6, +0xF6F7,0xF6F8,0xF794,0xF795,0xF796,0xF797,0xF798,0xC8FA,0xF6F9,0xF6FA,0xF6FB,0xF6FC,0xF799, +0xF79A,0xF6FD,0xF6FE,0xF7A1,0xF7A2,0xF7A3,0xF7A4,0xF7A5,0xF79B,0xF79C,0xF7A6,0xF7A7,0xF7A8, +0xB1EE,0xF7A9,0xF7AA,0xF7AB,0xF79D,0xF79E,0xF7AC,0xF7AD,0xC1DB,0xF7AE,0xF79F,0xF7A0,0xF7AF, +0xF840,0xF841,0xF842,0xF843,0xF844,0xF845,0xF846,0xF847,0xF848,0xF849,0xF84A,0xF84B,0xF84C, +0xF84D,0xF84E,0xF84F,0xF850,0xF851,0xF852,0xF853,0xF854,0xF855,0xF856,0xF857,0xF858,0xF859, +0xF85A,0xF85B,0xF85C,0xF85D,0xF85E,0xF85F,0xF860,0xF861,0xF862,0xF863,0xF864,0xF865,0xF866, +0xF867,0xF868,0xF869,0xF86A,0xF86B,0xF86C,0xF86D,0xF86E,0xF86F,0xF870,0xF871,0xF872,0xF873, +0xF874,0xF875,0xF876,0xF877,0xF878,0xF879,0xF87A,0xF87B,0xF87C,0xF87D,0xF87E,0xF880,0xF881, +0xF882,0xF883,0xF884,0xF885,0xF886,0xF887,0xF888,0xF889,0xF88A,0xF88B,0xF88C,0xF88D,0xF88E, +0xF88F,0xF890,0xF891,0xF892,0xF893,0xF894,0xF895,0xF896,0xF897,0xF898,0xF899,0xF89A,0xF89B, +0xF89C,0xF89D,0xF89E,0xF89F,0xF8A0,0xF940,0xF941,0xF942,0xF943,0xF944,0xF945,0xF946,0xF947, +0xF948,0xF949,0xF94A,0xF94B,0xF94C,0xF94D,0xF94E,0xF94F,0xF950,0xF951,0xF952,0xF953,0xF954, +0xF955,0xF956,0xF957,0xF958,0xF959,0xF95A,0xF95B,0xF95C,0xF95D,0xF95E,0xF95F,0xF960,0xF961, +0xF962,0xF963,0xF964,0xF965,0xF966,0xF967,0xF968,0xF969,0xF96A,0xF96B,0xF96C,0xF96D,0xF96E, +0xF96F,0xF970,0xF971,0xF972,0xF973,0xF974,0xF975,0xF976,0xF977,0xF978,0xF979,0xF97A,0xF97B, +0xF97C,0xF97D,0xF97E,0xF980,0xF981,0xF982,0xF983,0xF984,0xF985,0xF986,0xF987,0xF988,0xF989, +0xF98A,0xF98B,0xF98C,0xF98D,0xF98E,0xF98F,0xF990,0xF991,0xF992,0xF993,0xF994,0xF995,0xF996, +0xF997,0xF998,0xF999,0xF99A,0xF99B,0xF99C,0xF99D,0xF99E,0xF99F,0xF9A0,0xFA40,0xFA41,0xFA42, +0xFA43,0xFA44,0xFA45,0xFA46,0xFA47,0xFA48,0xFA49,0xFA4A,0xFA4B,0xFA4C,0xFA4D,0xFA4E,0xFA4F, +0xFA50,0xFA51,0xFA52,0xFA53,0xFA54,0xFA55,0xFA56,0xFA57,0xFA58,0xFA59,0xFA5A,0xFA5B,0xFA5C, +0xFA5D,0xFA5E,0xFA5F,0xFA60,0xFA61,0xFA62,0xFA63,0xFA64,0xFA65,0xFA66,0xFA67,0xFA68,0xFA69, +0xFA6A,0xFA6B,0xFA6C,0xFA6D,0xFA6E,0xFA6F,0xFA70,0xFA71,0xFA72,0xFA73,0xFA74,0xFA75,0xFA76, +0xFA77,0xFA78,0xFA79,0xFA7A,0xFA7B,0xFA7C,0xFA7D,0xFA7E,0xFA80,0xFA81,0xFA82,0xFA83,0xFA84, +0xFA85,0xFA86,0xFA87,0xFA88,0xFA89,0xFA8A,0xFA8B,0xFA8C,0xFA8D,0xFA8E,0xFA8F,0xFA90,0xFA91, +0xFA92,0xFA93,0xFA94,0xFA95,0xFA96,0xFA97,0xFA98,0xFA99,0xFA9A,0xFA9B,0xFA9C,0xFA9D,0xFA9E, +0xFA9F,0xFAA0,0xFB40,0xFB41,0xFB42,0xFB43,0xFB44,0xFB45,0xFB46,0xFB47,0xFB48,0xFB49,0xFB4A, +0xFB4B,0xFB4C,0xFB4D,0xFB4E,0xFB4F,0xFB50,0xFB51,0xFB52,0xFB53,0xFB54,0xFB55,0xFB56,0xFB57, +0xFB58,0xFB59,0xFB5A,0xFB5B,0xC4F1,0xF0AF,0xBCA6,0xF0B0,0xC3F9,0xFB5C,0xC5B8,0xD1BB,0xFB5D, +0xF0B1,0xF0B2,0xF0B3,0xF0B4,0xF0B5,0xD1BC,0xFB5E,0xD1EC,0xFB5F,0xF0B7,0xF0B6,0xD4A7,0xFB60, +0xCDD2,0xF0B8,0xF0BA,0xF0B9,0xF0BB,0xF0BC,0xFB61,0xFB62,0xB8EB,0xF0BD,0xBAE8,0xFB63,0xF0BE, +0xF0BF,0xBEE9,0xF0C0,0xB6EC,0xF0C1,0xF0C2,0xF0C3,0xF0C4,0xC8B5,0xF0C5,0xF0C6,0xFB64,0xF0C7, +0xC5F4,0xFB65,0xF0C8,0xFB66,0xFB67,0xFB68,0xF0C9,0xFB69,0xF0CA,0xF7BD,0xFB6A,0xF0CB,0xF0CC, +0xF0CD,0xFB6B,0xF0CE,0xFB6C,0xFB6D,0xFB6E,0xFB6F,0xF0CF,0xBAD7,0xFB70,0xF0D0,0xF0D1,0xF0D2, +0xF0D3,0xF0D4,0xF0D5,0xF0D6,0xF0D8,0xFB71,0xFB72,0xD3A5,0xF0D7,0xFB73,0xF0D9,0xFB74,0xFB75, +0xFB76,0xFB77,0xFB78,0xFB79,0xFB7A,0xFB7B,0xFB7C,0xFB7D,0xF5BA,0xC2B9,0xFB7E,0xFB80,0xF7E4, +0xFB81,0xFB82,0xFB83,0xFB84,0xF7E5,0xF7E6,0xFB85,0xFB86,0xF7E7,0xFB87,0xFB88,0xFB89,0xFB8A, +0xFB8B,0xFB8C,0xF7E8,0xC2B4,0xFB8D,0xFB8E,0xFB8F,0xFB90,0xFB91,0xFB92,0xFB93,0xFB94,0xFB95, +0xF7EA,0xFB96,0xF7EB,0xFB97,0xFB98,0xFB99,0xFB9A,0xFB9B,0xFB9C,0xC2F3,0xFB9D,0xFB9E,0xFB9F, +0xFBA0,0xFC40,0xFC41,0xFC42,0xFC43,0xFC44,0xFC45,0xFC46,0xFC47,0xFC48,0xF4F0,0xFC49,0xFC4A, +0xFC4B,0xF4EF,0xFC4C,0xFC4D,0xC2E9,0xFC4E,0xF7E1,0xF7E2,0xFC4F,0xFC50,0xFC51,0xFC52,0xFC53, +0xBBC6,0xFC54,0xFC55,0xFC56,0xFC57,0xD9E4,0xFC58,0xFC59,0xFC5A,0xCAF2,0xC0E8,0xF0A4,0xFC5B, +0xBADA,0xFC5C,0xFC5D,0xC7AD,0xFC5E,0xFC5F,0xFC60,0xC4AC,0xFC61,0xFC62,0xF7EC,0xF7ED,0xF7EE, +0xFC63,0xF7F0,0xF7EF,0xFC64,0xF7F1,0xFC65,0xFC66,0xF7F4,0xFC67,0xF7F3,0xFC68,0xF7F2,0xF7F5, +0xFC69,0xFC6A,0xFC6B,0xFC6C,0xF7F6,0xFC6D,0xFC6E,0xFC6F,0xFC70,0xFC71,0xFC72,0xFC73,0xFC74, +0xFC75,0xEDE9,0xFC76,0xEDEA,0xEDEB,0xFC77,0xF6BC,0xFC78,0xFC79,0xFC7A,0xFC7B,0xFC7C,0xFC7D, +0xFC7E,0xFC80,0xFC81,0xFC82,0xFC83,0xFC84,0xF6BD,0xFC85,0xF6BE,0xB6A6,0xFC86,0xD8BE,0xFC87, +0xFC88,0xB9C4,0xFC89,0xFC8A,0xFC8B,0xD8BB,0xFC8C,0xDCB1,0xFC8D,0xFC8E,0xFC8F,0xFC90,0xFC91, +0xFC92,0xCAF3,0xFC93,0xF7F7,0xFC94,0xFC95,0xFC96,0xFC97,0xFC98,0xFC99,0xFC9A,0xFC9B,0xFC9C, +0xF7F8,0xFC9D,0xFC9E,0xF7F9,0xFC9F,0xFCA0,0xFD40,0xFD41,0xFD42,0xFD43,0xFD44,0xF7FB,0xFD45, +0xF7FA,0xFD46,0xB1C7,0xFD47,0xF7FC,0xF7FD,0xFD48,0xFD49,0xFD4A,0xFD4B,0xFD4C,0xF7FE,0xFD4D, +0xFD4E,0xFD4F,0xFD50,0xFD51,0xFD52,0xFD53,0xFD54,0xFD55,0xFD56,0xFD57,0xC6EB,0xECB4,0xFD58, +0xFD59,0xFD5A,0xFD5B,0xFD5C,0xFD5D,0xFD5E,0xFD5F,0xFD60,0xFD61,0xFD62,0xFD63,0xFD64,0xFD65, +0xFD66,0xFD67,0xFD68,0xFD69,0xFD6A,0xFD6B,0xFD6C,0xFD6D,0xFD6E,0xFD6F,0xFD70,0xFD71,0xFD72, +0xFD73,0xFD74,0xFD75,0xFD76,0xFD77,0xFD78,0xFD79,0xFD7A,0xFD7B,0xFD7C,0xFD7D,0xFD7E,0xFD80, +0xFD81,0xFD82,0xFD83,0xFD84,0xFD85,0xB3DD,0xF6B3,0xFD86,0xFD87,0xF6B4,0xC1E4,0xF6B5,0xF6B6, +0xF6B7,0xF6B8,0xF6B9,0xF6BA,0xC8A3,0xF6BB,0xFD88,0xFD89,0xFD8A,0xFD8B,0xFD8C,0xFD8D,0xFD8E, +0xFD8F,0xFD90,0xFD91,0xFD92,0xFD93,0xC1FA,0xB9A8,0xEDE8,0xFD94,0xFD95,0xFD96,0xB9EA,0xD9DF, +0xFD97,0xFD98,0xFD99,0xFD9A,0xFD9B,0xFD9C,0xFD9D,0xFD9E,0xFD9F,0xFDA0,0xFE40,0xFE41,0xFE42, +0xFE43,0xFE44,0xFE45,0xFE46,0xFE47,0xFE48,0xFE49,0xFE4A,0xFE4B,0xFE4C,0xFE4D,0xFE4E,0xFE4F, +0xA955,0xA6F2,0xA6F4,0xA6F5,0xA6E0,0xA6E1,0xA6F0,0xA6F1,0xA6E2,0xA6E3,0xA6EE,0xA6EF,0xA6E6, +0xA6E7,0xA6E4,0xA6E5,0xA6E8,0xA6E9,0xA6EA,0xA6EB,0xA968,0xA969,0xA96A,0xA96B,0xA96C,0xA96D, +0xA96E,0xA96F,0xA970,0xA971,0xA972,0xA973,0xA974,0xA975,0xA976,0xA977,0xA978,0xA979,0xA97A, +0xA97B,0xA97C,0xA97D,0xA97E,0xA980,0xA981,0xA982,0xA983,0xA984,0xA985,0xA986,0xA987,0xA988, +0xA3A1,0xA3A2,0xA3A3,0xA1E7,0xA3A5,0xA3A6,0xA3A7,0xA3A8,0xA3A9,0xA3AA,0xA3AB,0xA3AC,0xA3AD, +0xA3AE,0xA3AF,0xA3B0,0xA3B1,0xA3B2,0xA3B3,0xA3B4,0xA3B5,0xA3B6,0xA3B7,0xA3B8,0xA3B9,0xA3BA, +0xA3BB,0xA3BC,0xA3BD,0xA3BE,0xA3BF,0xA3C0,0xA3C1,0xA3C2,0xA3C3,0xA3C4,0xA3C5,0xA3C6,0xA3C7, +0xA3C8,0xA3C9,0xA3CA,0xA3CB,0xA3CC,0xA3CD,0xA3CE,0xA3CF,0xA3D0,0xA3D1,0xA3D2,0xA3D3,0xA3D4, +0xA3D5,0xA3D6,0xA3D7,0xA3D8,0xA3D9,0xA3DA,0xA3DB,0xA3DC,0xA3DD,0xA3DE,0xA3DF,0xA3E0,0xA3E1, +0xA3E2,0xA3E3,0xA3E4,0xA3E5,0xA3E6,0xA3E7,0xA3E8,0xA3E9,0xA3EA,0xA3EB,0xA3EC,0xA3ED,0xA3EE, +0xA3EF,0xA3F0,0xA3F1,0xA3F2,0xA3F3,0xA3F4,0xA3F5,0xA3F6,0xA3F7,0xA3F8,0xA3F9,0xA3FA,0xA3FB, +0xA3FC,0xA3FD,0xA1AB,0xA1E9,0xA1EA,0xA956,0xA3FE,0xA957,0xA3A4}; + + +const unsigned short Uni936U[22047] = +{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0x0000,0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B, +0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018, +0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025, 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+unsigned int TEpDevice::GetInputModuleChannelCount(void) +{ + unsigned int i=0; + /*i = (fData.Split.Flag & 0x03) +1;*/ + return i; +} +unsigned int TEpDevice::GetOutputModuleChannelCount(void) +{ + unsigned int i=0; + /*i = (fData.Split.Flag & 0x03) +1;*/ + return i; +} +unsigned int TEpDevice::GetInOutModuleInChannelCount(void) +{ + unsigned int i=0; + /*i = (fData.Split.Flag & 0x01) +1;*/ + return i; +} +unsigned int TEpDevice::GetInOutModuleOutChannelCount(void) +{ + unsigned int i=0; + /*if (fData.Split.Flag & 0x02) i=2; + else i =1;*/ + return i; +} + +void TEpDevice::SetInputModuleChannelCount(unsigned int aCount) +{ + /*fData.Split.Flag &= ~0x03; + if(aCount == 2)fData.Split.Flag &= ~0x03; + else if(aCount == 3)fData.Split.Flag &= ~0x03; + else if(aCount == 4)fData.Split.Flag &= ~0x03;*/ +} +void TEpDevice::SetOutputModuleChannelCount(unsigned int aCount) +{ + /*fData.Split.Flag &= ~0x03; + if(aCount == 2)fData.Split.Flag &= ~0x03; + else if(aCount == 3)fData.Split.Flag &= ~0x03; + else if(aCount == 4)fData.Split.Flag &= ~0x03;*/ +} +void TEpDevice::SetInOutModuleInChannelCount(unsigned int aCount) +{ + /*if(aCount >1)fData.Split.Flag |= 0x01;*/ +} +void TEpDevice::SetInOutModuleOutChannelCount(unsigned int aCount) +{ + /*if(aCount >1)fData.Split.Flag |= 0x02;*/ +} + +unsigned int TEpDevice::Calc_Addr4EpData(void) +{ + unsigned int addr=0; + /*unsigned int PortNum, EpNum; + PortNum = static_cast(fData.Split.PortNum); + EpNum = static_cast(fData.Split.Id);*/ + //addr = dAddr_Flash_EpData + (PortNum * 16 * 256) + (EpNum * 16); + return addr; +} + +unsigned int TEpDevice::Calc_Addr4EpDataPage(void) +{ + unsigned int addr=0; + /*unsigned int PortNum, EpNum; + PortNum = static_cast(fData.Split.PortNum); + EpNum = static_cast(fData.Split.Id); + //addr = dAddr_Flash_EpData + (PortNum * 16 * 256) + (EpNum * 16); + addr = addr & 0xFFFFFF00;*/ + return addr; +} + +unsigned int TEpDevice::Calc_Addr4EpDataSector(void) +{ + unsigned int addr =0; + /*unsigned int PortNum, EpNum; + PortNum = static_cast(fData.Split.PortNum); + EpNum = static_cast(fData.Split.Id); + //addr = dAddr_Flash_EpData + (PortNum * 16 * 256) + (EpNum * 16); + addr = addr & 0xFFFFF000;*/ + return addr; +} + +unsigned int TEpDevice::Calc_D4K_PageIndex(void) +{ + unsigned int Index =0; + /*unsigned int PortNum, EpNum; + PortNum = static_cast(fData.Split.PortNum); + EpNum = static_cast(fData.Split.Id); + Index = ((PortNum * 16 * 256) + (EpNum * 16)) / 256;*/ + return Index; +} + +void TEpDevice::Copy_DataFrom4KData(unsigned int *D4K) +{ + /*unsigned int start; + unsigned int EpNum; + EpNum = static_cast(fData.Split.Id); + start = (EpNum * 16) / 4;*/ +} + +void TEpDevice::Write_DataTo4KData(unsigned int *D4K) +{ + /*unsigned int start; + unsigned int EpNum; + EpNum = static_cast(fData.Split.Id); + start = (EpNum * 16) / 4;*/ +} + + +//smoke +//const char cPrmSensitivity[8] = {"灵敏度"}; +//const char cPrmTH[8] = {"上阀值"}; +//const char cPrmTL[8] = {"下阀值"}; +//const char cPrmPollute[8] = {"污染度"}; + +//tempe +//const char cPrmAlarm[8] = {"报警值"}; +//const char cPrmWarn[8] = {"预警值"}; +//const char cPrmHoldTime[8] = {"时间值"}; + +void TEpDevice::PrintProperty(TMyString *Str0, TMyString *Str1, TMyString *Str2) +{ + //Str0->FromUInt6Dg(fData.Split.UserCode); + /*Str1->FromUInt3Dg(fData.Split.Id); + Str2->FromStr(StrType[fData.Split.dType]);*/ +} + + +void TEpDevice::PrintAttribute(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3) +{ + /*switch(fData.Split.dType){ + case dgTYPE_SMOKE_DETECTOR: + //Str0->FromStr("灵敏度"); + // Str0->FromUInt3Dg(fPrm.Smoke.Sensitivity); + //Str1->FromStr("上阀值"); + // Str1->FromUInt3Dg(fPrm.Smoke.UpPoint); + //Str2->FromStr("下阀值"); + // Str2->FromUInt3Dg(fPrm.Smoke.DownPoint); + //Str3->FromStr("污染度"); + // Str3->FromUInt3Dg(fPrm.Smoke.Pollute); + break; + + case dgTYPE_TEMPE_DETECTOR: + //Str0->FromStr("报警值"); + // Str0->FromUInt3Dg(fPrm.Tempe.AlarmPoint); + //Str1->FromStr("预警值"); + // Str1->FromUInt3Dg(fPrm.Tempe.WarningPoint); + //Str2->FromStr("时间值"); + // Str2->FromUInt3Dg(fPrm.Tempe.HoldTime_100mS); + break; + + //case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + //case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + //Str0->FromStr("灵敏度"); + // Str0->FromUInt3Dg(fPrm.SmokeTempe.Sensitivity); + //Str1->FromStr("污染度"); + // Str1->FromUInt3Dg(fPrm.SmokeTempe.Pollute); + //Str2->FromStr("报警值"); + // Str2->FromUInt3Dg(fPrm.SmokeTempe.AlarmPoint); + //Str3->FromStr("时间值"); + // Str3->FromUInt3Dg(fPrm.SmokeTempe.HoldTime_100mS); + // break; + + case dgTYPE_HAND_REPORT: + + break; + case dgTYPE_IN_MODULE: + + break; + case dgTYPE_OUT_MODULE: + + break; + case dgTYPE_INOUT_MODULE_NonSource: + case dgTYPE_INOUT_MODULE_Source: + + break; + case dgType_VAALRAM: + + break; + //case dgTYPE_BUS_BROKE: + + /// break; + + case dgTYPE_DISPLAY_PAD: + + break; + }*/ +} + +void TEpDevice::PrintAttribute(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5, TMyString *Str6, TMyString *Str7 ) +{ + /*switch(fData.Split.dType){ + case dgTYPE_SMOKE_DETECTOR: + //Str0->FromStr("灵敏度"); + // Str0->FromUInt3Dg(fPrm.Smoke.Sensitivity); + //Str1->FromStr("上阀值"); + // Str1->FromUInt3Dg(fPrm.Smoke.UpPoint); + //Str2->FromStr("下阀值"); + // Str2->FromUInt3Dg(fPrm.Smoke.DownPoint); + //Str3->FromStr("污染度"); + // Str3->FromUInt3Dg(fPrm.Smoke.Pollute); + break; + + case dgTYPE_TEMPE_DETECTOR: + //Str0->FromStr("报警值"); + // Str0->FromUInt3Dg(fPrm.Tempe.AlarmPoint); + //Str1->FromStr("预警值"); + // Str1->FromUInt3Dg(fPrm.Tempe.WarningPoint); + //Str2->FromStr("时间值"); + // Str2->FromUInt3Dg(fPrm.Tempe.HoldTime_100mS); + break; + + //case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + //case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + //Str0->FromStr("灵敏度"); + // Str0->FromUInt3Dg(fPrm.SmokeTempe.Sensitivity); + //Str1->FromStr("上阀值"); + // Str1->FromUInt3Dg(fPrm.SmokeTempe.UpPoint); + //Str2->FromStr("下阀值"); + // Str2->FromUInt3Dg(fPrm.SmokeTempe.DownPoint); + //Str3->FromStr("污染度"); + // Str3->FromUInt3Dg(fPrm.SmokeTempe.Pollute); + //Str4->FromStr("报警值"); + // Str4->FromUInt3Dg(fPrm.SmokeTempe.AlarmPoint); + //Str5->FromStr("预警值"); + // Str5->FromUInt3Dg(fPrm.SmokeTempe.WarningPoint); + //Str6->FromStr("时间值"); + // Str6->FromUInt3Dg(fPrm.SmokeTempe.HoldTime_100mS); + //break; + + case dgTYPE_HAND_REPORT: + + break; + case dgTYPE_IN_MODULE: + + break; + case dgTYPE_OUT_MODULE: + + break; + case dgTYPE_INOUT_MODULE_NonSource: + case dgTYPE_INOUT_MODULE_Source: + + break; + case dgType_VAALRAM: + + break; + //case dgTYPE_BUS_BROKE: + + // break; + + + case dgTYPE_DISPLAY_PAD: + + break; + }*/ +} + + + +void TEpDevice::PrintAttributeWithAName(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3) +{ + /*switch(fData.Split.dType){ + case dgTYPE_SMOKE_DETECTOR: + Str0->FromStr("灵敏度"); + // Str0->AddOn3Dg(fPrm.Smoke.Sensitivity); + Str1->FromStr("报警点"); + // Str1->AddOn3Dg(fPrm.Smoke.UpPoint); + Str2->FromStr("下阀值"); + // Str2->AddOn3Dg(fPrm.Smoke.DownPoint); + Str3->FromStr("污染度"); + // Str3->AddOn3Dg(fPrm.Smoke.Pollute); + break; + + case dgTYPE_TEMPE_DETECTOR: + Str0->FromStr("报警值"); + // Str0->AddOn3Dg(fPrm.Tempe.AlarmPoint); + Str1->FromStr("预警值"); + // Str1->AddOn3Dg(fPrm.Tempe.WarningPoint); + Str2->FromStr("时间值"); + // Str2->AddOn3Dg(fPrm.Tempe.HoldTime_100mS); + break; + + //case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + //case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + // Str0->FromStr("报警点"); + // Str0->AddOn3Dg(fPrm.SmokeTempe.UpPoint); + // Str1->FromStr("污染度"); + // Str1->AddOn3Dg(fPrm.SmokeTempe.Pollute); + // Str2->FromStr("报警值"); + // Str2->AddOn3Dg(fPrm.SmokeTempe.AlarmPoint); + // Str3->FromStr("延时"); + // Str3->AddOn3Dg(fPrm.SmokeTempe.HoldTime_100mS); + // break; + + case dgTYPE_HAND_REPORT: + + break; + case dgTYPE_IN_MODULE: + + break; + case dgTYPE_OUT_MODULE: + + break; + case dgTYPE_INOUT_MODULE_NonSource: + case dgTYPE_INOUT_MODULE_Source: + + break; + case dgType_VAALRAM: + + break; + //case dgTYPE_BUS_BROKE: + + // break; + + + case dgTYPE_DISPLAY_PAD: + + break; + }*/ +} + +void TEpDevice::PrintAttributeWithAName(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5, TMyString *Str6, TMyString *Str7 ) +{ + /*switch(fData.Split.dType){ + case dgTYPE_SMOKE_DETECTOR: + Str0->FromStr("灵敏度"); + // Str0->AddOn3Dg(fPrm.Smoke.Sensitivity); + Str1->FromStr("上阀值"); + // Str1->AddOn3Dg(fPrm.Smoke.UpPoint); + Str2->FromStr("下阀值"); + // Str2->AddOn3Dg(fPrm.Smoke.DownPoint); + Str3->FromStr("污染度"); + // Str3->AddOn3Dg(fPrm.Smoke.Pollute); + break; + + case dgTYPE_TEMPE_DETECTOR: + Str0->FromStr("报警值"); + // Str0->AddOn3Dg(fPrm.Tempe.AlarmPoint); + Str1->FromStr("预警值"); + // Str1->AddOn3Dg(fPrm.Tempe.WarningPoint); + Str2->FromStr("时间值"); + // Str2->AddOn3Dg(fPrm.Tempe.HoldTime_100mS); + break; + + //case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + //case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + // Str0->FromStr("灵敏度"); + // Str0->AddOn3Dg(fPrm.SmokeTempe.Sensitivity); + // Str1->FromStr("上阀值"); + // Str1->AddOn3Dg(fPrm.SmokeTempe.UpPoint); + // Str2->FromStr("下阀值"); + // Str2->AddOn3Dg(fPrm.SmokeTempe.DownPoint); + // Str3->FromStr("污染度"); + // Str3->AddOn3Dg(fPrm.SmokeTempe.Pollute); + // Str4->FromStr("报警值"); + // Str4->AddOn3Dg(fPrm.SmokeTempe.AlarmPoint); + // Str5->FromStr("预警值"); + // Str5->AddOn3Dg(fPrm.SmokeTempe.WarningPoint); + // Str6->FromStr("时间值"); + // Str6->AddOn3Dg(fPrm.SmokeTempe.HoldTime_100mS); + // break; + + case dgTYPE_HAND_REPORT: + + break; + case dgTYPE_IN_MODULE: + + break; + case dgTYPE_OUT_MODULE: + + break; + case dgTYPE_INOUT_MODULE_NonSource: + case dgTYPE_INOUT_MODULE_Source: + + break; + case dgType_VAALRAM: + + break; + //case dgTYPE_BUS_BROKE: + + // break; + + + case dgTYPE_DISPLAY_PAD: + + break; + }*/ +} + + +void TEpDevice::PrintSensitivity(TMyString *Str0) +{ + /*switch(fData.Split.dType){ + case dgTYPE_SMOKE_DETECTOR: + // Str0->FromUInt3Dg(fPrm.Smoke.Sensitivity); + break; + //case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + //case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + // Str0->FromUInt3Dg(fPrm.SmokeTempe.Sensitivity); + // break; + + }*/ +} + +void TEpDevice::PrintDynamicsData(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5) +{ + /*switch(fData.Split.dType){ + case dgTYPE_SMOKE_DETECTOR: + //Str0->FromUInt4Dg(fPrm.Smoke.IRVal); + //Str1->FromUInt4Dg(fPrm.Smoke.BlueVal); + //Str1->FromUInt4Dg(fPrm.Smoke.P1); + //Str1->FromUInt4Dg(fPrm.Smoke.P2); + break; + case dgTYPE_TEMPE_DETECTOR: + //Str0->FromUInt4Dg(fPrm.Tempe.DegVal); + break; + //case dgTYPE_SMOKE_TEMPE_DETECTOR_I: + //case dgTYPE_SMOKE_TEMPE_DETECTOR_II: + // Str0->FromUInt4Dg(fPrm.Smoke.IRVal); + // Str1->FromUInt4Dg(fPrm.Smoke.BlueVal); + // Str2->FromUInt4Dg(fPrm.Smoke.P1); + // Str3->FromUInt4Dg(fPrm.Smoke.P2); + // Str4->AddOn3Dg(fPrm.SmokeTempe.DegVal); + // break; + + case dgTYPE_HAND_REPORT: + + break; + case dgTYPE_IN_MODULE: + + break; + case dgTYPE_OUT_MODULE: + + break; + case dgTYPE_INOUT_MODULE_NonSource: + case dgTYPE_INOUT_MODULE_Source: + + break; + case dgType_VAALRAM: + + break; + //case dgTYPE_BUS_BROKE: + + // break; + case dgTYPE_DISPLAY_PAD: + + break; + }*/ +} + + diff --git a/MyCode/src/EpDevice.h b/MyCode/src/EpDevice.h new file mode 100644 index 0000000..3a8ff5e --- /dev/null +++ b/MyCode/src/EpDevice.h @@ -0,0 +1,149 @@ +#ifndef EPDEVICE_H_ +#define EPDEVICE_H_ + +#include "gvalue.h" +#include "gType.h" +#include "my_string.h" + +#define dEpDevTypeMin dgTYPE_COMM_CHANNEL //13 +#define dEpDevTypeMax dgTYPE_DISPLAY_PAD_I //23 + +typedef union{ + unsigned int D32[2]; + unsigned char D8[8]; + struct{ + unsigned char Sensitivity; + unsigned char UpPoint; + unsigned char DownPoint; + unsigned char Pollute ; + unsigned char IRVal; + unsigned char BlueVal; + unsigned char P1; + unsigned char P2; + }Smoke; + struct{ + unsigned char AlarmPoint; + unsigned char WarningPoint; + unsigned char HoldTime_100mS; + unsigned char DegVal; + }Tempe; + struct{ + unsigned char Sensitivity; + unsigned char UpPoint; + unsigned char DownPoint; + unsigned char Pollute ; + + unsigned char AlarmPoint; + unsigned char WarningPoint; + unsigned char HoldTime_100mS; + unsigned char DegVal; + }SmokeTempe; + struct{ + unsigned char OnOff; + }HandReport; + struct{ + unsigned char OnOff[4]; + }IsoInput; + struct{ + unsigned char OnOff[4]; + }IsoOutput; + struct{ + unsigned char InOnOff[2]; + unsigned char OutOnOff[2]; + }IsoIo; + struct{ + unsigned char BellOnOff; + unsigned char LumOnOff; + }VaAlram; + struct{ + unsigned char Lum; + unsigned char Size; + unsigned char *pchar; + }Display; + struct{ + unsigned char AlarmPoint; + unsigned char WarningPoint; + unsigned char Rsv0; + unsigned char Rsv1; + unsigned short dVal; + unsigned short dump0; + }Quake; + struct{ + unsigned char AlarmPoint; + unsigned char WarningPoint; + unsigned char Rsv0; + unsigned char Rsv1; + unsigned short dVal; + unsigned short dump0; + }Radar; +}TEpPrm; + + +typedef union{ + unsigned int D32; + unsigned char D8[4]; + struct{ + unsigned char dType; + unsigned char Id; + unsigned char PortNum; + unsigned char Flag; + //unsigned int UserCode; + }Split; +}TEpData; + +class TEpDevice { + public: + //TEpData fData; + //TEpPrm fPrm; + //unsigned short DynamicsFlag; + //unsigned char NotUpdataHours; + //unsigned char Not2; + private: + unsigned int Calc_Addr4EpData(void); + unsigned int Calc_Addr4EpDataPage(void); + unsigned int Calc_Addr4EpDataSector(void); + unsigned int Calc_D4K_PageIndex(void); + void Copy_DataFrom4KData(unsigned int *D4K); + void Write_DataTo4KData(unsigned int *D4K); + + public: + TEpDevice(void){ + //fData.D32= 0; + + //fPrm.D32[0] = 0; + //fPrm.D32[1] = 0; + } + void AssignByData(unsigned int *da); + + void PrintSensitivity(TMyString *Str0); + void PrintProperty(TMyString *Str0, TMyString *Str1, TMyString *Str2); //UserCode Id dType + void PrintAttribute(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3); + void PrintAttribute(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5, TMyString *Str6, TMyString *Str7 ); + void PrintAttributeWithAName(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3); + void PrintAttributeWithAName(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5, TMyString *Str6, TMyString *Str7 ); + void PrintDynamicsData(TMyString *Str0, TMyString *Str1, TMyString *Str2, TMyString *Str3, TMyString *Str4, TMyString *Str5); + + void GetDescp(char *StrGot); + void SetDescp(char *StrPut); + + void SetSmokePrm(unsigned char aSensitivity, unsigned char TimeDelay, unsigned short A, unsigned short B); + void GetSmokePrm(TEpDevice *aInstantial); + + void SetTempePrm(unsigned char aSensitivity, unsigned char Prm1, unsigned short Prm2, unsigned short Prm3); + void GetTempePrm(unsigned char *pSensitivity, unsigned char *pPrm1, unsigned short *pPrm2, unsigned short *pPrm3); + + unsigned int GetInputModuleChannelCount(void); + unsigned int GetOutputModuleChannelCount(void); + unsigned int GetInOutModuleInChannelCount(void); + unsigned int GetInOutModuleOutChannelCount(void); + void SetInputModuleChannelCount(unsigned int aCount); + void SetOutputModuleChannelCount(unsigned int aCount); + void SetInOutModuleInChannelCount(unsigned int aCount); + void SetInOutModuleOutChannelCount(unsigned int aCount); + +}; + + + +#endif + diff --git a/MyCode/src/GlobalString.cpp b/MyCode/src/GlobalString.cpp new file mode 100644 index 0000000..208e931 --- /dev/null +++ b/MyCode/src/GlobalString.cpp @@ -0,0 +1,13 @@ +#include"GlobalString.h" + + + + + + + + + + + + diff --git a/MyCode/src/GlobalString.h b/MyCode/src/GlobalString.h new file mode 100644 index 0000000..91312b3 --- /dev/null +++ b/MyCode/src/GlobalString.h @@ -0,0 +1,13 @@ +#ifndef GLOBALSTRING_H_ +#define GLOBALSTRING_H_ + + + + + + +#endif + + + + diff --git a/MyCode/src/GrayConvert.c b/MyCode/src/GrayConvert.c new file mode 100644 index 0000000..e69de29 diff --git a/MyCode/src/HistoryMsg.cpp b/MyCode/src/HistoryMsg.cpp new file mode 100644 index 0000000..e69de29 diff --git a/MyCode/src/HistoryMsg.h b/MyCode/src/HistoryMsg.h new file mode 100644 index 0000000..627bb2b --- /dev/null +++ b/MyCode/src/HistoryMsg.h @@ -0,0 +1,68 @@ +#ifndef HISTORYMSG_H_ +#define HISTORYMSG_H_ + +#define dFireAlarmRecordMsgMax 10000 + +typedef union{ + unsigned int DU32; + struct{ + unsigned char B3; + unsigned char B2; + unsigned char B1; + unsigned char B0; + }DU8; +}TDMixu32u8; + +typedef struct{ + unsigned char seconed ; + unsigned char minite ; + unsigned char hour ; + unsigned char day; + unsigned char month; + unsigned char year; + + unsigned char PortNum; + unsigned char EpNum; + + unsigned char Dtype; + unsigned char Action; + unsigned char rev1; + unsigned char rev2; +}TFireAlarmMsg; + +typedef struct{ + unsigned char seconed ; + unsigned char minite ; + unsigned char hour ; + unsigned char day; + unsigned char month; + unsigned char year; + + unsigned char PortNum; + unsigned char EpNum; + unsigned char ActionType; + unsigned char State; + + unsigned int LinkNum; +}TInterLinkMsg; + +class THistoryMsg{ + public: + struct{ + unsigned int Count; + unsigned int LastUpdataIndex; + TFireAlarmMsg Msg[dFireAlarmRecordMsgMax]; + }FireAlarm; + + public: + THistoryMsg(void){ + FireAlarm.Count=0; + FireAlarm.LastUpdataIndex=0; + } + +}; + + +#endif + + diff --git a/MyCode/src/InterLink.cpp b/MyCode/src/InterLink.cpp new file mode 100644 index 0000000..851e728 --- /dev/null +++ b/MyCode/src/InterLink.cpp @@ -0,0 +1,1783 @@ +#include "InterLink.h" +#include "Runtime.h" + +extern "C"{ + #include "user_norflash.h" + #include "user_eeprom.h" + #include "fdcan_task.h" + #include "task.h" + #include "HW_config.h" +} + +void TInterLink::Init(void) +{ + int i; + AllowOld = 0; + LinkIndex = 0; + LinkCount =0; + for(i=0; i= dLinkageOutputBufMaxCOunt)aInx = 0; + if(oBuf.Body[aInx].Spl.Action == dLNKSTART){ + oBuf.Body[aInx].Spl.CtlNum = MainCtl.fData.Split.MyNum; + Path0 = oBuf.Body[aInx].Spl.P0; + Path1 = oBuf.Body[aInx].Spl.P1; + if( (Path0) && (Path0 <= dPORT_MAX_COUNT) && (Path1) ){ + Path0--; Path1--; + + dType = Port[Path0].dTypeTable[Path1]; + Port[Path0].StateTable[Path1] &= ~dEpStateBitDelayStart;; + + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum;; + aIm.Splite.P0 = oBuf.Body[aInx].Spl.P0; + aIm.Splite.P1 = oBuf.Body[aInx].Spl.P1; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.dType = dType; + aIm.Splite.iByte0 = 0x01; + aIm.Splite.Data1 = 0; + + //Record.LinkageAdd(aIm); + //CtlCenter.ieManualPushOneMsgLinkageStart(aIm); + + Data.D8[0] = 0; + Data.D8[1] = MainCtl.fData.Split.MyNum; + Data.D8[2] = oBuf.Body[aInx].Spl.P0; + Data.D8[3] = oBuf.Body[aInx].Spl.P1; + Data.D8[4] = 0; + Data.D8[5] = dType; + Data.D8[6] = 0; + + aIde.BitF.Cmd = 18; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data.D8, 6); + //if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.SlaveDoSend2MasterMachine(aIm, 18); + }else + if( (Path0 >= dADDR_DIRECTPAD_START) && ( Path0 <= dADDR_DIRECTPAD_END) && (Path1)){ + Path1--; + if(Path1 < dDIRECTCTL_KEY_MAX_COUNT){ + Path0 = Path0 - dADDR_DIRECTPAD_START; + if(DirectCtlBoard[Path0].IsRegisted[Path1]){ + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum;; + aIm.Splite.P0 = oBuf.Body[aInx].Spl.P0; + aIm.Splite.P1 = oBuf.Body[aInx].Spl.P1; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.iByte0 = 0x01; + aIm.Splite.Data1 = 0; + + //Record.LinkageAdd(aIm); + //CtlCenter.ieManualPushOneMsgLinkageStart(aIm); + + Data.D8[0] = 0; + Data.D8[1] = MainCtl.fData.Split.MyNum; + Data.D8[2] = oBuf.Body[aInx].Spl.P0; + Data.D8[3] = oBuf.Body[aInx].Spl.P1; + Data.D8[4] = 2; + Data.D8[5] = 0; + + aIde.BitF.Cmd = cmDirectCtlPadLinkageState; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data.D8, 6); + + Data.D8[4] = 0; + Data.D8[5] = 1; + //if(MainCtl.fData.Split.NetworkMode == 0)ProtoC2C.SlaveDoSend2MasterMachine(aIm, 18); + } + } + } + oBuf.Body[aInx].Spl.Action = dLNKNONE; + }else + if(oBuf.Body[aInx].Spl.Action == dLNKSTOP){ + oBuf.Body[aInx].Spl.CtlNum = MainCtl.fData.Split.MyNum; + Path0 = oBuf.Body[aInx].Spl.P0; + Path1 = oBuf.Body[aInx].Spl.P1; + if( (Path0) && (Path0 <= dPORT_MAX_COUNT) && (Path1) ){ + Path0--; Path1--; + + dType = Port[Path0].dTypeTable[Path1]; + Port[Path0].StateTable[Path1] &= ~dEpStateBitDelayStart;; + + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum;; + aIm.Splite.P0 = oBuf.Body[aInx].Spl.P0; + aIm.Splite.P1 = oBuf.Body[aInx].Spl.P1; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.dType = dType; + aIm.Splite.iByte0 = 0x01; + aIm.Splite.Data1 = 0; + + //Record.LinkageAdd(aIm); + //CtlCenter.ieManualPushOneMsgLinkageStart(aIm); + + Data.D8[0] = 0; + Data.D8[1] = MainCtl.fData.Split.MyNum; + Data.D8[2] = oBuf.Body[aInx].Spl.P0; + Data.D8[3] = oBuf.Body[aInx].Spl.P1; + Data.D8[4] = 0; + Data.D8[5] = dType; + Data.D8[6] = 0; + + aIde.BitF.Cmd = cmAutoStop; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data.D8, 6); + //if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.SlaveDoSend2MasterMachine(aIm, 18); + }else + if( (Path0 >= dADDR_DIRECTPAD_START) && ( Path0 <= dADDR_DIRECTPAD_END) && (Path1)){ + Path1--; + if(Path1 < dDIRECTCTL_KEY_MAX_COUNT){ + Path0 = Path0 - dADDR_DIRECTPAD_START; + if(DirectCtlBoard[Path0].IsRegisted[Path1]){ + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum;; + aIm.Splite.P0 = oBuf.Body[aInx].Spl.P0; + aIm.Splite.P1 = oBuf.Body[aInx].Spl.P1; + aIm.Splite.P2 = 0; + + aIm.Splite.mType = etLinkageStart; + aIm.Splite.iByte0 = 0x01; + aIm.Splite.Data1 = 0; + + //Record.LinkageAdd(aIm); + //CtlCenter.ieManualPushOneMsgLinkageStart(aIm); + + Data.D8[0] = 0; + Data.D8[1] = MainCtl.fData.Split.MyNum; + Data.D8[2] = oBuf.Body[aInx].Spl.P0; + Data.D8[3] = oBuf.Body[aInx].Spl.P1; + Data.D8[4] = 3; + Data.D8[5] = 0; + + aIde.BitF.Cmd = cmDirectCtlPadLinkageState; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data.D8, 6); + + Data.D8[4] = 0; + Data.D8[5] = 1; + //if(MainCtl.fData.Split.NetworkMode == 0)ProtoC2C.SlaveDoSend2MasterMachine(aIm, 18); + } + } + } + oBuf.Body[aInx].Spl.Action = dLNKNONE; + }else + if( (oBuf.Body[aInx].Spl.Action == dLNKMATCH) || (oBuf.Body[aInx].Spl.Action == dLNKDISMATCH) ){ + oBuf.Body[aInx].Spl.CtlNum = MainCtl.fData.Split.MyNum; + Path0 = oBuf.Body[aInx].Spl.P0; + Path1 = oBuf.Body[aInx].Spl.P1; + if( (Path0 >= dADDR_DIRECTPAD_START) && ( Path0 <= dADDR_DIRECTPAD_END) && (Path1)){ + Path1-=1; + if(Path1 < dDIRECTCTL_KEY_MAX_COUNT){ + Path0 = Path0 - dADDR_DIRECTPAD_START; + if(DirectCtlBoard[Path0].IsRegisted[Path1]){ + Data.D8[0] = 0; + Data.D8[1] = MainCtl.fData.Split.MyNum; + Data.D8[2] = oBuf.Body[aInx].Spl.P0; + Data.D8[3] = oBuf.Body[aInx].Spl.P1; + if(oBuf.Body[aInx].Spl.Action == dLNKMATCH) + Data.D8[4] = 1; + else + Data.D8[4] = 0; + Data.D8[5] = 0; + + aIde.BitF.Cmd = cmDirectCtlPadLinkageState; + aIde.BitF.Pri = 1; + aIde.BitF.sLvl = 1; + aIde.BitF.dLvl = 7; + aIde.BitF.sAddr = 0; + aIde.BitF.dAddr = 127; + + InnerCan.CmdSendCustom(aIde, Data.D8, 6); + } + } + } + oBuf.Body[aInx].Spl.Action = dLNKNONE; + }else{ + //aIde.BitF.Cmd = 19; + //oBuf.Body[aInx].Spl.CtlNum = MainCtl.fData.Split.MyNum; + //oBuf.Body[aInx].Spl.Action = dLNKNONE; + //Path0 = oBuf.Body[aInx].Spl.P0; + //Path1 = oBuf.Body[aInx].Spl.P1; + //Path0--; Path1--; + //if(Path0 < dPORT_MAX_COUNT){ + // dType = Port[Path0].dTypeTable[Path1]; + // RtManualPushStartMsg(dType,1,oBuf.Body[aInx].D32); + // Record.OperateAdd_ManualStartCancel(oBuf.Body[aInx].D32, etLinkageStartCancel, 0x01); + //}else{ + // return; + //} + oBuf.Body[aInx].Spl.Action = dLNKNONE; + } + + oBuf.ReadIndex = aInx; + } +} + + +void TInterLink::WaitChipIdle(unsigned int aCnt) +{ + volatile unsigned int aWait, Sta; + do{ + for(aWait=0; aWaitdLinkageOutputBufMaxCOunt)return; + + i=aInx-1; + Crc32Reset(); + SysLoopTick = 0; + rAddr4Index = dSdAddrLinkageExp + (i*1024); + for(ord=0; ord<4; ord++){ + if(ord<3)Pst=64; else Pst=63; + for(x=0;xCrc[i]=*(volatile unsigned int *)(rAddr4Index + 63 *4); + rAddr4Index += 256; + } + tCrc=Crc32GetResult(); + if(tCrc == this->Crc[i]){ + if(CrcFlag[i]){ + CrcFlag[i] =0; + CtlCenter.ieAddBrdFaultCancelLinkageStorage(aInx); + } + }else{ + CrcFlag[i] =1; + CtlCenter.ieAddBrdFaultLinkageStorage(aInx); + } +} + +void TInterLink::CheckStorageCrc(unsigned short aInx) +{ + unsigned int x; + unsigned int fAddr4Index; + unsigned int i, ord, ava; + unsigned int Pst; + unsigned char tInx; + unsigned int tCrc; + + if(aInx==0)return; + if(aInx>dLinkageOutputBufMaxCOunt)return; + + i=aInx-1; + Crc32Reset(); + SysLoopTick = 0; + fAddr4Index = dFlashAddrLinkageExp + (i * 1024); + for(ord=0; ord<4; ord++){ + WaitChipIdle(1000); + nor_read_page(dFlashLinkageExpChipX, fAddr4Index, ReadWriteData.D8); + if(ord<3)Pst=64; else Pst=63; + for(x=0;xCrc[i]=ReadWriteData.D32[63]; + fAddr4Index += 256; + } + tCrc=Crc32GetResult(); + if(tCrc == this->Crc[i]){ + if(this->CrcFlag[i]){ + this->CrcFlag[i] =0; + CtlCenter.ieAddBrdFaultCancelLinkageStorage(aInx); + } + }else{ + this->CrcFlag[i] =1; + CtlCenter.ieAddBrdFaultLinkageStorage(aInx); + } +} + +void TInterLink::CheckStorageCrc() +{ + WaitChipIdle(100000); + for(int i=0; iCrc[aInx] = ReadWriteData.D32[63]; + if(this->Crc[aInx] == Crc32GetResult()){ + if(this->CrcFlag[aInx]){ + this->CrcFlag[aInx] =0; + CtlCenter.ieAddBrdFaultCancelLinkageStorage(aInx+1); + } + }else{ + this->CrcFlag[aInx] =1; + CtlCenter.ieAddBrdFaultLinkageStorage(aInx+1); + return -2; + } + //check ava + Idf.D32 = Exp.D32[0]; + if( (Idf.D8[0] != 'T') or (Idf.D8[1] != 'R') or (Idf.D8[2] != 'U') or (Idf.D8[3] != 'E') ){ + return -1; + } + return 0; +} + +void TInterLink::LoadExpression2Ram() +{ + unsigned int x,aInx; + unsigned int fAddr4Index; + unsigned int i, ord, ava; + unsigned int SysLinkAddr; + unsigned int Pst; + unsigned char tInx; + + SysLoopTick = 0; + LoadExpCount(); + WaitChipIdle(10000); + for(i=0; iCrc[aInx]=ReadWriteData.D32[63]; + + } + if(this->Crc[aInx] == Crc32GetResult()){ + if(this->CrcFlag[aInx]){ + this->CrcFlag[aInx] =0; + CtlCenter.ieAddBrdFaultCancelLinkageStorage(aInx+1); + } + }else{ + this->CrcFlag[aInx] =1; + CtlCenter.ieAddBrdFaultLinkageStorage(aInx+1); + } + } + + + } + } +} + +void TInterLink::ForceLoadLinkageExp() +{ + /*int i, Ava; + unsigned int ActualIndex; + volatile unsigned int aAddr; + + if(ForceInx < LinkCount){ + ActualIndex = LinkNumList[ForceInx]; + aAddr = dSdAddrLinkageExp + (ActualIndex * 1024); + for(i=0; i<256; i++){ + Exp.D32[i] = *(volatile unsigned int *)(aAddr + (i * 4)); + } + LinkCurrent = ActualIndex; + }*/ +} + +int TInterLink::GetFireStateViaPath(unsigned int aCode, unsigned char aDType) +{ + unsigned int i, x, HadPrc, Result; + + Result = 0; + HadPrc = 0; + for(i=0; i= Port[i].UserCodeMin) && (aCode <= Port[i].UserCodeMax) ){ + for(x=0; x<256; x++){ + if(Port[i].UcList[x].Full == aCode){ + if(Port[i].dTypeTable[x] == aDType){ + if(Port[i].StateTable[x] & dEpStateBitFire){ + return 1; + } + } + HadPrc = 1; + break; + } + } + } + if(HadPrc)break; + } + for(i=0; i=0; i--){ + if(CtlCenter.FiredUserCode.uCode[i] == 0) continue; + if(RunState != TRunModeCfg::RunModeAdjust){ + if(CtlCenter.FiredUserCode.eType[i] > TControlCenter::LinkInputTypeAvaEdge)continue; + } + if(CtlCenter.FiredUserCode.AssignType[i]) tType = CtlCenter.FiredUserCode.AssignType[i]; + else tType = CtlCenter.FiredUserCode.dType[i]; + if(aDType == tType){ + if(eInput.Asterisk[0])MaskVal.Spl.BcdText_0 = 10; else MaskVal.Spl.BcdText_0 = CtlCenter.FiredUserCode.uCode[i] / 10000000 % 10; + if(eInput.Asterisk[1])MaskVal.Spl.BcdText_1 = 10; else MaskVal.Spl.BcdText_1 = CtlCenter.FiredUserCode.uCode[i] / 1000000 % 10; + if(eInput.Asterisk[2])MaskVal.Spl.BcdText_2 = 10; else MaskVal.Spl.BcdText_2 = CtlCenter.FiredUserCode.uCode[i] / 100000 % 10; + if(eInput.Asterisk[3])MaskVal.Spl.BcdText_3 = 10; else MaskVal.Spl.BcdText_3 = CtlCenter.FiredUserCode.uCode[i] / 10000 % 10; + if(eInput.Asterisk[4])MaskVal.Spl.BcdText_4 = 10; else MaskVal.Spl.BcdText_4 = CtlCenter.FiredUserCode.uCode[i] / 1000 % 10; + if(eInput.Asterisk[5])MaskVal.Spl.BcdText_5 = 10; else MaskVal.Spl.BcdText_5 = CtlCenter.FiredUserCode.uCode[i] / 100 % 10; + if(eInput.Asterisk[6])MaskVal.Spl.BcdText_6 = 10; else MaskVal.Spl.BcdText_6 = CtlCenter.FiredUserCode.uCode[i] / 10 % 10; + if(eInput.Asterisk[7])MaskVal.Spl.BcdText_7 = 10; else MaskVal.Spl.BcdText_7 = CtlCenter.FiredUserCode.uCode[i] / 1 % 10; + if(aCode.Full == MaskVal.Full){ + ActCnt ++; + if(i>=FireInxPrv)tMatch =1; + if(ActCnt >= eInput.Entry[aEty].ThresholdCnt){ + eInput.Entry[aEty].Active = 1; + eInput.HasInput = 1; + if(tMatch)NewMatchFound =1; + return 1; + } + } + } + } + } + return 0; +} + +void TInterLink::GetFireStateByTypeViaMsg(unsigned char aDType, unsigned int aEty) +{ + unsigned int x, ActCnt, tMatch; + int i; + tMatch =0; + ActCnt = 0; + if(CtlCenter.FiredUserCode.Count){ + for(i=CtlCenter.FiredUserCode.Count-1; i>=0; i--){ + if(CtlCenter.FiredUserCode.uCode[i] == 0) continue; + if(RunState != TRunModeCfg::RunModeAdjust){ + if(CtlCenter.FiredUserCode.eType[i] > TControlCenter::LinkInputTypeAvaEdge)continue; + } + + if(aDType == 0){ + ActCnt ++; + if(i>=FireInxPrv)tMatch =1; + if(ActCnt >= eInput.Entry[aEty].ThresholdCnt){ + eInput.Entry[aEty].Active = 1; + eInput.HasInput = 1; + if(tMatch)NewMatchFound =1; + return; + } + }else{ + if(aDType == CtlCenter.FiredUserCode.dType[i]){ + ActCnt ++; + if(i>=FireInxPrv)tMatch =1; + if(ActCnt >= eInput.Entry[aEty].ThresholdCnt){ + eInput.Entry[aEty].Active = 1; + eInput.HasInput = 1; + if(tMatch)NewMatchFound =1; + return; + } + } + } + } + } +} + +void TInterLink::CanNetMasterSendOutput(TUserCodeStr aCode, unsigned char aDType, unsigned int aDelaySec, unsigned int aDoStop) +{ + unsigned char aSta; + if(aDoStop == 0){ + if( (ForceDoOutput) || (FirstDoOutput) || ( (NewMatchDoOutput) && (NewMatchFound) ) ){ + if(aDelaySec){ + aSta = 3; //Delay Start + }else{ + aSta = 2; //Start + } + }else{ + aSta = 1; //Match + } + ProtoC2C.MasterDoRemoteLnkStartStopViaUserCode(aCode.Full, aDType, aDelaySec, aSta); + }else{ + aSta = 0; //Stop + ProtoC2C.MasterDoRemoteLnkStartStopViaUserCode(aCode.Full, aDType, aDelaySec, aSta); + } +} + +void TInterLink::CanNetMasterSendOutputSimulate(TUserCodeStr aCode, unsigned char aDType, unsigned int aDelaySec, unsigned int aDoStop) +{ + unsigned char aSta; + if(aDoStop == 0){ + if( (ForceDoOutput) || (FirstDoOutput) || ( (NewMatchDoOutput) && (NewMatchFound) ) ){ + if(aDelaySec){ + aSta = 3; //Delay Start + }else{ + aSta = 2; //Start + } + }else{ + aSta = 1; //Match + } + ProtoC2C.MasterDoRemoteLnkStartStopViaUserCodeSimulate(aCode.Full, aDType, aDelaySec, aSta); + }else{ + aSta = 0; //Stop + ProtoC2C.MasterDoRemoteLnkStartStopViaUserCodeSimulate(aCode.Full, aDType, aDelaySec, aSta); + } +} + +int TInterLink::SetOutputStateViaUserCode(TUserCodeStr aCode, unsigned char aDType, unsigned int aEty, unsigned int aDelaySec, unsigned int aDoStop) +{ + unsigned int i, x, HadPrc, Result, HasMatch, tType; + TUserCodeStr DevUCode; + + Result = 0; + HadPrc = 0; + HasMatch = 0; + if( (ForceDoOutput) || (FirstDoOutput) || ( (NewMatchDoOutput) && (NewMatchFound) ) ){ + LinkHasStartTabel[LinkCurrent] =0xAA; + } + if(MainCtl.fData.Split.NetworkMode == 1){ + CanNetMasterSendOutput(aCode,aDType,aDelaySec,aDoStop); + } + if(aDoStop == 0){ + for(i=0; i= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + oBuf.Body[oBuf.WriteIndex].Spl.P0 = i+1; + oBuf.Body[oBuf.WriteIndex].Spl.P1 = x+1; + oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKSTART; + } + }else{ + Port[i].LnkRdyGo[x] = 0xA1; + } + } + } + } + } + } + } + } + for(i=0; i= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKMATCH; + HasMatch = 1; + } + } + }else{ + oBuf.WriteIndex++; + if(oBuf.WriteIndex >= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKSTART; + } + }else{ + DirectCtlBoard[i].LnkRdyGo[x] = 0xA1; + } + if(HasMatch == 0){ + if(DirectCtlBoard[i].LnkRdyGoOld[x] != DirectCtlBoard[i].LnkRdyGo[x]){ + DirectCtlBoard[i].LnkRdyGoOld[x] = DirectCtlBoard[i].LnkRdyGo[x]; + oBuf.WriteIndex++; + if(oBuf.WriteIndex >= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKMATCH; + } + } + } + } + } + } + } + } + }else{ + for(i=0; i= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + oBuf.Body[oBuf.WriteIndex].Spl.P0 = i+1; + oBuf.Body[oBuf.WriteIndex].Spl.P1 = x+1; + oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKSTOP; + }else{ + //Port[i].LnkRdyGo[x] = 0; + } + } + } + } + } + } + } + } + + for(i=0; i= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKSTOP; + }else{ + //DirectCtlBoard[i].LnkRdyGo[x] = 0; + } + //if(HasMatch == 0){ + // if(DirectCtlBoard[i].LnkRdyGoOld[x] != DirectCtlBoard[i].LnkRdyGo[x]){ + // DirectCtlBoard[i].LnkRdyGoOld[x] = DirectCtlBoard[i].LnkRdyGo[x]; + // oBuf.WriteIndex++; + // if(oBuf.WriteIndex >= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + // oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + // oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + // oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKDISMATCH; + // } + //} + //} + } + } + } + } + } + } + return 0; +} + +int TInterLink::SetOutputStateViaUserCodeSimulate(TUserCodeStr aCode, unsigned char aDType, unsigned int aEty, unsigned int aDelaySec, unsigned int aDoStop) +{ + unsigned int i, x, HadPrc, Result, HasMatch, tType, hType; + TUserCodeStr DevUCode; + + Result = 0; + HadPrc = 0; + HasMatch = 0; + if( (ForceDoOutput) || (FirstDoOutput) || ( (NewMatchDoOutput) && (NewMatchFound) ) ){ + LinkHasStartTabel[LinkCurrent] =0xAA; + } + if(MainCtl.fData.Split.NetworkMode == 1){ + CanNetMasterSendOutputSimulate(aCode,aDType,aDelaySec,aDoStop); + } + if(aDoStop == 0){ + for(i=0; i= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + // oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + // oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + // oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKMATCH; + // HasMatch = 1; + //} + } + }else{ + DirectCtlBoard[i].AddStartStopSimulate(1, i+dADDR_DIRECTPAD_START, x+1); + } + }else{ + DirectCtlBoard[i].LnkRdyGo[x] = 0xA1; + } + //if(HasMatch == 0){ + // if(DirectCtlBoard[i].LnkRdyGoOld[x] != DirectCtlBoard[i].LnkRdyGo[x]){ + // DirectCtlBoard[i].LnkRdyGoOld[x] = DirectCtlBoard[i].LnkRdyGo[x]; + // oBuf.WriteIndex++; + // if(oBuf.WriteIndex >= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + // oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + // oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + // oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKMATCH; + // } + //} + } + } + } + } + } + } + }else{ + for(i=0; i= dLinkageOutputBufMaxCOunt)oBuf.WriteIndex = 0; + // oBuf.Body[oBuf.WriteIndex].Spl.P0 = i +dADDR_DIRECTPAD_START; + // oBuf.Body[oBuf.WriteIndex].Spl.P1 = x +1; + // oBuf.Body[oBuf.WriteIndex].Spl.Action = dLNKDISMATCH; + // } + //} + } + } + } + } + } + } + } + return 0; +} + +void TInterLink::LoadOneEntryInput(unsigned int aEty) +{ + unsigned int i,x; + unsigned int aAddr; + unsigned int AsteriskCnt; + unsigned int ParCntHasGot; + + ParCntHasGot = 0; + + EntryChar.EntryInt32[0] = Exp.D32[(aEty * 4) + 4 + 0]; + EntryChar.EntryInt32[1] = Exp.D32[(aEty * 4) + 4 + 1]; + EntryChar.EntryInt32[2] = Exp.D32[(aEty * 4) + 4 + 2]; + EntryChar.EntryInt32[3] = Exp.D32[(aEty * 4) + 4 + 3]; + EntryChar.EntryInt32[4] = 0; + + eInput.IsAllFire = 0; + eInput.nWildcard = 0; + eInput.Entry[aEty].Illegal = 0; + eInput.Entry[aEty].Sym = 0; + eInput.Entry[aEty].BaseNum.Full = 0; + eInput.Entry[aEty].dType = 0; + eInput.Entry[aEty].Active = 0; + for(i=0; i<8; i++){ + eInput.Asterisk[i] = 0; + eInput.Hashtag[i] = 0; + } + x = 0; + AsteriskCnt = 0; + + if( (EntryChar.Str[0] >= '0') && (EntryChar.Str[0] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_0 = EntryChar.Str[0] -'0'; + else if (EntryChar.Str[0] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_0 = 10; eInput.Asterisk[0] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[0] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_0 = 11; eInput.Hashtag[0] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + if( (EntryChar.Str[1] >= '0') && (EntryChar.Str[1] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_1 = EntryChar.Str[1] -'0'; + else if (EntryChar.Str[1] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_1 = 10; eInput.Asterisk[1] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[1] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_1 = 11; eInput.Hashtag[1] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + if( (EntryChar.Str[2] >= '0') && (EntryChar.Str[2] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_2 = EntryChar.Str[2] -'0'; + else if (EntryChar.Str[2] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_2 = 10; eInput.Asterisk[2] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[2] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_2 = 11; eInput.Hashtag[2] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + if( (EntryChar.Str[3] >= '0') && (EntryChar.Str[3] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_3 = EntryChar.Str[3] -'0'; + else if (EntryChar.Str[3] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_3 = 10; eInput.Asterisk[3] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[3] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_3 = 11; eInput.Hashtag[3] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + if( (EntryChar.Str[4] >= '0') && (EntryChar.Str[4] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_4 = EntryChar.Str[4] -'0'; + else if (EntryChar.Str[4] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_4 = 10; eInput.Asterisk[4] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[4] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_4 = 11; eInput.Hashtag[4] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + if( (EntryChar.Str[5] >= '0') && (EntryChar.Str[5] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_5 = EntryChar.Str[5] -'0'; + else if (EntryChar.Str[5] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_5 = 10; eInput.Asterisk[5] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[5] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_5 = 11; eInput.Hashtag[5] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + if( (EntryChar.Str[6] >= '0') && (EntryChar.Str[6] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_6 = EntryChar.Str[6] -'0'; + else if (EntryChar.Str[6] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_6 = 10; eInput.Asterisk[6] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[6] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_6 = 11; eInput.Hashtag[6] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + if( (EntryChar.Str[7] >= '0') && (EntryChar.Str[7] <= '9') ) eInput.Entry[aEty].BaseNum.Spl.BcdText_7 = EntryChar.Str[7] -'0'; + else if (EntryChar.Str[7] == '*'){eInput.Entry[aEty].BaseNum.Spl.BcdText_7 = 10; eInput.Asterisk[7] = 1; eInput.Entry[aEty].Sym |= 1; AsteriskCnt++;} + else if (EntryChar.Str[7] == '#'){eInput.Entry[aEty].BaseNum.Spl.BcdText_7 = 11; eInput.Hashtag[7] = 1; eInput.Entry[aEty].Sym |= 2;} + else{eInput.Entry[aEty].Illegal = 1; return;} + + + if(eInput.Entry[aEty].Illegal == 0){ + if( (EntryChar.Str[8] >= '0') && (EntryChar.Str[8] <= '9') ){ + eInput.Entry[aEty].dType += static_cast(EntryChar.Str[8] - '0') * 100; + }else{ + eInput.Entry[aEty].Illegal = 1; + } + if( (EntryChar.Str[9] >= '0') && (EntryChar.Str[9] <= '9') ){ + eInput.Entry[aEty].dType += static_cast(EntryChar.Str[9] - '0') * 10; + }else{ + eInput.Entry[aEty].Illegal = 1; + } + if( (EntryChar.Str[10] >= '0') && (EntryChar.Str[10] <= '9') ){ + eInput.Entry[aEty].dType += static_cast(EntryChar.Str[10] - '0') * 1; + }else{ + eInput.Entry[aEty].Illegal = 1; + } + if(eInput.Entry[aEty].dType > 255)eInput.Entry[aEty].Illegal = 1; + } + + if(eInput.Entry[aEty].Illegal == 0){ + if( (EntryChar.Str[11] > '0') && (EntryChar.Str[11] <= '9') ){ + eInput.Entry[aEty].ThresholdCnt = EntryChar.Str[11] - '0'; + }else + if(EntryChar.Str[11] == ' '){ + eInput.Entry[aEty].ThresholdCnt = 1; + }else{ + eInput.Entry[aEty].Illegal = 1; + } + } + + if(eInput.Entry[aEty].Illegal == 0){ + if(EntryChar.Str[12] == 'X'){ + eInput.Entry[aEty].Logic = 'X'; + }else + if(EntryChar.Str[12] == '+'){ + eInput.Entry[aEty].Logic = '+'; + }else{ + eInput.Entry[aEty].Illegal = 1; + } + } + + if(eInput.Entry[aEty].Illegal == 0){ + if(ParCntHasGot == 0){ + if(eInput.Entry[aEty].Logic == 'X'){ + if( (EntryChar.Str[13] > '0') && (EntryChar.Str[13] <= '9') ){ + eInput.ParCnt = EntryChar.Str[13] - '0'; + ParCntHasGot = 1; + }else + if(EntryChar.Str[13] == ' '){ + eInput.ParCnt = 1; + ParCntHasGot = 1; + }else{ + eInput.Entry[aEty].Illegal = 1; + } + } + } + } + + if(eInput.Entry[aEty].Illegal == 0){ + if( AsteriskCnt > 7) { + GetFireStateByTypeViaMsg(eInput.Entry[aEty].dType, aEty); + }else{ + if(eInput.Entry[aEty].Sym == 0){ + //Direct + GetFireStateViaMsg(eInput.Entry[aEty].BaseNum , eInput.Entry[aEty].dType, aEty); + }else + if(eInput.Entry[aEty].Sym & 1){ + //Wildcard + GetFireStateViaMsg(eInput.Entry[aEty].BaseNum , eInput.Entry[aEty].dType, aEty); + }else + if(eInput.Entry[aEty].Sym == 2){ + //Foor + } + } + } +} + + +void TInterLink::ActiveEntryOutput(unsigned int aEty) +{ + unsigned int i,x; + unsigned int aAddr; + unsigned int AsteriskCnt; + + EntryChar.EntryInt32[0] = Exp.D32[(aEty * 4) + 4 + 64 + 0]; + EntryChar.EntryInt32[1] = Exp.D32[(aEty * 4) + 4 + 64 + 1]; + EntryChar.EntryInt32[2] = Exp.D32[(aEty * 4) + 4 + 64 + 2]; + EntryChar.EntryInt32[3] = Exp.D32[(aEty * 4) + 4 + 64 + 3]; + EntryChar.EntryInt32[4] = 0; + + eOutput.nWildcard = 0; + eOutput.Entry[aEty].Illegal = 0; + eOutput.Entry[aEty].Sym = 0; + eOutput.Entry[aEty].BaseNum.Full = 0; + eOutput.Entry[aEty].dType = 0; + eOutput.Entry[aEty].Active = 0; + for(i=0; i<8; i++){ + eOutput.Asterisk[i] = 0; + eOutput.Hashtag[i] = 0; + } + x = 0; + AsteriskCnt = 0; + if( (EntryChar.Str[0] >= '0') && (EntryChar.Str[0] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_0 = EntryChar.Str[0] -'0'; + else if (EntryChar.Str[0] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_0 = 10; eOutput.Asterisk[0] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[0] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_0 = 11; eOutput.Hashtag[0] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if( (EntryChar.Str[1] >= '0') && (EntryChar.Str[1] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_1 = EntryChar.Str[1] -'0'; + else if (EntryChar.Str[1] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_1 = 10; eOutput.Asterisk[1] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[1] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_1 = 11; eOutput.Hashtag[1] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if( (EntryChar.Str[2] >= '0') && (EntryChar.Str[2] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_2 = EntryChar.Str[2] -'0'; + else if (EntryChar.Str[2] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_2 = 10; eOutput.Asterisk[2] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[2] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_2 = 11; eOutput.Hashtag[2] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if( (EntryChar.Str[3] >= '0') && (EntryChar.Str[3] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_3 = EntryChar.Str[3] -'0'; + else if (EntryChar.Str[3] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_3 = 10; eOutput.Asterisk[3] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[3] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_3 = 11; eOutput.Hashtag[3] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if( (EntryChar.Str[4] >= '0') && (EntryChar.Str[4] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_4 = EntryChar.Str[4] -'0'; + else if (EntryChar.Str[4] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_4 = 10; eOutput.Asterisk[4] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[4] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_4 = 11; eOutput.Hashtag[4] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if( (EntryChar.Str[5] >= '0') && (EntryChar.Str[5] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_5 = EntryChar.Str[5] -'0'; + else if (EntryChar.Str[5] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_5 = 10; eOutput.Asterisk[5] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[5] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_5 = 11; eOutput.Hashtag[5] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if( (EntryChar.Str[6] >= '0') && (EntryChar.Str[6] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_6 = EntryChar.Str[6] -'0'; + else if (EntryChar.Str[6] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_6 = 10; eOutput.Asterisk[6] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[6] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_6 = 11; eOutput.Hashtag[6] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if( (EntryChar.Str[7] >= '0') && (EntryChar.Str[7] <= '9') ) eOutput.Entry[aEty].BaseNum.Spl.BcdText_7 = EntryChar.Str[7] -'0'; + else if (EntryChar.Str[7] == '*'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_7 = 10; eOutput.Asterisk[7] = 1; eOutput.Entry[aEty].Sym |= 1; AsteriskCnt ++;} + else if (EntryChar.Str[7] == '#'){eOutput.Entry[aEty].BaseNum.Spl.BcdText_7 = 11; eOutput.Hashtag[7] = 1; eOutput.Entry[aEty].Sym |= 2;} + else{ + eOutput.Entry[aEty].Illegal = 1; + return; + } + + if(eOutput.Entry[aEty].Illegal == 0){ + if(EntryChar.Str[8]=='*' and EntryChar.Str[9]=='*' and EntryChar.Str[10]=='*'){ + eOutput.Entry[aEty].dType=0; + }else + if(EntryChar.Str[8]=='*' or EntryChar.Str[9]=='*' or EntryChar.Str[10]=='*'){ + eOutput.Entry[aEty].Illegal = 1; + }else{ + if( (EntryChar.Str[8] >= '0') && (EntryChar.Str[8] <= '9') ){ + eOutput.Entry[aEty].dType += static_cast(EntryChar.Str[8] - '0') * 100; + }else{ + eOutput.Entry[aEty].Illegal = 1; + } + if( (EntryChar.Str[9] >= '0') && (EntryChar.Str[9] <= '9') ){ + eOutput.Entry[aEty].dType += static_cast(EntryChar.Str[9] - '0') * 10; + }else{ + eOutput.Entry[aEty].Illegal = 1; + } + if( (EntryChar.Str[10] >= '0') && (EntryChar.Str[10] <= '9') ){ + eOutput.Entry[aEty].dType += static_cast(EntryChar.Str[10] - '0') * 1; + }else{ + eOutput.Entry[aEty].Illegal = 1; + } + if(eOutput.Entry[aEty].dType==0 or eOutput.Entry[aEty].dType > 255)eOutput.Entry[aEty].Illegal = 1; + } + } + + if(eOutput.Entry[aEty].Illegal == 0){ + eOutput.Entry[aEty].DelaySec = 0; + if( (EntryChar.Str[11] >= '0') && (EntryChar.Str[11] <= '9') ){ + eOutput.Entry[aEty].DelaySec += static_cast(EntryChar.Str[11] - '0'); + } + if( (EntryChar.Str[12] >= '0') && (EntryChar.Str[12] <= '9') ){ + eOutput.Entry[aEty].DelaySec = eOutput.Entry[aEty].DelaySec * 10; + eOutput.Entry[aEty].DelaySec += static_cast(EntryChar.Str[12] - '0'); + } + if( (EntryChar.Str[13] >= '0') && (EntryChar.Str[13] <= '9') ){ + eOutput.Entry[aEty].DelaySec = eOutput.Entry[aEty].DelaySec * 10; + eOutput.Entry[aEty].DelaySec += static_cast(EntryChar.Str[13] - '0'); + } + if(eOutput.Entry[aEty].DelaySec > 600)eOutput.Entry[aEty].Illegal = 1; + } + + if(eOutput.Entry[aEty].Illegal == 0){ + //if( (AsteriskCnt > 7) && (eOutput.Entry[aEty].dType == dgType_VAALRAM) ){ + + //}else{ + if(eOutput.Entry[aEty].Sym == 0){ + //Direct + if(RunState != TRunModeCfg::RunModeAdjust){ + SetOutputStateViaUserCode(eOutput.Entry[aEty].BaseNum, eOutput.Entry[aEty].dType, aEty, eOutput.Entry[aEty].DelaySec, eOutput.DoStop); + }else{ + SetOutputStateViaUserCodeSimulate(eOutput.Entry[aEty].BaseNum, eOutput.Entry[aEty].dType, aEty, eOutput.Entry[aEty].DelaySec, eOutput.DoStop); + } + //if(MainCtl.fData.Split.NetworkMode == 1){ + // ProtoC2C.MasterDoRemoteLnkStartStopViaUserCode(eOutput.Entry[aEty].BaseNum.Full, eOutput.Entry[aEty].dType, eOutput.Entry[aEty].DelaySec, eOutput.DoStop); + //} + }else + if(eOutput.Entry[aEty].Sym & 1){ + //Wildcard + if(RunState != TRunModeCfg::RunModeAdjust){ + SetOutputStateViaUserCode(eOutput.Entry[aEty].BaseNum, eOutput.Entry[aEty].dType, aEty, eOutput.Entry[aEty].DelaySec, eOutput.DoStop); + }else{ + SetOutputStateViaUserCodeSimulate(eOutput.Entry[aEty].BaseNum, eOutput.Entry[aEty].dType, aEty, eOutput.Entry[aEty].DelaySec, eOutput.DoStop); + } + }else + if(eOutput.Entry[aEty].Sym == 2){ + //Foor + } + //} + } +} + +void TInterLink::LoadInputState() +{ + int x; + eInput.HasInput = 0; + for(x=0;x<16;x++)LoadOneEntryInput(x); +} + +void TInterLink::SetOutputState() +{ + int x; + for(x=0; x<16;x++)ActiveEntryOutput(x); +} + +void TInterLink::CheckGoRunLogic() +{ + int i, AndCnt, AndRdyCnt; + if(eInput.HasInput == 0){ + eOutput.Action = 0; + return; + }else{ + AndCnt = 0; + AndRdyCnt = 0; + for(i=0; i<16; i++){ + if( (eInput.Entry[i].Illegal == 0) && (eInput.Entry[i].Logic == 'X') ){ + AndCnt++; + if(eInput.Entry[i].Active){ + AndRdyCnt++; + } + } + } + if( (AndCnt >0) && (AndRdyCnt >= eInput.ParCnt) ){ + eOutput.Action = 1; + return; + } + for(i=0; i<16; i++){ + if(eInput.Entry[i].Active){ + if(eInput.Entry[i].Logic == '+'){ + eOutput.Action = 1; + return; + } + } + + } + } +} + + +int TInterLink::LoadLinkageExp() +{ + int i, Ava; + unsigned int ActualIndex; + volatile unsigned int aAddr; + + if(LinkIndex >= LinkCount)LinkIndex = 0; + ActualIndex = LinkNumList[LinkIndex]; + Ava = 0; + if( (LinkHasStartTabel[ActualIndex] == 0xAA) && (Forcing == 0) ){ + Ava = 0; + }else{ + aAddr = dSdAddrLinkageExp + (ActualIndex * 1024); + Crc32Reset(); + for(i=0; i<255; i++){ + Exp.D32[i] = *(volatile unsigned int *)(aAddr + (i * 4)); + Crc32Feed(Exp.D32[i]); + } + Exp.D32[255]=0; + if(this->Crc[ActualIndex] == Crc32GetResult()){ + LinkCurrent = ActualIndex; + Ava = 1; + }else{ + if(0==RuntimeReloadExpression2Ram(ActualIndex)){ + LinkCurrent = ActualIndex; + Ava = 1; + } + } + } + LinkIndex++; + if(LinkIndex >= LinkCount)LinkIndex = 0; + return Ava; +} + +void TInterLink::LoadExpSettingBytes(unsigned int aInx) +{ + volatile unsigned int aAddr = dSdAddrLinkageExp + (aInx * 1024); + Exp.D32[1] = *(volatile unsigned int *)(aAddr + (1 * 4)); +} + +int TInterLink::LoadExp(unsigned int aInx) +{ + volatile unsigned int aAddr; + unsigned int i; + aAddr = dSdAddrLinkageExp + (aInx * 1024); + Crc32Reset(); + for(i=0; i<255; i++){ + Exp.D32[i] = *(volatile unsigned int *)(aAddr + (i * 4)); + Crc32Feed(Exp.D32[i]); + } + Exp.D32[255]=0; + if(this->Crc[aInx] != Crc32GetResult()){ + if(0 != RuntimeReloadExpression2Ram(aInx)){ + return 0; + } + } + return 1; +} + +int TInterLink::QueueLoadExp() +{ + int i, Ava; + volatile unsigned int aAddr; + Ava =0; + ForceDoOutput =0; + FirstDoOutput =0; + NewMatchDoOutput =0; + NewMatchFound =0; + if(LinkIndex >= LinkCount)LinkIndex = 0; + LinkCurrent = LinkNumList[LinkIndex]; + LinkIndex++; + if(LinkIndex >= LinkCount)LinkIndex = 0; + + FireInxPrv = PrcFireOutputInx[LinkCurrent]; + + if( Forcing ){ + PrcFireOutputInx[LinkCurrent] = CtlCenter.FiredUserCode.Count; + PrcFireInx[LinkCurrent] = PrcFireOutputInx[LinkCurrent]; + ForceDoOutput =1; + Ava = LoadExp(LinkCurrent); + }else{ + if(AllowAuto){ + if(LinkHasStartTabel[LinkCurrent] == 0xAA){ + if( PrcFireOutputInx[LinkCurrent] < (CtlCenter.FiredUserCode.Count) ) { + PrcFireOutputInx[LinkCurrent] = CtlCenter.FiredUserCode.Count; + PrcFireInx[LinkCurrent] = PrcFireOutputInx[LinkCurrent]; + NewMatchDoOutput =1; + Ava = LoadExp(LinkCurrent); + } + }else{ + if( PrcFireOutputInx[LinkCurrent] < (CtlCenter.FiredUserCode.Count) ) { + PrcFireOutputInx[LinkCurrent] = CtlCenter.FiredUserCode.Count; + PrcFireInx[LinkCurrent] = PrcFireOutputInx[LinkCurrent]; + FirstDoOutput =1; + Ava = LoadExp(LinkCurrent); + } + } + }else{ + if( ( PrcFireOutputInx[LinkCurrent] < CtlCenter.FiredUserCode.Count ) or ( PrcFireInx[LinkCurrent] < CtlCenter.FiredUserCode.Count ) ){ + Ava = LoadExp(LinkCurrent); + } + if(Ava){ + if(Exp.Exp[6] == 'F'){ + if(LinkHasStartTabel[LinkCurrent] == 0xAA){ + if( PrcFireOutputInx[LinkCurrent] < CtlCenter.FiredUserCode.Count ) { + PrcFireOutputInx[LinkCurrent] = CtlCenter.FiredUserCode.Count; + PrcFireInx[LinkCurrent] = PrcFireOutputInx[LinkCurrent]; + NewMatchDoOutput =1; + } + }else{ + if( PrcFireOutputInx[LinkCurrent] < (CtlCenter.FiredUserCode.Count) ) { + PrcFireOutputInx[LinkCurrent] = CtlCenter.FiredUserCode.Count; + PrcFireInx[LinkCurrent] = PrcFireOutputInx[LinkCurrent]; + FirstDoOutput =1; + } + } + }else{ + if( PrcFireInx[LinkCurrent] < CtlCenter.FiredUserCode.Count ) { + PrcFireInx[LinkCurrent] = CtlCenter.FiredUserCode.Count; + } + } + } + } + } + + if(Ava ==0 )return 0; + if(Exp.Exp[4] == 'M')return 0; + if(Exp.Exp[5] == 'S')eOutput.DoStop =1; + else eOutput.DoStop = 0; + + return 1; +} + +void TInterLink::GoAction() +{ + LoadInputState(); + eOutput.Action = 0; + CheckGoRunLogic(); + + if(eOutput.Action){ + SetOutputState(); + }else{ + if(AllowAuto == 0){ + if(eOutput.DoStop == 0){ + LinkHasRdyGoTabel[LinkCurrent] =0; + } + } + } +} + +void TInterLink::DoLnk() +{ + if(QueueLoadExp()){ + LoadInputState(); + eOutput.Action = 0; + CheckGoRunLogic(); + if(eOutput.Action){ + SetOutputState(); + }else{ + if(AllowAuto == 0){ + if(eOutput.DoStop == 0){ + LinkHasRdyGoTabel[LinkCurrent] =0; + } + } + } + } + + if( LinkageManualGo ){ + LinkageManualGo = 0; + ForceInx = 0; + Forcing = 1; + } + if(Forcing){ + ForceInx++; + if(ForceInx > LinkCount){ + Forcing = 0; + } + } + + return; + + /*if(Forcing){ + DoTick = 10; + do{ + ForceLoadLinkageExp(); + GoAction(); + ForceInx++; + if(ForceInx >= LinkCount){ + Forcing = 0; + break; + } + DoTick--; + }while(DoTick > 0); + }else{ + if( (AllowManual) && (LinkageManualGo) ){ + LinkageManualGo = 0; + Forcing = 1; + ForceInx = 0; + }else{ + DoTick = 10; + if(ShouldGo){ + do{ + LinkAva = LoadLinkageExp(); + if(LinkAva){ + GoAction(); + } + if(LinkIndex == 0){ + ShouldGo = 0; + break; + } + DoTick--; + }while(DoTick > 0); + } + + if(ShouldGo == 0){ + DoEntryTickDiff = CtlCenter.SysFreeTick1Ms - DoEbtryLastTick; + if(DoEntryTickDiff > 1000){ + DoEbtryLastTick = CtlCenter.SysFreeTick1Ms; + ShouldGo = 1; + } + } + } + }*/ +} + +void TInterLink::RecallCrcFaultMsg() +{ + for(int i=0; i< dLINKAGE_MAX_COUNT; i++){ + if(CrcFlag[i]){ + CtlCenter.ieAddBrdFaultLinkageStorage(i+1); + } + } +} + +void TInterLink::Task10Ms() +{ + if(get_can_tx_complete()){ + if(oBuf.ReadIndex != oBuf.WriteIndex){ + SendOutputBuf(); + } + } +} + + + + + + + + + + + + + + diff --git a/MyCode/src/InterLink.h b/MyCode/src/InterLink.h new file mode 100644 index 0000000..353ceb4 --- /dev/null +++ b/MyCode/src/InterLink.h @@ -0,0 +1,256 @@ +#ifndef INTERLINK_H_ +#define INTERLINK_H_ + +#include "gvalue.h" +#include "my_string.h" +#include "record.h" +#include "ProtoC2C.h" + +#define dLNKNONE 0x00 +#define dLNKMATCH 0x11 +#define dLNKDISMATCH 0x10 +#define dLNKSTART 0x21 +#define dLNKSTOP 0x20 + +#define dSdAddrLinkageExp 0xC040'0000 + +#define dLinkageOutputBufMaxCOunt 2048 + +#define dStart 1 +#define dMSearchTarget 2 +#define dMSearchSource 3 +#define dMSearchPath 4 +#define dSDearchPathStart 5 +#define dSDearchPathEnd 6 +#define dSearchLogic 7 + +#define dToFindStart 99 +#define dFoundStart 100 +#define dFoundLogic 102 + +#define dLevelCount 6 +#define dLevelEntryCount 24 + +typedef struct{ + unsigned int IsMask; + unsigned int HasInput; + unsigned int IsAllFire; + unsigned int Asterisk[8]; + unsigned int Hashtag[8]; + unsigned int nWildcard; + unsigned int ParCnt; + struct{ + unsigned int Sym; //0 Direct; 1 Wildcard; 2 ByFloor + TUserCodeStr BaseNum; + unsigned int Logic; + unsigned int dType; + unsigned int Active; + unsigned int Illegal; + unsigned int ThresholdCnt; + //unsigned char WildcardAva[8]; + }Entry[24]; +}TLinkageRunTimeInput; + +typedef struct{ + unsigned int Action; + unsigned int DoStop; + unsigned int Asterisk[8]; + unsigned int Hashtag[8]; + unsigned int nWildcard; + struct{ + unsigned int Sym; //0 Direct; 1 Wildcard; 2 ByFloor + TUserCodeStr BaseNum; + unsigned int DelaySec; + unsigned int dType; + unsigned int Active; + unsigned int Illegal; + //unsigned char WildcardAva[8]; + }Entry[24]; +}TLinkageRunTimeOutput; + +typedef struct{ + int Count; + int WriteIndex; + int ReadIndex; + union{ + unsigned int D32; + struct{ + unsigned char CtlNum; + unsigned char P0; + unsigned char P1; + unsigned char Action; + }Spl; + }Body[dLinkageOutputBufMaxCOunt]; +}TOutputBuf; + +typedef struct{ + int Count; + int WriteIndex; + int ReadIndex; + union{ + unsigned int D32; + struct{ + unsigned char CtlNum; + unsigned char P0; + unsigned char P1; + unsigned char Action; + }Spl; + }Body[dLinkageOutputBufMaxCOunt]; +}TExtOutputBuf; + + +class TInterLink{ + public: + TLinkageRunTimeInput eInput; + TLinkageRunTimeOutput eOutput; + unsigned int Crc[dLINKAGE_MAX_COUNT]; + unsigned char CrcFlag[dLINKAGE_MAX_COUNT]; + + union{ + unsigned int D32[256]; + char Exp[1024]; + }Exp; + int ShouldGo; + int AllowOld; + int LinkIndex; + int LinkCount; + int LinkCurrent; + unsigned short FireInxPrv; + unsigned short PrcFireInx[dLINKAGE_MAX_COUNT]; + unsigned short PrcFireOutputInx[dLINKAGE_MAX_COUNT]; + unsigned short LinkNumList[dLINKAGE_MAX_COUNT]; + unsigned short CrcCheckInx[dLINKAGE_MAX_COUNT]; + unsigned char LinkHasRdyGoTabel[dLINKAGE_MAX_COUNT]; + unsigned char LinkHasStartTabel[dLINKAGE_MAX_COUNT]; + unsigned char LinkForceGoTabel[dLINKAGE_MAX_COUNT]; + unsigned char LinkMaskTable[dLINKAGE_MAX_COUNT]; + + int ForceDoOutput; + int FirstDoOutput; + int NewMatchDoOutput; + int NewMatchFound; + int ForceInx; + int Forcing; + + int DoEntryTickDiff; + int DoEbtryLastTick;; + int DoEntryPerSecond; + int DoEntryShouldRestart; + + char StrTmp[12]; + + int LinkAva; + int DoTick; + + unsigned char dType; + + union{ + unsigned int D32[2]; + unsigned char D8[8]; + }Data; + unsigned char eData[16]; + union{ + unsigned char D8[256]; + unsigned int D32[64]; + }ReadWriteData; + + TOutputBuf oBuf; + + TRecordCommon aIm; + TC2CBufBody aC2cNetBuf; + + union { + unsigned int EntryInt32[5]; + char Str[20]; + }EntryChar; + private: + + + public: + TInterLink(void){for(int i=0; iD32 =0; +} + +void TKeyPad::sKeyPadLedSetSuperSv(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.take_charge = aSta; +} +void TKeyPad::sKeyPadLedSetFeedBack(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.feedback = aSta; +} +void TKeyPad::sKeyPadLedSetStartDelay(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.start_delay = aSta; +} +void TKeyPad::sKeyPadLedSetStart(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.start = aSta; +} +void TKeyPad::sKeyPadLedSetMute(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.mute = aSta; +} +void TKeyPad::sKeyPadLedSetFault(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.fault = aSta; +} +void TKeyPad::sKeyPadLedSetAlarm(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.alarm = aSta; +} +void TKeyPad::sKeyPadLedSetLinkage(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + +} +void TKeyPad::sKeyPadLedSetSelfCheck(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.self_check = aSta; +} + +void TKeyPad::sKeyPadLedSetNormalCheck(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.normal_check = aSta; +} +void TKeyPad::sKeyPadLedSetAlarmFault(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.alarm_fault = aSta; +} +void TKeyPad::sKeyPadLedSetAlarmStart(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.alarm_start = aSta; +} +void TKeyPad::sKeyPadLedSetMask(TSys_State_Struct *fState, TKeyPadLedState aSta) +{ + fState->state.shield = aSta; +} +void TKeyPad::sKeyPadLedSetBuz(TSys_State_Struct *fState, unsigned char aSta) +{ + fState->state.buzzer = aSta; +} +void TKeyPad::sKeyPadLedSetAutoAllowState(TSys_State_Struct *fState, unsigned char aSta) +{ + fState->state.auto_state = aSta; +} +void TKeyPad::sKeyPadLedSetManualAllowState(TSys_State_Struct *fState, unsigned char aSta) +{ + fState->state.manual_state = aSta; +} +void TKeyPad::sKeyPadLedSetScreenSaveState(TSys_State_Struct *fState, unsigned char aSta) +{ + fState->state.ScreenSave = aSta; +} + +void TKeyPad::CheckKeyPadOffline() +{ + SilenceTick++; + if(SilenceTick > 22){ + SilenceTick = 26; + GPIOE->ODR |=0x04;; + }else{ + GPIOE->ODR &= ~0x04; + } +} + +void TKeyPad::ForceClearSysErrLed() +{ + GPIOE->ODR &= ~0x04; + SilenceTick = 0; +} + + + + + + + + diff --git a/MyCode/src/KeyPad.h b/MyCode/src/KeyPad.h new file mode 100644 index 0000000..74cb289 --- /dev/null +++ b/MyCode/src/KeyPad.h @@ -0,0 +1,138 @@ +#ifndef KEYPAD_H_ +#define KEYPAD_H_ + +#include "gType.h" + +typedef union +{ + unsigned int D32; + volatile unsigned char state_val[4]; + struct + { + volatile unsigned int shield : 2; /* [1-0] */ + volatile unsigned int take_charge : 2; /* [3-2] */ + volatile unsigned int feedback : 2; /* [5-4] */ + volatile unsigned int start_delay : 2; /* [7-6] */ + volatile unsigned int start : 2; /* [9-8] */ + volatile unsigned int mute : 2; /* [11-10] */ + volatile unsigned int fault : 2; /* [13-12] */ + volatile unsigned int alarm : 2; /* [15-14] */ + volatile unsigned int auto_state : 1; /* [16] */ + volatile unsigned int manual_state : 1; /* [17] */ + volatile unsigned int self_check : 2; /* [19-18] */ + volatile unsigned int ScreenSave : 2; /* [21-20] */ + volatile unsigned int normal_check : 2; /* [23-22] */ + volatile unsigned int alarm_fault : 2; /* [25-24] */ + volatile unsigned int alarm_start : 2; /* [27-26] */ + volatile unsigned int buzzer : 4; /* [31-28] */ + }state; +}TSys_State_Struct; + + +typedef enum{ + Off = 0, + Flicker = 1, + FullOn =2 +}TKeyPadLedState; + +class TKeyPad{ + public: + TSys_State_Struct LedState; + unsigned int FbMissCountOld; + unsigned int IsReqPowerSuplyCount; + unsigned int IsSendPowerSuplyCount; + + int SilenceTick; + int IsOffline; + private: + + + public: + TKeyPad(){ + LedState.D32 = 0; + IsReqPowerSuplyCount = 0; + IsSendPowerSuplyCount = 0; + SilenceTick = 0; + IsOffline = 0; + } + void Init(); + void InitKeyPad(); + + void SendResetCmd(); + void SendSelfCheckCmd(); + void SendPowerSuplyCount(); + void KeyPadLedSetSuperSv(TKeyPadLedState aSta); + void KeyPadLedSetFeedBack(TKeyPadLedState aSta); + void KeyPadLedSetStartDelay(TKeyPadLedState aSta); + void KeyPadLedSetStart(TKeyPadLedState aSta); + void KeyPadLedSetMute(TKeyPadLedState aSta); + void KeyPadLedSetFault(TKeyPadLedState aSta); + void KeyPadLedSetAlarm(TKeyPadLedState aSta); + void KeyPadLedSetLinkage(TKeyPadLedState aSta); + void KeyPadLedSetSelfCheck(TKeyPadLedState aSta); + + void KeyPadLedSetNormalCheck(TKeyPadLedState aSta); + void KeyPadLedSetAlarmFault(TKeyPadLedState aSta); + void KeyPadLedSetAlarmStart(TKeyPadLedState aSta); + void KeyPadLedSetMask(TKeyPadLedState aSta); + + void SetLedStateViaInteger(unsigned int); + unsigned int GetLedStateViaInteger(); + + static void sInit(TSys_State_Struct *fState); + static void sInitKeyPad(TSys_State_Struct *fState); + static void sKeyPadLedSetSuperSv(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetFeedBack(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetStartDelay(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetStart(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetMute(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetFault(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetAlarm(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetLinkage(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetNormalCheck(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetAlarmFault(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetAlarmStart(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetSelfCheck(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetMask(TSys_State_Struct *fState, TKeyPadLedState aSta); + static void sKeyPadLedSetBuz(TSys_State_Struct *fState, unsigned char aSta); + + static void sKeyPadLedSetAutoAllowState(TSys_State_Struct *fState, unsigned char aSta); + static void sKeyPadLedSetManualAllowState(TSys_State_Struct *fState, unsigned char aSta); + + static void sKeyPadLedSetScreenSaveState(TSys_State_Struct *fState, unsigned char aSta); + + void sSendState(); + void SendDumpCmd(); + + void CheckKeyPadOffline(); + void ForceClearSysErrLed(); +}; + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/MainCtl.cpp b/MyCode/src/MainCtl.cpp new file mode 100644 index 0000000..36b583e --- /dev/null +++ b/MyCode/src/MainCtl.cpp @@ -0,0 +1,360 @@ +#include "MainCtl.h" + +#define dNetStateCtlUsingByte 16384 +#define dNetStateCtlUsingInt 4096 +#define dNetStateCtlPortUsingByte 256 + +void TThisMainCtl::ClearVisioInf(void) +{ + CountAllDevice = 0; + CountRootDev = 0; + CountPort =0; + CountHandCtl =0; + CountDirectCtl =0; + CountMotherBoard =0; + CountCommBoard =0; + CountEpAll =0; + CountEp.UnDefine =0; + CountEp.Unknown =0; + CountEp.Smoker =0; + CountEp.Tempe =0; + CountEp.SmokeTempe = 0; + CountEp.HandReport =0; + CountEp.Fire_hydrant_Kp = 0; + CountEp.Input =0; + CountEp.Output =0; + CountEp.InOut =0; + CountEp.VaAlram =0; + CountEp.DisplayPad =0; + CountEp.LnkPs =0; + CountHandCtlPad =0; + CountDirectCtlPad =0; +} + +void TThisMainCtl::ClearNormalInf(void) +{ + CountEpNormal.Unknown =0; + CountEpNormal.UnDefine =0; + CountEpNormal.Smoker =0; + CountEpNormal.Tempe =0; + CountEpNormal.SmokeTempe = 0; + CountEpNormal.HandReport =0; + CountEpNormal.Fire_hydrant_Kp = 0; + CountEpNormal.Input =0; + CountEpNormal.Output =0; + CountEpNormal.InOut =0; + CountEpNormal.VaAlram =0; + CountEpNormal.DisplayPad =0; + CountEpNormal.LnkPs =0; +} + +void TThisMainCtl::ClearFaultInf(void) +{ + CountEpFault.Unknown =0; + CountEpFault.UnDefine =0; + CountEpFault.Smoker =0; + CountEpFault.Tempe =0; + CountEpFault.SmokeTempe = 0; + CountEpFault.HandReport =0; + CountEpFault.Fire_hydrant_Kp = 0; + CountEpFault.Input =0; + CountEpFault.Output =0; + CountEpFault.InOut =0; + CountEpFault.VaAlram =0; + CountEpFault.DisplayPad =0; + CountEpFault.LnkPs =0; +} + +void TThisMainCtl::ClearMaskInf(void) +{ + CountEpMask.Unknown =0; + CountEpMask.UnDefine =0; + CountEpMask.Smoker =0; + CountEpMask.Tempe =0; + CountEpMask.SmokeTempe = 0; + CountEpMask.HandReport =0; + CountEpMask.Fire_hydrant_Kp = 0; + CountEpMask.Input =0; + CountEpMask.Output =0; + CountEpMask.InOut =0; + CountEpMask.VaAlram =0; + CountEpMask.DisplayPad =0; + CountEpMask.LnkPs =0; +} + +void TThisMainCtl::LoadVisioInf() +{ + unsigned int sPath0,sPath1,aType0,aType1; + int i, j; + unsigned int aIndex, aCount; + unsigned char aType; + + ClearVisioInf(); + + CountPort = fData.Split.PortCount; + CountHandCtl = fData.Split.HandCtlCount; + CountDirectCtl = fData.Split.DirectCtlCount; + CountMotherBoard = fData.Split.MotherBoardCount; + CountCommBoard = fData.Split.CommModuleCount; + CountEpAll =0; + for(i=0; i3) ){ + Permission = 1; + }else{ + Permission = aPms; + } + fData.Split.MyNum = Addr; + + ClearVisioInf(); + + for(int i=0; i<32; i++){ + Sn[i] = i + '0'; + } + Sn[32] = '\0'; + Sn[33] = '\0'; + }; + void AssignByData(unsigned int *da); + void GetDescp(unsigned char *StrGot); + void SetDescp(unsigned char *StrPut); + void ClearState(); + + void ClearVisioInf(void); + void ClearNormalInf(void); + void ClearFaultInf(void); + void ClearMaskInf(void); + void LoadVisioInf(); + void LoadNormalInf(); + void LoadFaultInf(); + void LoadMaskInf(); + + void LnkRdyGoUpdata(); + + void LoadCirciutInf(); + void RecallCrcFaultMsg(); +}; + + + +#endif + diff --git a/MyCode/src/MqttData.cpp b/MyCode/src/MqttData.cpp new file mode 100644 index 0000000..8f29046 --- /dev/null +++ b/MyCode/src/MqttData.cpp @@ -0,0 +1,922 @@ +#include "my_string.h" +#include "MqttData.h" +#include "MainCtl.h" +#include "gvalue.h" + +#include +#include + +extern "C"{ + #include "HW_Config.h" + #include "uart_wifi_drv.h" + #include "cjson.h" +} + +void TMqttData::Init() +{ + unsigned int i = 0; + + LL_GPIO_SetOutputPin(GPIOC, LL_GPIO_PIN_8); + LL_GPIO_SetOutputPin(GPIOG, LL_GPIO_PIN_3); + + commPrm.moduleOnline = 0; + commPrm.moduleOfflineTick = 0; + + RxFlag = 0; + + commPrm.commState = MODULE_INIT_STATE; + commPrm.commType = Idle_State; + commPrm.wifiConnectState = Disconnect; + commPrm.mqttConnectState = Disconnect; + + TxPrm.commType = Idle_State; + + RxPrm.rxFlag = 0; + RxPrm.rxLen = 0; + RxPrm.rpyFlag = 0; + RxPrm.rpyLen = 0; + RxPrm.rpyTimeout = 0; + + for(i=0;i<128;i++){ + RxPrm.rxData.d32[i] = 0; + RxPrm.rpyData.d32[i] = 0; + TxPrm.data.d32[i] = 0; + } + + pRxPkg = uart_info_8bit[WIFI_UART].rx_buf; + + HAL_Delay(1000); +} + +void TMqttData::ClearTxString() +{ + unsigned int i = 0; + + for(i=0;i<128;i++){ + TxPrm.data.d32[i] = 0; + } +} + +void TMqttData::oBufProcess() +{ + unsigned int len = 0; + + for(len = 0;len < 512; len++){ + if(0 == TxPrm.data.d8[len]){ + break; + } + } + TxPrm.dataLen = len; + set_wifi_tx_data(TxPrm.data.d8, TxPrm.dataLen); +} + +void TMqttData::iBufProcess() +{ + unsigned int aLen; + unsigned int i; + + if(RxFlag){ + RxFlag = 0; + aLen = uart_info_8bit[WIFI_UART].rx_len; + for(i=aLen;i<512;i++){ + pRxPkg[i] = 0; + } + + pEventRxPkg = strstr((char*)pRxPkg, "+EVENT:"); + if(pEventRxPkg != NULL){ + RxPrm.eventStartTick = (unsigned int)pEventRxPkg - (unsigned int)pRxPkg; + pEndRxPkg = strstr(pEventRxPkg, "\r\n"); + RxPrm.eventEndTick = (unsigned int)pEndRxPkg - (unsigned int)pRxPkg; + + if(RxPrm.eventEndTick - RxPrm.eventStartTick <= 7){//event data invalid + ; + }else{ + RxPrm.rxLen = RxPrm.eventEndTick - RxPrm.eventStartTick; + for(i=0;i 10){ + commPrm.moduleOfflineTick = 20; + commPrm.moduleOnline = 0; + } + + //ModuleHeartBeat(); + //ModuleGetVersionPkg(); + //WifiGetMode(); + //WifiGetStaStatus(); + //WifiGetAutoConnect(); + + if(config){ + if(3 == tick)WifiGetStaStatus(); + else if(15 == tick){ + if(Connected == commPrm.wifiConnectState)MqttGetConnectCfg(); + }else + if(55 == tick){ + if((Connected == commPrm.wifiConnectState)&&(Connected == commPrm.mqttConnectState))MqttPublish(); + } + } + + if(tick > 60){ + tick = 0; + if(0 == config){ + if(Connected != commPrm.wifiConnectState){ + WifiGetStaStatus(); + }else + if(Connected != commPrm.mqttConnectState){ + MqttGetConnectCfg(); + }else{ + if(onceFlag){ + onceFlag = 0; + MqttSubscribe(); + }else{ + MqttPublish(); + config = 1; + } + } + } + }else{ + tick++; + } +} + +void TMqttData::CommModuleInitTask() +{ + ; +} + +void TMqttData::CommWifiDisconnectTask() +{ + ; +} + +void TMqttData::CommWifiCfgTask() +{ + ; +} + +void TMqttData::CommWifiConnectTask() +{ + ; +} + +void TMqttData::CommMqttCfgTask() +{ +} + +void TMqttData::CommMqttConnectTask() +{ + ; +} + +void TMqttData::CommTask() +{ + switch(commPrm.commState){ + case MODULE_INIT_STATE: + CommModuleInitTask(); + break; + + case WIFI_DISCONNECT_STATE: + CommWifiDisconnectTask(); + break; + + case WIFI_CONFIG_STATE: + CommWifiCfgTask(); + break; + + case WIFI_CONNECT_STATE: + CommWifiConnectTask(); + break; + + case MQTT_CONFIG_STATE: + CommMqttCfgTask(); + break; + + case MQTT_CONNECT_STATE: + CommMqttConnectTask(); + break; + + default: + break; + } +} + +void TMqttData::OperationTask() +{ + iBufProcess(); + + RxEventHandle(); + + RpyDataHandle(); +} diff --git a/MyCode/src/MqttData.h b/MyCode/src/MqttData.h new file mode 100644 index 0000000..106cb8d --- /dev/null +++ b/MyCode/src/MqttData.h @@ -0,0 +1,194 @@ +#ifndef MQTTDATA_H_ +#define MQTTDATA_H_ + +#define MQTT_SERVER "emqx.novix.fun" +#define MQTT_PORT_NON_SSL 21883 // 非SSL端口 +#define MQTT_PORT_SSL 28883 // SSL端口 + +//xiaoyi/{ctlKey}/ctlUpLoad // 控制器上传主题 +//xiaoyi/{ctlKey}/ctlDownLoad // 控制器下载主题 + +typedef enum{ + Idle_State = 0, + + Module_Heart_Beat = 1, + Module_RST, + Module_Get_Version, + Module_Restore_Default, + + Wifi_Set_Mode, + Wifi_Set_Connect, + Wifi_Set_Disconnect, + Wifi_Set_AutoConnectFlag, + Wifi_Get_Mode, + Wifi_Get_StaInfo, + Wifi_Get_AutoConnectFlag, + + BLE_Set_Mode, + BLE_Set_Name, + BLE_Enter_Transparent, + + MQTT_Get_Connect_Cfg, + MQTT_Set_Connect_Cfg1, + MQTT_Set_Connect_Cfg2, + MQTT_Set_Connect_Cfg3, + MQTT_Set_Connect_Cfg4, + MQTT_Set_Connect_Cfg5, + MQTT_Set_Connect_Cfg6, + MQTT_Set_Connect, + MQTT_Set_Disconnect, + MQTT_Subscribe, + MQTT_Unsubscribe, + MQTT_Publish, + MQTT_Check_Message, +}TWifiCommType; + +typedef enum{ + MODULE_INIT_STATE = 0, + WIFI_DISCONNECT_STATE = 1, + WIFI_CONFIG_STATE, + WIFI_CONNECT_STATE, + MQTT_CONFIG_STATE, + MQTT_CONNECT_STATE, +}TWifiCommState; + +typedef enum{ + Disconnect = 0, + Connected = 1, + Connecting = 2, +}TConnectState; + +typedef union{ + unsigned char d8[512]; + unsigned short d16[256]; + unsigned int d32[128]; +}TCommDta; + +typedef struct{ + unsigned int seq; + TWifiCommType commType; + unsigned short dataLen; + TCommDta data; +}TTxBodyFormat; + +typedef struct{ + unsigned int seq; + unsigned int rpyTimeout; + unsigned int eventStartTick; + unsigned int eventEndTick; + unsigned short rpyFlag; + unsigned short rxFlag; + unsigned short rpyLen; + unsigned short rxLen; + TCommDta rpyData; + TCommDta rxData; +}TRxBodyFormat; + +typedef struct{ + TWifiCommState commState; + TWifiCommType commType; + + TConnectState wifiConnectState; + TConnectState mqttConnectState; + + unsigned int moduleOnline; + unsigned int moduleOfflineTick; +}TWifiCommPrm; + +class TMqttData{ + public: + unsigned int RxFlag; + + TTxBodyFormat TxPrm; + TRxBodyFormat RxPrm; + + unsigned char * pRxPkg; + char * pEventRxPkg; + char * pEndRxPkg; + + TWifiCommPrm commPrm; + + public: + TMqttData(){}; + + void Init(); + void ClearTxString(); + + void iBufProcess(); + void oBufProcess(); + + void RxEventHandle(); + void RpyDataHandle(); + + //module + void AssembleModuleHeartBeatPkg(); + void AssembleModuleRstPkg(); + void AssembleModuleGetVersionPkg(); + void AssembleModuleRestoreDefaultPkg(); + + //wifi + void AssembleWifiSetModePkg(); + void AssembleWifiSetConnectPkg(); + void AssembleWifiSetDisconnectPkg(); + void AssembleWifiSetAutoConnectPkg(); + void AssembleWifiGetModePkg(); + void AssembleWifiGetStaInfoPkg(); + void AssembleWifiGetAutoConnectPkg(); + + //MQTT + void AssembleMqttGetConnectCfgPkg(); + void AssembleMqttSetConnectCfg1Pkg(); + void AssembleMqttSetConnectCfg2Pkg(); + void AssembleMqttSetConnectCfg3Pkg(); + void AssembleMqttSetConnectCfg4Pkg(); + void AssembleMqttSetConnectCfg5Pkg(); + void AssembleMqttSetConnectCfg6Pkg(); + void AssembleMqttSetConnectPkg(); + void AssembleMqttSetDisconnectPkg(); + void AssembleMqttSubscribePkg(); + void AssembleMqttUnsubscribePkg(); + void AssembleMqttPublishPkg(); + + void ModuleHeartBeat(); + void ModuleRST(); + void ModuleRestore(); + void ModuleGetVersionPkg(); + + void WifiSetMode(); + void WifiConnentAP(); + void WifiDisconnent(); + void WifiSetAutoConnect(); + void WifiGetMode(); + void WifiGetStaStatus(); + void WifiGetAutoConnect(); + + void MqttGetConnectCfg(); + void MqttSetConnectCfg1(); + void MqttSetConnectCfg2(); + void MqttSetConnectCfg3(); + void MqttSetConnectCfg4(); + void MqttSetConnectCfg5(); + void MqttSetConnectCfg6(); + void MqttSetConnect(); + void MqttDisconnect(); + void MqttSubscribe(); + void MqttUnsubscribe(); + void MqttPublish(); + + void WB2_MQTT_Publish_JSON(const char *topic, const char *json_str); + char* Set_cJSON_PrintUnformatted(); + + void CommModuleInitTask(); + void CommWifiDisconnectTask(); + void CommWifiCfgTask(); + void CommWifiConnectTask(); + void CommMqttCfgTask(); + void CommMqttConnectTask(); + void CommTask(); + + void Task10Ms(); + void Task1000Ms(); + void OperationTask(); +}; + +#endif diff --git a/MyCode/src/PinyinT9.cpp b/MyCode/src/PinyinT9.cpp new file mode 100644 index 0000000..5786dd8 --- /dev/null +++ b/MyCode/src/PinyinT9.cpp @@ -0,0 +1,975 @@ +#include "PinyinT9.h" +#include "gType.h" +////////////////////////////////////////////////////////////////////////////////// +//本程序只供学习使用，未经作者许可，不得用于其它任何用途 +//ALIENTEK STM32开发板 +//拼音输入法 代码 +//正点原子@ALIENTEK +//技术论坛:www.openedv.com +//创建日期:2016/1/12 +//版本：V1.0 +//版权所有，盗版必究。 +//Copyright(C) 广州市星翼电子科技有限公司 2009-2019 +//All rights reserved +//******************************************************************************* +//修改信息 +//无 +////////////////////////////////////////////////////////////////////////////////// + +typedef struct +{ + char *py_input;//输入的字符串 + char *py; //对应的拼音 + char *pymb; //码表 +}Tpy_index; + +//汉字排列表 +const c8 PY_mb_space []={""}; +const c8 PY_mb_a []={"啊阿腌吖锕厑嗄錒呵腌"}; +const c8 PY_mb_ai []={"爱埃挨哎唉哀皑癌蔼矮艾碍隘捱嗳嗌嫒瑷暧砹锿霭"}; +const c8 PY_mb_an []={"安俺按暗岸案鞍氨谙胺埯揞犴庵桉铵鹌黯"}; +const c8 PY_mb_ang []={"昂盎肮骯"}; +const c8 PY_mb_ao []={"凹敖熬翱袄傲奥懊澳坳拗嗷螯鏊鳌鏖岙廒遨媪骜獒聱"}; +const c8 PY_mb_ba []={"八巴爸拔芭捌扒叭吧笆疤跋靶把耙坝霸罢茇菝岜灞钯粑鲅魃"}; +const c8 PY_mb_bai []={"白柏百摆佰败拜稗伯捭掰"}; +const c8 PY_mb_ban []={"半办斑班搬扳般颁板版扮拌伴瓣绊阪坂贲钣瘢癍舨"}; +const c8 PY_mb_bang []={"邦帮梆榜膀绑棒磅蚌镑傍谤蒡浜"}; +const c8 PY_mb_bao []={"包宝保抱报暴苞胞褒剥薄雹堡饱豹鲍爆刨炮勹葆孢煲鸨褓趵龅"}; +const c8 PY_mb_bei []={"背贝北倍杯碑悲卑辈钡狈备惫焙被臂孛陂邶埤萆蓓呗悖碚鹎褙鐾鞴"};; +const c8 PY_mb_ben []={"本笨奔苯畚坌贲锛"}; +const c8 PY_mb_beng []={"蚌崩绷甭泵蹦迸堋嘣甏"}; +const c8 PY_mb_bi []={"逼鼻比鄙笔彼碧蓖蔽毕毙毖币庇痹闭匕敝弊必辟壁臂避陛秘泌俾埤芘荜荸萆薜吡哔狴庳愎滗濞弼妣婢嬖璧贲畀铋秕裨筚箅篦舭襞跸髀"}; +const c8 PY_mb_bian []={"边编贬便变卞鞭扁辨辩辫遍匾弁苄忭汴缏煸砭碥窆褊蝙笾鳊"}; +const c8 PY_mb_biao []={"表标彪膘婊骠杓飑飙飚镖镳瘭裱鳔髟"}; +const c8 PY_mb_bie []={"别鳖憋瘪蹩"}; +const c8 PY_mb_bin []={"彬斌濒滨宾摈傧豳缤玢槟殡膑镔髌鬓"}; +const c8 PY_mb_bing []={"兵冰柄丙秉饼炳病并屏禀冫邴摒槟"}; +const c8 PY_mb_bo []={"柏百剥薄博玻菠卜播拨钵波勃搏铂箔伯帛舶脖膊渤泊驳孛亳蕃啵饽檗擘礴钹鹁簸趵跛踣"}; +const c8 PY_mb_bu []={"不布步堡捕卜哺补埠簿部怖埔卟逋瓿晡钚钸醭"}; +const c8 PY_mb_ca []={"擦嚓礤"}; +const c8 PY_mb_cai []={"才财睬猜裁材踩采彩菜蔡"}; +const c8 PY_mb_can []={"餐参蚕残惭惨灿孱骖璨粲黪"}; +const c8 PY_mb_cang []={"苍舱仓沧藏伧"}; +const c8 PY_mb_cao []={"草操糙槽曹艹嘈漕螬艚"}; +const c8 PY_mb_ce []={"侧册测厕策恻"}; +const c8 PY_mb_cen []={"参岑涔"}; +const c8 PY_mb_ceng []={"层蹭曾噌"}; +const c8 PY_mb_cha []={"插叉茬茶查碴搽察岔差诧刹喳衩嚓猹馇汊姹杈楂槎檫锸镲"}; +const c8 PY_mb_chai []={"差拆柴豺侪钗瘥虿龇"}; +const c8 PY_mb_chan []={"产阐颤搀掺蝉馋谗缠铲孱单冁谄蒇廛忏潺澶羼婵觇禅镡蟾躔"}; +const c8 PY_mb_chang []={"长厂昌猖场尝常偿肠敞畅唱倡伥鬯苌菖徜怅惝阊娼嫦昶氅鲳"}; +const c8 PY_mb_chao []={"超抄钞朝嘲潮巢吵炒绰剿怊晁耖"}; +const c8 PY_mb_che []={"车扯撤掣彻澈坼屮砗"}; +const c8 PY_mb_chen []={"郴臣辰尘晨忱沉陈趁衬称谌谶抻嗔宸琛榇碜龀"}; +const c8 PY_mb_cheng []={"撑称城橙成呈乘程惩澄诚承逞骋秤盛丞埕噌徵枨柽塍瞠铖铛裎蛏酲"}; +const c8 PY_mb_chi []={"吃痴持匙池迟弛驰耻齿侈尺赤翅斥炽笞叱哧傺坻墀茌啻嗤彳饬媸敕眵鸱瘛褫蚩螭篪豉踟魑"}; +const c8 PY_mb_chong []={"充冲虫崇宠种重茺忡憧铳舂艟雠"}; +const c8 PY_mb_chou []={"抽酬丑畴踌稠愁筹仇绸瞅臭俦帱惆瘳雠"}; +const c8 PY_mb_chu []={"出初橱厨躇锄雏滁除楚础储矗搐触处畜亍刍怵憷绌杵楮樗褚蜍蹰黜"}; +const c8 PY_mb_chuai []={"揣搋嘬膪踹"}; +const c8 PY_mb_chuan []={"川穿椽传船喘串舛遄巛氚钏舡"}; +const c8 PY_mb_chuang[]={"疮窗幢床闯创怆疒"}; +const c8 PY_mb_chui []={"吹炊捶锤垂陲棰槌"}; +const c8 PY_mb_chun []={"春椿醇唇淳纯蠢莼鹑蝽"}; +const c8 PY_mb_chuo []={"戳绰啜辶辍踔龊"}; +const c8 PY_mb_ci []={"此刺赐次伺差疵茨磁雌辞慈瓷词兹茈呲祠鹚粢糍"}; +const c8 PY_mb_cong []={"从丛聪葱囱匆苁淙骢琮璁枞"}; +const c8 PY_mb_cou []={"凑楱辏腠"}; +const c8 PY_mb_cu []={"粗醋簇促蔟徂猝殂酢蹙蹴"}; +const c8 PY_mb_cuan []={"蹿篡窜攒汆撺爨镩"}; +const c8 PY_mb_cui []={"摧崔催脆瘁粹淬翠萃啐悴璀榱毳隹"}; +const c8 PY_mb_cun []={"村存寸忖皴"}; +const c8 PY_mb_cuo []={"磋撮搓措挫错厝嵯脞锉矬痤瘥鹾蹉躜"}; +const c8 PY_mb_da []={"大搭达答瘩打耷哒嗒怛妲沓疸褡笪靼鞑"}; +const c8 PY_mb_dai []={"大呆歹傣戴带殆代贷袋待逮怠黛埭甙呔岱迨骀绐玳"}; +const c8 PY_mb_dan []={"耽担丹单郸掸胆旦氮但惮淡诞弹蛋赡石儋萏啖澹殚赕眈疸瘅聃箪"}; +const c8 PY_mb_dang []={"当挡党荡档谠凼菪宕砀铛裆"}; +const c8 PY_mb_dao []={"刀捣蹈倒岛祷导到稻悼道盗刂叨帱忉氘焘纛"}; +const c8 PY_mb_de []={"德得的地锝"}; +const c8 PY_mb_dei []={"得"}; +const c8 PY_mb_deng []={"澄蹬灯登等瞪凳邓噔嶝戥磴镫簦"}; +const c8 PY_mb_di []={"的抵底地蒂第帝弟递堤低滴迪敌笛狄涤翟嫡缔提氐籴诋谛邸坻荻嘀娣柢棣觌砥碲睇镝羝骶"}; +const c8 PY_mb_dia []={"嗲"}; +const c8 PY_mb_dian []={"电店惦点典靛奠淀殿颠掂滇碘垫佃甸阽坫巅玷钿癜癫簟踮"}; +const c8 PY_mb_diao []={"吊刁掉钓调碉叼雕凋铞铫貂鲷"}; +const c8 PY_mb_die []={"跌爹碟蝶迭谍叠垤堞揲喋牒瓞耋蹀鲽"}; +const c8 PY_mb_ding []={"丁盯叮钉顶鼎锭定订仃啶玎腚碇町铤疔耵酊"}; +const c8 PY_mb_diu []={"丢铥"}; +const c8 PY_mb_dong []={"东冬董懂动栋侗恫冻洞咚岽峒氡胨胴硐鸫"}; +const c8 PY_mb_dou []={"豆逗痘都兜抖斗陡蔸窦蚪篼"}; +const c8 PY_mb_du []={"肚度渡都督毒犊独读堵睹赌杜镀妒芏嘟渎椟牍蠹笃髑黩"}; +const c8 PY_mb_duan []={"端短锻段断缎椴煅簖"}; +const c8 PY_mb_dui []={"堆兑队对怼憝碓"}; +const c8 PY_mb_dun []={"盾墩吨蹲敦顿囤钝遁沌炖砘礅盹镦趸"}; +const c8 PY_mb_duo []={"多朵度掇哆夺垛躲跺舵剁惰堕驮咄哚沲缍铎裰踱"}; +const c8 PY_mb_e []={"阿蛾峨鹅俄额讹娥恶厄扼遏鄂饿哦噩谔垩苊莪萼呃愕屙婀轭腭锇锷鹗颚鳄"}; +const c8 PY_mb_ei []={"诶"}; +const c8 PY_mb_en []={"恩蒽摁"}; +const c8 PY_mb_er []={"二而儿耳尔饵洱贰迩珥铒鸸鲕"}; +const c8 PY_mb_fa []={"发罚筏伐乏阀法珐垡砝"}; +const c8 PY_mb_fan []={"凡烦反返范贩犯饭泛藩帆番翻樊矾钒繁蕃蘩幡梵燔畈蹯"}; +const c8 PY_mb_fang []={"坊芳方肪房防妨仿访纺放匚邡枋钫舫鲂"}; +const c8 PY_mb_fei []={"菲非啡飞肥匪诽吠肺废沸费芾狒斐悱妃绯淝榧贲腓扉砩镄痱蜚篚翡霏鲱"}; +const c8 PY_mb_fen []={"分芬奋份忿愤粪酚吩氛纷坟焚汾粉偾瀵玢棼贲鲼鼢"}; +const c8 PY_mb_feng []={"丰封枫蜂峰锋风凤疯烽逢冯缝讽奉俸酆葑唪沣砜"}; +const c8 PY_mb_fo []={"佛"}; +const c8 PY_mb_fou []={"否缶"}; +const c8 PY_mb_fu []={"复佛傅付阜父夫敷肤孵妇扶拂辐幅氟符伏俘服浮涪福袱弗甫抚辅俯釜斧脯腑府腐赴副覆赋腹负富讣附缚咐匐凫阝郛芙芾苻茯莩菔拊呋幞怫滏艴孚驸绂绋桴赙祓砩黻黼罘稃馥蚨蜉蝠蝮麸趺跗鲋鳆"}; +const c8 PY_mb_ga []={"噶嘎夹咖伽尬尕尜旮钆"}; +const c8 PY_mb_gai []={"该改概钙盖溉芥丐陔垓戤赅胲"}; +const c8 PY_mb_gan []={"干甘杆柑竿肝赶感秆敢赣坩苷尴擀泔淦澉绀橄旰矸疳酐"}; +const c8 PY_mb_gang []={"冈刚钢缸肛纲岗港杠扛戆罡筻"}; +const c8 PY_mb_gao []={"告皋高膏篙羔糕搞镐稿睾诰郜藁缟槔槁杲锆"}; +const c8 PY_mb_ge []={"个各盖哥骼膈歌搁戈鸽胳疙割革葛格蛤阁隔铬合咯鬲仡哿圪塥嗝纥搿铪镉袼虼舸"}; +const c8 PY_mb_gei []={"给"}; +const c8 PY_mb_gen []={"根跟亘茛哏艮"}; +const c8 PY_mb_geng []={"耕更庚羹埂耿梗颈哽赓绠鲠"}; +const c8 PY_mb_gong []={"工共攻功恭公宫弓龚供躬巩汞拱贡蚣廾珙肱觥"}; +const c8 PY_mb_gou []={"钩勾沟苟够垢构购佝诟狗篝岣遘媾缑枸觏彀笱鞲"}; +const c8 PY_mb_gu []={"姑估沽孤菇咕辜箍鼓古蛊骨谷股故顾固雇贾嘏诂菰崮汩梏轱牯牿臌毂瞽罟钴锢鸪鹄痼蛄酤觚鲴鹘"}; +const c8 PY_mb_gua []={"刮瓜剐寡挂褂卦诖呱栝胍鸹"}; +const c8 PY_mb_guai []={"乖拐怪掴"}; +const c8 PY_mb_guan []={"关官冠观管馆罐惯灌贯纶倌莞棺掼涫盥鹳鳏"}; +const c8 PY_mb_guang []={"光广逛咣犷桄胱"}; +const c8 PY_mb_gui []={"瑰规圭硅归龟闺轨鬼诡桂柜跪贵刽癸炔匦刿庋宄妫桧炅晷皈簋鲑鳜"}; +const c8 PY_mb_gun []={"辊滚棍衮绲磙鲧"}; +const c8 PY_mb_guo []={"锅郭国果裹过涡馘埚掴呙帼崞猓椁虢锞聒蜾蝈"}; +const c8 PY_mb_ha []={"哈蛤铪"}; +const c8 PY_mb_hai []={"还咳孩海害氦亥骇骸嗨胲醢"}; +const c8 PY_mb_han []={"汗汉喊寒含涵函罕酣旱憾悍焊憨邯韩翰撼鼾捍邗菡撖瀚晗焓顸颔蚶"}; +const c8 PY_mb_hang []={"行夯杭航吭巷沆绗颃"}; +const c8 PY_mb_hao []={"郝好耗号昊皓毫浩灏镐壕嚎豪貉蒿薅嗥嚆濠颢蚝"}; +const c8 PY_mb_he []={"呵喝荷菏核禾和何合河盒貉阂涸赫贺褐鹤吓诃劾壑嗬阖纥曷盍颌蚵翮"}; +const c8 PY_mb_hei []={"黑嘿"}; +const c8 PY_mb_hen []={"痕很狠恨"}; +const c8 PY_mb_heng []={"哼亨横衡恒蘅珩桁"}; +const c8 PY_mb_hong []={"红轰哄烘虹鸿洪宏弘黉訇讧荭蕻薨闳泓"}; +const c8 PY_mb_hou []={"后喉侯猴吼厚候堠後逅瘊篌糇鲎骺"}; +const c8 PY_mb_hu []={"护互沪户核呼乎忽瑚壶葫胡蝴虎狐糊湖弧唬冱唿囫岵猢怙惚浒滹琥槲轷觳烀煳戽扈祜瓠鹄鹕鹱虍笏醐斛鹘"}; +const c8 PY_mb_hua []={"花华猾滑哗画划化话骅桦砉铧"}; +const c8 PY_mb_huai []={"坏槐徊怀淮踝"}; +const c8 PY_mb_huan []={"欢环桓还缓换患唤痪焕涣宦幻鬟浣豢郇奂垸萑擐圜獾洹漶寰逭缳锾鲩"}; +const c8 PY_mb_huang []={"晃荒慌黄磺蝗簧皇凰惶煌幌恍谎隍徨湟潢遑璜肓癀蟥篁鳇"}; +const c8 PY_mb_hui []={"会回毁悔灰挥辉徽恢蛔慧卉惠晦贿秽烩汇讳诲绘彗溃诙茴荟蕙咴哕喙隳洄浍缋桧晖恚虺蟪麾"}; +const c8 PY_mb_hun []={"荤昏婚魂浑混诨馄阍溷珲"}; +const c8 PY_mb_huo []={"和豁活伙火获或惑霍货祸劐藿攉嚯夥钬锪镬耠蠖"}; +const c8 PY_mb_ji []={"计记给技击基几脊己圾籍集及急疾汲即嫉级挤蓟既忌际冀季伎祭剂机畸稽积肌饥迹激讥鸡姬绩缉吉极棘箕辑悸济寄寂妓继纪藉奇系丌亟乩剞佶偈墼芨芰荠萁蒺蕺掎叽咭哜唧岌嵴洎彐屐骥畿玑楫殛戟戢赍觊犄齑矶羁嵇稷瘠虮笈笄暨跻跽霁鲚鲫髻麂"}; +const c8 PY_mb_jia []={"家加嘉夹佳荚颊贾甲钾假稼价架驾嫁枷茄嘏伽郏葭岬浃迦珈戛胛恝铗铪镓痂瘕袷蛱笳袈跏"}; +const c8 PY_mb_jian []={"建见件简健减歼荐监捡俭剪坚尖间煎兼肩艰奸缄茧检柬碱硷拣笺槛鉴践贱键箭舰剑饯渐溅涧僭谏谫谮菅蒹搛囝湔蹇謇缣枧楗戋戬牮犍毽腱睑锏鹣裥笕翦趼踺鲣鞯"}; +const c8 PY_mb_jiang []={"讲虹僵姜将浆江疆蒋桨奖匠酱降强茳洚绛缰犟礓耩糨豇"}; +const c8 PY_mb_jiao []={"叫较觉角校蕉椒礁焦胶交郊浇骄娇嚼搅铰矫侥脚狡饺缴绞剿教酵轿窖佼僬艽茭挢噍峤徼姣敫皎鹪蛟醮跤鲛"}; +const c8 PY_mb_jie []={"洁结解姐戒揭杰接皆界借介捷睫秸街阶截劫节桔竭藉芥疥诫届偈讦诘卩拮喈嗟婕孑桀碣锴疖颉蚧羯鲒骱"}; +const c8 PY_mb_jin []={"巾尽筋斤金今津紧锦仅谨进靳晋禁近烬浸劲襟卺荩堇噤馑廑妗缙瑾槿赆觐钅衿矜"}; +const c8 PY_mb_jing []={"京惊精经井睛晶景净颈静境敬警镜径竟竞劲荆兢茎鲸粳痉靖刭儆阱陉菁獍憬泾迳弪婧肼胫腈旌靓"}; +const c8 PY_mb_jiong []={"炯窘冂迥扃"}; +const c8 PY_mb_jiu []={"九就救揪究纠玖韭久灸酒旧臼舅咎疚厩僦啾阄柩桕鸠鹫赳鬏"}; +const c8 PY_mb_ju []={"巨具距俱句惧车柜剧居驹菊局咀矩举沮聚拒据踞锯炬鞠拘狙疽倨讵苣苴莒掬遽屦琚枸椐榘榉橘犋飓钜锔窭裾趄醵踽龃雎瞿鞫"}; +const c8 PY_mb_juan []={"眷卷捐鹃娟倦绢圈鄄狷涓桊蠲锩镌隽"}; +const c8 PY_mb_jue []={"决诀绝觉角掘倔嚼脚撅攫抉爵厥劂谲矍堀蕨噘崛獗孓珏桷橛爝镢蹶觖"}; +const c8 PY_mb_jun []={"军君均菌钧峻俊竣浚郡骏龟捃皲筠麇"}; +const c8 PY_mb_ka []={"卡喀咖咯佧咔胩"}; +const c8 PY_mb_kai []={"开揩楷凯慨剀垲蒈忾恺铠锎锴"}; +const c8 PY_mb_kan []={"看刊堪勘坎砍侃龛瞰凵莰阚槛戡"}; +const c8 PY_mb_kang []={"康慷糠扛抗亢炕伉闶钪"}; +const c8 PY_mb_kao []={"考靠拷烤栲犒铐尻"}; +const c8 PY_mb_ke []={"可渴克科刻客课嗑坷苛柯棵磕颗壳咳恪蝌岢溘稞骒缂珂轲氪瞌钶铪呵锞疴窠颏蚵髁"}; +const c8 PY_mb_ken []={"肯啃垦恳裉"}; +const c8 PY_mb_keng []={"坑吭铿胫铒"}; +const c8 PY_mb_kong []={"空恐孔控倥崆箜"}; +const c8 PY_mb_kou []={"抠口扣寇芤蔻叩眍筘"}; +const c8 PY_mb_ku []={"枯哭窟苦酷库裤绔骷刳堀喾"}; +const c8 PY_mb_kua []={"夸垮挎跨胯侉锞"}; +const c8 PY_mb_kuai []={"会块筷侩快蒯郐哙狯脍"}; +const c8 PY_mb_kuan []={"宽款髋"}; +const c8 PY_mb_kuang []={"况匡筐狂框矿眶旷诓诳邝圹夼哐纩贶"}; +const c8 PY_mb_kui []={"亏盔岿窥葵奎魁傀馈愧溃馗匮逵睽跬夔隗蒉揆喹喟悝愦暌聩蝰篑"}; +const c8 PY_mb_kun []={"坤昆捆困悃琨锟醌鲲阃髡"}; +const c8 PY_mb_kuo []={"括扩廓阔蛞"}; +const c8 PY_mb_la []={"垃拉喇蜡腊辣啦落剌邋旯砬瘌"}; +const c8 PY_mb_lai []={"莱来赖崃徕涞濑赉睐癞籁铼"}; +const c8 PY_mb_lan []={"蓝婪栏拦篮阑兰澜谰揽览懒缆烂滥岚漤榄斓镧褴罱"}; +const c8 PY_mb_lang []={"郎朗浪琅榔狼廊啷阆螂锒蒗稂莨"}; +const c8 PY_mb_lao []={"捞劳牢老佬姥酪烙涝落络唠崂醪栳铑铹痨耢"}; +const c8 PY_mb_le []={"勒乐了仂叻泐鳓"}; +const c8 PY_mb_lei []={"累勒雷镭蕾磊儡垒擂肋类泪羸诔嘞嫘缧檑耒酹"}; +const c8 PY_mb_leng []={"棱楞冷塄愣"}; +const c8 PY_mb_li []={"利力历厉立粒礼沥吏理李里厘励丽梨犁隶黎篱离漓鲤栗砾莉荔狸傈例俐痢璃哩鬲俪俚郦坜苈莅蓠藜呖唳喱猁溧澧逦娌嫠骊缡枥栎轹戾砺砬詈罹锂鹂疠疬蛎蜊蠡笠篥粝醴跞雳鲡鳢黧"}; +const c8 PY_mb_lia []={"俩"}; +const c8 PY_mb_lian []={"联莲连廉怜涟帘敛脸链恋炼练潋镰濂琏楝奁殓蔹臁裢裣蠊鲢"}; +const c8 PY_mb_liang []={"两亮俩粮凉梁粱良辆量晾谅墚莨椋踉魉"}; +const c8 PY_mb_liao []={"了撩料聊僚疗燎寥辽潦撂镣廖蓼尥嘹獠寮缭钌鹩"}; +const c8 PY_mb_lie []={"列裂烈劣洌猎冽埒捩咧趔躐鬣"}; +const c8 PY_mb_lin []={"临邻赁拎琳林磷霖鳞淋凛吝蔺啉嶙廪懔遴檩辚膦瞵粼躏麟"}; +const c8 PY_mb_ling []={"令灵另棱玲菱零龄铃伶羚凌陵岭聆领酃苓呤囹泠绫柃棂瓴蛉翎鲮"}; +const c8 PY_mb_liu []={"刘六溜琉榴硫馏留瘤流柳碌陆浏遛骝绺旒熘锍镏鹨鎏"}; +const c8 PY_mb_lo []={"咯"}; +const c8 PY_mb_long []={"龙弄聋咙笼窿隆垄拢陇垅茏泷珑栊胧砻癃"}; +const c8 PY_mb_lou []={"楼娄搂篓漏陋露偻蒌喽嵝镂瘘耧蝼髅"}; +const c8 PY_mb_lu []={"六芦卢颅庐炉掳卤虏鲁麓碌露路赂鹿潞禄录陆戮绿垆撸噜泸渌漉逯璐栌橹轳辂辘贲氇胪镥鸬鹭簏舻鲈"}; +const c8 PY_mb_lv []={"滤率绿吕铝侣旅履屡缕虑氯律驴褛偻捋闾榈膂稆"}; +const c8 PY_mb_luan []={"乱孪峦挛滦卵"}; +const c8 PY_mb_lue []={"掠略锊"}; +const c8 PY_mb_lun []={"仑抡轮伦沦纶论囵"}; +const c8 PY_mb_luo []={"落罗铬咯烙萝螺逻锣箩骡裸洛骆络倮蠃荦捋摞猡泺漯珞椤脶硌镙瘰雒"}; +const c8 PY_mb_m []={"呒"}; +const c8 PY_mb_ma []={"妈麻玛码蚂马骂嘛吗摩抹唛犸嬷杩蟆"}; +const c8 PY_mb_mai []={"埋瞒馒蛮满蔓曼慢漫谩墁幔缦熳镘颟螨鳗鞔"}; +const c8 PY_mb_man []={"蛮馒瞒满曼谩慢漫蔓"}; +const c8 PY_mb_mang []={"芒茫盲氓忙莽邙漭硭蟒"}; +const c8 PY_mb_mao []={"猫茅锚毛矛髦卯茂冒帽貌贸袤铆茆峁泖瑁昴牦耄旄懋瞀蝥蟊"}; +const c8 PY_mb_me []={"么"}; +const c8 PY_mb_mei []={"每妹美玫枚昧寐袂魅梅酶霉煤没眉媒镁媚莓嵋猸浼湄楣镅鹛"}; +const c8 PY_mb_men []={"门闷们扪焖懑钔"}; +const c8 PY_mb_meng []={"萌梦蒙檬盟锰猛孟勐甍瞢懵朦礞虻蜢蠓艋艨"}; +const c8 PY_mb_mi []={"眯醚靡糜迷谜弥米秘觅泌蜜密麋谧幂芈冖蘼咪嘧猕汨宓弭纟脒祢敉糸縻"}; +const c8 PY_mb_mian []={"面棉眠绵冕免勉娩缅沔渑湎宀腼眄"}; +const c8 PY_mb_miao []={"苗描瞄藐秒渺庙妙喵邈缈缪杪淼眇鹋"}; +const c8 PY_mb_mie []={"蔑灭乜咩篾蠛"}; +const c8 PY_mb_min []={"民抿皿敏悯闽苠岷闵泯缗玟珉愍黾鳘"}; +const c8 PY_mb_ming []={"明螟鸣铭名命冥茗溟暝瞑酩"}; +const c8 PY_mb_miu []={"谬缪"}; +const c8 PY_mb_mo []={"脉没摸摹蘑模膜磨摩魔抹末莫墨默沫漠寞陌麽万谟茉蓦馍嫫殁镆秣瘼耱貊貘"}; +const c8 PY_mb_mou []={"谋牟某侔哞缪眸蛑鍪"}; +const c8 PY_mb_mu []={"木目睦模牟拇牡亩姆母墓暮幕募慕牧穆苜沐仫坶毪钼"}; +const c8 PY_mb_na []={"拿哪呐钠那娜纳捺肭镎衲"}; +const c8 PY_mb_nai []={"氖乃奶耐奈鼐佴艿萘柰"}; +const c8 PY_mb_nan []={"南男难喃囡楠腩蝻赧"}; +const c8 PY_mb_nang []={"囊囔馕攮曩"}; +const c8 PY_mb_nao []={"挠脑恼闹淖孬垴呶猱瑙硇铙蛲"}; +const c8 PY_mb_ne []={"哪呢讷"}; +const c8 PY_mb_nei []={"内馁"}; +const c8 PY_mb_nen []={"嫩恁"}; +const c8 PY_mb_neng []={"能"}; +const c8 PY_mb_ng []={"嗯"}; +const c8 PY_mb_ni []={"你呢拟尼妮霓倪泥匿腻逆溺伲坭猊怩昵旎祢慝睨铌鲵"}; +const c8 PY_mb_nian []={"蔫拈年碾撵捻念廿埝辇黏鲇鲶"}; +const c8 PY_mb_niang []={"娘酿"}; +const c8 PY_mb_niao []={"鸟尿脲袅茑嬲"}; +const c8 PY_mb_nie []={"捏聂孽啮镊镍涅蹑蘖嗫乜陧颞臬"}; +const c8 PY_mb_nin []={"您"}; +const c8 PY_mb_ning []={"柠狞凝宁拧泞佞咛甯聍"}; +const c8 PY_mb_niu []={"牛扭钮纽拗妞狃忸"}; +const c8 PY_mb_nong []={"脓浓农弄侬哝"}; +const c8 PY_mb_nou []={"耨"}; +const c8 PY_mb_nu []={"奴努怒弩胬孥驽"}; +const c8 PY_mb_nuan []={"暖"}; +const c8 PY_mb_nue []={"疟虐"}; +const c8 PY_mb_nuo []={"娜挪懦糯诺傩搦喏锘"}; +const c8 PY_mb_nv []={"女恧钕衄"}; +const c8 PY_mb_o []={"哦喔噢"}; +const c8 PY_mb_ou []={"欧鸥殴藕呕偶沤区讴怄瓯耦"}; +const c8 PY_mb_pa []={"扒耙啪趴爬帕怕琶葩杷筢"}; +const c8 PY_mb_pai []={"拍排牌徘湃派迫俳蒎哌"}; +const c8 PY_mb_pan []={"番攀潘盘磐盼畔判叛蟠蹒胖拚丬爿泮贲袢襻"}; +const c8 PY_mb_pang []={"膀磅镑乓庞旁耪胖彷滂螃逄"}; +const c8 PY_mb_pao []={"抛咆刨炮袍跑泡狍庖疱脬匏"}; +const c8 PY_mb_pei []={"呸胚培裴赔陪配佩沛辔霈帔旆锫醅"}; +const c8 PY_mb_pen []={"喷盆湓"}; +const c8 PY_mb_peng []={"芃捧碰砰抨烹澎彭蓬棚硼篷膨朋鹏怦堋嘭蟛"}; +const c8 PY_mb_pi []={"辟否坯砒霹批披劈琵毗啤脾疲皮匹痞僻丕屁譬癖貔仳陂陴邳郫圮埤鼙芘擗噼庀淠媲纰枇甓睥罴铍裨疋蚍蜱"}; +const c8 PY_mb_pian []={"扁便篇偏片骗谝骈缏犏胼翩蹁"}; +const c8 PY_mb_piao []={"飘漂瓢票朴剽嫖缥瞟嘌骠殍螵"}; +const c8 PY_mb_pie []={"撇瞥丿苤氕"}; +const c8 PY_mb_pin []={"拼频贫品聘姘嫔榀牝颦"}; +const c8 PY_mb_ping []={"冯乒坪苹萍平凭瓶评屏俜娉枰鲆"}; +const c8 PY_mb_po []={"泊繁坡泼颇婆破魄迫粕朴叵陂鄱珀攴攵钋钷皤笸"}; +const c8 PY_mb_pou []={"剖裒掊"}; +const c8 PY_mb_pu []={"普堡暴脯扑铺仆莆葡菩蒲埔朴圃浦谱曝瀑匍噗溥蹼濮璞氆镤镨"}; +const c8 PY_mb_qi []={"七起妻乞企启稽缉期欺栖戚凄漆柒沏其棋奇歧畦崎脐齐旗祈岐祁骑岂琪琦杞契砌器气迄弃汽泣讫亟祺憩蹊鳍麒亓俟圻芑芪荠萋葺淇骐绮耆蕲桤槭欹嘁屺汔碛颀蛴蜞綦綮"}; +const c8 PY_mb_qia []={"卡掐恰洽葜袷髂"}; +const c8 PY_mb_qian []={"牵扦钎铅千迁签仟谦乾黔钱钳前潜遣浅谴堑嵌欠歉纤倩佥阡芊芡茜荨掮岍悭慊骞搴褰缱椠犍肷愆钤虔箝羟"}; +const c8 PY_mb_qiang []={"枪呛腔羌墙蔷强抢跄戕戗炝锵镪丬襁嫱樯蜣羟"}; +const c8 PY_mb_qiao []={"壳橇锹敲悄桥瞧乔侨巧鞘撬翘峭俏窍雀诮谯荞峤憔樵跷鞒缲劁愀硗铫"}; +const c8 PY_mb_qie []={"切茄且怯窃伽惬慊妾趄郄挈锲箧"}; +const c8 PY_mb_qin []={"钦侵亲秦琴勤芹擒禽寝沁芩揿衾吣嗪噙廑檎锓矜覃螓"}; +const c8 PY_mb_qing []={"亲青轻氢倾卿清擎晴氰情顷请庆磬苘圊檠锖蜻罄箐綮謦鲭黥"}; +const c8 PY_mb_qiong []={"琼穷穹蛩邛茕筇跫銎"}; +const c8 PY_mb_qiu []={"仇龟秋丘邱球求囚酋泅俅逑裘糗遒巯犰湫楸赇虬蚯蝤鳅"}; +const c8 PY_mb_qu []={"趋区蛆曲躯屈驱渠取娶龋趣去蛐黢戌诎劬凵苣蕖蘧岖衢阒璩觑氍朐祛磲鸲癯蠼麴瞿"}; +const c8 PY_mb_quan []={"圈颧权醛泉全痊拳犬券劝诠荃蜷鬈犭悛绻辁畎铨筌"}; +const c8 PY_mb_que []={"缺炔瘸却鹊榷确雀阕阙悫"}; +const c8 PY_mb_qui []={"鼽"}; +const c8 PY_mb_qun []={"裙群逡麇"}; +const c8 PY_mb_ran []={"然燃冉染苒蚺髯"}; +const c8 PY_mb_rang []={"瓤壤攘嚷让禳穰"}; +const c8 PY_mb_rao []={"饶扰绕荛娆桡"}; +const c8 PY_mb_re []={"惹热喏"}; +const c8 PY_mb_ren []={"壬仁人忍韧任认刃妊纫稔亻仞荏葚饪轫衽"}; +const c8 PY_mb_reng []={"扔仍"}; +const c8 PY_mb_ri []={"日"}; +const c8 PY_mb_rong []={"戎茸蓉荣融熔溶容绒冗嵘狨榕肜蝾"}; +const c8 PY_mb_rou []={"揉柔肉糅蹂鞣"}; +const c8 PY_mb_ru []={"茹蠕儒孺如辱乳汝入濡褥溽蓐嚅薷洳缛铷襦颥"}; +const c8 PY_mb_ruan []={"软阮朊"}; +const c8 PY_mb_rui []={"蕊瑞锐芮睿枘蕤蚋"}; +const c8 PY_mb_run []={"闰润"}; +const c8 PY_mb_ruo []={"若弱偌箬"}; +const c8 PY_mb_sa []={"撒洒萨卅仨飒脎"}; +const c8 PY_mb_sai []={"腮鳃塞赛噻"}; +const c8 PY_mb_san []={"三叁伞散馓毵糁"}; +const c8 PY_mb_sang []={"桑嗓丧搡磉颡"}; +const c8 PY_mb_sao []={"搔骚扫嫂臊瘙埽缫鳋"}; +const c8 PY_mb_se []={"塞瑟色涩啬铯穑"}; +const c8 PY_mb_sen []={"森"}; +const c8 PY_mb_seng []={"僧"}; +const c8 PY_mb_sha []={"莎砂杀刹沙纱傻啥煞杉厦痧裟霎鲨唼歃铩"}; +const c8 PY_mb_shai []={"色筛晒"}; +const c8 PY_mb_shan []={"掺单珊苫杉山删煽衫闪陕擅赡膳善汕扇缮栅讪疝舢蟮跚鳝剡鄯埏芟彡潸姗嬗骟膻禅钐髟"}; +const c8 PY_mb_shang []={"墒伤商赏晌上尚裳绱殇觞垧熵"}; +const c8 PY_mb_shao []={"鞘梢捎稍烧芍勺韶少哨邵绍劭苕艄潲杓蛸筲"}; +const c8 PY_mb_she []={"奢赊蛇舌舍赦摄射慑涉社设麝折厍佘揲猞滠歙畲铊"}; +const c8 PY_mb_shei []={"谁"}; +const c8 PY_mb_shen []={"什参砷申呻伸身深娠绅神沈审婶甚肾慎渗诜谂莘葚哂渖椹胂矧蜃"}; +const c8 PY_mb_sheng []={"乘声生甥牲升绳省盛剩胜圣笙嵊渑晟眚"}; +const c8 PY_mb_shi []={"是事匙师十石失狮施湿诗尸虱拾时什食蚀实识史矢使屎驶始式示士世柿拭誓逝势嗜噬适仕侍释饰氏市恃室视试似弑舐殖峙谥埘莳蓍饣轼贳炻礻铈铊螫筮酾豕鲥鲺"}; +const c8 PY_mb_shou []={"收手首守寿授售受瘦兽扌狩绶艏"}; +const c8 PY_mb_shu []={"蔬枢梳殊抒输叔舒淑疏书赎孰熟薯暑曙署蜀黍鼠属术述树束戍竖墅庶数漱恕倏塾沭澍姝丨菽摅纾毹腧殳镯秫疋"}; +const c8 PY_mb_shua []={"刷耍唰"}; +const c8 PY_mb_shuai []={"率摔衰甩帅蟀"}; +const c8 PY_mb_shuan []={"栓拴闩涮"}; +const c8 PY_mb_shuang[]={"霜双爽泷孀"}; +const c8 PY_mb_shui []={"水睡谁税说氵"}; +const c8 PY_mb_shun []={"吮瞬顺舜"}; +const c8 PY_mb_shuo []={"数说硕朔烁蒴搠妁槊铄"}; +const c8 PY_mb_si []={"斯撕嘶思私司丝死肆寺嗣四伺似饲巳厮咝俟兕厶饣汜泗澌姒驷缌祀锶鸶耜蛳笥"}; +const c8 PY_mb_song []={"松耸怂颂送宋讼诵嵩忪悚淞竦崧菘凇"}; +const c8 PY_mb_sou []={"搜艘擞嗽叟嗖馊溲飕瞍锼螋嗾薮"}; +const c8 PY_mb_su []={"苏酥俗素速粟僳塑溯宿诉肃缩夙愫涑簌稣谡蔌嗉觫"}; +const c8 PY_mb_suan []={"酸蒜算狻"}; +const c8 PY_mb_sui []={"虽岁绥隋随髓祟遂碎隧穗"}; +const c8 PY_mb_sun []={"孙损笋"}; +const c8 PY_mb_suo []={"蓑梭唆缩琐索锁所唢嗦嗍娑莎桫挲睃羧"}; +const c8 PY_mb_ta []={"塌他它她塔獭挞沓蹋踏拓闼遢榻铊趿溻鳎漯"}; +const c8 PY_mb_tai []={"胎苔抬台泰酞太态汰跆邰薹骀肽炱钛鲐"}; +const c8 PY_mb_tan []={"弹坍摊贪瘫滩坛檀痰潭谭谈坦毯袒碳探叹炭覃郯澹昙赕忐钽锬镡"}; +const c8 PY_mb_tang []={"汤塘搪堂棠膛唐糖倘躺淌趟烫傥饧溏瑭樘铛螳铴镗耥螗羰醣帑"}; +const c8 PY_mb_tao []={"掏涛滔绦萄桃逃淘陶讨套叨啕饕洮韬焘鼗"}; +const c8 PY_mb_te []={"特忒忑铽"}; +const c8 PY_mb_teng []={"藤腾疼滕誊"}; +const c8 PY_mb_ti []={"梯剔踢锑提题蹄啼体替嚏惕涕剃屉倜悌缇荑逖绨鹈裼醍"}; +const c8 PY_mb_tian []={"天添填田甜恬舔腆殄掭忝阗畋钿锘"}; +const c8 PY_mb_tiao []={"调挑条迢眺跳佻髫苕祧铫窕蜩笤粜龆鲦"}; +const c8 PY_mb_tie []={"贴铁帖餮锇萜"}; +const c8 PY_mb_ting []={"厅听烃汀廷停亭庭挺艇莛葶婷铤蜓霆梃"}; +const c8 PY_mb_tong []={"桐瞳同铜彤童桶捅筒统痛佟僮茼恸潼酮仝垌嗵峒砼"}; +const c8 PY_mb_tou []={"偷投头透骰钭亠"}; +const c8 PY_mb_tu []={"凸秃突图徒途涂屠土吐兔堍荼菟钍酴"}; +const c8 PY_mb_tuan []={"湍团抟彖疃"}; +const c8 PY_mb_tui []={"推颓腿蜕褪退煺"}; +const c8 PY_mb_tun []={"囤褪吞屯臀饨豚氽暾"}; +const c8 PY_mb_tuo []={"说拖拓托脱鸵陀驮驼椭妥唾跎乇佗坨沱柝柁橐砣铊鼍箨酡庹"}; +const c8 PY_mb_wa []={"挖哇蛙洼娃瓦袜佤娲腽"}; +const c8 PY_mb_wai []={"歪外崴"}; +const c8 PY_mb_wan []={"蔓豌弯湾玩顽丸烷完碗挽晚皖惋宛婉万腕剜芄莞菀纨蜿绾琬脘畹鞔"}; +const c8 PY_mb_wang []={"汪王亡枉网往旺望忘妄罔惘魍尢辋"}; +const c8 PY_mb_wei []={"为位谓威巍微危韦维违桅围唯惟潍苇萎委伟伪尾纬未蔚味畏胃喂魏渭尉慰卫偎诿隗圩葳薇帏帷崴嵬猬逶娓痿炜玮闱猥隈沩洧涠韪軎煨艉鲔囗"}; +const c8 PY_mb_wen []={"问文闻纹瘟温蚊吻稳紊刎雯玟阌汶璺"}; +const c8 PY_mb_weng []={"嗡翁瓮蓊蕹"}; +const c8 PY_mb_wo []={"我握喔蜗涡窝斡卧沃挝倭莴幄龌渥肟硪"}; +const c8 PY_mb_wu []={"五物勿务午舞伍武侮恶悟误兀巫雾呜钨乌污诬屋无芜梧吾吴毋捂坞戊晤仵邬鹉圬芴唔庑怃忤鹜痦蜈浯寤迕妩婺骛阢杌牾於焐鋈鼯"}; +const c8 PY_mb_xi []={"希习夕戏细昔熙析西硒矽晰嘻吸锡牺稀蹊息悉膝惜熄溪汐犀袭席媳喜洗系隙羲皙屣嬉玺樨奚茜檄烯铣匚僖兮隰郗菥葸蓰唏徙饩阋浠淅曦觋欷歙熹禊禧穸裼蜥螅蟋舄舾粞翕醯鼷"}; +const c8 PY_mb_xia []={"瞎虾匣霞辖暇峡侠狭下厦夏吓呷狎遐瑕柙硖罅黠"}; +const c8 PY_mb_xian []={"现先仙嫌显险献县贤铣洗掀锨鲜纤咸衔舷闲涎弦腺馅羡宪陷限线冼苋莶藓岘猃暹娴氙燹祆鹇痃痫蚬筅籼酰跣跹霰"}; +const c8 PY_mb_xiang []={"像向象降相厢镶香箱湘乡翔祥详想响享项巷橡襄飨芗葙饷庠骧缃蟓鲞"}; +const c8 PY_mb_xiao []={"小消肖萧硝霄削哮嚣销宵淆晓孝校啸笑效哓潇逍筱箫骁绡枭枵蛸魈"}; +const c8 PY_mb_xie []={"些歇蝎鞋协挟携邪斜胁谐写械卸蟹懈泄泻谢屑血解楔叶偕亵勰燮薤撷獬廨渫瀣邂绁缬榭榍颉躞鲑骱"}; +const c8 PY_mb_xin []={"薪芯锌欣辛新忻心信衅馨莘歆鑫昕囟忄镡"}; +const c8 PY_mb_xing []={"幸省星腥猩惺兴刑型形邢行醒杏性姓饧陉荇荥擤悻硎"}; +const c8 PY_mb_xiong []={"兄凶胸匈汹雄熊芎"}; +const c8 PY_mb_xiu []={"臭宿休修羞朽嗅锈秀袖绣咻溴貅馐岫庥鸺髹"}; +const c8 PY_mb_xu []={"续绪墟戌需虚嘘须徐许蓄酗叙旭序畜恤絮婿诩煦勖圩蓿洫浒溆顼栩吁胥盱糈醑"}; +const c8 PY_mb_xuan []={"玄选轩喧宣渲悬旋暄绚炫眩癣儇谖萱泫漩璇楦煊揎碹铉镟券"}; +const c8 PY_mb_xue []={"削靴薛学穴雪血鳕谑噱泶踅"}; +const c8 PY_mb_xun []={"寻旬迅讯询训勋熏循驯巡殉汛逊郇埙荀薰峋徇醺鲟浚荨蕈獯巽恂洵浔曛窨"}; +const c8 PY_mb_ya []={"牙芽亚哑压雅押鸦鸭呀丫崖衙涯讶轧伢蚜垭揠岈迓娅琊桠氩砑睚痖疋"}; +const c8 PY_mb_yan []={"言演验厌严沿炎燕咽阉奄掩眼烟淹盐研岩延颜阎衍艳堰砚雁唁焉彦焰宴谚蜒闫妍嫣胭腌焱恹俨偃铅殷厣赝剡兖讠谳阽郾鄢芫菸崦魇阏湮滟琰檐晏罨筵酽餍鼹鼽"}; +const c8 PY_mb_yang []={"央仰羊洋阳养样杨扬恙殃鸯秧佯氧疡痒漾徉怏泱炀烊蛘鞅"}; +const c8 PY_mb_yao []={"要邀咬药腰妖摇尧肴窈遥窑谣姚舀耀钥夭爻幺吆瑶啮疟侥崤崾徭珧杳轺曜铫鹞繇鳐"}; +const c8 PY_mb_ye []={"也页业叶夜液椰噎耶爷野冶掖曳腋邪咽谒盅靥邺揶琊晔烨铘"}; +const c8 PY_mb_yi []={"一乙已以忆义议谊译异益壹医揖铱依伊衣颐夷遗移仪胰疑沂宜姨彝椅蚁倚矣艺抑易邑屹亿役臆逸肄疫亦裔意毅溢诣翼翌艾尾绎刈劓佚佾诒阝圯埸懿苡荑薏弈奕挹弋呓咦咿噫峄嶷猗饴怿怡悒漪迤驿缢殪轶贻欹旖熠眙钇铊镒镱痍瘗癔翊衤蜴舣羿翳酏黟"}; +const c8 PY_mb_yin []={"尹引印茵荫因殷音阴姻吟银淫寅饮隐龈胤蚓鄞廴垠堙茚吲喑狺夤洇湮氤铟瘾窨霪"}; +const c8 PY_mb_ying []={"映影英莹萤营荧樱婴鹰应缨蝇迎赢盈颖硬嬴莺萦鹦潆瀛滢瑛郢茔荥蓥撄嘤膺璎楹媵瘿颍罂"}; +const c8 PY_mb_yo []={"哟育唷"}; +const c8 PY_mb_yong []={"用拥佣勇涌臃痈庸雍踊蛹咏泳永恿俑壅墉喁慵邕镛甬鳙饔"}; +const c8 PY_mb_you []={"尤有又诱幼友右佑幽优悠忧由邮铀犹油游酉釉呦疣鱿黝鼬蚰攸卣侑莠莜莸尢囿宥柚猷牖铕蚴蝣蝤繇"}; +const c8 PY_mb_yu []={"余与于予宇玉雨育誉浴鱼迂淤盂虞愚舆俞逾愉渝渔隅娱屿禹语羽域芋郁吁遇喻峪御愈榆欲狱寓裕预豫驭竽毓谀於谕蔚尉禺伛俣萸菀蓣揄圄圉嵛狳饫馀庾阈鬻妪妤纡瑜昱觎腴欤煜熨燠肀聿钰鹆鹬瘐瘀窬窳蜮蝓臾舁雩龉"}; +const c8 PY_mb_yuan []={"原元园员圆源缘远愿怨院鸳渊冤垣袁援辕猿苑媛塬芫掾圜沅瑗橼爰眢鸢螈箢鼋"}; +const c8 PY_mb_yue []={"月悦阅乐说曰约越跃钥岳粤龠哕瀹栎樾刖钺"}; +const c8 PY_mb_yun []={"云员允运晕耘匀陨蕴酝熨韵孕氲殒芸郧郓狁恽愠纭韫昀筠"}; +const c8 PY_mb_za []={"匝砸杂扎咋咂拶"}; +const c8 PY_mb_zai []={"再在栽哉灾宰载崽甾"}; +const c8 PY_mb_zan []={"咱攒暂赞昝簪拶瓒糌趱錾"}; +const c8 PY_mb_zang []={"藏赃脏葬驵臧"}; +const c8 PY_mb_zao []={"枣遭早造皂灶糟凿澡躁噪燥藻蚤唣"}; +const c8 PY_mb_ze []={"责择则泽咋仄赜啧帻迮昃笮箦舴"}; +const c8 PY_mb_zei []={"贼"}; +const c8 PY_mb_zen []={"怎谮"}; +const c8 PY_mb_zeng []={"增憎曾赠缯甑罾锃"}; +const c8 PY_mb_zha []={"扎闸查喳渣札轧铡眨栅榨咋乍炸诈吒咤柞揸蚱哳喋楂砟痄龃齄"}; +const c8 PY_mb_zhai []={"宅窄债翟择摘斋寨砦瘵"}; +const c8 PY_mb_zhan []={"占战站展沾绽瞻毡詹粘盏斩辗崭蘸颤栈湛谵搌骣旃"}; +const c8 PY_mb_zhang []={"张丈仗胀杖樟章彰漳掌涨帐账长瘴障幛嶂獐蟑仉鄣嫜璋"}; +const c8 PY_mb_zhao []={"找召爪着兆朝招昭诏沼赵照罩肇钊笊啁棹"}; +const c8 PY_mb_zhe []={"遮折哲蛰辙者锗蔗这浙着谪摺柘辄磔鹧褶蜇赭"}; +const c8 PY_mb_zhen []={"真贞针震振诊阵镇侦枕珍疹斟甄箴臻帧圳砧蓁浈溱缜桢椹榛轸赈胗朕祯畛稹鸩"}; +const c8 PY_mb_zheng []={"正证蒸挣睁征狰争怔整拯政症郑诤峥徵钲铮筝鲭"}; +const c8 PY_mb_zhi []={"只职识执值直植殖治支纸志址指质置制止至侄芝之汁旨枝知肢脂织趾挚掷致帜峙智秩稚吱蜘炙痔滞窒枳芷卮陟郅埴摭帙徵夂忮彘咫骘栉栀桎轵轾贽胝膣祉祗黹雉鸷痣蛭絷酯跖踬踯豸觯"}; +const c8 PY_mb_zhong []={"中众忠钟衷终种肿重仲盅冢忪锺螽舯踵"}; +const c8 PY_mb_zhou []={"舟周州洲诌粥轴肘帚咒皱宙昼骤荮啁妯纣绉胄碡籀繇酎"}; +const c8 PY_mb_zhu []={"主住注祝竹珠株蛛朱猪诸诛逐烛煮拄瞩嘱著柱助蛀贮铸筑驻伫竺箸侏属术邾苎茱洙渚潴杼槠橥炷铢疰瘃褚舳翥躅麈丶"}; +const c8 PY_mb_zhua []={"抓爪挝"}; +const c8 PY_mb_zhuai []={"拽转"}; +const c8 PY_mb_zhuan []={"传专砖转撰赚篆啭馔沌颛"}; +const c8 PY_mb_zhuang[]={"幢桩庄装妆撞壮状奘戆"}; +const c8 PY_mb_zhui []={"椎锥追赘坠缀惴骓缒隹"}; +const c8 PY_mb_zhun []={"谆准饨肫窀"}; +const c8 PY_mb_zhuo []={"着捉拙卓桌灼茁浊酌琢啄倬诼擢浞涿濯焯禚斫镯"}; +const c8 PY_mb_zi []={"自子字仔兹咨资姿滋淄孜紫籽滓渍龇姊吱嵫谘茈孳缁梓辎赀恣眦锱秭耔笫粢趑觜訾鲻髭"}; +const c8 PY_mb_zong []={"宗综总鬃棕踪纵粽偬枞腙"}; +const c8 PY_mb_zou []={"走奏揍邹诹陬鄹驺鲰"}; +const c8 PY_mb_zu []={"足组卒族租祖诅阻俎菹镞"}; +const c8 PY_mb_zuan []={"钻攥纂缵躜"}; +const c8 PY_mb_zui []={"最罪嘴醉蕞觜"}; +const c8 PY_mb_zun []={"尊遵樽鳟撙"}; +const c8 PY_mb_zuo []={"左佐做作坐座昨撮唑柞阼琢嘬怍胙祚砟酢"}; + +//拼音索引表 +const Tpy_index py_index3[]= +{ +{"" ,"",(c8*)PY_mb_space}, +{"2","a",(c8*)PY_mb_a}, +{"3","e",(c8*)PY_mb_e}, +{"6","o",(c8*)PY_mb_o}, +{"24","ai",(c8*)PY_mb_ai}, +{"26","an",(c8*)PY_mb_an}, +{"26","ao",(c8*)PY_mb_ao}, +{"22","ba",(c8*)PY_mb_ba}, +{"24","bi",(c8*)PY_mb_bi}, +{"26","bo",(c8*)PY_mb_bo}, +{"28","bu",(c8*)PY_mb_bu}, +{"22","ca",(c8*)PY_mb_ca}, +{"23","ce",(c8*)PY_mb_ce}, +{"24","ci",(c8*)PY_mb_ci}, +{"28","cu",(c8*)PY_mb_cu}, +{"32","da",(c8*)PY_mb_da}, +{"33","de",(c8*)PY_mb_de}, +{"34","di",(c8*)PY_mb_di}, +{"38","du",(c8*)PY_mb_du}, +{"36","en",(c8*)PY_mb_en}, +{"37","er",(c8*)PY_mb_er}, +{"32","fa",(c8*)PY_mb_fa}, +{"36","fo",(c8*)PY_mb_fo}, +{"38","fu",(c8*)PY_mb_fu}, +{"42","ha",(c8*)PY_mb_ha}, +{"42","ga",(c8*)PY_mb_ga}, +{"43","ge",(c8*)PY_mb_ge}, +{"43","he",(c8*)PY_mb_he}, +{"48","gu",(c8*)PY_mb_gu}, +{"48","hu",(c8*)PY_mb_hu}, +{"54","ji",(c8*)PY_mb_ji}, +{"58","ju",(c8*)PY_mb_ju}, +{"52","ka",(c8*)PY_mb_ka}, +{"53","ke",(c8*)PY_mb_ke}, +{"58","ku",(c8*)PY_mb_ku}, +{"52","la",(c8*)PY_mb_la}, +{"53","le",(c8*)PY_mb_le}, +{"54","li",(c8*)PY_mb_li}, +{"58","lu",(c8*)PY_mb_lu}, +{"58","lv",(c8*)PY_mb_lv}, +{"62","ma",(c8*)PY_mb_ma}, +{"63","me",(c8*)PY_mb_me}, +{"64","mi",(c8*)PY_mb_mi}, +{"66","mo",(c8*)PY_mb_mo}, +{"68","mu",(c8*)PY_mb_mu}, +{"62","na",(c8*)PY_mb_na}, +{"63","ne",(c8*)PY_mb_ne}, +{"64","ni",(c8*)PY_mb_ni}, +{"68","nu",(c8*)PY_mb_nu}, +{"68","nv",(c8*)PY_mb_nv}, +{"68","ou",(c8*)PY_mb_ou}, +{"72","pa",(c8*)PY_mb_pa}, +{"74","pi",(c8*)PY_mb_pi}, +{"76","po",(c8*)PY_mb_po}, +{"78","pu",(c8*)PY_mb_pu}, +{"74","qi",(c8*)PY_mb_qi}, +{"78","qu",(c8*)PY_mb_qu}, +{"73","re",(c8*)PY_mb_re}, +{"74","ri",(c8*)PY_mb_ri}, +{"78","ru",(c8*)PY_mb_ru}, +{"72","sa",(c8*)PY_mb_sa}, +{"73","se",(c8*)PY_mb_se}, +{"74","si",(c8*)PY_mb_si}, +{"78","su",(c8*)PY_mb_su}, +{"82","ta",(c8*)PY_mb_ta}, +{"83","te",(c8*)PY_mb_te}, +{"84","ti",(c8*)PY_mb_ti}, +{"88","tu",(c8*)PY_mb_tu}, +{"92","wa",(c8*)PY_mb_wa}, +{"96","wo",(c8*)PY_mb_wo}, +{"98","wu",(c8*)PY_mb_wu}, +{"94","xi",(c8*)PY_mb_xi}, +{"98","xu",(c8*)PY_mb_xu}, +{"92","ya",(c8*)PY_mb_ya}, +{"93","ye",(c8*)PY_mb_ye}, +{"94","yi",(c8*)PY_mb_yi}, +{"96","yo",(c8*)PY_mb_yo}, +{"98","yu",(c8*)PY_mb_yu}, +{"92","za",(c8*)PY_mb_za}, +{"93","ze",(c8*)PY_mb_ze}, +{"94","zi",(c8*)PY_mb_zi}, +{"98","zu",(c8*)PY_mb_zu}, +{"264","ang",(c8*)PY_mb_ang}, +{"224","bai",(c8*)PY_mb_bai}, +{"226","ban",(c8*)PY_mb_ban}, +{"226","bao",(c8*)PY_mb_bao}, +{"234","bei",(c8*)PY_mb_bei}, +{"236","ben",(c8*)PY_mb_ben}, +{"243","bie",(c8*)PY_mb_bie}, +{"246","bin",(c8*)PY_mb_bin}, +{"224","cai",(c8*)PY_mb_cai}, +{"226","can",(c8*)PY_mb_can}, +{"226","cao",(c8*)PY_mb_cao}, +{"242","cha",(c8*)PY_mb_cha}, +{"243","che",(c8*)PY_mb_che}, +{"244","chi",(c8*)PY_mb_chi}, +{"248","chu",(c8*)PY_mb_chu}, +{"268","cou",(c8*)PY_mb_cou}, +{"284","cui",(c8*)PY_mb_cui}, +{"286","cun",(c8*)PY_mb_cun}, +{"286","cuo",(c8*)PY_mb_cuo}, +{"324","dai",(c8*)PY_mb_dai}, +{"326","dan",(c8*)PY_mb_dan}, +{"326","dao",(c8*)PY_mb_dao}, +{"334","dei",(c8*)PY_mb_dei}, +{"343","die",(c8*)PY_mb_die}, +{"348","diu",(c8*)PY_mb_diu}, +{"368","dou",(c8*)PY_mb_dou}, +{"384","dui",(c8*)PY_mb_dui}, +{"386","dun",(c8*)PY_mb_dun}, +{"386","duo",(c8*)PY_mb_duo}, +{"326","fan",(c8*)PY_mb_fan}, +{"334","fei",(c8*)PY_mb_fei}, +{"336","fen",(c8*)PY_mb_fen}, +{"368","fou",(c8*)PY_mb_fou}, +{"424","gai",(c8*)PY_mb_gai}, +{"426","gan",(c8*)PY_mb_gan}, +{"426","gao",(c8*)PY_mb_gao}, +{"434","gei",(c8*)PY_mb_gei}, +{"436","gen",(c8*)PY_mb_gen}, +{"468","gou",(c8*)PY_mb_gou}, +{"482","gua",(c8*)PY_mb_gua}, +{"484","gui",(c8*)PY_mb_gui}, +{"486","gun",(c8*)PY_mb_gun}, +{"486","guo",(c8*)PY_mb_guo}, +{"424","hai",(c8*)PY_mb_hai}, +{"426","han",(c8*)PY_mb_han}, +{"426","hao",(c8*)PY_mb_hao}, +{"434","hei",(c8*)PY_mb_hei}, +{"436","hen",(c8*)PY_mb_hen}, +{"468","hou",(c8*)PY_mb_hou}, +{"482","hua",(c8*)PY_mb_hua}, +{"484","hui",(c8*)PY_mb_hui}, +{"486","hun",(c8*)PY_mb_hun}, +{"486","huo",(c8*)PY_mb_huo}, +{"542","jia",(c8*)PY_mb_jia}, +{"543","jie",(c8*)PY_mb_jie}, +{"546","jin",(c8*)PY_mb_jin}, +{"548","jiu",(c8*)PY_mb_jiu}, +{"583","jue",(c8*)PY_mb_jue}, +{"586","jun",(c8*)PY_mb_jun}, +{"524","kai",(c8*)PY_mb_kai}, +{"526","kan",(c8*)PY_mb_kan}, +{"526","kao",(c8*)PY_mb_kao}, +{"536","ken",(c8*)PY_mb_ken}, +{"568","kou",(c8*)PY_mb_kou}, +{"582","kua",(c8*)PY_mb_kua}, +{"584","kui",(c8*)PY_mb_kui}, +{"586","kun",(c8*)PY_mb_kun}, +{"586","kuo",(c8*)PY_mb_kuo}, +{"524","lai",(c8*)PY_mb_lai}, +{"526","lan",(c8*)PY_mb_lan}, +{"526","lao",(c8*)PY_mb_lao}, +{"534","lei",(c8*)PY_mb_lei}, +{"543","lie",(c8*)PY_mb_lie}, +{"546","lin",(c8*)PY_mb_lin}, +{"548","liu",(c8*)PY_mb_liu}, +{"568","lou",(c8*)PY_mb_lou}, +{"583","lue",(c8*)PY_mb_lue}, +{"586","lun",(c8*)PY_mb_lun}, +{"586","luo",(c8*)PY_mb_luo}, +{"624","mai",(c8*)PY_mb_mai}, +{"626","man",(c8*)PY_mb_man}, +{"626","mao",(c8*)PY_mb_mao}, +{"634","mei",(c8*)PY_mb_mei}, +{"636","men",(c8*)PY_mb_men}, +{"643","mie",(c8*)PY_mb_mie}, +{"646","min",(c8*)PY_mb_min}, +{"648","miu",(c8*)PY_mb_miu}, +{"668","mou",(c8*)PY_mb_mou}, +{"624","nai",(c8*)PY_mb_nai}, +{"626","nan",(c8*)PY_mb_nan}, +{"626","nao",(c8*)PY_mb_nao}, +{"634","nei",(c8*)PY_mb_nei}, +{"636","nen",(c8*)PY_mb_nen}, +{"643","nie",(c8*)PY_mb_nie}, +{"646","nin",(c8*)PY_mb_nin}, +{"648","niu",(c8*)PY_mb_niu}, +{"683","nue",(c8*)PY_mb_nue}, +{"686","nuo",(c8*)PY_mb_nuo}, +{"724","pai",(c8*)PY_mb_pai}, +{"726","pan",(c8*)PY_mb_pan}, +{"726","pao",(c8*)PY_mb_pao}, +{"734","pei",(c8*)PY_mb_pei}, +{"736","pen",(c8*)PY_mb_pen}, +{"743","pie",(c8*)PY_mb_pie}, +{"746","pin",(c8*)PY_mb_pin}, +{"768","pou",(c8*)PY_mb_pou}, +{"742","qia",(c8*)PY_mb_qia}, +{"743","qie",(c8*)PY_mb_qie}, +{"746","qin",(c8*)PY_mb_qin}, +{"748","qiu",(c8*)PY_mb_qiu}, +{"783","que",(c8*)PY_mb_que}, +{"786","qun",(c8*)PY_mb_qun}, +{"726","ran",(c8*)PY_mb_ran}, +{"726","rao",(c8*)PY_mb_rao}, +{"736","ren",(c8*)PY_mb_ren}, +{"768","rou",(c8*)PY_mb_rou}, +{"784","rui",(c8*)PY_mb_rui}, +{"786","run",(c8*)PY_mb_run}, +{"786","ruo",(c8*)PY_mb_ruo}, +{"724","sai",(c8*)PY_mb_sai}, +{"726","sao",(c8*)PY_mb_sao}, +{"726","san",(c8*)PY_mb_san}, +{"736","sen",(c8*)PY_mb_sen}, +{"742","sha",(c8*)PY_mb_sha}, +{"743","she",(c8*)PY_mb_she}, +{"744","shi",(c8*)PY_mb_shi}, +{"748","shu",(c8*)PY_mb_shu}, +{"768","sou",(c8*)PY_mb_sou}, +{"784","sui",(c8*)PY_mb_sui}, +{"786","sun",(c8*)PY_mb_sun}, +{"786","suo",(c8*)PY_mb_suo}, +{"824","tai",(c8*)PY_mb_tai}, +{"826","tan",(c8*)PY_mb_tan}, +{"826","tao",(c8*)PY_mb_tao}, +{"843","tie",(c8*)PY_mb_tie}, +{"868","tou",(c8*)PY_mb_tou}, +{"884","tui",(c8*)PY_mb_tui}, +{"886","tun",(c8*)PY_mb_tun}, +{"886","tuo",(c8*)PY_mb_tuo}, +{"924","wai",(c8*)PY_mb_wai}, +{"926","wan",(c8*)PY_mb_wan}, +{"934","wei",(c8*)PY_mb_wei}, +{"936","wen",(c8*)PY_mb_wen}, +{"942","xia",(c8*)PY_mb_xia}, +{"943","xie",(c8*)PY_mb_xie}, +{"946","xin",(c8*)PY_mb_xin}, +{"948","xiu",(c8*)PY_mb_xiu}, +{"983","xue",(c8*)PY_mb_xue}, +{"986","xun",(c8*)PY_mb_xun}, +{"926","yan",(c8*)PY_mb_yan}, +{"926","yao",(c8*)PY_mb_yao}, +{"946","yin",(c8*)PY_mb_yin}, +{"968","you",(c8*)PY_mb_you}, +{"983","yue",(c8*)PY_mb_yue}, +{"986","yun",(c8*)PY_mb_yun}, +{"924","zai",(c8*)PY_mb_zai}, +{"926","zan",(c8*)PY_mb_zan}, +{"926","zao",(c8*)PY_mb_zao}, +{"934","zei",(c8*)PY_mb_zei}, +{"936","zen",(c8*)PY_mb_zen}, +{"942","zha",(c8*)PY_mb_zha}, +{"943","zhe",(c8*)PY_mb_zhe}, +{"944","zhi",(c8*)PY_mb_zhi}, +{"948","zhu",(c8*)PY_mb_zhu}, +{"968","zou",(c8*)PY_mb_zou}, +{"984","zui",(c8*)PY_mb_zui}, +{"986","zun",(c8*)PY_mb_zun}, +{"986","zuo",(c8*)PY_mb_zuo}, +{"2264","bang",(c8*)PY_mb_bang}, +{"2364","beng",(c8*)PY_mb_beng}, +{"2426","bian",(c8*)PY_mb_bian}, +{"2426","biao",(c8*)PY_mb_biao}, +{"2464","bing",(c8*)PY_mb_bing}, +{"2264","cang",(c8*)PY_mb_cang}, +{"2364","ceng",(c8*)PY_mb_ceng}, +{"2424","chai",(c8*)PY_mb_chai}, +{"2426","chan",(c8*)PY_mb_chan}, +{"2426","chao",(c8*)PY_mb_chao}, +{"2436","chen",(c8*)PY_mb_chen}, +{"2468","chou",(c8*)PY_mb_chou}, +{"2484","chuai",(c8*)PY_mb_chuai}, +{"2484","chui",(c8*)PY_mb_chui}, +{"2486","chun",(c8*)PY_mb_chun}, +{"2486","chuo",(c8*)PY_mb_chuo}, +{"2664","cong",(c8*)PY_mb_cong}, +{"2826","cuan",(c8*)PY_mb_cuan}, +{"3264","dang",(c8*)PY_mb_dang}, +{"3364","deng",(c8*)PY_mb_deng}, +{"3426","dian",(c8*)PY_mb_dian}, +{"3426","diao",(c8*)PY_mb_diao}, +{"3464","ding",(c8*)PY_mb_ding}, +{"3664","dong",(c8*)PY_mb_dong}, +{"3826","duan",(c8*)PY_mb_duan}, +{"3264","fang",(c8*)PY_mb_fang}, +{"3364","feng",(c8*)PY_mb_feng}, +{"4264","gang",(c8*)PY_mb_gang}, +{"4364","geng",(c8*)PY_mb_geng}, +{"4664","gong",(c8*)PY_mb_gong}, +{"4824","guai",(c8*)PY_mb_guai}, +{"4826","guan",(c8*)PY_mb_guan}, +{"4264","hang",(c8*)PY_mb_hang}, +{"4364","heng",(c8*)PY_mb_heng}, +{"4664","hong",(c8*)PY_mb_hong}, +{"4823","huai",(c8*)PY_mb_huai}, +{"4826","huan",(c8*)PY_mb_huan}, +{"5426","jian",(c8*)PY_mb_jian}, +{"5426","jiao",(c8*)PY_mb_jiao}, +{"5464","jing",(c8*)PY_mb_jing}, +{"5826","juan",(c8*)PY_mb_juan}, +{"5264","kang",(c8*)PY_mb_kang}, +{"5364","keng",(c8*)PY_mb_keng}, +{"5664","kong",(c8*)PY_mb_kong}, +{"5824","kuai",(c8*)PY_mb_kuai}, +{"5826","kuan",(c8*)PY_mb_kuan}, +{"5264","lang",(c8*)PY_mb_lang}, +{"5366","leng",(c8*)PY_mb_leng}, +{"5426","lian",(c8*)PY_mb_lian}, +{"5426","liao",(c8*)PY_mb_liao}, +{"5464","ling",(c8*)PY_mb_ling}, +{"5664","long",(c8*)PY_mb_long}, +{"5826","luan",(c8*)PY_mb_luan}, +{"6264","mang",(c8*)PY_mb_mang}, +{"6364","meng",(c8*)PY_mb_meng}, +{"6426","mian",(c8*)PY_mb_mian}, +{"6426","miao",(c8*)PY_mb_miao}, +{"6464","ming",(c8*)PY_mb_ming}, +{"6264","nang",(c8*)PY_mb_nang}, +{"6364","neng",(c8*)PY_mb_neng}, +{"6426","nian",(c8*)PY_mb_nian}, +{"6426","niao",(c8*)PY_mb_niao}, +{"6464","ning",(c8*)PY_mb_ning}, +{"6664","nong",(c8*)PY_mb_nong}, +{"6826","nuan",(c8*)PY_mb_nuan}, +{"7264","pang",(c8*)PY_mb_pang}, +{"7364","peng",(c8*)PY_mb_peng}, +{"7426","pian",(c8*)PY_mb_pian}, +{"7426","piao",(c8*)PY_mb_piao}, +{"7464","ping",(c8*)PY_mb_ping}, +{"7426","qian",(c8*)PY_mb_qian}, +{"7426","qiao",(c8*)PY_mb_qiao}, +{"7464","qing",(c8*)PY_mb_qing}, +{"7826","quan",(c8*)PY_mb_quan}, +{"7264","rang",(c8*)PY_mb_rang}, +{"7364","reng",(c8*)PY_mb_reng}, +{"7664","rong",(c8*)PY_mb_rong}, +{"7826","ruan",(c8*)PY_mb_ruan}, +{"7264","sang",(c8*)PY_mb_sang}, +{"7364","seng",(c8*)PY_mb_seng}, +{"7424","shai",(c8*)PY_mb_shai}, +{"7426","shan",(c8*)PY_mb_shan}, +{"7426","shao",(c8*)PY_mb_shao}, +{"7434","shei",(c8*)PY_mb_shei}, +{"7436","shen",(c8*)PY_mb_shen}, +{"7468","shou",(c8*)PY_mb_shou}, +{"7482","shua",(c8*)PY_mb_shua}, +{"7484","shui",(c8*)PY_mb_shui}, +{"7486","shun",(c8*)PY_mb_shun}, +{"7486","shuo",(c8*)PY_mb_shuo}, +{"7664","song",(c8*)PY_mb_song}, +{"7826","suan",(c8*)PY_mb_suan}, +{"8264","tang",(c8*)PY_mb_tang}, +{"8364","teng",(c8*)PY_mb_teng}, +{"8426","tian",(c8*)PY_mb_tian}, +{"8426","tiao",(c8*)PY_mb_tiao}, +{"8464","ting",(c8*)PY_mb_ting}, +{"8664","tong",(c8*)PY_mb_tong}, +{"8826","tuan",(c8*)PY_mb_tuan}, +{"9264","wang",(c8*)PY_mb_wang}, +{"9364","weng",(c8*)PY_mb_weng}, +{"9426","xian",(c8*)PY_mb_xian}, +{"9426","xiao",(c8*)PY_mb_xiao}, +{"9464","xing",(c8*)PY_mb_xing}, +{"9826","xuan",(c8*)PY_mb_xuan}, +{"9264","yang",(c8*)PY_mb_yang}, +{"9464","ying",(c8*)PY_mb_ying}, +{"9664","yong",(c8*)PY_mb_yong}, +{"9826","yuan",(c8*)PY_mb_yuan}, +{"9264","zang",(c8*)PY_mb_zang}, +{"9364","zeng",(c8*)PY_mb_zeng}, +{"9424","zhai",(c8*)PY_mb_zhai}, +{"9426","zhan",(c8*)PY_mb_zhan}, +{"9426","zhao",(c8*)PY_mb_zhao}, +{"9436","zhen",(c8*)PY_mb_zhen}, +{"9468","zhou",(c8*)PY_mb_zhou}, +{"9482","zhua",(c8*)PY_mb_zhua}, +{"9484","zhui",(c8*)PY_mb_zhui}, +{"9486","zhun",(c8*)PY_mb_zhun}, +{"9486","zhuo",(c8*)PY_mb_zhuo}, +{"9664","zong",(c8*)PY_mb_zong}, +{"9826","zuan",(c8*)PY_mb_zuan}, +{"24264","chang",(c8*)PY_mb_chang}, +{"24364","cheng",(c8*)PY_mb_cheng}, +{"24664","chong",(c8*)PY_mb_chong}, +{"24826","chuan",(c8*)PY_mb_chuan}, +{"48264","guang",(c8*)PY_mb_guang}, +{"48264","huang",(c8*)PY_mb_huang}, +{"54264","jiang",(c8*)PY_mb_jiang}, +{"54664","jiong",(c8*)PY_mb_jiong}, +{"58264","kuang",(c8*)PY_mb_kuang}, +{"54264","liang",(c8*)PY_mb_liang}, +{"64264","niang",(c8*)PY_mb_niang}, +{"74264","qiang",(c8*)PY_mb_qiang}, +{"74664","qiong",(c8*)PY_mb_qiong}, +{"74264","shang ",(c8*)PY_mb_shang}, +{"74364","sheng",(c8*)PY_mb_sheng}, +{"74824","shuai",(c8*)PY_mb_shuai}, +{"74826","shuan",(c8*)PY_mb_shuan}, +{"94264","xiang",(c8*)PY_mb_xiang}, +{"94664","xiong",(c8*)PY_mb_xiong}, +{"94264","zhang",(c8*)PY_mb_zhang}, +{"94364","zheng",(c8*)PY_mb_zheng}, +{"94664","zhong",(c8*)PY_mb_zhong}, +{"94824","zhuai",(c8*)PY_mb_zhuai}, +{"94826","zhuan",(c8*)PY_mb_zhuan}, +{"248264","chuang",(c8*)PY_mb_chuang}, +{"748264","shuang",(c8*)PY_mb_shuang}, +{"948264","zhuang",(c8*)PY_mb_zhuang}, +}; + + +void TPinyinT9::Init() +{ + int i; + InxCount = sizeof(py_index3)/sizeof(py_index3[0]);//得到py索引表的大小. + + for(i=0; i<12; i++){ + InputStr.Num[i] = 0; + } +} + +//比较两个字符串的匹配情况 +//返回值:0xff,表示完全匹配. +//其他,匹配的字符数 +int TPinyinT9::TryGetMatch(int aInx) +{ + int i=0; + if(aInx>InxCount)return -1; + while(1){ + if(InputStr.Num[i] != py_index3[aInx].py_input[i]){ + if(InputStr.Num[i] != '\0'){ + i = 0; + } + break;//部分匹配 + } + if(InputStr.Num[i] == '\0'){ + if(i>0)i = 0xFF;//完全匹配 + break; + } + i++; + } + return i;//两个字符串相等 +} + +//获取匹配的拼音码表 +//*strin,输入的字符串,形如:"726" +//**matchlist,输出的匹配表. +//返回值:[7],0,表示完全匹配；1，表示部分匹配（仅在没有完全匹配的时候才会出现） +//[6:0],完全匹配的时候，表示完全匹配的拼音个数 +//部分匹配的时候，表示有效匹配的位数 +int TPinyinT9::GetMatchedPinyinCode(void) +{ + int alen=0; + int i=0; + int mGot =0; + alen = sizeof(py_index3) / sizeof(py_index3[0]); + + CnResult.FullMatch.Count = 0; + CnResult.PartMatch.Count = 0; + CnResult.Count = 0; + for(i=0; i= MAX_MATCH_PYMB ) && (CnResult.PartMatch.Count >= MAX_MATCH_PYMB) ){ + break; + } + } + } + for(i =0; i 9)break; + CnResult.Index[CnResult.Count] = CnResult.FullMatch.Index[i]; + //CnResult.Match.Type[CnResult.Match.Count] = 0xFF; + CnResult.Count++; + } + for(i = 0; i 9)break; + CnResult.Index[CnResult.Count] = CnResult.PartMatch.Index[i]; + CnResult.Count++; + } + + return CnResult.Count; +} + +const char * TPinyinT9::GetPinyin(int Index) +{ + const char *Rest; + int aInx; + aInx = CnResult.Index[Index]; + Rest = py_index3[aInx].py; + return Rest; +} + +void TPinyinT9::IdentifyCn(int Index) +{ + int i, aInx, Cnt; + Cnt = 0; + if(Index < CnResult.Count){ + aInx = CnResult.Index[Index]; + for(i=0; i<256; i++){ + if(py_index3[aInx].pymb[i] != '\0'){ + Cnt++; + }else{ + break; + } + } + CnResult.pCn = py_index3[aInx].pymb; + } + CnResult.CnCount = Cnt / 2; + CnResult.CnPageCount = CnResult.CnCount / 10 + 1; +} + +const char * TPinyinT9::TryGetCn(int iInx, int cInx) +{ + if(iInx < InxCount){ + return &py_index3[iInx].pymb[cInx * 2]; + }else{ + return nullptr; + } +} + + + + + + + + + + + + + + + diff --git a/MyCode/src/PinyinT9.h b/MyCode/src/PinyinT9.h new file mode 100644 index 0000000..108af23 --- /dev/null +++ b/MyCode/src/PinyinT9.h @@ -0,0 +1,54 @@ +#ifndef PINYINT9_H_ +#define PINYINT9_H_ + +#include "gType.h" + +#define MAX_MATCH_PYMB 10 //最大匹配数 +#define MAX_Cn_Len 256 + +class TPinyinT9{ + public: + int InxCount ; + struct{ + char Num[12]; + }InputStr; + struct{ + int Count; + int CnCount; + int CnPageCount; + int Index[MAX_MATCH_PYMB]; + struct{ + int Count; + int Index[MAX_MATCH_PYMB]; + }FullMatch,PartMatch; + const char *pCn; + }CnResult; + public: + TPinyinT9(){}; + void Init(); + + int TryGetMatch(int aInx); + int GetMatchedPinyinCode(void); + const char *GetPinyin(int Index); + void IdentifyCn(int Index); + const char * TryGetCn(int iInx, int cInx); +}; + + + + + + + + + + + + + + + + + + +#endif diff --git a/MyCode/src/Proto2Proto.cpp b/MyCode/src/Proto2Proto.cpp new file mode 100644 index 0000000..ea64a86 --- /dev/null +++ b/MyCode/src/Proto2Proto.cpp @@ -0,0 +1,34 @@ +#include "Proto2Proto.h" + +const unsigned short Inner2FecMappingTable[256] = { + + + + + + + +}; + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/Proto2Proto.h b/MyCode/src/Proto2Proto.h new file mode 100644 index 0000000..02559d2 --- /dev/null +++ b/MyCode/src/Proto2Proto.h @@ -0,0 +1,35 @@ +#ifndef PROTO2PROTO_H_ +#define PROTO2PROTO_H_ + +#include "ProtoInnerCan.h" +#include "ProtoFecBus.h" + +class TProto2Proto{ + public: + + + + public: + static TFecDevTypeCode dType2fecType(unsigned char dT); + static TFecEventCode evt2fecEvent(unsigned char aEvt); +}; + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/ProtoC2C.cpp b/MyCode/src/ProtoC2C.cpp new file mode 100644 index 0000000..f7c5f56 --- /dev/null +++ b/MyCode/src/ProtoC2C.cpp @@ -0,0 +1,2854 @@ +#include "ProtoInnerCan.h" +#include "ProtoC2C.h" + +#include "CnCpp.h" +#include "record.h" +#include "Runtime.h" +#include "server.h" +#include "Gui.h" + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" +} + +unsigned int TProtoC2C::DevDelayStartTick; + +void TProtoC2C::Init() +{ + unsigned int i,x; + NeedReply = 0; + ErrReport = 0; + ErrHasReport =0; + iBufInCount = 0; + iBufInCountPer2Sec = 0; + + iBuf.ReadIndex = 0; + iBuf.WriteIndex = 0; + oBuf.ReadIndex = 0; + oBuf.WriteIndex = 0; + + oEntryBasicService.Reset(); + oEntryFire.Reset(); + oEntrySv.Reset(); + oEntryLink.Reset(); + oEntryFault.Reset(); + oEntryNormal.Reset(); + + CheckOnlineHasStart = 0; + CheckOnlineUpdateTick = 0; + SlaveOnlineListOld[0] = 1; + for(i=1; i<=dNETWORK_MACHINE_COUNT; i++)SlaveOnlineListOld[i] = 1; + + for(i=0; i= dNetworkInBufMaxLength)iBuf.WriteIndex = 0; + RxMsg.D32[0] = iBuf.Body[iBuf.WriteIndex].D32[0]; + RxMsg.D32[1] = iBuf.Body[iBuf.WriteIndex].D32[1]; + RxMsg.D32[2] = iBuf.Body[iBuf.WriteIndex].D32[2]; + RxMsg.D32[3] = iBuf.Body[iBuf.WriteIndex].D32[3]; +} + +void TProtoC2C::iBufProcess() +{ + if(iBuf.ReadIndex != iBuf.WriteIndex){ + iBuf.ReadIndex++; + if(iBuf.ReadIndex >= dNetworkInBufMaxLength)iBuf.ReadIndex = 0; + RxMsg.D32[0] = iBuf.Body[iBuf.ReadIndex].D32[0]; + RxMsg.D32[1] = iBuf.Body[iBuf.ReadIndex].D32[1]; + RxMsg.D32[2] = iBuf.Body[iBuf.ReadIndex].D32[2]; + RxMsg.D32[3] = iBuf.Body[iBuf.ReadIndex].D32[3]; + if(RxMsg.Data.Routing == 0){ + if(MainCtl.fData.Split.NetworkMode == 1){ + MasterRxMsgProcess(); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + SlaveRxMsgProcess(); + } + }else + if(RxMsg.Data.Routing == 1){ + //Master To Master M2M + + }else{ + // undefine + + } + } +} + +void TProtoC2C::MasterRxMsgProcess() +{ + unsigned char aCmd, aCtlNum, CtlByte, aEventType, NewOrder, tForceIdf; + int i,HasPrc = 0; + unsigned int aAddr,AllDataOK; + unsigned int aDl, aDL2; + + aCtlNum = RxMsg.Data.Data[1]; + if( (aCtlNum==0) || (aCtlNum >dNETWORK_MACHINE_COUNT) )return; + if( (aCtlNum >= CtlMask.StartNum) && (aCtlNum <= CtlMask.EndNum) ) return; + + aCmd = RxMsg.Data.Cmd; + tForceIdf = RxMsg.Data.Identification; + + if(aCmd == dNetworkCmd_Ack){ + if(CheckIsInSlaveList(aCtlNum)){ + ProcessAckRecFromSlave(RxMsg.Data.Order, RxMsg.Data.Data); + } + return; + } + + if(aCmd == dNetworkCmd){ + if(1){ + NwSubCmd = RxMsg.Data.Data[2]; + switch(NwSubCmd){ + case CmdC2C_AskExist: + HasPrc =1; + break; + case CmdC2C_AskType: + HasPrc =1; + if(RxMsg.Data.Data[3] == MainCtl.fData.Split.MyNum){ + ReplyCtrlType(); + } + break; + case CmdC2C_AskNameLen: + HasPrc =1; + break; + case CmdC2C_AskNameContent: + HasPrc =1; + if(RxMsg.Data.Data[3] == MainCtl.fData.Split.MyNum){ + ReplyDescp(); + } + break; + } + if(HasPrc == 0){ + switch(NwSubCmd){ + case CmdC2C_RpyExist: + case CmdC2C_RpyType: + case CmdC2C_RpyNameLen: + case CmdC2C_RpyNameContent: + HasPrc =1; + if(CanNetworkRegister.IsOnSearching){ + CanNetworkRegister.PushfNetMsg(NwSubCmd, RxMsg.Data.Data, 8); + } + //if(fNetworkRegManual.IsShowing){ + // fNetworkRegManual.PushfNetMsg(NwSubCmd, RxMsg.Data.Data, 8); + //} + break; + case CmdC2C_SaveMasterList: + HasPrc =1; + SaveM2MCfgData(RxMsg.Data.Data); + break; + case CmdC2C_ClearMasterList: + HasPrc =1; + ClearM2MCfgData(RxMsg.Data.Data); + break; + } + } + if(HasPrc == 0){ + //Master + if(CheckIsInSlaveList(aCtlNum)){ + if(Register.IsOnShow && Register.IsOnGo && Register.IsOnNetwork && (Register.Nw.CtlNum == aCtlNum)){ + switch(NwSubCmd){ + case CmdC2C_DevRegRpyStart: + Register.Nw.SlaveState =RxMsg.Data.Data[3]; + if(Register.Nw.SlaveState == 1)Register.Nw.PortCountHasUpdate =1; + break; + case CmdC2C_DevRegRpyPortCnt: + if(RxMsg.Data.Data[3] <= 40){ + Register.MasterCanNetGetPortCount(RxMsg.Data.Data[3]); + } + break; + case CmdC2C_DevRegRpyProgress: + if(RxMsg.Data.Data[3] <= 100){ + Register.MasterCanNetGetProgressVal(RxMsg.Data.Data[3]); + } + break; + case CmdC2C_DevRegRpyEpCount: + Register.MasterCanNetGetEpCount(RxMsg.Data.Data[3], RxMsg.Data.Data[4], RxMsg.Data.Data[5]); + break; + case CmdC2C_DevRegRpyEpCompleted: + Register.MasterCanNetGetEpCountFinished(); + break; + + } + } + } + } + } + return; + }else + if(aCmd == dNetworkCmd_ReqDateTime){ + if(CheckIsInSlaveList(aCtlNum)){ + DateTimeSet(); + } + }else + if(aCmd == dNetworkCmd_PortExistRpy){ + fNetworkReg.PortExistGet(RxMsg.Data.Data[1], RxMsg.Data.Data[2], RxMsg.Data.Data[3]); + }else + if(aCmd == dNetworkCmd_DescpRpy){ + fNetworkReg.DescpListGet(RxMsg.Data.Data[1], RxMsg.Data.Data[2], RxMsg.Data.Data[3], RxMsg.Data.Data); + }else + if(aCmd == dNetworkCmd_CheckNormalData){ + + } + + if(0 == CheckIsInSlaveList(aCtlNum))return; + + NewOrder = RxMsg.Data.Order; + if(tForceIdf)OnReceive.IsProcessDone[aCtlNum] = 0; + if(OnReceive.OrderLast[aCtlNum] != NewOrder)OnReceive.IsProcessDone[aCtlNum] = 0; + if( OnReceive.IsProcessDone[aCtlNum] && (OnReceive.OrderAck[aCtlNum] == NewOrder ) ){ + Ack(aCtlNum, NewOrder); + return; + } + OnReceive.OrderLast[aCtlNum] = NewOrder; + + if(CmdActiveDefaultSet[aCmd][6] == FastCall){ + aCtlNum = RxMsg.Data.Data[1]; + if( (aCtlNum !=0) && (aCtlNum <=dNETWORK_MACHINE_COUNT)){ + if(1){ + AllDataOK = 0; + + Record.iMsgRx.Splite.Year = RecDateTime[aCtlNum].Dt.Year; + Record.iMsgRx.Splite.Month = RecDateTime[aCtlNum].Dt.Mon; + Record.iMsgRx.Splite.Day = RecDateTime[aCtlNum].Dt.Day; + Record.iMsgRx.Splite.Hour = RecDateTime[aCtlNum].Dt.Hour; + Record.iMsgRx.Splite.Minute = RecDateTime[aCtlNum].Dt.Min; + Record.iMsgRx.Splite.Second = RecDateTime[aCtlNum].Dt.Sec; + + Record.InnerMsgSet_mType (0, CmdActiveDefaultSet[aCmd][7]); + Record.InnerMsgSet_CtlNum (0, RxMsg.Data.Data[1]); + Record.InnerMsgSet_P0 (0, RxMsg.Data.Data[2]); + Record.InnerMsgSet_P1 (0, RxMsg.Data.Data[3]); + Record.InnerMsgSet_P2 (0, RxMsg.Data.Data[4]); + Record.InnerMsgSet_dType (0, RxMsg.Data.Data[5]); + Record.InnerMsgSet_Data0 (0, 0); + Record.InnerMsgSet_Data1 (0, 0); + Record.InnerMsgSet_iByte0 (0, CmdActiveDefaultSet[aCmd][8]); + Record.InnerMsgSet_iByte1 (0, 0); + + if(OnReceive.Piece[aCtlNum] && (OnReceive.OrderDt[aCtlNum] == NewOrder) ){ + if(aCmd == cmCircuitErr){ + Record.InnerMsgSet_P0 (0,RxMsg.Data.Data[2]); //Cir Index + Record.InnerMsgSet_P1 (0,0); + Record.InnerMsgSet_P2 (0,0); + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,0); + Record.InnerMsgSet_Data1 (0, RxMsg.Data.Data[7]); //Is Set=1 Recover=0 + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aCmd][8]); + CtlCenter.iePushOneMsg(Record.iMsgRx, aCmd); + AllDataOK = 1; + }else + if(aCmd == cmOtherErr){ + Record.InnerMsgSet_P2 (0,RxMsg.Data.Data[6]); + Record.InnerMsgSet_Data0 (0,RxMsg.Data.Data[6]); //Fault Type + Record.InnerMsgSet_Data1 (0,RxMsg.Data.Data[7]); //Is Set=1 Recover=0 + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aCmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + CtlCenter.iePushOneMsg(Record.iMsgRx, aCmd); + AllDataOK = 1; + }else + if(aCmd == cmVAAlramStart){ + if(RxMsg.Data.Data[0] == 0){ + if(OnReceive.Piece[aCtlNum]){ + Record.OperateAdd_AlramSoundOn(RxMsg.Data.Data[1], &RxMsg.Data.Data[2]); + AllDataOK = 1; + } + } + }else + if(aCmd == cmVAAlramStop){ + if(RxMsg.Data.Data[0] == 0){ + if(OnReceive.Piece[aCtlNum]){ + Record.OperateAdd_AlramSoundOff(RxMsg.Data.Data[1], &RxMsg.Data.Data[2]); + AllDataOK = 1; + } + } + }else + if(aCmd == cmPortModuleErr){ + Record.InnerMsgSet_P0 (0,RxMsg.Data.Data[2]); + Record.InnerMsgSet_P1 (0,RxMsg.Data.Data[3]); + Record.InnerMsgSet_P2 (0,RxMsg.Data.Data[4]); + Record.InnerMsgSet_dType (0,RxMsg.Data.Data[5]); + Record.InnerMsgSet_Data0 (0,RxMsg.Data.Data[4]); //Fault Type + Record.InnerMsgSet_Data1 (0,0x01); //Set + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aCmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + + RecUserCodeAreaNum[aCtlNum].UC.Bytes[1] = RxMsg.Data.Data[0]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[2] = RxMsg.Data.Data[6]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[3] = RxMsg.Data.Data[7]; + Record.iMsgRx.Splite.UserCode = RecUserCodeAreaNum[aCtlNum].UC.Full; + Record.iMsgRx.Splite.AreaNum = RecUserCodeAreaNum[aCtlNum].AN.Full; + + CtlCenter.iePushOneMsg(Record.iMsgRx, aCmd); + AllDataOK = 1; + }else + if(aCmd == cmPortModuleErrRecover){ + Record.InnerMsgSet_P0 (0,RxMsg.Data.Data[2]); + Record.InnerMsgSet_P1 (0,RxMsg.Data.Data[3]); + Record.InnerMsgSet_P2 (0,RxMsg.Data.Data[4]); + Record.InnerMsgSet_dType (0,RxMsg.Data.Data[5]); + Record.InnerMsgSet_Data0 (0,RxMsg.Data.Data[4]); //Fault Type + Record.InnerMsgSet_Data1 (0,0x00); //Recover + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aCmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + RecUserCodeAreaNum[aCtlNum].UC.Bytes[1] = RxMsg.Data.Data[0]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[2] = RxMsg.Data.Data[6]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[3] = RxMsg.Data.Data[7]; + Record.iMsgRx.Splite.UserCode = RecUserCodeAreaNum[aCtlNum].UC.Full; + Record.iMsgRx.Splite.AreaNum = RecUserCodeAreaNum[aCtlNum].AN.Full; + CtlCenter.iePushOneMsg(Record.iMsgRx, aCmd); + AllDataOK = 1; + }else{ + RecUserCodeAreaNum[aCtlNum].UC.Bytes[1] = RxMsg.Data.Data[0]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[2] = RxMsg.Data.Data[6]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[3] = RxMsg.Data.Data[7]; + + switch(aCmd){ + case cmAutoStart: + case cmAutoStop: + case dNetworkCmd_AutoStartDelay: + case cmAck: + case cmAckStop: + //aDL2 |= ((RxMsg.Data.Idf >> 4) & 0x0F); + //aDL2 <<= 8; + //aDL2 |= RxMsg.Data.Data[4]; + sIm.Splite.Year = ProtoC2C.RecDateTime[RxMsg.Data.Data[1]].Dt.Year; + sIm.Splite.Month = ProtoC2C.RecDateTime[RxMsg.Data.Data[1]].Dt.Mon; + sIm.Splite.Day = ProtoC2C.RecDateTime[RxMsg.Data.Data[1]].Dt.Day; + sIm.Splite.Hour = ProtoC2C.RecDateTime[RxMsg.Data.Data[1]].Dt.Hour; + sIm.Splite.Minute = ProtoC2C.RecDateTime[RxMsg.Data.Data[1]].Dt.Min; + sIm.Splite.Second = ProtoC2C.RecDateTime[RxMsg.Data.Data[1]].Dt.Sec; + + sIm.Splite.PCtlNum = RxMsg.Data.Data[1]; + sIm.Splite.P0 = RxMsg.Data.Data[2]; + sIm.Splite.P1 = RxMsg.Data.Data[3]; + sIm.Splite.P2 = 0; + sIm.Splite.dType = RxMsg.Data.Data[5]; + + sIm.Splite.UserCode = RecUserCodeAreaNum[aCtlNum].UC.Full; + + if(RxMsg.Data.Data[2] == 0){ + + }else + if(RxMsg.Data.Data[2] <= dPORT_MAX_COUNT){ + MasterDoEpMsg(aCmd, RxMsg.Data.Data); + }else + if( (RxMsg.Data.Data[2] >= dADDR_DIRECTPAD_START) && (RxMsg.Data.Data[2] <= dADDR_DIRECTPAD_END) ){ + MasterDoDirectPadNwPutLnkState(aCmd, RxMsg.Data.Data); + } + break; + default: + Record.InnerMsgSet_P0 (0,RxMsg.Data.Data[2]); + Record.InnerMsgSet_P1 (0,RxMsg.Data.Data[3]); + Record.InnerMsgSet_P2 (0,0); + Record.InnerMsgSet_dType (0,RxMsg.Data.Data[5]); + Record.InnerMsgSet_Data0 (0,RxMsg.Data.Data[6]); + Record.InnerMsgSet_Data1 (0,RxMsg.Data.Data[7]); + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aCmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + + RecUserCodeAreaNum[aCtlNum].AN.Full = RxMsg.Data.CarryByte; + RecUserCodeAreaNum[aCtlNum].AN.Full <<= 6; + RecUserCodeAreaNum[aCtlNum].AN.Full |= RxMsg.Data.Data[4]; + + Record.iMsgRx.Splite.UserCode = RecUserCodeAreaNum[aCtlNum].UC.Full; + Record.iMsgRx.Splite.AreaNum = RecUserCodeAreaNum[aCtlNum].AN.Full; + CtlCenter.iePushOneMsg(Record.iMsgRx, aCmd); + break; + } + AllDataOK = 1; + } + } + + if(AllDataOK){ + Ack(aCtlNum, NewOrder); + } + } + } + }else + if(CmdActiveDefaultSet[aCmd][6] == StdCall){ + /*if(aCmd == cmReset){ + if(RxMsg.Data.Data[0] == 0){ + if(OnReceive.Piece[aCtlNum]){ + Record.OperateAdd_Reset(RxMsg.Data.Data[1], &RxMsg.Data.Data[2]); + CtlCenter.NwMachineStateClear(RxMsg.Data.Data[1]); + CtlCenter.NwMachineMsgFireClear(RxMsg.Data.Data[1]); + CtlCenter.NwMachineMsgLinkageClear(RxMsg.Data.Data[1]); + //CtlCenter.NwMachineMsgSvClear(RxMsg.Data.Data[1]); + CtlCenter.NwMachineMsgFaultClear(RxMsg.Data.Data[1]); + OnReceive.IsProcessDone[aCtlNum] = 1; + Ack(aCtlNum, OnReceive.ProcessingOrder[aCtlNum]); + } + } + }else + if(aCmd == cmMuteBell){ + if(RxMsg.Data.Data[0] == 0){ + if(OnReceive.Piece[aCtlNum]){ + Record.OperateAdd_Mute(RxMsg.Data.Data[1], &RxMsg.Data.Data[2]); + OnReceive.IsProcessDone[aCtlNum] = 1; + Ack(aCtlNum, OnReceive.ProcessingOrder[aCtlNum]); + } + } + }*/ + if(aCmd == dNetworkCmd_MaskListSend){ + if(OnReceive.Piece[aCtlNum] && (OnReceive.OrderDt[aCtlNum] == NewOrder) ){ + MasterDoMaskListGet(RxMsg.Data.Data); + Ack(aCtlNum, NewOrder); + } + }else + if(aCmd == dNetworkCmd_DelayStartSend){ + if(RxMsg.Data.Data[2]){ + NwIsStartDelay |= 1 << aCtlNum; + }else{ + NwIsStartDelay &= ~(1 << aCtlNum); + } + Ack(aCtlNum, NewOrder); + }else + if(aCmd == dNetworkCmd_SlaveFbMissReport){ + if(RxMsg.Data.Data[2]){ + NwIsFbMiss |= 1<< RxMsg.Data.Data[1]; + }else{ + NwIsFbMiss &= ~(1<< RxMsg.Data.Data[1]); + } + Ack(aCtlNum, NewOrder); + }else + if(aCmd == dNetworkCmd_CheckNormalData){ + Ack(aCtlNum, NewOrder); + MasterGetCheckNormalData(RxMsg.Data.Data); + } + }else + if(CmdActiveDefaultSet[aCmd][6] == NetNormalCall){ + if(aCmd == dNetworkCmd_PublishOperate){ + if(OnReceive.Piece[aCtlNum] && (OnReceive.OrderDt[aCtlNum] == NewOrder) ){ + if(RxMsg.Data.Data[6] == otCfgDateTime){ + if( (OnReceive.Piece[aCtlNum] == 0x03) && (OnReceive.OrderNewDt[aCtlNum] == NewOrder) ){ + OperateGet(aCmd,RxMsg.Data.Data); + Ack(aCtlNum, NewOrder); + } + }else{ + OperateGet(aCmd,RxMsg.Data.Data); + Ack(aCtlNum, NewOrder); + } + } + }else + if(aCmd == dNetworkCmd_EventTime){ + OnReceive.OrderDt[aCtlNum] = NewOrder; + RecDateTime[aCtlNum].D32[0] = RxMsg.D32[2]; + RecDateTime[aCtlNum].D32[1] = RxMsg.D32[3]; + RecDateTime[aCtlNum].D32[2] = 1; + RecUserCodeAreaNum[aCtlNum].AN.Full = RxMsg.Data.CarryByte; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[0] = RxMsg.Data.Data[0]; + OnReceive.Piece[aCtlNum] |= 0x01; + }else + if(aCmd == dNetworkCmd_NewTime){ + OnReceive.OrderNewDt[aCtlNum] = NewOrder; + RecNewDateTime[aCtlNum].D32[0] = RxMsg.D32[2]; + RecNewDateTime[aCtlNum].D32[1] = RxMsg.D32[3]; + RecNewDateTime[aCtlNum].D32[2] = 1; + OnReceive.Piece[aCtlNum] |= 0x02; + }else + if(aCmd == dNetworkCmd_DevDescp){ + //ProcessDevDescpRec(); + } + }else + if(CmdActiveDefaultSet[aCmd][6] == SimEvent){ + if(OnReceive.Piece[aCtlNum] && (OnReceive.OrderDt[aCtlNum] == NewOrder) ){ + sIm.Splite.Year = RecDateTime[aCtlNum].Dt.Year; + sIm.Splite.Month = RecDateTime[aCtlNum].Dt.Mon; + sIm.Splite.Day = RecDateTime[aCtlNum].Dt.Day; + sIm.Splite.Hour = RecDateTime[aCtlNum].Dt.Hour; + sIm.Splite.Minute = RecDateTime[aCtlNum].Dt.Min; + sIm.Splite.Second = RecDateTime[aCtlNum].Dt.Sec; + + sIm.Splite.mType = CmdActiveDefaultSet[aCmd][7]; + sIm.Splite.iByte0 = CmdActiveDefaultSet[aCmd][8]; + + sIm.Splite.PCtlNum = RxMsg.Data.Data[1]; + sIm.Splite.P0 = RxMsg.Data.Data[2]; + sIm.Splite.P1 = RxMsg.Data.Data[3]; + sIm.Splite.P2 = 0; + sIm.Splite.dType = RxMsg.Data.Data[5]; + + RecUserCodeAreaNum[aCtlNum].UC.Bytes[1] = RxMsg.Data.Data[0]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[2] = RxMsg.Data.Data[6]; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[3] = RxMsg.Data.Data[7]; + + RecUserCodeAreaNum[aCtlNum].AN.Full = RxMsg.Data.CarryByte; + RecUserCodeAreaNum[aCtlNum].AN.Full <<= 6; + RecUserCodeAreaNum[aCtlNum].AN.Full |= RxMsg.Data.Data[4]; + + sIm.Splite.UserCode = RecUserCodeAreaNum[aCtlNum].UC.Full; + Record.iMsgRx.Splite.AreaNum = RecUserCodeAreaNum[aCtlNum].AN.Full; + + + switch(aCmd){ + case cmVIrtualStart: + TControlCenter::sSimStartGot(&sIm); + break; + case smVIrtualStop: + TControlCenter::sSimStartCancelGot(&sIm); + break; + case cmVIrtualAck: + TControlCenter::sSimFeedBackGot(&sIm); + break; + case cmVIrtualAckStop: + + break; + case cmVIrtualAlram: + TControlCenter::sSimFireGot(&sIm); + break; + case cmVIrtualSuperVi: + TControlCenter::sSimSvGot(&sIm); + break; + case dNetworkCmd_AutoStartDelaySimulate: + unsigned short aDl; + aDl = RxMsg.Data.CarryByte & 0x0F; + aDl &= 0x000F; + aDl <<= 8; + aDl |= RxMsg.Data.Data[4]; + sSimGetStartDelay(&sIm, aDl); + break; + } + Ack(aCtlNum, NewOrder); + } + } +} + +void TProtoC2C::SlaveRxMsgProcess() +{ + unsigned char aCmd, aCtlNum, CtlByte, aEventType, NewOrder, tForceIdf; + int i,HasPrc = 0; + unsigned int aAddr; + TDMix DMix; + + aCtlNum = RxMsg.Data.Data[1]; + if( (aCtlNum==0) || (aCtlNum >32) )return; + if( (aCtlNum >= CtlMask.StartNum) && (aCtlNum <= CtlMask.EndNum) ) return; + + + aCmd = RxMsg.Data.Cmd; + tForceIdf = RxMsg.Data.Identification; + + if(aCmd == dNetworkCmd_Ack){ + if(aCtlNum == MasterNum){ + if(CheckIsInSlaveList(MainCtl.fData.Split.MyNum)){ + ProcessAckRecFromMaster(RxMsg.Data.Order, RxMsg.Data.Data); + } + } + return; + } + + if(aCmd == dNetworkCmd){ + if(1){ + NwSubCmd = RxMsg.Data.Data[2]; + switch(NwSubCmd){ + case CmdC2C_AskExist: + HasPrc =1; + break; + case CmdC2C_AskType: + HasPrc =1; + if(RxMsg.Data.Data[3] == MainCtl.fData.Split.MyNum){ + ReplyCtrlType(); + } + break; + case CmdC2C_AskNameLen: + HasPrc =1; + break; + case CmdC2C_AskNameContent: + HasPrc =1; + if(RxMsg.Data.Data[3] == MainCtl.fData.Split.MyNum){ + ReplyDescp(); + } + break; + } + if(HasPrc == 0){ + switch(NwSubCmd){ + case CmdC2C_RpyExist: + case CmdC2C_RpyType: + case CmdC2C_RpyNameLen: + case CmdC2C_RpyNameContent: + HasPrc =1; + if(CanNetworkRegister.IsOnSearching){ + CanNetworkRegister.PushfNetMsg(NwSubCmd, RxMsg.Data.Data, 8); + } + break; + case CmdC2C_SaveData: + HasPrc =1; + SaveCfgData(RxMsg.Data.Data); + break; + case CmdC2C_ClearReg: + HasPrc =1; + ClearCfgData(RxMsg.Data.Data); + break; + } + } + if(HasPrc == 0){ + //Slave + if(aCtlNum == MasterNum){ + if(CheckIsInSlaveList(MainCtl.fData.Split.MyNum)){ + if(RxMsg.Data.Data[3] == MainCtl.fData.Split.MyNum){ + switch(NwSubCmd){ + case CmdC2C_DevRegStartSeq: + CtlByte = Register.SlaveGetStartSeq(RxMsg.Data.Data); + if(CtlByte <=dPORT_MAX_COUNT){ + int Res = CheckIsRemoteRegFeasible(); + if(1 == Res){ + RemoteReq.Reg.RegPath = CtlByte; + RemoteReq.Reg.IsRequsting =1; + }else + if(-1 == Res){ + Register.SlaveReplyStartState(3); + }else{ + Register.SlaveReplyStartState(2); + } + }else + if(CtlByte == 254){ + Register.SlaveReplyStartState(2); + } + break; + case CmdC2C_DevRegReqEpCount: + Register.SlaveRpyEpCount(); + break; + case CmdC2C_DevRegEpCountCorrect: + Register.SlaveRecMasterGotCompleted(); + break; + + } + } + } + } + } + } + return; + }else + if(aCmd == dNetworkCmd_SetDateTime){ + //Record.OperateAdd_GetDateTime(RxMsg.Data.Data[2], RxMsg.Data.Data[3], RxMsg.Data.Data[4], RxMsg.Data.Data[5], RxMsg.Data.Data[6] ,RxMsg.Data.Data[7]); + //DataTimeSet(RxMsg.Data.Data[2], RxMsg.Data.Data[3], RxMsg.Data.Data[4], RxMsg.Data.Data[5], RxMsg.Data.Data[6] ,RxMsg.Data.Data[7], 1); //aWk 1..7 + }else + if(aCmd == dNetworkCmd_PortExistAsk){ + PortExistRpy(RxMsg.Data.Data[1], RxMsg.Data.Data[2]); + }else + if(aCmd == dNetworkCmd_DescpAsk){ + if(RxMsg.Data.Data[4]){ + if(RxMsg.Data.Data[2] < 41) + DescpListRpy(RxMsg.Data.Data[1], RxMsg.Data.Data[2], RxMsg.Data.Data[4]); + if(RxMsg.Data.Data[2] == 41) + DescpListDirectPadRpy(RxMsg.Data.Data[1],RxMsg.Data.Data[4]); + } + if(RxMsg.Data.Data[5]){ + if(RxMsg.Data.Data[2] < 41) + DescpListRpy(RxMsg.Data.Data[1], RxMsg.Data.Data[2], RxMsg.Data.Data[5]); + if(RxMsg.Data.Data[2] == 41) + DescpListDirectPadRpy(RxMsg.Data.Data[1],RxMsg.Data.Data[5]); + } + if(RxMsg.Data.Data[6]){ + if(RxMsg.Data.Data[2] < 41) + DescpListRpy(RxMsg.Data.Data[1], RxMsg.Data.Data[2], RxMsg.Data.Data[6]); + if(RxMsg.Data.Data[2] == 41) + DescpListDirectPadRpy(RxMsg.Data.Data[1],RxMsg.Data.Data[6]); + } + if(RxMsg.Data.Data[7]){ + if(RxMsg.Data.Data[2] < 41) + DescpListRpy(RxMsg.Data.Data[1], RxMsg.Data.Data[2], RxMsg.Data.Data[7]); + if(RxMsg.Data.Data[2] == 41) + DescpListDirectPadRpy(RxMsg.Data.Data[1],RxMsg.Data.Data[7]); + } + }else + if(aCmd == dNetworkCmd_DescpOnePortAsk){ + SlaveDoNetDescpRpy(RxMsg.Data.Data[1], RxMsg.Data.Data[2]); + } + + if(aCtlNum != MasterNum)return; + if(0 == CheckIsInSlaveList(MainCtl.fData.Split.MyNum))return; + + NewOrder = RxMsg.Data.Order; + + if(tForceIdf)OnReceive.IsProcessDone[aCtlNum] = 0; + if(OnReceive.OrderLast[aCtlNum] != NewOrder)OnReceive.IsProcessDone[aCtlNum] = 0; + if( OnReceive.IsProcessDone[aCtlNum] && (OnReceive.OrderAck[aCtlNum] == NewOrder ) ){ + if(OnReceive.IsCheckOnline){ + AckOnlineCheck(aCtlNum, NewOrder); + }else{ + Ack(aCtlNum, NewOrder); + } + return; + } + OnReceive.OrderLast[aCtlNum] = NewOrder; + + if(CmdActiveDefaultSet[aCmd][6] == FastCall){ + if(OnReceive.Piece[aCtlNum] && (OnReceive.OrderDt[aCtlNum] == NewOrder) ){ + if(aCmd == cmVAAlramStart){ + if(RxMsg.Data.Data[0]){ + if(OnReceive.Piece[aCtlNum]){ + SlaveDoAlramOnOff(1); + Ack(aCtlNum, NewOrder); + } + } + }else + if(aCmd == cmVAAlramStop){ + if(RxMsg.Data.Data[0]){ + if(OnReceive.Piece[aCtlNum]){ + SlaveDoAlramOnOff(0); + Ack(aCtlNum, NewOrder); + } + } + } + } + }else + if(CmdActiveDefaultSet[aCmd][6] == StdCall){ + /*if(aCmd == cmReset){ + if(RxMsg.Data.Data[0]){ + //Reset + if(OnReceive.Piece[aCtlNum]){ + ResetCallBack(); + OnReceive.IsProcessDone[aCtlNum] = 1; + Ack(aCtlNum, OnReceive.ProcessingOrder[aCtlNum]); + } + } + }*/ + if(aCmd == dNetworkCmd_CheckOnline){ + if( (RxMsg.Data.Data[2] == 0xA5) && ( RxMsg.Data.Data[3] == 0x5A) ){ + CheckOnlineUpdateTick =0; + AckOnlineCheck(aCtlNum, NewOrder); + } + }else + if(aCmd == dNetworkCmd_CheckNormalData){ + if( (RxMsg.Data.Data[2] == MainCtl.fData.Split.MyNum) && (RxMsg.Data.Data[3] == 0x5A) ){ + Ack(aCtlNum, NewOrder); + SlaveDoRpyCheckNormalData(); + } + }else + if(aCmd == dNetworkCmd_SetSlaveAllow){ + if( RxMsg.Data.Data[2] == MainCtl.fData.Split.MyNum ){ + Ack(aCtlNum, NewOrder); + SlaveSetAllowStateBySpc(MainCtl.fData.Split.MyNum, RxMsg.Data.Data[3]); + } + } + }else + if(CmdActiveDefaultSet[aCmd][6] == NetNormalCall){ + if(aCmd == dNetworkCmd_ClearCtlFire){ + ClearNwCtlFire(RxMsg.Data.Data[0]); + Ack(aCtlNum, NewOrder); + }else + if(aCmd == dNetworkCmd_PublishFireCancel){ + + }else + if(aCmd == dNetworkCmd_PublishFire){ + ProtoC2C.SetNwFire(RxMsg.Data.Data[0], RxMsg.Data.Data[2], RxMsg.Data.Data[3], 0xA5A5A500 + RxMsg.Data.Data[5]); + Ack(aCtlNum, NewOrder); + }else + if(aCmd == dNetworkCmd_PublishOperate){ + if(OnReceive.Piece[aCtlNum] && (OnReceive.OrderDt[aCtlNum] == NewOrder) ){ + if(RxMsg.Data.Data[6] == otCfgDateTime){ + if( (OnReceive.Piece[aCtlNum] == 0x03) && (OnReceive.OrderNewDt[aCtlNum] == NewOrder) ){ + OperateGet(aCmd,RxMsg.Data.Data); + Ack(aCtlNum, NewOrder); + } + }else{ + if(otReset == RxMsg.Data.Data[6]){ + OnReceive.CallResetCtlNum = aCtlNum; + OnReceive.CallResetNetOrder = NewOrder; + OperateGet(aCmd,RxMsg.Data.Data); + }else{ + OperateGet(aCmd,RxMsg.Data.Data); + Ack(aCtlNum, NewOrder); + } + } + } + }else + if(aCmd == dNetworkCmd_EventTime){ + OnReceive.OrderDt[aCtlNum] = NewOrder; + RecUserCodeAreaNum[aCtlNum].UC.Bytes[0] = RxMsg.Data.Data[0]; + RecDateTime[aCtlNum].D32[0] = RxMsg.D32[2]; + RecDateTime[aCtlNum].D32[1] = RxMsg.D32[3]; + RecDateTime[aCtlNum].D32[2] = 1; + OnReceive.Piece[aCtlNum] |= 0x01; + }else + if(aCmd == dNetworkCmd_NewTime){ + OnReceive.OrderNewDt[aCtlNum] = NewOrder; + RecNewDateTime[aCtlNum].D32[0] = RxMsg.D32[2]; + RecNewDateTime[aCtlNum].D32[1] = RxMsg.D32[3]; + RecNewDateTime[aCtlNum].D32[2] = 1; + OnReceive.Piece[aCtlNum] |= 0x02; + }else + if(aCmd == dNetworkCmd_RemoteStartStop){ + if(RxMsg.Data.Data[0] == MainCtl.fData.Split.MyNum){ + SlaveDoGetRemoteStartStop(MainCtl.fData.Split.MyNum, RxMsg.Data.Data[2], RxMsg.Data.Data[3], RxMsg.Data.Data[5]); + } + Ack(aCtlNum, NewOrder); + }else + if(aCmd == dNetworkCmd_RemoteStartStopViaUserCode){ + unsigned short aDelay; + Ack(aCtlNum, NewOrder); + CtlByte = RxMsg.Data.Data[0] & 0x0F; + aDelay = RxMsg.Data.Data[0] & 0xF0; + aDelay <= 4; + aDelay &= 0x0F00; + aDelay |= RxMsg.Data.Data[7]; + DMix.D8[0] = RxMsg.Data.Data[2]; + DMix.D8[1] = RxMsg.Data.Data[3]; + DMix.D8[2] = RxMsg.Data.Data[4]; + DMix.D8[3] = RxMsg.Data.Data[6]; + SlaveDoGetRemoteStartStopUserCode(DMix.D32, RxMsg.Data.Data[5], aDelay, CtlByte); + }else + if(aCmd == dNetworkCmd_RemoteStartStopViaUserCodeSimulate){ + unsigned short aDelay; + Ack(aCtlNum, NewOrder); + CtlByte = RxMsg.Data.Data[0] & 0x0F; + aDelay = RxMsg.Data.Data[0] & 0xF0; + aDelay <= 4; + aDelay &= 0x0F00; + aDelay |= RxMsg.Data.Data[7]; + DMix.D8[0] = RxMsg.Data.Data[2]; + DMix.D8[1] = RxMsg.Data.Data[3]; + DMix.D8[2] = RxMsg.Data.Data[4]; + DMix.D8[3] = RxMsg.Data.Data[6]; + SlaveDoGetRemoteStartStopUserCodeSimulate(DMix.D32, RxMsg.Data.Data[5], aDelay, CtlByte); + } + }else + if(CmdActiveDefaultSet[aCmd][6] == SimEvent){ + if(OnReceive.Piece[aCtlNum] && (OnReceive.OrderDt[aCtlNum] == NewOrder) ){ + if(aCmd == cmVIrtualStart){ + //if(RxMsg.Data.Data[0]){ + if(OnReceive.Piece[aCtlNum]){ + //SlaveDoAlramOnOff(1); + Ack(aCtlNum, NewOrder); + } + //} + }else + if(aCmd == smVIrtualStop){ + //if(RxMsg.Data.Data[0]){ + if(OnReceive.Piece[aCtlNum]){ + // SlaveDoAlramOnOff(0); + Ack(aCtlNum, NewOrder); + } + //} + } + } + } +} + +void TProtoC2C::ProcessoEntry() +{ + int i, pNum, IsAckOk, IsAckNotOk, CanLoadNew, aNewCtlNotAck; + if(MainCtl.fData.Split.MyNum == 0)return; + if(MainCtl.fData.Split.NetworkMode == 1){ + if(OnTransmite.OnGoing){ + IsAckOk = 0; + IsAckNotOk = 0; + CanLoadNew = 0; + if(OnTransmite.IsBroadCast){ + for(i=0; i dNETWORK_MACHINE_COUNT)pNum = 0; + if (pNum){ + if( (pNum CtlMask.EndNum) ){ + if(OnTransmite.AckOk[pNum]){ + NoAckList[pNum] = 0; + if( ReportSlaveOffline[pNum] ==1){ + RemoveMasterCommFault(pNum); + ReportSlaveOffline[pNum] = 0; + } + }else{ + if( ReportSlaveOffline[pNum] == 0 ){ + IsAckNotOk = 1; + } + } + } + } + } + //if(AckOkCnt >= SlaveCount){ + if(IsAckNotOk == 0){ + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + }else{ + //Lost At Less 1 Ctl Not Ack + OnTransmite.TimeOutTick++; + if(OnTransmite.TimeOutTick >50){ + if(iBufInCountPer2Sec > 40){ + //Bus Is Busy + OnTransmite.TimeOutTick = 0; + }else{ + OnTransmite.RetryTimes++; + if( OnTransmite.RetryTimes > 10){ + //Abort + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + + for(i=0; iCtlMask.EndNum ) ){ + if(OnTransmite.AckOk[pNum] == 0){ + if(CommLostCount[pNum] <201)CommLostCount[pNum]++; + if( ReportSlaveOffline[pNum] ==0){ + AddMasterCommFault(pNum); + ReportSlaveOffline[pNum] = 1; + } + NoAckList[pNum] = 1; + } + ErrReport = 1; + } + } + } + }else{ + //Check Is New Ctl Not ACK + aNewCtlNotAck = 0; + for(i=0; iCtlMask.EndNum ) ){ + if(OnTransmite.AckOk[pNum] == 0){ + if( NoAckList[pNum] == 0){ + aNewCtlNotAck = 1; + } + } + } + } + } + if(aNewCtlNotAck == 0){ + //No New Ctl Not Ack , Abort + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + }else{ + //a New Ctl Not Ack , ReSend All Data Pkg With Old Order + OnTransmite.TimeOutTick = 0; + ExportEntry2oBuf(0); + OnTransmite.OnGoing = 1; + + MasterRetrySendEntryCount++; + } + } + } + } + } + }else{ + if( (OnTransmite.SlaveCtlNum >0) && (OnTransmite.SlaveCtlNum <= dNETWORK_MACHINE_COUNT) ){ + pNum = OnTransmite.SlaveCtlNum; + if(OnTransmite.AckOk[pNum]){ + NoAckList[pNum] = 0; + IsAckOk =1; + if( ReportSlaveOffline[pNum] ==1){ + RemoveMasterCommFault(pNum); + ReportSlaveOffline[pNum] = 0; + } + }else{ + if ( (pNum >= CtlMask.StartNum) || (pNum <= CtlMask.EndNum) ) { + IsAckOk =1; + } + } + if(IsAckOk){ + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + }else{ + //Lost At Less 1 Ctl Not Ack + OnTransmite.TimeOutTick++; + if(OnTransmite.TimeOutTick >50){ + if(iBufInCountPer2Sec > 40){ + //Bus Is Busy + OnTransmite.TimeOutTick = 0; + }else{ + OnTransmite.RetryTimes++; + if( OnTransmite.RetryTimes > 10){ + //Abort + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + + if(OnTransmite.AckOk[pNum] == 0){ + if(OnTransmite.IsReportErr){ + if(CommLostCount[pNum] <201)CommLostCount[pNum]++; + if( ReportSlaveOffline[pNum] ==0){ + AddMasterCommFault(pNum); + ReportSlaveOffline[pNum] = 1; + } + NoAckList[pNum] = 1; + } + } + ErrReport = 1; + }else{ + //Check Is New Ctl Not ACK + aNewCtlNotAck = 0; + if(OnTransmite.AckOk[pNum] == 0){ + if( NoAckList[pNum] == 0){ + aNewCtlNotAck = 1; + } + } + if(aNewCtlNotAck == 0){ + //No New Ctl Not Ack , Abort + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + }else{ + //a New Ctl Not Ack , ReSend All Data Pkg With Old Order + OnTransmite.TimeOutTick = 0; + ExportEntry2oBuf(0); + OnTransmite.OnGoing = 1; + + MasterRetrySendEntryCount++; + } + } + } + } + } + } + } + }else{ + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + } + + if(CanLoadNew){ + //Check And Load New Entry + if(TryLoadNewEntry()){ + OnTransmite.Order++; + if(OnTransmite.Order == 0)OnTransmite.Order = 1; + OnTransmite.TimeOutTick = 0; + OnTransmite.RetryTimes = 0; + NeedRpyCount = 0; + for(int i=0; iCtlMask.EndNum ) ){ + OnTransmite.DesireAckOrder[pNum] = OnTransmite.Order; + OnTransmite.AckOk[pNum] = 0; + NeedRpyCount ++; + } + } + } + ExportEntry2oBuf(1); + OnTransmite.OnGoing = 1; + } + } + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + if( (MasterNum == 0) || (MasterNum > dNETWORK_MACHINE_COUNT) ){ + OnTransmite.OnGoing = 0; + return; + } + if ( (MasterNum >= CtlMask.StartNum) and (MasterNum <= CtlMask.EndNum) ) { + OnTransmite.OnGoing = 0; + return; + } + if(OnTransmite.OnGoing){ + IsAckOk = 0; + CanLoadNew = 0; + if(OnTransmite.AckOk[MasterNum]){ + IsAckOk =1; + } + if(IsAckOk){ + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + if(ReportMasterOffline){ + RemoveSlaveCommFault(MasterNum); + ReportMasterOffline = 0; + } + }else{ + OnTransmite.TimeOutTick++; + if(OnTransmite.TimeOutTick >50){ + if(iBufInCountPer2Sec > 40){ + //Bus Is Busy + OnTransmite.TimeOutTick = 0; + }else{ + OnTransmite.RetryTimes++; + if(OnTransmite.RetryTimes > 10){ + //Abort + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + + if(CommLostCount[0] <201)CommLostCount[0]++; + if(ReportMasterOffline == 0){ + AddSlaveCommFault(MasterNum); + ReportMasterOffline = 1; + } + ErrReport = 1; + }else{ + //ReSend All Data Pkg With Old Order + OnTransmite.TimeOutTick = 0; + ExportEntry2oBuf(0); + OnTransmite.OnGoing = 1; + SlaveRetrySendEntryCount++; + } + } + } + } + }else{ + CanLoadNew = 1; + OnTransmite.OnGoing = 0; + } + + if(CanLoadNew){ + //Check And Load New Entry + if(TryLoadNewEntry()){ + OnTransmite.Order++; + if(OnTransmite.Order == 0)OnTransmite.Order = 1; + OnTransmite.TimeOutTick = 0; + OnTransmite.RetryTimes = 0; + if( (MasterNum CtlMask.EndNum ) ){ + if(CheckIsInSlaveList(MainCtl.fData.Split.MyNum)){ + OnTransmite.DesireAckOrder[MasterNum] = OnTransmite.Order; + OnTransmite.AckOk[MasterNum] = 0; + ExportEntry2oBuf(1); + OnTransmite.OnGoing = 1; + } + } + } + } + }else{ + OnTransmite.OnGoing = 0; + } +} + +int TProtoC2C::TryLoadNewEntry() +{ + int Loaded =0; + if(oEntryBasicService.CheckDataAvalibel()){ + oEntryBasicService.Read(oEntry.rBody.D32); + Loaded=1; + }else + if(oEntryFire.CheckDataAvalibel()){ + oEntryFire.Read(oEntry.rBody.D32); + Loaded=1; + }else + if(oEntrySv.CheckDataAvalibel()){ + oEntrySv.Read(oEntry.rBody.D32); + Loaded=1; + }else + if(oEntryLink.CheckDataAvalibel()){ + oEntryLink.Read(oEntry.rBody.D32); + Loaded=1; + }else + if(oEntryFault.CheckDataAvalibel()){ + oEntryFault.Read(oEntry.rBody.D32); + Loaded=1; + }else + if(oEntryNormal.CheckDataAvalibel()){ + oEntryNormal.Read(oEntry.rBody.D32); + Loaded=1; + } + return Loaded; +} + +void TProtoC2C::oBufInsert() +{ + unsigned int aAddr; + + oBuf.WriteIndex++; + if(oBuf.WriteIndex >= dNetworkOutBufMaxLength)oBuf.WriteIndex = 0; + + aAddr = dAddrSdram_C2cOutBuf + (oBuf.WriteIndex * 16); + TxMsg.Data.Routing = 0; + * (volatile unsigned int *)(aAddr + 0) = TxMsg.D32[0]; + * (volatile unsigned int *)(aAddr + 4) = TxMsg.D32[1]; + * (volatile unsigned int *)(aAddr + 8) = TxMsg.D32[2]; + * (volatile unsigned int *)(aAddr + 12) = TxMsg.D32[3]; +} + +void TProtoC2C::oBufInsert(TC2CBufBody aNsBuf) +{ + unsigned int aAddr; + + oBuf.WriteIndex++; + if(oBuf.WriteIndex >= dNetworkOutBufMaxLength)oBuf.WriteIndex = 0; + + aAddr = dAddrSdram_C2cOutBuf + (oBuf.WriteIndex * 16); + * (volatile unsigned int *)(aAddr + 0) = aNsBuf.D32[0]; + * (volatile unsigned int *)(aAddr + 4) = aNsBuf.D32[1]; + * (volatile unsigned int *)(aAddr + 8) = aNsBuf.D32[2]; + * (volatile unsigned int *)(aAddr + 12) = aNsBuf.D32[3]; +} + +void TProtoC2C::oBufMsgPreload(TRecordCommon aIm, unsigned char aCmd) +{ + if(MainCtl.fData.Split.NetworkMode == 0)return; + + oEntry.wBody.Split.Cmd = aCmd; + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.Year = DateTime.Date.Split.Year; + oEntry.wBody.Split.Mon = DateTime.Date.Split.Month; + oEntry.wBody.Split.Day = DateTime.Date.Split.Day; + oEntry.wBody.Split.Hour = DateTime.Time.Split.Hour; + oEntry.wBody.Split.Min = DateTime.Time.Split.Minute; + oEntry.wBody.Split.Sec = DateTime.Time.Split.Second; + + oEntry.wBody.Split.P0 = aIm.Splite.P0; + oEntry.wBody.Split.P1 = aIm.Splite.P1; + oEntry.wBody.Split.Prm = aIm.Splite.P2; + oEntry.wBody.Split.dType = aIm.Splite.dType; + oEntry.wBody.Split.Prm1 = aIm.Splite.Data0; + oEntry.wBody.Split.Prm2 = aIm.Splite.Data1; + oEntry.wBody.Split.sType = aIm.Splite.iByte0; +} +void TProtoC2C::oBufMsgInsertBasicService() +{ + oEntryBasicService.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertFire() +{ + oEntryFire.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertSv() +{ + oEntrySv.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertLink() +{ + oEntryLink.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertFault() +{ + oEntryFault.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertNormal() +{ + oEntryNormal.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertBasicService(TRecordCommon aIm, unsigned char aCmd) +{ + oBufMsgPreload(aIm,aCmd); + oEntryBasicService.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertFire(TRecordCommon aIm, unsigned char aCmd) +{ + oBufMsgPreload(aIm,aCmd); + oEntryFire.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertSv(TRecordCommon aIm, unsigned char aCmd) +{ + oBufMsgPreload(aIm,aCmd); + oEntrySv.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertLink(TRecordCommon aIm, unsigned char aCmd) +{ + oBufMsgPreload(aIm,aCmd); + oEntryLink.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertFault(TRecordCommon aIm, unsigned char aCmd) +{ + oBufMsgPreload(aIm,aCmd); + oEntryFault.Write(oEntry.wBody.D32); +} +void TProtoC2C::oBufMsgInsertNormal(TRecordCommon aIm, unsigned char aCmd) +{ + oBufMsgPreload(aIm,aCmd); + oEntryNormal.Write(oEntry.wBody.D32); +} + +void TProtoC2C::oBufProcess() +{ + unsigned int aAddr, aVal, aLoad; + if(oBuf.ReadIndex != oBuf.WriteIndex){ + if(get_excan_linkage_tx_complete()){ + oBuf.ReadIndex++; + if(oBuf.ReadIndex >= dNetworkOutBufMaxLength)oBuf.ReadIndex = 0; + aAddr = dAddrSdram_C2cOutBuf + (oBuf.ReadIndex * 16); + oBuf.aBody.D32[0] = * (volatile unsigned int *)(aAddr + 0); + oBuf.aBody.D32[1] = * (volatile unsigned int *)(aAddr + 4); + oBuf.aBody.D32[2] = * (volatile unsigned int *)(aAddr + 8); + oBuf.aBody.D32[3] = * (volatile unsigned int *)(aAddr + 12); + aLoad = static_cast(oBuf.aBody.Data.Identification); + aVal = (aLoad << 24 ) & (1<<24); + aLoad = static_cast(oBuf.aBody.Data.Routing); + aVal |= (aLoad << 25 ) & (3<<25); + aLoad = static_cast(oBuf.aBody.Data.Priority); + aVal |= (aLoad << 27 ) & (3<<27); + oBuf.aBody.D32[0] &= 0x00FFFFFF; + oBuf.aBody.D32[0] |= aVal; + outer_can_send_data(oBuf.aBody.D32[0], oBuf.aBody.Data.Data, oBuf.aBody.Data.Len); + } + } +} + +void TProtoC2C::ReplyCtrlType() +{ + unsigned char aType; + //CmdC2C_RpyType : D0=Len, D1=Pri, D2=CMD, D3=CTLBYTE D4=SubCmd D5=CtlNum D6=Type (Master or Slave, See Define) + if(MainCtl.fData.Split.NetworkMode == 1){ + aType = dNetworkTypeMaster; + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + aType = dNetworkTypeSlave; + }else{ + aType = dNetworkTypeNone; + } + + TxMsg.Data.Cmd = dNetworkCmd; + TxMsg.Data.Len = 6; + TxMsg.Data.Data[0] = 0; + TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum ; + TxMsg.Data.Data[2] = CmdC2C_RpyType; + TxMsg.Data.Data[3] = aType; + if(MainCtl.fData.Split.NetworkMode == 1){ + TxMsg.Data.Data[4] = this->SlaveCount; + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TxMsg.Data.Data[4] = this->MasterNum; + } + oBufInsert(); + + if(0){ + TxMsg.Data.Cmd = dNetworkCmd; + TxMsg.Data.Len = 4; + TxMsg.Data.Data[0] = 0; + TxMsg.Data.Data[1] = 6; + TxMsg.Data.Data[2] = CmdC2C_RpyType; + TxMsg.Data.Data[3] = dNetworkTypeSlave; + + oBufInsert(); + + TxMsg.Data.Cmd = dNetworkCmd; + TxMsg.Data.Len = 4; + TxMsg.Data.Data[0] = 0; + TxMsg.Data.Data[1] = 7; + TxMsg.Data.Data[2] = CmdC2C_RpyType; + TxMsg.Data.Data[3] = dNetworkTypeSlave; + + oBufInsert(); + + TxMsg.Data.Cmd = dNetworkCmd; + TxMsg.Data.Len = 4; + TxMsg.Data.Data[0] = 0; + TxMsg.Data.Data[1] = 8; + TxMsg.Data.Data[2] = CmdC2C_RpyType; + TxMsg.Data.Data[3] = dNetworkTypeSlave; + + oBufInsert(); + + TxMsg.Data.Cmd = dNetworkCmd; + TxMsg.Data.Len = 4; + TxMsg.Data.Data[0] = 0; + TxMsg.Data.Data[1] = 9; + TxMsg.Data.Data[2] = CmdC2C_RpyType; + TxMsg.Data.Data[3] = dNetworkTypeSlave; + + oBufInsert(); + } +} + +void TProtoC2C::ReplyDescp() +{ + char *p; + int Offset; + + p = "ccccccccccccccc"; +} + +void TProtoC2C::NwDevDescpInit() +{ + unsigned int i; + volatile unsigned int aAddr; + aAddr = dAddrSdRam_DescpNw; + for(i=0;i<2621440;i++){ + *(volatile unsigned int *)(aAddr) =0; + aAddr += 4; + } +} + +void TProtoC2C::BufInit() +{ + unsigned int i; + volatile unsigned int aAddr; + aAddr = dAddrSdram_C2cOutBuf; + for(i=0;i<262144;i++){ + *(volatile unsigned int *)(aAddr) =0; + aAddr += 4; + } +} + +void TProtoC2C::ExportMachineEventTime2Master(unsigned char IsNew) +{ + TDMix DMix; + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Identification = 0; + + TxMsg.Data.Cmd = dNetworkCmd_EventTime; + TxMsg.Data.Order = OnTransmite.Order; + if(IsNew)TxMsg.Data.Identification = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Data[0] = 0; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum; + + if(CmdFillAreaNum){ + TxMsg.Data.CarryByte = static_cast(((oEntry.rBody.Split.AreaNum & 0x0F00) >> 8 )); + } + if(CmdFillUserCode){ + DMix.D32 = oEntry.rBody.Split.UserCode; + TxMsg.Data.Data[0] = DMix.D8[0]; + } + + if( (oEntry.rBody.Split.Cmd == dNetworkCmd_PublishOperate) && (otSetNwTime == oEntry.rBody.Split.sType) ){ + TxMsg.Data.Data[2] = DateTime.Date.Split.Year; + TxMsg.Data.Data[3] = DateTime.Date.Split.Month; + TxMsg.Data.Data[4] = DateTime.Date.Split.Day; + TxMsg.Data.Data[5] = DateTime.Time.Split.Hour; + TxMsg.Data.Data[6] = DateTime.Time.Split.Minute; + TxMsg.Data.Data[7] = DateTime.Time.Split.Second; + }else{ + TxMsg.Data.Data[2] = oEntry.rBody.Split.Year; + TxMsg.Data.Data[3] = oEntry.rBody.Split.Mon; + TxMsg.Data.Data[4] = oEntry.rBody.Split.Day; + TxMsg.Data.Data[5] = oEntry.rBody.Split.Hour; + TxMsg.Data.Data[6] = oEntry.rBody.Split.Min; + TxMsg.Data.Data[7] = oEntry.rBody.Split.Sec; + } + + oBufInsert(); + +} + +void TProtoC2C::ExportMachineEventNewTime2Master(unsigned char IsNew) +{ + unsigned int i,aAddr; + if(MainCtl.fData.Split.NetworkMode == 2){ + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Cmd = dNetworkCmd_NewTime; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Len = 8; + TxMsg.Data.Data[0] = 1; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] = oEntry.rBody.Split.Prm; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] = oEntry.rBody.Split.Prm1; + TxMsg.Data.Data[7] = oEntry.rBody.Split.Prm2; + + oBufInsert(); + } +} + +void TProtoC2C::Ack(unsigned char TargetNum, unsigned char aOrder) +{ + OnReceive.IsCheckOnline = 0; + + OnReceive.IsProcessDone[TargetNum] = 1; + OnReceive.OrderAck[TargetNum] = aOrder; + OnReceive.Piece[TargetNum] =0; + OnReceive.OrderDt[TargetNum] = 0; + + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Identification = 0; + + TxMsg.Data.Cmd = dNetworkCmd_Ack; + TxMsg.Data.Order = aOrder; + TxMsg.Data.Len = 4; + TxMsg.Data.Data[0] = 0; + TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + TxMsg.Data.Data[2] = TargetNum; + TxMsg.Data.Data[3] = 0; + + oBufInsert(); +} + +void TProtoC2C::AckOnlineCheck(unsigned char TargetNum, unsigned char aOrder) +{ + OnReceive.IsCheckOnline = 1; + + OnReceive.IsProcessDone[TargetNum] = 1; + OnReceive.OrderAck[TargetNum] = aOrder; + OnReceive.Piece[TargetNum] =0; + OnReceive.OrderDt[TargetNum] = 0; + + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Identification = 0; + + TxMsg.Data.Cmd = dNetworkCmd_Ack; + TxMsg.Data.Order = aOrder; + TxMsg.Data.Len = 4; + TxMsg.Data.Data[0] = 0x55; + TxMsg.Data.Data[1] = MainCtl.fData.Split.MyNum; + TxMsg.Data.Data[2] = TargetNum; + TxMsg.Data.Data[3] = 0xAA; + + oBufInsert(); +} + +void TProtoC2C::ProcessAckRecFromSlave(unsigned char aOrder, unsigned char *Data) +{ + if(Data[2] == MainCtl.fData.Split.MyNum){ + if(aOrder == OnTransmite.DesireAckOrder[Data[1]]){ + if( Data[1] && (Data[1] <=dNETWORK_MACHINE_COUNT) ){ + OnTransmite.AckOk[Data[1]] = 1; + if( (Data[0] == 0x55) && (Data[3] == 0xAA) ){ + SlaveOnlineList[Data[1]] = 1; + } + } + } + } +} + +void TProtoC2C::ProcessAckRecFromMaster(unsigned char aOrder, unsigned char *Data) +{ + if(Data[2] == MainCtl.fData.Split.MyNum){ + if(aOrder == OnTransmite.DesireAckOrder[Data[1]]){ + if( Data[1] && (Data[1] <= dNETWORK_MACHINE_COUNT) ){ + if(Data[1] == ProtoC2C.MasterNum) CheckOnlineUpdateTick = 0; + OnTransmite.AckOk[Data[1]] = 1; + } + } + } +} + +void TProtoC2C::ExportEntry2oBuf(unsigned char IsNew) +{ + unsigned short aRemainCountDown; + TDMix DMix; + unsigned char aEt; + if(MainCtl.fData.Split.NetworkMode == 0)return; + CmdFillAreaNum =0; + CmdFillDelayTime =0; + CmdFillUserCode =0; + OnTransmite.IsReportErr = 1; + OnTransmite.IsBroadCast =1; + switch(oEntry.rBody.Split.Cmd){ + case cmPublishAlram: + case cmVIrtualAlram: + case cmConfirmAlram: + case cmAutoStart: + case cmAutoStop: + case cmAck: + case cmAckStop: + case cmTakeChargeAlram: + case cmTakeChargeAlramResume: + case cmVIrtualStart: + case smVIrtualStop: + case cmVIrtualAck: + case cmVIrtualAckStop: + case cmVIrtualSuperVi: + CmdFillAreaNum =1; + CmdFillUserCode =1; + ExportMachineEventTime2Master(IsNew); + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Identification = 0; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = OnTransmite.Order; + if(IsNew)TxMsg.Data.Identification =1; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + TxMsg.Data.Data[0] =0; + TxMsg.Data.Data[1] =oEntry.rBody.Split.CtlNum; + TxMsg.Data.Data[2] =oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] =oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] =oEntry.rBody.Split.Prm; + TxMsg.Data.Data[5] =oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] =oEntry.rBody.Split.Prm1; + TxMsg.Data.Data[7] =oEntry.rBody.Split.Prm2; + if(CmdFillAreaNum){ + TxMsg.Data.Data[4] = static_cast(oEntry.rBody.Split.AreaNum & 0x00FF); + TxMsg.Data.CarryByte = static_cast(((oEntry.rBody.Split.AreaNum & 0x0F00) >> 8 )); + } + if(CmdFillUserCode){ + DMix.D32 = oEntry.rBody.Split.UserCode; + TxMsg.Data.Data[0] = DMix.D8[1]; + TxMsg.Data.Data[6] = DMix.D8[2]; + TxMsg.Data.Data[7] = DMix.D8[3]; + } + + oBufInsert(); + break; + case dNetworkCmd_AutoStartDelay: + case dNetworkCmd_AutoStartDelaySimulate: + CmdFillDelayTime =1; + CmdFillUserCode =1; + ExportMachineEventTime2Master(IsNew); + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Identification = 0; + if(IsNew)TxMsg.Data.Identification =1; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + //Is Delay Start + TxMsg.Data.Data[1] =oEntry.rBody.Split.CtlNum; + TxMsg.Data.Data[2] =oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] =oEntry.rBody.Split.P1; + //TxMsg.Data.Data[4] =oEntryBuf.rBody.Split.Prm; + TxMsg.Data.Data[5] =oEntry.rBody.Split.dType; + if(CmdFillDelayTime){ + aRemainCountDown = GetThisCtlCountDownTime(oEntry.rBody.Split.CtlNum, oEntry.rBody.Split.P0, oEntry.rBody.Split.P1); + TxMsg.Data.Data[4] = static_cast(aRemainCountDown & 0x00FF); + TxMsg.Data.CarryByte |= static_cast(((aRemainCountDown & 0x0F00) >> 8 )); + } + if(CmdFillUserCode){ + DMix.D32 = oEntry.rBody.Split.UserCode; + TxMsg.Data.Data[0] = DMix.D8[1]; + TxMsg.Data.Data[6] = DMix.D8[2]; + TxMsg.Data.Data[7] = DMix.D8[3]; + } + oBufInsert(); + break; + case cmPortModuleErr: + case cmPortModuleErrRecover: + CmdFillUserCode =1; + ExportMachineEventTime2Master(IsNew); + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Identification = 0; + if(IsNew)TxMsg.Data.Identification =1; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] =0; + TxMsg.Data.Data[1] =oEntry.rBody.Split.CtlNum; + TxMsg.Data.Data[2] =oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] =oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] =oEntry.rBody.Split.Prm; + TxMsg.Data.Data[5] =oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] =oEntry.rBody.Split.Prm1; + TxMsg.Data.Data[7] =oEntry.rBody.Split.Prm2; + if(CmdFillUserCode){ + DMix.D32 = oEntry.rBody.Split.UserCode; + TxMsg.Data.Data[0] = DMix.D8[1]; + TxMsg.Data.Data[6] = DMix.D8[2]; + TxMsg.Data.Data[7] = DMix.D8[3]; + } + oBufInsert(); + break; + case cmCircuitErr: + case cmOtherErr: + ExportMachineEventTime2Master(IsNew); + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] =oEntry.rBody.Split.sType; + TxMsg.Data.Data[1] =oEntry.rBody.Split.CtlNum; + TxMsg.Data.Data[2] =oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] =oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] =oEntry.rBody.Split.Prm; + TxMsg.Data.Data[5] =oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] =oEntry.rBody.Split.Prm1; + TxMsg.Data.Data[7] =oEntry.rBody.Split.Prm2; + + oBufInsert(); + break; + + case cmVAAlramStart: + case cmVAAlramStop: + ExportMachineEventTime2Master(IsNew); + if(MainCtl.fData.Split.NetworkMode == 1){ + TxMsg.Data.Data[0] =1; + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + TxMsg.Data.Data[0] =0; + } + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum; + TxMsg.Data.Data[2] = oEntry.rBody.Split.Year; + TxMsg.Data.Data[3] = oEntry.rBody.Split.Mon; + TxMsg.Data.Data[4] = oEntry.rBody.Split.Day; + TxMsg.Data.Data[5] = oEntry.rBody.Split.Hour; + TxMsg.Data.Data[6] = oEntry.rBody.Split.Min; + TxMsg.Data.Data[7] = oEntry.rBody.Split.Sec; + oBufInsert(); + break; + case dNetworkCmd_PublishOperate: + CmdFillAreaNum =0; + CmdFillDelayTime =0; + CmdFillUserCode =0; + aEt = oEntry.rBody.Split.sType; + if(aEt == otMask){ + CmdFillUserCode =1; + }else + if(aEt == otUnMask){ + CmdFillUserCode =1; + } + ExportMachineEventTime2Master(IsNew); + + if(oEntry.rBody.Split.sType == otCfgDateTime){ + ExportMachineEventNewTime2Master(IsNew); + } + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] =0; + TxMsg.Data.Data[1] =oEntry.rBody.Split.CtlNum; + TxMsg.Data.Data[2] =oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] =oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] =oEntry.rBody.Split.mType; + TxMsg.Data.Data[5] =oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] =oEntry.rBody.Split.sType; + TxMsg.Data.Data[7] =oEntry.rBody.Split.Prm2; + + if( (oEntry.rBody.Split.sType == otReset) && (MainCtl.fData.Split.NetworkMode == 1) ){ + TxMsg.Data.Data[0] =1; + TxMsg.Data.Data[7] =1; + } + if(otFaultRemoteConfirm == oEntry.rBody.Split.sType){ + TxMsg.Data.Data[0] =oEntry.rBody.Split.Prm1; + TxMsg.Data.Data[1] =MainCtl.fData.Split.MyNum; + TxMsg.Data.Data[2] =oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] =oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] =oEntry.rBody.Split.Prm; + TxMsg.Data.Data[5] =oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] =oEntry.rBody.Split.sType; + TxMsg.Data.Data[7] =oEntry.rBody.Split.Prm2; + }else + if(otRegisterByManual == oEntry.rBody.Split.sType){ + TxMsg.Data.Data[0] =0; + TxMsg.Data.Data[1] =MainCtl.fData.Split.MyNum; + TxMsg.Data.Data[2] =oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] =oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] =oEntry.rBody.Split.Prm; + TxMsg.Data.Data[5] =oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] =oEntry.rBody.Split.sType; + TxMsg.Data.Data[7] =oEntry.rBody.Split.Prm2; + } + + if(CmdFillUserCode){ + DMix.D32 = oEntry.rBody.Split.UserCode; + TxMsg.Data.Data[0] =DMix.D8[1]; + TxMsg.Data.Data[4] =DMix.D8[2]; + TxMsg.Data.Data[7] =DMix.D8[3]; + } + + oBufInsert(); + break; + case dNetworkCmd_MaskListSend: + CmdFillUserCode =1; + ExportMachineEventTime2Master(IsNew); + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] =0; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] = 0; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + + if(CmdFillUserCode){ + DMix.D32 = oEntry.rBody.Split.UserCode; + TxMsg.Data.Data[0] =DMix.D8[1]; + TxMsg.Data.Data[6] =DMix.D8[2]; + TxMsg.Data.Data[7] =DMix.D8[3]; + } + + oBufInsert(); + break; + case dNetworkCmd_SlaveFbMissReport: + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 4; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] =0; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] = 0; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + + oBufInsert(); + break; + case dNetworkCmd_CheckOnline: + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 4; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] =0; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] = 0; + + CheckOnlineHasSend = 1; + + oBufInsert(); + break; + case dNetworkCmd_CheckNormalData: + if(oEntry.rBody.Split.Year == 0){ + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 4; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] = oEntry.rBody.Split.Year ; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + + OnTransmite.IsReportErr = 0; + OnTransmite.IsBroadCast =0; + OnTransmite.SlaveCtlNum = oEntry.rBody.Split.P0; + oBufInsert(); + }else + if(oEntry.rBody.Split.Year){ + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] = oEntry.rBody.Split.Year ; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] = oEntry.rBody.Split.Prm; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] = oEntry.rBody.Split.Prm1; + TxMsg.Data.Data[7] = oEntry.rBody.Split.Prm2; + + oBufInsert(); + } + break; + case dNetworkCmd_RemoteStartStop: + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] = oEntry.rBody.Split.Prm ; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] = 0; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] = oEntry.rBody.Split.Prm1; + TxMsg.Data.Data[7] = oEntry.rBody.Split.Prm2; + + oBufInsert(); + break; + case dNetworkCmd_RemoteStartStopViaUserCode: + case dNetworkCmd_RemoteStartStopViaUserCodeSimulate: + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + DMix.D32 = oEntry.rBody.Split.UserCode; + + TxMsg.Data.Data[0] = oEntry.rBody.Split.Prm & 0x0F; //Load Sta + TxMsg.Data.Data[0] |= (oEntry.rBody.Split.Prm2 << 4); + + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = DMix.D8[0]; + TxMsg.Data.Data[3] = DMix.D8[1]; + TxMsg.Data.Data[4] = DMix.D8[2]; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] = DMix.D8[3]; + TxMsg.Data.Data[7] = oEntry.rBody.Split.Prm1; + + oBufInsert(); + break; + case dNetworkCmd_ClearCtlFire: + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 6; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + TxMsg.Data.Data[0] = oEntry.rBody.Split.Prm ; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntry.rBody.Split.P1; + TxMsg.Data.Data[4] = 0; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + + oBufInsert(); + break; + case dNetworkCmd_PublishFireCancel: + case dNetworkCmd_PublishFire: + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 6; + TxMsg.Data.Identification = IsNew; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Cmd = oEntry.rBody.Split.Cmd; + + DMix.D32 = oEntry.rBody.Split.UserCode; + + TxMsg.Data.Data[0] = oEntry.rBody.Split.Prm ; + TxMsg.Data.Data[1] = oEntry.rBody.Split.CtlNum ; + TxMsg.Data.Data[2] = DMix.D8[0]; + TxMsg.Data.Data[3] = DMix.D8[1]; + TxMsg.Data.Data[4] = DMix.D8[2]; + TxMsg.Data.Data[5] = oEntry.rBody.Split.dType; + TxMsg.Data.Data[6] = DMix.D8[3]; + TxMsg.Data.Data[7] = oEntry.rBody.Split.Prm2; + + oBufInsert(); + break; + } +} + +void TProtoC2C::PublishEventAlramOnOff(int aOnOff) +{ + if(aOnOff){ + oEntry.wBody.Split.Cmd = cmVAAlramStart; + }else{ + oEntry.wBody.Split.Cmd = cmVAAlramStop; + } + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.Year =DateTime.Date.Split.Year; + oEntry.wBody.Split.Mon =DateTime.Date.Split.Month; + oEntry.wBody.Split.Day = DateTime.Date.Split.Day; + oEntry.wBody.Split.Hour = DateTime.Time.Split.Hour; + oEntry.wBody.Split.Min = DateTime.Time.Split.Minute; + oEntry.wBody.Split.Sec = DateTime.Time.Split.Second; + + oBufMsgInsertNormal(); +} + +void TProtoC2C::PublishEventMute() +{ + if(MainCtl.fData.Split.NetworkMode != 2)return; + oEntry.wBody.Split.Cmd = cmMuteBell; + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.Year =DateTime.Date.Split.Year; + oEntry.wBody.Split.Mon =DateTime.Date.Split.Month; + oEntry.wBody.Split.Day = DateTime.Date.Split.Day; + oEntry.wBody.Split.Hour = DateTime.Time.Split.Hour; + oEntry.wBody.Split.Min = DateTime.Time.Split.Minute; + oEntry.wBody.Split.Sec = DateTime.Time.Split.Second; + + oBufMsgInsertNormal(); +} + +void TProtoC2C::PublishEventReset() +{ + if(MainCtl.fData.Split.NetworkMode == 0)return; + oBufInsert(); + oEntry.wBody.Split.Cmd = cmReset; + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.Year =DateTime.Date.Split.Year; + oEntry.wBody.Split.Mon =DateTime.Date.Split.Month; + oEntry.wBody.Split.Day = DateTime.Date.Split.Day; + oEntry.wBody.Split.Hour = DateTime.Time.Split.Hour; + oEntry.wBody.Split.Min = DateTime.Time.Split.Minute; + oEntry.wBody.Split.Sec = DateTime.Time.Split.Second; + + if(MainCtl.fData.Split.NetworkMode == 1){ + oEntry.wBody.Split.Prm1 =1; + }else{ + oEntry.wBody.Split.Prm1 =0; + } + oBufMsgInsertNormal(); +} + + + + + +/* +void TRecord::OperateAdd_CfgDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec) +{ + eOperateEvent.Splite.Year = DateTime.Date.Split.Year; + eOperateEvent.Splite.Month = DateTime.Date.Split.Month; + eOperateEvent.Splite.Day = DateTime.Date.Split.Day; + eOperateEvent.Splite.Hour = DateTime.Time.Split.Hour; + eOperateEvent.Splite.Minute = DateTime.Time.Split.Minute; + eOperateEvent.Splite.Second = DateTime.Time.Split.Second; + + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgDateTime; + + eOperateEvent.Splite.P0 = aY; + eOperateEvent.Splite.P1 = aM; + eOperateEvent.Splite.P2 = aD; + eOperateEvent.Splite.Data1 = aH; + eOperateEvent.Splite.iByte0 = aMin; + eOperateEvent.Splite.iByte1 = aSec; + + OperateAdd(eOperateEvent); + + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TProtoC2C::ExportMachineEventNewTime2Master(unsigned char IsNew) +{ + unsigned int i,aAddr; + if(MainCtl.fData.Split.IsMaster == 0){ + TxMsg.Data.Pri = 1; + TxMsg.Data.Cmd = dNetworkCmd_EventTime; + TxMsg.Data.Order = OnTransmite.Order; + TxMsg.Data.Idf = IsNew; + TxMsg.Data.Len = 8; + TxMsg.Data.Data[0] = 1; + TxMsg.Data.Data[1] = oEntryBuf.rBody.Split.CtlNum; + TxMsg.Data.Data[2] = oEntryBuf.rBody.Split.P0; + TxMsg.Data.Data[3] = oEntryBuf.rBody.Split.P1; + TxMsg.Data.Data[4] = oEntryBuf.rBody.Split.Prm; + TxMsg.Data.Data[5] = oEntryBuf.rBody.Split.dType; + TxMsg.Data.Data[6] = oEntryBuf.rBody.Split.Prm1; + TxMsg.Data.Data[7] = oEntryBuf.rBody.Split.Prm2; + + oBufInsert(); + } +} + +*/ + +void TProtoC2C::PublishOperate(TRecordCommon aIm) +{ + oEntry.wBody.Split.Cmd = dNetworkCmd_PublishOperate; + oEntry.wBody.Split.Year = aIm.Splite.Year; + oEntry.wBody.Split.Mon = aIm.Splite.Month; + oEntry.wBody.Split.Day = aIm.Splite.Day; + oEntry.wBody.Split.Hour = aIm.Splite.Hour; + oEntry.wBody.Split.Min = aIm.Splite.Minute; + oEntry.wBody.Split.Sec = aIm.Splite.Second; + + oEntry.wBody.Split.CtlNum = aIm.Splite.PCtlNum; + + if( aIm.Splite.Data0 == otCfgDateTime){ + oEntry.wBody.Split.P0 = aIm.Splite.P0; + oEntry.wBody.Split.P1 = aIm.Splite.P1; + oEntry.wBody.Split.Prm = aIm.Splite.P2; + + oEntry.wBody.Split.dType = aIm.Splite.Data1; + oEntry.wBody.Split.Prm1 = aIm.Splite.iByte0; + oEntry.wBody.Split.Prm2 = aIm.Splite.iByte1; + + oEntry.wBody.Split.mType = aIm.Splite.mType; + oEntry.wBody.Split.sType = aIm.Splite.Data0; + }else{ + oEntry.wBody.Split.P0 = aIm.Splite.P0; + oEntry.wBody.Split.P1 = aIm.Splite.P1; + oEntry.wBody.Split.Prm = aIm.Splite.P2; + oEntry.wBody.Split.dType = aIm.Splite.dType; + oEntry.wBody.Split.Prm2 = aIm.Splite.Data1; + + oEntry.wBody.Split.mType = aIm.Splite.mType; + oEntry.wBody.Split.sType = aIm.Splite.Data0; + + if(oEntry.wBody.Split.sType == otFaultRemoteConfirm) + oEntry.wBody.Split.Prm1 = aIm.Splite.iByte0; + } + + oEntry.wBody.Split.UserCode = aIm.Splite.UserCode; + oBufMsgInsertNormal(); +} + +void TProtoC2C::OperateGet(unsigned char aCmd, unsigned char *Data) +{ + unsigned int tUc; + unsigned char aEt; + TDMix Dm; + TDMix16 Dm16; + + if(MainCtl.fData.Split.NetworkMode == 0)return; + + if( (Data[1] == 0) || (Data[1] > 32) ) return; + OperateEntry.Splite.Year = RecDateTime[Data[1]].Dt.Year; + OperateEntry.Splite.Month = RecDateTime[Data[1]].Dt.Mon; + OperateEntry.Splite.Day = RecDateTime[Data[1]].Dt.Day; + OperateEntry.Splite.Hour = RecDateTime[Data[1]].Dt.Hour; + OperateEntry.Splite.Minute = RecDateTime[Data[1]].Dt.Min; + OperateEntry.Splite.Second = RecDateTime[Data[1]].Dt.Sec; + + OperateEntry.Splite.PCtlNum = Data[1]; + OperateEntry.Splite.P0 = Data[2]; + OperateEntry.Splite.P1 = Data[3]; + OperateEntry.Splite.mType = Data[4]; + OperateEntry.Splite.iByte0 = Data[5]; + OperateEntry.Splite.Data0 = Data[6]; + OperateEntry.Splite.Data1 = Data[7]; + + aEt = Data[6]; + + if(MainCtl.fData.Split.NetworkMode == 1){ + if(aEt == otReset){ + //CtlCenter.NwMachineStateClear(RxMsg.Data.Data[1]); + //CtlCenter.NwMachineMsgFireClear(RxMsg.Data.Data[1]); + //CtlCenter.CheckSoundFire(); + //CtlCenter.NwMachineMsgLinkageClear(RxMsg.Data.Data[1]); + //CtlCenter.CheckSoundLinkage(); + //CtlCenter.NwMachineMsgSvClear(RxMsg.Data.Data[1]); + //CtlCenter.CheckSoundSv(); + //CtlCenter.NwMachineMsgFaultClear(RxMsg.Data.Data[1]); + //CtlCenter.CheckSoundFault(); + //MasterDoMaskListRemove(RxMsg.Data.Data[1]); + //ProtoC2C.ClearNwCtlFire(RxMsg.Data.Data[1]); + //ProtoC2C.MasterDoPublishClearNwCtlFire(RxMsg.Data.Data[1]); + }else + if(aEt == otCfgDateTime){ + if(OnReceive.Piece[Data[1]] == 3){ + OperateEntry.Splite.P0 = RecNewDateTime[Data[1]].Dt.Year; + OperateEntry.Splite.P1 = RecNewDateTime[Data[1]].Dt.Mon; + OperateEntry.Splite.P2 = RecNewDateTime[Data[1]].Dt.Day; + OperateEntry.Splite.Data1 = RecNewDateTime[Data[1]].Dt.Hour; + OperateEntry.Splite.iByte0 = RecNewDateTime[Data[1]].Dt.Min; + OperateEntry.Splite.iByte1 = RecNewDateTime[Data[1]].Dt.Sec; + + //TxMsg.Data.Data[2] = oEntryBuf.rBody.Split.P0; + //TxMsg.Data.Data[3] = oEntryBuf.rBody.Split.P1; + //TxMsg.Data.Data[4] = oEntryBuf.rBody.Split.Prm; + //TxMsg.Data.Data[5] = oEntryBuf.rBody.Split.dType; + //TxMsg.Data.Data[6] = oEntryBuf.rBody.Split.Prm1; + //TxMsg.Data.Data[7] = oEntryBuf.rBody.Split.Prm2; + + + //eOperateEvent.Splite.P0 = aY; + //eOperateEvent.Splite.P1 = aM; + //eOperateEvent.Splite.P2 = aD; + //eOperateEvent.Splite.Data1 = aH; + //eOperateEvent.Splite.iByte0 = aMin; + //eOperateEvent.Splite.iByte1 = aSec; + } + }else + if(aEt == otMask){ + Dm.D8[0] = RecUserCodeAreaNum[Data[1]].UC.Bytes[0]; + Dm.D8[1] = Data[0]; + Dm.D8[2] = Data[4]; + Dm.D8[3] = Data[7]; + MasterDoAddRemoveMask(Data[1], Data[2], Data[3], Data[5], Dm.D32, 1); + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); + + OperateEntry.Splite.mType = etOperate; + OperateEntry.Splite.Data0 = otMask; + OperateEntry.Splite.dType = Data[5]; + OperateEntry.Splite.UserCode = Dm.D32; + }else + if(aEt == otUnMask){ + Dm.D8[0] = RecUserCodeAreaNum[Data[1]].UC.Bytes[0]; + Dm.D8[1] = Data[0]; + Dm.D8[2] = Data[4]; + Dm.D8[3] = Data[7]; + MasterDoAddRemoveMask(Data[1], Data[2], Data[3], Data[5], 0, 0); + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); + + OperateEntry.Splite.dType = Data[5]; + OperateEntry.Splite.mType = etOperate; + OperateEntry.Splite.Data0 = otUnMask; + OperateEntry.Splite.UserCode = Dm.D32; + }else + if(aEt == otUserCheck){ + if(Data[2]){ + NwIsNormalCheck |= 1 << Data[1]; + }else{ + NwIsNormalCheck &= ~(1< dNETWORK_MACHINE_COUNT)return; + if(aP0 > dPORT_MAX_COUNT)return; + + NumOffSet = (static_cast(aNum)) * 40960; + P0OffSet = (static_cast(aP0)) * 1024; + P1OffSet = (static_cast(aP1)) * 4; + + aAddr = dAddrSdram_NwFireIdf + NumOffSet + P0OffSet + P1OffSet; + *(volatile unsigned int *)aAddr = Sta; +} + +unsigned int TProtoC2C::GetNwFire(unsigned char aNum, unsigned char aP0, unsigned char aP1) +{ + unsigned int aAddr; + unsigned int NumOffSet, P0OffSet, P1OffSet; + unsigned int aSta; + if(aNum > dNETWORK_MACHINE_COUNT)return 0; + if(aP0 > dPORT_MAX_COUNT)return 0; + + NumOffSet = (static_cast(aNum)) * 40960; + P0OffSet = (static_cast(aP0)) * 1024; + P1OffSet = (static_cast(aP1)) * 4; + + aAddr = dAddrSdram_NwFireIdf + NumOffSet + P0OffSet + P1OffSet; + aSta = *(volatile unsigned int *)aAddr; + return aSta; +} + +void TProtoC2C::ClearNwCtlFire(unsigned char aNum) +{ + unsigned int aAddr; + unsigned int NumOffSet, i; + if(aNum > dNETWORK_MACHINE_COUNT)return; + + NumOffSet = (static_cast(aNum)) * 40960; + + aAddr = dAddrSdram_NwFireIdf + NumOffSet; + for(i=0; i<10240; i++){ + *(volatile unsigned int *)aAddr = 0; + aAddr += 4; + } +} + +void TProtoC2C::ClearNwAllCtlFire() +{ + unsigned int i; + for(i=1; i<=dNETWORK_MACHINE_COUNT; i++)ClearNwCtlFire(i); +} + +void TProtoC2C::IdfCmdExternFill(unsigned char aCmd, unsigned char aPrm) +{ + CmdFillAreaNum =0; + CmdFillDelayTime =0; + CmdFillUserCode =0; + + if(aCmd == cmPublishAlram){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + }else + if(aCmd == cmTakeChargeAlram){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + }else + if(aCmd == cmConfirmAlram){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + }else + if(aCmd == cmAutoStart){ + if(aPrm){ + //Start Delay + CmdFillDelayTime =1; + CmdFillUserCode =1; + }else{ + //Start + CmdFillAreaNum =1; + CmdFillUserCode =1; + } + }else + if(aCmd == cmAutoStop){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + }else + if(aCmd == cmAck){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + }else + if(aCmd == cmAckStop){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + }else + if(aCmd == cmPortModuleErr){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + }else + if(aCmd == cmPortModuleErrRecover){ + CmdFillAreaNum =1; + CmdFillUserCode =1; + } +} + +void TProtoC2C::GetFireRemoteConfirm(unsigned char *Data) +{ + unsigned char aEt; + TDMix Dm; + TDMix16 Dm16; + + if(MainCtl.fData.Split.NetworkMode == 0)return; + + if( (Data[1] == 0) || (Data[1] > 32) ) return; + OperateEntry.Splite.Year = RecDateTime[Data[1]].Dt.Year; + OperateEntry.Splite.Month = RecDateTime[Data[1]].Dt.Mon; + OperateEntry.Splite.Day = RecDateTime[Data[1]].Dt.Day; + OperateEntry.Splite.Hour = RecDateTime[Data[1]].Dt.Hour; + OperateEntry.Splite.Minute = RecDateTime[Data[1]].Dt.Min; + OperateEntry.Splite.Second = RecDateTime[Data[1]].Dt.Sec; + + OperateEntry.Splite.PCtlNum = Data[0]; + OperateEntry.Splite.P0 = Data[2]; + OperateEntry.Splite.P1 = Data[3]; + OperateEntry.Splite.mType = Data[4]; + OperateEntry.Splite.iByte0 = Data[5]; + OperateEntry.Splite.Data0 = Data[6]; + OperateEntry.Splite.Data1 = Data[7]; + + Dm.D8[0] = Data[0]; + Dm.D8[1] = Data[2]; + Dm.D8[2] = Data[3]; + Dm.D8[3] = 0; + CtlCenter.ieFireMsgConfAddr(Dm.D32); + CtlCenter.ieMsgFire.ReflashIndex++; + CtlCenter.ieGot = 1; + + OperateEntry.Splite.PCtlNum = Data[7]; + OperateEntry.Splite.P0 = Data[2]; + OperateEntry.Splite.P1 = Data[3]; + OperateEntry.Splite.P2 = Data[1]; + OperateEntry.Splite.dType = Data[5]; + OperateEntry.Splite.Data1 = Data[0]; + + OperateEntry.Splite.mType = etOperate; + OperateEntry.Splite.Data0 = otFireRemoteConfirm; +} + +void TProtoC2C::GetFaultRemoteConfirm(unsigned char *Data) +{ + unsigned char aEt; + TDMix Dm; + TDMix16 Dm16; + + if(MainCtl.fData.Split.NetworkMode == 0)return; + + if( (Data[1] == 0) || (Data[1] > 32) ) return; + OperateEntry.Splite.Year = RecDateTime[Data[1]].Dt.Year; + OperateEntry.Splite.Month = RecDateTime[Data[1]].Dt.Mon; + OperateEntry.Splite.Day = RecDateTime[Data[1]].Dt.Day; + OperateEntry.Splite.Hour = RecDateTime[Data[1]].Dt.Hour; + OperateEntry.Splite.Minute = RecDateTime[Data[1]].Dt.Min; + OperateEntry.Splite.Second = RecDateTime[Data[1]].Dt.Sec; + + OperateEntry.Splite.PCtlNum = Data[0]; + OperateEntry.Splite.P0 = Data[2]; + OperateEntry.Splite.P1 = Data[3]; + OperateEntry.Splite.mType = Data[4]; + OperateEntry.Splite.iByte0 = Data[5]; + OperateEntry.Splite.Data0 = Data[6]; + OperateEntry.Splite.Data1 = Data[7]; + + if((MainCtl.fData.Split.NetworkMode == 2) && (OperateEntry.Splite.PCtlNum != MainCtl.fData.Split.MyNum))return; + + Dm.D8[0] = Data[0]; + Dm.D8[1] = Data[2]; + Dm.D8[2] = Data[3]; + Dm.D8[3] = 0; + CtlCenter.ieFaultMsgFaultConfAddr(Dm.D32); + CtlCenter.ieMsgFault.ReflashIndex++; + CtlCenter.ieGot = 1; + + OperateEntry.Splite.PCtlNum = Data[0]; + OperateEntry.Splite.P0 = Data[2]; + OperateEntry.Splite.P1 = Data[3]; + OperateEntry.Splite.P2 = Data[4]; + OperateEntry.Splite.dType = Data[5]; + OperateEntry.Splite.Data0 = Data[6]; + OperateEntry.Splite.Data1 = Data[7]; + + OperateEntry.Splite.mType = etOperate; + OperateEntry.Splite.Data0 = otFaultRemoteConfirm; +} + +void TProtoC2C::sSimGetStartDelay(TRecordCommon *aRc, unsigned short aDelayTimes) +{ + aRc->Splite.P2 = 0; + if(aRc->Splite.P0 == 0){ + + }else + if(aRc->Splite.P0 <= dPORT_MAX_COUNT){ + aRc->Splite.mType = etLinkageStart; + aRc->Splite.iByte0 = 0x0A; + aRc->Splite.Data1 = TControlCenter::StartTypeSimulate; + sSetNwDevDelayStartPoint(aRc->Splite.PCtlNum, aRc->Splite.P0, aRc->Splite.P1, aDelayTimes); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartSimulate(*aRc); + } + }else + if( (aRc->Splite.P0 >= dADDR_DIRECTPAD_START) && (aRc->Splite.P0 <= dADDR_DIRECTPAD_END) ){ + aRc->Splite.mType = etLinkageStart; + aRc->Splite.iByte0 = 0x0A; + aRc->Splite.Data1 = TControlCenter::StartTypeSimulate; + sSetNwDirectPadDelayStartPoint(aRc->Splite.PCtlNum, aRc->Splite.P0 - dADDR_DIRECTPAD_START + 1, aRc->Splite.P1, aDelayTimes); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStartSimulate(*aRc); + } + } +} + + +void TProtoC2C::Task10Ms() +{ + if(MainCtl.fData.Split.NetworkMode == 0)return; + ProcessoEntry(); + oBufProcess(); + + if(MainCtl.fData.Split.NetworkMode == 1)MasterDoCheckOnlineTask(); + else if(MainCtl.fData.Split.NetworkMode == 2)SlaveDoCheckOnlineTask(); + + if(NeedReply){ + if(ReplyWhat == dNetworkRpyType){ + ReplyCtrlType(); + }else + if(ReplyWhat == dNetworkRpyDescp){ + ReplyDescp(); + } + } +} + + + + + + + + + + + diff --git a/MyCode/src/ProtoC2C.h b/MyCode/src/ProtoC2C.h new file mode 100644 index 0000000..bfe342e --- /dev/null +++ b/MyCode/src/ProtoC2C.h @@ -0,0 +1,719 @@ +#ifndef PROTOC2C_H_ +#define PROTOC2C_H_ + +#include "gvalue.h" +#include "gType.h" +#include "ProtoInnerCan.h" +#include "TDateTime.h" +#include "record.h" +#include "ProtoM2M.h" + +#define dNetworkInBufMaxLength 1024 + +#define OutputEntrySize 24 +//(0xC1900000) +#define dNetworkOutEntryBufFireMaxLength 16000 +#define dNetworkOutEntryBufSvMaxLength 8000 +#define dNetworkOutEntryBufLinkMaxLength 8000 +#define dNetworkOutBufMaxLength 10000 + +//(0xC1A00000) +#define dNetworkOutEntryBufFaultMaxLength 20000 +#define dNetworkOutEntryBufNormalMaxLength 16000 +#define dNetworkOutEntryBufBasicServiceMaxLength 5000 + + +#define dNetworkCmd 251 +#define dNetworkCmd_ReqDateTime 252 +#define dNetworkCmd_SetDateTime 253 +#define dNetworkCmd_EventTime 254 +#define dNetworkCmd_DevDescp 255 + +#define dNetworkCmd_PublishOperate 250 +#define dNetworkCmd_Ack 249 + +#define dNetworkCmd_PortExistAsk 248 +#define dNetworkCmd_PortExistRpy 247 +#define dNetworkCmd_DescpAsk 246 +#define dNetworkCmd_DescpRpy 245 +#define dNetworkCmd_DescpOnePortAsk 244 + +#define dNetworkCmd_CheckNormalData 225 +#define dNetworkCmd_CheckOnline 224 +#define dNetworkCmd_SlaveFbMissReport 223 +#define dNetworkCmd_DelayStartSend 222 +#define dNetworkCmd_MaskListSend 221 + +#define dNetworkCmd_ClearCtlFire 214 +#define dNetworkCmd_PublishFireCancel 213 +#define dNetworkCmd_PublishFire 212 +#define dNetworkCmd_RemoteStartStop 211 +#define dNetworkCmd_RemoteStartStopViaUserCode 210 +#define dNetworkCmd_NewTime 209 + +#define dNetworkCmd_AutoStartDelay 208 +#define dNetworkCmd_SetSlaveAllow 207 +#define dNetworkCmd_SendRegSeq 206 +#define dNetworkCmd_SendRegRpy 205 + +#define dNetworkCmd_AutoStartDelaySimulate 204 +#define dNetworkCmd_RemoteStartStopViaUserCodeSimulate 203 + + +#define dNetworkRpyType 0x02 +#define dNetworkRpyDescp 0x04 + +#define dNetworkTypeMaster 0x01 +#define dNetworkTypeSlave 0x02 +#define dNetworkTypeNone 0x03 +#define dNetworkTypeDual 0x04 + +typedef enum{ + CmdC2C_AskExist = 1, + CmdC2C_RpyExist = 2, + CmdC2C_AskType = 3, + CmdC2C_RpyType = 4, + CmdC2C_AskNameLen = 5, + CmdC2C_RpyNameLen = 6, + CmdC2C_AskNameContent = 7, + CmdC2C_RpyNameContent = 8, + CmdC2C_SaveData = 9, + CmdC2C_ClearReg = 10, + CmdC2C_DevRegStartSeq = 11, + CmdC2C_DevRegRpyStart = 12, + CmdC2C_DevRegRpyPortCnt = 13, + CmdC2C_DevRegRpyProgress = 14, + CmdC2C_DevRegRpyEpCount = 15, + CmdC2C_DevRegRpyEpCompleted =16, + CmdC2C_DevRegReqEpCount =17, + CmdC2C_DevRegEpCountCorrect, + CmdC2C_SaveMasterList, + CmdC2C_ClearMasterList, +}TSubCmdC2C; + +typedef union{ + unsigned int D32[4]; + unsigned char D8[16]; + struct{ + unsigned char Cmd; + unsigned char Order; + unsigned char CarryByte; + unsigned char Mix3Data; + + unsigned char Len; + unsigned char Identification; + unsigned char Routing; + unsigned char Priority; + + unsigned char Data[8]; + }Data; +}TC2CBufBody; + +typedef struct{ + int Count; + int WriteIndex; + int ReadIndex; + TC2CBufBody Body[dNetworkInBufMaxLength]; +}TC2CInOutBuf; + +typedef union{ + unsigned int D32[6]; + unsigned short D16[12]; + unsigned char D8[24]; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char iByte0; + unsigned char iByte1; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char mType; + unsigned char dType; + unsigned char Data0; + unsigned char Data1; + + unsigned int UserCode; + unsigned short AreaNum; + unsigned short DumpShort; + }Splite; +}TC2CMsgCommon; + +typedef struct{ + union{ + unsigned int D32[6]; + unsigned char D8[24]; + struct{ + unsigned char Cmd; + unsigned char CtlNum; + unsigned char P0; + unsigned char P1; + + unsigned char dType; + unsigned char mType; + unsigned char sType; + unsigned char Prm; + + unsigned char Year; + unsigned char Mon; + unsigned char Day; + unsigned char Hour; + + unsigned char Min; + unsigned char Sec; + unsigned char Prm1; + unsigned char Prm2; + + unsigned int UserCode; + unsigned short AreaNum; + unsigned short DumpShort; + }Split; + }rBody,wBody; +}TC2CEntry; + +template +struct TC2cEntryBuf{ + int Count; + int WriteIndex; + int ReadIndex; + void Reset(){ + unsigned int OffSet; + WriteIndex=0; + ReadIndex=0; + for(int i=0; i=BufSize)WriteIndex =0; + return dAddrSdram_C2cOutEntrySvBuf + (EntrySize * WriteIndex); + } + unsigned int IncReadIndex(){ + ReadIndex++; + if(ReadIndex >=BufSize)ReadIndex =0; + return dAddrSdram_C2cOutEntrySvBuf + (EntrySize * ReadIndex); + } + int CheckDataAvalibel(){ + if(ReadIndex!=WriteIndex)return 1; else return 0; + } + void Write(unsigned int *pEty){ + WriteIndex++; + if(WriteIndex >=BufSize)WriteIndex =0; + unsigned int OffSet =WriteIndex * EntrySize; + *(volatile unsigned int *)(BaseAddr + OffSet + 0) =*pEty++; + *(volatile unsigned int *)(BaseAddr + OffSet + 4) =*pEty++; + *(volatile unsigned int *)(BaseAddr + OffSet + 8) =*pEty++; + *(volatile unsigned int *)(BaseAddr + OffSet + 12) =*pEty++; + *(volatile unsigned int *)(BaseAddr + OffSet + 16) =*pEty++; + *(volatile unsigned int *)(BaseAddr + OffSet + 20) =*pEty; + } + void Read(unsigned int *pEty){ + ReadIndex++; + if(ReadIndex >=BufSize)ReadIndex =0; + unsigned int OffSet =ReadIndex * EntrySize; + *pEty++ = *(volatile unsigned int *)(BaseAddr + OffSet + 0) ; + *pEty++ = *(volatile unsigned int *)(BaseAddr + OffSet + 4) ; + *pEty++ = *(volatile unsigned int *)(BaseAddr + OffSet + 8) ; + *pEty++ = *(volatile unsigned int *)(BaseAddr + OffSet + 12) ; + *pEty++ = *(volatile unsigned int *)(BaseAddr + OffSet + 16) ; + *pEty = *(volatile unsigned int *)(BaseAddr + OffSet + 20) ; + } +}; + +class TProtoC2C{ + public: + enum TMsgType{ + mtBasicService =0, + mtFire =1, + mtSv =2, + mtLink =3, + mtFault =4, + mtNormal =5, + }; + static unsigned int DevDelayStartTick; + public: + struct{ + unsigned int started; + unsigned char *pData; + unsigned int Len; + unsigned int BlockCount; + unsigned int SectionCount; + }File; + unsigned int CheckOnlineHasSend; + unsigned int CheckOnlineAfterSendTick; + unsigned int CheckOnlineTick; + unsigned int CheckOnlineHasStart; + unsigned int CheckOnlineUpdateTick; + + unsigned char NwSubCmd; + unsigned int ErrReport; + unsigned int ErrHasReport; + unsigned int iBufInCount; + unsigned int iBufInCountPer2Sec; + unsigned int iBufInCountOdd; + + int NeedReply; + unsigned char ReplyWhat; + unsigned char ReplyTick; + + TC2CBufBody RxMsg; + TC2CBufBody TxMsg; + TRecordMaskMsg MaskMsg; + + volatile TC2CInOutBuf iBuf; + volatile struct{ + int Count; + int WriteIndex; + int ReadIndex; + TC2CBufBody aBody; + }oBuf; + TC2cEntryBuf oEntryBasicService; + TC2cEntryBuf oEntryFire; + TC2cEntryBuf oEntrySv; + TC2cEntryBuf oEntryLink; + TC2cEntryBuf oEntryFault; + TC2cEntryBuf oEntryNormal; + + TC2CEntry oEntry; + + unsigned char SlaveOnlineList[68]; + unsigned char SlaveOnlineListOld[68]; + union{ + unsigned int D32[3]; + unsigned char D8[12]; + struct{ + unsigned char Inx; + unsigned char CtlNum; + unsigned char Year ; + unsigned char Mon; + unsigned char Day; + unsigned char Hour; + + unsigned char Min; + unsigned char Sec; + + unsigned char Dump2; + unsigned char Dump3; + unsigned char Dump4; + unsigned char Dump5; + }Dt; + }RecDateTime[68]; + + struct{ + union{ + unsigned int Full; + unsigned char Bytes[4]; + }UC; + union{ + unsigned short Full; + unsigned char Bytes[2]; + }AN; + unsigned short DumpShort; + }RecUserCodeAreaNum[68]; + + union{ + unsigned int D32[3]; + unsigned char D8[12]; + struct{ + unsigned char Inx; + unsigned char CtlNum; + unsigned char Year ; + unsigned char Mon; + unsigned char Day; + unsigned char Hour; + + unsigned char Min; + unsigned char Sec; + + unsigned char Dump2; + unsigned char Dump3; + unsigned char Dump4; + unsigned char Dump5; + }Dt; + }RecNewDateTime[68]; + + struct{ + unsigned char State[68]; + unsigned char AckOk[68]; + unsigned char DesireAckOrder[68]; + unsigned char OnGoing; + unsigned char Order; + unsigned char RetryTimes; + unsigned char Dump0; + unsigned int TimeOutTick; + unsigned char AckNeedCount; + unsigned char IsReportErr; + unsigned char IsBroadCast; + unsigned char SlaveCtlNum; + }OnTransmite; + + struct{ + unsigned char State[68]; + unsigned char IsProcessDone[68]; + unsigned char RecOnGoing[68]; + unsigned int Piece[68]; + unsigned char OrderDt[68]; + unsigned char OrderAck[68]; + unsigned char OrderNewDt[68]; + unsigned char OrderLast[68]; + unsigned char OnGoing; + unsigned char IsCheckOnline; + unsigned char CallResetCtlNum; + unsigned char CallResetNetOrder; + }OnReceive; + + unsigned char NoAckList[68]; + unsigned char NoAckMaster; + + struct{ + unsigned char CtlNum; + unsigned char P0; + unsigned char P1; + unsigned char Dump; + union{ + unsigned int D32[64]; + unsigned char D8[256]; + }dType; + union{ + unsigned int D32[8]; + unsigned char D8[32]; + }Descp; + unsigned int DescpPiece; + unsigned int dTypePiece; + }OnSetup; + + union{ + unsigned int D32[8]; + unsigned char D8[32]; + }DescpBuf, DescpBufRec; + + unsigned int State; + unsigned char tData[8]; + + TC2CMsgCommon OperateEntry; + + unsigned char MasterNum; + unsigned char SlaveCount; + unsigned char SlaveList[68]; + + unsigned char CommLostCount[68]; + + struct{ + unsigned int Cnt; + unsigned char Items[dNETWORK_MACHINE_MASTER_COUNT]; + }M2MList; + + struct{ + unsigned int IsFbMiss; + unsigned int IsVaStart; + unsigned int IsVaFault; + }SlaveCtlState; + + unsigned int MasterRetrySendEntryCount; + unsigned int SlaveRetrySendEntryCount; + + union{ + unsigned int D32[60]; + unsigned short D16[120]; + unsigned char D8[240]; + struct{ + struct{ + unsigned short Smoke; + unsigned short Tempe; + unsigned short HandReport; + unsigned short HydKp; + unsigned short ModuleInput; + unsigned short ModuleInOut; + unsigned short ModuleOutput; + unsigned short Va; + unsigned short FDisplay; + unsigned short LnkPs; + unsigned short cOther; + }Designed; + struct{ + unsigned short Smoke; + unsigned short Tempe; + unsigned short HandReport; + unsigned short HydKp; + unsigned short ModuleInput; + unsigned short ModuleInOut; + unsigned short ModuleOutput; + unsigned short Va; + unsigned short FDisplay; + unsigned short LnkPs; + unsigned short cOther; + }Normal; + + struct{ + unsigned short Smoke; + unsigned short Tempe; + unsigned short HandReport; + unsigned short HydKp; + unsigned short ModuleInput; + unsigned short ModuleInOut; + unsigned short ModuleOutput; + unsigned short Va; + unsigned short FDisplay; + unsigned short LnkPs; + unsigned short cOther; + }Fault; + struct{ + unsigned short Smoke; + unsigned short Tempe; + unsigned short HandReport; + unsigned short HydKp; + unsigned short ModuleInput; + unsigned short ModuleInOut; + unsigned short ModuleOutput; + unsigned short Va; + unsigned short FDisplay; + unsigned short LnkPs; + unsigned short cOther; + }Mask; + }Slave; + }CheckNormalDataSlave[dNETWORK_MACHINE_COUNT]; + unsigned int CheckNormalDataSlaveGotPiece[dNETWORK_MACHINE_COUNT]; + unsigned char IsCheckNormalDataSlaveDone[dNETWORK_MACHINE_COUNT]; + + unsigned int ShouldSyncTime ; + + unsigned char ReportSlaveOffline[68]; + unsigned char ReportMasterOffline; + + struct{ + unsigned char StartNum; + unsigned char EndNum; + }CtlMask; + struct{ + unsigned char StartNum; + unsigned char EndNum; + }RegMask; + int NeedRpyCount; + struct{ + unsigned char CtlCount; + unsigned char CtlList[68]; + }CfgData; + struct{ + struct{ + unsigned char IsRequsting; + unsigned char RegPath; + }Reg; + }RemoteReq; + private: + TRecordCommon sIm; + unsigned char CmdFillAreaNum; + unsigned char CmdFillDelayTime; + unsigned char CmdFillUserCode; + + unsigned char IsRecAreaNum; + unsigned char IsRecDelayTime; + unsigned char IsRecUserCode; + + public: + TProtoC2C(){}; + void Init(); + void ReInit(); + void DelayMs(unsigned int aMs); + + void PublishEventMute(); + void PublishEventReset(); + + void DateTimeReq(); + void DateTimeSet(); + + void ReplyCtrlType(); + void ReplyDescp(); + void SaveCfgData(unsigned char *data); + void ClearCfgData(unsigned char *data); + void SaveM2MCfgData(unsigned char *data); + void ClearM2MCfgData(unsigned char *data); + + void SetNwFire(unsigned char aNum, unsigned char aP0, unsigned char aP1, unsigned int Sta); + unsigned int GetNwFire(unsigned char aNum, unsigned char aP0, unsigned char aP1); + + void MasterRxMsgProcess(); + void SlaveRxMsgProcess(); + void oBufInsert(); + void oBufInsert(TC2CBufBody aNsBuf); + void iBufInsert(); + void iBufProcess(); + void oBufProcess(); + + void oBufMsgPreload(TRecordCommon aIm, unsigned char aCmd); + + void oBufMsgInsertBasicService(); + void oBufMsgInsertFire(); + void oBufMsgInsertSv(); + void oBufMsgInsertLink(); + void oBufMsgInsertFault(); + void oBufMsgInsertNormal(); + void oBufMsgInsertBasicService(TRecordCommon aIm, unsigned char aCmd); + void oBufMsgInsertFire(TRecordCommon aIm, unsigned char aCmd); + void oBufMsgInsertSv(TRecordCommon aIm, unsigned char aCmd); + void oBufMsgInsertLink(TRecordCommon aIm, unsigned char aCmd); + void oBufMsgInsertFault(TRecordCommon aIm, unsigned char aCmd); + void oBufMsgInsertNormal(TRecordCommon aIm, unsigned char aCmd); + + void NwDevDescpInit(); + void BufInit(); + + void FillDescp(); + void ProcessDevDescpRec(); + void PublishEventAlramOnOff(int aOnOff); + void PublishReset(); + void PublishMute(); + void PublishEventAllowState(); + void PublishOperate(TRecordCommon aOperateEvent); + + void OperateGet(unsigned char aCmd, unsigned char *Data); + + void WriteEntryBuf(); + void ReadEntryBuf(); + void ExportMachineEventTime2Master(unsigned char IsNew); + void ExportMachineEventNewTime2Master(unsigned char IsNew); + void ExportEntry2oBuf(unsigned char IsNew); + void ProcessoEntry(); + void Ack(unsigned char TargetNum, unsigned char aOrder); + void AckOnlineCheck(unsigned char TargetNum, unsigned char aOrder); + void ProcessAckRecFromSlave(unsigned char aOrder, unsigned char *Data); + void ProcessAckRecFromMaster(unsigned char aOrder, unsigned char *Data); + + void MasterDoEpMsg(unsigned char aCmd, unsigned char *Data); + void MasterDoDirectPadNwPutLnkState(unsigned char aCmd, unsigned char *Data); + void MasterDoMaskAdd(int aInx); + void MasterDoMaskAdd(TRecordMaskMsg aMaskMsg, int aInx); + void MasterDoMaskListGet(unsigned char *Data); + void MasterDoAddRemoveMask(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc, unsigned int IsAdd); + void GetMsgViaIndex(int aInx); + void ClearMsgViaIndex(int aInx); + void MasterDoMaskListRemove(unsigned char aCtlNum); + void MasterDoCheckOnlineTask(); + void CheckNormalSlave(unsigned char aCtlNum); + void MasterGetCheckNormalData(unsigned char *Data); + void MasterDoDevRemoteStart(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType); + void MasterDoRemoteLnkStartStopViaUserCode(unsigned int aUc, unsigned char aType, unsigned short aDelaySec, unsigned char IsStart); + void MasterDoPublishFire(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc); + void MasterDoPublishFireCancel(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc); + void MasterDoPublishClearNwCtlFire(unsigned char CtlNum); + + void SlaveDoAlramOnOff(int aOnOff); + void SlaveDoSend2MasterMachine(TRecordCommon aIm, unsigned char aCmd, TMsgType aMsgType); + void SlaveDoUploadMaskList(); + void SlaveDoUploadCtlState(); + void SlaveDoUploadStartDelay(); + void SlaveReportFbMissCount(unsigned char aFbCnt); + void SlaveDoCheckOnlineTask(); + void ClearCheckNormalDataSlave(); + void SlaveDoRpyCheckNormalData(); + void SlaveDoGetRemoteStartStop(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char IsStart); + void SlaveDoGetRemoteStartStopUserCode(unsigned int aUc, unsigned char aDType, unsigned short aDelaySec, unsigned char IsStart); + void SlaveDoNetDescpRpy(unsigned char aCtlNum, unsigned char aP0); + void SlaveDoSend2MasterDelayStart(TRecordCommon aIm, unsigned char aCmd); + + void SlaveSetAutoState(unsigned char aSta); + void SlaveSetManualState(unsigned char aSta); + void SlaveSetAllowState(unsigned char aSta); + void SlaveSetAllowStateBySpc(unsigned char CtlNum, unsigned char aSta); + + void PortExistAsk(unsigned char aNum, unsigned char aP0); + void DescpListAsk(unsigned char aNum, unsigned char aP0, unsigned char Inx, unsigned char *pAddrList); + void PortExistRpy(unsigned char aNum, unsigned char aP0); + void DescpListRpy(unsigned char aNum, unsigned char aP0, unsigned char Addr); + void DescpListDirectPadRpy(unsigned char aNum, unsigned char aPadNum, unsigned char aKey); + void DescpListDirectPadRpy(unsigned char aNum, unsigned char Inx); + + void DescpOnePortAsk(unsigned char aNum, unsigned char aP0); + void DescpOnePortRpy(unsigned char aNum, unsigned char aP0); + void DescpAllDirectPadRpy(unsigned char aNum); + + void AddRemoveNwCommFault(unsigned char aCtlNum, unsigned int IsAdd); + void AddMasterCommFault(unsigned char aCtlNum); + void RemoveMasterCommFault(unsigned char aCtlNum); + void AddSlaveCommFault(unsigned char aCtlNum); + void RemoveSlaveCommFault(unsigned char aCtlNum); + void ResetCoomm(); + void CheckInBufCount(); + + void ClearNwCtlFire(unsigned char aNum); + void ClearNwAllCtlFire(); + + static void sSetNwDevDelayStartPoint(unsigned char aNum, unsigned char aP0, unsigned char aP1, unsigned int aCountDown); + unsigned int GetNwDevDelayCountDown(unsigned char aNum, unsigned char aP0, unsigned char aP1); + static void sSetNwDirectPadDelayStartPoint(unsigned int aNum, unsigned int aDirectPad, unsigned int aNode, unsigned int TickZeroPoint); + unsigned int GetNwDirectPadDelayStartPoint(unsigned int aNum, unsigned int aDirectPad, unsigned int aNode); + void ClearNwDelayStartPoint(unsigned int aNum); + + unsigned int GetThisCtlCountDownTime(unsigned int aNum, unsigned int aP0, unsigned int aP1); + + void WriteMaskCtlNum(unsigned char aStart, unsigned char aEnd); + void ReadMaskCtlNum(); + + void IdfCmdExternFill(unsigned char aCmd, unsigned char aPrm); + + + void GetFireRemoteConfirm(unsigned char *Data); + void GetFaultRemoteConfirm(unsigned char *Data); + void OperatePublic_FireRemoteConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char dType, unsigned int aUc); + void OperatePublic_FaultRemoteConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char dType, unsigned char fType, unsigned char aIsDescp, unsigned int aUc); + + int CheckIsInSlaveList(unsigned char aCn); + void SyncCheckOnline(); + + void SlaveDoSend2MasterDelayStartSimulate(TRecordCommon aIm, unsigned char aCmd); + void SlaveDoGetRemoteStartStopUserCodeSimulate(unsigned int aUc, unsigned char aDType, unsigned short aDelaySec, unsigned char IsStart); + void MasterDoRemoteLnkStartStopViaUserCodeSimulate(unsigned int aUc, unsigned char aType, unsigned short aDelaySec, unsigned char aSta); + + int TryLoadNewEntry(); + + static void sSimGetStartDelay(TRecordCommon *aRc, unsigned short aDelayTimes); + + void SyncCheckM2MOnline(){}//_____________________< + + void TaskSecondUpdate(); + void Task10Ms(); + void Task1000Ms(); +}; + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/ProtoC2cMasterDo.cpp b/MyCode/src/ProtoC2cMasterDo.cpp new file mode 100644 index 0000000..59f6fc9 --- /dev/null +++ b/MyCode/src/ProtoC2cMasterDo.cpp @@ -0,0 +1,735 @@ +#include "ProtoInnerCan.h" +#include "ProtoC2C.h" + +#include "CnCpp.h" +#include "record.h" +#include "Runtime.h" +#include "server.h" + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" +} + +void TProtoC2C::MasterDoEpMsg(unsigned char aCmd, unsigned char *Data) +{ + int i; + unsigned char aCn, aP0, aP1; + + aCn = Data[1]; + aP0 = Data[2]; + aP1 = Data[3]; + + if( (aCn == 0) || (aCn >dNETWORK_MACHINE_COUNT) )return; + if( (aP0 <1) || (aP0 >dPORT_MAX_COUNT) )return; + if( (aP1 <1) || (aP1 >dEP_MAX_COUNT_PER_PORT) )return; + + if(aCmd == cmAutoStart){ + sIm.Splite.mType = etLinkageStart; + sIm.Splite.iByte0 = 0x01; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(sIm); + } + }else + if(aCmd == cmAutoStop){ + sIm.Splite.mType = etLinkageStart; + //sIm.Splite.iByte0 = 0x09; //make Msg Show On eventshow + if(CtlCenter.IsMsgReseting == 0){ + //CtlCenter.iePushOneMsgLinkageStart(sIm); //make Msg Show On eventshow + CtlCenter.iePushOneMsgLinkageStartCancel(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + sIm.Splite.iByte0 = 0xB1; + Record.LinkageAdd(sIm); + } + }else + if(aCmd == dNetworkCmd_AutoStartDelay){ + sIm.Splite.mType = etLinkageStart; + sIm.Splite.iByte0 = 0x0A; + unsigned short aDl; + aDl = RxMsg.Data.CarryByte; + aDl &= 0x000F; + aDl <<= 8; + aDl |= RxMsg.Data.Data[4]; + sSetNwDevDelayStartPoint(RxMsg.Data.Data[1], RxMsg.Data.Data[2], RxMsg.Data.Data[3], aDl); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(sIm); + } + }else + if(aCmd == cmAck){ + sIm.Splite.mType = etLinkageFeedBack; + sIm.Splite.iByte0 = 0x03; + if(CtlCenter.IsMsgReseting == 0){ + Record.LinkageAdd(sIm); + CtlCenter.iePushOneMsgLinkageFb(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + } + }else + if(aCmd == cmAckStop){ + sIm.Splite.mType = etLinkageFeedBack; + sIm.Splite.iByte0 = 0xB3; + if(CtlCenter.IsMsgReseting == 0){ + Record.LinkageAdd(sIm); + CtlCenter.iePushOneMsgLinkageFbCancel(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + } + } +} + +void TProtoC2C::MasterDoDirectPadNwPutLnkState(unsigned char aCmd, unsigned char *Data) +{ + int i; + unsigned char aCn, aP0, aNode; + + aCn = Data[1]; + aP0 = Data[2]; + aNode = Data[3]; + + if( (aCn == 0) || (aCn >dNETWORK_MACHINE_COUNT) )return; + if( (aP0 dADDR_DIRECTPAD_END) )return; + if( (aNode <1) || (aNode >dDIRECTCTL_KEY_MAX_COUNT) )return; + + sIm.Splite.Year = ProtoC2C.RecDateTime[Data[1]].Dt.Year; + sIm.Splite.Month = ProtoC2C.RecDateTime[Data[1]].Dt.Mon; + sIm.Splite.Day = ProtoC2C.RecDateTime[Data[1]].Dt.Day; + sIm.Splite.Hour = ProtoC2C.RecDateTime[Data[1]].Dt.Hour; + sIm.Splite.Minute = ProtoC2C.RecDateTime[Data[1]].Dt.Min; + sIm.Splite.Second = ProtoC2C.RecDateTime[Data[1]].Dt.Sec; + + sIm.Splite.PCtlNum = Data[1]; + sIm.Splite.P0 = Data[2]; + sIm.Splite.P1 = Data[3]; + sIm.Splite.P2 = 0; + sIm.Splite.dType = Data[5]; + + if(aCmd == cmAutoStart){ + sIm.Splite.mType = etLinkageStart; + sIm.Splite.iByte0 = 0x01; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(sIm); + } + }else + if(aCmd == cmAutoStop){ + sIm.Splite.mType = etLinkageStart; + sIm.Splite.iByte0 = 0x09; + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + Record.LinkageAdd(sIm); + } + }else + if(aCmd == dNetworkCmd_AutoStartDelay){ + sIm.Splite.mType = etLinkageStart; + sIm.Splite.iByte0 = 0x0A; + unsigned short aDl; + aDl = RxMsg.Data.CarryByte; + aDl &= 0x000F; + aDl <<= 8; + aDl |= RxMsg.Data.Data[4]; + sSetNwDirectPadDelayStartPoint(RxMsg.Data.Data[1], RxMsg.Data.Data[2] - dADDR_DIRECTPAD_START + 1, RxMsg.Data.Data[3], aDl); + if(CtlCenter.IsMsgReseting == 0){ + CtlCenter.iePushOneMsgLinkageStart(sIm); + } + }else + if(aCmd == cmAck){ + sIm.Splite.mType = etLinkageFeedBack; + sIm.Splite.iByte0 = 0x03; + if(CtlCenter.IsMsgReseting == 0){ + Record.LinkageAdd(sIm); + CtlCenter.iePushOneMsgLinkageFb(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + } + }else + if(aCmd == cmAckStop){ + sIm.Splite.mType = etLinkageFeedBack; + sIm.Splite.iByte0 = 0xB3; + if(CtlCenter.IsMsgReseting == 0){ + Record.LinkageAdd(sIm); + CtlCenter.iePushOneMsgLinkageFbCancel(sIm); + ExRecord.SetStateCodeStart(); + FecBusCRT.SetStateCodeStart(); + } + } +} + +void TProtoC2C::MasterDoMaskAdd(int aInx) +{ + volatile unsigned int sAddr; + sAddr = dAddrSdRam_MsgMask + aInx* 24; + + MaskMsg.Body.iByte0 = 0; + MaskMsg.Body.State = 1; + + *(volatile unsigned int *)(sAddr + 0) = MaskMsg.D32[0]; + *(volatile unsigned int *)(sAddr + 4) = MaskMsg.D32[1]; + *(volatile unsigned int *)(sAddr + 8) = MaskMsg.D32[2]; + *(volatile unsigned int *)(sAddr + 12) = MaskMsg.D32[3]; + *(volatile unsigned int *)(sAddr + 16) = MaskMsg.D32[4]; + *(volatile unsigned int *)(sAddr + 20) = MaskMsg.D32[5]; +} + +void TProtoC2C::MasterDoMaskAdd(TRecordMaskMsg aMaskMsg, int aInx) +{ + volatile unsigned int sAddr; + TRecordMaskMsg tMaskMsg; + + sAddr = dAddrSdRam_MsgMask + aInx* 24; + + tMaskMsg.D32[0] = aMaskMsg.D32[0]; + tMaskMsg.D32[1] = aMaskMsg.D32[1]; + tMaskMsg.D32[2] = aMaskMsg.D32[2]; + tMaskMsg.D32[3] = aMaskMsg.D32[3]; + tMaskMsg.D32[4] = aMaskMsg.D32[4]; + tMaskMsg.D32[5] = aMaskMsg.D32[5]; + + tMaskMsg.Body.iByte0 = 0; + tMaskMsg.Body.State = 1; + + *(volatile unsigned int *)(sAddr + 0) = tMaskMsg.D32[0]; + *(volatile unsigned int *)(sAddr + 4) = tMaskMsg.D32[1]; + *(volatile unsigned int *)(sAddr + 8) = tMaskMsg.D32[2]; + *(volatile unsigned int *)(sAddr + 12) = tMaskMsg.D32[3]; + *(volatile unsigned int *)(sAddr + 16) = tMaskMsg.D32[4]; + *(volatile unsigned int *)(sAddr + 20) = tMaskMsg.D32[5]; +} + +void TProtoC2C::MasterDoMaskListGet(unsigned char *Data) +{ + volatile unsigned int IsFound; + unsigned int FirstNullIndex, Cnt; + volatile int i; + TDMix aAddr; + + if( (Data[2] == 0) || (Data[2] >dPORT_MAX_COUNT) )return; + if( (Data[3] == 0) || (Data[3] >250) )return; + + aAddr.D8[0] = Data[1]; + aAddr.D8[1] = Data[2]; + aAddr.D8[2] = Data[3]; + aAddr.D8[3] = 0; + + IsFound = 0; + if(1){ + for(i=0; i ieMSG_MASK_MAX_COUNT)FirstNullIndex = i; + }else + if( MaskMsg.Body.PCtlNum == aCtlNum ){ + ClearMsgViaIndex(i); + if(FirstNullIndex > ieMSG_MASK_MAX_COUNT){ + FirstNullIndex = i; + } + CtlCenter.ieMsgMask.ReflashIndex++; + CtlCenter.ieGot = 1; + }else{ + if(FirstNullIndex < ieMSG_MASK_MAX_COUNT){ + MasterDoMaskAdd(FirstNullIndex); + ClearMsgViaIndex(i); + FirstNullIndex++; + } + Cnt++; + } + } + CtlCenter.ieMsgMask.Count = Cnt; + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); +} + +void TProtoC2C::MasterDoAddRemoveMask(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc, unsigned int IsAdd) +{ + volatile unsigned int IsFound; + unsigned int FirstNullIndex, Cnt; + volatile int i; + TDMix aAddr; + + if( (aP0 == 0) || (aP0 >dPORT_MAX_COUNT) )return; + if( (aP1 == 0) || (aP1 >250) )return; + + aAddr.D8[0] = aCtlNum; + aAddr.D8[1] = aP0; + aAddr.D8[2] = aP1; + aAddr.D8[3] = 0; + + IsFound = 0; + if(IsAdd){ + for(i=0; i ieMSG_MASK_MAX_COUNT)FirstNullIndex = i; + }else + if( MaskMsg.D32[2] == aAddr.D32 ){ + ClearMsgViaIndex(i); + if(FirstNullIndex > ieMSG_MASK_MAX_COUNT){ + FirstNullIndex = i; + } + CtlCenter.ieMsgMask.ReflashIndex++; + CtlCenter.ieGot = 1; + }else{ + if(FirstNullIndex < ieMSG_MASK_MAX_COUNT){ + MasterDoMaskAdd(FirstNullIndex); + ClearMsgViaIndex(i); + FirstNullIndex++; + } + Cnt++; + } + } + CtlCenter.ieMsgMask.Count = Cnt; + //EventShow.MsgList[4].Count = CtlCenter.ieMsgMask.Count; + //EventShow.MsgList[4].NewCount = CtlCenter.ieMsgMask.Count; + //EventShow.TryGetMaskData(2, 20240428); + } + ExRecord.SetStateCodeMask(); + FecBusCRT.SetStateCodeMask(); +} + +void TProtoC2C::MasterDoCheckOnlineTask() +{ + int i, Num, IsLost; + + CheckOnlineTick++; + if(CheckOnlineHasSend)CheckOnlineAfterSendTick++; + if(CheckOnlineTick > 4000){ + CheckOnlineTick =0; + if( (CheckOnlineHasStart) && (CheckOnlineAfterSendTick > 2000) ){ + IsLost = 0; + for(i=1; i<=dNETWORK_MACHINE_COUNT; i++){ + if(SlaveOnlineList[i] == 0){ + IsLost = 1; + if( ReportSlaveOffline[i] ==0){ + AddMasterCommFault(i); + ReportSlaveOffline[i] = 1; + } + }else{ + if( ReportSlaveOffline[i]){ + RemoveMasterCommFault(i); + ReportSlaveOffline[i] = 0; + } + } + } + + if(IsLost || ErrReport){ + if(ErrHasReport == 0){ + ErrHasReport = 1; + ErrReport = 0; + //AddRemoveNwCommFault(MainCtl.fData.Split.MyNum, 1); + } + }else{ + if(ErrHasReport){ + ErrHasReport = 0; + //AddRemoveNwCommFault(MainCtl.fData.Split.MyNum, 0); + } + } + }else{ + //Network Is Busy + } + + for(i=1; i<=dNETWORK_MACHINE_COUNT; i++){ + SlaveOnlineList[i] = 1; + } + for(i=0; i dNETWORK_MACHINE_COUNT)return; + if( (Data[0]) && (Data[0] < 16)){ + ix = Data[0] * 6 -6; + CheckNormalDataSlave[Data[1]-1].D8[ix +0] = Data[2]; + CheckNormalDataSlave[Data[1]-1].D8[ix +1] = Data[3]; + CheckNormalDataSlave[Data[1]-1].D8[ix +2] = Data[4]; + CheckNormalDataSlave[Data[1]-1].D8[ix +3] = Data[5]; + CheckNormalDataSlave[Data[1]-1].D8[ix +4] = Data[6]; + CheckNormalDataSlave[Data[1]-1].D8[ix +5] = Data[7]; + CheckNormalDataSlaveGotPiece[Data[1]] |= 1<< Data[0]; + } + if(CheckNormalDataSlaveGotPiece[Data[1]] == 0x0000FFFE)IsCheckNormalDataSlaveDone[Data[1]-1] = 1; +} + +void TProtoC2C::MasterDoDevRemoteStart(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char IsSatrt) +{ + oEntry.wBody.Split.Cmd = dNetworkCmd_RemoteStartStop; + + oEntry.wBody.Split.Prm = CtlNum; + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.P0 = aP0; + oEntry.wBody.Split.P1 = aP1; + oEntry.wBody.Split.dType = IsSatrt; + + oBufMsgInsertLink(); +} + +void TProtoC2C::MasterDoRemoteLnkStartStopViaUserCode(unsigned int aUc, unsigned char aType, unsigned short aDelaySec, unsigned char aSta) +{ + oEntry.wBody.Split.Cmd = dNetworkCmd_RemoteStartStopViaUserCode; + + oEntry.wBody.Split.Prm = aSta; //0:Off,1:Match,2:Start,3:DelayStart + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.UserCode = aUc; + oEntry.wBody.Split.dType = aType; + oEntry.wBody.Split.Prm1 = static_cast(aDelaySec & 0x00FF); + oEntry.wBody.Split.Prm2 = static_cast( (aDelaySec >> 8) & 0x00FF); + oBufMsgInsertLink(); +} + +void TProtoC2C::MasterDoRemoteLnkStartStopViaUserCodeSimulate(unsigned int aUc, unsigned char aType, unsigned short aDelaySec, unsigned char aSta) +{ + oEntry.wBody.Split.Cmd = dNetworkCmd_RemoteStartStopViaUserCodeSimulate; + + oEntry.wBody.Split.Prm = aSta; //0:Off,1:Match,2:Start,3:DelayStart + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.UserCode = aUc; + oEntry.wBody.Split.dType = aType; + oEntry.wBody.Split.Prm1 = static_cast(aDelaySec & 0x00FF); + oEntry.wBody.Split.Prm2 = static_cast( (aDelaySec >> 8) & 0x00FF); + oBufMsgInsertLink(); +} + +void TProtoC2C::MasterDoPublishFire(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc) +{ + if(MainCtl.fData.Split.NetworkMode != 1)return; + oEntry.wBody.Split.Cmd = dNetworkCmd_PublishFire; + + oEntry.wBody.Split.Prm = CtlNum; + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.P0 = aP0; + oEntry.wBody.Split.P1 = aP1; + oEntry.wBody.Split.dType = aType; + oEntry.wBody.Split.UserCode = aUc; + oBufMsgInsertFire(); +} + +void TProtoC2C::MasterDoPublishFireCancel(unsigned char CtlNum, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc) +{ + oEntry.wBody.Split.Cmd = dNetworkCmd_PublishFireCancel; + + oEntry.wBody.Split.Prm = CtlNum; + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.P0 = aP0; + oEntry.wBody.Split.P1 = aP1; + oEntry.wBody.Split.dType = aType; + oEntry.wBody.Split.UserCode = aUc; + + oBufMsgInsertFire(); +} + +void TProtoC2C::MasterDoPublishClearNwCtlFire(unsigned char CtlNum) +{ + oEntry.wBody.Split.Cmd = dNetworkCmd_ClearCtlFire; + + oEntry.wBody.Split.Prm = CtlNum; + oEntry.wBody.Split.CtlNum = MainCtl.fData.Split.MyNum; + oEntry.wBody.Split.P0 = 0; + oEntry.wBody.Split.P1 = 0; + oEntry.wBody.Split.dType = 0; + + oBufMsgInsertNormal(); +} + +void TProtoC2C::sSetNwDevDelayStartPoint(unsigned char aNum, unsigned char aP0, unsigned char aP1, unsigned int aCountDown) +{ + unsigned int aAddr; + unsigned int NumOffSet, P0OffSet, P1OffSet; + unsigned int TickZeroPoint; + if(aNum > dNETWORK_MACHINE_COUNT)return; + if(aP0 > dPORT_MAX_COUNT)return; + + NumOffSet = (static_cast(aNum)) * 44'000; + P0OffSet = (static_cast(aP0)) * 1024; + P1OffSet = (static_cast(aP1)) * 4; + + aAddr = dAddrSdram_NwDelayStart + NumOffSet + P0OffSet + P1OffSet; + if(aCountDown <= 600){ + TickZeroPoint = TProtoC2C::DevDelayStartTick + aCountDown; + }else{ + TickZeroPoint = TProtoC2C::DevDelayStartTick + 600; + } + *(volatile unsigned int *)aAddr = TickZeroPoint; +} + +unsigned int TProtoC2C::GetNwDevDelayCountDown(unsigned char aNum, unsigned char aP0, unsigned char aP1) +{ + unsigned int aAddr; + unsigned int NumOffSet, P0OffSet, P1OffSet; + unsigned int TickZeroPoint; + unsigned int DelayCountDown; + if(aNum > dNETWORK_MACHINE_COUNT)return 0; + if(aP0 > dPORT_MAX_COUNT)return 0; + + NumOffSet = (static_cast(aNum)) * 44'000; + P0OffSet = (static_cast(aP0)) * 1024; + P1OffSet = (static_cast(aP1)) * 4; + + aAddr = dAddrSdram_NwDelayStart + NumOffSet + P0OffSet + P1OffSet; + TickZeroPoint = *(volatile unsigned int *)aAddr; + DelayCountDown = TickZeroPoint - TProtoC2C::DevDelayStartTick; + if(DelayCountDown > 600){ + DelayCountDown = 0; + } + return DelayCountDown; +} + +void TProtoC2C::sSetNwDirectPadDelayStartPoint(unsigned int aNum, unsigned int aDirectPad, unsigned int aNode, unsigned int aCountDown) +{ + unsigned int aAddr; + unsigned int NumOffSet, OffSet; + unsigned int TickZeroPoint; + if(aNum > dNETWORK_MACHINE_COUNT)return; + if(aDirectPad > dDIRECTCTL_MAX_COUNT)return; + if(aNode > dDIRECTCTL_KEY_MAX_COUNT)return; + + NumOffSet = aNum * 44'000 + 42'000; + OffSet = aDirectPad * dDIRECTCTL_KEY_MAX_COUNT * 4 + (aNode *4 ); + + aAddr = dAddrSdram_NwDelayStart + NumOffSet + OffSet; + if(aCountDown <= 600){ + TickZeroPoint = TProtoC2C::DevDelayStartTick + aCountDown; + }else{ + TickZeroPoint = TProtoC2C::DevDelayStartTick + 600; + } + *(volatile unsigned int *)aAddr = TickZeroPoint; +} + +unsigned int TProtoC2C::GetNwDirectPadDelayStartPoint(unsigned int aNum, unsigned int aDirectPad, unsigned int aNode) +{ + unsigned int aAddr; + unsigned int NumOffSet, OffSet; + unsigned int TickZeroPoint; + unsigned int DelayCountDown; + if(aNum > dNETWORK_MACHINE_COUNT)return 0; + if(aDirectPad > dDIRECTCTL_MAX_COUNT)return 0; + if(aNode > dDIRECTCTL_KEY_MAX_COUNT)return 0; + + NumOffSet = aNum * 44'000 + 42'000; + OffSet = aDirectPad * dDIRECTCTL_KEY_MAX_COUNT * 4 + (aNode *4 ); + + aAddr = dAddrSdram_NwDelayStart + NumOffSet + OffSet; + TickZeroPoint = *(volatile unsigned int *)aAddr; + DelayCountDown = TickZeroPoint - TProtoC2C::DevDelayStartTick; + if(DelayCountDown > 600){ + DelayCountDown = 0; + } + return DelayCountDown; +} + +void TProtoC2C::ClearNwDelayStartPoint(unsigned int aNum) +{ + unsigned int aAddr; + unsigned int NumOffSet, i; + if(aNum > 16)return; + + NumOffSet = aNum * 44'000; + aAddr = dAddrSdram_NwDelayStart + NumOffSet; + for(i=0; i<10240; i++){ + *(volatile unsigned int *)aAddr = 0; + aAddr += 4; + } + + NumOffSet = aNum * 44'000 + 42'000; + aAddr = dAddrSdram_NwDelayStart + NumOffSet; + for(i=0; i<200; i++){ + *(volatile unsigned int *)aAddr = 0; + aAddr += 4; + } +} + +void TProtoC2C::Task1000Ms() +{ + TProtoC2C::DevDelayStartTick++; +} + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/ProtoC2cOnSetup.cpp b/MyCode/src/ProtoC2cOnSetup.cpp new file mode 100644 index 0000000..9bc9c4a --- /dev/null +++ b/MyCode/src/ProtoC2cOnSetup.cpp @@ -0,0 +1,794 @@ +#include "ProtoInnerCan.h" +#include "ProtoC2C.h" + +#include "CnCpp.h" +#include "record.h" +#include "Runtime.h" +#include "server.h" + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" + #include "user_eeprom.h" +} + +void TProtoC2C::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick dNETWORK_MACHINE_COUNT) ){ + CtlMask.StartNum =0; + CtlMask.EndNum =0; + return; + } + if( (CtlMask.EndNum ==0) || (CtlMask.EndNum > dNETWORK_MACHINE_COUNT) ){ + CtlMask.StartNum =0; + CtlMask.EndNum =0; + return; + } + if( CtlMask.StartNum > CtlMask.EndNum){ + CtlMask.StartNum =0; + CtlMask.EndNum =0; + return; + } + } +} + +void TProtoC2C::FillDescp() +{ + unsigned int Inx, CtlNum,x, aP0, aP1, aAddr; + aP0 = oEntry.rBody.Split.P0; + aP1 = oEntry.rBody.Split.P1; + if( (aP0 ==0) || (aP0>dPORT_MAX_COUNT) )return; + if( (aP1 ==0) || (aP0>250) )return; + + aP0--; + aP1--; + + TxMsg.Data.Routing =0; + + TxMsg.Data.Cmd = dNetworkCmd_DevDescp; + TxMsg.Data.Order = 0; // On Setup + + aAddr = dAddrSdRam_Descp; + for(x=0;x<8;x++)DescpBuf.D32[x] = *(volatile unsigned int *)(aAddr + (aP0 * 8192) + (aP1 * 32) + (x * 4)); + + TxMsg.Data.Len = 8; + TxMsg.Data.Data[1] =MainCtl.fData.Split.MyNum; + + TxMsg.Data.Data[0] =1; + for(x=2;x<8;x++)TxMsg.Data.Data[x] = DescpBuf.D8[x-2]; + oBufInsert(TxMsg); + + TxMsg.Data.Data[0] =2; + for(x=2;x<8;x++)TxMsg.Data.Data[x] = DescpBuf.D8[x+4]; + oBufInsert(TxMsg); + + TxMsg.Data.Data[0] =3; + for(x=2;x<8;x++)TxMsg.Data.Data[x] = DescpBuf.D8[x+10]; + oBufInsert(TxMsg); + + TxMsg.Data.Data[0] =4; + for(x=2;x<8;x++)TxMsg.Data.Data[x] = DescpBuf.D8[x+16]; + oBufInsert(TxMsg); + + TxMsg.Data.Data[0] =5; + for(x=2;x<8;x++)TxMsg.Data.Data[x] = DescpBuf.D8[x+22]; + oBufInsert(TxMsg); + + TxMsg.Data.Len = 6; + TxMsg.Data.Data[0] =6; + + TxMsg.Data.Data[2] = DescpBuf.D8[30]; + TxMsg.Data.Data[3] = DescpBuf.D8[31]; + TxMsg.Data.Data[4] = oEntry.rBody.Split.P0; + TxMsg.Data.Data[5] = oEntry.rBody.Split.P1; + oBufInsert(TxMsg); +} + +void TProtoC2C::ProcessDevDescpRec() +{ + unsigned int Inx, CtlNum,x, aP, aP0, aP1; + volatile unsigned int aAddr; + Inx = RxMsg.Data.Data[0]; + CtlNum = RxMsg.Data.Data[1]; + if( (CtlNum ==0) || (CtlNum>32) )return; + if(Inx == 1){ + for(x=2;x<8;x++)OnSetup.Descp.D8[x-2] = RxMsg.Data.Data[x]; + OnSetup.DescpPiece |= 0x00000001; + }else + if(Inx == 2){ + for(x=2;x<8;x++)OnSetup.Descp.D8[x+4] = RxMsg.Data.Data[x]; + OnSetup.DescpPiece |= 0x00000002; + }else + if(Inx == 3){ + for(x=2;x<8;x++)OnSetup.Descp.D8[x+10] = RxMsg.Data.Data[x]; + OnSetup.DescpPiece |= 0x00000004; + }else + if(Inx == 4){ + for(x=2;x<8;x++)OnSetup.Descp.D8[x+16] = RxMsg.Data.Data[x]; + OnSetup.DescpPiece |= 0x00000008; + }else + if(Inx == 5){ + for(x=2;x<8;x++)OnSetup.Descp.D8[x+22] = RxMsg.Data.Data[x]; + OnSetup.DescpPiece |= 0x000000010; + }else + if(Inx == 6){ + OnSetup.Descp.D8[30] = RxMsg.Data.Data[2]; + OnSetup.Descp.D8[31] = RxMsg.Data.Data[3]; + aP0 = RxMsg.Data.Data[4]; + aP1 = RxMsg.Data.Data[5]; + if(OnSetup.DescpPiece == 0x0000001F){ + if( (aP0 != 0) && (aP0 <=dPORT_MAX_COUNT) ){ + if( (aP1 != 0) && (aP1 <=250) ){ + aP = CtlNum -1; + aP0--; + aP1--; + aAddr = dAddrSdRam_DescpNw; + for(x=0; x<8; x++){ + *(volatile unsigned int *)(aAddr + (aP*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32) + (x*4)) = OnSetup.Descp.D32[x]; + } + } + } + + OnSetup.DescpPiece = 0; + }else{ + //Fail Ack ReSend + + + } + } +} + +void TProtoC2C::SaveCfgData(unsigned char *data) +{ + unsigned int Inx, CtlNum; + volatile unsigned int aAddr; + Inx = RxMsg.Data.Data[0]; + CtlNum = RxMsg.Data.Data[1]; + if( (CtlNum ==0) || (CtlNum>32) )return; + + if(Inx == 0){ + MasterNum = CtlNum; + CfgData.CtlCount = RxMsg.Data.Data[3]; + }else + if(Inx == 1){ + CfgData.CtlList[ 0] = RxMsg.Data.Data[4]; + CfgData.CtlList[ 1] = RxMsg.Data.Data[5]; + CfgData.CtlList[ 2] = RxMsg.Data.Data[6]; + CfgData.CtlList[ 3] = RxMsg.Data.Data[7]; + }else + if(Inx == 2){ + CfgData.CtlList[ 4] = RxMsg.Data.Data[4]; + CfgData.CtlList[ 5] = RxMsg.Data.Data[5]; + CfgData.CtlList[ 6] = RxMsg.Data.Data[6]; + CfgData.CtlList[ 7] = RxMsg.Data.Data[7]; + }else + if(Inx == 3){ + CfgData.CtlList[ 8] = RxMsg.Data.Data[4]; + CfgData.CtlList[ 9] = RxMsg.Data.Data[5]; + CfgData.CtlList[10] = RxMsg.Data.Data[6]; + CfgData.CtlList[11] = RxMsg.Data.Data[7]; + }else + if(Inx == 4){ + CfgData.CtlList[12] = RxMsg.Data.Data[4]; + CfgData.CtlList[13] = RxMsg.Data.Data[5]; + CfgData.CtlList[14] = RxMsg.Data.Data[6]; + CfgData.CtlList[15] = RxMsg.Data.Data[7]; + }else + if(Inx == 5){ + CfgData.CtlList[16] = RxMsg.Data.Data[4]; + CfgData.CtlList[17] = RxMsg.Data.Data[5]; + CfgData.CtlList[18] = RxMsg.Data.Data[6]; + CfgData.CtlList[19] = RxMsg.Data.Data[7]; + }else + if(Inx == 6){ + CfgData.CtlList[20] = RxMsg.Data.Data[4]; + CfgData.CtlList[21] = RxMsg.Data.Data[5]; + CfgData.CtlList[22] = RxMsg.Data.Data[6]; + CfgData.CtlList[23] = RxMsg.Data.Data[7]; + }else + if(Inx == 7){ + CfgData.CtlList[24] = RxMsg.Data.Data[4]; + CfgData.CtlList[25] = RxMsg.Data.Data[5]; + CfgData.CtlList[26] = RxMsg.Data.Data[6]; + CfgData.CtlList[27] = RxMsg.Data.Data[7]; + }else + if(Inx == 8){ + CfgData.CtlList[28] = RxMsg.Data.Data[4]; + CfgData.CtlList[29] = RxMsg.Data.Data[5]; + CfgData.CtlList[30] = RxMsg.Data.Data[6]; + CfgData.CtlList[31] = RxMsg.Data.Data[7]; + }else + if(Inx == 9){ + if( (MainCtl.fData.Split.MyNum RxMsg.Data.Data[5]) ){ + if( (RxMsg.Data.Data[1] < ProtoC2C.CtlMask.StartNum) || (RxMsg.Data.Data[1] > ProtoC2C.CtlMask.EndNum) ){ + CtlNum = RxMsg.Data.Data[1]; + CfgData.CtlCount = RxMsg.Data.Data[3]; + int IncludeMe =0; + for(int i=0; (i32) )return; + + if(Inx == 0){ + TProtoM2M::sCnt = RxMsg.Data.Data[3]; + TProtoM2M::sRecPiece = 0x01; + }else + if(Inx == 1){ + TProtoM2M::sList[ 0] = RxMsg.Data.Data[4]; + TProtoM2M::sList[ 1] = RxMsg.Data.Data[5]; + TProtoM2M::sList[ 2] = RxMsg.Data.Data[6]; + TProtoM2M::sList[ 3] = RxMsg.Data.Data[7]; + TProtoM2M::sRecPiece |= 0x02; + }else + if(Inx == 2){ + TProtoM2M::sList[ 4] = RxMsg.Data.Data[4]; + TProtoM2M::sList[ 5] = RxMsg.Data.Data[5]; + TProtoM2M::sList[ 6] = RxMsg.Data.Data[6]; + TProtoM2M::sList[ 7] = RxMsg.Data.Data[7]; + TProtoM2M::sRecPiece |= 0x04; + + if(TProtoM2M::sRecPiece != 0x07){ + TProtoM2M::sRecPiece = 0; + return; + } + TProtoM2M::sRecPiece = 0; + if( (RxMsg.Data.Data[1] < ProtoC2C.CtlMask.StartNum) || (RxMsg.Data.Data[1] > ProtoC2C.CtlMask.EndNum) ){ + CtlNum = RxMsg.Data.Data[1]; + TProtoM2M::sCnt = RxMsg.Data.Data[3]; + int IncludeMe =0; + for(int i=0; (i32) )return; + + if(Inx == 0){ + CfgData.CtlCount = 0; + }else + if(Inx == 1){ + CfgData.CtlList[ 0] = RxMsg.Data.Data[4]; + CfgData.CtlList[ 1] = RxMsg.Data.Data[5]; + CfgData.CtlList[ 2] = RxMsg.Data.Data[6]; + CfgData.CtlList[ 3] = RxMsg.Data.Data[7]; + }else + if(Inx == 2){ + CfgData.CtlList[ 4] = RxMsg.Data.Data[4]; + CfgData.CtlList[ 5] = RxMsg.Data.Data[5]; + CfgData.CtlList[ 6] = RxMsg.Data.Data[6]; + CfgData.CtlList[ 7] = RxMsg.Data.Data[7]; + }else + if(Inx == 3){ + CfgData.CtlList[ 8] = RxMsg.Data.Data[4]; + CfgData.CtlList[ 9] = RxMsg.Data.Data[5]; + CfgData.CtlList[10] = RxMsg.Data.Data[6]; + CfgData.CtlList[11] = RxMsg.Data.Data[7]; + }else + if(Inx == 4){ + CfgData.CtlList[12] = RxMsg.Data.Data[4]; + CfgData.CtlList[13] = RxMsg.Data.Data[5]; + CfgData.CtlList[14] = RxMsg.Data.Data[6]; + CfgData.CtlList[15] = RxMsg.Data.Data[7]; + }else + if(Inx == 5){ + CfgData.CtlList[16] = RxMsg.Data.Data[4]; + CfgData.CtlList[17] = RxMsg.Data.Data[5]; + CfgData.CtlList[18] = RxMsg.Data.Data[6]; + CfgData.CtlList[19] = RxMsg.Data.Data[7]; + }else + if(Inx == 6){ + CfgData.CtlList[20] = RxMsg.Data.Data[4]; + CfgData.CtlList[21] = RxMsg.Data.Data[5]; + CfgData.CtlList[22] = RxMsg.Data.Data[6]; + CfgData.CtlList[23] = RxMsg.Data.Data[7]; + }else + if(Inx == 7){ + CfgData.CtlList[24] = RxMsg.Data.Data[4]; + CfgData.CtlList[25] = RxMsg.Data.Data[5]; + CfgData.CtlList[26] = RxMsg.Data.Data[6]; + CfgData.CtlList[27] = RxMsg.Data.Data[7]; + }else + if(Inx == 8){ + CfgData.CtlList[28] = RxMsg.Data.Data[4]; + CfgData.CtlList[29] = RxMsg.Data.Data[5]; + CfgData.CtlList[30] = RxMsg.Data.Data[6]; + CfgData.CtlList[31] = RxMsg.Data.Data[7]; + }else + if(Inx == 9){ + if( (MainCtl.fData.Split.MyNum RxMsg.Data.Data[5]) ){ + if( (RxMsg.Data.Data[1] < this->CtlMask.StartNum) || (RxMsg.Data.Data[1] > this->CtlMask.EndNum) ){ + CtlNum = RxMsg.Data.Data[1]; + int IncludeMe =0; + for(int i=0; iMasterNum){ + for(x=0; x32) )return; + if(MainCtl.fData.Split.NetworkMode != 1)return; + + if(Inx == 0){ + TProtoM2M::sCnt = 0; + TProtoM2M::sRecPiece = 1; + }else + if(Inx == 1){ + TProtoM2M::sList[0] =0; + TProtoM2M::sList[1] =0; + TProtoM2M::sList[2] =0; + TProtoM2M::sList[3] =0; + TProtoM2M::sRecPiece |= 0x02; + }else + if(Inx == 2){ + TProtoM2M::sList[4] =0; + TProtoM2M::sList[5] =0; + TProtoM2M::sList[6] =0; + TProtoM2M::sList[7] =0; + TProtoM2M::sRecPiece |= 0x04; + + if(TProtoM2M::sRecPiece != 0x07){ + TProtoM2M::sRecPiece = 0; + return; + } + TProtoM2M::sRecPiece = 0; + if( (MainCtl.fData.Split.MyNum RxMsg.Data.Data[5]) ){ + if( (RxMsg.Data.Data[1] < ProtoC2C.CtlMask.StartNum) || (RxMsg.Data.Data[1] > ProtoC2C.CtlMask.EndNum) ){ + CtlNum = RxMsg.Data.Data[1]; + int IncludeInitiator =0; + for(int i=0; (i dPORT_MAX_COUNT)return; + if(aNum == MainCtl.fData.Split.MyNum){ + if(aP0 <= dPORT_MAX_COUNT){ + if(MainCtl.fData.Split.ExistTablePort[P0]){ + TxMsg.Data.Data[3] = 0xFF; + }else{ + TxMsg.Data.Data[3] = 0x10; + } + }else + if(aP0 == (dPORT_MAX_COUNT +1)){ + TxMsg.Data.Data[3] = 0xFF; + } + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Cmd = dNetworkCmd_PortExistRpy; + TxMsg.Data.Len = 4; + TxMsg.Data.Data[0] =1; + TxMsg.Data.Data[1] = aNum; + TxMsg.Data.Data[2] = aP0; + oBufInsert(); + } +} + +void TProtoC2C::DescpListRpy(unsigned char aNum, unsigned char aP0, unsigned char Addr) +{ + unsigned char P0, P1; + char *p; + unsigned int i, aAddr, Dok; + + if( (aP0 ==0) || (aP0>dPORT_MAX_COUNT) )return; + if( (Addr ==0) || (Addr>250) )return; + + P0 =aP0-1; + P1 =Addr-1; + Dok = 0; + if(aNum == MainCtl.fData.Split.MyNum){ + if(MainCtl.fData.Split.ExistTablePort[P0]){ + if( Port[P0].ExistTable[P1] ){ + aAddr = dAddrSdRam_Descp + (P0 * 256 * 32) + (P1 * 32); + for(i=0; i<8; i++){ + DescpBuf.D32[i] = *(volatile unsigned int *)(aAddr + (i *4)); + } + if( DescpBuf.D8[0] != '\0') Dok = 1; + }else{ + Dok = 0; + } + } + if( (DescpBuf.D8[0] == 0xFF) && (DescpBuf.D8[1] == 0xFF) ) Dok = 0; + + TxMsg.Data.Cmd = dNetworkCmd_DescpRpy; + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = 0; + TxMsg.Data.Identification = 0; + TxMsg.Data.Data[1] = aNum; + TxMsg.Data.Data[2] = aP0; + TxMsg.Data.Data[3] = Addr; + if(Dok){ + for(i=0; i<8; i++){ + TxMsg.Data.Data[0] = i; + TxMsg.Data.Data[4] = DescpBuf.D8[i*4 +0]; + TxMsg.Data.Data[5] = DescpBuf.D8[i*4 +1]; + TxMsg.Data.Data[6] = DescpBuf.D8[i*4 +2]; + TxMsg.Data.Data[7] = DescpBuf.D8[i*4 +3]; + oBufInsert(); + } + }else{ + TxMsg.Data.Data[0] = 0x33; + TxMsg.Data.Data[4] = 0; + TxMsg.Data.Data[5] = 0; + TxMsg.Data.Data[6] = 0; + TxMsg.Data.Data[7] = 0; + oBufInsert(); + } + } +} + +void TProtoC2C::DescpListDirectPadRpy(unsigned char aNum, unsigned char aPadNum, unsigned char aKey) +{ + unsigned char P0, P1; + char *p; + unsigned int i, aAddr, Dok; + unsigned int OffSet; + + if( (aPadNum ==0) || (aPadNum > dDIRECTCTL_MAX_COUNT) )return; + if( (aKey ==0) || (aKey > dDIRECTCTL_KEY_MAX_COUNT) )return; + + OffSet = (aPadNum-1) * 8 + (aKey); + + Dok = 0; + if(aNum == MainCtl.fData.Split.MyNum){ + aAddr = dAddrSdRam_Descp + 327680 + (OffSet * 32); + for(i=0; i<8; i++){ + DescpBuf.D32[i] = *(volatile unsigned int *)(aAddr + (i *4)); + } + if( DescpBuf.D8[0] != '\0') Dok = 1; + if( (DescpBuf.D8[0] == 0xFF) && (DescpBuf.D8[1] == 0xFF) ) Dok = 0; + + TxMsg.Data.Cmd = dNetworkCmd_DescpRpy; + TxMsg.Data.Routing =0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = 0; + TxMsg.Data.Identification = 0; + TxMsg.Data.Data[1] = aNum; + TxMsg.Data.Data[2] = 41; + TxMsg.Data.Data[3] = OffSet; + if(Dok){ + for(i=0; i<8; i++){ + TxMsg.Data.Data[0] = i; + TxMsg.Data.Data[4] = DescpBuf.D8[i*4 +0]; + TxMsg.Data.Data[5] = DescpBuf.D8[i*4 +1]; + TxMsg.Data.Data[6] = DescpBuf.D8[i*4 +2]; + TxMsg.Data.Data[7] = DescpBuf.D8[i*4 +3]; + oBufInsert(); + } + }else{ + TxMsg.Data.Data[0] = 0x33; + TxMsg.Data.Data[4] = 0; + TxMsg.Data.Data[5] = 0; + TxMsg.Data.Data[6] = 0; + TxMsg.Data.Data[7] = 0; + oBufInsert(); + } + } +} + +void TProtoC2C::DescpListDirectPadRpy(unsigned char aNum, unsigned char Inx) +{ + unsigned char P0, P1; + char *p; + unsigned int i, aAddr, Dok; + unsigned int OffSet; + + if( (Inx ==0) || (Inx > 160) )return; + + OffSet = Inx; + + Dok = 0; + if(aNum == MainCtl.fData.Split.MyNum){ + aAddr = dAddrSdRam_Descp + 327680 + (OffSet * 32); + for(i=0; i<8; i++){ + DescpBuf.D32[i] = *(volatile unsigned int *)(aAddr + (i *4)); + } + if( DescpBuf.D8[0] != '\0') Dok = 1; + if( (DescpBuf.D8[0] == 0xFF) && (DescpBuf.D8[1] == 0xFF) ) Dok = 0; + + TxMsg.Data.Cmd = dNetworkCmd_DescpRpy; + TxMsg.Data.Routing = 0; + TxMsg.Data.Priority = 1; + TxMsg.Data.Len = 8; + TxMsg.Data.Order = 0; + TxMsg.Data.Identification = 0; + TxMsg.Data.Data[1] = aNum; + TxMsg.Data.Data[2] = 41; + TxMsg.Data.Data[3] = OffSet; + if(Dok){ + for(i=0; i<8; i++){ + TxMsg.Data.Data[0] = i; + TxMsg.Data.Data[4] = DescpBuf.D8[i*4 +0]; + TxMsg.Data.Data[5] = DescpBuf.D8[i*4 +1]; + TxMsg.Data.Data[6] = DescpBuf.D8[i*4 +2]; + TxMsg.Data.Data[7] = DescpBuf.D8[i*4 +3]; + oBufInsert(); + } + }else{ + TxMsg.Data.Data[0] = 0x33; + TxMsg.Data.Data[4] = 0; + TxMsg.Data.Data[5] = 0; + TxMsg.Data.Data[6] = 0; + TxMsg.Data.Data[7] = 0; + oBufInsert(); + } + } +} + +void TProtoC2C::TaskSecondUpdate() +{ + if( (DateTime.Time.Split.Hour == 1) && + (DateTime.Time.Split.Minute == 2 ) && + (DateTime.Time.Split.Second == 3 ) ){ + ShouldSyncTime = 1; + } + if(ShouldSyncTime){ + DateTimeSet(); + ShouldSyncTime = 0; + } +} + +void TProtoC2C::SyncCheckOnline() +{ + if(MainCtl.fData.Split.NetworkMode == 1){ + CheckOnlineTick =0; + CheckOnlineHasStart =0; + CheckOnlineAfterSendTick =0; + + for(int i=1; i<=dNETWORK_MACHINE_COUNT; i++){ + SlaveOnlineList[i] = 1; + } + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + CheckOnlineUpdateTick =0; + } +} + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/ProtoC2cSlaveDo.cpp b/MyCode/src/ProtoC2cSlaveDo.cpp new file mode 100644 index 0000000..27a1e9c --- /dev/null +++ b/MyCode/src/ProtoC2cSlaveDo.cpp @@ -0,0 +1,897 @@ +#include "ProtoInnerCan.h" +#include "ProtoC2C.h" + +#include "CnCpp.h" +#include "record.h" +#include "Runtime.h" +#include "server.h" + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" +} + + +void TProtoC2C::SlaveDoAlramOnOff(int aOnOff) +{ + sIm.Splite.Year = DateTime.Date.Split.Year; + sIm.Splite.Month = DateTime.Date.Split.Month; + sIm.Splite.Day = DateTime.Date.Split.Day; + sIm.Splite.Hour = DateTime.Time.Split.Hour; + sIm.Splite.Minute = DateTime.Time.Split.Minute; + sIm.Splite.Second = DateTime.Time.Split.Second; + sIm.Splite.mType = etLinkageStart; + sIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + sIm.Splite.P0 = 0xF0; //Board Index + sIm.Splite.P1 = 0xF0; + sIm.Splite.P2 = 0xF0; + sIm.Splite.dType = 0; + sIm.Splite.Data0 = 0x06; + sIm.Splite.Data1 = 0;//Is Set=1 Recover=0 + sIm.Splite.iByte0 = CmdActiveDefaultSet[cmVAAlramStart][8]; + + if(aOnOff == 0){ + FireVaTrenOned = 0; + AlramVaOnOff = 0; + sIm.Splite.Data0 = CmdActiveDefaultSet[cmVAAlramStop][8]; + sIm.Splite.iByte0 = CmdActiveDefaultSet[cmVAAlramStop][8]; + Record.OperateAdd_AlramSoundOff(MainCtl.fData.Split.MyNum); + tData[0] = 0; + tData[1] = 0; + tData[2] = 0; + InnerCan.OBufInsert(1, cmVAAlramStop, tData, 3); + }else{ + AlramVaOnOff = 1; + sIm.Splite.Data0 = CmdActiveDefaultSet[cmVAAlramStart][8]; + sIm.Splite.iByte0 = CmdActiveDefaultSet[cmVAAlramStart][8]; + Record.OperateAdd_AlramSoundOn(MainCtl.fData.Split.MyNum); + tData[0] = 0; + tData[1] = 0; + tData[2] = 0; + InnerCan.OBufInsert(1, cmVAAlramStart, tData, 3); + } +} + +void TProtoC2C::SlaveDoSend2MasterMachine(TRecordCommon aIm, unsigned char aCmd, TMsgType aMsgType) +{ + unsigned int i,aAddr; + if(MainCtl.fData.Split.NetworkMode == 2){ + oEntry.wBody.Split.Cmd = aCmd; + + //if( (aCmd == cmManualStart) || (aCmd == cmAutoStart) ){ + if(aIm.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + if( (aIm.Splite.P0) && (aIm.Splite.P0 <= dPORT_MAX_COUNT) ){ + if(Port[aIm.Splite.P0-1].StateTable[aIm.Splite.P1-1] & dEpStateBitMask) return; + } + } + //} + + oEntry.wBody.Split.CtlNum = aIm.Splite.PCtlNum; + oEntry.wBody.Split.Year = aIm.Splite.Year; + oEntry.wBody.Split.Mon = aIm.Splite.Month; + oEntry.wBody.Split.Day = aIm.Splite.Day; + oEntry.wBody.Split.Hour = aIm.Splite.Hour; + oEntry.wBody.Split.Min = aIm.Splite.Minute; + oEntry.wBody.Split.Sec = aIm.Splite.Second; + + oEntry.wBody.Split.P0 = aIm.Splite.P0; + oEntry.wBody.Split.P1 = aIm.Splite.P1; + oEntry.wBody.Split.Prm = aIm.Splite.P2; + oEntry.wBody.Split.dType = aIm.Splite.dType; + oEntry.wBody.Split.Prm1 = aIm.Splite.Data0; + oEntry.wBody.Split.Prm2 = aIm.Splite.Data1; + + oEntry.wBody.Split.UserCode = aIm.Splite.UserCode; + oEntry.wBody.Split.AreaNum = aIm.Splite.AreaNum; + + switch(aMsgType){ + case mtBasicService :oBufMsgInsertBasicService(); break; + case mtFire :oBufMsgInsertFire(); break; + case mtSv :oBufMsgInsertSv(); break; + case mtLink :oBufMsgInsertLink(); break; + case mtFault :oBufMsgInsertFault(); break; + case mtNormal :oBufMsgInsertNormal(); break; + default:break; + } + } +} + +void TProtoC2C::SlaveDoUploadMaskList() +{ + volatile int i; + if(MainCtl.fData.Split.NetworkMode != 2) return; + for(i=0; i dNETWORK_MACHINE_COUNT)return 0; + + if((aP0 >0) && (aP1 >0)){ + if(aP0 <= dPORT_MAX_COUNT){ + P0 = aP0-1; + P1 = aP1-1; + if( Port[P0].DelayTick[P1] > 2){ + DelaySec = Port[P0].DelayTick[P1] -2; + }else{ + DelaySec = 0; + } + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + P0 = aP0-dADDR_DIRECTPAD_START; + P1 = aP1-1; + if(DirectCtlBoard[P0].DelayTick[P1] > 2){ + DelaySec = DirectCtlBoard[P0].DelayTick[P1] -2; + }else{ + DelaySec = 0; + } + }else{ + DelaySec = 0; + } + return DelaySec; + }else{ + return 0; + } + return 0; +} + +void TProtoC2C::SlaveSetAutoState(unsigned char aSta) +{ + if(aSta == 0){ + AllowAuto = 0; + if(AllowManual == 0){ + AllowManual = 1; + ProcessUserSetManualState(); + } + }else{ + AllowAuto = 1; + } + Allow.ExtChange(AllowAuto); + ProcessUserSetAutoState(); +} + +void TProtoC2C::SlaveSetManualState(unsigned char aSta) +{ + if(aSta == 0){ + AllowManual = 0; + if(AllowAuto == 0){ + AllowAuto = 1; + ProcessUserSetAutoState(); + } + }else{ + AllowManual = 1; + } + Allow.ExtChange(AllowAuto); + ProcessUserSetManualState(); +} + +void TProtoC2C::SlaveSetAllowState(unsigned char aSta) +{ + if(aSta == 0){ + AllowAuto = 1; + AllowManual = 2; + }else + if(aSta == 1){ + AllowAuto = 1; + AllowManual = 0; + }else + if(aSta == 2){ + AllowAuto = 0; + AllowManual = 2; + }else + if(aSta == 3){ + AllowAuto = 1; + AllowManual = 2; + } + Allow.ExtChange(AllowAuto); + ProcessUserSetAutoState(); +} + +void TProtoC2C::SlaveSetAllowStateBySpc(unsigned char CtlNum, unsigned char aSta) +{ + if(CtlNum == MainCtl.fData.Split.MyNum){ + if(aSta) + SlaveSetAllowState(1); + else + SlaveSetAllowState(2); + } +} + +int TProtoC2C::CheckIsInSlaveList(unsigned char aCn) +{ + int Found; + if( aCn && (aCn <= dNETWORK_MACHINE_COUNT) ){ + Found =0; + for(int i=0; (i= dCRT_BufLen_Rx)iBuf.WriteIndex = 0; + aAddr = dAddrSdram_CrtRxBuf + (iBuf.WriteIndex * dCRT_BufEntrySize_Rx); + *(volatile unsigned int *)(aAddr + 0 ) = pD[0]; + *(volatile unsigned int *)(aAddr + 4 ) = pD[1]; + *(volatile unsigned int *)(aAddr + 8 ) = pD[2]; + *(volatile unsigned int *)(aAddr + 12) = pD[3]; + *(volatile unsigned int *)(aAddr + 16) = pD[4]; +} + +void TProtoCrt::iBufProcess() +{ + unsigned int aAddr; + if(iBuf.ReadIndex != iBuf.WriteIndex){ + iBuf.ReadIndex++; + if(iBuf.ReadIndex >= dCRT_BufLen_Rx)iBuf.ReadIndex = 0; + aAddr = dAddrSdram_CrtRxBuf + (iBuf.ReadIndex * dCRT_BufEntrySize_Rx); + iBuf.rBody.D32[0] = *(volatile unsigned int *)(aAddr + 0 ); + iBuf.rBody.D32[1] = *(volatile unsigned int *)(aAddr + 4 ); + iBuf.rBody.D32[2] = *(volatile unsigned int *)(aAddr + 8 ); + iBuf.rBody.D32[3] = *(volatile unsigned int *)(aAddr + 12); + iBuf.rBody.D32[4] = *(volatile unsigned int *)(aAddr + 16); + + if(iBuf.rBody.Splite.Cmd == dCRT_CMD_ACK){ + //Get Ack State + OnTransmite.CrtAckState = iBuf.rBody.Splite.Ack; + }else + if(iBuf.rBody.Splite.Cmd == dCRT_CMD_OPA){ + //Get Operate + DoCrtReqOperate(); + } + } +} + +void TProtoCrt::oBufInsert() +{ + unsigned int aAddr; + + oBuf.WriteIndex++; + if(oBuf.WriteIndex >= dCRT_BufLen_Tx)oBuf.WriteIndex = 0; + + aAddr = dAddrSdram_CrtTxBuf + (oBuf.WriteIndex * dCRT_BufEntrySize_Tx); + * (volatile unsigned int *)(aAddr + 0) = oBuf.wBody.D32[0]; + * (volatile unsigned int *)(aAddr + 4) = oBuf.wBody.D32[1]; + * (volatile unsigned int *)(aAddr + 8) = oBuf.wBody.D32[2]; + * (volatile unsigned int *)(aAddr + 12) = oBuf.wBody.D32[3]; + * (volatile unsigned int *)(aAddr + 16) = oBuf.wBody.D32[4]; +} + +void TProtoCrt::oBufInsert(unsigned int *pD) +{ + unsigned int aAddr; + + oBuf.WriteIndex++; + if(oBuf.WriteIndex >= dCRT_BufLen_Tx)oBuf.WriteIndex = 0; + + aAddr = dAddrSdram_CrtTxBuf + (oBuf.WriteIndex * 16); + * (volatile unsigned int *)(aAddr + 0) = pD[0]; + * (volatile unsigned int *)(aAddr + 4) = pD[1]; + * (volatile unsigned int *)(aAddr + 8) = pD[2]; + * (volatile unsigned int *)(aAddr + 12) = pD[3]; + * (volatile unsigned int *)(aAddr + 16) = pD[4]; +} + +void TProtoCrt::oBufInsert(unsigned char aCmd, unsigned char aMsgType, TRecordCommon aBufBody) +{ + unsigned int aAddr; + TDMix aDMix; + + oBuf.WriteIndex++; + if(oBuf.WriteIndex >= dCRT_BufLen_Tx)oBuf.WriteIndex = 0; + + aDMix.D32 = 0; + aDMix.D8[0] = aCmd; + aDMix.D8[1] = aMsgType; + + aAddr = dAddrSdram_CrtTxBuf + (oBuf.WriteIndex * 16); + * (volatile unsigned int *)(aAddr + 0) = aDMix.D32; + * (volatile unsigned int *)(aAddr + 4) = aBufBody.D32[0]; + * (volatile unsigned int *)(aAddr + 8) = aBufBody.D32[1]; + * (volatile unsigned int *)(aAddr + 12) = aBufBody.D32[2]; + * (volatile unsigned int *)(aAddr + 16) = aBufBody.D32[3]; +} + +void TProtoCrt::oBufTryTxNewMsg() +{ + unsigned int aAddr; + if(oBuf.ReadIndex != oBuf.WriteIndex){ + if(get_excan_linkage_tx_complete()){ + oBuf.ReadIndex++; + if(oBuf.ReadIndex >= dCRT_BufLen_Tx)oBuf.ReadIndex = 0; + aAddr = dAddrSdram_C2cOutBuf + (oBuf.ReadIndex * 16); + + tData.D32[0] = * (volatile unsigned int *)(aAddr + 0); + //Do Send Data Here + + OnTransmite.NoCommTick = 0; + OnTransmite.WaitTick = 0; + OnTransmite.RetryTimes = 0; + OnTransmite.CrtAckState = 0; + + OnTransmite.OnGoing = 1; + } + } +} + +void TProtoCrt::PublishOperate(TRecordCommon aIm) +{ + oBufInsert(0, 5, aIm); +} + +void TProtoCrt::ResetCoomm() +{ + Init(); +} + +void TProtoCrt::PrcErrMsg() +{ + if(Err.TransferBoardOffline != ErrReport.TransferBoardOffline){ + if(Err.TransferBoardOffline){ + //Add Fault Msg Here + }else{ + //Cancel Fault Msg Here + } + ErrReport.TransferBoardOffline = Err.TransferBoardOffline; + } + + if(Err.CrtOffline != ErrReport.CrtOffline){ + if(Err.CrtOffline){ + //Add Fault Msg Here + }else{ + //Cancel Fault Msg Here + } + ErrReport.CrtOffline = Err.CrtOffline; + } +} + +void TProtoCrt::oBufProcess() +{ + OnTransmite.NoCommTick++; + if(OnTransmite.OnGoing){ + if(OnTransmite.CrtAckState == 0){ + //No Rpy Here + OnTransmite.WaitTick++; + if(OnTransmite.WaitTick > 100){ + //Resend Old Pkg Here + OnTransmite.WaitTick =0; + if(OnTransmite.RetryTimes < 20){ + OnTransmite.RetryTimes++; + }else{ + //Report Err Here + Err.TransferBoardOffline =1; + PrcErrMsg(); + } + } + }else + if(OnTransmite.CrtAckState == 1){ + //Rpy Ack Ok Here, Load Next + OnTransmite.OnGoing = 0; + }else + if(OnTransmite.CrtAckState == 2){ + //Rpy No Need Ack Here, Load Next + OnTransmite.OnGoing = 0; + }else + if(OnTransmite.CrtAckState == 3){ + //Rpy Not Found Crt + OnTransmite.OnGoing = 0; + Err.CrtOffline = 1; + PrcErrMsg(); + } + } + + if(OnTransmite.OnGoing == 0){ + if(oBuf.ReadIndex != oBuf.WriteIndex){ + oBufTryTxNewMsg(); + }else{ + if(OnTransmite.NoCommTick > 2999){ + //Add a Dump Buf Here For Check Online + } + } + } +} + +void TProtoCrt::DoCrtReqOperate() +{ + unsigned char aOpaCode; + aOpaCode = iBuf.rBody.Splite.OpaCode; + switch(aOpaCode){ + case 0: + break; + case 1: + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +void TProtoCrt::Task10Ms() +{ + if(GraphUsing == 0)return; + if(MainCtl.fData.Split.NetworkMode == 2)return; + + oBufProcess(); +} + + + + + + + + + + + + + diff --git a/MyCode/src/ProtoCrt.h b/MyCode/src/ProtoCrt.h new file mode 100644 index 0000000..70c3dd8 --- /dev/null +++ b/MyCode/src/ProtoCrt.h @@ -0,0 +1,118 @@ +#ifndef PROTOCRT_H_ +#define PROTOCRT_H_ + +#include "gType.h" +#include "ProtoInnerCan.h" +#include "TDateTime.h" +#include "record.h" + +#define dCRT_CMD_OPA 201 +#define dCRT_CMD_ACK 202 + +#define dCRT_BufLen_Tx 1024 +#define dCRT_BufLen_Rx 4096 + +#define dCRT_BufEntrySize_Tx 32*3 +#define dCRT_BufEntrySize_Rx 32 + +typedef union{ + unsigned int D32[8]; + struct{ + unsigned char Cmd; //Cmd + unsigned char MsgType; // 0:Fire, 1:Linkage, 2:Sv, 3:Fault, 4:Mask, 5:Operate + unsigned char Ack; + unsigned char OpaCode; + + TRecordCommon Msg; + }Splite; +}TCrtMsg; + + +class TProtoCrt{ + public: + volatile struct{ + int Count; + unsigned int WriteIndex; + unsigned int ReadIndex; + TCrtMsg wBody; + TCrtMsg rBody; + }iBuf, oBuf; + + TRecordCommon TxOperateBody; + + union { + unsigned int D32[4]; + unsigned char D8[16]; + }tData; + + struct{ + unsigned char State; + unsigned char OnGoing; + unsigned char CrtAckState; + unsigned int WaitTick; + unsigned int NoCommTick; + unsigned int RetryTimes; + }OnTransmite; + + struct{ + unsigned char TransferBoardOffline; + unsigned char CrtOffline; + }Err, ErrReport; + + public: + TProtoCrt(){}; + void Init(); + void dInit(); + + void PublishEventMute(); + void PublishEventReset(); + + void iBufInsertDump(); + void iBufInsert(); + void iBufInsert(unsigned int *pD); + void iBufInsert(TRecordCommon aNsBuf); + void iBufProcess(); + + void PublishOperate(TRecordCommon aIm); + + void oBufInsert(); + void oBufInsert(unsigned int *pD); + void oBufInsert(unsigned char aCmd, unsigned char aMsgType, TRecordCommon aBufBody); + void oBufTryTxNewMsg(); + void oBufProcess(); + + void PrcErrMsg(); + void DoCrtReqOperate(); + + void ResetCoomm(); + void Task10Ms(); +}; + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/ProtoFecBus.cpp b/MyCode/src/ProtoFecBus.cpp new file mode 100644 index 0000000..17da0e9 --- /dev/null +++ b/MyCode/src/ProtoFecBus.cpp @@ -0,0 +1,2943 @@ +#include "ProtoFecBus.h" +#include "Runtime.h" + +extern "C" { + #include "uart_fec_std_drv.h" + #include "fdcan_task.h" +} + +#define Priority0 0 +#define Priority1 1 +#define Priority2 2 +#define Priority3 3 + +#define FecFrmTX 0 +#define FecFrmACK 1 +#define FecFrmRX 1 +#define FecFrmRXFORMMAS 0 + +#define FecCtlAddr 1 + +#define FecHeader 0x7E +#define FecEnding 0x7E + +#define CommAckTimeout 59//6s通讯超时 unit 100ms + +//(1024*1024) +#define dFecBus_AddrCount 62//2-63 +#define dFecBus_BufEntrySize_Event 16 + +//16 bytes 为单位 +#define dFecBus_OneBufCount (1024) +#define dFecBus_DownEventBufCount (1024) +#define dFecBus_UpEventBufCount (1024*62) +#define dFecBus_CurrentEventBufCount (1024*62) +#define dFecBus_HistoryEventBufCount (1024) + +#define dAddrSdram_FECDownEventBuf dAddrSdram_FECStdBuf +#define dAddrSdram_FECUpEventBuf (dAddrSdram_FECDownEventBuf + dFecBus_DownEventBufCount) +#define dAddrSdram_FECCurrentEventBuf (dAddrSdram_FECUpEventBuf + dFecBus_UpEventBufCount) +#define dAddrSdram_FECHistoryEventBuf (dAddrSdram_FECCurrentEventBuf + dFecBus_CurrentEventBufCount) + +void TFecBus::Init() +{ + u32 x = 0; + u32 y = 0; + u32 aAddr; + + uMsgOutIndex = 1; + RxGetFlag = 0; + RxHandleFlag = 0; + TxSetFlag = 0; + + RxMsg.avalibel = 0; + RxMsg.UsingMsgIndex = 0; + RxMsg.FrmCount = 0; + for(x=0;x<128;x++) + for(y=0;y<16;y++) + RxMsg.body[x].D8[y] = 0; + + RxMsgState = ackMsgSectionEnd; + + for(x=0;x<258;x++){ + uDataRX.da32[x] = 0; + uDataTX.da32[x] = 0; + } + + OnTransmite.AckOk = 1; + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + OnTransmite.TimeOutTick = 0; + + CommPrm.CuuerntAddr = 2; + CommPrm.Phase = FecPolling; + CommPrm.State = FecCommExit; + //CommPrm.Phase = FecSetUpComm; + //CommPrm.State = FecCommQueryVer44; + CommPrm.SetDownEventFlag = 0; + CommPrm.SetDownCmdFlag = 0; + CommPrm.TimeoutTick = 0; + CommPrm.NoAckTick = 0; + + CommPrm.SetDownPath.Addr = 2; + + for(x=0;x<64;x++){ + CommPrm.Register[x] = 0; + } + + CommPrm.DownEventCount = 0; + for(x=0; x 63)uMsgOutIndex = 1; +} + +u16 TFecBus::Crc16(u8 *pD, u8 Len) const +{ + u16 aCrc = 0xFFFF; + for (int i = 0; i < Len; i++){ + aCrc ^= static_cast(pD[i]); + for (int j = 0; j < 8; j++){ + if (aCrc & 0x0001){ + aCrc = (aCrc >> 1) ^ 0xA001; + }else{ + aCrc = aCrc >> 1; + } + } + } + return aCrc; +} + +void TFecBus::getSysTime(void) +{ + dateTime.Year = (DateTime.Date.Split.Year/16*10) + (DateTime.Date.Split.Year & 0x0F); + dateTime.Mon = (DateTime.Date.Split.Month/16*10) + (DateTime.Date.Split.Month & 0x0F); + dateTime.Day = (DateTime.Date.Split.Day/16*10) + (DateTime.Date.Split.Day & 0x0F); + dateTime.Hour = (DateTime.Time.Split.Hour/16*10) + (DateTime.Time.Split.Hour & 0x0F); + dateTime.Min = (DateTime.Time.Split.Minute/16*10) + (DateTime.Time.Split.Minute & 0x0F); + dateTime.Sec = (DateTime.Time.Split.Second/16*10) + (DateTime.Time.Split.Second & 0x0F); +} + +u32 TFecBus::GetNewPublishCount(void) +{ + u32 i, cnt; + cnt = 0; + for(i=0; i (128*8))return; + + for(i=1;i<=RxMsg.FrmCount;i++){ + for(x=0;x 1)&&(uDataRX.body.SrcAddr < 64)&& + CommPrm.GetAddr = uDataRX.body.SrcAddr; + + if(FecFrmRXFORMMAS == uDataRX.body.FrmType){//接收2-63主发 + switch(uDataRX.body.DPFC[0]){ + case FecFunInformedEmergencyEvent: //17 通告紧急事件 + if((FecPolling == CommPrm.Phase)&&(FecCommPolling33Ack == CommPrm.State)){ + CommPrm.AckStatus = 3; + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.UpEventData); + AddUpEventList(CommPrm.GetAddr, &CommPrm.UpEventData); + }else + if((FecDownEvent == CommPrm.Phase)&&(FecCommPolling33Ack == CommPrm.State)){ + CommPrm.AckStatus = 2; + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.UpEventData); + AddUpEventList(CommPrm.GetAddr, &CommPrm.UpEventData); + } + break; + + case FecFunInformedGeneralEvent: //18 通告一般事件 + if((FecPolling == CommPrm.Phase)&&(FecCommPolling33Ack == CommPrm.State)){ + CommPrm.AckStatus = 3; + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.UpEventData); + AddUpEventList(CommPrm.GetAddr, &CommPrm.UpEventData); + }else + if((FecDownEvent == CommPrm.Phase)&&(FecCommPolling33UpAck == CommPrm.State)){ + CommPrm.AckStatus = 2; + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.UpEventData); + AddUpEventList(CommPrm.GetAddr, &CommPrm.UpEventData); + } + break; + + case FecFunInformedAdjustEvent: //19 通告调试事件 + if((FecPolling == CommPrm.Phase)&&(FecCommPolling33Ack == CommPrm.State)){ + CommPrm.AckStatus = 3; + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.UpEventData); + AddUpEventList(CommPrm.GetAddr, &CommPrm.UpEventData); + }else + if((FecDownEvent == CommPrm.Phase)&&(FecCommPolling33UpAck == CommPrm.State)){ + CommPrm.AckStatus = 2; + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.UpEventData); + AddUpEventList(CommPrm.GetAddr, &CommPrm.UpEventData); + } + break; + + case FecFunInformedHeartbeat: //20 通告心跳 + break; + + default: //未识别命令 + break; + } + }else + if(FecFrmRX == uDataRX.body.FrmType){//接收2-63回复 + switch(uDataRX.body.DPFC[0]){ + case FecFunSyncSysTick: //0 同步系统节拍 + if((FecDownCmd == CommPrm.Phase)&&(FecCommSyncSysTick00Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunSysReset: //1 系统复位 + if((FecDownCmd == CommPrm.Phase)&&(FecCommSysReset01Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunSysMute: //2 系统消音 + if((FecDownCmd == CommPrm.Phase)&&(FecCommSysMute02Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunSysSlefCheck: //3 系统自检 + if((FecDownCmd == CommPrm.Phase)&&(FecCommSysSlefCheck03Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunSyncTime: //4 广播时钟 + if((FecSetUpComm == CommPrm.Phase)&&(FecCommSyncTime04Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + }else + if((FecDownCmd == CommPrm.Phase)&&(FecCommSyncTime04Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunPublishEmergencyEvent: //5 通告紧急事件 + if((FecDownEvent == CommPrm.Phase)&&(FecCommDownEvent05Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunPublishGeneralEvent: //6 通告一般事件 + if((FecDownEvent == CommPrm.Phase)&&(FecCommDownEvent06Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunPublishAdjustEvent: //7 通告调试事件 + if((FecDownEvent == CommPrm.Phase)&&(FecCommDownEvent07Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecFunStateAck: //15 状态码应答，或结束帧标志 + if((FecSetUpComm == CommPrm.Phase)&&(FecCommQueryCurrentEvent41Ack == CommPrm.State)){ + fMsgRX_Cmd15(CommPrm.GetAddr,CommPrm.AckCode); + //CommPrm.AckStatus = 1;//1接收正确(在41命令) 2当前事件接收完成 + if(ackEventOver == CommPrm.AckCode)CommPrm.AckStatus = 2; + }else + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryCurrentEvent41Ack == CommPrm.State)){ + fMsgRX_Cmd15(CommPrm.GetAddr,CommPrm.AckCode); + //CommPrm.AckStatus = 1;//1接收正确(在41命令) 2当前事件接收完成 + if(ackEventOver == CommPrm.AckCode)CommPrm.AckStatus = 2; + }else + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryHistoryEvent42Ack == CommPrm.State)){ + fMsgRX_Cmd15(CommPrm.GetAddr,CommPrm.AckCode); + //CommPrm.AckStatus = 1;//1接收正确(在41命令) 2当前事件接收完成 + if(ackEventOver == CommPrm.AckCode)CommPrm.AckStatus = 2; + } + break; + + case FecFunInspectionDevice: //33 设备巡检 + if((FecPolling == CommPrm.Phase)&&(FecCommPolling33Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + }else + if((FecDownCmd == CommPrm.Phase)&&(FecCommPolling33Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + }else + if((FecDownEvent == CommPrm.Phase)&&(FecCommPolling33UpAck == CommPrm.State)){ + CommPrm.AckStatus = 3; + } + break; + + case FecFunQueryDeviceState: //34 查设备状态 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceState34Ack == CommPrm.State)){ + fMsgRX_Cmd34(CommPrm.CuuerntAddr, CommPrm.GetCmd34DeviceState); + CommPrm.AckStatus = 1; + } + break; + + case FecFunQueryDeviceConfig: //35 查设备配置 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceConfig35Ack == CommPrm.State)){ + fMsgRX_Cmd35(CommPrm.CuuerntAddr, CommPrm.GetCmd35ConfigCode); + CommPrm.AckStatus = 1; + } + break; + + case FecFunQueryDeviceIdf: //36 查设备标识 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceIdf36Ack == CommPrm.State)){ + fMsgRX_Cmd36(CommPrm.CuuerntAddr, CommPrm.GetCmd36DeviceIdf); + CommPrm.AckStatus = 1; + } + break; + + case FecFunQueryDeviceParameter: //37 查设备参量 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceParameter37Ack == CommPrm.State)){ + fMsgRX_Cmd37(CommPrm.CuuerntAddr, CommPrm.GetCmd37DevicePrmType, CommPrm.GetCmd37DevicePrmValue); + CommPrm.AckStatus = 1; + } + break; + + case FecFunQueryDeviceDescp: //38 查设备注释 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceDescp38Ack == CommPrm.State)){ + fMsgRX_Cmd38_40(CommPrm.CuuerntAddr, &CommPrm.GetCmd38To40Data); + CommPrm.AckStatus = 1; + } + break; + + case FecFunQueryDeviceProgram: //39 查设备编程 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceProgram39Ack == CommPrm.State)){ + fMsgRX_Cmd38_40(CommPrm.CuuerntAddr, &CommPrm.GetCmd38To40Data); + CommPrm.AckStatus = 1; + } + break; + + case FecFunQueryDeviceRegisterInfo: //40 查注册登记信息 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceRegisterInfo40Ack == CommPrm.State)){ + fMsgRX_Cmd38_40(CommPrm.CuuerntAddr, &CommPrm.GetCmd38To40Data); + CommPrm.AckStatus = 1; + } + break; + + case FecQueryCurrentEvent: //41 查设备当前事件 + if((FecSetUpComm == CommPrm.Phase)&&(FecCommQueryCurrentEvent41Ack == CommPrm.State)){ + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.CurrentEventData); + AddCurrentEventList(CommPrm.GetAddr, &CommPrm.CurrentEventData); + //CommPrm.getCurrentEventTick++; + CommPrm.AckStatus = 1; + }else + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryCurrentEvent41Ack == CommPrm.State)){ + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.CurrentEventData); + AddCurrentEventList(CommPrm.GetAddr, &CommPrm.CurrentEventData); + //CommPrm.getCurrentEventTick++; + CommPrm.AckStatus = 1; + } + break; + + case FecQueryHistoryEvent: //42 查设备历史事件 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryHistoryEvent42Ack == CommPrm.State)){ + fMsgRX_Cmd17To19n41_42(CommPrm.GetAddr,&CommPrm.HistoryEventData); + AddHistoryEventList(&CommPrm.HistoryEventData); + CommPrm.AckStatus = 1; + } + break; + + case FecStopQueryDeviceEvent: //43 停止查询设备事件 + if((FecDownCmd == CommPrm.Phase)&&(FecCommStopQueryDeviceEvent43Ack == CommPrm.State)){ + CommPrm.AckStatus = 1; + } + break; + + case FecQueryFECBusVer: //44 查FECBus协议版本号 + if((FecSetUpComm == CommPrm.Phase)&&(FecCommQueryVer44Ack == CommPrm.State)){ + fMsgRX_Cmd44(CommPrm.GetAddr,CommPrm.GetCmd44Ver); + CommPrm.AckStatus = 1; + }else + if((FecPolling == CommPrm.Phase)&&(FecCommPolling33Ack == CommPrm.State)){ + fMsgRX_Cmd44(CommPrm.GetAddr,CommPrm.GetCmd44Ver); + CommPrm.AckStatus = 2;//跳到注册 + }else + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryVer44Ack == CommPrm.State)){ + fMsgRX_Cmd44(CommPrm.GetAddr,CommPrm.GetCmd44Ver); + CommPrm.AckStatus = 1; + } + break; + + case FecQueryDeviceList: //45 查设备列表 + if((FecDownCmd == CommPrm.Phase)&&(FecCommQueryDeviceList45Ack == CommPrm.State)){ + fMsgRX_Cmd45(CommPrm.GetAddr,&CommPrm.GetCmd45Data); + CommPrm.AckStatus = 1; + } + break; + + default: //未识别命令 + break; + } + } + }else{ + //地址错误 + //参数错误 + } +} + +unsigned int TFecBus::fMsgRX_Cmd00To07(u8 aSrcAddr) +{ + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + return 0; +} + +unsigned int TFecBus::fMsgRX_Cmd15(u8 aSrcAddr, u8 aState) +{ + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + aState = uDataRX.body.DPFC[1]; + + return 0; +} + +unsigned int TFecBus::fMsgRX_Cmd17To19n41_42(u8 aSrcAddr, TFecEventBufBody * pFecEvent) +{ + unsigned int i = 0; + + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + for(i= 0;i<16;i++){ + pFecEvent->D8[i] = uDataRX.body.DPFC[i+1]; + } + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd33(u8 aSrcAddr) +{ + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd34(u8 aSrcAddr, TFecStateCode aStateCode) +{ + unsigned short aState; + + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + aState = uDataRX.body.DPFC[2]; + aState<<=8; + aState|= uDataRX.body.DPFC[1]; + aStateCode.D16 = aState; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd35(u8 aSrcAddr, u16 aConfigCode) +{ + u16 aD16; + + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + aD16 = uDataRX.body.DPFC[2]; + aD16<<=8; + aD16|= uDataRX.body.DPFC[1]; + aConfigCode = aD16; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd36(u8 aSrcAddr, u8 * aIdfCode) +{ + u32 i = 0; + + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + for(i=0;i<7;i++) + aIdfCode[i] = uDataRX.body.DPFC[i+1]; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd37(u8 aSrcAddr, TParameterType aPrmType, u16 aPrm) +{ + u16 aD16 = 0; + + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + aPrmType = (TParameterType)uDataRX.body.DPFC[1]; + aD16 = uDataRX.body.DPFC[3]; + aD16<<=8; + aD16|= uDataRX.body.DPFC[2]; + aPrm = aD16; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd38_40(u8 aSrcAddr, TGetCmd38_40Data * pData) +{ + u32 i= 0; + + aSrcAddr = uDataRX.body.SrcAddr; + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + pData->CtlNum = uDataRX.body.DPFC[1]; + pData->UnitNum = uDataRX.body.DPFC[2]; + pData->DevNum = uDataRX.body.DPFC[3]; + pData->Len = uDataRX.body.DPFC[4]; + + for(i=0;iLen;i++) + pData->Value[i] = uDataRX.body.DPFC[i+5]; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd43(u8 aSrcAddr) +{ + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd44(u8 aSrcAddr, u16 aVer) +{ + u16 aD16 = 0; + + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + aD16 = uDataRX.body.DPFC[2]; + aD16<<=8; + aD16|= uDataRX.body.DPFC[1]; + aVer = aD16; + + return 0; +} + +u32 TFecBus::fMsgRX_Cmd45(u8 aSrcAddr, TGetCmd45Data * pTData) +{ + unsigned int i = 0; + + if((aSrcAddr < 2)||(aSrcAddr > 63))return 1; + + aSrcAddr = uDataRX.body.SrcAddr; + + if(1 == CommPrm.GetCmd45Data.type){ + CommPrm.GetCmd45Data.Count = uDataRX.body.DPFC[1]; + + for(i=0;i 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority0; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunSyncSysTick; + + uSetTXData(); +} + +void TFecBus::fMsgTX01_SysReset(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority1; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecFunSysReset; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX02_SysMute(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority1; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecFunSysMute; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX03_SysSelfCheck(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority3; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecFunSysSlefCheck; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX04_SyncTime(u8 aDestAddr, u8 aCtlNum, u8 aY, u8 aMon, u8 aDay, u8 aH, u8 aMin, u8 aSec) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority3; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 8; + uDataTX.body.DPFC[0] = FecFunSyncTime; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aY; + uDataTX.body.DPFC[3] = aMon; + uDataTX.body.DPFC[4] = aDay; + uDataTX.body.DPFC[5] = aH; + uDataTX.body.DPFC[6] = aMin; + uDataTX.body.DPFC[7] = aSec; + + uSetTXData(); +} + +void TFecBus::fMsgTX05_PublishEmergencyEvent(u8 aDestAddr, TFecEventBufBody * pEvent) +{ + u32 i = 0; + + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority1; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 17; + uDataTX.body.DPFC[0] = FecFunPublishEmergencyEvent; + for(i=0;i<16;i++){ + uDataTX.body.DPFC[i+1] = pEvent->D8[i]; + } + + uSetTXData(); +} + +void TFecBus::fMsgTX06_PublishGeneralEvent(u8 aDestAddr, TFecEventBufBody * pEvent) +{ + u32 i = 0; + + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority3; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 17; + uDataTX.body.DPFC[0] = FecFunPublishGeneralEvent; + for(i=0;i<16;i++){ + uDataTX.body.DPFC[i+1] = pEvent->D8[i]; + } + + uSetTXData(); +} + +void TFecBus::fMsgTX07_PublishAdjustEvent(u8 aDestAddr, TFecEventBufBody * pEvent) +{ + u32 i = 0; + + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority3; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 17; + uDataTX.body.DPFC[0] = FecFunPublishAdjustEvent; + for(i=0;i<16;i++){ + uDataTX.body.DPFC[i+1] = pEvent->D8[i]; + } + + uSetTXData(); +} + +void TFecBus::fMsgTX15_Ack_StateAck(u8 aDestAddr, TFecAckCode aState) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmACK; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority3; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecFunStateAck; + uDataTX.body.DPFC[1] = aState; + + uSetTXData(); +} + +void TFecBus::fMsgRpy17_Ack_PublishEmergencyEvent(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmACK; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority1; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunInformedEmergencyEvent; + + uSetTXData(); +} + +void TFecBus::fMsgRpy18_Ack_InformedGeneralEvent(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmACK; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority3; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunInformedGeneralEvent; + + uSetTXData(); +} + +void TFecBus::fMsgRpy19_Ack_InformedAdjustEvent(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmACK; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority3; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunInformedAdjustEvent; + + uSetTXData(); +} + +void TFecBus::fMsgTX33_InspectionDevice(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunInspectionDevice; + + uSetTXData(); +} + +void TFecBus::fMsgTX34_QueryDeviceState(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunQueryDeviceState; + + uSetTXData(); +} + +void TFecBus::fMsgTX34_QueryDeviceState(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecFunQueryDeviceState; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX34_QueryDeviceState(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 3; + uDataTX.body.DPFC[0] = FecFunQueryDeviceState; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX34_QueryDeviceState(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecFunQueryDeviceState; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + uDataTX.body.DPFC[3] = aDev; + + uSetTXData(); +} + +void TFecBus::fMsgTX35_QueryDeviceConfig(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunQueryDeviceConfig; + + uSetTXData(); +} + +void TFecBus::fMsgTX35_QueryDeviceConfig(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecFunQueryDeviceConfig; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX35_QueryDeviceConfig(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 3; + uDataTX.body.DPFC[0] = FecFunQueryDeviceConfig; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX35_QueryDeviceConfig(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecFunQueryDeviceConfig; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + uDataTX.body.DPFC[3] = aDev; + + uSetTXData(); +} + +void TFecBus::fMsgTX36_QueryDeviceIdf(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecFunQueryDeviceIdf; + + uSetTXData(); +} +void TFecBus::fMsgTX36_QueryDeviceIdf(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecFunQueryDeviceIdf; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX36_QueryDeviceIdf(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 3; + uDataTX.body.DPFC[0] = FecFunQueryDeviceIdf; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX36_QueryDeviceIdf(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecFunQueryDeviceIdf; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + uDataTX.body.DPFC[3] = aDev; + + uSetTXData(); +} + +void TFecBus::fMsgTX37_QueryDeviceParameter(u8 aDestAddr, TFecItemPath * pPath) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 5; + uDataTX.body.DPFC[0] = FecFunQueryDeviceParameter; + uDataTX.body.DPFC[1] = pPath->CtlNum; + uDataTX.body.DPFC[2] = pPath->UnitNum; + uDataTX.body.DPFC[3] = pPath->DevNum; + uDataTX.body.DPFC[4] = pPath->ChannelNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX38_QueryDeviceDescp(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecFunQueryDeviceDescp; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + uDataTX.body.DPFC[3] = aDev; + + uSetTXData(); +} + +void TFecBus::fMsgTX39_QueryDeviceProgram(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecFunQueryDeviceProgram; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + uDataTX.body.DPFC[3] = aDev; + + uSetTXData(); +} + +void TFecBus::fMsgTX40_QueryDeviceRegisterInfo(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 3; + uDataTX.body.DPFC[0] = FecFunQueryDeviceRegisterInfo; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX40_QueryDeviceRegisterInfo(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecFunQueryDeviceRegisterInfo; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + uDataTX.body.DPFC[3] = aDev; + + uSetTXData(); +} + +void TFecBus::fMsgTX41_QueryCurrentEvent(u8 aDestAddr, u8 aCtlNum, TFecEventCode aEvent) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecQueryCurrentEvent; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aEvent & 0xFF; + uDataTX.body.DPFC[3] = (aEvent>>8) & 0xFF; + + uSetTXData(); +} + +void TFecBus::fMsgTX42_QueryHistoryEvent(u8 aDestAddr, u8 aCtlNum, TFecEventCode aEvent, u8 aSY, u8 aSM, u8 aSD) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 7; + uDataTX.body.DPFC[0] = FecQueryHistoryEvent; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aEvent & 0xFF; + uDataTX.body.DPFC[3] = (aEvent>>8) & 0xFF; + uDataTX.body.DPFC[4] = aSY; + uDataTX.body.DPFC[5] = aSM; + uDataTX.body.DPFC[6] = aSD; + + uSetTXData(); +} + +void TFecBus::fMsgTX43_StopQueryDeviceEvent(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecStopQueryDeviceEvent; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); +} + +void TFecBus::fMsgTX44_QueryFECBusVer(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecQueryFECBusVer; + + uSetTXData(); +} + +void TFecBus::fMsgTX45_QueryDeviceList(u8 aDestAddr) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 1; + uDataTX.body.DPFC[0] = FecQueryDeviceList; + + uSetTXData(); + + CommPrm.GetCmd45Data.type = 1; +} + +void TFecBus::fMsgTX45_QueryDeviceList(u8 aDestAddr, u8 aCtlNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 2; + uDataTX.body.DPFC[0] = FecQueryDeviceList; + uDataTX.body.DPFC[1] = aCtlNum; + + uSetTXData(); + + CommPrm.GetCmd45Data.type = 2; +} + +void TFecBus::fMsgTX45_QueryDeviceList(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 3; + uDataTX.body.DPFC[0] = FecQueryDeviceList; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + + uSetTXData(); + + CommPrm.GetCmd45Data.type = 3; +} + +void TFecBus::fMsgTX45_QueryDeviceList(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev) +{ + if(aDestAddr > 63)return; + + uDataTX.body.FrmType = FecFrmTX; + uDataTX.body.DestAddr = aDestAddr; + uDataTX.body.Priority = Priority2; + uDataTX.body.SrcAddr = FecCtlAddr; + uDataTX.body.Dlen = 4; + uDataTX.body.DPFC[0] = FecQueryDeviceList; + uDataTX.body.DPFC[1] = aCtlNum; + uDataTX.body.DPFC[2] = aUnitNum; + uDataTX.body.DPFC[3] = aDev; + + uSetTXData(); + + CommPrm.GetCmd45Data.type = 4; +} + +void TFecBus::uSetTXData() +{ + u32 x = 0,y = 0,section = 0; + u16 crc_value; + + if(uDataTX.body.Dlen > 8){ + uMsgOut.avalibel = 1; + uMsgOut.UsingMsgIndex = 1; + uMsgOut.FrameTick = 0; + if(uDataTX.body.Dlen % 8){ + uMsgOut.FrameNum = uDataTX.body.Dlen / 8 + 2; + }else{ + uMsgOut.FrameNum = uDataTX.body.Dlen / 8 + 1; + } + if(uMsgOut.FrameNum > 4)return; + uMsgOutIndex++; + if(uMsgOutIndex > 63)uMsgOutIndex = 1; + for(x=1;x 8){ + uMsgOut.Section[x].body.Dlen = 8; + }else{ + uMsgOut.Section[x].body.Dlen = uDataTX.body.Dlen - ((x - 1)*8); + } + for(y = 0;y < uMsgOut.Section[x].body.Dlen;y++){ + uMsgOut.Section[x].body.DPFC[y] = uDataTX.body.DPFC[(x-1)*8+y]; + } + crc_value = Crc16(uMsgOut.Section[x].D8,(8 + uMsgOut.Section[x].body.Dlen)); + uMsgOut.Section[x].body.CrcLoByte = crc_value & 0xFF; + uMsgOut.Section[x].body.CrcHiByte = (crc_value>>8) & 0xFF; + uMsgOut.Section[x].body.Eop = FecEnding; + } + + uMsgOut.Section[0].body.Header = FecHeader; + uMsgOut.Section[0].body.FrmType = uDataTX.body.FrmType; + uMsgOut.Section[0].body.DestAddr = uDataTX.body.DestAddr; + uMsgOut.Section[0].body.Priority = uDataTX.body.Priority; + uMsgOut.Section[0].body.SrcAddr = uDataTX.body.SrcAddr; + uMsgOut.Section[0].body.MsgIndex = uMsgOutIndex; + uMsgOut.Section[0].body.FrmIndex = 0; + uMsgOut.Section[0].body.Dlen = 2; + uMsgOut.Section[0].body.DPFC[0] = FecFunStateAck; + uMsgOut.Section[0].body.DPFC[1] = ackMsgSectionEnd; + crc_value = Crc16(uMsgOut.Section[0].D8,(8 + uMsgOut.Section[0].body.Dlen)); + uMsgOut.Section[0].body.CrcLoByte = crc_value & 0xFF; + uMsgOut.Section[0].body.CrcHiByte = (crc_value>>8) & 0xFF; + uMsgOut.Section[0].body.Eop = FecEnding; + }else{ + uMsgOut.avalibel = 1; + uMsgOut.UsingMsgIndex = 0; + + uMsgOut.Section[0].body.Header = FecHeader; + uMsgOut.Section[0].body.FrmType = uDataTX.body.FrmType; + uMsgOut.Section[0].body.DestAddr = uDataTX.body.DestAddr; + uMsgOut.Section[0].body.Priority = uDataTX.body.Priority; + uMsgOut.Section[0].body.SrcAddr = uDataTX.body.SrcAddr; + + if(0 == uDataTX.body.DPFC[0]){ + uMsgOut.Section[0].body.MsgIndex = 0; + }else{ + uMsgOutIndex++; + if(uMsgOutIndex > 63)uMsgOutIndex = 1; + uMsgOut.Section[0].body.MsgIndex = uMsgOutIndex; + } + + uMsgOut.Section[0].body.FrmIndex = 0; + uMsgOut.Section[0].body.Dlen = uDataTX.body.Dlen; + + for(x=0;x>8) & 0xFF; + uMsgOut.Section[0].body.Eop = FecEnding; + } + + TxSetFlag = 1; +} + +void TFecBus::uDataTXTask()//10ms +{ + unsigned int retry_time = 0; + + if(OnTransmite.OnGoing){ + OnTransmite.TimeOutTick++; + + retry_time = 99;//1000ms retry + + if(OnTransmite.TimeOutTick > retry_time){ + OnTransmite.TimeOutTick = 0; + + if(OnTransmite.RetryTimes < 3){ + OnTransmite.RetryFLAG = 1; + }else{ + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + } + } + } + + if(!fec_std_tx_is_busy()){ + if(TxSetFlag){ + if(uMsgOut.UsingMsgIndex){ + uMsgOut.FrameTick++; + if(uMsgOut.FrameTick >= uMsgOut.FrameNum){ + uMsgOut.FrameTick = 0; + TxSetFlag = 0; + } + set_fec_std_tx_data(uMsgOut.Section[uMsgOut.FrameTick].D8); + }else{ + set_fec_std_tx_data(uMsgOut.Section[0].D8); + TxSetFlag = 0; + } + OnTransmite.TimeOutTick = 0; + OnTransmite.AckOk = 0; + OnTransmite.OnGoing = 1; + }else + if(OnTransmite.RetryFLAG){ + if(uMsgOut.UsingMsgIndex){ + uMsgOut.FrameTick++; + if(uMsgOut.FrameTick >= uMsgOut.FrameNum){ + uMsgOut.FrameTick = 0; + OnTransmite.RetryFLAG = 0; + OnTransmite.RetryTimes++; + } + set_fec_std_tx_data(uMsgOut.Section[uMsgOut.FrameTick].D8); + }else{ + set_fec_std_tx_data(uMsgOut.Section[0].D8); + OnTransmite.RetryFLAG = 0; + OnTransmite.RetryTimes++; + } + + OnTransmite.TimeOutTick = 0; + OnTransmite.AckOk = 0; + OnTransmite.OnGoing = 1; + } + } +} + +//表 C.13 查询设备历史事件数据帧 及其 应答数据帧 +//>---------------> +void TFecBus::fMsgC7_QueryDevEventHistory (TFecItemPath aPath, TFecEventCode aEvt, TsDateTime aDT) +{ + u32 i,idx; + u32 CanExdId_29; + u8 aPriority = 3; + + idx = FindIdleMsgIndex(); + if(BusType == UsingUart){ + for(i=0; i<1; i++){ + uMsgOut.Section[i].body.Header = 0x7E; + uMsgOut.avalibel = 1; + uMsgOut.Section[i].body.FrmType = 1; + uMsgOut.Section[i].body.DestAddr = aPath.DevNum; + uMsgOut.Section[i].body.Priority = aPriority; + uMsgOut.Section[i].body.SrcAddr = ThisAddr; + uMsgOut.Section[i].body.MsgIndex = idx; + uMsgOut.Section[i].body.Eop = 0x7E; + } + i = 0; + uMsgOut.Section[i].body.FrmIndex = 0; + uMsgOut.Section[i].body.Dlen = 7; + uMsgOut.Section[i].body.DPFC[0] = 0x2A; //The Fuction Code + uMsgOut.Section[i].body.DPFC[1] = aPath.CtlNum; + uMsgOut.Section[i].body.DPFC[2] = static_cast(aEvt & 0x00FF); + uMsgOut.Section[i].body.DPFC[3] = static_cast( (aEvt>>8) & 0x00FF); + uMsgOut.Section[i].body.DPFC[4] = aDT.Year; + uMsgOut.Section[i].body.DPFC[5] = aDT.Month; + uMsgOut.Section[i].body.DPFC[6] = aDT.Day; + uMsgOut.Section[i].body.DPFC[7] = 0; + }else + if(BusType == UsingCan){ + CanExdId_29 = 0; + for(i=0; i<4; i++){ + cMsgOut.Section[i].avalibel = 1; + CanExdId_29 |= 1<<27; + CanExdId_29 |= (static_cast(aPath.DevNum)) << 21; + CanExdId_29 |= (static_cast(aPriority)) << 19; + CanExdId_29 |= (static_cast(ThisAddr)) << 13; + CanExdId_29 |= (static_cast(idx)) << 7; + } + i = 0; + CanExdId_29 |= static_cast(0) ; + cMsgOut.Section[i].body.spl.Dlen = 7; + cMsgOut.Section[i].body.spl.DPFC[0] = 0x2A; //The Fuction Code + cMsgOut.Section[i].body.spl.DPFC[1] = aPath.CtlNum; + cMsgOut.Section[i].body.spl.DPFC[2] = static_cast(aEvt & 0x00FF); + cMsgOut.Section[i].body.spl.DPFC[3] = static_cast( (aEvt>>8) & 0x00FF); + cMsgOut.Section[i].body.spl.DPFC[4] = aDT.Year; + cMsgOut.Section[i].body.spl.DPFC[5] = aDT.Month; + cMsgOut.Section[i].body.spl.DPFC[6] = aDT.Day; + cMsgOut.Section[i].body.spl.DPFC[7] = 0; + } +} + +//<-----------------< +void TFecBus::fMsgC13_Reply_QueryDevEventHistory (TFecItemPath aPath, u16 aDtc, u16 aEvt, u16 aDevState, TsDateTime aDT) //42 +{ + u32 i,idx; + u32 CanExdId_29; + u8 aPriority = 3; + + idx = FindIdleMsgIndex(); + if(BusType == UsingUart){ + for(i=0; i<4; i++){ + uMsgOut.Section[i].body.Header = 0x7E; + uMsgOut.avalibel = 1; + uMsgOut.Section[i].body.FrmType = 1; + uMsgOut.Section[i].body.DestAddr = aPath.DevNum; + uMsgOut.Section[i].body.Priority = aPriority; + uMsgOut.Section[i].body.SrcAddr = ThisAddr; + uMsgOut.Section[i].body.MsgIndex = idx; + uMsgOut.Section[i].body.Eop = 0x7E; + } + i = 0; + uMsgOut.Section[i].body.FrmIndex = 1; + uMsgOut.Section[i].body.Dlen = 8; + uMsgOut.Section[i].body.DPFC[0] = 0x2A; //The Fuction Code + uMsgOut.Section[i].body.DPFC[1] = aPath.CtlNum; + uMsgOut.Section[i].body.DPFC[2] = aPath.UnitNum; + uMsgOut.Section[i].body.DPFC[3] = aPath.DevNum; + uMsgOut.Section[i].body.DPFC[4] = aPath.ChannelNum; + uMsgOut.Section[i].body.DPFC[5] = static_cast(aDtc & 0x00FF); + uMsgOut.Section[i].body.DPFC[6] = static_cast( (aDtc>>8) & 0x00FF); + uMsgOut.Section[i].body.DPFC[7] = static_cast(aEvt & 0x00FF); + uMsgOut.Section[i].body.CrcLoByte = 0; + uMsgOut.Section[i].body.CrcHiByte = 0; + i = 1; + uMsgOut.Section[i].body.FrmIndex = 2; + uMsgOut.Section[i].body.Dlen = 8; + uMsgOut.Section[i].body.DPFC[0] = static_cast( (aEvt>>8) & 0x00FF); + uMsgOut.Section[i].body.DPFC[1] = static_cast(aDevState & 0x00FF); + uMsgOut.Section[i].body.DPFC[2] = static_cast( (aDevState>>8) & 0x00FF); + uMsgOut.Section[i].body.DPFC[3] = aDT.Year; + uMsgOut.Section[i].body.DPFC[4] = aDT.Month; + uMsgOut.Section[i].body.DPFC[5] = aDT.Day; + uMsgOut.Section[i].body.DPFC[6] = aDT.Hour; + uMsgOut.Section[i].body.DPFC[7] = aDT.Minute; + uMsgOut.Section[i].body.CrcLoByte = 0; + uMsgOut.Section[i].body.CrcHiByte = 0; + i = 2; + uMsgOut.Section[i].body.FrmIndex = 3; + uMsgOut.Section[i].body.Dlen = 1; + uMsgOut.Section[i].body.DPFC[0] = aDT.Second; + uMsgOut.Section[i].body.DPFC[1] = 0; + uMsgOut.Section[i].body.DPFC[2] = 0; + uMsgOut.Section[i].body.DPFC[3] = 0; + uMsgOut.Section[i].body.DPFC[4] = 0; + uMsgOut.Section[i].body.DPFC[5] = 0; + uMsgOut.Section[i].body.DPFC[6] = 0; + uMsgOut.Section[i].body.DPFC[7] = 0; + uMsgOut.Section[i].body.CrcLoByte = 0; + uMsgOut.Section[i].body.CrcHiByte = 0; + i = 3; + uMsgOut.Section[i].body.FrmIndex = 0; + uMsgOut.Section[i].body.Dlen = 2; + uMsgOut.Section[i].body.DPFC[0] = 0x0F; // End this Index + uMsgOut.Section[i].body.DPFC[1] = 0x00; + uMsgOut.Section[i].body.DPFC[2] = 0; + uMsgOut.Section[i].body.DPFC[3] = 0; + uMsgOut.Section[i].body.DPFC[4] = 0; + uMsgOut.Section[i].body.DPFC[5] = 0; + uMsgOut.Section[i].body.DPFC[6] = 0; + uMsgOut.Section[i].body.DPFC[7] = 0; + uMsgOut.Section[i].body.CrcLoByte = 0; + uMsgOut.Section[i].body.CrcHiByte = 0; + }else + if(BusType == UsingCan){ + CanExdId_29 = 0; + for(i=0; i<4; i++){ + cMsgOut.Section[i].avalibel = 1; + CanExdId_29 |= 1<<27; + CanExdId_29 |= (static_cast(aPath.DevNum)) << 21; + CanExdId_29 |= (static_cast(aPriority)) << 19; + CanExdId_29 |= (static_cast(ThisAddr)) << 13; + CanExdId_29 |= (static_cast(idx)) << 7; + } + i = 0; + CanExdId_29 |= static_cast(1) ; + cMsgOut.Section[i].body.spl.Dlen = 8; + cMsgOut.Section[i].body.spl.DPFC[0] = 0x2A; //The Fuction Code + cMsgOut.Section[i].body.spl.DPFC[1] = aPath.CtlNum; + cMsgOut.Section[i].body.spl.DPFC[2] = aPath.UnitNum; + cMsgOut.Section[i].body.spl.DPFC[3] = aPath.DevNum; + cMsgOut.Section[i].body.spl.DPFC[4] = aPath.ChannelNum; + cMsgOut.Section[i].body.spl.DPFC[5] = static_cast(aDtc & 0x00FF); + cMsgOut.Section[i].body.spl.DPFC[6] = static_cast( (aDtc>>8) & 0x00FF); + cMsgOut.Section[i].body.spl.DPFC[7] = static_cast(aEvt & 0x00FF); + i = 1; + CanExdId_29 |= static_cast(2) ; + cMsgOut.Section[i].body.spl.Dlen = 8; + cMsgOut.Section[i].body.spl.DPFC[0] = static_cast( (aEvt>>8) & 0x00FF); + cMsgOut.Section[i].body.spl.DPFC[1] = static_cast(aDevState & 0x00FF); + cMsgOut.Section[i].body.spl.DPFC[2] = static_cast( (aDevState>>8) & 0x00FF); + cMsgOut.Section[i].body.spl.DPFC[3] = aDT.Year; + cMsgOut.Section[i].body.spl.DPFC[4] = aDT.Month; + cMsgOut.Section[i].body.spl.DPFC[5] = aDT.Day; + cMsgOut.Section[i].body.spl.DPFC[6] = aDT.Hour; + cMsgOut.Section[i].body.spl.DPFC[7] = aDT.Minute; + i = 2; + CanExdId_29 |= static_cast(3) ; + cMsgOut.Section[i].body.spl.Dlen = 1; + cMsgOut.Section[i].body.spl.DPFC[0] = aDT.Second; + cMsgOut.Section[i].body.spl.DPFC[1] = 0; + cMsgOut.Section[i].body.spl.DPFC[2] = 0; + cMsgOut.Section[i].body.spl.DPFC[3] = 0; + cMsgOut.Section[i].body.spl.DPFC[4] = 0; + cMsgOut.Section[i].body.spl.DPFC[5] = 0; + cMsgOut.Section[i].body.spl.DPFC[6] = 0; + cMsgOut.Section[i].body.spl.DPFC[7] = 0; + i = 3; + CanExdId_29 |= static_cast(0) ; + cMsgOut.Section[i].body.spl.Dlen = 2; + cMsgOut.Section[i].body.spl.DPFC[0] = 0x0F; // End this Index + cMsgOut.Section[i].body.spl.DPFC[1] = 0x00; + cMsgOut.Section[i].body.spl.DPFC[2] = 0; + cMsgOut.Section[i].body.spl.DPFC[3] = 0; + cMsgOut.Section[i].body.spl.DPFC[4] = 0; + cMsgOut.Section[i].body.spl.DPFC[5] = 0; + cMsgOut.Section[i].body.spl.DPFC[6] = 0; + cMsgOut.Section[i].body.spl.DPFC[7] = 0; + } +} + +void TFecBus::fMsgC13_Reply_QueryDevEventHistory (TFecItemPath aPath, TFecDevTypeCode aDtc, TFecEventCode aEvt, u16 aDevState, TsDateTime aDT) //42 +{ + u16 tDtc, tEvt; + tDtc = static_cast(aDtc); + tEvt = static_cast(aEvt); + fMsgC13_Reply_QueryDevEventHistory(aPath, tDtc, tEvt, aDevState, aDT); +} + + +//表 C.14 查询设备列表应答数据帧 >_________________________________________________________________________ +void TFecBus::LongReplyClearTx(void) +{ + LongReplyTx.PkgCount = 0; + LongReplyTx.Body.D32[0] = 0; + LongReplyTx.Body.D32[1] = 0; +} + +void TFecBus::C14_DevList_CtlClearTx(void) +{ + LongReplyTx.PkgCount = 0; + LongReplyClearTx(); + LongReplyTx.Body.CtlListInf.CtlCount = 0; +} + +void TFecBus::C14_DevList_UnitClearTx(void) +{ + LongReplyTx.PkgCount = 0; + LongReplyClearTx(); + LongReplyTx.Body.UnitListInf.UnitCount = 0; +} + +void TFecBus::C14_DevList_DevClearTx(void) +{ + LongReplyTx.PkgCount = 0; + LongReplyClearTx(); + LongReplyTx.Body.DevListInf.DevCount = 0; +} + +void TFecBus::C14_DevList_ChlClearTx(void) +{ + LongReplyTx.PkgCount = 0; + LongReplyClearTx(); + LongReplyTx.Body.ChannelListInf.ChannelCount = 0; +} + +void TFecBus::C14_DevList_CtlAdd (u8 aCtlNum, TFecDevTypeCode aDtc) //Add Item to 控制器列表 +{ + u32 i; + if(aCtlNum < 64){ + i = LongReplyTx.Body.CtlListInf.CtlCount; + if(i < 64){ + LongReplyTx.Body.CtlListInf.List[i].CtlNum = aCtlNum; + LongReplyTx.Body.CtlListInf.List[i].DevTypeLoByte = static_cast(aDtc & 0x00FF) ; + LongReplyTx.Body.CtlListInf.List[i].DevTypeHiByte = static_cast( (aDtc >> 8) & 0x00FF ) ; + } + LongReplyTx.Body.CtlListInf.CtlCount++; + } +} + +void TFecBus::C14_DevList_UnitAdd (u8 aCtlNum, u8 aUnitNum, TFecDevTypeCode aDtc) //Add Item to 单元列表 +{ + +} + +void TFecBus::C14_DevList_DevAdd (u8 aCtlNum, u8 aUnitNum, u8 aDev, TFecDevTypeCode aDtc) //Add Item to 设备列表 +{ + +} + +void TFecBus::C14_DevList_ChlAdd (u8 aCtlNum, u8 aUnitNum, u8 aDev, u8 aChl, TFecDevTypeCode aDtc) //Add Item to 通道列表 +{ + +} + +void fMsgC14_Reply_QueryDevList_Ctl (void) //45 //查询控制器列表 +{ + +} + +void fMsgC14_Reply_QueryDevList_Unit (void) //45 //查询单元列表 +{ + +} + +void fMsgC14_Reply_QueryDevList_Dev (void) //45 //查询设备列表 +{ + +} + +void fMsgC14_Reply_QueryDevList_Chl (void) //45 //查询通道列表 +{ + +} + +//___________________________________________________________________________________________________< C14 + + +//通讯阶段 下发事件，下发命令，建立连接 +//通讯状态 巡检，功能码 +//建立连接 + +void TFecBus::Task10ms(void) +{ + uDataTXTask(); + if(CommPrm.NoAckTick)CommPrm.NoAckTick--; +} + +void TFecBus::Task100ms(void) +{ + if(CommPrm.TimeoutTick < 10000)CommPrm.TimeoutTick++; + else CommPrm.TimeoutTick = 10000; +} + +void TFecBus::SetCommAddr(u8 addr) +{ + CommPrm.CuuerntAddr = addr; +} + +void TFecBus::SetRegister(u8 aAddr) +{ + CommPrm.Register[aAddr] = 1; +} + +u8 TFecBus::GetRegisterStatus(u8 aAddr) +{ + return CommPrm.Register[aAddr]; +} + +void TFecBus::SetLogout(u8 aAddr) +{ + CommPrm.Register[aAddr] = 0; +} + +void TFecBus::SetUpCommTask(void) +{ + switch(CommPrm.State){ + case FecCommExit : + if((CommPrm.CuuerntAddr < 63)&&(CommPrm.CuuerntAddr > 1)){ + CommPrm.CuuerntAddr++; + CommPrm.Phase = FecSetUpComm; + CommPrm.State = FecCommQueryVer44; + }else + if(63 == CommPrm.CuuerntAddr){ + CommPrm.CuuerntAddr = 2; + CommPrm.Phase = FecPolling; + CommPrm.State = FecCommPolling33; + } + break; + + case FecCommQueryVer44 : + fMsgTX44_QueryFECBusVer(CommPrm.CuuerntAddr);//发44 + CommPrm.State = FecCommQueryVer44Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryVer44Ack : //等待44回复 + if(CommPrm.AckStatus){ + CommPrm.State = FecCommSyncTime04; + SetRegister(CommPrm.CuuerntAddr); + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + + case FecCommSyncTime04 : //发04 + getSysTime(); + fMsgTX04_SyncTime(CommPrm.CuuerntAddr, 0, \ + dateTime.Year, \ + dateTime.Mon, \ + dateTime.Day, \ + dateTime.Hour, \ + dateTime.Min, \ + dateTime.Sec); + CommPrm.State = FecCommSyncTime04Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommSyncTime04Ack : //等待04回复 + if(CommPrm.AckStatus){ + CommPrm.State = FecCommQueryCurrentEvent41; + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + + case FecCommQueryCurrentEvent41 : + fMsgTX41_QueryCurrentEvent(CommPrm.CuuerntAddr, 0, evtRsv0); + //直到事件结束，下一个地址44，...................退出进入巡检 + ClearCurrentEventList(CommPrm.CuuerntAddr); + CommPrm.State = FecCommQueryCurrentEvent41Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryCurrentEvent41Ack : + if(1 == CommPrm.AckStatus){ + //fMsgTX15_Ack_StateAck(CommPrm.CuuerntAddr, ackRecDataCorrect); + if(1 == EventCodePrm[CommPrm.CurrentEventData.Data.EventCode]){ + fMsgRpy18_Ack_InformedGeneralEvent(CommPrm.CuuerntAddr); + }else + if(2 == EventCodePrm[CommPrm.CurrentEventData.Data.EventCode]){ + fMsgRpy17_Ack_PublishEmergencyEvent(CommPrm.CuuerntAddr); + } + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + }else + if(2 == CommPrm.AckStatus){ + CommPrm.State = FecCommQueryCurrentEvent41Ending; + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + + case FecCommQueryCurrentEvent41Ending : + CommPrm.State = FecCommExit; + break; + + default : + CommPrm.CuuerntAddr = 2; + CommPrm.Phase = FecPolling; + CommPrm.State = FecCommPolling33; + break; + } +} + +void TFecBus::ClearDownEventList() +{ + CommPrm.DownEventCount = 0; + CommPrm.DownEventTick = 0; +} + +void TFecBus::AddDownEventList(TFecEventBufBody * pEvent) +{ + u32 i; + u32 aSAddr; + + if(CommPrm.DownEventCount >= dFecBus_DownEventBufCount)return; + + aSAddr = dAddrSdram_FECDownEventBuf + (CommPrm.DownEventCount * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + *(volatile unsigned int *)(aSAddr + (i*4)) = pEvent->D32[i]; + + CommPrm.DownEventCount++; +} + +void TFecBus::SetDownEventData(u32 Ord) +{ + u32 i; + u32 aSAddr; + + if(Ord >= dFecBus_DownEventBufCount)return; + + aSAddr = dAddrSdram_FECDownEventBuf + (Ord * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + CommPrm.DownEventData.D32[i] = (*(volatile unsigned int *)(aSAddr + (i*4))); +} + +void TFecBus::EnterSetDownEvent(u8 aAddr) +{ + if((aAddr < 2)||(aAddr > 63))return; + + CommPrm.DownEventTick = 0; + CommPrm.SetDownEventFlag = 1; + CommPrm.SetDownPath.Addr = aAddr; +} + + +void TFecBus::ClearUpEventList(u8 aAddr) +{ + if((aAddr < 2)||(aAddr > 63))return; + + CommPrm.UpEventCount[aAddr] = 0; + CommPrm.UpEventSRTick[aAddr] = 0; +} + +void TFecBus::AddUpEventList(u8 aAddr, TFecEventBufBody * pEvent) +{ + u32 i; + u32 aSAddr; + + if((aAddr < 2)||(aAddr > 63))return; + + if(CommPrm.UpEventCount[aAddr] >= dFecBus_OneBufCount){ + CommPrm.UpEventCount[aAddr] = dFecBus_OneBufCount; + aSAddr = dAddrSdram_FECUpEventBuf + ((aAddr-2) * dFecBus_OneBufCount) + (CommPrm.UpEventSRTick[aAddr] * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + *(volatile unsigned int *)(aSAddr + (i*4)) = pEvent->D32[i]; + + CommPrm.UpEventSRTick[aAddr]++; + }else{ + aSAddr = dAddrSdram_FECUpEventBuf + ((aAddr-2) * dFecBus_OneBufCount) + (CommPrm.UpEventCount[aAddr] * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + *(volatile unsigned int *)(aSAddr + (i*4)) = pEvent->D32[i]; + + CommPrm.UpEventCount[aAddr]++; + } +} + +void TFecBus::ClearCurrentEventList(u8 aAddr) +{ + if((aAddr < 2)||(aAddr > 63))return; + + CommPrm.CurrentEventCount[aAddr] = 0; + CommPrm.CurrentEventSRTick[aAddr] = 0; +} + +void TFecBus::AddCurrentEventList(u8 aAddr, TFecEventBufBody * pEvent) +{ + u32 i; + u32 aSAddr; + + if((aAddr < 2)||(aAddr > 63))return; + + if(CommPrm.CurrentEventCount[aAddr] >= dFecBus_OneBufCount){ + CommPrm.CurrentEventCount[aAddr] = dFecBus_OneBufCount; + aSAddr = dAddrSdram_FECCurrentEventBuf + ((aAddr-2) * dFecBus_OneBufCount) + (CommPrm.CurrentEventSRTick[aAddr] * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + *(volatile unsigned int *)(aSAddr + (i*4)) = pEvent->D32[i]; + + CommPrm.CurrentEventSRTick[aAddr]++; + }else{ + aSAddr = dAddrSdram_FECCurrentEventBuf + ((aAddr-2) * dFecBus_OneBufCount) + (CommPrm.CurrentEventCount[aAddr] * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + *(volatile unsigned int *)(aSAddr + (i*4)) = pEvent->D32[i]; + + CommPrm.CurrentEventCount[aAddr]++; + } +} + +void TFecBus::ClearHistoryEventList() +{ + CommPrm.HistoryEventCount = 0; + CommPrm.HistoryEventSRTick = 0; +} + +void TFecBus::AddHistoryEventList(TFecEventBufBody * pEvent) +{ + u32 i; + u32 aAddr; + + if(CommPrm.HistoryEventCount >= dFecBus_HistoryEventBufCount){ + CommPrm.HistoryEventCount = dFecBus_HistoryEventBufCount; + aAddr = dAddrSdram_FECHistoryEventBuf + (CommPrm.HistoryEventSRTick * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + *(volatile unsigned int *)(aAddr + (i*4)) = pEvent->D32[i]; + + CommPrm.HistoryEventSRTick++; + }else{ + aAddr = dAddrSdram_FECHistoryEventBuf + (CommPrm.HistoryEventCount * dFecBus_BufEntrySize_Event); + for(i = 0;i<(dFecBus_BufEntrySize_Event/4);i++) + *(volatile unsigned int *)(aAddr + (i*4)) = pEvent->D32[i]; + + CommPrm.HistoryEventCount++; + } +} + +void TFecBus::DownEventTask(void) +{ + switch(CommPrm.State){ + case FecCommExit : + CommPrm.Phase = FecPolling; + break; + /* + case FecCommPolling33 : + fMsgTX33_InspectionDevice(CommPrm.CuuerntAddr);//发33 + CommPrm.State = FecCommPolling33Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + */ + case FecCommPolling33Ack : //等待回复 + if(1 == CommPrm.AckStatus){ + //set down event prm + CommPrm.DownEventTick = 0; + if(CommPrm.DownEventCount){ + SetDownEventData(CommPrm.DownEventTick); + if(2 == EventCodePrm[CommPrm.DownEventData.Data.EventCode]){ + CommPrm.State = FecCommDownEvent05; + }else + if(1 == EventCodePrm[CommPrm.DownEventData.Data.EventCode]){ + CommPrm.State = FecCommDownEvent06; + } + CommPrm.DownEventTick++; + }else{ + CommPrm.State = FecCommPolling33Up; + } + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + //按列表下发事件 + case FecCommDownEvent05 : //05下发事件 + fMsgTX05_PublishEmergencyEvent(CommPrm.CuuerntAddr, &CommPrm.DownEventData);//装载事件 + CommPrm.State = FecCommDownEvent05Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommDownEvent05Ack : //等待05回复 + if(CommPrm.AckStatus){ + if(CommPrm.DownEventTick < CommPrm.DownEventCount){ + SetDownEventData(CommPrm.DownEventTick); + if(2 == EventCodePrm[CommPrm.DownEventData.Data.EventCode]){ + CommPrm.State = FecCommDownEvent05; + }else + if(1 == EventCodePrm[CommPrm.DownEventData.Data.EventCode]){ + CommPrm.State = FecCommDownEvent06; + } + CommPrm.DownEventTick++; + }else{ + CommPrm.State = FecCommPolling33Up; + } + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + + case FecCommDownEvent06 : //06下发事件 + fMsgTX06_PublishGeneralEvent(CommPrm.CuuerntAddr, &CommPrm.DownEventData); + CommPrm.State = FecCommDownEvent06Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommDownEvent06Ack : //等待06回复 + if(CommPrm.AckStatus){ + if(CommPrm.DownEventTick < CommPrm.DownEventCount){ + SetDownEventData(CommPrm.DownEventTick); + if(2 == EventCodePrm[CommPrm.DownEventData.Data.EventCode]){ + CommPrm.State = FecCommDownEvent05; + }else + if(1 == EventCodePrm[CommPrm.DownEventData.Data.EventCode]){ + CommPrm.State = FecCommDownEvent06; + } + CommPrm.DownEventTick++; + }else{ + CommPrm.State = FecCommPolling33Up; + } + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + /* + case FecCommDownEvent07 : //07下发事件 + CommPrm.DownEventTick++; + if(CommPrm.DownEventTick > CommPrm.DownEventCount){ + CommPrm.State = FecCommPolling33Up; + }else{ + fMsgTX07_PublishAdjustEvent(CommPrm.CuuerntAddr, &CommPrm.DownEventData); + CommPrm.State = FecCommDownEvent07Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + } + break; + + case FecCommDownEvent07Ack : //等待07回复 + if(CommPrm.AckStatus){ + //CommPrm.State = FecCommDownEvent05; + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + */ + case FecCommPolling33Up : + fMsgTX33_InspectionDevice(CommPrm.CuuerntAddr);//发33 + CommPrm.State = FecCommPolling33UpAck; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommPolling33UpAck : + if(3 == CommPrm.AckStatus){ + CommPrm.State = FecCommExit; + }else + if(2 == CommPrm.AckStatus){ + if(1 == EventCodePrm[CommPrm.UpEventData.Data.EventCode]){ + fMsgRpy18_Ack_InformedGeneralEvent(CommPrm.CuuerntAddr); + CommPrm.NoAckTick = 3;//delay 30ms + CommPrm.State = FecCommDelay; + }else + if(2 == EventCodePrm[CommPrm.UpEventData.Data.EventCode]){ + fMsgRpy17_Ack_PublishEmergencyEvent(CommPrm.CuuerntAddr); + CommPrm.NoAckTick = 3;//delay 30ms + CommPrm.State = FecCommDelay; + } + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + + case FecCommDelay ://延时等待发送完 + if(0 == CommPrm.NoAckTick)CommPrm.State = FecCommPolling33Up; + break; + + default : + CommPrm.Phase = FecPolling; + CommPrm.State = FecCommExit; + break; + } +} + +void TFecBus::EnterSetDownCmd(TFecFunctionCode aCmd, TFecCmdPath * aCmdPath) +{ + if((aCmdPath->Addr < 2)||(aCmdPath->Addr > 63))return; + + if((FecFunQueryDeviceState == aCmd)||(FecFunQueryDeviceConfig == aCmd)||(FecFunQueryDeviceIdf == aCmd)||(FecQueryDeviceList == aCmd)){ + if((aCmdPath->PathLevel)&&(aCmdPath->PathLevel < 5)){ + ; + }else return; + }else + if(FecQueryCurrentEvent == aCmd){ + if((aCmdPath->PathLevel > 2)&&(aCmdPath->PathLevel < 5)){ + ; + }else return; + } + + CommPrm.SetDownCmdFlag = 1; + CommPrm.SetDownPath.Addr = aCmdPath->Addr; + + switch(aCmd){ + case FecFunSyncSysTick ://0 同步系统节拍 + //CommPrm.State = FecCommSyncSysTick00; + CommPrm.SetDownCmdState = FecCommSyncSysTick00; + break; + + case FecFunSysReset ://1 系统复位 + CommPrm.SetDownCmdState = FecCommSysReset01; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + break; + + case FecFunSysMute ://2 系统消音 + CommPrm.SetDownCmdState = FecCommSysMute02; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + break; + + case FecFunSysSlefCheck ://3 系统自检 + CommPrm.SetDownCmdState = FecCommSysSlefCheck03; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + break; + + case FecFunSyncTime :// 设置时间 + CommPrm.SetDownCmdState = FecCommSyncTime04; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + break; + + case FecFunQueryDeviceState ://34 查设备状态 + CommPrm.SetDownCmdState = FecCommQueryDeviceState34; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + break; + + case FecFunQueryDeviceConfig ://35 查设备配置 + CommPrm.SetDownCmdState = FecCommQueryDeviceConfig35; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + break; + + case FecFunQueryDeviceIdf ://36 查设备标识 + CommPrm.SetDownCmdState = FecCommQueryDeviceIdf36; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + break; + + case FecFunQueryDeviceParameter ://37 查设备参量 + CommPrm.SetDownCmdState = FecCommQueryDeviceParameter37; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + CommPrm.SetDownPath.ChannelNum = aCmdPath->ChannelNum; + break; + + case FecFunQueryDeviceDescp ://38 查设备注释 + CommPrm.SetDownCmdState = FecCommQueryDeviceDescp38; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + break; + + case FecFunQueryDeviceProgram ://39 查设备编程 + CommPrm.SetDownCmdState = FecCommQueryDeviceProgram39; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + break; + + case FecFunQueryDeviceRegisterInfo ://40 查注册登记信息 + CommPrm.SetDownCmdState = FecCommQueryDeviceRegisterInfo40; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + break; + + case FecQueryCurrentEvent :// 查询当前事件 + CommPrm.SetDownCmdState = FecCommQueryCurrentEvent41; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.Event = aCmdPath->Event; + break; + + case FecQueryHistoryEvent ://42 查设备历史事件 + CommPrm.SetDownCmdState = FecCommQueryHistoryEvent42; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.Event = aCmdPath->Event; + CommPrm.SetDownPath.SYear = aCmdPath->SYear; + CommPrm.SetDownPath.SMon = aCmdPath->SMon; + CommPrm.SetDownPath.SDay = aCmdPath->SDay; + break; + + case FecStopQueryDeviceEvent ://43 停止查询设备事件 + CommPrm.SetDownCmdState = FecCommStopQueryDeviceEvent43; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + break; + + case FecQueryFECBusVer ://44 查询版本 + CommPrm.SetDownCmdState = FecCommQueryVer44; + break; + + case FecQueryDeviceList ://45 查设备列表 + CommPrm.SetDownCmdState = FecCommQueryDeviceList45; + CommPrm.SetDownPath.CtlNum = aCmdPath->CtlNum; + CommPrm.SetDownPath.UnitNum = aCmdPath->UnitNum; + CommPrm.SetDownPath.DevNum = aCmdPath->DevNum; + CommPrm.SetDownPath.ChannelNum = aCmdPath->ChannelNum; + break; + + default : + CommPrm.Phase = FecPolling; + CommPrm.SetDownCmdState = FecCommNone; + break; + } +} +void TFecBus::DownCmdAckHandle(void) +{ + if(CommPrm.AckStatus){ + CommPrm.State = FecCommExit; + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } +} + +void TFecBus::DownCmdTask(void) +{ + switch(CommPrm.State){ + case FecCommExit : + CommPrm.Phase = FecPolling; + break; + /* + case FecCommPolling33 : + fMsgTX33_InspectionDevice(CommPrm.CuuerntAddr);//发33 + CommPrm.State = FecCommPolling33Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + */ + case FecCommPolling33Ack : //等待回复 + CommPrm.State = CommPrm.SetDownCmdState; + break; + + //按列设置下发命令 + case FecCommSyncSysTick00 ://0 同步系统节拍 + fMsgTX00_SysSyncTick(CommPrm.CuuerntAddr); + CommPrm.State = FecCommSyncSysTick00Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommSyncSysTick00Ack : + DownCmdAckHandle(); + break; + + case FecCommSysReset01 ://1 系统复位 + fMsgTX01_SysReset(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + CommPrm.State = FecCommSysReset01Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommSysReset01Ack : + DownCmdAckHandle(); + break; + + case FecCommSysMute02 ://2 系统消音 + fMsgTX02_SysMute(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + CommPrm.State = FecCommSysMute02Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommSysMute02Ack : + DownCmdAckHandle(); + break; + + case FecCommSysSlefCheck03 ://3 系统自检 + fMsgTX03_SysSelfCheck(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + CommPrm.State = FecCommSysSlefCheck03Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommSysSlefCheck03Ack : + DownCmdAckHandle(); + break; + + case FecCommSyncTime04 :// 设置时间 + getSysTime(); + fMsgTX04_SyncTime(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, \ + dateTime.Year, \ + dateTime.Mon, \ + dateTime.Day, \ + dateTime.Hour, \ + dateTime.Min, \ + dateTime.Sec); + CommPrm.State = FecCommSyncTime04Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommSyncTime04Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceState34 ://34 查设备状态 + if(1 == CommPrm.SetDownPath.PathLevel){ + fMsgTX34_QueryDeviceState(CommPrm.CuuerntAddr); + }else + if(2 == CommPrm.SetDownPath.PathLevel){ + fMsgTX34_QueryDeviceState(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + }else + if(3 == CommPrm.SetDownPath.PathLevel){ + fMsgTX34_QueryDeviceState(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum); + }else{ + fMsgTX34_QueryDeviceState(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum, CommPrm.SetDownPath.DevNum); + } + CommPrm.State = FecCommQueryDeviceState34Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceState34Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceConfig35 ://35 查设备配置 + if(1 == CommPrm.SetDownPath.PathLevel){ + fMsgTX35_QueryDeviceConfig(CommPrm.CuuerntAddr); + }else + if(2 == CommPrm.SetDownPath.PathLevel){ + fMsgTX35_QueryDeviceConfig(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + }else + if(3 == CommPrm.SetDownPath.PathLevel){ + fMsgTX35_QueryDeviceConfig(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum); + }else{ + fMsgTX35_QueryDeviceConfig(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum, CommPrm.SetDownPath.DevNum); + } + CommPrm.State = FecCommQueryDeviceConfig35Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceConfig35Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceIdf36 ://36 查设备标识 + if(1 == CommPrm.SetDownPath.PathLevel){ + fMsgTX36_QueryDeviceIdf(CommPrm.CuuerntAddr); + }else + if(2 == CommPrm.SetDownPath.PathLevel){ + fMsgTX36_QueryDeviceIdf(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + }else + if(3 == CommPrm.SetDownPath.PathLevel){ + fMsgTX36_QueryDeviceIdf(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum); + }else{ + fMsgTX36_QueryDeviceIdf(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum, CommPrm.SetDownPath.DevNum); + } + CommPrm.State = FecCommQueryDeviceIdf36Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceIdf36Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceParameter37 ://37 查设备参量 + CommPrm.SetCmd37Path.CtlNum = CommPrm.SetDownPath.CtlNum & 0xFF; + CommPrm.SetCmd37Path.UnitNum = CommPrm.SetDownPath.UnitNum & 0xFF; + CommPrm.SetCmd37Path.DevNum = CommPrm.SetDownPath.DevNum & 0xFF; + CommPrm.SetCmd37Path.ChannelNum = CommPrm.SetDownPath.ChannelNum & 0xFF; + fMsgTX37_QueryDeviceParameter(CommPrm.CuuerntAddr, &CommPrm.SetCmd37Path); + CommPrm.State = FecCommQueryDeviceParameter37Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceParameter37Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceDescp38 ://38 查设备注释 + fMsgTX38_QueryDeviceDescp(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum, CommPrm.SetDownPath.DevNum); + CommPrm.State = FecCommQueryDeviceDescp38Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceDescp38Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceProgram39 ://39 查设备编程 + fMsgTX39_QueryDeviceProgram(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum, CommPrm.SetDownPath.DevNum); + CommPrm.State = FecCommQueryDeviceProgram39Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceProgram39Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceRegisterInfo40 ://40 查注册登记信息 + if(3 == CommPrm.SetDownPath.PathLevel){ + fMsgTX40_QueryDeviceRegisterInfo(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum); + }else{ + fMsgTX40_QueryDeviceRegisterInfo(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum, CommPrm.SetDownPath.DevNum); + } + CommPrm.State = FecCommQueryDeviceRegisterInfo40Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceRegisterInfo40Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryCurrentEvent41 :// 查询当前事件 + fMsgTX41_QueryCurrentEvent(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.Event); + ClearCurrentEventList(CommPrm.CuuerntAddr); + CommPrm.State = FecCommQueryCurrentEvent41Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryCurrentEvent41Ack : + //43 停止查询设备事件 + if(1 == CommPrm.AckStatus){ + if((CommPrm.SetDownCmdFlag)&&(FecCommStopQueryDeviceEvent43 == CommPrm.SetDownCmdState)&&(CommPrm.SetDownPath.Addr == CommPrm.CuuerntAddr)){ + CommPrm.SetDownCmdFlag = 0; + CommPrm.State = CommPrm.SetDownCmdState; + }else + if(1 == EventCodePrm[CommPrm.CurrentEventData.Data.EventCode]){ + fMsgRpy18_Ack_InformedGeneralEvent(CommPrm.CuuerntAddr); + }else + if(2 == EventCodePrm[CommPrm.CurrentEventData.Data.EventCode]){ + fMsgRpy17_Ack_PublishEmergencyEvent(CommPrm.CuuerntAddr); + } + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + }else + if(2 == CommPrm.AckStatus){ + CommPrm.State = FecCommQueryCurrentEvent41Ending; + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + + case FecCommQueryCurrentEvent41Ending : + CommPrm.State = FecCommExit; + break; + + case FecCommQueryHistoryEvent42 ://42 查设备历史事件 + fMsgTX42_QueryHistoryEvent(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.Event, \ + CommPrm.SetDownPath.SYear, CommPrm.SetDownPath.SMon, CommPrm.SetDownPath.SDay); + ClearHistoryEventList(); + CommPrm.State = FecCommQueryHistoryEvent42Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryHistoryEvent42Ack : + //43 停止查询设备事件 + if(1 == CommPrm.AckStatus){ + if((CommPrm.SetDownCmdFlag)&&(FecCommStopQueryDeviceEvent43 == CommPrm.SetDownCmdState)&&(CommPrm.SetDownPath.Addr == CommPrm.CuuerntAddr)){ + CommPrm.SetDownCmdFlag = 0; + CommPrm.State = CommPrm.SetDownCmdState; + }else + if(1 == EventCodePrm[CommPrm.CurrentEventData.Data.EventCode]){ + fMsgRpy18_Ack_InformedGeneralEvent(CommPrm.CuuerntAddr); + }else + if(2 == EventCodePrm[CommPrm.CurrentEventData.Data.EventCode]){ + fMsgRpy17_Ack_PublishEmergencyEvent(CommPrm.CuuerntAddr); + } + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + }else + if(2 == CommPrm.AckStatus){ + CommPrm.State = FecCommQueryHistoryEvent42Ending; + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + CommPrm.State = FecCommExit; + } + break; + + case FecCommQueryHistoryEvent42Ending : + CommPrm.State = FecCommExit; + break; + + case FecCommStopQueryDeviceEvent43 ://43 停止查询设备事件 + fMsgTX43_StopQueryDeviceEvent(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + CommPrm.State = FecCommStopQueryDeviceEvent43Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommStopQueryDeviceEvent43Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryVer44 :// 44 查询版本 + fMsgTX44_QueryFECBusVer(CommPrm.CuuerntAddr); + CommPrm.State = FecCommQueryVer44Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryVer44Ack : + DownCmdAckHandle(); + break; + + case FecCommQueryDeviceList45 ://45 查设备列表 + if(1 == CommPrm.SetDownPath.PathLevel){ + fMsgTX45_QueryDeviceList(CommPrm.CuuerntAddr); + }else + if(2 == CommPrm.SetDownPath.PathLevel){ + fMsgTX45_QueryDeviceList(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum); + }else + if(3 == CommPrm.SetDownPath.PathLevel){ + fMsgTX45_QueryDeviceList(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum); + }else{ + fMsgTX45_QueryDeviceList(CommPrm.CuuerntAddr, CommPrm.SetDownPath.CtlNum, CommPrm.SetDownPath.UnitNum, CommPrm.SetDownPath.DevNum); + } + CommPrm.State = FecCommQueryDeviceList45Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommQueryDeviceList45Ack : + DownCmdAckHandle(); + break; + + default : + CommPrm.Phase = FecPolling; + CommPrm.State = FecCommExit; + break; + } +} + +//按地址巡检，下面有事件就上传 +void TFecBus::SendPollingTask(void) +{ + switch(CommPrm.State){ + case FecCommExit : + if((CommPrm.CuuerntAddr < 63)&&(CommPrm.CuuerntAddr > 1)){ + CommPrm.CuuerntAddr++; + }else + if(63 == CommPrm.CuuerntAddr){ + CommPrm.CuuerntAddr = 2; + } + CommPrm.Phase = FecPolling; + CommPrm.State = FecCommPolling33; + break; + + case FecCommPolling33 : + fMsgTX33_InspectionDevice(CommPrm.CuuerntAddr);//发33 + CommPrm.State = FecCommPolling33Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + break; + + case FecCommPolling33Ack : //等待回复 + if(1 == CommPrm.AckStatus){ + if((CommPrm.SetDownCmdFlag)||(CommPrm.SetDownEventFlag)){ + if(CommPrm.CuuerntAddr != CommPrm.SetDownPath.Addr){ + CommPrm.CuuerntAddr = CommPrm.SetDownPath.Addr; + fMsgTX33_InspectionDevice(CommPrm.CuuerntAddr);//发33 + CommPrm.State = FecCommPolling33Ack; + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + }else{ + if(CommPrm.SetDownCmdFlag){ + CommPrm.SetDownCmdFlag = 0; + CommPrm.Phase = FecDownCmd; + CommPrm.CuuerntAddr = CommPrm.SetDownPath.Addr; + }else + if(CommPrm.SetDownEventFlag){ + CommPrm.SetDownEventFlag = 0; + CommPrm.Phase = FecDownEvent; + CommPrm.CuuerntAddr = CommPrm.SetDownPath.Addr; + } + } + }else{ + CommPrm.State = FecCommExit; + } + }else + if(2 == CommPrm.AckStatus){//建立连接，重新配置 + CommPrm.Phase = FecSetUpComm; + CommPrm.State = FecCommSyncTime04; + }else + if(3 == CommPrm.AckStatus){//子系统有事件上传，上传完一个，再跳到巡检，知道上传完为止 + if(1 == EventCodePrm[CommPrm.UpEventData.Data.EventCode]){ + fMsgRpy18_Ack_InformedGeneralEvent(CommPrm.CuuerntAddr); + CommPrm.NoAckTick = 3;//delay 30ms + }else + if(2 == EventCodePrm[CommPrm.UpEventData.Data.EventCode]){ + fMsgRpy17_Ack_PublishEmergencyEvent(CommPrm.CuuerntAddr); + CommPrm.NoAckTick = 3;//delay 30ms + } + CommPrm.State = FecCommDelay; + }else + if(CommPrm.TimeoutTick > CommAckTimeout){ + CommPrm.TimeoutTick = 0; + if(GetRegisterStatus(CommPrm.CuuerntAddr))SetLogout(CommPrm.CuuerntAddr); + + if((CommPrm.SetDownCmdFlag)||(CommPrm.SetDownEventFlag)){ + if(CommPrm.CuuerntAddr != CommPrm.SetDownPath.Addr){ + CommPrm.CuuerntAddr = CommPrm.SetDownPath.Addr; + fMsgTX33_InspectionDevice(CommPrm.CuuerntAddr);//发33 + CommPrm.AckStatus = 0; + CommPrm.TimeoutTick = 0; + }else{ + if(CommPrm.SetDownCmdFlag){ + CommPrm.SetDownCmdFlag = 0; + } + if(CommPrm.SetDownEventFlag){ + CommPrm.SetDownEventFlag = 0; + } + CommPrm.State = FecCommExit; + } + }else{ + CommPrm.State = FecCommExit; + } + } + + if(CommPrm.AckStatus){ + if(!GetRegisterStatus(CommPrm.CuuerntAddr)){ + SetRegister(CommPrm.CuuerntAddr); + } + } + break; + + case FecCommDelay ://延时等待发送完 + if(0 == CommPrm.NoAckTick)CommPrm.State = FecCommPolling33; + break; + + default : + CommPrm.CuuerntAddr = 2; + CommPrm.State = FecCommPolling33; + break; + } +} + +void TFecBus::OperationTask(void) +{ + static unsigned char Ord = 0; + + if(RxHandleFlag){ + RxHandleFlag = 0; + uDataRXTask(); + } + + switch(CommPrm.Phase){ + case FecNotConnected: //0 没有连接 + CommPrm.CuuerntAddr = 2; + CommPrm.Phase = FecPolling; + CommPrm.State = FecCommPolling33; + break; + + case FecSetUpComm: //1 建立连接 + SetUpCommTask(); + break; + + case FecPolling: //2 巡检 + SendPollingTask(); + break; + + case FecDownEvent: //3 下发事件 + DownEventTask(); + break; + + case FecDownCmd: //4 设置命令 + DownCmdTask(); + break; + + default : + CommPrm.Phase = FecNotConnected; + break; + } + + DebugProcess(); +} + +void TFecBus::DebugProcess(void) +{ + static TFecCmdPath aSetCmdPath; + static TFecEventBufBody aSetEvent; + u16 aEvent; + + if(SetDebug.Flag){ + SetDebug.Flag = 0; + + switch(SetDebug.Prm.Body.Cmd){ + case FecFunSyncSysTick ://0 同步系统节拍 + case FecFunSysReset ://1 系统复位 + case FecFunSysMute ://2 系统消音 + case FecFunSysSlefCheck ://3 系统自检 + case FecFunSyncTime ://4 广播时钟 + case FecFunInspectionDevice ://33 设备巡检 + case FecFunQueryDeviceState ://34 查设备状态 + case FecFunQueryDeviceConfig ://35 查设备配置 + case FecFunQueryDeviceIdf ://36 查设备标识 + case FecFunQueryDeviceParameter ://37 查设备参量 + case FecFunQueryDeviceDescp ://38 查设备注释 + case FecFunQueryDeviceProgram ://39 查设备编程 + case FecFunQueryDeviceRegisterInfo ://40 查注册登记信息 + case FecQueryCurrentEvent ://41 查设备当前事件 + case FecQueryHistoryEvent ://42 查设备历史事件 + case FecStopQueryDeviceEvent ://43 停止查询设备事件 + case FecQueryFECBusVer ://44 查FECBus协议版本号 + case FecQueryDeviceList ://45 查设备列表 + aSetCmdPath.Addr = SetDebug.Prm.Body.DesAddr; + aSetCmdPath.CtlNum = SetDebug.Prm.Body.Data[0]; + aSetCmdPath.UnitNum = SetDebug.Prm.Body.Data[1]; + aSetCmdPath.DevNum = SetDebug.Prm.Body.Data[2]; + aSetCmdPath.ChannelNum = SetDebug.Prm.Body.Data[3]; + aSetCmdPath.PathLevel = SetDebug.Prm.Body.Data[4]; + aSetCmdPath.SYear = SetDebug.Prm.Body.Data[5]; + aSetCmdPath.SMon = SetDebug.Prm.Body.Data[6]; + aSetCmdPath.SDay = SetDebug.Prm.Body.Data[7]; + aEvent = SetDebug.Prm.Body.Data[8]; + aEvent<<=8; + aEvent |= SetDebug.Prm.Body.Data[9]; + aSetCmdPath.Event = (TFecEventCode)aEvent; + EnterSetDownCmd((TFecFunctionCode)SetDebug.Prm.Body.Cmd, &aSetCmdPath); + break; + + case FecFunPublishEmergencyEvent ://5 通告紧急事件 + case FecFunPublishGeneralEvent ://6 通告一般事件 + case FecFunPublishAdjustEvent ://7 通告调试事件 + ClearDownEventList(); + + aSetEvent.Data.CtlNum = 6;//控制器编号（1字节） + aSetEvent.Data.UnitNum = 6;//单元编号（1字节） + aSetEvent.Data.DeviceNum = 6; //设备编号（1字节） + aSetEvent.Data.ChannelNum = 1; //通道编号（1字节） + aSetEvent.Data.DeviceCode = ftFireSmokeDetecter; //设备类型代码（2字节） + aSetEvent.Data.EventCode = evElevatorLanding; //事件代码（2字节） + aSetEvent.Data.StateCode.D16 = 6; //状态代码（2字节） + aSetEvent.Data.Year = 24;//年（1字节） + aSetEvent.Data.Mon = 6;//月（1字节） + aSetEvent.Data.Day = 6;//日（1字节） + aSetEvent.Data.Hour = 6;//时（1字节） + aSetEvent.Data.Min = 6;//分（1字节） + aSetEvent.Data.Sec = 6;//秒（1字节） + AddDownEventList(&aSetEvent); + + aSetEvent.Data.CtlNum = 5;//控制器编号（1字节） + aSetEvent.Data.UnitNum = 5;//单元编号（1字节） + aSetEvent.Data.DeviceNum = 5; //设备编号（1字节） + aSetEvent.Data.ChannelNum = 1; //通道编号（1字节） + aSetEvent.Data.DeviceCode = ftDisplayPad; //设备类型代码（2字节） + aSetEvent.Data.EventCode = evFireAlarmElectrical; //事件代码（2字节） + aSetEvent.Data.StateCode.D16 = 6; //状态代码（2字节） + aSetEvent.Data.Year = 24;//年（1字节） + aSetEvent.Data.Mon = 5;//月（1字节） + aSetEvent.Data.Day = 5;//日（1字节） + aSetEvent.Data.Hour = 5;//时（1字节） + aSetEvent.Data.Min = 5;//分（1字节） + aSetEvent.Data.Sec = 5;//秒（1字节） + AddDownEventList(&aSetEvent); + + EnterSetDownEvent(SetDebug.Prm.Body.DesAddr); + break; + + default : + break; + } + } +} + +void TFecBus::TriggerCmd01SysReset(void) +{ + SetDebug.Flag = 1; + SetDebug.Prm.Body.DesAddr = 6; + SetDebug.Prm.Body.Cmd = FecFunSysReset; + SetDebug.Prm.Body.Data[0] = 0;//CtlNum +} + +void TFecBus::TriggerCmd02SysMute(void) +{ + SetDebug.Flag = 1; + SetDebug.Prm.Body.DesAddr = 6; + SetDebug.Prm.Body.Cmd = FecFunSysMute; + SetDebug.Prm.Body.Data[0] = 0;//CtlNum +} + +void TFecBus::TrigerCmd03SysSlefCheck(void) +{ + SetDebug.Flag = 1; + SetDebug.Prm.Body.DesAddr = 6; + SetDebug.Prm.Body.Cmd = FecFunSysSlefCheck; + SetDebug.Prm.Body.Data[0] = 0;//CtlNum +} + +void TFecBus::TriggerCmd04SyncTime(void) +{ + SetDebug.Flag = 1; + SetDebug.Prm.Body.DesAddr = 6; + SetDebug.Prm.Body.Cmd = FecFunSyncTime; + SetDebug.Prm.Body.Data[0] = 0;//CtlNum +} + +//void EnterSetDownCmd(TFecFunctionCode aCmd, TFecCmdPath * aCmdPath); +//void EnterSetDownEvent(u8 aAddr); + + + + + + + + + + diff --git a/MyCode/src/ProtoFecBus.h b/MyCode/src/ProtoFecBus.h new file mode 100644 index 0000000..0bd55f7 --- /dev/null +++ b/MyCode/src/ProtoFecBus.h @@ -0,0 +1,1543 @@ +#ifndef PROTOFECBUS_H_ +#define PROTOFECBUS_H_ + +#include "gType.h" +#include "TDateTime.h" + +#define FecPublishEventRxBufCount 16 +#define FecRecentUsingCount 16 + +#define dFEC_MSG_RECORD_LEN 17 + +typedef enum{ + ftRsv = 0,//0 预留 + ftMainCtl = 1,//1 控制器/具有联动控制功能的控制器 + ftMainCtlFireLinkkage,//2 消防联动控制器 + ftGraphShow,//3 消防控制室图形显示装置 + + ftRsv4, ftRsv5, ftRsv6, ftRsv7, ftRsv8, ftRsv9, // 4 ~ 9 预留 + + ftDisplayPad,//10 火灾显示盘 + ftDetecteCircuit, //11 探测回路 + ftCtlCircuit, //12 控制回路 + ftCircuit, //13 探测与控制复合回路 + ftMainPower, //14 主电源 + ftStandbyPower, //15 备用电源 + ftBatChargeCircuit, //16 充电电路 + ftAlramVaCircuit, //17 声光警报回路 + ftDataMemCard, //18 运行数据存储单元 + + ftRsv19, //19 预留 + + ftFireDetecter,//20 火灾探测 + ftFireSmokeDetecter,//21 感烟火灾探测器 + ftPointIonSmokeDetecter,//22 点型离子感烟火灾探测器 + ftPointLightSmokeDetecter,//23 点型光电感烟火灾探测器 + ftLineLightSmokeDetecter,//24 线型光束感烟火灾探测器 + ftAirBreathingSmokeDetecter,//25 吸气式感烟火灾探测器 + + ftRsv26, ftRsv27, ftRsv28, ftRsv29, // 26 ~ 29 预留 + + ftTempDetecter,//30 感温火灾探测器 + ftPointTempDetecter,//31 点型感温火灾探测器 + ftLineTempDetecter,//32 线型感温火灾探测器 + + ftCableLineFireDetecter,//33 缆式线型火灾探测器 + ftAirTubeLineFireDetecter,//34 空气管式线型火灾探测器 + ftLineOpticalTempDetecter,//35 线型光纤感温火灾探测器 + + ftRsv36, ftRsv37, ftRsv38, ftRsv39, // 36 ~ 39 预留 + + ftFlameDetector,//40 火焰探测器 + ftPointIrFlameDetector,//41 点型红外火焰探测器 + ftPointUvFlameDetector,//42 点型紫外火焰探测器 + ftPointCompoundIrUvFlameDetector,//43 点型复合式红外紫外火焰探测器 + + ftRsv44, ftRsv45, ftRsv46, ftRsv47, ftRsv48, ftRsv49, // 44 ~ 49 预留 + + ftMultiSensorCompositeDetector,//50 多传感复合探测器 + ftLightSensitiveFireDetecter,//51 感光火灾探测器 + ftPhotoFireDetecter,//52 图像型火灾探测器 + ftPointCoFireDetecter,//53 点型一氧化碳火灾探测器 + + ftRsv54, ftRsv55, ftRsv56, ftRsv57, ftRsv58, ftRsv59, ftRsv60, //54~60 预留 + + ftManualFireAlarmButton,//61 手动火灾报警按钮 + ftFireHydrantButton,//62 消火栓按钮 + ftEmergencyStartButton,//63 紧急启动按钮 + ftEmergencyStopButton,//64 紧急停止按钮 + ftRsv65, ftRsv66, ftRsv67, ftRsv68, ftRsv69, ftRsv70, //65~70 预留 + + ftMoudle,//71 模块 + ftInputMoudle,//72 输入模块 + ftOutputMoudle,//73 输出模块 + ftInOutMoudle,//74 输入/输出模块 + ftRepeaterMoudle,//75 中继模块 + ftShortCircuitIsolator,//76 短路隔离器 + + ftRsv77, ftRsv78, ftRsv79, ftRsv80, //77~80 预留 + + ftFireAlarmDevice,//81 火灾警报装置 + ftSoundLightFireAlarm,//82 火灾声光警报器 + ftSoundFireAlarm,//83 火灾声警报器 + ftLightFireAlarm,//84 火灾光警报器 + ftGasReleaseAlarm,//85 气体释放警报器 + ftAlarmBell,//86 警铃 + + ftRsv87, ftRsv88, ftRsv89, ftRsv90, + ftRsv91, ftRsv92, ftRsv93, ftRsv94, ftRsv95, ftRsv96, ftRsv97, ftRsv98, ftRsv99, //87~99 预留 + + ftCombustibleGasAlarmController,//100 可燃气体报警控制器 + ftCombustibleGasDetecter,//101 可燃气体探测器 + ftPointCombustibleGasDetecter,//102 点型可燃气体探测器 + ftLineCombustibleGasDetecter,//103 线型可燃气体探测器 + + ftRsv104, ftRsv105, ftRsv106, ftRsv107, ftRsv108, ftRsv109, //104~109 预留 + + ftElecFireMonitor,//110 电气火灾监控设备 + ftElecFireMonitoringDetector,//111 电气火灾监控探测器 + ftResidualCurrentElecFireMonitoringDetector,//112 剩余电流式电气火灾监控探测器 + ftTempMeasuringElecFireMonitoringDetector,//113 测温式电气火灾监控探测器 + ftFaultArcDetectionDevice,//114 故障电弧探测装置 + + ftRsv115, ftRsv116, ftRsv117, ftRsv118, ftRsv119, //115~119 预留 + + ftEmergencyLightingController,//120 应急照明控制器 + ftFireEmergencySignLamp,//121 消防应急标志灯具 + ftFireEmergencyLightingLamp,//122 消防应急照明灯具 + ftFireEmergencyLampPower,//123 消防应急灯具专用应急电源 + ftEmergencyLightingDistributionDevice,//124 应急照明分配电装置 + + ftRsv125, ftRsv126, ftRsv127, ftRsv128, ftRsv129, //125~129 预留 + + ftFireDoorMonitor,//130 防火门监控器 + ftNormalCloseFireDoor,//131 常闭防火门 + ftNormalOpenFireDoor,//132 常开防火门 + ftFireDoorElectricCloser,//133 防火门电动闭门器 + ftFireDoorElectromagneticRelease,//134 防火门电磁释放器 + ftFireDoorMagneticSwitch,//135 防火门门磁开关 + + ftRsv136, ftRsv137, ftRsv138, ftRsv139, //136~139 预留 + + ftFireEquipmentPowerMonitor,//140 消防设备电源监控器 + ftFireEquipmentPowerVoltageSensor,//141 消防设备电源电压信号传感器 + ftFireEquipmentPowerCurrentSensor,//142 消防设备电源电流信号传感器 + ftFireEquipmentPowerVoltageCurrentSensor,//143 消防设备电源电压/电流信号传感器 + + ftRsv144, ftRsv145, ftRsv146, ftRsv147, ftRsv148, ftRsv149, //144~149 预留 + + ftGasFireControler,//150 气体灭火控制器 + ftFoamExtinguishingSystem,//151 泡沫灭火系统 + ftPowderExtinguishingSystem,//152 干粉灭火系统 + ftSmokePreventionExhaustSystem,//153 防烟排烟系统 + ftFireShutterContorler,//154 防火卷帘控制器 + ftCeilingScreenControler,//155 挡烟垂壁控制装置 + ftFireEmergencyBroadcastSystem,//156 消防应急广播系统 + ftFireTelephoneHost,//157 消防电话主机 + ftFireEmergencyPower,//158 消防设备应急电源 + ftTransmissionDevice,//159 传输设备 + ftHomeFireSystemControlCenterMonitor,//160 家用火灾安全系统控制中心监控设备 + ftFireWaterLevelMonitor,//161 消防水位监视器 + ftFireLift,//162 消防电梯 + ftFireElectricalControler,//163 消防电气控制装置 + + ftRsv164, ftRsv165, ftRsv166, ftRsv167, ftRsv168, ftRsv169, ftRsv170, + ftRsv171, ftRsv172, ftRsv173, ftRsv174, ftRsv175, ftRsv176, ftRsv177, ftRsv178, //164~178 预留 + + ftFirePumpController,//179 消防泵控制器 + ftFireHydrantPump,//180 消防栓泵 + ftWaterSprayPump,//181 水喷雾泵 + ftWaterMistPump,//182 细水雾泵 + ftStabilizedPressurePump,//183 稳压泵 + ftSprinklerPump,//184 喷淋泵 + ftDelugePump,//185 雨淋泵 + ftFoamConcentratePump,//186 泡沫液泵 + ftWaterFlowIndicator,//187 水流指示器 + ftAlarmValve,//188 报警阀 + ftPressureSwitch,//189 压力开关 + ftFlowSwitch,//190 流量开关 + ftValveActuator,//191 阀驱动装置 + ftElectricFireValve,//192 电动防火阀 + ftFireDamper70deg,//193 70℃防火阀 + ftFireDamper280deg,//194 280℃防火阀 + ftVentilatingAirConditioning,//195 通风空调 + ftPipeNetworkElectromagneticValve,//196 管网电磁阀 + ftSmokePreventionExhaustFan,//197 防烟排烟风机 + ftElectricExhaustFireDamper,//198 电动排烟防火阀 + ftNormalCloseAirSupplyOutlet,//199 常闭送风口 + ftSmokeOutlet,//200 排烟口 + ftFireWaterMonitor,//201 消防水炮 + ftElectricDoor,//202 电动门 + ftSmokeVentilator,//203 排烟机 + ftForcedDraughtBlower,//204 送风机 + ftElectromagneticValve,//205 电磁阀 + ftLightDistribution,//206 照明配电 + ftPowerDistribution,//207 动力配电 + ftAirCompressor,//208 空压机 + ftValve,//209 阀门 + ftDistributionBox,//210 配电箱 + + ftRsv211, ftRsv212, ftRsv213, ftRsv214, ftRsv215, ftRsv216, ftRsv217, ftRsv218, ftRsv219, ftRsv220, //211~220 预留 + + //211~251 User Define + ftMethaneDetector, // 221 + ftPropaneDetector, // 222 + ftMethaneCODetector, // 223 + ftH2SDetector, // 224 + ftSmokeHeatDetector, // 225 + ftSmokeCODetector, // 226 + ftBuzzerBase, // 227 + ftSingleDoorInputModule, // 228 + ftDoubleDoorInputModule, // 229 + ftActiveIOModule, // 230 + ftBroadcastModule, // 231 + ftCodedTelephoneModule, // 232 + ftTheftDetectorInterface, // 233 + ftIndustrialModule, // 234 + ftDoorLight, // 235 + ftExplosionProofBox, // 236 + ftHeatCableProcessor, // 237 + ftHeatAlarm, // 238 + ftHeatLeakageAlarm, // 239 + ft3PhasePowerMonitor, // 240 + ft2PhasePowerMonitor, // 241 + ftPressureController, // 242 + ftPressureDetector, // 243 + ftSignalValve, // 244 + ftLinkagePower, // 245 + ftManualAutoIndicator, // 246 + ftEmergencyStartStop, // 247 + ftDirCtlPanel, // 248 多线盘 + ftBusCtlPanel, // 249 总线盘 + ftGasExtinguishPanel, // 250 + ftCanNetworkComm, // 251 联网接口卡 + + ftRsv252, ftRsv253, ftRsv254, ftRsv255, ftRsv256, //252~256 预留 + //256~65534 User Define + ftUndefineFecDevType = 300,//300 未知设备类型 + + ftConnectMutiDevice = 65535,//65535 连接了多种设备 + +}TFecDevTypeCode; + +typedef enum { + evtRsv0 = 0, //0 预留 预留 + evNormal = 1, //1 正常 一般事件 + evFirstFireAlarm , //2 首火警 紧急事件 + evFireAlarm, //3 火警 紧急事件 + evFireAlarmElectrical, //4 电气火灾报警 紧急事件 + evGasLowThreshold, //5 可燃气体低限报警 紧急事件 + + evGasHiThreshold, //6 可燃气体高限报警 紧急事件 + evGasExcess, //7 可燃气体超量程报警 紧急事件 + evFireAlarmPreWarning, //8 电气火灾预警 紧急事件 + evFaultOrFireAlarmExactly, //9 确认故障信息、火灾报警信息 紧急事件 + evFaultOrFireAlarmRevoke, //10 火警撤销 紧急事件 + evFireAlarmElectricalRevoke, //11 电气火灾报警撤销 紧急事件 + evGasLowThresholdRevoke, //12 1可燃气体低限报警撤销 紧急事件 + evGasHiThresholdRevoke, //13 可燃气体高限报警撤销 紧急事件 + evGasExcessRevoke, //14 可燃气体超量程报警撤销 紧急事件 + evFireAlarmPreWarningRevoke, //15 电气火灾预警撤销 紧急事件 + + evRsv16, evRsv17, evRsv18, //16～18 预留 预留 + + evLaunch, //19 启动 紧急事件 + evLaunchAutomatic, //20 自动启动 紧急事件 + evLaunchManual, //21 手动启动 紧急事件 + evLaunchLiveEmergency, //22 现场急启 紧急事件 + evLaunchInrerLink, //23 联动启动 紧急事件 + evGasMisfireDelay, //24 气体灭火开始延时 紧急事件 + evGasSplash, //25 气体喷洒 紧急事件 + evFeedBack, //26 反馈 紧急事件 + evGasSplashFeedBack, //27 喷洒反馈 紧急事件 + evFeedBackRevoke, //28 反馈撤销 紧急事件 + evShutoff, //29 停止 紧急事件 + evShutoffLiveEmergency, //30 现场急停 紧急事件 + evHydrantLowPressure, //31 消火栓系统、自动喷淋系统水压低 一般事件 + + evRsv32, evRsv33, evRsv34, //32～39 预留 预留 + evRsv35, evRsv36, evRsv37, //32～39 预留 预留 + evRsv38, evRsv39, //32～39 预留 预留 + + evEmergency, //40 应急 紧急事件 + evMonthlyCheck, //41 月检 一般事件 + evYearlyCheck, //42 年检 一般事件 + evSigneLumSigneChanged, //43 标志灯具改变方向 一般事件 + + evElevatorLanding, //44 电梯迫降 紧急事件 + evRollerShutterHalfShut, //45 卷帘半降 紧急事件 + evRollerShutterShut, //46 卷帘全降 紧急事件 + evCall, //47 呼叫 紧急事件 + evTelephoneCommunications, //48 通话 紧急事件 + evDevPowerLost, //49 消防设备电源失电 紧急事件 + evDevPowerVoltageLow, //50 消防设备电源欠压 一般事件 + evDevPowerVoltageHi, //51 消防设备电源过压 一般事件 + evDevPowerOverLoad, //52 消防设备电源过载 一般事件 + evDevPowerPhaseLacking, //53 消防设备电源缺相 紧急事件 + evDevPowerPhaseStagger, //54 消防设备电源错相 紧急事件 + evCisternWaterLow, //55 消防水箱（池）水位低 一般事件 + evEmergencyElevator, //56 消防电梯停用 紧急事件 + + evRsv57,evRsv58,evRsv59, //57～69 预留 预留 + evRsv60,evRsv61,evRsv62, //57～69 预留 预留 + evRsv63,evRsv64,evRsv65, //57～69 预留 预留 + evRsv66,evRsv67,evRsv68, //57～69 预留 预留 + evRsv69, //57～69 预留 预留 + + evSuperVisory, //70 监管 紧急事件 + evSuperVisoryRelieve, //71 监管解除 紧急事件 + evMask, //72 屏蔽 一般事件 + evMaskRelieve, //73 屏蔽解除 一般事件 + + evRsv74, evRsv75, evRsv76, //74～79 预留 预留 + evRsv77, evRsv78, evRsv79, //74～79 预留 预留 + + evFault, //80 故障 一般事件 + evFaultCommunications, //81 通讯故障 一般事件 */ + evFaultMainPower, //82 主电故障 一般事件 + evFaultSparePower, //83 备电故障 一般事件 + evFaultCharge, //84 充电故障 一般事件 + evFaultLoopTank, //85 回路故障 紧急事件 + evFaultComponent, //86 部件故障 一般事件 + evFaultCircuit, //87 线路故障 一般事件 circuit + evFaultGrounding, //88 接地故障 一般事件 + evNormallyCloseDoorOpen, //89 常闭防火门打开 一般事件 + evNormallyOpenDoorClose, //90 常开防火门关闭 一般事件 + + evRsv91, evRsv92, evRsv93, //91～99 预留 预留 + evRsv94, evRsv95, evRsv96, //91～99 预留 预留 + evRsv97, evRsv98, evRsv99, //91～99 预留 预留 + + evFaultRecover, //100 故障恢复 一般事件 + evFaultCommunicationsRecover, //101 通讯故障恢复 一般事件 + evFaultMainPowerRecover, //102 主电故障恢复 一般事件 + evFaultSparePowerRecover, //103 备电故障恢复 一般事件 + evFaultChargeRecover, //104 充电故障恢复 一般事件 + evFaultLoopTankRecover, //105 回路故障恢复 一般事件 + evFaultComponentRecover, //106 部件故障恢复 一般事件 + evFaultCircuitRecover, //107 线路故障恢复 一般事件 + evFaultGroundingRecover, //108 接地故障恢复 一般事件 + evNormallyCloseDoorOpenRecover, //109 常闭防火门恢复关闭状态 一般事件 + evNormallyOpenDoorCloseRecover, //110 常开防火门恢复开门状态 一般事件 + + evRsv111, evRsv112, evRsv113, //111～119 预留 预留 + evRsv114, evRsv115, evRsv116, //111～119 预留 预留 + evRsv117, evRsv118, evRsv119, //111～119 预留 预留 + + evSystemPowerOn, //120 开机 一般事件 + evSystemPowerOff, //121 关机 一般事件 + evReset, //122 复位 紧急事件 + evSelfCheck, //123 自检 一般事件 + evSelfCheckFailure, //124 自检失败 一般事件 + evManual, //125 手动状态 紧急事件 + evAutomatic, //126 自动状态 紧急事件 + evMuteBell, //127 消音 一般事件 + evKeyPressMessageConfirm, //128 信息确认控制按钮动作 一般事件 + evKeyPressFunctionCheck, //129 检查功能按钮动作 一般事件 + evKeyPressInterLinkTurnOn, //130 联动启动按钮动作 紧急事件 + evAdjustClock, //131 调整时钟 一般事件 + + //132~255 Rsv + //256~65535 User Define + evUndefine = 65535, //未知事件 +}TFecEventCode; + +const u8 GBDeviceCodePrm[256] = { + //0 + 0, // 0 国标预留 + 1,// 1 + 1, // 2 + 1, // 3 + 0, // 4 国标预留 + 0, // 5 未使用 + 0, // 6 未使用 + 0, // 7 未使用 + 0, // 8 未使用 + 0, // 9 未使用 + 1, // 10 + 1, // 11 + 1, // 12 + 1, // 13 + 1, // 14 + 1, // 15 + 1, // 16 + 1, // 17 + 1, // 18 + 0, // 19 国标预留 + 1, // 20 + 1, // 21 + 1, // 22 + 1, // 23 + 1, // 24 + 1, // 25 + 0, // 26 国标预留 + 0, // 27 未使用 + 0, // 28 未使用 + 0, // 29 未使用 + 1, // 30 + 1, // 31 + 1, // 32 + 1, // 33 + 1, // 34 + 1, // 35 + 0, // 36 国标预留 + 0, // 37 未使用 + 0, // 38 未使用 + 0, // 39 未使用 + 1, // 40 + 1, // 41 + 1, // 42 + 1, // 43 + 0, // 44 国标预留 + 0, // 45 未使用 + 0, // 46 未使用 + 0, // 47 未使用 + 0, // 48 未使用 + 0, // 49 未使用 + 1, // 50 + 1, // 51 + 1, // 52 + 1, // 53 + 0, // 54 国标预留 + 0, // 55 未使用 + 0, // 56 未使用 + 0, // 57 未使用 + 0, // 58 未使用 + 0, // 59 未使用 + 0, // 60 未使用 + 1, // 61 + 1, // 62 + 1, // 63 + 1, // 64 + 0, // 65 国标预留 + 0, // 66 未使用 + 0, // 67 未使用 + 0, // 68 未使用 + 0, // 69 未使用 + 0, // 70 未使用 + 1, // 71 + 1, // 72 + 1, // 73 + 1, // 74 + 1, // 75 + 1, // 76 + 0, // 77 国标预留 + 0, // 78 未使用 + 0, // 79 未使用 + 0, // 80 未使用 + 1, // 81 + 1, // 82 + 1, // 83 + 1, // 84 + 1, // 85 + 1, // 86 + 0, // 87 国标预留 + 0, // 88 未使用 + 0, // 89 未使用 + 0, // 90 未使用 + 0, // 91 未使用 + 0, // 92 未使用 + 0, // 93 未使用 + 0, // 94 未使用 + 0, // 95 未使用 + 0, // 96 未使用 + 0, // 97 未使用 + 0, // 98 未使用 + 0, // 99 未使用 + 1, // 100 + 1, // 101 + 1, // 102 + 1, // 103 + 0, // 104 国标预留 + 0, // 105 未使用 + 0, // 106 未使用 + 0, // 107 未使用 + 0, // 108 未使用 + 0, // 109 未使用 + 1, // 110 + 1, // 111 + 1, // 112 + 1, // 113 + 1, // 114 + 0, // 115 国标预留 + 0, // 116 未使用 + 0, // 117 未使用 + 0, // 118 未使用 + 0, // 119 未使用 + 1, // 120 + 1, // 121 + 1, // 122 + 1, // 123 + 1, // 124 + 0, // 125 国标预留 + 0, // 126 未使用 + 0, // 127 未使用 + 0, // 128 未使用 + 0, // 129 未使用 + 1, // 130 + 1, // 131 + 1, // 132 + 1, // 133 + 1, // 134 + 1, // 135 + 0, // 136 国标预留 + 0, // 137 未使用 + 0, // 138 未使用 + 0, // 139 未使用 + 1, // 140 + 1, // 141 + 1, // 142 + 1,// 143 + 0, // 144 国标预留 + 0, // 145 未使用 + 0, // 146 未使用 + 0, // 147 未使用 + 0, // 148 未使用 + 0, // 149 未使用 + 1, // 150 + 1, // 151 + 1, // 152 + 1, // 153 + 1, // 154 + 1, // 155 + 1, // 156 + 1, // 157 + 1, // 158 + 1, // 159 + 1,// 160 + 1, // 161 + 1, // 162 + 1, // 163 + 0, // 164 国标预留 + 0, // 165 未使用 + 0, // 166 未使用 + 0, // 167 未使用 + 0, // 168 未使用 + 0, // 169 未使用 + 0, // 170 未使用 + 0, // 171 未使用 + 0, // 172 未使用 + 0, // 173 未使用 + 0, // 174 未使用 + 0, // 175 未使用 + 0, // 176 未使用 + 0, // 177 未使用 + 0, // 178 未使用 + 1, // 179 + 1, // 180 + 1, // 181 + 1, // 182 + 1, // 183 + 1, // 184 + 1, // 185 + 1, // 186 + 1, // 187 + 1, // 188 + 1, // 189 + 1, // 190 + 1, // 191 + 1, // 192 + 1, // 193 + 1, // 194 + 1, // 195 + 1, // 196 + 1, // 197 + 1, // 198 + 1, // 199 + 1, // 200 + 1, // 201 + 1, // 202 + 1, // 203 + 1, // 204 + 1, // 205 + 1, // 206 + 1, // 207 + 1, // 208 + 1, // 209 + 1, // 210 + 0, // 211 未使用 + 0, // 212 未使用 + 0, // 213 未使用 + 0, // 214 未使用 + 0, // 215 未使用 + 0, // 216 未使用 + 0, // 217 未使用 + 0, // 218 未使用 + 0, // 219 未使用 + 0, // 220 未使用 + 2, // 221 + 2, // 222 + 2, // 223 + 2, // 224 + 2, // 225 + 2, // 226 + 2, // 227 + 2, // 228 + 2, // 229 + 2, // 230 + 2, // 231 + 2, // 232 + 2, // 233 + 2, // 234 + 2, // 235 + 2, // 236 + 2, // 237 + 2, // 238 + 2, // 239 + 2, // 240 + 2, // 241 + 2, // 242 + 2, // 243 + 2, // 244 + 2, // 245 + 2, // 246 + 2, // 247 + 2, // 248 + 2, // 249 + 2, // 250 + 2, // 251 + 0, // 252 未使用 + 0, // 253 未使用 + 0, // 254 未使用 + 0, // 255 未使用 +}; + +const u8 EventCodePrm[256] = { + 0,//evtRsv0 = 0, //0 预留 预留 + 1,//evNormal = 1, //1 正常 一般事件 + 2,//evFirstFireAlarm , //2 首火警 紧急事件 + 2,//evFireAlarm, //3 火警 紧急事件 + 2,//evFireAlarmElectrical, //4 电气火灾报警 紧急事件 + 2,//evGasLowThreshold, //5 可燃气体低限报警 紧急事件 + + 2,//evGasHiThreshold, //6 可燃气体高限报警 紧急事件 + 2,//evGasExcess, //7 可燃气体超量程报警 紧急事件 + 2,//evFireAlarmPreWarning, //8 电气火灾预警 紧急事件 + 2,//evFaultOrFireAlarmExactly, //9 确认故障信息、火灾报警信息 紧急事件 + 2,//evFaultOrFireAlarmRevoke, //10 火警撤销 紧急事件 + 2,//evFireAlarmElectricalRevoke, //11 电气火灾报警撤销 紧急事件 + 2,//evGasLowThresholdRevoke, //12 1可燃气体低限报警撤销 紧急事件 + 2,//evGasHiThresholdRevoke, //13 可燃气体高限报警撤销 紧急事件 + 2,//evGasExcessRevoke, //14 可燃气体超量程报警撤销 紧急事件 + 2,//evFireAlarmPreWarningRevoke, //15 电气火灾预警撤销 紧急事件 + + 0,0,0,//evRsv16, evRsv17, evRsv18, //16～18 预留 预留 + + 2,//evLaunch, //19 启动 紧急事件 + 2,//evLaunchAutomatic, //20 自动启动 紧急事件 + 2,//evLaunchManual, //21 手动启动 紧急事件 + 2,//evLaunchLiveEmergency, //22 现场急启 紧急事件 + 2,//evLaunchInrerLink, //23 联动启动 紧急事件 + 2,//evGasMisfireDelay, //24 气体灭火开始延时 紧急事件 + 2,//evGasSplash, //25 气体喷洒 紧急事件 + 2,//evFeedBack, //26 反馈 紧急事件 + 2,//evGasSplashFeedBack, //27 喷洒反馈 紧急事件 + 2,//evFeedBackRevoke, //28 反馈撤销 紧急事件 + 2,//evShutoff, //29 停止 紧急事件 + 2,//evShutoffLiveEmergency, //30 现场急停 紧急事件 + 1,//evHydrantLowPressure, //31 消火栓系统、自动喷淋系统水压低 一般事件 + + 0,0,0,//evRsv32, evRsv33, evRsv34, //32～39 预留 预留 + 0,0,0,//evRsv35, evRsv36, evRsv37, //32～39 预留 预留 + 0,0,//evRsv38, evRsv39, //32～39 预留 预留 + + 2,//evEmergency, //40 应急 紧急事件 + 1,//evMonthlyCheck, //41 月检 一般事件 + 1,//evYearlyCheck, //42 年检 一般事件 + 1,//evSigneLumSigneChanged, //43 标志灯具改变方向 一般事件 + + 2,//evElevatorLanding, //44 电梯迫降 紧急事件 + 2,//evRollerShutterHalfShut, //45 卷帘半降 紧急事件 + 2,//evRollerShutterShut, //46 卷帘全降 紧急事件 + 2,//evCall, //47 呼叫 紧急事件 + 2,//evTelephoneCommunications, //48 通话 紧急事件 + 2,//evDevPowerLost, //49 消防设备电源失电 紧急事件 + 1,//evDevPowerVoltageLow, //50 消防设备电源欠压 一般事件 + 1,//evDevPowerVoltageHi, //51 消防设备电源过压 一般事件 + 1,//evDevPowerOverLoad, //52 消防设备电源过载 一般事件 + 2,//evDevPowerPhaseLacking, //53 消防设备电源缺相 紧急事件 + 2,//evDevPowerPhaseStagger, //54 消防设备电源错相 紧急事件 + 1,//evCisternWaterLow, //55 消防水箱（池）水位低 一般事件 + 2,//evEmergencyElevator, //56 消防电梯停用 紧急事件 + + 0,0,0,//evRsv57,evRsv58,evRsv59, //57～69 预留 预留 + 0,0,0,//evRsv60,evRsv61,evRsv62, //57～69 预留 预留 + 0,0,0,//evRsv63,evRsv64,evRsv65, //57～69 预留 预留 + 0,0,0,//evRsv66,evRsv67,evRsv68, //57～69 预留 预留 + 0,//evRsv69, //57～69 预留 预留 + + 2,//evSuperVisory, //70 监管 紧急事件 + 2,//evSuperVisoryRelieve, //71 监管解除 紧急事件 + 1,//evMask, //72 屏蔽 一般事件 + 1,//evMaskRelieve, //73 屏蔽解除 一般事件 + + 0,0,0,//evRsv74, evRsv75, evRsv76, //74～79 预留 预留 + 0,0,0,//evRsv77, evRsv78, evRsv79, //74～79 预留 预留 + + 1,//evFault, //80 故障 一般事件 + 1,//evFaultCommunications, //81 通讯故障 一般事件 */ + 1,//evFaultMainPower, //82 主电故障 一般事件 + 1,//evFaultSparePower, //83 备电故障 一般事件 + 1,//evFaultCharge, //84 充电故障 一般事件 + 2,//evFaultLoopTank, //85 回路故障 紧急事件 + 1,//evFaultComponent, //86 部件故障 一般事件 + 1,//evFaultCircuit, //87 线路故障 一般事件 circuit + 1,//evFaultGrounding, //88 接地故障 一般事件 + 1,//evNormallyCloseDoorOpen, //89 常闭防火门打开 一般事件 + 1,//evNormallyOpenDoorClose, //90 常开防火门关闭 一般事件 + + 0,0,0,//evRsv91, evRsv92, evRsv93, //91～99 预留 预留 + 0,0,0,//evRsv94, evRsv95, evRsv96, //91～99 预留 预留 + 0,0,0,//evRsv97, evRsv98, evRsv99, //91～99 预留 预留 + + 1,//evFaultRecover, //100 故障恢复 一般事件 + 1,//evFaultCommunicationsRecover, //101 通讯故障恢复 一般事件 + 1,//evFaultMainPowerRecover, //102 主电故障恢复 一般事件 + 1,//evFaultSparePowerRecover, //103 备电故障恢复 一般事件 + 1,//evFaultChargeRecover, //104 充电故障恢复 一般事件 + 1,//evFaultLoopTankRecover, //105 回路故障恢复 一般事件 + 1,//evFaultComponentRecover, //106 部件故障恢复 一般事件 + 1,//evFaultCircuitRecover, //107 线路故障恢复 一般事件 + 1,//evFaultGroundingRecover, //108 接地故障恢复 一般事件 + 1,//evNormallyCloseDoorOpenRecover, //109 常闭防火门恢复关闭状态 一般事件 + 1,//evNormallyOpenDoorCloseRecover, //110 常开防火门恢复开门状态 一般事件 + + 0,0,0,//evRsv111, evRsv112, evRsv113, //111～119 预留 预留 + 0,0,0,//evRsv114, evRsv115, evRsv116, //111～119 预留 预留 + 0,0,0,//evRsv117, evRsv118, evRsv119, //111～119 预留 预留 + + 1,//evSystemPowerOn, //120 开机 一般事件 + 1,//evSystemPowerOff, //121 关机 一般事件 + 2,//evReset, //122 复位 紧急事件 + 1,//evSelfCheck, //123 自检 一般事件 + 1,//evSelfCheckFailure, //124 自检失败 一般事件 + 2,//evManual, //125 手动状态 紧急事件 + 2,//evAutomatic, //126 自动状态 紧急事件 + 1,//evMuteBell, //127 消音 一般事件 + 1,//evKeyPressMessageConfirm, //128 信息确认控制按钮动作 一般事件 + 1,//evKeyPressFunctionCheck, //129 检查功能按钮动作 一般事件 + 2,//evKeyPressInterLinkTurnOn, //130 联动启动按钮动作 紧急事件 + 1,//evAdjustClock, //131 调整时钟 一般事件 + + //132~255 Rsv + //256~65535 User Define + 0,//evUndefine = 65535, //未知事件 +}; + +typedef union{ + u16 D16; + struct{ + u16 Bit0 :1; + u16 Bit1 :1; + u16 Bit2 :1; + u16 Bit3 :1; + u16 Bit4 :1; + u16 Bit5 :1; + u16 Bit6 :1; + u16 Bit7 :1; + + u16 Bit8 :1; + u16 Bit9 :1; + u16 Bit10 :1; + u16 Bit11 :1; + u16 Bit12 :1; + u16 Bit13 :1; + u16 Bit14 :1; + u16 Bit15 :1; + }BitF; + struct{ + u16 IsAutomatic :1; //0:Manual; 1:Automatic + u16 IsUsingStandByPower :1; //0:Using Main Power; 1:Using Standby Power + u16 IsPowerError :1; + u16 IsAlram :1; + u16 IsAction :1; + u16 IsFeedBack :1; + u16 IsSuperVisory :1; + u16 IsFault :1; + + u16 IsMask :1; + u16 IsGasSpay :1; + u16 IsEmergency :1; + u16 Rsv0 :1; + u16 Rsv1 :1; + u16 Rsv2 :1; + u16 Rsv3 :1; + u16 Rsv4 :1; + }BitFlag; +}TFecStateCode; + + +typedef struct{ + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 ChannelNum; +}TFecItemPath; + +typedef enum{ + UsingUart= 0, + UsingCan = 1 +}TFecBusType; + +typedef struct{ + u32 PollIndex; + struct{ + TDateTime fTime; + u8 Busy; + u8 Section; + u8 SectionCount; + u8 Rsv0; + }body[64]; + //the 0 is dump +}TFecMsgReference; + +typedef struct{ + u32 PollIndex; + struct{ + u32 PollIndex; + u16 List[FecRecentUsingCount]; + }Recent; + struct{ + u8 State; + u8 MsgRefIndex; + u8 SrcAddr; + u8 RecTimes; + TFecItemPath PathMutual; + TDateTime Dt; + u8 Body[20]; + }Items[FecPublishEventRxBufCount]; +}TFecPublishMsgRxList; + +//C.2 +typedef enum{ + FecFunSyncSysTick = 0,//0 同步系统节拍 + FecFunSysReset = 1,//1 系统复位 + FecFunSysMute,//2 系统消音 + FecFunSysSlefCheck,//3 系统自检 + FecFunSyncTime,//4 广播时钟 + FecFunPublishEmergencyEvent,//5 通告紧急事件 + FecFunPublishGeneralEvent,//6 通告一般事件 + FecFunPublishAdjustEvent,//7 通告调试事件 + + FecFunRsv08,FecFunRsv09,FecFunRsv10, + FecFunRsv11,FecFunRsv12,FecFunRsv13, + FecFunRsv14,//8-14 自定义 + + FecFunStateAck,//15 状态码应答，或结束帧标志 + FecFunRsv16,//16 保留 + + FecFunInformedEmergencyEvent,//17 通告紧急事件 + FecFunInformedGeneralEvent,//18 通告一般事件 + FecFunInformedAdjustEvent,//19 通告调试事件 + FecFunInformedHeartbeat,//20 通告心跳 + + FecFunRsv21,FecFunRsv22,FecFunRsv23,FecFunRsv24,FecFunRsv25, + FecFunRsv26,FecFunRsv27,FecFunRsv28,FecFunRsv29,FecFunRsv30,FecFunRsv31,//21-31 自定义 + FecFunRsv32,//32 保留 + + FecFunInspectionDevice,//33 设备巡检 + FecFunQueryDeviceState,//34 查设备状态 + FecFunQueryDeviceConfig,//35 查设备配置 + FecFunQueryDeviceIdf,//36 查设备标识 + FecFunQueryDeviceParameter,//37 查设备参量 + FecFunQueryDeviceDescp,//38 查设备注释 + FecFunQueryDeviceProgram,//39 查设备编程 + FecFunQueryDeviceRegisterInfo,//40 查注册登记信息 + FecQueryCurrentEvent,//41 查设备当前事件 + FecQueryHistoryEvent,//42 查设备历史事件 + FecStopQueryDeviceEvent,//43 停止查询设备事件 + FecQueryFECBusVer,//44 查FECBus协议版本号 + FecQueryDeviceList,//45 查设备列表 + + //--------------- 46-127 自定义 --------------- + FecFunRsv46,FecFunRsv47,FecFunRsv48,FecFunRsv49,FecFunRsv50, + FecFunRsv51,FecFunRsv52,FecFunRsv53,FecFunRsv54,FecFunRsv55, + FecFunRsv56,FecFunRsv57,FecFunRsv58,FecFunRsv59,FecFunRsv60, +}TFecFunctionCode; + +//C.4.2.5 +typedef enum{ + ackMsgSectionEnd = 0, + ackCrcError = 1, + ackInvalidRequst, + ackUnitFault, + ackSystemBusy, + ackUnknownCmd, + ackAddrNotExist, + ackParameterError, + ackInProcess, + ackEventOver, + ackRecDataCorrect, +}TFecAckCode; + +typedef enum{ + pmRsv0 = 0,//预留 + pmHeightIn10CM = 1, //高度 0.01m + pmTempeInTenth, //温度 0.1℃ + pmPressureInMpk,//压力 0.1MPa + pmPressureInKpk,//压力 0.1KPa + pmGasConsistence_ThousandthLEL,//气体浓度 0.1%LEL + pmGasConsistence_Volumel10N7P,//气体浓度 0.1X10(-6) (体积分数) + pmGasConsistence_Volume110N3P,//气体浓度 0.1% (体积分数) + pmGasConsistence_Volume110N3P2,//气体浓度 1000X10(-6) (体积分数) + pmGasConsistence_Volumel1MgM3P,//气体浓度 1mg/m3 + pmTimeOneSecond,//时间 1s + pmVoltageN1P,//电压 0.1V + pmCurrentN1P,//电流 0.1A + pmN1PLPerSecond,//流量 0.1L/s + pmVolumeFlow,//风量 0.1m3/min + pmAirSpeed,//风速 0.1m/s + pmRemainCurrent,//剩余电流 1mA + pmSmokePrm,//烟参量 + pmRsv18,//18-127 预留 + pmCustom0 = 128, //128-255 自定义 +}TParameterType; + +typedef struct{ + u8 Index; + enum{ + OrionalNone = 0, + OrionaReset = 1, + OrionalNotDone, + OrionalDone + }State; +}TMsgInInf; + +typedef union{ + u32 da32[258]; + u8 da8[1032]; + struct{ + u8 FrmType; + u8 DestAddr; + u8 Priority; + u8 SrcAddr; + u8 MsgIndex; + u8 FrmIndex; + u16 Dlen;//max 128*8 + u8 DPFC[128*8]; //Data PlusIn Function Code + }body; +}TFecBusData; + +typedef union{ + u32 D32[4]; + u8 D8[16]; + struct{ + u8 CtlNum ;//控制器编号（1字节） + u8 UnitNum ;//单元编号（1字节） + u8 DeviceNum ; //设备编号（1字节） + u8 ChannelNum ; //通道编号（1字节） + + u16 DeviceCode ; //设备类型代码（2字节）TFecDevTypeCode + u16 EventCode ; //事件代码（2字节）TFecEventCode + + TFecStateCode StateCode ; //状态代码（2字节） + u8 Year ;//年（1字节） + u8 Mon;//月（1字节） + + u8 Day;//日（1字节） + u8 Hour;//时（1字节） + u8 Min;//分（1字节） + u8 Sec;//秒（1字节） + }Data; +}TFecEventBufBody; + +typedef struct{ + u8 avalibel; + u8 UsingMsgIndex; + u8 FrameNum; + u8 FrameTick; + union{ + u8 D8[20]; + struct{ + u8 Header; + u8 FrmType; + u8 DestAddr; + u8 Priority; + u8 SrcAddr; + u8 MsgIndex; + u8 FrmIndex; + u8 Dlen; + u8 DPFC[8]; //Data PlusIn Function Code + u8 CrcLoByte; + u8 CrcHiByte; + u8 Eop; + u8 Rsv; + }body; + }Section[4]; +}TFecBusMsgUartTx; + +typedef struct{ + struct{ + u8 avalibel; + u8 UsingMsgIndex; + u8 Rsv0; + u8 Rsv1; + union{ + u32 D32[4]; + u8 D8[16]; + struct{ + u8 DPFC[8]; //Data PlusIn Function Code + u32 ExtendedId; + u32 Dlen; + }spl; + }body; + }Section[4]; +}TFecBusMsgCanTx; + +typedef struct{ + u8 avalibel; + u8 UsingMsgIndex; + u8 FrmCount; + u8 Rsv; + union{ + u8 D8[16]; + struct{ + u8 Header; + u8 FrmType; + u8 DestAddr; + u8 Priority; + u8 SrcAddr; + u8 MsgIndex; + u8 FrmIndex; + u8 Dlen; + u8 DPFC[8]; //Data PlusIn Function Code + }spl; + }body[128]; +}TFecBusPkgRxList; + +typedef struct{ + u32 PkgCount; + union{ + //char in UTF-8 + u8 D32[194]; + u8 D8[776]; + //C.9 + struct{ + u8 Cmd; //0x26 + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 DescpLen; + u8 DescpFirstByte; + }DescpInf; + //C.10 + struct{ + u8 Cmd; //0x27 + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 ProgramLen; + u8 ProgramFirstByte; + }ProgramInf; + //C.11 + struct{ + u8 Cmd; //0x27 + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 RegisterLen; + u8 RegisterFirstByte; + }RegisterInf; + //C.14 + struct{ + u8 Cmd; //0x2D + u8 CtlCount; + struct{ + u8 CtlNum; + u8 DevTypeLoByte; + u8 DevTypeHiByte; + }List[256]; + }CtlListInf; + struct{ + u8 Cmd; //0x2D + u8 CtlNum; + u8 UnitCount; + struct{ + u8 UnitNum; + u8 DevTypeLoByte; + u8 DevTypeHiByte; + }List[256]; + }UnitListInf; + struct{ + u8 Cmd; //0x2D + u8 CtlNum; + u8 UnitNum; + u8 DevCount; + struct{ + u8 DevNum; + u8 DevTypeLoByte; + u8 DevTypeHiByte; + }List[256]; + }DevListInf; + struct{ + u8 Cmd; //0x2D + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 ChannelCount; + struct{ + u8 ChlNum; + u8 DevTypeLoByte; + u8 DevTypeHiByte; + }List[256]; + }ChannelListInf; + }Body; +}TFecBusQueryLongReply; + +typedef enum{ + FecNotConnected = 0,//0 没有连接 + FecSetUpComm = 1,//1 建立连接 + FecPolling = 2,//2 巡检 + FecDownEvent,//3 下发事件 + FecDownCmd,//4 设置命令 +}TFecCommPhase; + +typedef enum{ + FecCommNone = 0, + FecCommExit = 1, + FecCommSyncSysTick00,//0 同步系统节拍 + FecCommSyncSysTick00Ack, + FecCommSysReset01,//1 系统复位 + FecCommSysReset01Ack, + FecCommSysMute02,//2 系统消音 + FecCommSysMute02Ack, + FecCommSysSlefCheck03,//3 系统自检 + FecCommSysSlefCheck03Ack, + FecCommSyncTime04,// 设置时间 + FecCommSyncTime04Ack, + FecCommDownEvent05,//通讯事件 + FecCommDownEvent05Ack, + FecCommDownEvent06, + FecCommDownEvent06Ack, + FecCommDownEvent07, + FecCommDownEvent07Ack, + FecCommPolling33,// 巡检33 + FecCommPolling33Ack, + FecCommPolling33Up,// 巡检33上传数据用表C.5 + FecCommPolling33UpAck, + FecCommQueryDeviceState34,//34 查设备状态 + FecCommQueryDeviceState34Ack, + FecCommQueryDeviceConfig35,//35 查设备配置 + FecCommQueryDeviceConfig35Ack, + FecCommQueryDeviceIdf36,//36 查设备标识 + FecCommQueryDeviceIdf36Ack, + FecCommQueryDeviceParameter37,//37 查设备参量 + FecCommQueryDeviceParameter37Ack, + FecCommQueryDeviceDescp38,//38 查设备注释 + FecCommQueryDeviceDescp38Ack, + FecCommQueryDeviceProgram39,//39 查设备编程 + FecCommQueryDeviceProgram39Ack, + FecCommQueryDeviceRegisterInfo40,//40 查注册登记信息 + FecCommQueryDeviceRegisterInfo40Ack, + FecCommQueryCurrentEvent41,// 查询当前事件 + FecCommQueryCurrentEvent41Ack, + FecCommQueryCurrentEvent41Ending, + FecCommQueryHistoryEvent42,//42 查设备历史事件 + FecCommQueryHistoryEvent42Ack, + FecCommQueryHistoryEvent42Ending, + FecCommStopQueryDeviceEvent43,//43 停止查询设备事件 + FecCommStopQueryDeviceEvent43Ack, + FecCommQueryVer44,// 第一次建立连接44，查询版本 + FecCommQueryVer44Ack, + FecCommQueryDeviceList45,//45 查设备列表 + FecCommQueryDeviceList45Ack, + FecCommDelay, +}TFecCommState; + +typedef struct{ + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 ChannelNum; + + u8 Addr; + u8 SYear; + u8 SMon; + u8 SDay; + + TFecEventCode Event;//u16 + u16 PathLevel; +}TFecCmdPath; + +typedef struct{ + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 Len; + u8 Value[256]; +}TGetCmd38_40Data; + +typedef struct{ + u32 type; + u8 CtlNum; + u8 UnitNum; + u8 DevNum; + u8 Count; + union{ + u32 d32[192]; + u8 d8[768]; + struct{ + u8 Order; + u8 DevTypeLoByte; + u8 DevTypeHiByte; + }List[256]; + }Body; +}TGetCmd45Data; + +typedef struct{ + u8 Register[64]; + + u8 CuuerntAddr; + u8 GetAddr; + u8 MsgIndex; + u8 AckStatus; + + TFecCommPhase Phase;//u8 + TFecCommState State;//u8 + u16 TimeoutTick; + + TFecAckCode AckCode;//u8 + u8 SetDownEventFlag; + u8 SetDownCmdFlag; + TFecCommState SetDownCmdState;//u8 + + TFecCmdPath SetDownPath; + + TFecStateCode GetCmd34DeviceState;//u16 + u16 GetCmd35ConfigCode; + + u8 GetCmd36DeviceIdf[8]; + u8 NoAckTick; + TParameterType GetCmd37DevicePrmType;//u8 + u16 GetCmd37DevicePrmValue; + + TGetCmd38_40Data GetCmd38To40Data; + u16 GetCmd44Ver; + u16 Rsv1; + TGetCmd45Data GetCmd45Data; + + TFecItemPath SetCmd37Path; + + u16 DownEventCount; + u16 DownEventTick; + u16 UpEventCount[64]; + u16 UpEventSRTick[64]; + + TFecEventBufBody DownEventData; + TFecEventBufBody UpEventData; + + u16 CurrentEventCount[64]; + u16 CurrentEventSRTick[64]; + u16 HistoryEventCount; + u16 HistoryEventSRTick; + + TFecEventBufBody CurrentEventData; + TFecEventBufBody HistoryEventData; +}TFecCommPrm; + +typedef struct{ + u8 Year ;//年（1字节） + u8 Mon;//月（1字节） + + u8 Day;//日（1字节） + u8 Hour;//时（1字节） + u8 Min;//分（1字节） + u8 Sec;//秒（1字节） + + u8 rsv1; + u8 rsv2; +}TFecTime; + +typedef struct{ + u32 Flag; + union{ + u8 D8[20]; + struct{ + u8 Head; + u8 DesAddr; + u8 Cmd; + u8 Len; + + u8 Data[16]; + }Body; + }Prm; +}TFecSetTest; + +class TFecBus{ + private: + u8 ThisAddr; + TFecBusType BusType; + u8 TmpD8[20]; + + TDMix16 TxCrc; + TDMix16 RxCrc; + + public: + TFecTime dateTime; + + u8 uMsgOutIndex; + u8 RxGetFlag; + u16 RxHandleFlag; + u16 TxSetFlag; + TFecAckCode RxMsgState;//u16 + + TFecBusPkgRxList RxMsg; + + TFecBusData uDataRX; + TFecBusData uDataTX; + + struct{ + unsigned char State; + unsigned char AckOk; + unsigned char OnGoing; + unsigned char Order; + unsigned char RetryTimes; + unsigned char RetryFLAG; + unsigned short TimeOutTick; + }OnTransmite; + + //Idf is Uart Or Can + TFecMsgReference MsgReference; + + //Long pkg In + TFecBusQueryLongReply LongReplyRx; + //Publish Event Buf In + TFecPublishMsgRxList PublishMsgRxList ; + + //Mid Len Pkg Buf Out + TFecBusMsgUartTx uMsgOut; + TFecBusMsgCanTx cMsgOut; + + //Long pkg Out + TFecBusQueryLongReply LongReplyTx; + + u8 FireElectricalCtlDevList[64]; + TFecCommPrm CommPrm; + + TFecSetTest SetDebug; + + private: + void MsgOutIndexInc(); + u8 FindIdleMsgIndex(void); + void LongReplyClearRx(void); + void LongReplyClearTx(void); + + public: + TFecBus(){}; + TFecBus(u8 aAddr, TFecBusType aBusType){ + Init(aAddr, aBusType); + } + void Init(); + void ResetCallBack(); + void Init(u8 aAddr, TFecBusType aBusType); + + void SetBusType(TFecBusType bsType); + + void ClearInput(void); + void ClearOutput(void); + TMsgInInf InputMsg(u8 *p); + TMsgInInf InputMsg(u32 *p); + + void SetDownEventData(u32 Ord); + void ClearDownEventList(); + void AddDownEventList(TFecEventBufBody * pEvent); + void ClearUpEventList(u8 aAddr); + void AddUpEventList(u8 aAddr, TFecEventBufBody * pEvent); + + void ClearCurrentEventList(u8 aAddr); + void AddCurrentEventList(u8 aAddr, TFecEventBufBody * pEvent); + void ClearHistoryEventList(); + void AddHistoryEventList(TFecEventBufBody * pEvent); + + void getSysTime(void); + + //Commo + void iBufProcess(); + void uDataRXTask(); + + void uSetTXData(); + void uDataTXTask();//10ms + void fMsg_ACK_State (TFecAckCode aStateCode); + void fMsg_ACK2Reply_State (TFecAckCode aStateCode); + + //表 C.3 设置数据帧 + //________________________________________________________________ + void fMsgTX00_SysSyncTick(u8 aDestAddr); //00 + void fMsgTX01_SysReset(u8 aDestAddr, u8 aCtlNum); //01 + void fMsgTX02_SysMute(u8 aDestAddr, u8 aCtlNum); //02 + void fMsgTX03_SysSelfCheck(u8 aDestAddr, u8 aCtlNum); //03 + void fMsgTX04_SyncTime(u8 aDestAddr, u8 aCtlNum, u8 aY, u8 aMon, u8 aDay, u8 aH, u8 aMin, u8 aSec);//04 + void fMsgTX05_PublishEmergencyEvent(u8 aDestAddr, TFecEventBufBody * pEvent); //05 通告紧急事件 + void fMsgTX06_PublishGeneralEvent(u8 aDestAddr, TFecEventBufBody * pEvent); //06 通告一般事件 + void fMsgTX07_PublishAdjustEvent(u8 aDestAddr, TFecEventBufBody * pEvent); //07 通告调试事件 + //表 C.4 设置数据帧应答 + unsigned int fMsgRX_Cmd00To07(u8 aSrcAddr); + unsigned int fMsgRX_Cmd15(u8 aSrcAddr, u8 aState); + + //________________________________________________________________ + + void fMsgTX15_Ack_StateAck(u8 aDestAddr, TFecAckCode aState); + void fMsgRpy17_Ack_PublishEmergencyEvent(u8 aDestAddr); + void fMsgRpy18_Ack_InformedGeneralEvent(u8 aDestAddr); + void fMsgRpy19_Ack_InformedAdjustEvent(u8 aDestAddr); + + unsigned int fMsgRX_Cmd17To19n41_42(u8 aSrcAddr,TFecEventBufBody * pFecEvent); + unsigned int fMsgRX_Cmd20(u8 aSrcAddr); + + //表 C.5 通告数据帧 + void fMsgC5_PublishEmergencyEvent(TFecItemPath aPath, u16 aDevType, u16 aEventCode, u16 aStateCode, TsDateTime aDt); //17 通告紧急事件 + void fMsgC5_PublishGeneralEvent (TFecItemPath aPath, u16 aDevType, u16 aEventCode, u16 aStateCode, TsDateTime aDt); //18 通告一般事件 + void fMsgC5_PublishAdjustEvent (TFecItemPath aPath, u16 aDevType, u16 aEventCode, u16 aStateCode, TsDateTime aDt); //19 通告调试事件 + void fMsgC5_PublishHeartBeat(void); //20 通告心跳 + //表 C.6 通告数据帧应答 + void fMsgC6_ACK_PublishEmergencyEvent(void); //17 通告紧急事件 + void fMsgC6_ACK_PublishGeneralEvent(void); //18 通告一般事件 + void fMsgC6_ACK_PublishAdjustEvent(void); //19 通告调试事件 + + //表 C.7 查询数据帧 + void fMsgTX33_InspectionDevice(u8 aDestAddr); //33 + + void fMsgTX34_QueryDeviceState(u8 aDestAddr); //34 + void fMsgTX34_QueryDeviceState(u8 aDestAddr, u8 aCtlNum); //34 + void fMsgTX34_QueryDeviceState(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum); //34 + void fMsgTX34_QueryDeviceState(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev); //34 + + void fMsgTX35_QueryDeviceConfig(u8 aDestAddr); //35 + void fMsgTX35_QueryDeviceConfig(u8 aDestAddr, u8 aCtlNum); //35 + void fMsgTX35_QueryDeviceConfig(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum); //35 + void fMsgTX35_QueryDeviceConfig(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev); //35 + + void fMsgTX36_QueryDeviceIdf(u8 aDestAddr); //36 + void fMsgTX36_QueryDeviceIdf(u8 aDestAddr, u8 aCtlNum); //36 + void fMsgTX36_QueryDeviceIdf(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum); //36 + void fMsgTX36_QueryDeviceIdf(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev); //36 + + void fMsgTX37_QueryDeviceParameter(u8 aDestAdd, TFecItemPath * pPath); //37 + void fMsgTX38_QueryDeviceDescp(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev); //38 + void fMsgTX39_QueryDeviceProgram(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev); //39 + + void fMsgTX40_QueryDeviceRegisterInfo(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum); //40 + void fMsgTX40_QueryDeviceRegisterInfo(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev); //40 + void fMsgTX41_QueryCurrentEvent(u8 aDestAddr, u8 aCtlNum, TFecEventCode aEvent); //41 + void fMsgTX42_QueryHistoryEvent(u8 aDestAddr, u8 aCtlNum, TFecEventCode aEvent, u8 aSY, u8 aSM, u8 aSD); //42 + void fMsgTX43_StopQueryDeviceEvent(u8 aDestAddr, u8 aCtlNum); //43 + void fMsgTX44_QueryFECBusVer(u8 aDestAddr); //44 + + void fMsgTX45_QueryDeviceList(u8 aDestAddr); //45 + void fMsgTX45_QueryDeviceList(u8 aDestAddr, u8 aCtlNum); //45 + void fMsgTX45_QueryDeviceList(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum); //45 + void fMsgTX45_QueryDeviceList(u8 aDestAddr, u8 aCtlNum, u8 aUnitNum, u8 aDev); //45 + + u32 fMsgRX_Cmd33(u8 aSrcAddr); + u32 fMsgRX_Cmd34(u8 aSrcAddr, TFecStateCode aStateCode); + u32 fMsgRX_Cmd35(u8 aSrcAddr, u16 aConfigCode); + u32 fMsgRX_Cmd36(u8 aSrcAddr, u8 * aIdfCode); + u32 fMsgRX_Cmd37(u8 aSrcAddr, TParameterType aPrmType, u16 aPrm); + u32 fMsgRX_Cmd38_40(u8 aSrcAddr, TGetCmd38_40Data * pData); + u32 fMsgRX_Cmd43(u8 aSrcAddr); + u32 fMsgRX_Cmd44(u8 aSrcAddr, u16 aVer); + u32 fMsgRX_Cmd45(u8 aSrcAddr, TGetCmd45Data * pTData); + + void fMsgC7_QueryDevEvent (TFecItemPath aPath); //41 + void fMsgC7_QueryDevEventHistory (TFecItemPath aPath, TFecEventCode aEvt, TsDateTime aDT); //42 + void fMsgC7_CancleQueryDevEvent (TFecItemPath aPath); //43 + void fMsgC7_QueryThisVer (TFecItemPath aPath); //44 + + void fMsgC7_QueryDevList (void); //45 //查询控制器列表 + void fMsgC7_QueryDevList (u8 aCtlNum); //45 //查询单元列表 + void fMsgC7_QueryDevList (u8 aCtlNum, u8 aUnitNum); //45 //查询设备列表 + void fMsgC7_QueryDevList (u8 aCtlNum, u8 aUnitNum, u8 aDev); //45 //查询通道列表 + + //表 C.8 单帧查询应答数据帧 + void fMsgC8_Reply_DevInspection (void); //33 + void fMsgC8_Reply_QueryDevState (u16 aStateCode); //34 + void fMsgC8_Reply_QueryDevConfig (u16 aStateCode); //35 + void fMsgC8_Reply_QueryDevIdentify (u8 *p);//36 + + void fMsgC8_Reply_QueryDevParameter (TParameterType aType, u16 aValue); //37 + void fMsgC8_Reply_QueryDevParameter (TParameterType aType, u32 aValue); //37 + + void fMsgC8_Reply_CancleQueryDevEvent (void); //43 + void fMsgC8_Reply_QueryThisVer (u16 aVer); //44 + + //表 C.9 查询设备注释信息应答数据帧 + void fMsgC9_Reply_QueryDevDescp (TFecItemPath aPath, u8 aDescpLength, u8 *p); //38 The Descp payload is In UTF-8 + + //表 C.10 查询设备编程信息应答数据帧 + void fMsgC10_Reply_QueryDevProgram (TFecItemPath aPath, u8 aCodeLength, u8 *p); //39 The Descp payload is In UTF-8 + + //表 C.11 查询设备信息应答数据帧 + void fMsgC11_Reply_QueryDevRegisterInf (TFecItemPath aPath, u8 aInfLength, u8 *p); //40 + + //表 C.12 查询当前事件应答数据帧 + void fMsgC12_Reply_QueryDevEvent (TFecItemPath aPath, TFecDevTypeCode aDtc, TFecEventCode aEvt, u16 aDevState, TsDateTime aDT); //41 + void fMsgC12_Reply_QueryDevEvent (TFecItemPath aPath, u16 aDtc, u16 aEvt, u16 aDevState, TsDateTime aDT); //41 + + //表 C.13 查询设备历史事件应答数据帧 + void fMsgC13_Reply_QueryDevEventHistory (TFecItemPath aPath, TFecDevTypeCode aDtc, TFecEventCode aEvt, u16 aDevState, TsDateTime aDT); //42 + void fMsgC13_Reply_QueryDevEventHistory (TFecItemPath aPath, u16 aDtc, u16 aEvt, u16 aDevState, TsDateTime aDT); //42 + + //表 C.14 查询设备列表应答数据帧 + void C14_DevList_CtlClearTx(void); + void C14_DevList_UnitClearTx(void); + void C14_DevList_DevClearTx(void); + void C14_DevList_ChlClearTx(void); + void C14_DevList_CtlAdd (u8 aCtlNum, TFecDevTypeCode aDtc); //Add Item to 控制器列表 + void C14_DevList_UnitAdd (u8 aCtlNum, u8 aUnitNum, TFecDevTypeCode aDtc); //Add Item to 单元列表 + void C14_DevList_DevAdd (u8 aCtlNum, u8 aUnitNum, u8 aDev, TFecDevTypeCode aDtc); //Add Item to 设备列表 + void C14_DevList_ChlAdd (u8 aCtlNum, u8 aUnitNum, u8 aDev, u8 aChl, TFecDevTypeCode aDtc); //Add Item to 通道列表 + void fMsgC14_Reply_QueryDevList_Ctl (void); //45 //查询控制器列表 + void fMsgC14_Reply_QueryDevList_Unit (void); //45 //查询单元列表 + void fMsgC14_Reply_QueryDevList_Dev (void); //45 //查询设备列表 + void fMsgC14_Reply_QueryDevList_Chl (void); //45 //查询通道列表 + + void ProcesserPublishEmergyRx(void); + void ProcesserPublishRx(void); + + u32 GetNewPublishCount(void); + u32 GetNewPublishEmerGyCount(void); + + u32 MsgIn(u32 CanExdId, u32 data0, u32 data1); + u32 MsgIn(u8 *pData, u32 Len); + u32 CheckInput(void); + + u16 Crc16(u8 *pD, u8 Len) const; + void Crc16(); + + void Task10ms(void); + void Task100ms(void); + void OperationTask(void); + + void SetRegister(u8 aAddr); + u8 GetRegisterStatus(u8 aAddr); + void SetLogout(u8 aAddr); + + void SetDownEventList(u8 aType,u8 aCount); + void SetDownCmdList(void); + + void GetUpEventTask(void); + void SetCommAddr(u8 addr); + void SetCommPhase(u8 addr);//通讯阶段 下发事件，下发命令，建立连接 + void SetCommState(u8 addr);//通讯状态 巡检，功能码 + + void SetUpCommTask(void); + + void EnterSetDownEvent(u8 aAddr); + void DownEventTask(void); + + void EnterSetDownCmd(TFecFunctionCode aCmd, TFecCmdPath * aCmdPath); + void DownCmdAckHandle(void); + void DownCmdTask(void); + + void SendPollingTask(void); + + void DebugProcess(void); + + void TriggerCmd01SysReset(void); + void TriggerCmd02SysMute(void); + void TrigerCmd03SysSlefCheck(void); + void TriggerCmd04SyncTime(void); +}; + +#endif + diff --git a/MyCode/src/ProtoFecBusCRT.cpp b/MyCode/src/ProtoFecBusCRT.cpp new file mode 100644 index 0000000..1db5eba --- /dev/null +++ b/MyCode/src/ProtoFecBusCRT.cpp @@ -0,0 +1,1887 @@ +#include "ProtoFecBusCRT.h" +#include "MainCtl.h" +#include "CnCpp.h" + +#define FecBusMasterAddr 1 + +extern "C"{ + #include "uart_fecbus_drv.h" + #include "uart_key_drv.h" +} + +unsigned short FecBusCRTStateCode; +unsigned char MsgFrmIndex = 1; + +void TFecBusCRT::Init() +{ + unsigned int i; + unsigned int x; + unsigned int aAddr; + + RxGetFlag = 0; + TxSetFlag = 0; + + InTxIndex = 0; + OutTxIndex = 0; + + OnlineTick = 0; + + for(i=0; i 63)MsgFrmIndex = 1; +} + +unsigned short TFecBusCRT::Crc16Data(unsigned char* pdata,unsigned int len) +{ + unsigned int x = 0,y = 0; + unsigned short crc = 0xFFFF; + unsigned char data = 0; + + for(x=0;x>=1; + crc ^= 0xA001; + }else{ + crc>>=1; + } + } + pdata++; + } + return crc; +} + +unsigned int TFecBusCRT::CheckCrc16(unsigned char* pdata,unsigned int len) +{ + unsigned short CrcData = 0; + + CrcData = *(pdata + len - 1); + CrcData<<=8; + CrcData |= *(pdata + len - 2); + + if(CrcData == Crc16Data(pdata,(len - 2))){ + return 0; + } + return 1; +} + +void TFecBusCRT::iBufInsert() +{ + ; +} + +void TFecBusCRT::iBufProcess() +{ + unsigned char aYear, aMon, aDay, aHour, aMin, aSec; + + if(RxGetFlag){ + RxGetFlag = 0; + + if(ackRecDataCorrect == RxMsgState){ + + OnlineTick = 0; + ErrState.Body.OffLine = 0; + ErrState.Body.OffLineTick = 0; + + if((2 == RxMsg.Prm.Section[0].body.Dlen)&&(FecFunStateAck == RxMsg.Prm.Section[0].body.DPFC[0])&&\ + (ackAddrNotExist != RxMsg.Prm.Section[0].body.DPFC[1])&&(RxMsg.Prm.Section[0].body.DPFC[1] <= ackRecDataCorrect)){ + + OnTransmite.AckOk = 1; + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + OnTransmite.TimeOutTick = 0; + + if(ErrReport.Body.OffLine){ + //Remove Err Here + ErrReport.Body.OffLine = 0; + CtlCenter.ieAddBrdFaultCancel(9, 9); + } + }else + if((4 == RxMsg.Prm.Section[0].body.Dlen)&&(FecQueryCurrentEvent == RxMsg.Prm.Section[0].body.DPFC[0])){ + //------------------------------------------------------------------------------------------------------------->>>>> + Upload.Active = 1; + Upload.InxFire = 0; + Upload.InxStart = 0; + Upload.InxSv = 0; + Upload.InxFault = 0; + Upload.InxMask = 0; + }else + if((8 == RxMsg.Prm.Section[0].body.Dlen)&&(FecFunSyncTime == RxMsg.Prm.Section[0].body.DPFC[0])){ + aYear = (RxMsg.Prm.Section[0].body.DPFC[2]/10*16) + (RxMsg.Prm.Section[0].body.DPFC[2]%10); + aMon = (RxMsg.Prm.Section[0].body.DPFC[3]/10*16) + (RxMsg.Prm.Section[0].body.DPFC[3]%10); + aDay = (RxMsg.Prm.Section[0].body.DPFC[4]/10*16) + (RxMsg.Prm.Section[0].body.DPFC[4]%10); + aHour = (RxMsg.Prm.Section[0].body.DPFC[5]/10*16) + (RxMsg.Prm.Section[0].body.DPFC[5]%10); + aMin = (RxMsg.Prm.Section[0].body.DPFC[6]/10*16) + (RxMsg.Prm.Section[0].body.DPFC[6]%10); + aSec = (RxMsg.Prm.Section[0].body.DPFC[7]/10*16) + (RxMsg.Prm.Section[0].body.DPFC[7]%10); + DataTimeSet(aYear, aMon, aDay, aHour, aMin, aSec, 1); //aWk 1..7 + Record.OperateAdd_CfgDateTime(aYear, aMon, aDay, aHour, aMin ,aSec); + }else + if((1 == RxMsg.Prm.Section[0].body.Dlen)&&(FecFunInformedHeartbeat == RxMsg.Prm.Section[0].body.DPFC[0])){ + rpyFecBusCRTMsg15();//应答状态 + } + }else + if(ackCrcError == RxMsgState){ + OnlineTick = 0; + ErrState.Body.OffLine = 0; + ErrState.Body.OffLineTick = 0; + } + } +} + +void TFecBusCRT::oBufInsert()//10ms +{ + unsigned int i,x,y; + unsigned int aAddr; + + if(!OnTransmite.OnGoing){ + + if(InTxIndex != OutTxIndex){ + OutTxIndex++; + if(OutTxIndex >= dFecCRT_BufCount_Tx)OutTxIndex = 0; + + aAddr = dAddrSdram_CrtTxBuf + (OutTxIndex * dFecCRT_BufEntrySize_Tx); + for(i=0;i<(dFecCRT_BufEntrySize_Tx/4);i++) + TxMsg.D32[i] = *(volatile unsigned int *)(aAddr + (i*4)); + /* + TxMsg.avalibel = TxCRTMsg[OutTxIndex].avalibel; + TxMsg.UsingMsgIndex = TxCRTMsg[OutTxIndex].UsingMsgIndex; + TxMsg.FrameNum = TxCRTMsg[OutTxIndex].FrameNum; + + for(y = 0;y < TxMsg.FrameNum;y++){ + if(y > 3)break; + for(x = 0;x < 5;x++){ + TxMsg.Section[y].D32[x] = TxCRTMsg[OutTxIndex].Section[y].D32[x]; + } + } + */ + TxSetFlag = 1; + } + } +} + +void TFecBusCRT::oBufProcess()//10ms +{ + unsigned int retry_time = 0; + + if(OnTransmite.OnGoing){ + OnTransmite.TimeOutTick++; + + retry_time = 99;//1000ms retry + + if(OnTransmite.TimeOutTick > retry_time){ + OnTransmite.TimeOutTick = 0; + + if(OnTransmite.RetryTimes < 3){ + OnTransmite.RetryFLAG = 1; + }else{ + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + //ErrState |= exErrCom; + } + } + } + + if(!fecbus_tx_is_busy()){ + if(TxSetFlag){ + if(TxMsg.Prm.UsingMsgIndex){ + TxMsg.Prm.FrameTick++; + if(TxMsg.Prm.FrameTick >= TxMsg.Prm.FrameNum){ + TxMsg.Prm.FrameTick = 0; + TxSetFlag = 0; + } + set_fecbus_tx_data(TxMsg.Prm.Section[TxMsg.Prm.FrameTick].da8); + }else{ + set_fecbus_tx_data(TxMsg.Prm.Section[0].da8); + TxSetFlag = 0; + } + OnTransmite.TimeOutTick = 0; + OnTransmite.AckOk = 0; + OnTransmite.OnGoing = 1; + }else + if(OnTransmite.RetryFLAG){ + if(TxMsg.Prm.UsingMsgIndex){ + TxMsg.Prm.FrameTick++; + if(TxMsg.Prm.FrameTick >= TxMsg.Prm.FrameNum){ + TxMsg.Prm.FrameTick = 0; + OnTransmite.RetryFLAG = 0; + OnTransmite.RetryTimes++; + } + set_fecbus_tx_data(TxMsg.Prm.Section[TxMsg.Prm.FrameTick].da8); + }else{ + set_fecbus_tx_data(TxMsg.Prm.Section[0].da8); + OnTransmite.RetryFLAG = 0; + OnTransmite.RetryTimes++; + } + + OnTransmite.TimeOutTick = 0; + OnTransmite.AckOk = 0; + OnTransmite.OnGoing = 1; + } + } +} + +void TFecBusCRT::iFecBusMsgInsert(TFecBusMsgUart * pMsg) +{ + unsigned int i = 0; + unsigned int aSection = 0; + unsigned int aAddr; + + InTxIndex++; + if(InTxIndex >= dFecCRT_BufCount_Tx)InTxIndex = 0; + + //----------------load to full----------------------- + if(InTxIndex == OutTxIndex){ + if(0 == InTxIndex)InTxIndex = dFecCRT_BufCount_Tx; + else InTxIndex--; + return; + } + //---------------------------------------------------- + + aAddr = dAddrSdram_CrtTxBuf + (InTxIndex * dFecCRT_BufEntrySize_Tx); + for(i=0;i<(dFecCRT_BufEntrySize_Tx/4);i++) + *(volatile unsigned int *)(aAddr + (i*4)) = pMsg->D32[i]; + /* + TxCRTMsg[InTxIndex].avalibel = pMsg->avalibel; + TxCRTMsg[InTxIndex].UsingMsgIndex = pMsg->UsingMsgIndex; + TxCRTMsg[InTxIndex].FrameNum = pMsg->FrameNum; + + for(aSection = 0;aSection < (pMsg->FrameNum);aSection++){ + for(i=0;i<5;i++){ + TxCRTMsg[InTxIndex].Section[aSection].D32[i] = pMsg->Section[aSection].D32[i]; + } + } + */ +} + +void TFecBusCRT::iSetFecBusBufEnd(TFecBusMsgUart * pMsg,unsigned char Priority) +{ + TCrcValue CrcValue; + + pMsg->Prm.Section[0].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[0].body.FrmType = 0; + pMsg->Prm.Section[0].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[0].body.Priority = Priority; + pMsg->Prm.Section[0].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[0].body.MsgIndex = 0x01;//------------- + pMsg->Prm.Section[0].body.FrmIndex = 0x00; + pMsg->Prm.Section[0].body.Dlen = 0x02; + pMsg->Prm.Section[0].body.DPFC[0] = 0x0F; + pMsg->Prm.Section[0].body.DPFC[1] = 0x00; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[0].da8, (pMsg->Prm.Section[0].body.Dlen + 8)); + + pMsg->Prm.Section[0].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[0].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[0].body.Eop = FECBUS_END; +} + +void TFecBusCRT::iSetFecBusMsg00(TFecBusMsgUart * pMsg) +{ + TCrcValue CrcValue; + + pMsg->Prm.avalibel = 1; + pMsg->Prm.UsingMsgIndex = 0; + pMsg->Prm.FrameNum = 1; + + pMsg->Prm.Section[0].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[0].body.FrmType = 0; + pMsg->Prm.Section[0].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[0].body.Priority = 0x00; + pMsg->Prm.Section[0].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[0].body.MsgIndex = 0x00; + pMsg->Prm.Section[0].body.FrmIndex = 0x00; + pMsg->Prm.Section[0].body.Dlen = 0x01; + pMsg->Prm.Section[0].body.DPFC[0] = FecFunSyncSysTick; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[0].da8, (pMsg->Prm.Section[0].body.Dlen + 8)); + + pMsg->Prm.Section[0].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[0].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[0].body.Eop = FECBUS_END; +} + +void TFecBusCRT::iSetFecBusMsg01(TFecBusMsgUart * pMsg, unsigned char aCtlNum) +{ + TCrcValue CrcValue; + + pMsg->Prm.avalibel = 1; + pMsg->Prm.UsingMsgIndex = 0; + pMsg->Prm.FrameNum = 1; + + pMsg->Prm.Section[0].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[0].body.FrmType = 0; + pMsg->Prm.Section[0].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[0].body.Priority = 0x01; + pMsg->Prm.Section[0].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[0].body.MsgIndex = 0x01; + pMsg->Prm.Section[0].body.FrmIndex = 0x00; + pMsg->Prm.Section[0].body.Dlen = 0x02; + pMsg->Prm.Section[0].body.DPFC[0] = FecFunSysReset; + pMsg->Prm.Section[0].body.DPFC[1] = aCtlNum; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[0].da8, (pMsg->Prm.Section[0].body.Dlen + 8)); + + pMsg->Prm.Section[0].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[0].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[0].body.Eop = FECBUS_END; +} + +void TFecBusCRT::iSetFecBusMsg02(TFecBusMsgUart * pMsg, unsigned char aCtlNum) +{ + TCrcValue CrcValue; + + pMsg->Prm.avalibel = 1; + pMsg->Prm.UsingMsgIndex = 0; + pMsg->Prm.FrameNum = 1; + + pMsg->Prm.Section[0].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[0].body.FrmType = 0; + pMsg->Prm.Section[0].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[0].body.Priority = 0x01; + pMsg->Prm.Section[0].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[0].body.MsgIndex = 0x01; + pMsg->Prm.Section[0].body.FrmIndex = 0x00; + pMsg->Prm.Section[0].body.Dlen = 0x02; + pMsg->Prm.Section[0].body.DPFC[0] = FecFunSysMute; + pMsg->Prm.Section[0].body.DPFC[1] = aCtlNum; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[0].da8, (pMsg->Prm.Section[0].body.Dlen + 8)); + + pMsg->Prm.Section[0].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[0].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[0].body.Eop = FECBUS_END; +} + +void TFecBusCRT::iSetFecBusMsg03(TFecBusMsgUart * pMsg, unsigned char aCtlNum) +{ + TCrcValue CrcValue; + + pMsg->Prm.avalibel = 1; + pMsg->Prm.UsingMsgIndex = 0; + pMsg->Prm.FrameNum = 1; + + pMsg->Prm.Section[0].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[0].body.FrmType = 0; + pMsg->Prm.Section[0].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[0].body.Priority = 0x03; + pMsg->Prm.Section[0].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[0].body.MsgIndex = 0x01; + pMsg->Prm.Section[0].body.FrmIndex = 0x00; + pMsg->Prm.Section[0].body.Dlen = 0x02; + pMsg->Prm.Section[0].body.DPFC[0] = FecFunSysSlefCheck; + pMsg->Prm.Section[0].body.DPFC[1] = aCtlNum; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[0].da8, (pMsg->Prm.Section[0].body.Dlen + 8)); + + pMsg->Prm.Section[0].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[0].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[0].body.Eop = FECBUS_END; +} + +void TFecBusCRT::iSetFecBusMsg05(TFecBusMsgUart * pMsg, TFecEventBufBody * pEvent) +{ + TCrcValue CrcValue; + + pMsg->Prm.avalibel = 1; + pMsg->Prm.UsingMsgIndex = 1; + pMsg->Prm.FrameNum = 4; + + //-------------------------------------1------------------------------------------------- + pMsg->Prm.Section[1].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[1].body.FrmType = 0; + pMsg->Prm.Section[1].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[1].body.Priority = 0x01; + pMsg->Prm.Section[1].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[1].body.MsgIndex = 0x01; + pMsg->Prm.Section[1].body.FrmIndex = 0x01; + pMsg->Prm.Section[1].body.Dlen = 0x08; + pMsg->Prm.Section[1].body.DPFC[0] = FecFunPublishEmergencyEvent; + pMsg->Prm.Section[1].body.DPFC[1] = pEvent->D8[0]; + pMsg->Prm.Section[1].body.DPFC[2] = pEvent->D8[1]; + pMsg->Prm.Section[1].body.DPFC[3] = pEvent->D8[2]; + pMsg->Prm.Section[1].body.DPFC[4] = pEvent->D8[3]; + pMsg->Prm.Section[1].body.DPFC[5] = pEvent->D8[4]; + pMsg->Prm.Section[1].body.DPFC[6] = pEvent->D8[5]; + pMsg->Prm.Section[1].body.DPFC[7] = pEvent->D8[6]; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[1].da8, (pMsg->Prm.Section[1].body.Dlen + 8)); + + pMsg->Prm.Section[1].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[1].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[1].body.Eop = FECBUS_END; + //-------------------------------------2------------------------------------------------- + pMsg->Prm.Section[2].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[2].body.FrmType = 0; + pMsg->Prm.Section[2].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[2].body.Priority = 0x01; + pMsg->Prm.Section[2].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[2].body.MsgIndex = 0x01; + pMsg->Prm.Section[2].body.FrmIndex = 0x02; + pMsg->Prm.Section[2].body.Dlen = 0x08; + pMsg->Prm.Section[2].body.DPFC[0] = pEvent->D8[7]; + pMsg->Prm.Section[2].body.DPFC[1] = pEvent->D8[8]; + pMsg->Prm.Section[2].body.DPFC[2] = pEvent->D8[9]; + pMsg->Prm.Section[2].body.DPFC[3] = pEvent->D8[10]; + pMsg->Prm.Section[2].body.DPFC[4] = pEvent->D8[11]; + pMsg->Prm.Section[2].body.DPFC[5] = pEvent->D8[12]; + pMsg->Prm.Section[2].body.DPFC[6] = pEvent->D8[13]; + pMsg->Prm.Section[2].body.DPFC[7] = pEvent->D8[14]; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[2].da8, (pMsg->Prm.Section[2].body.Dlen + 8)); + + pMsg->Prm.Section[2].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[2].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[2].body.Eop = FECBUS_END; + //-------------------------------------3------------------------------------------------- + pMsg->Prm.Section[3].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[3].body.FrmType = 0; + pMsg->Prm.Section[3].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[3].body.Priority = 0x01; + pMsg->Prm.Section[3].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[3].body.MsgIndex = 0x01; + pMsg->Prm.Section[3].body.FrmIndex = 0x03; + pMsg->Prm.Section[3].body.Dlen = 0x01; + pMsg->Prm.Section[3].body.DPFC[0] = pEvent->D8[15]; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[3].da8, (pMsg->Prm.Section[3].body.Dlen + 8)); + + pMsg->Prm.Section[3].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[3].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[3].body.Eop = FECBUS_END; + + iSetFecBusBufEnd(pMsg,0x01); +} + +void TFecBusCRT::iSetFecBusMsg06(TFecBusMsgUart * pMsg, TFecEventBufBody * pEvent) +{ + TCrcValue CrcValue; + + pMsg->Prm.avalibel = 1; + pMsg->Prm.UsingMsgIndex = 1; + pMsg->Prm.FrameNum = 4; + + //-------------------------------------1------------------------------------------------- + pMsg->Prm.Section[1].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[1].body.FrmType = 0; + pMsg->Prm.Section[1].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[1].body.Priority = 0x03; + pMsg->Prm.Section[1].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[1].body.MsgIndex = 0x01; + pMsg->Prm.Section[1].body.FrmIndex = 0x01; + pMsg->Prm.Section[1].body.Dlen = 0x08; + pMsg->Prm.Section[1].body.DPFC[0] = FecFunPublishGeneralEvent; + pMsg->Prm.Section[1].body.DPFC[1] = pEvent->D8[0]; + pMsg->Prm.Section[1].body.DPFC[2] = pEvent->D8[1]; + pMsg->Prm.Section[1].body.DPFC[3] = pEvent->D8[2]; + pMsg->Prm.Section[1].body.DPFC[4] = pEvent->D8[3]; + pMsg->Prm.Section[1].body.DPFC[5] = pEvent->D8[4]; + pMsg->Prm.Section[1].body.DPFC[6] = pEvent->D8[5]; + pMsg->Prm.Section[1].body.DPFC[7] = pEvent->D8[6]; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[1].da8, (pMsg->Prm.Section[1].body.Dlen + 8)); + + pMsg->Prm.Section[1].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[1].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[1].body.Eop = FECBUS_END; + //-------------------------------------2------------------------------------------------- + pMsg->Prm.Section[2].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[2].body.FrmType = 0; + pMsg->Prm.Section[2].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[2].body.Priority = 0x03; + pMsg->Prm.Section[2].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[2].body.MsgIndex = 0x01; + pMsg->Prm.Section[2].body.FrmIndex = 0x02; + pMsg->Prm.Section[2].body.Dlen = 0x08; + pMsg->Prm.Section[2].body.DPFC[0] = pEvent->D8[7]; + pMsg->Prm.Section[2].body.DPFC[1] = pEvent->D8[8]; + pMsg->Prm.Section[2].body.DPFC[2] = pEvent->D8[9]; + pMsg->Prm.Section[2].body.DPFC[3] = pEvent->D8[10]; + pMsg->Prm.Section[2].body.DPFC[4] = pEvent->D8[11]; + pMsg->Prm.Section[2].body.DPFC[5] = pEvent->D8[12]; + pMsg->Prm.Section[2].body.DPFC[6] = pEvent->D8[13]; + pMsg->Prm.Section[2].body.DPFC[7] = pEvent->D8[14]; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[2].da8, (pMsg->Prm.Section[2].body.Dlen + 8)); + + pMsg->Prm.Section[2].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[2].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[2].body.Eop = FECBUS_END; + //-------------------------------------3------------------------------------------------- + pMsg->Prm.Section[3].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[3].body.FrmType = 0; + pMsg->Prm.Section[3].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[3].body.Priority = 0x03; + pMsg->Prm.Section[3].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[3].body.MsgIndex = 0x01; + pMsg->Prm.Section[3].body.FrmIndex = 0x03; + pMsg->Prm.Section[3].body.Dlen = 0x01; + pMsg->Prm.Section[3].body.DPFC[0] = pEvent->D8[15]; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[3].da8, (pMsg->Prm.Section[3].body.Dlen + 8)); + + pMsg->Prm.Section[3].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[3].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[3].body.Eop = FECBUS_END; + + iSetFecBusBufEnd(pMsg,0x03); +} + +void TFecBusCRT::iSetFecBusMsg15(TFecBusMsgUart * pMsg) +{ + TCrcValue CrcValue; + + pMsg->Prm.avalibel = 1; + pMsg->Prm.UsingMsgIndex = 0; + pMsg->Prm.FrameNum = 1; + + pMsg->Prm.Section[0].body.Header = FECBUS_HEAD; + pMsg->Prm.Section[0].body.FrmType = 1; + pMsg->Prm.Section[0].body.DestAddr = GraphAddr;//CRT addr + pMsg->Prm.Section[0].body.Priority = 0x03; + pMsg->Prm.Section[0].body.SrcAddr = FecBusMasterAddr;//fix 0x01; MainCtl.fData.Split.MyNum; + pMsg->Prm.Section[0].body.MsgIndex = 0x01; + pMsg->Prm.Section[0].body.FrmIndex = 0x00; + pMsg->Prm.Section[0].body.Dlen = 0x02; + pMsg->Prm.Section[0].body.DPFC[0] = FecFunStateAck; + pMsg->Prm.Section[0].body.DPFC[1] = ackRecDataCorrect; + + CrcValue.D16 = Crc16Data(pMsg->Prm.Section[0].da8, (pMsg->Prm.Section[0].body.Dlen + 8)); + + pMsg->Prm.Section[0].body.CrcLoByte = CrcValue.body.LoByte; + pMsg->Prm.Section[0].body.CrcHiByte = CrcValue.body.HiByte; + pMsg->Prm.Section[0].body.Eop = FECBUS_END; +} + +void TFecBusCRT::setFecBusCRTMsg01(unsigned char aCtlNum) +{ + iSetFecBusMsg01(&FecBusMsgUartTemp, aCtlNum); + iFecBusMsgInsert(&FecBusMsgUartTemp); +} + +void TFecBusCRT::setFecBusCRTMsg02(unsigned char aCtlNum) +{ + iSetFecBusMsg02(&FecBusMsgUartTemp, aCtlNum); + iFecBusMsgInsert(&FecBusMsgUartTemp); +} + +void TFecBusCRT::setFecBusCRTMsg03(unsigned char aCtlNum) +{ + iSetFecBusMsg03(&FecBusMsgUartTemp, aCtlNum); + iFecBusMsgInsert(&FecBusMsgUartTemp); +} + +void TFecBusCRT::rpyFecBusCRTMsg15(void) +{ + iSetFecBusMsg15(&FecBusMsgUartTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); +} + +void TFecBusCRT::getFecBusCRTTime(TRecordCommon aRC) +{ + FecBusCRTBufTemp.Data.Year = (aRC.Splite.Year/16*10) + (aRC.Splite.Year & 0x0F); + FecBusCRTBufTemp.Data.Mon = (aRC.Splite.Month/16*10) + (aRC.Splite.Month & 0x0F); + FecBusCRTBufTemp.Data.Day = (aRC.Splite.Day/16*10) + (aRC.Splite.Day & 0x0F); + FecBusCRTBufTemp.Data.Hour = (aRC.Splite.Hour/16*10) + (aRC.Splite.Hour & 0x0F); + FecBusCRTBufTemp.Data.Min = (aRC.Splite.Minute/16*10) + (aRC.Splite.Minute & 0x0F); + FecBusCRTBufTemp.Data.Sec = (aRC.Splite.Second/16*10) + (aRC.Splite.Second & 0x0F); +} + +void TFecBusCRT::getFecBusCRTStateCode(unsigned short StateCode) +{ + FecBusCRTBufTemp.Data.StateCode.D16 = StateCode; +} + +void TFecBusCRT::setFecBusCRTStateCode(unsigned short StateCode) +{ + FecBusCRTStateCode = StateCode; +} + +void TFecBusCRT::SetStateCodeAll() +{ + unsigned int aC; + aC = 0; + + //AllowAuto, AllowManual, + if(AllowAuto) aC |= 1; + if(PowerSuplyState) aC |= 2; + if(PowerSuplyComm | PowerBkState | BatState) aC |= 4; + if(CtlCenter.ieMsgFire.Count >0) aC |= 8; + if(CtlCenter.ieMsgLinkage.StartCount >0) aC |= 0x0000'0010; + if(CtlCenter.ieMsgLinkage.FbCount >0) aC |= 0x0000'0020; + if(CtlCenter.ieMsgSv.Count >0) aC |= 0x0000'0040; + if(CtlCenter.ieMsgFault.Count >0) aC |= 0x0000'0080; + if(CtlCenter.ieMsgMask.Count >0) aC |= 0x0000'0100; + + setFecBusCRTStateCode(static_cast(aC)); +} + +void TFecBusCRT::SetStateCodeAutoManual() +{ + if(AllowAuto)FecBusCRTStateCode |= 0x0001; + else FecBusCRTStateCode &= ~0x0001; +} + +void TFecBusCRT::SetStateCodePsOnActive() +{ + if(PowerSuplyState)FecBusCRTStateCode |= 0x0002; + else FecBusCRTStateCode &= ~0x0002; +} + +void TFecBusCRT::SetStateCodePsError() +{ + if(PowerSuplyComm | PowerBkState | BatState)FecBusCRTStateCode |= 0x0004; + else FecBusCRTStateCode &= ~0x0004; +} + +void TFecBusCRT::SetStateCodeFire() +{ + if(CtlCenter.ieMsgFire.Count >0)FecBusCRTStateCode |= 0x0008; + else FecBusCRTStateCode &= ~0x0008; +} + +void TFecBusCRT::SetStateCodeStart() +{ + if(CtlCenter.ieMsgLinkage.StartCount >0)FecBusCRTStateCode |= 0x0010; + else FecBusCRTStateCode &= ~0x0010; +} + +void TFecBusCRT::SetStateCodeFeedBack() +{ + if(CtlCenter.ieMsgLinkage.FbCount >0)FecBusCRTStateCode |= 0x0020; + else FecBusCRTStateCode &= ~0x0020; +} + +void TFecBusCRT::SetStateCodeSv() +{ + if(CtlCenter.ieMsgSv.Count >0)FecBusCRTStateCode |= 0x0040; + else FecBusCRTStateCode &= ~0x0040; +} + +void TFecBusCRT::SetStateCodeFault() +{ + if(CtlCenter.ieMsgFault.Count >0)FecBusCRTStateCode |= 0x0080; + else FecBusCRTStateCode &= ~0x0080; +} + +void TFecBusCRT::SetStateCodeMask() +{ + if(CtlCenter.ieMsgMask.Count >0)FecBusCRTStateCode |= 0x0100; + else FecBusCRTStateCode &= ~0x0100; +} + +void TFecBusCRT::getFecBusCRTDeviceCode(unsigned char dType) +{ + if(GBDeviceCodePrm[dType]){ + FecBusCRTBufTemp.Data.DeviceCode = dType; + }else{ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + } +} + +void TFecBusCRT::getFecBusCRTEpFaultEvent(unsigned char aType, unsigned char State) +{ + if(1 == State){ + switch(aType){ + case 0: + FecBusCRTBufTemp.Data.EventCode = evFault; + break; + + case 1: + case 2: + case 3: + FecBusCRTBufTemp.Data.EventCode = evFaultComponent; + break; + + case 4: + case 5: + FecBusCRTBufTemp.Data.EventCode = evFaultCircuit; + break; + + case 6: + FecBusCRTBufTemp.Data.EventCode = evFaultMainPower; + break; + + case 7: + case 8: + FecBusCRTBufTemp.Data.EventCode = evFaultSparePower; + break; + + default: + FecBusCRTBufTemp.Data.EventCode = evUndefine; + break; + } + }else{ + switch(aType){ + case 0: + FecBusCRTBufTemp.Data.EventCode = evFaultRecover; + break; + + case 1: + case 2: + case 3: + FecBusCRTBufTemp.Data.EventCode = evFaultComponentRecover; + break; + + case 4: + case 5: + FecBusCRTBufTemp.Data.EventCode = evFaultCircuitRecover; + break; + + case 6: + FecBusCRTBufTemp.Data.EventCode = evFaultMainPowerRecover; + break; + + case 7: + case 8: + FecBusCRTBufTemp.Data.EventCode = evFaultSparePowerRecover; + break; + + default: + FecBusCRTBufTemp.Data.EventCode = evUndefine; + break; + } + } +} + +void TFecBusCRT::getFecBusCRTFaultBrdDeviceCode(unsigned char aType) +{ + switch(aType){ + case 0: + case 7: + case 11: + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + break; + + case 1: + case 10: + FecBusCRTBufTemp.Data.DeviceCode = ftCtlCircuit; + break; + + case 2: + FecBusCRTBufTemp.Data.DeviceCode = ftBusCtlPanel; + break; + + case 3: + FecBusCRTBufTemp.Data.DeviceCode = ftDirCtlPanel; + break; + + case 4: + FecBusCRTBufTemp.Data.DeviceCode = ftCanNetworkComm; + break; + + case 5: + FecBusCRTBufTemp.Data.DeviceCode = ftMainPower; + break; + + case 6: + FecBusCRTBufTemp.Data.DeviceCode = ftStandbyPower; + break; + + case 8: + FecBusCRTBufTemp.Data.DeviceCode = ftBatChargeCircuit; + break; + + case 9: + FecBusCRTBufTemp.Data.DeviceCode = ftGraphShow; + break; + + default: + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + break; + } +} + +void TFecBusCRT::getFecBusCRTFaultBrdEventCode(unsigned char aType, unsigned char State) +{ + if(1 == State){ + switch(aType){ + case 0: + case 2: + case 3: + FecBusCRTBufTemp.Data.EventCode = evFault; + break; + + case 1: + FecBusCRTBufTemp.Data.EventCode = evFaultLoopTank; + break; + + case 4: + FecBusCRTBufTemp.Data.EventCode = evFaultCommunications; + break; + + case 5: + FecBusCRTBufTemp.Data.EventCode = evFaultMainPower; + break; + + case 6: + FecBusCRTBufTemp.Data.EventCode = evFaultSparePower; + break; + + case 7: + FecBusCRTBufTemp.Data.EventCode = evFaultCircuit; + break; + + case 8: + FecBusCRTBufTemp.Data.EventCode = evFaultCharge; + break; + + case 9: + case 10: + FecBusCRTBufTemp.Data.EventCode = evFaultCommunications; + break; + + default: + FecBusCRTBufTemp.Data.EventCode = evFault; + break; + } + }else{ + switch(aType){ + case 0: + case 2: + case 3: + FecBusCRTBufTemp.Data.EventCode = evFaultRecover; + break; + + case 1: + FecBusCRTBufTemp.Data.EventCode = evFaultLoopTankRecover; + break; + + case 4: + FecBusCRTBufTemp.Data.EventCode = evFaultCommunicationsRecover; + break; + + case 5: + FecBusCRTBufTemp.Data.EventCode = evFaultMainPowerRecover; + break; + + case 6: + FecBusCRTBufTemp.Data.EventCode = evFaultSparePowerRecover; + break; + + case 7: + FecBusCRTBufTemp.Data.EventCode = evFaultCircuitRecover; + break; + + case 8: + FecBusCRTBufTemp.Data.EventCode = evFaultChargeRecover; + break; + + case 9: + case 10: + FecBusCRTBufTemp.Data.EventCode = evFaultCommunicationsRecover; + break; + + default: + FecBusCRTBufTemp.Data.EventCode = evFaultRecover; + break; + } + } +} + +void TFecBusCRT::getFecBusCRTFaultDevDeviceCode(unsigned char aType) +{ + switch(aType){ + case 0: + case 1: + case 5: + case 14: + case 17: + case 18: + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + break; + + case 2: + FecBusCRTBufTemp.Data.DeviceCode = ftCtlCircuit; + break; + + case 3: + FecBusCRTBufTemp.Data.DeviceCode = ftBusCtlPanel; + break; + + case 4: + FecBusCRTBufTemp.Data.DeviceCode = ftDirCtlPanel; + break; + + case 6: + FecBusCRTBufTemp.Data.DeviceCode = ftDataMemCard; + break; + + case 7: + case 8: + case 19: + case 21: + case 22: + case 23: + FecBusCRTBufTemp.Data.DeviceCode = ftMainPower; + break; + + case 9: + case 10: + case 20: + case 24: + case 25: + case 26: + case 27: + FecBusCRTBufTemp.Data.DeviceCode = ftStandbyPower; + break; + + case 11: + case 12: + case 15: + case 16: + FecBusCRTBufTemp.Data.DeviceCode = ftCanNetworkComm; + break; + + case 13: + FecBusCRTBufTemp.Data.DeviceCode = ftGraphShow; + break; + + default: + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + break; + } +} + +void TFecBusCRT::getFecBusCRTFaultDevEventCode(unsigned char aType, unsigned char State) +{ + if(1 == State){ + switch(aType){ + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 14: + FecBusCRTBufTemp.Data.EventCode = evFault; + break; + + case 7: + case 19: + FecBusCRTBufTemp.Data.EventCode = evFaultMainPower; + break; + + case 8: + case 11: + case 12: + case 13: + case 15: + case 16: + case 21: + FecBusCRTBufTemp.Data.EventCode = evFaultCommunications; + break; + + case 9: + case 10: + case 20: + case 24: + case 25: + case 26: + case 27: + FecBusCRTBufTemp.Data.EventCode = evFaultSparePower; + break; + + case 22: + case 23: + FecBusCRTBufTemp.Data.EventCode = evFaultCircuit; + break; + + default: + FecBusCRTBufTemp.Data.EventCode = evUndefine; + break; + } + }else{ + switch(aType){ + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 14: + FecBusCRTBufTemp.Data.EventCode = evFaultRecover; + break; + + case 7: + case 19: + FecBusCRTBufTemp.Data.EventCode = evFaultMainPowerRecover; + break; + + case 8: + case 11: + case 12: + case 13: + case 15: + case 16: + case 21: + FecBusCRTBufTemp.Data.EventCode = evFaultCommunicationsRecover; + break; + + case 9: + case 10: + case 20: + case 24: + case 25: + case 26: + case 27: + FecBusCRTBufTemp.Data.EventCode = evFaultSparePowerRecover; + break; + + case 22: + case 23: + FecBusCRTBufTemp.Data.EventCode = evFaultCircuitRecover; + break; + + default: + FecBusCRTBufTemp.Data.EventCode = evUndefine; + break; + } + } +} + +void TFecBusCRT::iFecBusCRTFaultInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + + if(MainCtl.fData.Split.NetworkMode == 2)return; + if(GraphUsing == 0)return; + + FecBusCRTBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + + if((aRC.Splite.Data1 & 0xF0) == 0xC0){ + if((aRC.Splite.P1 >= dADDR_HANDPAD_START) && (aRC.Splite.P1 <= dADDR_HANDPAD_END)){ + FecBusCRTBufTemp.Data.UnitNum = aRC.Splite.P1; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + if(aData1)FecBusCRTBufTemp.Data.EventCode = evFaultCommunications; + else FecBusCRTBufTemp.Data.EventCode = evFaultCommunicationsRecover; + }else + if((aRC.Splite.P1 >= dADDR_DIRECTPAD_START) && (aRC.Splite.P1 <= dADDR_DIRECTPAD_END)){ + FecBusCRTBufTemp.Data.UnitNum = aRC.Splite.P1; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + if(aData1)FecBusCRTBufTemp.Data.EventCode = evFaultCommunications; + else FecBusCRTBufTemp.Data.EventCode = evFaultCommunicationsRecover; + } + }else + if((aRC.Splite.Data1 & 0xF0) == 0xD0){ + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + getFecBusCRTFaultDevDeviceCode(aData0); + getFecBusCRTFaultDevEventCode(aData0, aData1); + }else + if((aRC.Splite.Data1 & 0xF0) == 0xE0){ + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + FecBusCRTBufTemp.Data.DeviceCode = ftCtlCircuit; + if(aData1)FecBusCRTBufTemp.Data.EventCode = evFault; + else FecBusCRTBufTemp.Data.EventCode = evFaultRecover; + }else + if((aRC.Splite.Data1 & 0xF0) == 0xF0){ + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + getFecBusCRTFaultBrdDeviceCode(aData0); + getFecBusCRTFaultBrdEventCode(aData0, aData1); + }else{ + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + if((aP0 > 0)&&(aP0 < 40)){ + getFecBusCRTDeviceCode(dType); + }else + if((aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_START)){ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + } + + getFecBusCRTEpFaultEvent(aData0, aData1); + } + + getFecBusCRTTime(aRC); + getFecBusCRTStateCode(FecBusCRTStateCode); + + if(FecBusCRTBufTemp.Data.EventCode > 131)return; + if(1 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg06(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + }else + if(2 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg05(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + } +} + +void TFecBusCRT::iFecBusCRTFireInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + unsigned char IsFirst; + + if(MainCtl.fData.Split.NetworkMode == 2)return; + if(GraphUsing == 0)return; + + FecBusCRTBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + IsFirst = aRC.Splite.Data1; + + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + if((aP0)&&(aP0 <= 40)){ + getFecBusCRTDeviceCode(dType); + }else + if((aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END)){ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + }else{ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + } + + if(1 == IsFirst){ + FecBusCRTBufTemp.Data.EventCode = evFirstFireAlarm; + }else{ + FecBusCRTBufTemp.Data.EventCode = evFireAlarm; + } + + getFecBusCRTTime(aRC); + getFecBusCRTStateCode(FecBusCRTStateCode); + + if(FecBusCRTBufTemp.Data.EventCode > 131)return; + if(1 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg06(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + }else + if(2 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg05(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + } +} + +void TFecBusCRT::iFecBusCRTOperateInsert(TRecordCommon aRC) +{ + static unsigned int setHandAuto = 0x00; + + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char mType; + unsigned char aData0; + unsigned char aData1; + + if(MainCtl.fData.Split.NetworkMode == 2)return; + if(GraphUsing == 0)return; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + mType = aRC.Splite.mType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1; + + FecBusCRTBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + if(mType == etOperate){ + switch(aData0){ + case otPowerOff: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evSystemPowerOff; + break; + + case otPowerOn: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evSystemPowerOn; + break; + + case otReset: + if((MainCtl.fData.Split.NetworkMode != 2)&&(FecBusCRTBufTemp.Data.CtlNum == 1)){ + }else return; + + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evReset; + + //if((MainCtl.fData.Split.NetworkMode == 1)&&(FecBusCRTBufTemp.Data.CtlNum != 1))SendMaskFlag = 1; + break; + + case otMute: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evMuteBell; + break; + + case otMask: + FecBusCRTBufTemp.Data.UnitNum = aRC.Splite.P0; + FecBusCRTBufTemp.Data.DeviceNum = aRC.Splite.P1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evMask; + break; + + case otUnMask: + FecBusCRTBufTemp.Data.UnitNum = aRC.Splite.P0; + FecBusCRTBufTemp.Data.DeviceNum = aRC.Splite.P1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evMaskRelieve; + break; + + case otRegiste: + return; + break; + + case otUnRegiste: + return; + break; + + case otSetCanNetwork: + return; + break; + + case otCfgBoard: + return; + break; + + case otCfgCrt: + return; + break; + + case otCfgPriter: + return; + break; + + case otCfgDevice: + return; + break; + + case otCfgDateTime: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evAdjustClock; + break; + + case otCfgPermissionAllow: + return; + break; + + case otAllowSet: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + + if(setHandAuto != (aData1 & 0x01)){ + setHandAuto &=~0x01; + setHandAuto |=(aData1 & 0x01); + FecBusCRTBufTemp.Data.EventCode = evAutomatic; + }else + if(setHandAuto != (aData1 & 0x02)){ + setHandAuto &=~0x02; + setHandAuto |=(aData1 & 0x02); + FecBusCRTBufTemp.Data.EventCode = evManual; + } + break; + + case otAlramSetOnOff: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftAlramVaCircuit; + if(aData1){ + FecBusCRTBufTemp.Data.EventCode = evLaunch; + }else{ + FecBusCRTBufTemp.Data.EventCode = evShutoff; + } + break; + + case otBusPadOn: + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evLaunch; + break; + + case otBusPadOff: + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evShutoff; + break; + + case otDirectPadManualAllowOn: + return; + //--------------------------------------------------------------------------------- + //FillText4DirectPadManualAllowOn(); + break; + + case otDirectPadManualAllowOff: + return; + //--------------------------------------------------------------------------------- + //FillText4DirectPadManualAllowOff(); + break; + + case otDirectPadNodeOn: + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evLaunch; + break; + + case otDirectPadNodeOff: + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evShutoff; + break; + + case otUserCheck: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evKeyPressFunctionCheck; + break; + + case otLinkageGo: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evLaunchInrerLink; + break; + + case otSetNwTime: + case otReqNwTime: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evAdjustClock; + break; + + case otSelfCheck: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evSelfCheck; + break; + + case otSetManualAllowState: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evManual; + break; + + case otSetAutoAllowState: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evAutomatic; + break; + + case otRemoteSetManualAllowState: + return; + break; + + case otRemoteSetAutoAllowState: + return; + break; + + case otReportManualAllowState: + return; + break; + + case otReportAutoAllowState: + return; + break; + + case otFireConfirm: + case otFireRemoteConfirm: + case otFaultConfirm: + case otFaultRemoteConfirm: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + FecBusCRTBufTemp.Data.EventCode = evFaultOrFireAlarmExactly; + break; + + case otSetSmokeSensViaCircuit: + return; + break; + + case otSetSmokeSensViaAddr: + return; + break; + + case otCleanUp: + return; + break; + + case otLinkageExpsSaveRemove: + return; + break; + + case otBusPadModify: + return; + break; + + case otDirectPadModify: + return; + break; + + case otDescpModify: + return; + break; + + case otPassWdModify: + return; + break; + + case otRegisterByManual: + return; + break; + + case otAddRemoveNwCtl: + return; + break; + + case otRegCanNetwork: + return; + break; + + case otClearNetworkCfg: + return; + break; + + case otBroadcastVa: + return; + break; + + case otSetAllowState: + FecBusCRTBufTemp.Data.UnitNum = 0; + FecBusCRTBufTemp.Data.DeviceNum = 0; + FecBusCRTBufTemp.Data.ChannelNum = 0; + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + if(aData1 == 3)FecBusCRTBufTemp.Data.EventCode = evManual; + else if(aData1 == 1)FecBusCRTBufTemp.Data.EventCode = evAutomatic; + else if(aData1 == 2)FecBusCRTBufTemp.Data.EventCode = evManual; + else if(aData1 == 2)FecBusCRTBufTemp.Data.EventCode = evManual; + break; + } + } + + getFecBusCRTTime(aRC); + getFecBusCRTStateCode(FecBusCRTStateCode); + + if(FecBusCRTBufTemp.Data.EventCode > 131)return; + if(1 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg06(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + }else + if(2 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg05(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + } +} + +void TFecBusCRT::iFecBusCRTLinkageInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + unsigned char data; + + if(MainCtl.fData.Split.NetworkMode == 2)return; + if(GraphUsing == 0)return; + + FecBusCRTBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + data = aRC.Splite.iByte0; + + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + if( (aP0 >0) && (aP0 <=40) ){ + getFecBusCRTDeviceCode(dType); + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + }else{ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + } + + if(data == 0x01){ + FecBusCRTBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x02){ + FecBusCRTBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x03){ + FecBusCRTBufTemp.Data.EventCode = evFeedBack; + }else + if(data == 0x04){ + FecBusCRTBufTemp.Data.EventCode = evFeedBack; + }else + if(data == 0x05){ + FecBusCRTBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x06){ + FecBusCRTBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x07){ + return; + }else + if(data == 0xB1){ + FecBusCRTBufTemp.Data.EventCode = evShutoff; + }else + if(data == 0xB3){ + FecBusCRTBufTemp.Data.EventCode = evFeedBackRevoke; + }else + if(data == 0xB5){ + FecBusCRTBufTemp.Data.EventCode = evShutoff; + }else + if(data == 0xB6){ + FecBusCRTBufTemp.Data.EventCode = evShutoff; + }else + if(data == 0xB7){ + return; + } + + getFecBusCRTTime(aRC); + getFecBusCRTStateCode(FecBusCRTStateCode); + + if(FecBusCRTBufTemp.Data.EventCode > 131)return; + if(1 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg06(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + }else + if(2 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg05(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + } +} + +void TFecBusCRT::iFecBusCRTSvInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + + if(MainCtl.fData.Split.NetworkMode == 2)return; + if(GraphUsing == 0)return; + + FecBusCRTBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + + FecBusCRTBufTemp.Data.UnitNum = aP0; + FecBusCRTBufTemp.Data.DeviceNum = aP1; + FecBusCRTBufTemp.Data.ChannelNum = 0; + + if( (aP0 >0) && (aP0 <=40) ){ + getFecBusCRTDeviceCode(dType); + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + }else{ + FecBusCRTBufTemp.Data.DeviceCode = ftMainCtl; + } + + FecBusCRTBufTemp.Data.EventCode = evSuperVisory; + + getFecBusCRTTime(aRC); + getFecBusCRTStateCode(FecBusCRTStateCode); + + if(FecBusCRTBufTemp.Data.EventCode > 131)return; + if(1 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg06(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + }else + if(2 == EventCodePrm[FecBusCRTBufTemp.Data.EventCode]){ + iSetFecBusMsg05(&FecBusMsgUartTemp, &FecBusCRTBufTemp); + iFecBusMsgInsert(&FecBusMsgUartTemp); + } +} + +void TFecBusCRT::Task10Ms() +{ + static unsigned int TaskTick = 0; + TaskTick++; + if(TaskTick > 29){//300ms + TaskTick = 0; + oBufInsert(); + } + oBufProcess(); +} + +void TFecBusCRT::Task1000Ms() +{ + static TFecBusMsgUart ipMsg; + static TFecEventBufBody ipEvent; + static unsigned int send_tick; + + static unsigned int tick = 1; + + if(MainCtl.fData.Split.NetworkMode == 2)return; + if(GraphUsing == 0)return; + + ipEvent.Data.CtlNum = 1; + ipEvent.Data.UnitNum = 1;//单元编号（1字节） + ipEvent.Data.DeviceNum = tick; //设备编号（1字节） + ipEvent.Data.ChannelNum = 1; //通道编号（1字节） + + ipEvent.Data.DeviceCode = ftMainCtlFireLinkkage; //设备类型代码（2字节） + ipEvent.Data.EventCode = evFaultCommunications;//evFireAlarm; //事件代码（2字节） + + ipEvent.Data.StateCode.D16 = 1; //状态代码（2字节） + ipEvent.Data.Year = 24;//年（1字节） + ipEvent.Data.Mon = 8;//月（1字节） + + ipEvent.Data.Day = 3;//日（1字节） + ipEvent.Data.Hour = 12;//时（1字节） + ipEvent.Data.Min = 1;//分（1字节） + ipEvent.Data.Sec = 1;//秒（1字节） + + + send_tick++; + if(4 == send_tick){ + if(InTxIndex == OutTxIndex){ + iSetFecBusMsg00(&ipMsg);//sync heart + + iFecBusMsgInsert(&ipMsg); + } + }else + if(send_tick > 15){ + send_tick = 0; + /* + tick++;if(tick>2)tick=1; + iSetFecBusMsg06(&ipMsg,&ipEvent); + + iFecBusMsgInsert(&ipMsg); + */ + } + + ErrState.Body.OffLineTick++; + if(ErrState.Body.OffLineTick > 75){ + ErrState.Body.OffLineTick = 100; + ErrState.Body.OffLine = 1; + if(ErrReport.Body.OffLine == 0){ + //Report Here + ErrReport.Body.OffLine = 1; + CtlCenter.ieAddBrdFault(9, 9); + } + } + + UploadMask2CrtTask(); +} + +void TFecBusCRT::Upload2CrtTask(void) +{ + unsigned int PrcCount; + if(Upload.Active != 1)return; + if(MainCtl.fData.Split.NetworkMode == 2)return; + PrcCount = 0; + while(Upload.InxFire < CtlCenter.ieMsgFire.Count){ + TControlCenter::sFireGetViaIndex(Upload.InxFire, &EvMsg); + ShipMsg(); + iFecBusCRTFireInsert(Upload.aRc); + Upload.InxFire++; + if(PrcCount++ > 1000){ PrcCount =0; sys_error_led_task();} + } + while(Upload.InxStart < CtlCenter.ieMsgLinkage.Count){ + TControlCenter::sLinkageGetViaIndex(Upload.InxStart, &EvMsg); + ShipMsg(); + + if(Upload.aRc.Splite.mType == etLinkageStart){ + Upload.aRc.Splite.iByte0 = 0x01;//启动 + if(0x09 == Upload.aRc.Splite.Data0){ + Upload.aRc.Splite.iByte0 = 0xB1;//停止 + } + }else + if(Upload.aRc.Splite.mType == etLinkageFeedBack){ + Upload.aRc.Splite.iByte0 = 0x03; + } + + iFecBusCRTLinkageInsert(Upload.aRc); + Upload.InxStart++; + if(PrcCount++ > 1000){ PrcCount =0; sys_error_led_task();} + + } + while(Upload.InxSv < CtlCenter.ieMsgSv.Count){ + TControlCenter::sSvGetViaIndex(Upload.InxSv, &EvMsg); + ShipMsg(); + iFecBusCRTSvInsert(Upload.aRc); + Upload.InxSv++; + if(PrcCount++ > 1000){ PrcCount =0; sys_error_led_task();} + } + while(Upload.InxFault < CtlCenter.ieMsgFault.Count){ + TControlCenter::sFaultGetViaIndex(Upload.InxFault, &EvMsg); + ShipMsg(); + iFecBusCRTFaultInsert(Upload.aRc); + Upload.InxFault++; + if(PrcCount++ > 1000){ PrcCount =0; sys_error_led_task();} + } + while(Upload.InxMask < CtlCenter.ieMsgMask.Count){ + TControlCenter::sMaskGetViaIndex(Upload.InxMask, &EvMsg); + ShipMsg(); + Upload.aRc.Splite.mType = etOperate; + Upload.aRc.Splite.Data0 = otMask; + iFecBusCRTOperateInsert(Upload.aRc); + Upload.InxMask++; + if(PrcCount++ > 1000){ PrcCount =0; sys_error_led_task();} + } + Upload.Active = 0; + sys_error_led_task(); +} + +void TFecBusCRT::UploadMask2CrtTask(void) +{ + static unsigned int UploadTick = 0; + unsigned int PrcCount=0,Index=0; + + if(SendMaskFlag){ + UploadTick++; + if(UploadTick > 19){ + UploadTick = 0; + SendMaskFlag = 0; + if(1 == MainCtl.fData.Split.NetworkMode){ + while(Index < CtlCenter.ieMsgMask.Count){ + TControlCenter::sMaskGetViaIndex(Index, &EvMsg); + ShipMsg(); + Upload.aRc.Splite.mType = etOperate; + Upload.aRc.Splite.Data0 = otMask; + iFecBusCRTOperateInsert(Upload.aRc); + Index++; + if(PrcCount++ > 1000){ PrcCount =0; sys_error_led_task();} + } + } + } + }else{ + UploadTick = 0; + } +} + +void TFecBusCRT::ShipMsg() +{ + Upload.aRc.D32[0] = EvMsg.D32[0]; + Upload.aRc.D32[1] = EvMsg.D32[1]; + Upload.aRc.D32[2] = EvMsg.D32[2]; + Upload.aRc.D32[3] = EvMsg.D32[3]; +} + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/ProtoFecBusCRT.h b/MyCode/src/ProtoFecBusCRT.h new file mode 100644 index 0000000..8c6b7b2 --- /dev/null +++ b/MyCode/src/ProtoFecBusCRT.h @@ -0,0 +1,196 @@ +#ifndef PROTOFECBUSCRT_H_ +#define PROTOFECBUSCRT_H_ + +#include "gType.h" +#include "TDateTime.h" +#include "ProtoFecBus.h" +#include "record.h" +#include "Runtime.h" + +#define dFecCRT_BufCount_Tx 10240 +#define dFecCRT_BufEntrySize_Tx 96 + +#define FECBUS_HEAD 0x7E +#define FECBUS_END 0x7E + +typedef union{ + unsigned short D16; + unsigned char D8[2]; + struct{ + unsigned char LoByte; + unsigned char HiByte; + }body; +}TCrcValue; + +typedef union{ + unsigned int D32[24]; + unsigned char D8[96]; + struct{ + unsigned int avalibel; + unsigned int UsingMsgIndex; + unsigned int FrameNum; + unsigned int FrameTick; + union{ + unsigned int da32[5]; + unsigned char da8[20]; + struct{ + unsigned char Header; + unsigned char FrmType; + unsigned char DestAddr; + unsigned char Priority; + unsigned char SrcAddr; + unsigned char MsgIndex; + unsigned char FrmIndex; + unsigned char Dlen; + unsigned char DPFC[8]; //Data PlusIn Function Code + unsigned char CrcLoByte; + unsigned char CrcHiByte; + unsigned char Eop; + unsigned char rsv; + }body; + }Section[4]; + }Prm; +}TFecBusMsgUart; + +class TFecBusCRT{ + public: + unsigned int SendMaskFlag; + + TFecEventBufBody FecBusCRTBufTemp; + TFecBusMsgUart FecBusMsgUartTemp; + + unsigned int RxGetFlag; + TFecBusMsgUart RxMsg; + TFecAckCode RxMsgState; + + unsigned int TxSetFlag; + TFecBusMsgUart TxMsg; + + unsigned int InTxIndex; + unsigned int OutTxIndex; + //TFecBusMsgUart TxCRTEntryMsg; + + struct{ + unsigned char State; + unsigned char AckOk; + unsigned char OnGoing; + unsigned char Order; + unsigned char RetryTimes; + unsigned char RetryFLAG; + unsigned short TimeOutTick; + }OnTransmite; + + union{ + unsigned int D32; + struct{ + unsigned char OffLine; + unsigned char ReadWriteFail; + unsigned char OffLineTick; + unsigned char Rsv0; + }Body; + }ErrState, ErrReport; + + unsigned int OnlineTick; + + struct{ + unsigned int Active; + unsigned int InxFire; + unsigned int InxStart; + unsigned int InxSv; + unsigned int InxFault; + unsigned int InxMask; + TRecordCommon aRc; + }Upload; + + //unsigned int CrtActive; + //unsigned char LineType; + //unsigned char CrtNum; + + TEventMsg EvMsg; + + public: + TFecBusCRT(){}; + void Init(); + + void ResetCallBack(); + + void MsgFrmIndexInc(); + + unsigned short Crc16Data(unsigned char* pdata,unsigned int len); + unsigned int CheckCrc16(unsigned char* pdata,unsigned int len); + + void getFecBusCRTTime(TRecordCommon aRC); + void getFecBusCRTStateCode(unsigned short StateCode); + void setFecBusCRTStateCode(unsigned short StateCode); + + void SetStateCodeAll(); + void SetStateCodeAutoManual(); + void SetStateCodePsOnActive(); + void SetStateCodePsError(); + void SetStateCodeFire(); + void SetStateCodeStart(); + void SetStateCodeFeedBack(); + void SetStateCodeSv(); + void SetStateCodeFault(); + void SetStateCodeMask(); + + void getFecBusCRTDeviceCode(unsigned char dType); + + void getFecBusCRTEpFaultEvent(unsigned char aType, unsigned char State); + + void getFecBusCRTFaultBrdDeviceCode(unsigned char aType); + void getFecBusCRTFaultBrdEventCode(unsigned char aType, unsigned char State); + void getFecBusCRTFaultDevDeviceCode(unsigned char aType); + void getFecBusCRTFaultDevEventCode(unsigned char aType, unsigned char State); + + void oBufInsert(); + void iBufInsert(); + void iBufProcess(); + void oBufProcess(); + + void iFecBusBufInsert(unsigned char * pdata); + void iFecBusMsgInsert(TFecBusMsgUart * pMsg); + + void iSetFecBusBufEnd(TFecBusMsgUart * pMsg,unsigned char Priority); + void iSetFecBusMsg00(TFecBusMsgUart * pMsg); + void iSetFecBusMsg01(TFecBusMsgUart * pMsg, unsigned char aCtlNum); + void iSetFecBusMsg02(TFecBusMsgUart * pMsg, unsigned char aCtlNum); + void iSetFecBusMsg03(TFecBusMsgUart * pMsg, unsigned char aCtlNum); + void iSetFecBusMsg05(TFecBusMsgUart * pMsg, TFecEventBufBody * pEvent); + void iSetFecBusMsg06(TFecBusMsgUart * pMsg, TFecEventBufBody * pEvent); + void iSetFecBusMsg15(TFecBusMsgUart * pMsg); + + void setFecBusCRTMsg01(unsigned char aCtlNum); + void setFecBusCRTMsg02(unsigned char aCtlNum); + void setFecBusCRTMsg03(unsigned char aCtlNum); + void rpyFecBusCRTMsg15(void); + + //interface + void iFecBusCRTFireInsert(TRecordCommon aRC); + void iFecBusCRTFaultInsert(TRecordCommon aRC); + + void iFecBusCRTLinkageInsert(TRecordCommon aRC); + void iFecBusCRTOperateInsert(TRecordCommon aRC); + void iFecBusCRTSvInsert(TRecordCommon aRC); + //---< + void ShipMsg(); + + void oCmdInsert(); + + void Upload2CrtTask(void); + void UploadMask2CrtTask(void); + + void Task10Ms(); + void Task1000Ms(); +}; + +#endif + + + + + + + + + diff --git a/MyCode/src/ProtoInnerCan.cpp b/MyCode/src/ProtoInnerCan.cpp new file mode 100644 index 0000000..a5e9ef9 --- /dev/null +++ b/MyCode/src/ProtoInnerCan.cpp @@ -0,0 +1,2917 @@ +#include "ProtoInnerCan.h" +#include "gvalue.h" +#include "CnCpp.h" +#include "record.h" +#include "Runtime.h" + +extern "C" { + #include "fdcan_task.h" +} + +const unsigned char CmdActiveDefaultSet[256][10] = { + //0 + {0 , 0, 0, 0, 1, 1, FastCall,0,0,0}, + {cmSyncBeat, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmReset, 0, 0, 0, 1, 3, StdCall, 0,0,0}, + {cmMuteBell, 0, 0, 0, 1, 3, StdCall, 0,0,0}, + {cmSelfCheck, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBroadcastTime, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmInspection , 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + + //7 + {cmPublishAlram, 0, 0, 0, 1, 2, FastCall, etFire, 0, 0}, + {cmPublishPreAlram, 0, 0, 0, 1, 2, FastCall, etFire, 0, 0}, + {cmPublishPreAlramResume, 0, 0, 0, 1, 2, FastCall, etFire, 0, 0}, + {cmTakeChargeAlram, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0, 0}, + {cmTakeChargeAlramResume, 0, 0, 0, 1, 2, FastCall, etSuperViCancel, 0, 0}, + {cmConfirmAlram, 0, 0, 0, 1, 2, FastCall, etFire, 0, 0}, + {cmThresholdHiAlram, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0, 0}, + {cmThresholdLowAlram, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0, 0}, + //15 + {cmManualStart, 0, 0, 0, 1, 2, FastCall, etLinkageStart, 0x05, 0}, //(0x06 0xB6 手动声光启动 及停止) + {cmManualStop, 0, 0, 0, 1, 2, FastCall, etLinkageStartCancel, 0x05, 0}, + {cmAutoDelayStart, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0, 0}, + {cmAutoStart, 0, 0, 0, 1, 2, FastCall, etLinkageStart, 0x01, 0}, + {cmAutoStop, 0, 0, 0, 1, 2, FastCall, etLinkageStartCancel, 0xB1, 0}, + {cmAck, 0, 0, 0, 1, 2, FastCall, etLinkageFeedBack, 0x03, 0}, + {cmAckStop, 0, 0, 0, 1, 2, FastCall, etLinkageFeedBackCancel, 0xB3, 0}, + {cmAckMiss, 0, 0, 0, 1, 2, FastCall, etLinkageFeedBack, 0x04, 0}, + {cmAckHydrant, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0, 0}, + {cmAckFireAreaHydrant, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0, 0}, + //25 + {cmVAAlramStart, 0, 0, 0, 1, 2, FastCall, etLinkageStart, 0x06, 0}, + {cmVAAlramStop, 0, 0, 0, 1, 2, FastCall, etLinkageStartCancel, 0xB6, 0}, + {cmFireAreaVAAlramStart, 0, 0, 0, 1, 2, FastCall, 0, 0x10, 0}, + {cmFireAreaVAAlramStop, 0, 0, 0, 1, 2, FastCall, 0, 0x11, 0}, + {cmFireAreaStart, 0, 0, 0, 1, 2, FastCall, 0, 0x20, 0}, + {cmFireAreaStop, 0, 0, 0, 1, 2, FastCall, 0, 0x21, 0}, + //31 + {cmMainManualAutoState, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0,0}, + {cmDirCtlManualAutoState, 0, 0, 0, 1, 2, FastCall, etSuperVi, 0,0}, + //33 + {cmPortModuleErr, 0, 0, 0, 1, 2, FastCall, etFault, 0,0}, + {cmPortModuleErrRecover, 0, 0, 0, 1, 2, FastCall, etFaultCancel, 0,0}, + {cmCircuitErr, 0, 0, 0, 1, 2, FastCall, etFault, 0xE0,0}, + {cmOtherErr, 0, 0, 0, 1, 2, FastCall, etFault, 0xF0,0}, + {cmMainPowerErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x10,0}, + {cmBKPowerErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x20,0}, + {cmDC24PowerrErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x30,0}, + {cmBatteryPowerrErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x40,0}, + {cmGNDConnectErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x50,0}, + {cmTrialTimeUpErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x60,0}, + {xxcmOtherErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x70,0}, + {cmSYSErr, 0, 0, 0, 1, 2, FastCall, etFault, 0x80,0}, + + //45~53 + {cmAllPortAutoRegist, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmSinglePortAutoRegist, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmSinglePortAddrManualRegist,0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmClearAllRegist, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmClearSinglePortRegist, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmClearSinglePortAddrRegist, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmPortRegistProgress, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmPortRegistFinished, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmPortRegistAbort, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + + //54~66 + {cmQueryVer, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryPortReg, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryRunState, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryRuntimeData, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryStaticData, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryMacCode, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQuerySens, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryAnalogRawData, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryVoltage, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryPortRunParam, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryAbout, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryCmdConfirm, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryPortPowerSet, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + + //67~77 + {cmEpDeviceMask, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmEpDeviceMaskRemove, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmMaskRemoveAll, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmDeviceConfig, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmDeviceSetSens, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmDeviceSetLogicAddr, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmQueryDisplayPadAddrSegment,0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmSetDisplayPadAddrSegment, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmSetDisplayPadPositionInf, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmSendDisplayPadInf, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmAddDisplayPadAddrSegment, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //78~88 + {cmBusCtlPadConfig, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadAction, 0, 0, 0, 1, 1, StdCall, etBusPadAction,0,0}, + {cmBusCtlPadState, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadNoAck, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadAllAckOk, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadAckLack, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadAutoOnActive, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadAutoNotActive, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadConfigReq, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmBusCtlPadConfigReq, 0, 0, 0, 1, 1, StdCall, etBusPadRequst,0,0}, + {cmBusCtlPadManualState, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //89~97 + {cmDirectCtlPadConfig, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmDirectCtlPadAction , 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmDirectCtlPadSilence, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmDirectCtlPadManualState, 0, 0, 0, 1, 1, StdCall, etDirectPadAction,0,0}, + {cmDirectCtlPadChannelState, 0, 0, 0, 1, 1, StdCall, etDirectPadAction,0,0}, + {cmDirectCtlPadLinkageState, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmDirectCtlPadAutoNotActive, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmDirectPadConfigReq, 0, 0, 0, 1, 1, StdCall, etDirectPadRequst,0,0}, + {cmDirectCtlPadQueryPort, 0, 0, 0, 1, 1, StdCall, etDirectPadRequst,0,0}, + + //98~106 + {cmVIrtualAlram, 0, 0, 0, 1, 1, SimEvent, 0,0,0}, + {cmVIrtualAlramCancle, 0, 0, 0, 1, 1, SimEvent, 0,0,0}, + {cmVIrtualStart, 0, 0, 0, 1, 1, SimEvent, etLinkageStart, 0x01,0}, + {smVIrtualStop, 0, 0, 0, 1, 1, SimEvent, etLinkageStartCancel, 0xB1,0}, + {cmVIrtualAck, 0, 0, 0, 1, 1, SimEvent, etLinkageFeedBack, 0x03,0}, + {cmVIrtualAckStop, 0, 0, 0, 1, 1, SimEvent, etLinkageFeedBackCancel, 0xB3,0}, + {cm104, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cm105, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cm106, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //107~127 + {cmDevLightOn, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmDevMute, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmDuplicateAddrCheckStart, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmDuplicateAddrCheckPrg, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmDuplicateAddrData, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmDuplicateAddrCheckEnd, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {113, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {114, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {115, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmSetConfigAddrSegment, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmQueryStaticDataAddrSegment, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {cmDuplicateAddrEpDeviceLed, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {119, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmEnterAdjustMode, 0, 0, 0, 1, 1, StdCall, etDirectPadReport,0,0}, + {cmExitAdjustMode, 0, 0, 0, 1, 1, StdCall, etDirectPadReport,0,0}, + {122, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {123, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {124, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {125, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {126, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmCtrlPowerOn, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //128 + {128, 0, 0, 0, 1, 1, FastCall, etLinkageFeedBack, 0x07, 0}, //0x07 消钮应答亮灯 (0x06 0xB6 手动声光启动 及停止) + {129, 0, 0, 0, 1, 1, FastCall, etLinkageFeedBackCancel, 0xB7, 0}, //0xB7 消钮取消应答灭灯 + + //130~140 + {cmAlternatingSpeakerSL, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {131, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + {132, 0, 0, 0, 1, 1, StdCall, etConfig,0,0}, + {133, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {134, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {135, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {136, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {137, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {138, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {139, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmVIrtualSuperVi, 0, 0, 0, 1, 1, SimEvent, etSuperVi,0,0}, + + //141~150 + {141, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {142, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {143, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {144, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {145, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {146, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {147, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {148, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {149, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {cmQueryBoardModel, 0, 0, 0, 1, 1, StdCall, etReport,0,0}, + + //151~160 + {cmBusDataSyncRegisterReq, 0, 0, 0, 1, 1, PortSync, 0,0,0}, + {cmBusDataSyncRegister, 0, 0, 0, 1, 1, PortSync, 0,0,0}, + {cmBusDataSyncRegisterRes, 0, 0, 0, 1, 1, PortSync, 0,0,0}, + {cmBusDataSyncIsolationReq, 0, 0, 0, 1, 1, PortSync, 0,0,0}, + {cmBusDataSyncIsolation, 0, 0, 0, 1, 1, PortSync, 0,0,0}, + {cmBusDataSyncIsolationRes, 0, 0, 0, 1, 1, PortSync, 0,0,0}, + {157, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {158, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {159, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {160, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //161~170 + {141, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {142, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {143, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {144, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {145, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {146, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {147, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {148, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {149, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {150, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //171~180 + {141, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {142, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {143, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {144, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {145, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {146, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {147, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {148, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {149, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {150, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //181~190 + {141, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {142, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {143, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {144, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {145, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {146, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {147, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {148, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {149, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {150, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //191~200 + {141, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {142, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {143, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {144, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {145, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {146, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {147, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {148, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {149, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {150, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //201~210 + {201, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {202, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {dNetworkCmd_RemoteStartStopViaUserCodeSimulate, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {dNetworkCmd_AutoStartDelaySimulate, 0, 0, 0, 1, 1, SimEvent, 0,0,0}, + {dNetworkCmd_SendRegRpy, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {dNetworkCmd_SendRegSeq, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {dNetworkCmd_SetSlaveAllow, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {dNetworkCmd_AutoStartDelay, 0, 0, 0, 1, 1, FastCall, 0,0,0}, + {dNetworkCmd_NewTime, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {dNetworkCmd_RemoteStartStopViaUserCode, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + + //211~220 + {211, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {212, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {213, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {214, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {215, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {216, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {217, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {218, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {219, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {220, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //221~230 + {221, 0, 0, 0, 1, 1, StdCall, 0,0,0}, //Mask List Send + {222, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {223, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {224, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {225, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {226, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {227, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {228, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {229, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {230, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //231~240 + {231, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {232, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {233, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {234, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {235, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {236, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {237, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {238, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {239, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + {240, 0, 0, 0, 1, 1, StdCall, 0,0,0}, + + //241~250 + {241, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {242, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {243, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {244, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {245, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {246, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {247, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {248, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {249, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {250, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + + //251~255 + {251, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {252, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {253, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {254, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, + {255, 0, 0, 0, 1, 1, NetNormalCall, 0,0,0}, +}; + +int TInnerCan::CheckPathKissAss(unsigned char aP0, unsigned char aP1) +{ + if((aP0 == 0) || (aP1 == 0))return 1; + if( aP0 <= dPORT_MAX_COUNT){ + if(aP1 > dEP_MAX_COUNT_PER_PORT)return 1; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END )){ + if(aP1 > dDIRECTCTL_KEY_MAX_COUNT)return 1; + }else{ + return 1; + } + return 0; +} + +void TInnerCan::ProcRxMsg(void) +{ + unsigned char CtlByte, aP0, aP1, aP2, aMT, aDT, aCmd; + unsigned int i; + if(aRxMsg.Ava){ + aRxMsg.Ava = 0; + if(aRxMsg.Ide.BitF.dAddr == 0){ + if( (aRxMsg.Ide.BitF.sAddr > 0) && (aRxMsg.Ide.BitF.sAddr < 5) ){ + MotherBoard.NoReportTick[aRxMsg.Ide.BitF.sAddr -1] = 0; + } + } + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][6] == FastCall){ + CtlByte = aRxMsg.Data.D8[0]; + + Record.InnerMsgSetYear (0, DateTime.Date.Split.Year); + Record.InnerMsgSetMonth (0, DateTime.Date.Split.Month); + Record.InnerMsgSetDay (0, DateTime.Date.Split.Day); + Record.InnerMsgSetHour (0, DateTime.Time.Split.Hour); + Record.InnerMsgSetMinute (0, DateTime.Time.Split.Minute); + Record.InnerMsgSetSecond (0, DateTime.Time.Split.Second); + Record.InnerMsgSet_mType (0, CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7]); + Record.InnerMsgSet_CtlNum (0, MainCtl.fData.Split.MyNum ); //(0,aRxMsg.Data.D8[1]); + + if(aRxMsg.Ide.BitF.Cmd == cmPortModuleErr){ + if(CheckPathKissAss(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3]))return; + Record.InnerMsgSet_P0 (0,aRxMsg.Data.D8[2]); + Record.InnerMsgSet_P1 (0,aRxMsg.Data.D8[3]); + Record.InnerMsgSet_P2 (0,aRxMsg.Data.D8[6]); + Record.InnerMsgSet_dType (0,aRxMsg.Data.D8[5]); + Record.InnerMsgSet_Data0 (0,aRxMsg.Data.D8[6]); //Fault Type + Record.InnerMsgSet_Data1 (0,0x01); //Set + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + + GetEpUserCodeAreaNumDevType(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3], &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + }else + if(aRxMsg.Ide.BitF.Cmd == cmPortModuleErrRecover){ + if(CheckPathKissAss(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3]))return; + Record.InnerMsgSet_P0 (0,aRxMsg.Data.D8[2]); + Record.InnerMsgSet_P1 (0,aRxMsg.Data.D8[3]); + Record.InnerMsgSet_P2 (0,aRxMsg.Data.D8[6]); + Record.InnerMsgSet_dType (0,aRxMsg.Data.D8[5]); + Record.InnerMsgSet_Data0 (0,aRxMsg.Data.D8[6]); //Fault Type + Record.InnerMsgSet_Data1 (0,0x00); //Recover + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + + GetEpUserCodeAreaNumDevType(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3], &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + }else + if(aRxMsg.Ide.BitF.Cmd == cmCircuitErr){ + Record.InnerMsgSet_P0 (0,aRxMsg.Data.D8[2]); //Cir Index + Record.InnerMsgSet_P1 (0,0); + Record.InnerMsgSet_P2 (0,0); + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,0); + Record.InnerMsgSet_Data1 (0,aRxMsg.Data.D8[4] + 0xE0); //Is Set=1 Recover=0 + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + }else + if(aRxMsg.Ide.BitF.Cmd == cmOtherErr){ + Record.InnerMsgSet_P0 (0,0xE0); //Board Index + Record.InnerMsgSet_P1 (0,0); + Record.InnerMsgSet_P2 (0,aRxMsg.Data.D8[3]); //Fault Type + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,aRxMsg.Data.D8[3]); //Fault Type + Record.InnerMsgSet_Data1 (0,aRxMsg.Data.D8[4] + 0xF0); //Is Set=1 Recover=0 + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + }else{ + Record.InnerMsgSet_P0 (0,aRxMsg.Data.D8[2]); + Record.InnerMsgSet_P1 (0,aRxMsg.Data.D8[3]); + Record.InnerMsgSet_P2 (0,aRxMsg.Data.D8[4]); + Record.InnerMsgSet_dType (0,aRxMsg.Data.D8[5]); + Record.InnerMsgSet_Data0 (0,aRxMsg.Data.D8[6]); + Record.InnerMsgSet_Data1 (0,aRxMsg.Data.D8[7]); + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + + GetEpUserCodeAreaNumDevType(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3], &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + } + if( (aRxMsg.Ide.BitF.Cmd == cmPublishAlram) || (aRxMsg.Ide.BitF.Cmd == cmAutoStart) || (aRxMsg.Ide.BitF.Cmd == cmAutoStop) || + (aRxMsg.Ide.BitF.Cmd == cmAck) || (aRxMsg.Ide.BitF.Cmd == cmAckStop) || (aRxMsg.Ide.BitF.Cmd == cmAckHydrant) ){ + if(CheckPathKissAss(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3]))return; + } + if(Register.IsDevRegisting != 0x00A5A5A5){ + if(aRxMsg.Ide.BitF.Cmd == cmPublishAlram){ + if(CtlCenter.ieMsgFire.Count <1)Record.InnerMsgSet_Data1 (0,1); + else Record.InnerMsgSet_Data1 (0,0); + } + if( (aRxMsg.Ide.BitF.Cmd == cmAutoStart) || (aRxMsg.Ide.BitF.Cmd == cmAutoStop) || (aRxMsg.Ide.BitF.Cmd == cmAck) || (aRxMsg.Ide.BitF.Cmd == cmAckStop) ){ + Record.InnerMsgSet_Data1 (0,0); + } + CtlCenter.iePushOneMsg(Record.iMsgRx, aRxMsg.Ide.BitF.Cmd); + } + }else + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][6] == StdCall){ + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7] == etReport){ + CtlByte = InnerCan.aRxMsg.Data.D8[0]; + if(aRxMsg.Ide.BitF.Cmd == cmQueryRuntimeData){ + DevProperty.PushOneRealDataReport(aRxMsg.Data.D8[1], aRxMsg.Data.D8[2], aRxMsg.Data.D8[3], aRxMsg.Data.D8[4], aRxMsg.Data.D8[5], aRxMsg.Data.D8[6], aRxMsg.Data.D8[7]); + DevStartStop.PushOneRealDataReport(aRxMsg.Data.D8[1], aRxMsg.Data.D8[2], aRxMsg.Data.D8[3], aRxMsg.Data.D8[4], aRxMsg.Data.D8[5], aRxMsg.Data.D8[6], aRxMsg.Data.D8[7]); + }else + if(aRxMsg.Ide.BitF.Cmd == cmEpDeviceMask){ + DevMask.PushOneDataRec(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8[1], aRxMsg.Data.D8[2], aRxMsg.Data.D8[3]); + }else + if(aRxMsg.Ide.BitF.Cmd == cmEpDeviceMaskRemove){ + DevMask.PushOneDataRec(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8[1], aRxMsg.Data.D8[2], aRxMsg.Data.D8[3]); + }else + if(aRxMsg.Ide.BitF.Cmd == cmInspection){ + CtlCenter.PushInspecRpy(aRxMsg.Data.D8[1], aRxMsg.Data.D8[2]); + }else + if(aRxMsg.Ide.BitF.Cmd == cmSinglePortAddrManualRegist){ + RegisterManual.PushRecData(aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmDeviceSetSens){ + DevProperty.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmQuerySens){ + DevProperty.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + DevStartStop.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmDeviceConfig){ + DevProperty.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmQueryStaticData){ + DevProperty.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + DevStartStop.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmQueryMacCode){ + DevProperty.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmSetDisplayPadPositionInf){ + DisplayPadDescpDownload.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmSyncBeat){ + if(aRxMsg.Ide.BitF.dAddr == 0){ + if( (aRxMsg.Ide.BitF.sAddr > 0) && (aRxMsg.Ide.BitF.sAddr < 5) ){ + MotherBoard.NoReportTick[aRxMsg.Ide.BitF.sAddr -1] = 0; + } + } + }else + if(aRxMsg.Ide.BitF.Cmd == cmQueryBoardModel){ + HwInf.InnerCanPushData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmQueryVer){ + HwInf.InnerCanPushData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmDuplicateAddrCheckPrg){ + DuplicateCheck.InnerCanPushData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmDuplicateAddrData){ + DuplicateCheck.InnerCanPushData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmDuplicateAddrCheckEnd){ + DuplicateCheck.InnerCanPushData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmSetConfigAddrSegment){ + DevOutputCfg.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + DevSensitiveCfg.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + DevVaCfg.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(aRxMsg.Ide.BitF.Cmd == cmQueryStaticDataAddrSegment){ + DevOutputCfg.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + DevSensitiveCfg.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + DevVaCfg.PushInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + } + else + if(aRxMsg.Ide.BitF.Cmd == cmDeviceConfig){ + //DevOutputCfg + //DevSensitiveCfg + }else{ + Record.InnerMsgSetYear (0, DateTime.Date.Split.Year); + Record.InnerMsgSetMonth (0, DateTime.Date.Split.Month); + Record.InnerMsgSetDay (0, DateTime.Date.Split.Day); + Record.InnerMsgSetHour (0, DateTime.Time.Split.Hour); + Record.InnerMsgSetMinute (0, DateTime.Time.Split.Minute); + Record.InnerMsgSetSecond (0, DateTime.Time.Split.Second); + Record.InnerMsgSet_mType (0,CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7]); + Record.InnerMsgSet_CtlNum (0,MainCtl.fData.Split.MyNum ); //(0,aRxMsg.Data.D8[1]); + Record.InnerMsgSet_P0 (0,aRxMsg.Data.D8[2]); + Record.InnerMsgSet_P1 (0,aRxMsg.Data.D8[3]); + Record.InnerMsgSet_P2 (0,aRxMsg.Data.D8[4]); + Record.InnerMsgSet_dType (0,aRxMsg.Data.D8[5]); + Record.InnerMsgSet_Data0 (0,aRxMsg.Data.D8[6]); + Record.InnerMsgSet_Data1 (0,aRxMsg.Data.D8[7]); + Record.InnerMsgSet_iByte0 (0,CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][8]); + Record.InnerMsgSet_iByte1 (0,CtlByte); + + if(aRxMsg.Ide.BitF.Cmd == cmQueryPortReg ){ + Record.InnerMsgSet_CtlNum(0,aRxMsg.Data.D8[1]); + }else{ + GetEpUserCodeAreaNumDevType(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3], &Record.iMsgRx.Splite.UserCode, &Record.iMsgRx.Splite.AreaNum, &Record.iMsgRx.Splite.dType); + } + CtlCenter.iePushOneMsg(Record.iMsgRx, aRxMsg.Ide.BitF.Cmd); + } + }else + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7] == etBusPadAction){ + BusPadGoAction(aRxMsg.Data.D8[2], aRxMsg.Data.D8[3]); + }else + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7] == etBusPadRequst){ + if(aRxMsg.Ide.BitF.Cmd == cmBusCtlPadConfigReq){ + CtlCenter.DeviceRequest(cmBusCtlPadConfigReq, 0, aRxMsg.Data.D8[2]); + } + }else + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7] == etDirectPadAction){ + DirectUpLoad(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8); + }else + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7] == etDirectPadRequst){ + + }else + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][7] == etDirectPadReport){ + RunModeCfg.GetInnerCanData(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8[2]); + } + }else + if(CmdActiveDefaultSet[aRxMsg.Ide.BitF.Cmd][6] == PortSync){ + CtlCenter.ProcPortSyncCmd(aRxMsg.Ide.BitF.Cmd, aRxMsg.Data.D8[1], aRxMsg.Data.D8[2]); + } + } +} + +void TInnerCan::CmdSendReset() +{ + tData[0] = 0; tData[1] = 0; tData[2] = 0; tData[3] = 0; + tData[4] = 0; tData[5] = 0; tData[6] = 0; tData[7] = 0; + OBufInsert(1,cmReset,tData,1); +} + +void TInnerCan::OBufFastInsert(unsigned char Pri, unsigned char Cmd, unsigned char *Data, unsigned char Len) +{ + int i; + unsigned int aAddr; + OutBufFast.WriteIndex++; + if(OutBufFast.WriteIndex >= InnerFastTxBufCount)OutBufFast.WriteIndex = 0; + + OutBufFast.wBody.Ide.BitF.Pri = Pri & 0x03; + OutBufFast.wBody.Ide.BitF.sLvl = 1; + OutBufFast.wBody.Ide.BitF.dLvl = 7; + OutBufFast.wBody.Ide.BitF.sAddr = 0; + OutBufFast.wBody.Ide.BitF.dAddr = 127; + OutBufFast.wBody.Ide.BitF.Cmd = Cmd; + + OutBufFast.wBody.Dlc = Len; + for(i=0; i= InnerEventTxBufCount)OutBuf.WriteIndex = 0; + + OutBuf.wBody.Ide.BitF.Pri = Pri & 0x03; + OutBuf.wBody.Ide.BitF.sLvl = 1; + OutBuf.wBody.Ide.BitF.dLvl = 7; + OutBuf.wBody.Ide.BitF.sAddr = 0; + OutBuf.wBody.Ide.BitF.dAddr = 127; + OutBuf.wBody.Ide.BitF.Cmd = Cmd; + + OutBuf.wBody.Dlc = Len; + for(i=0; i= dADDR_DIRECTPAD_START) && ( aP0 <= dADDR_DIRECTPAD_END) && (aP1)){ + aP1--; + if(aP1 < dDIRECTCTL_KEY_MAX_COUNT){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + if(DirectCtlBoard[aP0].IsRegisted[aP1]){ + Record.FastBuf.Splite.Year = DateTime.Date.Split.Year; + Record.FastBuf.Splite.Month = DateTime.Date.Split.Month; + Record.FastBuf.Splite.Day = DateTime.Date.Split.Day; + Record.FastBuf.Splite.Hour = DateTime.Time.Split.Hour; + Record.FastBuf.Splite.Minute = DateTime.Time.Split.Minute; + Record.FastBuf.Splite.Second = DateTime.Time.Split.Second; + Record.FastBuf.Splite.PCtlNum = MainCtl.fData.Split.MyNum;; + Record.FastBuf.Splite.P0 = OutBuf.Body[OutBuf.ReadIndex].Data.D8[2]; + Record.FastBuf.Splite.P1 = OutBuf.Body[OutBuf.ReadIndex].Data.D8[3]; + Record.FastBuf.Splite.P2 = 0; + + Record.FastBuf.Splite.mType = etLinkageStart; + Record.FastBuf.Splite.iByte0 = 0x01; + + Record.FastBuf.Splite.Data1 = 0; + Record.LinkageAdd(Record.FastBuf); + CtlCenter.ieManualPushOneMsgLinkageStart(Record.FastBuf); + } + } + }*/ + }else + if( (aCmd == 128) || (aCmd == 129) ){ + Record.InnerMsgSetYear (0, DateTime.Date.Split.Year); + Record.InnerMsgSetMonth (0, DateTime.Date.Split.Month); + Record.InnerMsgSetDay (0, DateTime.Date.Split.Day); + Record.InnerMsgSetHour (0, DateTime.Time.Split.Hour); + Record.InnerMsgSetMinute (0, DateTime.Time.Split.Minute); + Record.InnerMsgSetSecond (0, DateTime.Time.Split.Second); + Record.InnerMsgSet_mType (0, etLinkageFeedBack); + Record.InnerMsgSet_CtlNum (0, MainCtl.fData.Split.MyNum ); //(0,aRxMsg.Data.D8[1]); + + Record.InnerMsgSet_P0 (0,254); + Record.InnerMsgSet_P1 (0,254); + Record.InnerMsgSet_P2 (0,254); + + Record.InnerMsgSet_dType (0,0); + Record.InnerMsgSet_Data0 (0,0); + Record.InnerMsgSet_Data1 (0,0); + + Record.InnerMsgSet_iByte0(0,CmdActiveDefaultSet[aCmd][8]); + if(aCmd == 128){ + CtlCenter.iePushOneMsgLinkageFb(Record.iMsgRx); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); + Record.LinkageAdd(Record.iMsgRx); + }else{ + CtlCenter.iePushOneMsgLinkageFbCancel(Record.iMsgRx); + ExRecord.SetStateCodeFeedBack(); + FecBusCRT.SetStateCodeFeedBack(); + Record.LinkageAdd(Record.iMsgRx); + } + } +} + +int TInnerCan::CheckOutBufFastFinish() +{ + unsigned int aAddr; + if(OutBufFast.ReadIndex != OutBufFast.WriteIndex){ + if(get_can_tx_complete()){ + OutBufFast.ReadIndex++; + if(OutBufFast.ReadIndex >=InnerFastTxBufCount)OutBufFast.ReadIndex =0; + + aAddr = dAddrSdram_InnerCanFastOut + (OutBufFast.ReadIndex * 16); + OutBufFast.rBody.Ide.D32 = *(volatile unsigned int *)(aAddr); + OutBufFast.rBody.Data.D32[0] = *(volatile unsigned int *)(aAddr+4); + OutBufFast.rBody.Data.D32[1] = *(volatile unsigned int *)(aAddr+8); + OutBufFast.rBody.Dlc = *(volatile unsigned int *)(aAddr+12); + if(OutBufFast.rBody.Ide.BitF.Cmd == cmBroadcastTime){ + tData[0] = 0; + tData[1] = MainCtl.fData.Split.MyNum; + tData[2] = DateTime.Date.Split.Year; + tData[3] = DateTime.Date.Split.Month; + tData[4] = DateTime.Date.Split.Day; + tData[5] = DateTime.Time.Split.Hour; + tData[6] = DateTime.Time.Split.Minute; + tData[7] = DateTime.Time.Split.Second; + internal_can_send_data(OutBufFast.rBody.Ide.D32, tData, 8); + }else{ + internal_can_send_data(OutBufFast.rBody.Ide.D32, OutBufFast.rBody.Data.D8, OutBufFast.rBody.Dlc); + } + } + return 0; + }else{ + return 1; + } +} + +void TInnerCan::OBufCheckSend() +{ + unsigned int aAddr; + if(get_can_tx_complete()){ + if(OutBufFast.ReadIndex != OutBufFast.WriteIndex){ + OutBufFast.ReadIndex++; + if(OutBufFast.ReadIndex >=InnerFastTxBufCount)OutBufFast.ReadIndex =0; + + aAddr = dAddrSdram_InnerCanFastOut + (OutBufFast.ReadIndex * 16); + OutBufFast.rBody.Ide.D32 = *(volatile unsigned int *)(aAddr); + OutBufFast.rBody.Data.D32[0] = *(volatile unsigned int *)(aAddr+4); + OutBufFast.rBody.Data.D32[1] = *(volatile unsigned int *)(aAddr+8); + OutBufFast.rBody.Dlc = *(volatile unsigned int *)(aAddr+12); + if(OutBufFast.rBody.Ide.BitF.Cmd == cmBroadcastTime){ + tData[0] = 0; + tData[1] = MainCtl.fData.Split.MyNum; + tData[2] = DateTime.Date.Split.Year; + tData[3] = DateTime.Date.Split.Month; + tData[4] = DateTime.Date.Split.Day; + tData[5] = DateTime.Time.Split.Hour; + tData[6] = DateTime.Time.Split.Minute; + tData[7] = DateTime.Time.Split.Second; + internal_can_send_data(OutBufFast.rBody.Ide.D32, tData, 8); + }else{ + internal_can_send_data(OutBufFast.rBody.Ide.D32, OutBufFast.rBody.Data.D8, OutBufFast.rBody.Dlc); + } + }else + if(OutBuf.ReadIndex != OutBuf.WriteIndex){ + OutBuf.ReadIndex++; + if(OutBuf.ReadIndex >=InnerEventTxBufCount)OutBuf.ReadIndex =0; + + aAddr = dAddrSdram_InnerCan + (OutBuf.ReadIndex * 16); + OutBuf.rBody.Ide.D32 = *(volatile unsigned int *)(aAddr); + OutBuf.rBody.Data.D32[0] = *(volatile unsigned int *)(aAddr+4); + OutBuf.rBody.Data.D32[1] = *(volatile unsigned int *)(aAddr+8); + OutBuf.rBody.Dlc = *(volatile unsigned int *)(aAddr+12); + if(OutBuf.rBody.Ide.BitF.Cmd == cmBroadcastTime){ + tData[0] = 0; + tData[1] = MainCtl.fData.Split.MyNum; + tData[2] = DateTime.Date.Split.Year; + tData[3] = DateTime.Date.Split.Month; + tData[4] = DateTime.Date.Split.Day; + tData[5] = DateTime.Time.Split.Hour; + tData[6] = DateTime.Time.Split.Minute; + tData[7] = DateTime.Time.Split.Second; + internal_can_send_data(OutBuf.rBody.Ide.D32, tData, 8); + }else{ + internal_can_send_data(OutBuf.rBody.Ide.D32, OutBuf.rBody.Data.D8, OutBuf.rBody.Dlc); + //OBufPrcRecordAndEvent(); + } + }else + if(Buf4GuiSend.Inx_Out != Buf4GuiSend.Inx_In){ + Buf4GuiSend.Inx_Out++; + if(Buf4GuiSend.Inx_Out >= Buf4GuiInxMax)Buf4GuiSend.Inx_Out = 0; + internal_can_send_data(Buf4GuiSend.Body[Buf4GuiSend.Inx_Out].Ide.D32, Buf4GuiSend.Body[Buf4GuiSend.Inx_Out].Da, Buf4GuiSend.Body[Buf4GuiSend.Inx_Out].Len); + } + } +} + +void TInnerCan::CmdSendCustom(TCanHeaderID aIde, unsigned char *p, unsigned int aLen) +{ + internal_can_send_data(aIde.D32, p, aLen); +} + +unsigned int TInnerCan::CmdSendCustomWithReturn(TCanHeaderID aIde, unsigned char *p, unsigned int aLen) +{ + return internal_can_send_data(aIde.D32, p, aLen); +} + +void TInnerCan::BusPadGoAction(unsigned char P0, unsigned char aKeyNum) +{ + unsigned char aP0; + if( (P0>=dADDR_HANDPAD_START) && (P0 <= dADDR_HANDPAD_END) ){ + if( (aKeyNum >0) && (aKeyNum <= dHANDCTL_KEY_MAX_COUNT) ){ + aP0 = P0 - dADDR_HANDPAD_START; + HandCtlBoard[aP0].KeyPress(MainCtl.fData.Split.MyNum, aP0+1, aKeyNum); + } + } +} + +void TInnerCan::DirectUpLoad(unsigned char aCmd, unsigned char *Data) +{ + unsigned char aP0; + if(aCmd == cmDirectCtlPadManualState){ + aP0 = Data[2]; + if( (aP0>=dADDR_DIRECTPAD_START) && (aP0<=dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + DirectCtlBoard[aP0].dUploadAllowState(MainCtl.fData.Split.MyNum, aP0, Data[3]); + } + }else + if(aCmd == cmDirectCtlPadChannelState){ + aP0 = Data[2]; + if( (aP0>=dADDR_DIRECTPAD_START) && (aP0<=dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + DirectCtlBoard[aP0].dUploadNodeState(MainCtl.fData.Split.MyNum, aP0, Data[3], Data[4]); + } + } +} + +void TInnerCan::DirectRequest(unsigned char aCmd, unsigned char *Data) +{ + unsigned char aP0; + if(aCmd == cmBusCtlPadConfigReq){ + aP0 = Data[1]; + if( (aP0>=dADDR_DIRECTPAD_START) && (aP0<=dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + DirectCtlBoard[aP0].SendPadCfg2Pad(aP0); + } + }else + if(aCmd == cmDirectCtlPadQueryPort){ + aP0 = Data[2]; + if( (aP0>=dADDR_DIRECTPAD_START) && (aP0<=dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + } + } +} + +void TInnerCan::TaskSecondUpdate() +{ + if( (DateTime.Time.Split.Minute == 4 ) && + (DateTime.Time.Split.Second == 5 ) ){ + tData[0] = 0; + tData[1] = MainCtl.fData.Split.MyNum; + tData[2] = DateTime.Date.Split.Year; + tData[3] = DateTime.Date.Split.Month; + tData[4] = DateTime.Date.Split.Day; + tData[5] = DateTime.Time.Split.Hour; + tData[6] = DateTime.Time.Split.Minute; + tData[7] = DateTime.Time.Split.Second; + OBufInsert(1,cmBroadcastTime,tData,8); + } +} + +void TInnerCan::ForceSecondUpdate() +{ + tData[0] = 0; + tData[1] = MainCtl.fData.Split.MyNum; + tData[2] = DateTime.Date.Split.Year; + tData[3] = DateTime.Date.Split.Month; + tData[4] = DateTime.Date.Split.Day; + tData[5] = DateTime.Time.Split.Hour; + tData[6] = DateTime.Time.Split.Minute; + tData[7] = DateTime.Time.Split.Second; + OBufInsert(1,cmBroadcastTime,tData,8); +} + +void TInnerCan::LoadPreset(unsigned char aCmd) +{ + aTxMsg.Ide.BitF.Cmd = aCmd; + aTxMsg.Data.D8[0] = CmdActiveDefaultSet[aCmd][3]; + aTxMsg.DelayMs = CmdActiveDefaultSet[aCmd][4]; + aTxMsg.Ide.BitF.Pri = CmdActiveDefaultSet[aCmd][5]; +} + +void TInnerCan::SetTarget(u8 aPathLevel) +{ + aTxMsg.Ide.BitF.sLvl = 1; + aTxMsg.Ide.BitF.sAddr = 0; + aTxMsg.Ide.BitF.dAddr = 127; //set Bost, if need, will be Overwrite + if(aPathLevel < 10){ + aTxMsg.Ide.BitF.dLvl = aPathLevel; + }else + if(aPathLevel < 100){ + if(aPathLevel == 12) aTxMsg.Ide.BitF.dLvl = 5; + if(aPathLevel == 23) aTxMsg.Ide.BitF.dLvl = 4; + }else{ + aTxMsg.Ide.BitF.dLvl = 7; + } + aTxMsg.Dlc = 1; +} + +void TInnerCan::SetTarget(u8 aPathLevel, unsigned char Path1) +{ + SetTarget(aPathLevel); + aTxMsg.Ide.BitF.dAddr = Path1; + aTxMsg.Data.D8[1] = Path1; + aTxMsg.Dlc = 2; +} + +void TInnerCan::SetTarget(u8 aPathLevel, unsigned char Path1, unsigned char Path2) +{ + SetTarget(aPathLevel,Path1); + aTxMsg.Data.D8[2] = Path2; + aTxMsg.Dlc = 3; +} + +void TInnerCan::SetTarget(u8 aPathLevel, unsigned char Path1, unsigned char Path2, unsigned char Path3) +{ + SetTarget(aPathLevel,Path1, Path2); + aTxMsg.Data.D8[3] = Path3; + aTxMsg.Dlc = 4; +} + +void TInnerCan::SendCmdPowerOnFast() +{ + unsigned char Data[8]; + + Data[0] = 0; + Data[1] = MainCtl.fData.Split.MyNum; + Data[2] = 0; + Data[3] = 0; + Data[4] = 0; + Data[5] = 0; + Data[6] = 0; + + OBufFastInsert(0, cmCtrlPowerOn, Data, 1); +} + +void TInnerCan::GetEpUserCodeAreaNumDevType(unsigned char aP0, unsigned char aP1, unsigned int *pUc, unsigned short *pAreaNum, unsigned char *pDevType) +{ + if(aP0 ==0){*pUc =0; *pAreaNum =0; *pDevType = 0; return;} + if(aP1 ==0){*pUc =0; *pAreaNum =0; *pDevType = 0; return;} + + if(aP0 <= dPORT_MAX_COUNT){ + if(aP1 >dEP_MAX_COUNT_PER_PORT){*pUc =0; *pAreaNum =0; *pDevType = 0; return;} + aP0--; aP1--; + *pUc = Port[aP0].UcList[aP1].Full; + *pAreaNum = Port[aP0].Area[aP1]; + if(Port[aP0].AssignType[aP1]){ + *pDevType = Port[aP0].AssignType[aP1]; + }else{ + if(Port[aP0].ExistTable[aP1] == 0xA5){ + *pDevType = Port[aP0].dTypeTable[aP1]; + }else{ + *pDevType = 0; + } + } + }else{ + *pUc = 0; + *pAreaNum = 0; + *pDevType = 0; + } +} + +void TInnerCan::SendCmdBroadcastFast(unsigned char aCdt) +{ + unsigned char Data[8]; + + Data[0] = 0; + Data[1] = aCdt; + Data[2] = 0; + Data[3] = 0; + Data[4] = 0; + Data[5] = 0; + Data[6] = 0; + + OBufFastInsert(0, cmAlternatingSpeakerSL, Data, 2); +} + +void TInnerCan::SendCmdClearRegData() +{ + unsigned char Data[8]; + //0x00 0xFE 0x7F 0x5A 0xA5 0x26 0x82 0x79 + + Data[0] = 0; + Data[1] = 0xFE; + Data[2] = 0x7F; + Data[3] = 0x5A; + Data[4] = 0xA5; + Data[5] = 0x26; + Data[6] = 0x82; + Data[7] = 0x79; + + OBufFastInsert(0, cmClearAllRegist, Data, 8); +} + +void TInnerCan::SendCmdMaskRemoveAll() +{ + unsigned char Data[8]; + //0x00 0xXX + Data[0] = 0; + OBufFastInsert(0, cmMaskRemoveAll, Data, 1); +} + +//f state set--------------------------------------------> +/* +void TInnerCan::fStateSetHandPadChannel(u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_HAND_CTL_CHANNEL; + aTxMsg.Data.D8[2] = aOnOff; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetHandPadChannel(u8 aPath1, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_HAND_CTL_CHANNEL; + aTxMsg.Data.D8[3] = aOnOff; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetHandPadChannel(u8 aPath1, u8 aPath2, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_HAND_CTL_CHANNEL; + aTxMsg.Data.D8[4] = aOnOff; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetDirectCtlChannel(u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_DIRECT_CTL_CHANNEL; + aTxMsg.Data.D8[2] = aOnOff; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetDirectCtlChannel(u8 aPath1, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_DIRECT_CTL_CHANNEL; + aTxMsg.Data.D8[3] = aOnOff; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetDirectCtlChannel(u8 aPath1, u8 aPath2, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_DIRECT_CTL_CHANNEL; + aTxMsg.Data.D8[4] = aOnOff; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetPort(u8 aIntv1, u8 aIntv2) +{ + LoadPreset(cmStateSetByType); + SetTarget(1); + aTxMsg.Data.D8[1] = dgTYPE_PORT; + aTxMsg.Data.D8[2] = aIntv1; + aTxMsg.Data.D8[3] = aIntv2; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetPort(u8 aPath1, u8 aIntv1, u8 aIntv2) +{ + LoadPreset(cmStateSetByType); + SetTarget(1,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_PORT; + aTxMsg.Data.D8[3] = aIntv1; + aTxMsg.Data.D8[4] = aIntv2; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetMotherBoard(u8 aLocalInterLinkSelfRun) +{ + LoadPreset(cmStateSetByType); + SetTarget(1); + aTxMsg.Data.D8[1] = dgTYPE_MOTHER_BOARD; + aTxMsg.Data.D8[2] = aLocalInterLinkSelfRun; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetMotherBoard(u8 aPath1, u8 aLocalInterLinkSelfRun) +{ + LoadPreset(cmStateSetByType); + SetTarget(1,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_MOTHER_BOARD; + aTxMsg.Data.D8[3] = aLocalInterLinkSelfRun; + aTxMsg.Dlc = 4; +} + +void TInnerCan::fStateSetCommBoard(u8 aEn1, u8 aEn2, u8 aEn3, u8 aEn4) +{ + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = aEn1; + Fbit8.BitF.Bit1 = aEn2; + Fbit8.BitF.Bit2 = aEn3; + Fbit8.BitF.Bit3 = aEn4; + + LoadPreset(cmStateSetByType); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_COMM_MULTI; + aTxMsg.Data.D8[2] = Fbit8.D8; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetCommBoard(u8 aPath1, u8 aEn1, u8 aEn2, u8 aEn3, u8 aEn4) +{ + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = aEn1; + Fbit8.BitF.Bit1 = aEn2; + Fbit8.BitF.Bit2 = aEn3; + Fbit8.BitF.Bit3 = aEn4; + + LoadPreset(cmStateSetByType); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_COMM_MULTI; + aTxMsg.Data.D8[3] = Fbit8.D8; + aTxMsg.Dlc = 4; +} + +void TInnerCan::fStateSetDisplayPad(u8 IsShow, u8 BackLightOnOff, u8 BeepOnOff, u8 IndexLongShow, u8 IndexShortShow) +{ + //IndexLongShow : Mask Value = 0xFF; + //IndexShortShow : Mask Value = 0xFF; + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = IsShow; + Fbit8.BitF.Bit1 = BackLightOnOff; + Fbit8.BitF.Bit2 = BeepOnOff; + + LoadPreset(cmStateSetByType); + SetTarget(123); + aTxMsg.Data.D8[1] = dgTYPE_DISPLAY_PAD_I; + aTxMsg.Data.D8[2] = Fbit8.D8; + aTxMsg.Data.D8[3] = IndexLongShow; + aTxMsg.Data.D8[4] = IndexShortShow; + aTxMsg.Dlc = 5; +} +void TInnerCan::fStateSetDisplayPad(u8 aPath1, u8 IsShow, u8 BackLightOnOff, u8 BeepOnOff, u8 IndexLongShow, u8 IndexShortShow) +{ + //IndexLongShow : Mask Value = 0xFF; + //IndexShortShow : Mask Value = 0xFF; + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = IsShow; + Fbit8.BitF.Bit1 = BackLightOnOff; + Fbit8.BitF.Bit2 = BeepOnOff; + + LoadPreset(cmStateSetByType); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_DISPLAY_PAD_I; + aTxMsg.Data.D8[3] = Fbit8.D8; + aTxMsg.Data.D8[4] = IndexLongShow; + aTxMsg.Data.D8[5] = IndexShortShow; + aTxMsg.Dlc = 6; +} +void TInnerCan::fStateSetDisplayPad(u8 aPath1, u8 aPath2, u8 IsShow, u8 BackLightOnOff, u8 BeepOnOff, u8 IndexLongShow, u8 IndexShortShow) +{ + //IndexLongShow : Mask Value = 0xFF; + //IndexShortShow : Mask Value = 0xFF; + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = IsShow; + Fbit8.BitF.Bit1 = BackLightOnOff; + Fbit8.BitF.Bit2 = BeepOnOff; + + LoadPreset(cmStateSetByType); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_DISPLAY_PAD_I; + aTxMsg.Data.D8[4] = Fbit8.D8; + aTxMsg.Data.D8[5] = IndexLongShow; + aTxMsg.Data.D8[6] = IndexShortShow; + aTxMsg.Dlc = 7; +} + +void TInnerCan::fStateSetIsoOutput(u8 aGroupOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(123); + aTxMsg.Data.D8[1] = dgTYPE_OUT_MODULE; + aTxMsg.Data.D8[2] = aGroupOnOff; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetIsoOutput(u8 aPath1, u8 aGroupOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(3,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_OUT_MODULE; + aTxMsg.Data.D8[3] = aGroupOnOff; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetIsoOutput(u8 aPath1, u8 aPath2, u8 aGroupOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(3,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_OUT_MODULE; + aTxMsg.Data.D8[4] = aGroupOnOff; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetIsoInOut(u8 aGroupOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_OUT_MODULE; + aTxMsg.Data.D8[2] = aGroupOnOff; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetIsoInOut(u8 aPath1, u8 aGroupOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_INOUT_MODULE; + aTxMsg.Data.D8[3] = aGroupOnOff; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetIsoInOut(u8 aPath1, u8 aPath2, u8 aGroupOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_INOUT_MODULE; + aTxMsg.Data.D8[4] = aGroupOnOff; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetVaAlram(u8 aBellOnOff, u8 aLightOnOff) +{ + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = aBellOnOff; + Fbit8.BitF.Bit1 = aLightOnOff; + + LoadPreset(cmStateSetByType); + SetTarget(12); + aTxMsg.Data.D8[1] = dgType_VAALRAM; + aTxMsg.Data.D8[2] = Fbit8.D8; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetVaAlram(u8 aPath1, u8 aBellOnOff, u8 aLightOnOff) +{ + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = aBellOnOff; + Fbit8.BitF.Bit1 = aLightOnOff; + + LoadPreset(cmStateSetByType); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgType_VAALRAM; + aTxMsg.Data.D8[3] = Fbit8.D8; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetVaAlram(u8 aPath1, u8 aPath2, u8 aBellOnOff, u8 aLightOnOff) +{ + Tu8BitFiled Fbit8; + Fbit8.BitF.Bit0 = aBellOnOff; + Fbit8.BitF.Bit1 = aLightOnOff; + + LoadPreset(cmStateSetByType); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgType_VAALRAM; + aTxMsg.Data.D8[4] = Fbit8.D8; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetBroke(u8 aBroke) +{ + LoadPreset(cmStateSetByType); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_BUS_BROKE; + aTxMsg.Data.D8[2] = aBroke; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetBroke(u8 aPath1, u8 aBroke) +{ + LoadPreset(cmStateSetByType); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_BUS_BROKE; + aTxMsg.Data.D8[3] = aBroke; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetBroke(u8 aPath1, u8 aPath2, u8 aBroke) +{ + LoadPreset(cmStateSetByType); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_BUS_BROKE; + aTxMsg.Data.D8[4] = aBroke; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetExtCurrentSensor(u8 aEnable) +{ + LoadPreset(cmStateSetByType); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_EXTCURRENT_SENSOR_CHANNEL; + aTxMsg.Data.D8[2] = aEnable; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetExtCurrentSensor(u8 aPath1, u8 aEnable) +{ + LoadPreset(cmStateSetByType); + SetTarget(12, aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_EXTCURRENT_SENSOR_CHANNEL; + aTxMsg.Data.D8[3] = aEnable; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetExtCurrentSensor(u8 aPath1, u8 aPath2, u8 aEnable) +{ + LoadPreset(cmStateSetByType); + SetTarget(2, aPath1, aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_EXTCURRENT_SENSOR_CHANNEL; + aTxMsg.Data.D8[4] = aEnable; + aTxMsg.Dlc = 5; +} + +void TInnerCan::fStateSetIsoOutputChannel(u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(123); + aTxMsg.Data.D8[1] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[2] = aOnOff; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetIsoOutputChannel(u8 aPath1, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(123,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[3] = aOnOff; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(23,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[4] = aOnOff; + aTxMsg.Dlc = 5; +} +void TInnerCan::fStateSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(3,aPath1,aPath2,aPath3); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = aPath3; + aTxMsg.Data.D8[4] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[5] = aOnOff; + aTxMsg.Dlc = 6; +} + +void TInnerCan::fStateSetIsoInOutChannel(u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(3); + aTxMsg.Data.D8[1] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[2] = aOnOff; + aTxMsg.Dlc = 3; +} +void TInnerCan::fStateSetIsoInOutChannel(u8 aPath1, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(3,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[3] = aOnOff; + aTxMsg.Dlc = 4; +} +void TInnerCan::fStateSetIsoInOutChannel(u8 aPath1, u8 aPath2, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(3,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[4] = aOnOff; + aTxMsg.Dlc = 5; +} +void TInnerCan::fStateSetIsoInOutChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aOnOff) +{ + LoadPreset(cmStateSetByType); + SetTarget(3,aPath1,aPath2,aPath3); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = aPath3; + aTxMsg.Data.D8[4] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[5] = aOnOff; + aTxMsg.Dlc = 6; +} + +//f ParameterSet +void TInnerCan::fParameterSetHandPadChannel(u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_HAND_CTL_CHANNEL; + aTxMsg.Data.D8[2] = aAssignType; + aTxMsg.Data.D8[3] = aAssignRank; + aTxMsg.Dlc = 4; +} +void TInnerCan::fParameterSetHandPadChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_HAND_CTL_CHANNEL; + aTxMsg.Data.D8[3] = aAssignType; + aTxMsg.Data.D8[4] = aAssignRank; + aTxMsg.Dlc = 5; +} +void TInnerCan::fParameterSetHandPadChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_HAND_CTL_CHANNEL; + aTxMsg.Data.D8[4] = aAssignType; + aTxMsg.Data.D8[5] = aAssignRank; + aTxMsg.Dlc = 6; +} + +void TInnerCan::fParameterSetDirectCtlChannel(u8 aAssignType, u8 aAssignRank, u8 aCLow, u8 aCHi) +{ + //aCLow aCHi 0=Ignore, 0=Default + LoadPreset(cmDevParameterWrite); + SetTarget(2); + aTxMsg.Data.D8[1] = dgTYPE_DIRECT_CTL_CHANNEL; + aTxMsg.Data.D8[2] = aAssignType; + aTxMsg.Data.D8[3] = aAssignRank; + aTxMsg.Data.D8[4] = aCLow; + aTxMsg.Data.D8[5] = aCHi; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetDirectCtlChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank, u8 aCLow, u8 aCHi) +{ + //aCLow aCHi 0=Ignore, 0=Default + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_DIRECT_CTL_CHANNEL; + aTxMsg.Data.D8[3] = aAssignType; + aTxMsg.Data.D8[4] = aAssignRank; + aTxMsg.Data.D8[5] = aCLow; + aTxMsg.Data.D8[6] = aCHi; + aTxMsg.Dlc = 7; +} +void TInnerCan::fParameterSetDirectCtlChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank, u8 aCLow, u8 aCHi) +{ + //aCLow aCHi 0=Ignore, 0=Default + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_DIRECT_CTL_CHANNEL; + aTxMsg.Data.D8[4] = aAssignType; + aTxMsg.Data.D8[5] = aAssignRank; + aTxMsg.Data.D8[6] = aCLow; + aTxMsg.Data.D8[7] = aCHi; + aTxMsg.Dlc = 8; +} + +void TInnerCan::fParameterSetPort(u8 aSubItemCount, u8 aBrokeCurrent, u8 aShortCurrent, u8 aVLow) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(1); + aTxMsg.Data.D8[1] = dgTYPE_PORT; + aTxMsg.Data.D8[2] = aSubItemCount; + aTxMsg.Data.D8[3] = aBrokeCurrent; + aTxMsg.Data.D8[4] = aShortCurrent; + aTxMsg.Data.D8[5] = aVLow; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetPort(u8 aPath1, u8 aSubItemCount, u8 aBrokeCurrent, u8 aShortCurrent, u8 aVLow) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(1,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_PORT; + aTxMsg.Data.D8[3] = aSubItemCount; + aTxMsg.Data.D8[4] = aBrokeCurrent; + aTxMsg.Data.D8[5] = aShortCurrent; + aTxMsg.Data.D8[6] = aVLow; + aTxMsg.Dlc = 7; +} + +void TInnerCan::fParameterSetMotherBoard(u8 aSubItemCount) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(1); + aTxMsg.Data.D8[1] = dgTYPE_MOTHER_BOARD; + aTxMsg.Data.D8[2] = aSubItemCount; + aTxMsg.Dlc = 3; +} +void TInnerCan::fParameterSetMotherBoard(u8 aPath1, u8 aSubItemCount) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(1,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_MOTHER_BOARD; + aTxMsg.Data.D8[3] = aSubItemCount; + aTxMsg.Dlc = 4; +} + +void TInnerCan::fParameterSetCommBoardChannel(u8 aPath1, u8 aChannel, u8 aCommType, u8 aSpeed, u8 aFerture) +{ + //aFerture = BIt0..3 Bits Bit4..5 Stop Bits Bit6..7 Parity + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aChannel); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aChannel; + aTxMsg.Data.D8[3] = dgTYPE_COMM_CHANNEL; + aTxMsg.Data.D8[4] = aCommType; + aTxMsg.Data.D8[5] = aSpeed; + aTxMsg.Data.D8[6] = aFerture; + aTxMsg.Dlc = 7; +} + +void TInnerCan::fParameterSetDisplayPad(u8 IsDefaultShow, u8 IndexLongShow, u8 IndexShortShow, u8 aIntv) +{ + // Mask Value = 0xFF; + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_DISPLAY_PAD_I; + aTxMsg.Data.D8[2] = IsDefaultShow; + aTxMsg.Data.D8[3] = IndexLongShow; + aTxMsg.Data.D8[4] = IndexShortShow; + aTxMsg.Data.D8[5] = aIntv; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetDisplayPad(u8 aPath1, u8 IsDefaultShow, u8 IndexLongShow, u8 IndexShortShow, u8 aIntv) +{ + // Mask Value = 0xFF; + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_DISPLAY_PAD_I; + aTxMsg.Data.D8[3] = IsDefaultShow; + aTxMsg.Data.D8[4] = IndexLongShow; + aTxMsg.Data.D8[5] = IndexShortShow; + aTxMsg.Data.D8[6] = aIntv; + aTxMsg.Dlc = 7; +} +void TInnerCan::fParameterSetDisplayPad(u8 aPath1, u8 aPath2, u8 IsDefaultShow, u8 IndexLongShow, u8 IndexShortShow, u8 aIntv) // Mask Value = 0xFF; +{ + // Mask Value = 0xFF; + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_DISPLAY_PAD_I; + aTxMsg.Data.D8[4] = IsDefaultShow; + aTxMsg.Data.D8[5] = IndexLongShow; + aTxMsg.Data.D8[6] = IndexShortShow; + aTxMsg.Data.D8[7] = aIntv; + aTxMsg.Dlc = 8; +} + +void TInnerCan::fParameterSetIsoInput(u8 aSens1, u8 aSens2, u8 aSens3, u8 aSens4) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_IN_MODULE; + aTxMsg.Data.D8[2] = aSens1; + aTxMsg.Data.D8[3] = aSens2; + aTxMsg.Data.D8[4] = aSens3; + aTxMsg.Data.D8[5] = aSens4; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetIsoInput(u8 aPath1, u8 aSens1, u8 aSens2, u8 aSens3, u8 aSens4) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_IN_MODULE; + aTxMsg.Data.D8[3] = aSens1; + aTxMsg.Data.D8[4] = aSens2; + aTxMsg.Data.D8[5] = aSens3; + aTxMsg.Data.D8[6] = aSens4; + aTxMsg.Dlc = 7; +} +void TInnerCan::fParameterSetIsoInput(u8 aPath1, u8 aPath2, u8 aSens1, u8 aSens2, u8 aSens3, u8 aSens4) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_IN_MODULE; + aTxMsg.Data.D8[4] = aSens1; + aTxMsg.Data.D8[5] = aSens2; + aTxMsg.Data.D8[6] = aSens3; + aTxMsg.Data.D8[7] = aSens4; + aTxMsg.Dlc = 8; +} + +void TInnerCan::fParameterSetIsoInputChannel(u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(123); + aTxMsg.Data.D8[1] = dgTYPE_IN_CHANNEL; + aTxMsg.Data.D8[2] = aAssignType; + aTxMsg.Data.D8[3] = aAssignRank; + aTxMsg.Dlc = 4; +} +void TInnerCan::fParameterSetIsoInputChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(123,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_IN_CHANNEL; + aTxMsg.Data.D8[3] = aAssignType; + aTxMsg.Data.D8[4] = aAssignRank; + aTxMsg.Dlc = 5; +} +void TInnerCan::fParameterSetIsoInputChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(123,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_IN_CHANNEL; + aTxMsg.Data.D8[4] = aAssignType; + aTxMsg.Data.D8[5] = aAssignRank; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetIsoInputChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(123,aPath1,aPath2,aPath3); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = aPath3; + aTxMsg.Data.D8[4] = dgTYPE_IN_CHANNEL; + aTxMsg.Data.D8[5] = aAssignType; + aTxMsg.Data.D8[6] = aAssignRank; + aTxMsg.Dlc = 7; +} + +void TInnerCan::fParameterSetIsoOutput(u8 aThreshold1, u8 aThreshold2, u8 aThreshold3, u8 aThreshold4) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_OUT_MODULE; + aTxMsg.Data.D8[2] = aThreshold1; + aTxMsg.Data.D8[3] = aThreshold2; + aTxMsg.Data.D8[4] = aThreshold3; + aTxMsg.Data.D8[5] = aThreshold4; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetIsoOutput(u8 aPath1, u8 aThreshold1, u8 aThreshold2, u8 aThreshold3, u8 aThreshold4) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_OUT_MODULE; + aTxMsg.Data.D8[3] = aThreshold1; + aTxMsg.Data.D8[4] = aThreshold2; + aTxMsg.Data.D8[5] = aThreshold3; + aTxMsg.Data.D8[6] = aThreshold4; + aTxMsg.Dlc = 7; +} +void TInnerCan::fParameterSetIsoOutput(u8 aPath1, u8 aPath2, u8 aThreshold1, u8 aThreshold2, u8 aThreshold3, u8 aThreshold4) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_OUT_MODULE; + aTxMsg.Data.D8[4] = aThreshold1; + aTxMsg.Data.D8[5] = aThreshold2; + aTxMsg.Data.D8[6] = aThreshold3; + aTxMsg.Data.D8[7] = aThreshold4; + aTxMsg.Dlc = 8; +} + +void TInnerCan::fParameterSetIsoOutputChannel(u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(123); + aTxMsg.Data.D8[1] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[2] = aAssignType; + aTxMsg.Data.D8[3] = aAssignRank; + aTxMsg.Dlc = 5; +} +void TInnerCan::fParameterSetIsoOutputChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(123,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[3] = aAssignType; + aTxMsg.Data.D8[4] = aAssignRank; + aTxMsg.Dlc = 5; +} +void TInnerCan::fParameterSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(23,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[4] = aAssignType; + aTxMsg.Data.D8[5] = aAssignRank; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aAssignType, u8 aAssignRank) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(3,aPath1,aPath2,aPath3); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = aPath3; + aTxMsg.Data.D8[4] = dgTYPE_OUT_CHANNEL; + aTxMsg.Data.D8[5] = aAssignType; + aTxMsg.Data.D8[6] = aAssignRank; + aTxMsg.Dlc = 7; +} + +void TInnerCan::fParameterSetIsoInOut(u8 aSens1, u8 aSens2, u8 aThreshold1, u8 aThreshold2) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_INOUT_MODULE; + aTxMsg.Data.D8[2] = aSens1; + aTxMsg.Data.D8[3] = aSens2; + aTxMsg.Data.D8[4] = aThreshold1; + aTxMsg.Data.D8[5] = aThreshold2; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetIsoInOut(u8 aPath1, u8 aSens1, u8 aSens2, u8 aThreshold1, u8 aThreshold2) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_INOUT_MODULE; + aTxMsg.Data.D8[3] = aSens1; + aTxMsg.Data.D8[4] = aSens2; + aTxMsg.Data.D8[5] = aThreshold1; + aTxMsg.Data.D8[6] = aThreshold2; + aTxMsg.Dlc = 7; +} +void TInnerCan::fParameterSetIsoInOut(u8 aPath1, u8 aPath2, u8 aSens1, u8 aSens2, u8 aThreshold1, u8 aThreshold2) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_INOUT_MODULE; + aTxMsg.Data.D8[4] = aSens1; + aTxMsg.Data.D8[5] = aSens2; + aTxMsg.Data.D8[6] = aThreshold1; + aTxMsg.Data.D8[7] = aThreshold2; + aTxMsg.Dlc = 8; +} + +void TInnerCan::fParameterSetVaAlram() +{ + //No Any Function +} + +void TInnerCan::fParameterSetBroke(u8 aBrokeCurrent, u8 aTimeDelay) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_BUS_BROKE; + aTxMsg.Data.D8[2] = aBrokeCurrent; + aTxMsg.Data.D8[3] = aTimeDelay; + aTxMsg.Dlc = 4; +} +void TInnerCan::fParameterSetBroke(u8 aPath1, u8 aBrokeCurrent, u8 aTimeDelay) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_BUS_BROKE; + aTxMsg.Data.D8[3] = aBrokeCurrent; + aTxMsg.Data.D8[4] = aTimeDelay; + aTxMsg.Dlc = 5; +} +void TInnerCan::fParameterSetBroke(u8 aPath1, u8 aPath2, u8 aBrokeCurrent, u8 aTimeDelay) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_BUS_BROKE; + aTxMsg.Data.D8[4] = aBrokeCurrent; + aTxMsg.Data.D8[5] = aTimeDelay; + aTxMsg.Dlc = 6; +} + +void TInnerCan::fParameterSetExtCurrentSensor(u8 aCRatio, u8 aLowThreshold, u8 aHiThreshold) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_EXTCURRENT_SENSOR_CHANNEL; + aTxMsg.Data.D8[2] = aCRatio; + aTxMsg.Data.D8[3] = aLowThreshold; + aTxMsg.Data.D8[4] = aHiThreshold; + aTxMsg.Dlc = 5; +} +void TInnerCan::fParameterSetExtCurrentSensor(u8 aPath1, u8 aCRatio, u8 aLowThreshold, u8 aHiThreshold) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_EXTCURRENT_SENSOR_CHANNEL; + aTxMsg.Data.D8[3] = aCRatio; + aTxMsg.Data.D8[4] = aLowThreshold; + aTxMsg.Data.D8[5] = aHiThreshold; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetExtCurrentSensor(u8 aPath1, u8 aPath2, u8 aCRatio, u8 aLowThreshold, u8 aHiThreshold) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_EXTCURRENT_SENSOR_CHANNEL; + aTxMsg.Data.D8[4] = aCRatio; + aTxMsg.Data.D8[5] = aLowThreshold; + aTxMsg.Data.D8[6] = aHiThreshold; + aTxMsg.Dlc = 7; +} + +void TInnerCan::fParameterSetSmoke(u8 Sens, u8 aTimeDelay, u8 A, u8 B) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12); + aTxMsg.Data.D8[1] = dgTYPE_SMOKE_DETECTOR_I; + aTxMsg.Data.D8[2] = Sens; + aTxMsg.Data.D8[3] = aTimeDelay; + aTxMsg.Data.D8[4] = A; + aTxMsg.Data.D8[5] = B; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetSmoke(u8 aPath1, u8 Sens, u8 aTimeDelay, u8 A, u8 B) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(12,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_SMOKE_DETECTOR_I; + aTxMsg.Data.D8[3] = Sens; + aTxMsg.Data.D8[4] = aTimeDelay; + aTxMsg.Data.D8[5] = A; + aTxMsg.Data.D8[6] = B; + aTxMsg.Dlc = 7; +} +void TInnerCan::fParameterSetSmoke(u8 aPath1, u8 aPath2, u8 Sens, u8 aTimeDelay, u8 A, u8 B) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_SMOKE_DETECTOR_I; + aTxMsg.Data.D8[4] = Sens; + aTxMsg.Data.D8[5] = aTimeDelay; + aTxMsg.Data.D8[6] = A; + aTxMsg.Data.D8[7] = B; + aTxMsg.Dlc = 8; +} + +void TInnerCan::fParameterSetTempe(u8 aThreshold1, u8 aThreshold2, u8 aIndex) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2); + aTxMsg.Data.D8[1] = dgTYPE_TEMPE_DETECTOR_I; + aTxMsg.Data.D8[2] = aThreshold1; + aTxMsg.Data.D8[3] = aThreshold2; + aTxMsg.Data.D8[4] = aIndex; + aTxMsg.Dlc = 5; +} +void TInnerCan::fParameterSetTempe(u8 aPath1, u8 aThreshold1, u8 aThreshold2, u8 aIndex) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = dgTYPE_TEMPE_DETECTOR_I; + aTxMsg.Data.D8[3] = aThreshold1; + aTxMsg.Data.D8[4] = aThreshold2; + aTxMsg.Data.D8[5] = aIndex; + aTxMsg.Dlc = 6; +} +void TInnerCan::fParameterSetTempe(u8 aPath1, u8 aPath2, u8 aThreshold1, u8 aThreshold2, u8 aIndex) +{ + LoadPreset(cmDevParameterWrite); + SetTarget(2,aPath1,aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = dgTYPE_TEMPE_DETECTOR_I; + aTxMsg.Data.D8[4] = aThreshold1; + aTxMsg.Data.D8[5] = aThreshold2; + aTxMsg.Data.D8[6] = aIndex; + aTxMsg.Dlc = 7; +} +*/ + +//CMD ------------------> + +unsigned int TInnerCan::CmdSyncBeat(void) +{ + LoadPreset(cmSyncBeat); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdReset() +{ + LoadPreset(cmReset); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdMuteBell() +{ + LoadPreset(cmMuteBell); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdSelfCheck() +{ + LoadPreset(cmSelfCheck); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdBroadcastTime() +{ + LoadPreset(cmBroadcastTime); + SetTarget(123); + aTxMsg.Data.D8[1] = 0; + aTxMsg.Data.D8[2] = 0; + aTxMsg.Data.D8[3] = 0; + aTxMsg.Data.D8[4] = 0; + aTxMsg.Data.D8[5] = 0; + aTxMsg.Data.D8[6] = 0; + aTxMsg.Dlc += 6; + return 0; +} + +unsigned int TInnerCan::CmdInspection() +{ + LoadPreset(cmInspection); + SetTarget(123); + return 0; +} + + +//Reg------------> +/* +unsigned int TInnerCan::CmdRegCheckDeviceExist(u8 aPath1) +{ + LoadPreset(cmRegCheckDeviceExist); + SetTarget(1,aPath1); + return 0; +} +unsigned int TInnerCan::CmdRegCheckDeviceExist(u8 aPath1, u8 aPath2) +{ + LoadPreset(cmRegCheckDeviceExist); + SetTarget(12,aPath1,aPath2); + return 0; +} +unsigned int TInnerCan::CmdRegCheckDeviceExist(u8 aPath1, u8 aPath2, u8 aPath3) +{ + LoadPreset(cmRegCheckDeviceExist); + SetTarget(12, aPath1, aPath2, aPath3); + return 0; +} + +unsigned int TInnerCan::CmdRegRescanDevList(u8 aPath1) +{ + LoadPreset(cmRegRescanDevList); + SetTarget(1,aPath1); + return 0; +} + +unsigned int TInnerCan::CmdRegQueryRescanDevListDone(u8 aPath1) +{ + LoadPreset(cmRegQueryRescanDevListDone); + SetTarget(1,aPath1); + return 0; +} + +unsigned int TInnerCan::CmdRegRequstDeviceList(u8 aPath1) +{ + LoadPreset(cmRegRequstDeviceList); + SetTarget(1,aPath1); + return 0; +} +//Reg <--------------- + +//Adj Mode-----------> +unsigned int TInnerCan::CmdAdjustModeEnter() +{ + LoadPreset(cmAdjustModeEnter); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdAdjustModeExit() +{ + LoadPreset(cmAdjustModeExit); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdAdjustModeCompare(u8 aActiveOrNot) +{ + LoadPreset(cmAdjustModeCompare); + SetTarget(123); + aTxMsg.Data.D8[1] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdAdjustModeCompareCancel() +{ + LoadPreset(cmAdjustModeCompareCancel); + SetTarget(123); + return 0; +} +//Adj Mode <------------- + +unsigned int TInnerCan::CmdManualAllow() +{ + LoadPreset(cmManualAllow); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdManualNotAllow() +{ + LoadPreset(cmManualNotAllow); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdManualCompareAllow(u8 aActiveOrNot) +{ + LoadPreset(cmManualCompareAllow); + SetTarget(123); + aTxMsg.Data.D8[1] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdManualCompareAllowCancel() +{ + LoadPreset(cmManualCompareAllowCancel); + SetTarget(123); + return 0; +} + +//自动 +unsigned int TInnerCan::CmdAutoAllow() +{ + LoadPreset(cmAutoAllow); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdAutoNotAllow() +{ + LoadPreset(cmAutoNotAllow); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdAutoCompareAllow(u8 aActiveOrNot) +{ + LoadPreset(cmAutoCompareAllow); + SetTarget(123); + aTxMsg.Data.D8[1] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdAutoCompareAllowCancel() +{ + LoadPreset(cmAutoCompareAllowCancel); + SetTarget(123); + return 0; +} + +//喷洒设定 mode +unsigned int TInnerCan::CmdSplashAllow() +{ + LoadPreset(cmSplashAllow); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdSplashNotAllow() +{ + LoadPreset(cmSplashNotAllow); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdSplashCompare(u8 aActiveOrNot) +{ + LoadPreset(cmSplashCompare); + SetTarget(123); + aTxMsg.Data.D8[1] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdSplashCompareCancel() +{ + LoadPreset(cmSplashCompareCancel); + SetTarget(123); + return 0; +} + +//屏蔽 +unsigned int TInnerCan::CmdMaskAll() +{ + LoadPreset(cmMaskAll); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdMaskAllRecover() +{ + LoadPreset(cmMaskAllRecover); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdMaskTypeDevice(u8 aPath1, u8 aType) +{ + LoadPreset(cmMaskTypeDevice); + SetTarget(1,aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskTypeDevice(u8 aPath1,u8 aPath2, u8 aType) +{ + LoadPreset(cmMaskTypeDevice); + SetTarget(12, aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskTypeDevice(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType) +{ + LoadPreset(cmMaskTypeDevice); + SetTarget(123, aPath1, aPath2, aPath3); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskTypeDeviceRecover(u8 aPath1, u8 aType) +{ + LoadPreset(cmMaskTypeDeviceRecover); + SetTarget(1,aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskTypeDeviceRecover(u8 aPath1,u8 aPath2, u8 aType) +{ + LoadPreset(cmMaskTypeDeviceRecover); + SetTarget(12, aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskTypeDeviceRecover(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType) +{ + LoadPreset(cmMaskTypeDeviceRecover); + SetTarget(123, aPath1, aPath2, aPath3); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMask(u8 aPath1) +{ + LoadPreset(cmMask); + SetTarget(1, aPath1); + return 0; +} + +unsigned int TInnerCan::CmdMask(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmMask); + SetTarget(2, aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdMask(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmMask); + SetTarget(3, aPath1, aPath2, aPath3); + return 0; +} + +unsigned int TInnerCan::CmdMaskRecover(u8 aPath1) +{ + LoadPreset(cmMaskRecover); + SetTarget(1, aPath1); + return 0; +} + +unsigned int TInnerCan::CmdMaskRecover(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmMaskRecover); + SetTarget(2, aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdMaskRecover(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmMaskRecover); + SetTarget(3, aPath1, aPath2, aPath3); + return 0; +} + +unsigned int TInnerCan::CmdMaskAllTemp() +{ + LoadPreset(cmMaskAllTemp); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdMaskAllTempRecover() +{ + LoadPreset(cmMaskAllTempRecover); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdMaskStateCompare(u8 aPath1, u8 aActiveOrNot) +{ + LoadPreset(cmMaskStateCompare); + SetTarget(123, aPath1); + aTxMsg.Data.D8[2] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskStateCompare(u8 aPath1,u8 aPath2, u8 aActiveOrNot) +{ + LoadPreset(cmMaskStateCompare); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskStateCompare(u8 aPath1,u8 aPath2,u8 aPath3, u8 aActiveOrNot) +{ + LoadPreset(cmMaskStateCompare); + SetTarget(3, aPath1, aPath2, aPath3); + aTxMsg.Data.D8[4] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdMaskStateCompareRecover(u8 aPath1) +{ + LoadPreset(cmMaskStateCompareRecover); + SetTarget(123, aPath1); + return 0; +} + +unsigned int TInnerCan::CmdMaskStateCompareRecover(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmMaskStateCompareRecover); + SetTarget(23, aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdMaskStateCompareRecover(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmMaskStateCompareRecover); + SetTarget(3, aPath1, aPath2, aPath3); + return 0; +} + +//按类激活或取消火报状态 +unsigned int TInnerCan::CmdFireAlramSetTypeActive(u8 aType) +{ + LoadPreset(cmFireAlramSetTypeActive); + SetTarget(123); + aTxMsg.Data.D8[1] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetTypeActive(u8 aPath1, u8 aType) +{ + LoadPreset(cmFireAlramSetTypeActive); + SetTarget(123, aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetTypeActive(u8 aPath1,u8 aPath2, u8 aType) +{ + LoadPreset(cmFireAlramSetTypeActive); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetTypeActive(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType) +{ + LoadPreset(cmFireAlramSetTypeDeActive); + SetTarget(3, aPath1, aPath2, aPath2); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetTypeDeActive(u8 aType) +{ + LoadPreset(cmFireAlramSetTypeDeActive); + SetTarget(123); + aTxMsg.Data.D8[1] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetTypeDeActive(u8 aPath1, u8 aType) +{ + LoadPreset(cmFireAlramSetTypeDeActive); + SetTarget(123, aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetTypeDeActive(u8 aPath1,u8 aPath2, u8 aType) +{ + LoadPreset(cmFireAlramSetTypeDeActive); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetTypeDeActive(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType) +{ + LoadPreset(cmFireAlramSetTypeDeActive); + SetTarget(3, aPath1, aPath2, aPath2); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByType(u8 aType, u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByType); + SetTarget(123); + aTxMsg.Data.D8[1] = aType; + aTxMsg.Data.D8[2] = aActiveOrNot; + aTxMsg.Dlc += 2; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByType(u8 aPath1, u8 aType, u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByType); + SetTarget(123,aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Data.D8[3] = aActiveOrNot; + aTxMsg.Dlc += 2; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByType(u8 aPath1,u8 aPath2, u8 aType, u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByType); + SetTarget(23,aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Data.D8[4] = aActiveOrNot; + aTxMsg.Dlc += 2; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByType(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType, u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByType); + SetTarget(3,aPath1, aPath2, aPath3); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Data.D8[5] = aActiveOrNot; + aTxMsg.Dlc += 2; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetActive() +{ + LoadPreset(cmFireAlramSetActive); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetActive(u8 aPath1) +{ + LoadPreset(cmFireAlramSetActive); + SetTarget(123,aPath1); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetActive(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmFireAlramSetActive); + SetTarget(23,aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetActive(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmFireAlramSetActive); + SetTarget(3,aPath1, aPath2, aPath3); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetDeActive() +{ + LoadPreset(cmFireAlramSetDeActive); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetDeActive(u8 aPath1) +{ + LoadPreset(cmFireAlramSetDeActive); + SetTarget(123,aPath1); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetDeActive(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmFireAlramSetDeActive); + SetTarget(23,aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramSetDeActive(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmFireAlramSetDeActive); + SetTarget(3,aPath1, aPath2, aPath3); + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByPath(u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByPath); + SetTarget(123); + aTxMsg.Data.D8[1] = aActiveOrNot; + aTxMsg.Dlc +=1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByPath(u8 aPath1, u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByPath); + SetTarget(123,aPath1); + aTxMsg.Data.D8[2] = aActiveOrNot; + aTxMsg.Dlc +=1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByPath(u8 aPath1,u8 aPath2, u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByPath); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aActiveOrNot; + aTxMsg.Dlc +=1; + return 0; +} + +unsigned int TInnerCan::CmdFireAlramQueryByPath(u8 aPath1,u8 aPath2,u8 aPath3, u8 aActiveOrNot) +{ + LoadPreset(cmFireAlramQueryByPath); + SetTarget(3, aPath1, aPath2, aPath3); + aTxMsg.Data.D8[4] = aActiveOrNot; + aTxMsg.Dlc +=1; + return 0; +} + + +//按地址激活或取消灭火行为 +unsigned int TInnerCan::CmdExtinguishSetTypeEnter(u8 aType) +{ + LoadPreset(cmExtinguishSetTypeEnter); + SetTarget(123); + aTxMsg.Data.D8[1] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishSetTypeEnter(u8 aPath1, u8 aType) +{ + LoadPreset(cmExtinguishSetTypeEnter); + SetTarget(123, aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishSetTypeEnter(u8 aPath1,u8 aPath2, u8 aType) +{ + LoadPreset(cmExtinguishSetTypeEnter); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishSetTypeEnter(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType) +{ + LoadPreset(cmExtinguishSetTypeEnter); + SetTarget(3, aPath1, aPath2, aPath2); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishSetTypeExit(u8 aType) +{ + LoadPreset(cmExtinguishSetTypeExit); + SetTarget(123); + aTxMsg.Data.D8[1] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishSetTypeExit(u8 aPath1, u8 aType) +{ + LoadPreset(cmExtinguishSetTypeExit); + SetTarget(123, aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishSetTypeExit(u8 aPath1,u8 aPath2, u8 aType) +{ + LoadPreset(cmExtinguishSetTypeExit); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishSetTypeExit(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType) +{ + LoadPreset(cmExtinguishSetTypeExit); + SetTarget(3, aPath1, aPath2, aPath2); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByType(u8 aType) +{ + LoadPreset(cmExtinguishQueryStateByType); + SetTarget(123); + aTxMsg.Data.D8[1] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByType(u8 aPath1, u8 aType) +{ + LoadPreset(cmExtinguishQueryStateByType); + SetTarget(123, aPath1); + aTxMsg.Data.D8[2] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByType(u8 aPath1,u8 aPath2, u8 aType) +{ + LoadPreset(cmExtinguishQueryStateByType); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByType(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType) +{ + LoadPreset(cmExtinguishQueryStateByType); + SetTarget(3, aPath1, aPath2, aPath2); + aTxMsg.Data.D8[4] = aType; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishEnter() +{ + LoadPreset(cmExtinguishEnter); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishEnter(u8 aPath1) +{ + LoadPreset(cmExtinguishEnter); + SetTarget(123, aPath1); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishEnter(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmExtinguishEnter); + SetTarget(23, aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishEnter(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmExtinguishEnter); + SetTarget(3, aPath1, aPath2, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishExit() +{ + LoadPreset(cmExtinguishExit); + SetTarget(123); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishExit(u8 aPath1) +{ + LoadPreset(cmExtinguishExit); + SetTarget(123, aPath1); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishExit(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmExtinguishExit); + SetTarget(23, aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishExit(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmExtinguishExit); + SetTarget(3, aPath1, aPath2, aPath3); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByPath(u8 aActiveOrNot) +{ + LoadPreset(cmExtinguishQueryStateByPath); + SetTarget(123); + aTxMsg.Data.D8[1] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByPath(u8 aPath1, u8 aActiveOrNot) +{ + LoadPreset(cmExtinguishQueryStateByPath); + SetTarget(123, aPath1); + aTxMsg.Data.D8[2] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByPath(u8 aPath1,u8 aPath2, u8 aActiveOrNot) +{ + LoadPreset(cmExtinguishQueryStateByPath); + SetTarget(23, aPath1, aPath2); + aTxMsg.Data.D8[3] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishQueryStateByPath(u8 aPath1,u8 aPath2,u8 aPath3, u8 aActiveOrNot) +{ + LoadPreset(cmExtinguishQueryStateByPath); + SetTarget(3, aPath1, aPath2, aPath2); + aTxMsg.Data.D8[4] = aActiveOrNot; + aTxMsg.Dlc += 1; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishGetState() +{ + + return 0; +} + +unsigned int TInnerCan::CmdExtinguishGetState(u8 aPath1) +{ + LoadPreset(cmExtinguishGetState); + SetTarget(1, aPath1); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishGetState(u8 aPath1,u8 aPath2) +{ + LoadPreset(cmExtinguishGetState); + SetTarget(2, aPath1, aPath2); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishGetState(u8 aPath1,u8 aPath2,u8 aPath3) +{ + LoadPreset(cmExtinguishGetState); + SetTarget(3, aPath1, aPath2, aPath3); + return 0; +} + +unsigned int TInnerCan::CmdExtinguishEnterViaUserCode(unsigned int aUc) +{ + LoadPreset(cmExtinguishEnterViaUserCode); + SetTarget(123); + aTxMsg.Data.D8[1] = static_cast(aUc & 0x000000FF) ; + aTxMsg.Data.D8[2] = static_cast((aUc >> 8)& 0x000000FF) ; + aTxMsg.Data.D8[3] = static_cast((aUc >> 16)& 0x000000FF) ; + aTxMsg.Dlc += 3; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishExitViaUserCode(unsigned int aUc) +{ + LoadPreset(cmExtinguishExitViaUserCode); + SetTarget(123); + aTxMsg.Data.D8[1] = static_cast(aUc & 0x000000FF) ; + aTxMsg.Data.D8[2] = static_cast((aUc >> 8)& 0x000000FF) ; + aTxMsg.Data.D8[3] = static_cast((aUc >> 16)& 0x000000FF) ; + aTxMsg.Dlc += 3; + return 0; +} + +unsigned int TInnerCan::CmdExtinguishGetStateViaUserCode(unsigned int aUc) +{ + LoadPreset(cmExtinguishGetStateViaUserCode); + SetTarget(123); + aTxMsg.Data.D8[1] = static_cast(aUc & 0x000000FF) ; + aTxMsg.Data.D8[2] = static_cast((aUc >> 8)& 0x000000FF) ; + aTxMsg.Data.D8[3] = static_cast((aUc >> 16)& 0x000000FF) ; + aTxMsg.Dlc += 3; + return 0; +} +*/ + +//_________________________________________________ +//按行为设定状态 1个行为 带 1 个参数 +unsigned int TInnerCan::CmdStateSet(TBehaviorCode aBehaviorCode, u8 aPrm) +{ + + return 0; +} +unsigned int TInnerCan::CmdStateSet(u8 aPath1, TBehaviorCode aBehaviorCode, u8 aPrm) +{ + + return 0; +} +unsigned int TInnerCan::CmdStateSet(u8 aPath1, u8 aPath2, TBehaviorCode aBehaviorCode, u8 aPrm) +{ + + return 0; +} +unsigned int TInnerCan::CmdStateSet(u8 aPath1, u8 aPath2, u8 aPath3, TBehaviorCode aBehaviorCode, u8 aPrm) +{ + + return 0; +} +//按行为设定状态 1个行为 +/* +unsigned int TInnerCan::CmdStateSet(TBehaviorCode aBehaviorCode) +{ + LoadPreset(cmBehaviorSet1); + SetTarget(123); + aTxMsg.Data.D8[1] = static_cast(aBehaviorCode); + aTxMsg.Dlc = 2; + return 0; +} +unsigned int TInnerCan::CmdStateSet(u8 aPath1, TBehaviorCode aBehaviorCode) +{ + LoadPreset(cmBehaviorSet1); + SetTarget(123, aPath1); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = static_cast(aBehaviorCode); + aTxMsg.Dlc = 3; + return 0; +} +unsigned int TInnerCan::CmdStateSet(u8 aPath1, u8 aPath2, TBehaviorCode aBehaviorCode) +{ + LoadPreset(cmBehaviorSet1); + SetTarget(123, aPath1, aPath2); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = static_cast(aBehaviorCode); + aTxMsg.Dlc = 4; + return 0; +} +unsigned int TInnerCan::CmdStateSet(u8 aPath1, u8 aPath2, u8 aPath3, TBehaviorCode aBehaviorCode) +{ + LoadPreset(cmBehaviorSet1); + SetTarget(123, aPath1, aPath2, aPath3); + aTxMsg.Data.D8[1] = aPath1; + aTxMsg.Data.D8[2] = aPath2; + aTxMsg.Data.D8[3] = aPath3; + aTxMsg.Data.D8[4] = static_cast(aBehaviorCode); + aTxMsg.Dlc = 5; + return 0; +} +*/ +unsigned int CmdStateSet(); +unsigned int CmdStateRead(); +unsigned int CmdStateSetViaUserCode(); +unsigned int CmdStateReadViaUserCode(); +unsigned int CmdStateReport(); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/ProtoInnerCan.h b/MyCode/src/ProtoInnerCan.h new file mode 100644 index 0000000..f21988d --- /dev/null +++ b/MyCode/src/ProtoInnerCan.h @@ -0,0 +1,1032 @@ +#ifndef PROTOINNERCAN_H_ +#define PROTOINNERCAN_H_ + +#include "gType.h" + +#define InnerEventRxCount 128 +#define InnerRecentUsingCount 16 + +#define InnerFastTxBufCount 10000 +#define InnerEventTxBufCount 50000 + +extern const unsigned char CmdActiveDefaultSet[256][10]; + +typedef enum{ + FastCall = 0, + StdCall = 1, + NetNormalCall = 2, + SimEvent =3, + PortSync +}TInnerCanCmdCallType; + +typedef enum{ + etFire = 1, + etFireCancel = 2, + etFault =3, + etFaultCancel =4, + etSuperVi, + etSuperViCancel, + etLinkageStart, + etLinkageStartCancel, + etLinkageFeedBack, + etLinkageFeedBackCancel, + + etOperate, + etReport, + etBusPadAction, + etDirectPadAction, + etBusPadRequst, + etDirectPadRequst, + etStartDelay, + + etFireSimulate, + etSuperViSimulate, + etLinkageStartSimulate, + etDirectPadReport, + etConfig, +}TInnerEventType; + +typedef enum{ + ftSmoke = 1, + ftTempe =2, + ftHandset, +}TInnerMsgFireType; + +typedef enum{ + stPreAlram = 1, + stPreAlramCanel =2, + stThreholdHi, + stThreholdLow, + stDoorOpen, + stDoorClose, + stManualTouck = 0, + stDevOffLine = 1, + stPowerVoltageInputLow, + stWaterGageLow, + stWaterPressureLow, + stBatteryError, +}TInnerMsgSuperViType; + +typedef enum{ + ttDevOffLine = 1, + ttDevFault = 2, //回路部件故障 + ttDevFaultCancle, //回路部件故障恢复 + ttCirt, //线路故障 + ttBoardErr, //板卡故障 + ttMainPowerErr, //主电故障 + ttStandbyPowerErr, //备电故障 + tt24VErr, //24V故障 + ttBatErr, //电池故障 + ttEarthContactErr, //接地故障 + ttTrialTimeOut, //试用期到期故障 + ttOther, //其他故障 + ttValueErr, //故障统一成一条指令 + tbDevManualReport, + +}TInnerMsgFaultType; + +typedef enum{ + neReset = 0, + +}TInnerNormalEvent; + +typedef enum{ + cmUndefine =0, + cmSyncBeat =1, + cmReset =2, + cmMuteBell, + cmSelfCheck, + cmBroadcastTime, + cmInspection , + //7 + cmPublishAlram, + cmPublishPreAlram, + cmPublishPreAlramResume, + cmTakeChargeAlram, + cmTakeChargeAlramResume, + cmConfirmAlram, + cmThresholdHiAlram, + cmThresholdLowAlram, + //15 + cmManualStart, //手动启动 + cmManualStop, //手动停止 + cmAutoDelayStart, //自动延时启动 + cmAutoStart, //自动启动 + cmAutoStop, //自动停止 + cmAck, //应答 + cmAckStop, //停止应答 + cmAckMiss, //应答缺失 + cmAckHydrant, //消火栓应答 + cmAckFireAreaHydrant, //防火区消火栓应答 + //防火区与声光 + //25 + cmVAAlramStart, //声光启动 + cmVAAlramStop, //声光停止 + cmFireAreaVAAlramStart, //防火区声光启动 + cmFireAreaVAAlramStop, //防火区声光停止 + cmFireAreaStart, //防火区启动 + cmFireAreaStop, //防火区停止 + //31 + cmMainManualAutoState, //主机手自动状态 + cmDirCtlManualAutoState, //多线盘手自动状态 + //故障 + //33 0x21 + cmPortModuleErr, //回路部件故障 + cmPortModuleErrRecover, //回路部件故障恢复 + cmCircuitErr, //线路故障 + cmOtherErr, //板卡故障 + cmMainPowerErr, //主电故障 + cmBKPowerErr, //备电故障 + cmDC24PowerrErr, //24V故障 + cmBatteryPowerrErr, //电池故障 + cmGNDConnectErr, //接地故障 + cmTrialTimeUpErr, //试用期到期故障 + xxcmOtherErr, //其他故障 + cmSYSErr, //故障统一成一条指令 + + //45~53 + cmAllPortAutoRegist, + cmSinglePortAutoRegist, + cmSinglePortAddrManualRegist, + cmClearAllRegist, + cmClearSinglePortRegist, + cmClearSinglePortAddrRegist, + cmPortRegistProgress, + cmPortRegistFinished, + cmPortRegistAbort, + + //54~66 + cmQueryVer, + cmQueryPortReg, + cmQueryRunState, + cmQueryRuntimeData, + cmQueryStaticData, + cmQueryMacCode, + cmQuerySens, + cmQueryAnalogRawData, + cmQueryVoltage, + cmQueryPortRunParam, + cmQueryAbout, + cmQueryCmdConfirm, + cmQueryPortPowerSet, + + //67~77 + cmEpDeviceMask, + cmEpDeviceMaskRemove, + cmMaskRemoveAll, + cmDeviceConfig, + cmDeviceSetSens, + cmDeviceSetLogicAddr, + cmQueryDisplayPadAddrSegment, + cmSetDisplayPadAddrSegment, + cmSetDisplayPadPositionInf, + cmSendDisplayPadInf, + cmAddDisplayPadAddrSegment, + + //78~88 + cmBusCtlPadConfig, + cmBusCtlPadAction, + cmBusCtlPadState, + cmBusCtlPadNoAck, + cmBusCtlPadAckOk, + cmBusCtlPadAllAckOk, + cmBusCtlPadAckLack, + cmBusCtlPadAutoOnActive, + cmBusCtlPadAutoNotActive, + cmBusCtlPadConfigReq, + cmBusCtlPadManualState, + + //89~97 + cmDirectCtlPadConfig, + cmDirectCtlPadAction, + cmDirectCtlPadSilence, + cmDirectCtlPadManualState, + cmDirectCtlPadChannelState, + cmDirectCtlPadLinkageState, + cmDirectCtlPadAutoNotActive, + cmDirectPadConfigReq, + cmDirectCtlPadQueryPort, + + //98 + cmVIrtualAlram, + cmVIrtualAlramCancle, + cmVIrtualStart, + smVIrtualStop, + cmVIrtualAck, + cmVIrtualAckStop, + cm104, + cm105, + cm106, + cmDevLightOn, + cmDevMute, + cmDuplicateAddrCheckStart, + + //110 + cmDuplicateAddrCheckPrg, + cmDuplicateAddrData, + cmDuplicateAddrCheckEnd, + cm113, + cm114, + cm115, + cmSetConfigAddrSegment, + cmQueryStaticDataAddrSegment, + cmDuplicateAddrEpDeviceLed, + cm119, + + cmEnterAdjustMode, + cmExitAdjustMode, + cm122, + cm123, + cm124, + cm125, + cm126, + cmCtrlPowerOn, + cmAckHydrantCommon, + cmAckHydrantCancel, + + cmAlternatingSpeakerSL, + cm131, + cm132, + cm133, + cm134, + cm135, + cm136, + cm137, + cm138, + cm139, + + cmVIrtualSuperVi, + cm141, + cm142, + cm143, + cm144, + cm145, + cm146, + cm147, + cm148, + cm149, + + cmQueryBoardModel, + cmBusDataSyncRegisterReq, + cmBusDataSyncRegister, + cmBusDataSyncRegisterRes, + cmBusDataSyncIsolationReq, + cmBusDataSyncIsolation, + cmBusDataSyncIsolationRes, + cmBusDataSynAlarmLinkage, + cmBusDataSynAlarmLinkageRes, + cm159, + + + /* + cmReportFireDelay, //报告火警延时 + cmReportSuperVisoryDelay, //报告监管事件延时 + cmReportTroubleDelay, //报告故障延时 + cmReportEventDelay, //报告事件延时 + + //注册 Device List + cmRegCheckDeviceExist, + cmRegRescanDevList, + cmRegQueryRescanDevListDone, + cmRegRequstDeviceList, + + //发布状态____________________________________ + //调试模式 mode + cmAdjustModeEnter, + cmAdjustModeExit, + cmAdjustModeCompare, + cmAdjustModeCompareCancel, + + //允许 手动 + cmManualAllow, + cmManualNotAllow, + cmManualCompareAllow, + cmManualCompareAllowCancel, + + //自动模式 mode + cmAutoAllow, + cmAutoNotAllow, + cmAutoCompareAllow, + cmAutoCompareAllowCancel, + + //喷洒设定 mode + cmSplashAllow, + cmSplashNotAllow, + cmSplashCompare, + cmSplashCompareCancel, + + //屏蔽 + cmMaskAll, + cmMaskAllRecover, + cmMaskTypeDevice, + cmMaskTypeDeviceRecover, + cmMask, + cmMaskRecover, + cmMaskAllTemp, + cmMaskAllTempRecover, + cmMaskStateCompare, + cmMaskStateCompareRecover, + + //按类激活或取消火报状态 + cmFireAlramSetTypeActive, + cmFireAlramSetTypeDeActive, + cmFireAlramQueryByType, + cmFireAlramSetActive, + cmFireAlramSetDeActive, + cmFireAlramQueryByPath, + + //按地址激活或取消灭火行为 一级路径，二级路径 + cmExtinguishSetTypeEnter, + cmExtinguishSetTypeExit, + cmExtinguishQueryStateByType, + cmExtinguishEnter, + cmExtinguishExit, + cmExtinguishQueryStateByPath, + cmExtinguishEnterViaUserCode, + cmExtinguishExitViaUserCode, + cmExtinguishGetState, + cmExtinguishGetStateViaUserCode, + + //按类型设定状态 + cmStateSetByType, + + //按设定状态 1级路径 2级路径 3级路径 + cmBehaviorSet1, //以1个行为类型设定设备状态 + cmBehaviorSet2, //以2个行为类型设定状态 + cmBehaviorSet3, //以3个行为类型设定状态 + cmBehaviorSet4, //以4个行为类型设定状态 + cmBehaviorSet1AndPrm1, //以1个行为类型设定设备状态带一个参数 + cmBehaviorSetViaUserCodeSet1, //以1个行为类型设定设备状态 + cmBehaviorSetViaUserCodeSet2, //以2个行为类型设定状态 + cmBehaviorSetViaUserCodeSet3, //以3个行为类型设定状态 + cmBehaviorSetViaUserCodeSet4, //以4个行为类型设定状态 + cmBehaviorSetViaUserCodeSet1AndPrm1, //以1个行为类型设定设备状态带一个参数 + + //读取状态 一级路径类型，二级路径类型 + cmStateRead, + //按用户码读取设备状态 + cmStateReadViaUserCode, + //主动上报状态 + cmStateReport, + + //读取设备属性 一级路径类型，二级路径类型 + cmPropertyRead, + cmPropertyReadViaUserCode, + //参数 读写 一级路径类型，二级路径类型 + cmDevParameterWrite, + cmDevParameterRead, + + //Query 查讯， 这些会触发一个 多 Section 回复 一级路径类型，二级路径类型 + cmQueryDevDescp, + + //手动盘主动报告手动开关是否激活 + cmHandPadManualAllowReport, + //查询手动盘手动开关是否激活 + cmHandPadManualAllowQuery, + //手动盘主动报告状态 + cmHandPadSwitchStateReport, + //查询手动盘开关状态 + cmHandPadSwitchStateQuery, + + //多线盘主动报告手动开关是否激活 + cmDirectCtlManualAllowReport, + //查询多线盘手动开关是否激活 + cmDirectCtlManualAllowQuery, + //多线盘主动报告自动开关是否激活 + cmDirectCtlAutoAllowReport, + //查询多线盘自动开关是否激活 + cmDirectCtlAutoAllowQuery, + //查询多线盘开关状态 + cmDirectCtlSwitchStateQuery, + //查询多线盘通道状态 + cmDirectCtlChannelQuery, + //多线盘输出运行时负载状态 + cmDirectCtlLoadStateQuery, + //多线盘通道类型指派 + cmDirectCtlChannelTypeAssign, + //多线盘通道类型查询 + cmDirectCtlChannelTypeQuery, + + //读取版本 + cmQueryVer, + //停止查询当前 + cmQUeryBrokeAnyway, + //读取运行时原生数据 一级路径类型，二级路径类型 + cmQueryDevRawData, + + //显示盘 Display pad + cmDisplayPadSet, // + cmDisplayPadItemSet, + cmDisplayPadAddItem, + cmDisplayPadReqCtl, + cmDisplayPadCtlReturn, + cmDisplayPadReqInf, + cmDisplayPadReqPevInf, + cmDisplayPadReqNextInf, + cmDisplayPadMsgSend, + cmDisplayPadMsgSendTime, //追加显示盘上一条信息时间戳 + + + cmDescpStringRead, + cmDescpStringWrite, + cmDescpStringErase, + + cmInterLinkPublish, + cmInterLinkWrite, + cmInterLinkDelete, + cmInterLinkActive, + cmInterLinkDeActive, + cmInterLinkDeActiveUnExe , + + + //设置二级总线断路器 (如果回路中的断路器可寻址，可见) + cmBusBreakDoBreak, + cmBusBreakDoContact, + + //回路数据备份复制, 覆盖，可用于回路交换，卡替换 + //cmPortDataRead_1, + //cmPortDataWrite_1, + cmRequstTime, + + //向数据持有端请求传输块数据 属性(数据导入表，配置表，参数表，修正表，可烧录文件) + cmBlockRead, + //主动传输块数据到有对应用途的 设备 属性(数据导入表，配置表，参数表，修正表，可烧录文件) + cmBlockTransmite, + + cmPublishPowerLostTime, + cmPublishEnergy, + + cmManualInspectionStart, + cmManualInspectionDataGet, + cmMonthlyInspectionStart, + cmMonthlyInspectionDataGet, + cmAnnuallyInspectionStart, + cmAnnuallyInspectionDataGet, + + //扩展检流板设置 + cmExternCurrentReportEvent,*/ +}TInnerCommand; + +typedef enum{ + //(数据导入表，配置表，参数表，修正表，可烧录文件) + dtData, + dtConfig, + dtParameter, + dtAlterTable, + dtBurnfiles, + dtExeFile, +}TInnerDataType; + +typedef enum{ + rqNotReqReturn = 0, //无需要回复 不需要接收端回复 + rqAck = 1, //需求回复接收确认 + rqState, //需求回复状态 + rqExeResult, //需求回复执行结果 设置状态，设置输入输出，设置等等 + rqDetails, //需求回复详情 查询，读参数，读取状态， 等等 时使用 可以触发 多块， 多片段传输 + + ackOK, //回复接收确认 + + ackExeState, //回复执行状态 + ackInProcesser, //正在执行 + ackExecuteDone, //回复执行完成 + ackDetails, + + //以下为回复的状态，或执行结果 + ackStateOK, + ackStateOverSize, + ackParseError, + ackInvalidData, + ackBusy, + ackDevFault, + ackUnknown, + ackReqError, + ackSubDevNotExist, //代理回复， 访问二级路径时， 二级路径所属一级路径持有者可以代理回复 + + //以下为 多块，多片段发送 控制字 + //收到以下控制字，各自有默认的回复类型， 不需外加 回复请求 + bsAckOK, + bsAckRepeat, + bsExeDone, + bsExeNotDone, + bsMultiBlockInit, //数据持有端发出 初始化一个多块传输 添加参数描述 byte数量， 块数量， 数据属性(数据导入表，配置表，参数表，修正表，可烧录文件) + bsWaitForCompleted, // 可选回复， 表示当前片段接收正确，等待继续传输。 + bsCheckIntact, //数据持有端发出 询问接收者是否完整 ， 完整的返回接收完整， 否则回复 第一包Byte0=bsRequestBlockX， ,第二包 Byte0 = bsRequestSectionX ，然后主发端重新发送片段 + bsIntact, // 接收完整 + bsExecute, //数据持有端发出 根据数据属性描述，执行文件 ， 要求接收端返回执行结果。 + bsRequestBlockX, // 请求切换到 块 X + bsRequestSectionX, // 请求发送 片段 X + + + bsBlockX, //数据持有端发出 切换到 Block X ，接收端回复描述详情 + bsSection0 = 50, //数据持有端发出 初始化开始传输片段， 接收端可选回复描述详情 + //以下数据持有端发出 以下可选需求即时回复， 或者可以选在在主动传输完成后询问接收者状态 + bsSection1 = 51, + bsSection2, + bsSection3, + bsSection4, + bsSection5, + bsSection6, + bsSection7, + bsSection8, + bsSection9, + bsSection10, + bsSection11, + bsSection12, + bsSection13, + bsSection14, + bsSection15, + bsSection16, + bsSection17, + bsSection18, + bsSection19, + //max = 250 + bsSectionEnd = 251, +}TInnerControlByte; + +typedef enum{ + bcNone = 0, + bcMakeActive = 1, + bcMakeDeActive, + bcMakeChannelActive, + bcMakeChannelDeActive, + bcFireAlarmEnter, + bcFireAlarmExit, + bcExtinguishEnter, + bcExtinguishExit, + bcMakeMask, + bcMakeUnMask, + bcStopQueryReply, + bcSetBackLightOn, + bcSetBackLightOff, + bcSetShowIndexPrv, + bcSetShowIndexNext, + bcSetShowIndex, + bcVaAlramBellOn, + bcVaAlramBellOff, + bcVaAlramLightOn, + bcVaAlramLightOff, + bcVaAlramFullOn, + bcVaAlramAllOff, + bcAdjustModeEnter, + bcAdjustModeExit, + bcManualAllow, + bcManualNotAllow, + bcAutomaticAllow, + bcAutomaticNotAllow, + bcSplashNotAllow, + bcSplashAllow, + bcInterLinkActive, + bcInterLinkDeActive, + bcSetBrokerBroke, + bcSetBrokerContact, + bcRequstLocalInterLinkTakeCtl, + bcRequstLocalInterLinkReturnCtl, +}TBehaviorCode; + +typedef union{ + unsigned int D32[2]; + unsigned char D8[8]; + struct{ + unsigned char rqAck; + unsigned char Byte1; + unsigned char Byte2; + unsigned char Byte3; + unsigned char Byte4; + unsigned char Byte5; + unsigned char Byte6; + unsigned char Byte7; + }Common; +}TStateSetDataMapping; + +typedef struct{ + TCanHeaderID Ide; + union{ + unsigned int D32[2]; + unsigned char D8[8]; + }Data; + unsigned char Dlc; + unsigned char Ava; + unsigned short DelayMs; +}TInnerCanMsg; + +typedef struct{ + int WriteIndex; + int ReadIndex; + struct{ + TCanHeaderID Ide; + union{ + unsigned int D32[2]; + unsigned char D8[8]; + }Data; + unsigned int Dlc; + }wBody, rBody; +}TOutBuf; + +class TInnerCan{ + private: + static const unsigned int Buf4GuiInxMax = 32; + unsigned char ThisAddr; + struct{ + unsigned char iType; + TStateSetDataMapping StateSet; + }ItemTx; + public: + struct{ + unsigned int started; + unsigned char *pData; + unsigned int Len; + unsigned int BlockCount; + unsigned int SectionCount; + }File; + + //TInnerSectionMsg SectionTx; + //TInnerSectionMsg SectionRx; + ///TInnerBlockRx BlockRx; + + TInnerCanMsg aRxMsg; + TInnerCanMsg aTxMsg; + + TInnerCanMsg oBufMsg; + + TOutBuf OutBufFast; + TOutBuf OutBuf; + unsigned char tData[8]; + unsigned int ShouldSyncTime; + + struct{ + unsigned char Inx_In; + unsigned char Inx_Out; + struct{ + TCanHeaderID Ide; + unsigned char Da[8]; + unsigned int Len; + }Body[Buf4GuiInxMax]; + void Insert(TCanHeaderID aIde, unsigned char *aDa, unsigned int aLen){ + Inx_In++; + if(Inx_In >= Buf4GuiInxMax)Inx_In = 0; + Body[Inx_In].Ide.D32 = aIde.D32; + for(int i=0, x=0; (i8 ? 8: aLen; + } + void Reset(){ + Inx_In = 0; + Inx_Out = 0; + } + }Buf4GuiSend; + public: + TInnerCan(){}; + TInnerCan(unsigned char aAddr){ + Init(aAddr); + Buf4GuiSend.Reset(); + } + void Init(unsigned char aAddr){ + unsigned int i,x; + ThisAddr = aAddr; + + aRxMsg.Ava = 0; + aTxMsg.Ava = 0; + + OutBufFast.ReadIndex = 0; + OutBufFast.WriteIndex = 0; + + OutBuf.ReadIndex = 0; + OutBuf.WriteIndex = 0; + + ShouldSyncTime = 0; + + Buf4GuiSend.Reset(); + } + + void ProcesserPublishEmergencyRx(void); + void ProcesserPublishRx(void); + + unsigned int GetNewPublishCount(void); + unsigned int GetNewPublishEmerGencyCount(void); + + unsigned int FileInit(unsigned char pData, unsigned int len); + unsigned int FileGetData(unsigned char *aPd, unsigned int aBlock, unsigned int aSection); + + void LoadPreset(u8 aCmd); + void SetTarget(u8 aPathLevel); + void SetTarget(u8 aPathLevel, unsigned char Path1); + void SetTarget(u8 aPathLevel, unsigned char Path1, unsigned char Path2); + void SetTarget(u8 aPathLevel, unsigned char Path1, unsigned char Path2, unsigned char Path3); + void CanBusFill(void); + + void CmdSendReset(); + void OBufFastInsert(unsigned char Pri, unsigned char Cmd, unsigned char *Data, unsigned char Len); + void OBufInsert(unsigned char Pri, unsigned char Cmd, unsigned char *Data, unsigned char Len); + void OBufPrcRecordAndEvent(); + void OBufCheckSend(); + + void CheckSend2MasterMachine(); + + void CmdSendCustom(TCanHeaderID aIde, unsigned char *p, unsigned int aLen); + unsigned int CmdSendCustomWithReturn(TCanHeaderID aIde, unsigned char *p, unsigned int aLen); + + void BusPadGoAction(unsigned char P0, unsigned char aKeyNum); + void DirectUpLoad(unsigned char aCmd, unsigned char *Data); + void DirectRequest(unsigned char aCmd, unsigned char *Data); + + void SendCmdBroadcastFast(unsigned char aCdt); + void SendCmdClearRegData(); + void SendCmdMaskRemoveAll(); + + + //按类型设定状态 //f State Set + void fStateSetHandPadChannel(u8 aOnOff); + void fStateSetHandPadChannel(u8 aPath1, u8 aOnOff); + void fStateSetHandPadChannel(u8 aPath1, u8 aPath2, u8 aOnOff); + //void fStateSetHandPadChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aOnOff); + void fStateSetDirectCtlChannel(u8 aOnOff); + void fStateSetDirectCtlChannel(u8 aPath1, u8 aOnOff); + void fStateSetDirectCtlChannel(u8 aPath1, u8 aPath2, u8 aOnOff); + //void fStateSetDirectCtlChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aOnOff); + void fStateSetPort(u8 aIntv1, u8 aIntv2); + void fStateSetPort(u8 aPath1, u8 aIntv1, u8 aIntv2); + void fStateSetMotherBoard(u8 aLocalInterLinkSelfRun); + void fStateSetMotherBoard(u8 aPath1, u8 aLocalInterLinkSelfRun); + void fStateSetCommBoard(u8 aEn1, u8 aEn2, u8 aEn3, u8 aEn4); + void fStateSetCommBoard(u8 aPath1, u8 aEn1, u8 aEn2, u8 aEn3, u8 aEn4); + void fStateSetDisplayPad(u8 IsShow, u8 BackLightOnOff, u8 BeepOnOff, u8 IndexLongShow, u8 IndexShortShow); //IndexLongShow : Mask Value = 0xFF; //IndexShortShow : Mask Value = 0xFF; + void fStateSetDisplayPad(u8 aPath1, u8 IsShow, u8 BackLightOnOff, u8 BeepOnOff, u8 IndexLongShow, u8 IndexShortShow); //IndexLongShow : Mask Value = 0xFF; //IndexShortShow : Mask Value = 0xFF; + void fStateSetDisplayPad(u8 aPath1, u8 aPath2, u8 IsShow, u8 BackLightOnOff, u8 BeepOnOff, u8 IndexLongShow, u8 IndexShortShow); //IndexLongShow : Mask Value = 0xFF; //IndexShortShow : Mask Value = 0xFF; + void fStateSetIsoOutput(u8 aGroupOnOff); // 4 channel 0..3 Bit + void fStateSetIsoOutput(u8 aPath1, u8 aGroupOnOff); // 4 channel 0..3 Bit + void fStateSetIsoOutput(u8 aPath1, u8 aPath2, u8 aGroupOnOff); // 4 channel 0..3 Bit + //void fStateSetIsoOutput(u8 aPath1, u8 aPath2, u8 aPath3, u8 aGroupOnOff); // 4 channel 0..3 Bit + void fStateSetIsoInOut(u8 aGroupOnOff); // 2 channel 0..1 Bit + void fStateSetIsoInOut(u8 aPath1, u8 aGroupOnOff); // 2 channel 0..1 Bit + void fStateSetIsoInOut(u8 aPath1, u8 aPath2, u8 aGroupOnOff); // 2 channel 0..1 Bit + //void fStateSetIsoInOut(u8 aPath1, u8 aPath2, u8 aPath3, u8 aGroupOnOff); // 2 channel 0..1 Bit + void fStateSetVaAlram(u8 aBellOnOff, u8 aLightOnOff); + void fStateSetVaAlram(u8 aPath1, u8 aBellOnOff, u8 aLightOnOff); + void fStateSetVaAlram(u8 aPath1, u8 aPath2, u8 aBellOnOff, u8 aLightOnOff); + void fStateSetBroke(u8 aBroke); + void fStateSetBroke(u8 aPath1, u8 aBroke); + void fStateSetBroke(u8 aPath1, u8 aPath2, u8 aBroke); + void fStateSetExtCurrentSensor(u8 aEnable); + void fStateSetExtCurrentSensor(u8 aPath1, u8 aEnable); + void fStateSetExtCurrentSensor(u8 aPath1, u8 aPath2, u8 aEnable); + void fStateSetIsoOutputChannel(u8 aOnOff); + void fStateSetIsoOutputChannel(u8 aPath1, u8 aOnOff); + void fStateSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aOnOff); + void fStateSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aOnOff); + void fStateSetIsoInOutChannel(u8 aOnOff); + void fStateSetIsoInOutChannel(u8 aPath1, u8 aOnOff); + void fStateSetIsoInOutChannel(u8 aPath1, u8 aPath2, u8 aOnOff); + void fStateSetIsoInOutChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aOnOff); + + //f ParameterSet + void fParameterSetHandPadChannel(u8 aAssignType, u8 aAssignRank); + void fParameterSetHandPadChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank); + void fParameterSetHandPadChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank); + + void fParameterSetDirectCtlChannel(u8 aAssignType, u8 aAssignRank, u8 aCLow, u8 aCHi); //aCLow aCHi 0=Ignore, 0=Default + void fParameterSetDirectCtlChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank, u8 aCLow, u8 aCHi); //aCLow aCHi 0=Ignore, 0=Default + void fParameterSetDirectCtlChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank, u8 aCLow, u8 aCHi);//aCLow aCHi 0=Ignore, 0=Default + + void fParameterSetPort(u8 aSubItemCount, u8 aBrokeCurrent, u8 aShortCurrent, u8 aVLow); + void fParameterSetPort(u8 aPath1, u8 aSubItemCount, u8 aBrokeCurrent, u8 aShortCurrent, u8 aVLow); + void fParameterSetMotherBoard(u8 aSubItemCount); + void fParameterSetMotherBoard(u8 aPath1, u8 aSubItemCount); + + void fParameterSetCommBoardChannel(u8 aPath1, u8 aChannel, u8 aCommType, u8 aSpeed, u8 aFerture); //aFerture = BIt0..3 Bits Bit4..5 Stop Bits Bit6..7 Parity + + void fParameterSetDisplayPad(u8 IsDefaultShow, u8 IndexLongShow, u8 IndexShortShow, u8 aIntv); // Mask Value = 0xFF; + void fParameterSetDisplayPad(u8 aPath1, u8 IsDefaultShow, u8 IndexLongShow, u8 IndexShortShow, u8 aIntv); // Mask Value = 0xFF; + void fParameterSetDisplayPad(u8 aPath1, u8 aPath2, u8 IsDefaultShow, u8 IndexLongShow, u8 IndexShortShow, u8 aIntv); // Mask Value = 0xFF; + + void fParameterSetIsoInput(u8 aSens1, u8 aSens2, u8 aSens3, u8 aSens4); + void fParameterSetIsoInput(u8 aPath1, u8 aSens1, u8 aSens2, u8 aSens3, u8 aSens4); + void fParameterSetIsoInput(u8 aPath1, u8 aPath2, u8 aSens1, u8 aSens2, u8 aSens3, u8 aSens4); + + void fParameterSetIsoInputChannel(u8 aAssignType, u8 aAssignRank); + void fParameterSetIsoInputChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank); + void fParameterSetIsoInputChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank); + void fParameterSetIsoInputChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aAssignType, u8 aAssignRank); + + void fParameterSetIsoOutput(u8 aThreshold1, u8 aThreshold2, u8 aThreshold3, u8 aThreshold4); + void fParameterSetIsoOutput(u8 aPath1, u8 aThreshold1, u8 aThreshold2, u8 aThreshold3, u8 aThreshold4); + void fParameterSetIsoOutput(u8 aPath1, u8 aPath2, u8 aThreshold1, u8 aThreshold2, u8 aThreshold3, u8 aThreshold4); + + void fParameterSetIsoOutputChannel(u8 aAssignType, u8 aAssignRank); + void fParameterSetIsoOutputChannel(u8 aPath1, u8 aAssignType, u8 aAssignRank); + void fParameterSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aAssignType, u8 aAssignRank); + void fParameterSetIsoOutputChannel(u8 aPath1, u8 aPath2, u8 aPath3, u8 aAssignType, u8 aAssignRank); + + void fParameterSetIsoInOut(u8 aSens1, u8 aSens2, u8 aThreshold1, u8 aThreshold2); + void fParameterSetIsoInOut(u8 aPath1, u8 aSens1, u8 aSens2, u8 aThreshold1, u8 aThreshold2); + void fParameterSetIsoInOut(u8 aPath1, u8 aPath2, u8 aSens1, u8 aSens2, u8 aThreshold1, u8 aThreshold2); + + void fParameterSetVaAlram(); //No Any Function + + void fParameterSetBroke(u8 aBrokeCurrent, u8 aTimeDelay); + void fParameterSetBroke(u8 aPath1, u8 aBrokeCurrent, u8 aTimeDelay); + void fParameterSetBroke(u8 aPath1, u8 aPath2, u8 aBrokeCurrent, u8 aTimeDelay); + + void fParameterSetExtCurrentSensor(u8 aCRatio, u8 aLowThreshold, u8 aHiThreshold); + void fParameterSetExtCurrentSensor(u8 aPath1, u8 aCRatio, u8 aLowThreshold, u8 aHiThreshold); + void fParameterSetExtCurrentSensor(u8 aPath1, u8 aPath2, u8 aCRatio, u8 aLowThreshold, u8 aHiThreshold); + + void fParameterSetSmoke(u8 Sens, u8 aTimeDelay, u8 A, u8 B); + void fParameterSetSmoke(u8 aPath1, u8 Sens, u8 aTimeDelay, u8 A, u8 B); + void fParameterSetSmoke(u8 aPath1, u8 aPath2, u8 Sens, u8 aTimeDelay, u8 A, u8 B); + + void fParameterSetTempe(u8 aThreshold1, u8 aThreshold2, u8 aIndex); + void fParameterSetTempe(u8 aPath1, u8 aThreshold1, u8 aThreshold2, u8 aIndex); + void fParameterSetTempe(u8 aPath1, u8 aPath2, u8 aThreshold1, u8 aThreshold2, u8 aIndex); + + //Broadcast_____________________________________________ + unsigned int CmdSyncBeat(); + unsigned int CmdReset(); + unsigned int CmdMuteBell(); + unsigned int CmdSelfCheck(); + unsigned int CmdBroadcastTime(); + unsigned int CmdInspection(); + unsigned int CmdForceCheckTrouble(); + + unsigned int CmdPublishFireAlram(); + unsigned int CmdPublishFireAlramResume(); + unsigned int CmdPublishSuperVisory(); + unsigned int CmdPublishSuperVisoryResume(); + unsigned int CmdPublishEvent(); + unsigned int CmdPublishEventResume(); + unsigned int CmdNoticeEvent(); + unsigned int CmdNoticeEventResume(); + + unsigned int CmdRegCheckDeviceExist(u8 aPath1); + unsigned int CmdRegCheckDeviceExist(u8 aPath1,u8 aPath2); + unsigned int CmdRegCheckDeviceExist(u8 aPath1,u8 aPath2,u8 aPath3); + unsigned int CmdRegRescanDevList(u8 aPath1); + unsigned int CmdRegQueryRescanDevListDone(u8 aPath1); + unsigned int CmdRegRequstDeviceList(u8 aPath1); + //调试模式 + unsigned int CmdAdjustModeEnter(void); + unsigned int CmdAdjustModeExit(void); + unsigned int CmdAdjustModeCompare(u8 aActiveOrNot); + unsigned int CmdAdjustModeCompareCancel(void); + //手动 + unsigned int CmdManualAllow(void); + unsigned int CmdManualNotAllow(void); + unsigned int CmdManualCompareAllow(u8 aActiveOrNot); + unsigned int CmdManualCompareAllowCancel(void); + //自动 + unsigned int CmdAutoAllow(); + unsigned int CmdAutoNotAllow(); + unsigned int CmdAutoCompareAllow(u8 aActiveOrNot); + unsigned int CmdAutoCompareAllowCancel(); + //喷洒设定 mode + unsigned int CmdSplashAllow(); + unsigned int CmdSplashNotAllow(); + unsigned int CmdSplashCompare(u8 aActiveOrNot); + unsigned int CmdSplashCompareCancel(); + //屏蔽 + unsigned int CmdMaskAll(); + unsigned int CmdMaskAllRecover(); + unsigned int CmdMaskTypeDevice(u8 aPath1, u8 aType); + unsigned int CmdMaskTypeDevice(u8 aPath1,u8 aPath2, u8 aType); + unsigned int CmdMaskTypeDevice(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType); + unsigned int CmdMaskTypeDeviceRecover(u8 aPath1, u8 aType); + unsigned int CmdMaskTypeDeviceRecover(u8 aPath1,u8 aPath2, u8 aType); + unsigned int CmdMaskTypeDeviceRecover(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType); + unsigned int CmdMask(u8 aPath1); + unsigned int CmdMask(u8 aPath1,u8 aPath2); + unsigned int CmdMask(u8 aPath1,u8 aPath2,u8 aPath3); + unsigned int CmdMaskRecover(u8 aPath1); + unsigned int CmdMaskRecover(u8 aPath1,u8 aPath2); + unsigned int CmdMaskRecover(u8 aPath1,u8 aPath2,u8 aPath3); + unsigned int CmdMaskAllTemp(); + unsigned int CmdMaskAllTempRecover(); + unsigned int CmdMaskStateCompare(u8 aPath1, u8 aActiveOrNot); + unsigned int CmdMaskStateCompare(u8 aPath1,u8 aPath2, u8 aActiveOrNot); + unsigned int CmdMaskStateCompare(u8 aPath1,u8 aPath2,u8 aPath3, u8 aActiveOrNot); + unsigned int CmdMaskStateCompareRecover(u8 aPath1); + unsigned int CmdMaskStateCompareRecover(u8 aPath1,u8 aPath2); + unsigned int CmdMaskStateCompareRecover(u8 aPath1,u8 aPath2,u8 aPath3); + + //按类激活或取消火报状态 + unsigned int CmdFireAlramSetTypeActive(u8 aType); + unsigned int CmdFireAlramSetTypeActive(u8 aPath1, u8 aType); + unsigned int CmdFireAlramSetTypeActive(u8 aPath1,u8 aPath2, u8 aType); + unsigned int CmdFireAlramSetTypeActive(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType); + unsigned int CmdFireAlramSetTypeDeActive(u8 aType); + unsigned int CmdFireAlramSetTypeDeActive(u8 aPath1, u8 aType); + unsigned int CmdFireAlramSetTypeDeActive(u8 aPath1,u8 aPath2, u8 aType); + unsigned int CmdFireAlramSetTypeDeActive(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType); + unsigned int CmdFireAlramQueryByType(u8 aType, u8 aActiveOrNot); + unsigned int CmdFireAlramQueryByType(u8 aPath1, u8 aType, u8 aActiveOrNot); + unsigned int CmdFireAlramQueryByType(u8 aPath1,u8 aPath2, u8 aType, u8 aActiveOrNot); + unsigned int CmdFireAlramQueryByType(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType, u8 aActiveOrNot); + + unsigned int CmdFireAlramSetActive(); + unsigned int CmdFireAlramSetActive(u8 aPath1); + unsigned int CmdFireAlramSetActive(u8 aPath1,u8 aPath2); + unsigned int CmdFireAlramSetActive(u8 aPath1,u8 aPath2,u8 aPath3); + unsigned int CmdFireAlramSetDeActive(); + unsigned int CmdFireAlramSetDeActive(u8 aPath1); + unsigned int CmdFireAlramSetDeActive(u8 aPath1,u8 aPath2); + unsigned int CmdFireAlramSetDeActive(u8 aPath1,u8 aPath2,u8 aPath3); + unsigned int CmdFireAlramQueryByPath(u8 aActiveOrNot); + unsigned int CmdFireAlramQueryByPath(u8 aPath1, u8 aActiveOrNot); + unsigned int CmdFireAlramQueryByPath(u8 aPath1,u8 aPath2, u8 aActiveOrNot); + unsigned int CmdFireAlramQueryByPath(u8 aPath1,u8 aPath2,u8 aPath3, u8 aActiveOrNot); + + //按地址激活或取消灭火行为 + unsigned int CmdExtinguishSetTypeEnter(u8 aType); + unsigned int CmdExtinguishSetTypeEnter(u8 aPath1, u8 aType); + unsigned int CmdExtinguishSetTypeEnter(u8 aPath1,u8 aPath2, u8 aType); + unsigned int CmdExtinguishSetTypeEnter(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType); + + unsigned int CmdExtinguishSetTypeExit(u8 aType); + unsigned int CmdExtinguishSetTypeExit(u8 aPath1, u8 aType); + unsigned int CmdExtinguishSetTypeExit(u8 aPath1,u8 aPath2, u8 aType); + unsigned int CmdExtinguishSetTypeExit(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType); + + unsigned int CmdExtinguishQueryStateByType(u8 aType); + unsigned int CmdExtinguishQueryStateByType(u8 aPath1, u8 aType); + unsigned int CmdExtinguishQueryStateByType(u8 aPath1,u8 aPath2, u8 aType); + unsigned int CmdExtinguishQueryStateByType(u8 aPath1,u8 aPath2,u8 aPath3, u8 aType); + + unsigned int CmdExtinguishEnter(); + unsigned int CmdExtinguishEnter(u8 aPath1); + unsigned int CmdExtinguishEnter(u8 aPath1,u8 aPath2); + unsigned int CmdExtinguishEnter(u8 aPath1,u8 aPath2,u8 aPath3); + + unsigned int CmdExtinguishExit(); + unsigned int CmdExtinguishExit(u8 aPath1); + unsigned int CmdExtinguishExit(u8 aPath1,u8 aPath2); + unsigned int CmdExtinguishExit(u8 aPath1,u8 aPath2,u8 aPath3); + + unsigned int CmdExtinguishQueryStateByPath(u8 aActiveOrNot); + unsigned int CmdExtinguishQueryStateByPath(u8 aPath1,u8 aActiveOrNot); + unsigned int CmdExtinguishQueryStateByPath(u8 aPath1,u8 aPath2,u8 aActiveOrNot); + unsigned int CmdExtinguishQueryStateByPath(u8 aPath1,u8 aPath2,u8 aPath3, u8 aActiveOrNot); + + unsigned int CmdExtinguishGetState(); + unsigned int CmdExtinguishGetState(u8 aPath1); + unsigned int CmdExtinguishGetState(u8 aPath1,u8 aPath2); + unsigned int CmdExtinguishGetState(u8 aPath1,u8 aPath2,u8 aPath3); + + unsigned int CmdExtinguishEnterViaUserCode(unsigned int aUc); + unsigned int CmdExtinguishExitViaUserCode(unsigned int aUc); + unsigned int CmdExtinguishGetStateViaUserCode(unsigned int aUc); + + //unsigned int CmdStateSetByType(); //See 按类型设定状态 f State Set + + unsigned int CmdStateSet(TBehaviorCode aBehaviorCode); + unsigned int CmdStateSet(u8 aPath1, TBehaviorCode aBehaviorCode); + unsigned int CmdStateSet(u8 aPath1, u8 aPath2, TBehaviorCode aBehaviorCode); + unsigned int CmdStateSet(u8 aPath1, u8 aPath2, u8 aPath3, TBehaviorCode aBehaviorCode); + unsigned int CmdStateSet(TBehaviorCode aBehaviorCode, u8 aPrm); + unsigned int CmdStateSet(u8 aPath1, TBehaviorCode aBehaviorCode, u8 aPrm); + unsigned int CmdStateSet(u8 aPath1, u8 aPath2, TBehaviorCode aBehaviorCode, u8 aPrm); + unsigned int CmdStateSet(u8 aPath1, u8 aPath2, u8 aPath3, TBehaviorCode aBehaviorCode, u8 aPrm); + + unsigned int CmdStateSetViaUserCode(); + + unsigned int CmdStateRead(); + unsigned int CmdStateReadViaUserCode(); + unsigned int CmdStateReport(); + + void GetEpUserCodeAreaNumDevType(unsigned char aP0, unsigned char aP1, unsigned int *pUc, unsigned short *pAreaNum, unsigned char *pDevType); + + int CheckPathKissAss(unsigned char aP0, unsigned char aP1); + + int CheckOutBufFastFinish(); + void SendCmdPowerOnFast(); + + void ProcRxMsg(void); + void TaskSecondUpdate(); + void ForceSecondUpdate(); + +}; + + + + + + + + + + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/ProtoM2M.cpp b/MyCode/src/ProtoM2M.cpp new file mode 100644 index 0000000..e8281d5 --- /dev/null +++ b/MyCode/src/ProtoM2M.cpp @@ -0,0 +1,9 @@ +#include "ProtoM2M.h" +#include "Runtime.h" + +unsigned char TProtoM2M::sList[dNETWORK_MACHINE_MASTER_COUNT]; +unsigned char TProtoM2M::sCnt; +unsigned char TProtoM2M::sInitiator; +unsigned char TProtoM2M::sRecPiece; + + diff --git a/MyCode/src/ProtoM2M.h b/MyCode/src/ProtoM2M.h new file mode 100644 index 0000000..5376981 --- /dev/null +++ b/MyCode/src/ProtoM2M.h @@ -0,0 +1,45 @@ +#ifndef PROTOM2M_H_ +#define PROTOM2M_H_ + +#include "gvalue.h" +#include "gType.h" + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" + #include "user_eeprom.h" +} + +class TProtoM2M{ + public: + static unsigned char sList[dNETWORK_MACHINE_MASTER_COUNT]; + static unsigned char sCnt; + static unsigned char sInitiator; + static unsigned char sRecPiece; + public: + TProtoM2M(){}; + void Init(){ + for(int i=0; i 16) )return 0; + if(aP0 == 0)return 0; + if(aP1 == 0)return 0; + + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + aP1--; + aAddr = dAddrSdram_NwUserCodeAbs + (aP0 * 1024) + ( aP1*4 ); + return *(volatile unsigned int *)aAddr; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) && (aP1 <= dDIRECTCTL_KEY_MAX_COUNT) ){ + aP0 -= dADDR_DIRECTPAD_START; + aP1--; + aP1 = aP0 * 8 + aP1; + aAddr = dAddrSdram_NwUserCodeAbs + (40 * 1024) + ( aP1*4 ); + return *(volatile unsigned int *)aAddr; + } + + + return 0; +} + + + diff --git a/MyCode/src/RtUserCode.h b/MyCode/src/RtUserCode.h new file mode 100644 index 0000000..830f86a --- /dev/null +++ b/MyCode/src/RtUserCode.h @@ -0,0 +1,53 @@ +#ifndef RTUSERCODE_H_ +#define RTUSERCODE_H_ + +typedef struct{ + unsigned int uCode; + union{ + unsigned int Full; + struct{ + unsigned char Addr; + unsigned char P0; + unsigned char Dump0; + unsigned char Dump1; + }Spl; + }Path; +}TBackIndex; + +typedef struct{ + struct{ + TBackIndex Body[10240]; + unsigned int BackEndPst; + unsigned int BackIndex[100]; + }Local; + struct{ + unsigned int BackEndPst; + unsigned int BackIndex[1600]; + }Nw; +}TUserCodeDs; + +class TRtUserCode{ + private: + unsigned int ScL0_inx; + unsigned int ScL1_Inx; + public: + TUserCodeDs Context; + + unsigned int ScopeByValStart; + unsigned int ScopeByValEnd; + + unsigned int InxByValStart; + unsigned int InxByValEnd; + public: + TRtUserCode(){} + void Init(); + void BackIndexClear(); + + unsigned int NwGetUserCode(unsigned int aNum, unsigned int aP0, unsigned int aP1); + +}; + + + +#endif + diff --git a/MyCode/src/Runtime.cpp b/MyCode/src/Runtime.cpp new file mode 100644 index 0000000..0c6e8c6 --- /dev/null +++ b/MyCode/src/Runtime.cpp @@ -0,0 +1,1191 @@ +#include "RuntimeData.h" +#include "Runtime.h" +#include "record.h" +#include "EncodeConv.h" +#include "CnCpp.h" + + +#define dNetStateCtlUsingByte 32768 +#define dNetStateCtlUsingInt 8192 +#define dNetStateCtlPortUsingByte 512 + +#define dNetDayTimeCtlUsingByte 65536 +#define dNetDayTimeCtlUsingInt 16384 +#define dNetDayTimePortUsingByte 1024 + +#define dNetYearMonthCtlUsingByte 32768 +#define dNetYearMonthCtlUsingInt 8192 +#define dNetYearMonthPortUsingByte 512 + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" + #include "uart_printer_drv.h" + #include "fdcan_task.h" + #include "task.h" +} + +TSysAuthorize SysAuthorize; + + +unsigned int InnerCanStartUpCmpl = 0; + +const char VerString[32] = {"V0.10\0"}; +const char VerDateTimeString[32] = {"a2024-12-05 19:30:00\0"}; + +volatile int IsEventAddBlock = 0; +TManualEventMsgAdd ManualEventMsgAdd; + +unsigned char SystemPermission = 1; +int SystemPermissionTick =0; + +TPermissionDt PermissionDt; +TPriterSetting PriterSetting; + +unsigned char PrjName[36]; +unsigned char CtlName[36]; +class TDateTime PrjBuildDateTime; + +class TDateTime DateTime; +class TDateTime TrialEndDateTime; + +unsigned char RunState = TRunModeCfg::RunModeRun; + +unsigned char OuterCanTxState = 0; +TInnerCanRxBuf InnerCanRxBuf; +TExtCanRxBufUsingUart ExtCanRxBufUsingUart; + +char CommomGuiTempText[64]; + +unsigned int GraphUsing = 0; +unsigned int GraphAddr =2; +unsigned int GraphLineType =0; +//unsigned int GraphDevBrd = 9600; +//unsigned short GraphDevFrameIntervalMs = 20; +//unsigned short GraphDevHalfDuplex = 1; +//unsigned short GraphDevReplyDelayUs = 4; +//unsigned short GraphDevReplyRetainTimeMs = 80; + +TBroadcast Broadcast; +TScreenAndKeyLock ScreenAndKeyLock; + +unsigned char AlramVaOnOff = 0; +unsigned int AlarmSoundWhat = 0x07; +unsigned int IsMute = 0; +unsigned int IsMuteFire = 0; +unsigned int IsMuteLnk= 0; +unsigned int IsMuteSv= 0; +unsigned int IsMuteFault= 0; +unsigned int IsMuteOpa= 0; + +unsigned char PumpOnOff = 0; +unsigned char PumpFeedBack = 0; + +unsigned int IsSystemError = 0; +unsigned int IsShowingMsgReset = 0; +unsigned int IsShowTipPopup =0; +unsigned int AllowAuto; +unsigned int AllowManual; +unsigned char LinkageManualGo = 0; + +unsigned char PowerSuplyStateOld =0; +unsigned char PowerSuplyState =0; +unsigned char PowerSuplyCommOld =0; +unsigned char PowerSuplyComm =0; +unsigned char PowerBkStateOld =0; +unsigned char PowerBkState =0; +unsigned char BatStateOld =0; +unsigned char BatState =0; +unsigned char PowerSuplyOutputOld =0; +unsigned char PowerSuplyOutput =0; +unsigned char Bat1UnderVoltageOld =0; +unsigned char Bat2UnderVoltageOld =0; +unsigned char Bat1UnderVoltage =0; +unsigned char Bat2UnderVoltage =0; + + +unsigned int FireVaTrenOned =0; + +unsigned int C2cCompletedTick = 0; +unsigned int GolbalDelayTick = 0; + +unsigned char IsStartDelay = 0; +unsigned char NwIsSelfCheck = 0; +unsigned char NwSelfCheckTick[32]; +unsigned int NwIsNormalCheck =0; +unsigned int NwIsStartDelay =0; +unsigned int NwIsFbMiss =0; + +unsigned int LanguageEnCn; +unsigned int TimeSecHasRun =0; + +unsigned int SysIsAuthState = 0; +unsigned int SysRemainAuthTimeHour = 0; +unsigned int IsDulAddrChecking = 0; + +TTextAnsi TextAnsi; +TTextUtf8 TextUtf8; + +int PsBatDataAva = 0; +int PsBatDataHasUpdate = 0; +TPsBatData PsBatData, PsBatDataOld; +TKeyPadData KeyPadData; +TInspec InspecData; + +//TDisplayPadRt DisplayPadRt; +//TBusPadRt BusPadRt; +TDesigePrmData DesigePrmData; +TMaintainData MaintainData; +//TRunModeData RunModeData; +TAreaSetting AreaSetting; +TBroadcastAlramAlternating BroadcastAlramAlternating; + +int TrialCountDownDay; +int TrialEndDay; + +int IsHotKeyCheckingPermission = 0; + +static TRecordCommon aIm; + +TTextInputMode CnInputMode; + +int IsMaintainTip =0; +int LastMaintainTip =0; +int MaintainHourTick=0; +int MaintainHourRdy=0; +TLastMaintain LastMaintain; + +int StartUpCompleted =0; +unsigned int TickNoKey4PopupTip =0; + +TRtReadWriteBuf256Bytes RtBuf256Bytes; + +class TDoPrint DoPrint; +class TexRecord ExRecord; +class TFecBusCRT FecBusCRT; +class TFecBus FecStd; +class TRecord Record; +class TConfig Config; +class TControlCenter CtlCenter; +class TCtrlStartUp CtrlStartUp; +class TPinyinT9 PinyinT9; +class TKeyPad KeyPad; +class TProtoC2C ProtoC2C; +class TInterLink InterLink; +class TDevPrinter DevPrinter; +class TProtoCrt Crt; +class TGeneralDev GeneralDev; +//class TRtUserCode RtUserCode; +class TRemoteData RemoteData; +class TMqttData MqttData; + +TPowerPrmValue PowerPrmValue; +TFecBusCfg FecBusCfg; + +int SlaveInRemoteCtl = 0; + +void TaskTimeUpData() +{ + #define stRadix 16 + int d,e; + if(TimeUpdata){ + TimeUpdata = 0; + if(LiteSelfCheck.IsShowing == 0){ + STextTimeShow.Text[0] = '2'; + STextTimeShow.Text[1] = '0'; + + d = DateTime.Date.Split.Year /stRadix % 10; + e = DateTime.Date.Split.Year % stRadix % 10; + STextTimeShow.Text[2] = d + '0'; + STextTimeShow.Text[3] = e + '0'; + + STextTimeShow.Text[4] = '-'; + + d = DateTime.Date.Split.Month /stRadix % 10; + e = DateTime.Date.Split.Month % stRadix % 10; + STextTimeShow.Text[5] = d + '0'; + STextTimeShow.Text[6] = e + '0'; + STextTimeShow.Text[7] = '-'; + + d = DateTime.Date.Split.Day /stRadix % 10; + e = DateTime.Date.Split.Day % stRadix % 10; + STextTimeShow.Text[8] = d + '0'; + STextTimeShow.Text[9] = e + '0'; + + STextTimeShow.Text[10] = ' '; + + d = DateTime.Time.Split.Hour /stRadix % 10; + e = DateTime.Time.Split.Hour % stRadix % 10; + STextTimeShow.Text[11] = d + '0'; + STextTimeShow.Text[12] = e + '0'; + STextTimeShow.Text[13] = ':'; + + d = DateTime.Time.Split.Minute /stRadix % 10; + e = DateTime.Time.Split.Minute % stRadix % 10; + STextTimeShow.Text[14] = d + '0'; + STextTimeShow.Text[15] = e + '0'; + STextTimeShow.Text[16] = ':'; + + d = DateTime.Time.Split.Second /stRadix % 10; + e = DateTime.Time.Split.Second % stRadix % 10; + STextTimeShow.Text[17] = d + '0'; + STextTimeShow.Text[18] = e + '0'; + STextTimeShow.Text[19] = 0; + STextTimeShow.Text[20] = 0; + + //if(DtStartupCrt == 0){ + // DtCrt[0] = 0; + //} + + STextTimeShow.FontSize = 24;//816; + STextTimeShow.TextDraw(); + } + InnerCan.TaskSecondUpdate(); + ProtoC2C.TaskSecondUpdate(); + } +} + +void PreventEventShow() +{ + EventShow.KeyJab(); +} + +void LoopCheck1S() +{ + SysLoopTick = 0; + if(sys_tick_1s_rdy){ + sys_tick_1s_rdy = 0; + UART7->TDR = KEY_UART_HEAD; + UART7->TDR = 0x42; + UART7->TDR = 0x04; + UART7->TDR = 0xAA; + UART7->TDR = 0x55; + UART7->TDR = 0x00; + UART7->TDR = 0x00; + unsigned char check_sum = KEY_UART_HEAD+0x42+0x04+0xAA+0x55; + UART7->TDR = check_sum; + UART7->TDR = KEY_UART_END; + CtlCenter.PrcBroadcastAlternating(); + DoUpdataRtc(); + TaskTimeUpData(); + } + PreventEventShow(); +} + +void InspecDataInit() +{ + int i; + InspecData.tick = 0; + InspecData.IsStartCheck = 0; + for(i=0; i dNETWORK_MACHINE_COUNT) ) return; + + Cv = 0; + Cv |= (dEpStateBitFire + dEpStateBitStart + dEpStateBitFeedBack + dEpStateBitFbMiss + dEpStateBitFault + dEpStateBitSv + dEpStateBitDelayStart); + Cv <<= 16; + Cv |= (dEpStateBitFire + dEpStateBitStart + dEpStateBitFeedBack + dEpStateBitFbMiss + dEpStateBitFault + dEpStateBitSv + dEpStateBitDelayStart); + Cv |= 0xFF00FF00; + ClearValue = 0xFFFFFFFF; + ClearValue &= ~Cv; + i = aCtlNum-1; + for(x=0; x= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=0; i<8; i++){ + TextAnsi.D32[i] = *(volatile unsigned int *)(aAddr + i *4); + } + } + }else + if( (aRC.Splite.PCtlNum) && (aRC.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = aRC.Splite.PCtlNum -1; + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + TextAnsi.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + } + } + + return CP936ToUTF8(TextAnsi.Text, TextUtf8.Text); +} + +int Check4ModifiedDate2ClearLastMaintain(unsigned char aYear, unsigned char aMonth, unsigned char aDay) +{ + TDMix Now, Prv; + Now.D8[0] = aDay; + Now.D8[1] = aMonth; + Now.D8[2] = aYear; + Now.D8[3] = 0x20; + + Prv.D8[0] = LastMaintain.Day; + Prv.D8[1] = LastMaintain.Month; + Prv.D8[2] = LastMaintain.Year; + Prv.D8[3] = 0x20; + + if(Now.D32 < Prv.D32){ + return 1; + }else{ + return 0; + } +} + +void Check4MaintainToShow() +{ + TDMix16 Now; + TDMix16 tChk, tMt; + + int Active =0; + if(MaintainData.fDa.IsCustomTime){ + if(LastMaintain.Year < (DateTime.Date.Split.Year-1)){ + //Make Active + IsMaintainTip = 1; + return; + }else + if(LastMaintain.Year < DateTime.Date.Split.Year){ + //Check 3 target + tMt.D8[0] = LastMaintain.Day; + tMt.D8[1] = LastMaintain.Month; + + tChk.D8[0] = MaintainData.fDa.Day0; + tChk.D8[1] = MaintainData.fDa.Month0; + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + tChk.D8[0] = MaintainData.fDa.Day1; + tChk.D8[1] = MaintainData.fDa.Month1; + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + tChk.D8[0] = MaintainData.fDa.Day2; + tChk.D8[1] = MaintainData.fDa.Month2; + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + }else{ + // + Now.D8[0] = DateTime.Date.Split.Day; + Now.D8[1] = DateTime.Date.Split.Month; + tMt.D8[0] = LastMaintain.Day; + tMt.D8[1] = LastMaintain.Month; + tChk.D8[0] = MaintainData.fDa.Day0; + tChk.D8[1] = MaintainData.fDa.Month0; + if(Now.D16 >= tChk.D16){ + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + } + tChk.D8[0] = MaintainData.fDa.Day1; + tChk.D8[1] = MaintainData.fDa.Month1; + if(Now.D16 >= tChk.D16){ + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + } + tChk.D8[0] = MaintainData.fDa.Day2; + tChk.D8[1] = MaintainData.fDa.Month2; + if(Now.D16 >= tChk.D16){ + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + } + } + }else{ + if(MaintainData.fDa.IsHalfYear){ + if(LastMaintain.Year < (DateTime.Date.Split.Year-1)){ + //Make Active + IsMaintainTip = 1; + return; + }else + if(LastMaintain.Year < DateTime.Date.Split.Year){ + //Check 3 target + tMt.D8[0] = LastMaintain.Day; + tMt.D8[1] = LastMaintain.Month; + + tChk.D8[0] = 0x05; + tChk.D8[1] = 0x01; + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + tChk.D8[0] = 0x05; + tChk.D8[1] = 0x07; + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + }else{ + // + Now.D8[0] = DateTime.Date.Split.Day; + Now.D8[1] = DateTime.Date.Split.Month; + tMt.D8[0] = LastMaintain.Day; + tMt.D8[1] = LastMaintain.Month; + tChk.D8[0] = 0x05; + tChk.D8[1] = 0x01; + if(Now.D16 >= tChk.D16){ + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + } + tChk.D8[0] = 0x05; + tChk.D8[1] = 0x07; + if(Now.D16 >= tChk.D16){ + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + } + } + }else{ + if(LastMaintain.Year < (DateTime.Date.Split.Year-1)){ + //Make Active + IsMaintainTip = 1; + return; + }else + if(LastMaintain.Year < DateTime.Date.Split.Year){ + //Check 3 target + tMt.D8[0] = LastMaintain.Day; + tMt.D8[1] = LastMaintain.Month; + tChk.D8[0] = 0x05; + tChk.D8[1] = 0x07; + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + }else{ + // + Now.D8[0] = DateTime.Date.Split.Day; + Now.D8[1] = DateTime.Date.Split.Month; + tMt.D8[0] = LastMaintain.Day; + tMt.D8[1] = LastMaintain.Month; + tChk.D8[0] = 0x05; + tChk.D8[1] = 0x07; + if(Now.D16 >= tChk.D16){ + if(tMt.D16 < tChk.D16){ + IsMaintainTip = 1; + return; + } + } + } + } + } + + IsMaintainTip = 0; +} + +void CommonDelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick 9) goto Illegal_Here; + if ((Src.Splite.Year % 16) > 9) goto Illegal_Here; + + aValTens = Src.Splite.Month / 16 *10; + aValOnes = Src.Splite.Month % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) == 0) goto Illegal_Here; + if( (aValTens + aValOnes) > 12) goto Illegal_Here; + + aValTens = Src.Splite.Day / 16 *10; + aValOnes = Src.Splite.Day % 16; + if( aValOnes > 9) goto Illegal_Here; + aVal = aValTens + aValOnes; + if(aVal == 0) goto Illegal_Here; + if(aVal > 31) goto Illegal_Here; + + aValTens = Src.Splite.Hour / 16 *10; + aValOnes = Src.Splite.Hour % 16; + if( aValOnes > 9) goto Illegal_Here; + aVal = aValTens + aValOnes; + if( aVal > 23) goto Illegal_Here; + + aValTens = Src.Splite.Minute / 16 *10; + aValOnes = Src.Splite.Minute % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) > 59) goto Illegal_Here; + + aValTens = Src.Splite.Second / 16 *10; + aValOnes = Src.Splite.Second % 16; + if( aValOnes > 9) goto Illegal_Here; + if( (aValTens + aValOnes) > 59) goto Illegal_Here; + + Dst->Year = Src.Splite.Year; + Dst->Month = Src.Splite.Month; + Dst->Day = Src.Splite.Day; + Dst->Hour = Src.Splite.Hour; + Dst->Minute = Src.Splite.Minute; + Dst->Second = Src.Splite.Second; + return; + + Illegal_Here: + Dst->Year = 0x22; + Dst->Month = 0x01; + Dst->Day = 0x01; + Dst->Hour = 0x08; + Dst->Minute = 0x10; + Dst->Second = 0x10; +} + + +/* +void FireSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FireDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int FireGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FireDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + return *(volatile unsigned short *)(aAddr); +} + +void FireSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FireYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int FireGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FireYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + return *(volatile unsigned short *)(aAddr); +} + + +void LinkageStartSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageStartDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int LinkageStartGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageStartDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + return *(volatile unsigned short *)(aAddr); +} + +void LinkageStartSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageStartYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int LinkageStartGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageStartYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + return *(volatile unsigned short *)(aAddr); +} + +void LinkageFbSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageFbDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int LinkageFbGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageFbDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + return *(volatile unsigned short *)(aAddr); +} + +void LinkageFbSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageFbYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int LinkageFbGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_LinkageFbYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + return *(volatile unsigned short *)(aAddr); +} + + +void FaultSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FaultDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int FaultGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FaultDayTime + (iPn * dNetDayTimeCtlUsingByte) + (iP0 * dNetDayTimePortUsingByte) + (iP1 * 4); + return *(volatile unsigned short *)(aAddr); +} + +void FaultSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FaultYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + *(volatile unsigned short *)(aAddr) = aDt; +} + +unsigned int FaultGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1) +{ + unsigned char Pn,P0,P1; + unsigned int aAddr; + unsigned int iPn, iP0, iP1; + + Pn = aCtlNum; + P0 = aP0; + P1 = aP1; + Pn--; + P0--; + P1--; + iPn = Pn; iP0 =P0; iP1 =P1; + aAddr = dAddrSdram_FaultYearMonth + (iPn * dNetYearMonthCtlUsingByte) + (iP0 * dNetYearMonthPortUsingByte) + (iP1 * 2); + return *(volatile unsigned short *)(aAddr); +} +*/ + diff --git a/MyCode/src/Runtime.h b/MyCode/src/Runtime.h new file mode 100644 index 0000000..4576872 --- /dev/null +++ b/MyCode/src/Runtime.h @@ -0,0 +1,510 @@ +#ifndef RUNTIME_H_ +#define RUNTIME_H_ + +#include "gType.h" +#include "ControlCenter.h" +#include "MainCtl.h" +#include "CtrlStartUp.h" +#include "PinyinT9.h" +#include "KeyPad.h" +#include "ProtoC2C.h" +#include "ProtoM2M.h" +#include "InterLink.h" +#include "DoPrint.h" +#include "exRecord.h" +#include "ProtoFecBusCRT.h" +#include "ProtoCrt.h" +//#include "RtUserCode.h" +#include "Config.h" +#include "RemoteData.h" +#include "MqttData.h" + +#define dInnerCanRxBufMaxCount 2048 +#define dExtCanRxBufUsingUartMaxCount 256 + +typedef struct{ + int WriteIndex; + int ReadIndex; + struct{ + TCanHeaderID Ide; + unsigned char Len; + unsigned char Rsv0; + unsigned char Rsv1; + unsigned char Rsv2; + unsigned char Da[8]; + }Body[dInnerCanRxBufMaxCount]; +}TInnerCanRxBuf; + +typedef struct{ + int WriteIndex; + int ReadIndex; + struct{ + unsigned char Da[12]; + }Body[dExtCanRxBufUsingUartMaxCount]; +}TExtCanRxBufUsingUart; + +typedef struct{ + unsigned char QueryInf; + unsigned char ClearCtlVoice; + unsigned char Check; + unsigned char InfReadConfirm; + unsigned char LinkageActive; + unsigned char MaskAndUnMask; + unsigned char Rsv0; + unsigned char Rsv1; +}TPermissionDt; + +typedef struct{ + unsigned char PadAddr; + unsigned char Addr; + unsigned char AreaNum; + unsigned char SyncMode; + unsigned short BroadcastTime; + unsigned short VaTime; +}TBroadcast; + +typedef struct{ + unsigned char SaveOn; + unsigned char SaveTime; + unsigned char IsKeyLock; + unsigned char Dump; + char UnLockText[4]; +}TScreenAndKeyLock; + +typedef struct{ + unsigned char D8[256]; + unsigned short D16[128]; + unsigned int D32[64]; + void Clear(){ + for(int i=0;i<64;i++)D32[i]=0; + } +}TRtReadWriteBuf256Bytes; + +typedef struct{ + unsigned int Path; + unsigned int mType; + unsigned int SubType; + unsigned int dType; +}TManualEventMsgAdd; + +typedef struct{ + unsigned int Tick; + unsigned int Active; + unsigned int Sync; + unsigned int InBroadcast; +}TBroadcastAlramAlternating; + +typedef struct{ + union{ + unsigned int D32[4]; + struct{ + unsigned char ThisP0; + unsigned char ThisP1; + unsigned char Dump0; + unsigned char Dump1; + struct{ + unsigned char CtlNum; + unsigned char P0; + unsigned char BeginAddr; + unsigned char EndAddr; + }UsingPath[3]; + }Spl; + }Entry[dPORT_MAX_COUNT][dDISPLAYPAD_MAX_COUNT]; + unsigned char Count4Circuit[dPORT_MAX_COUNT]; +}TDisplayPadRt; + +typedef struct{ + union{ + unsigned int D32[4]; + struct{ + unsigned char P0; + unsigned char BeginAddr; + unsigned char EndAddr; + unsigned char Dump; + }TargetPath[4]; + }Entry[dHANDCTL_MAX_COUNT][dHANDCTL_KEY_MAX_COUNT]; +}TBusPadRt; + +typedef union{ + unsigned int D32[16]; + unsigned char D8[64]; + struct{ + unsigned int Smoke; + unsigned int Tempe; + unsigned int HydrantKp; + unsigned int HandReport; + unsigned int ModuleInput; + unsigned int ModuleInOut; + unsigned int ModuleOutput; + unsigned int Va; + + unsigned int DisplayPad; + unsigned int LnkPs; + unsigned int Other; + unsigned int Dump1; + unsigned int Dump2; + unsigned int Dump3; + unsigned int Dump4; + unsigned int Dump5; + }Count; +}TDesigePrmData; + +typedef union{ + unsigned int D32[4]; + unsigned short D16[8]; + unsigned char D8[16]; + struct{ + TDMix16 PsVoltageCh1; + TDMix16 PsVoltageCh2; + TDMix16 BkVoltage; + TDMix16 BatVoltage1; + TDMix16 BatVoltage2; + unsigned char BatEnerger1; + unsigned char BatEnerger2; + + unsigned int HasUpdate; + }Body; +}TPsBatData; + +typedef struct{ + unsigned char AutoManual; + unsigned char BatState; + unsigned short HasUpdate; +}TKeyPadData; + +typedef struct{ + unsigned int tick; + unsigned int IsStartCheck; + unsigned char Port[dPORT_MAX_COUNT]; + unsigned char BusPad[dHANDCTL_MAX_COUNT]; + unsigned char DirectPad[dDIRECTCTL_MAX_COUNT]; + unsigned char ExStroge; + unsigned char KeyBoard; + unsigned char Rsv0; + unsigned char Rsv1; + + unsigned char ErrPort[dPORT_MAX_COUNT]; + unsigned char ErrBusPad[dHANDCTL_MAX_COUNT]; + unsigned char ErrDirectPad[dDIRECTCTL_MAX_COUNT]; + unsigned char ErrExStroge; + unsigned char ErrKeyBoard; + unsigned char ErrRsv0; + unsigned char ErrRsv1; +}TInspec; + +typedef struct{ + unsigned int MainCount; + unsigned int SubExist[2]; + union{ + unsigned char D8[20]; + unsigned int D32[5]; + struct{ + unsigned short vChannel1; + unsigned short vChannel2; + unsigned short vBak; + unsigned short vBat1; + unsigned short vBat2; + unsigned char PercentBat1; + unsigned char PercentBat2; + unsigned char PowerLineFault; + unsigned char BatFault; + unsigned char OfflineFault; + unsigned char OutputFault; + unsigned char Bat1VoltageLow; + unsigned char Bat2VoltageLow; + }Body; + }Sub1, Sub2; +}TPowerPrmValue; + +typedef union{ + unsigned char D8[16]; + struct{ + unsigned char IsCustomTime; + unsigned char IsHalfYear; + unsigned char LastMonth; + unsigned char LastDay; + unsigned char Month0; + unsigned char Day0; + unsigned char Month1; + unsigned char Day1; + unsigned char Month2; + unsigned char Day2; + unsigned char Month3; + unsigned char Day3; + unsigned char Month4; + unsigned char Day4; + unsigned char Month5; + unsigned char Day5; + }fDa; +}TMaintainData; + +typedef union{ + unsigned char D8[16]; + struct{ + unsigned char Day; + unsigned char Month; + unsigned char Year; + unsigned char Cent; + + unsigned char WholeYear; + unsigned char YearOneOffTwo; + unsigned char YearTwoOffTwo; + unsigned char AssignOneOffThree; + unsigned char AssignTwoOffThree; + unsigned char AssignThreeOffThree; + }; + struct{ + unsigned int FullDate; + unsigned char Dump[12]; + }; +}TLastMaintain; + +typedef struct{ + unsigned char IsNormal; + unsigned char Hours; + unsigned char Dump0; + unsigned char Dump1; +}TRunModeData; + +typedef union{ + unsigned char D8[40]; + struct{ + unsigned int Done; + unsigned int nDays; + unsigned char CodeSet[32]; + }fDa; +}TSysAuthorize; + +typedef union{ + unsigned int D32[9]; + char Text[36]; +}TTextAnsi; + +typedef union{ + unsigned int D32[36]; + char Text[136]; +}TTextUtf8; + +typedef struct{ + unsigned short OnOff; + unsigned short PrintSelected; +}TPriterSetting; + +typedef struct{ + unsigned char BusEN; + unsigned char TxEN; + unsigned char RxEN; +}TFecBusCfg; + +typedef struct{ + unsigned int Count; + unsigned char Exist[dAreaCountMax]; + +}TAreaSetting; + +extern const char VerString[32]; +extern const char VerDateTimeString[32]; +extern unsigned char OuterCanTxState; +extern TInnerCanRxBuf InnerCanRxBuf; +extern TExtCanRxBufUsingUart ExtCanRxBufUsingUart; +extern char CommomGuiTempText[64]; + +extern volatile int IsEventAddBlock; +extern TManualEventMsgAdd ManualEventMsgAdd; + +extern unsigned char PrjName[36]; +extern unsigned char CtlName[36]; +extern class TDateTime PrjBuildDateTime; +extern class TDateTime TrialEndDateTime; +extern int TrialCountDownDay; +extern int TrialEndDay; + +extern unsigned char AlramVaOnOff; +extern unsigned int AlarmSoundWhat; +extern unsigned int IsMute; +extern unsigned int IsMuteFire; +extern unsigned int IsMuteLnk; +extern unsigned int IsMuteSv; +extern unsigned int IsMuteFault; +extern unsigned int IsMuteOpa; +extern unsigned char PumpOnOff; +extern unsigned char PumpFeedBack; + +extern unsigned char PowerSuplyStateOld ; +extern unsigned char PowerSuplyState ; +extern unsigned char PowerSuplyCommOld ; +extern unsigned char PowerSuplyComm ; +extern unsigned char PowerBkStateOld ; +extern unsigned char PowerBkState ; +extern unsigned char BatStateOld ; +extern unsigned char BatState ; +extern unsigned char PowerSuplyOutputOld; +extern unsigned char PowerSuplyOutput; +extern unsigned char Bat1UnderVoltageOld; +extern unsigned char Bat2UnderVoltageOld; +extern unsigned char Bat1UnderVoltage; +extern unsigned char Bat2UnderVoltage; + +extern unsigned int FireVaTrenOned; + +extern unsigned int IsSystemError; +extern unsigned int IsShowingMsgReset; +extern unsigned int IsShowTipPopup; +extern unsigned char RunState; +extern unsigned int AllowAuto; +extern unsigned int AllowManual; +extern unsigned char LinkageManualGo; + +extern class TDateTime DateTime; +extern unsigned char SystemPermission; +extern int SystemPermissionTick; +extern int IsHotKeyCheckingPermission; + +extern int PsBatDataHasUpdate; +extern int PsBatDataAva; +extern TPsBatData PsBatData; +extern TPsBatData PsBatDataOld; +extern TKeyPadData KeyPadData;; +extern TInspec InspecData; + +extern TPermissionDt PermissionDt; +extern TPriterSetting PriterSetting; + +extern TMaintainData MaintainData; +//extern TRunModeData RunModeData; +extern TSysAuthorize SysAuthorize; + +extern unsigned int GraphUsing; +extern unsigned int GraphAddr; +extern unsigned int GraphLineType; +//extern unsigned int GraphDevBrd; +//extern unsigned short GraphDevFrameIntervalMs; +//extern unsigned short GraphDevHalfDuplex; +//extern unsigned short GraphDevReplyDelayUs; +//extern unsigned short GraphDevReplyRetainTimeMs; + +extern TTextAnsi TextAnsi; +extern TTextUtf8 TextUtf8; + +extern TTextInputMode CnInputMode; + +extern class TDoPrint DoPrint; +extern class TexRecord ExRecord; +extern class TFecBusCRT FecBusCRT; +extern class TFecBus FecStd; +extern class TRecord Record; +extern class TConfig Config; +extern class TControlCenter CtlCenter; +extern class TCtrlStartUp CtrlStartUp; +extern class TPinyinT9 PinyinT9; +extern class TKeyPad KeyPad; +extern class TProtoC2C ProtoC2C; +extern class TInterLink InterLink; +extern class TDevPrinter DevPrinter; +extern class TProtoCrt Crt; +extern class TGeneralDev GeneralDev; +//extern class TRtUserCode RtUserCode; +extern class TRemoteData RemoteData; +extern class TMqttData MqttData; + +extern unsigned int C2cCompletedTick; +extern unsigned int GolbalDelayTick; + +extern TBroadcast Broadcast; +extern TScreenAndKeyLock ScreenAndKeyLock; + +//extern TDisplayPadRt DisplayPadRt; +//extern TBusPadRt BusPadRt; +extern TDesigePrmData DesigePrmData; +extern unsigned int TimeSecHasRun; + +extern unsigned int SysIsAuthState; +extern unsigned int SysRemainAuthTimeHour; + +extern unsigned char IsStartDelay; +extern unsigned char NwIsSelfCheck; +extern unsigned char NwSelfCheckTick[32]; +extern unsigned int NwIsNormalCheck; +extern unsigned int NwIsStartDelay; +extern unsigned int NwIsFbMiss; +extern unsigned int LanguageEnCn; + +extern TPowerPrmValue PowerPrmValue; + +extern TFecBusCfg FecBusCfg; +extern TAreaSetting AreaSetting; +extern TBroadcastAlramAlternating BroadcastAlramAlternating; + +extern int SlaveInRemoteCtl; +extern int IsMaintainTip; +extern int LastMaintainTip; +extern int MaintainHourTick; +extern int MaintainHourRdy; +extern TLastMaintain LastMaintain; +extern int StartUpCompleted; + +extern unsigned int TickNoKey4PopupTip; +extern unsigned int IsDulAddrChecking; +extern TRtReadWriteBuf256Bytes RtBuf256Bytes; + + +extern void PreventEventShow(); +extern void TaskTimeUpData(); +extern void LoopCheck1S(); + +extern void InspecDataInit(); +extern void InspecDataRestart(); +extern void RuntimeDataInit(); +extern void RtManualPushStartMsg(unsigned char aType, unsigned char SubType, unsigned int aPath); +extern void RtManualPushStartCancelMsg(unsigned char aType, unsigned char SubType, unsigned int aPath); +extern void RtManualPushFbMissMsg(unsigned char aType, unsigned int aPath); + +extern void InitAllNetworkEpData(); +extern void ResetOneNetworkEpState(unsigned int aCtlNum); +extern void ResetAllNetworkEpState(); +extern unsigned char GetNetworkEpState(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void SetNetworkEpState(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned char aSta); +extern unsigned char GetNetworkEpDType(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void SetNetworkEpDType(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned char dType); +extern unsigned short GetNetworkEpData(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void SetNetworkEpData(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned short aData); + +extern void SelfCheckCountDown(); +extern int CheckIsFrozeScreen(); + +extern void Test_AddMask1(); +extern void Test_AddUnMask1(); +extern void Test_AddMask2(); +extern void Test_AddUnMask2(); + +extern int Conv2Utf8Text(TRecordCommon aRC); +extern int Check4ModifiedDate2ClearLastMaintain(unsigned char aYear, unsigned char aMonth, unsigned char aDay); +extern void Check4MaintainToShow(); +extern void CommonDelayMs(unsigned int aMs); + +extern void CoverDateTimeIllegal(TRecordBody Src, TDateTimeBytes *Dst); + +/* +extern void FireSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int FireGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void FireSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int FireGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void LinkageStartSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int LinkageStartGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void LinkageStartSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int LinkageStartGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void LinkageFbSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int LinkageFbGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void LinkageFbSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int LinkageFbGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void FaultSetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int FaultGetEpDayTime(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +extern void FaultSetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1, unsigned int aDt); +extern unsigned int FaultGetEpYearMonth(unsigned char aCtlNum, unsigned char aP0, unsigned char aP1); +*/ + + + +#endif + + diff --git a/MyCode/src/RuntimeData.cpp b/MyCode/src/RuntimeData.cpp new file mode 100644 index 0000000..ed4a662 --- /dev/null +++ b/MyCode/src/RuntimeData.cpp @@ -0,0 +1,61 @@ +#include "RuntimeData.h" + +class TInnerCan InnerCan; +class TFCBusTx FCBusTx; + +class TEpDevice EpDev[dPORT_MAX_COUNT][dEP_MAX_COUNT_PER_PORT]; +class TPort Port[dPORT_MAX_COUNT]; +class THandCtlBoard HandCtlBoard[dHANDCTL_MAX_COUNT]; +class TDirectCtlBoard DirectCtlBoard[dDIRECTCTL_MAX_COUNT]; +class TMotherBoard MotherBoard ; +class TCommBoard CommBoard[dCOMMBOARD_MAX_COUNT] ; +class TThisMainCtl MainCtl, MainCtlReg; + +//class TFecBus FecBus; + +void RtDataInit(void) +{ + unsigned int i; + + InnerCan.Init(0x00); + Record.Init(); + //FecBus.Init(0x00, UsingUart); + + for(i=0; iSplit.Month=1; + sec = sec - 0; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dLEAPMONTH_2){ + pDate->Split.Month=2; + sec = sec - dLEAPMONTH_1; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=3; + sec = sec - dLEAPMONTH_2; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + }else + if(sec < dLEAPMONTH_6){ + if(sec < dLEAPMONTH_4){ + pDate->Split.Month=4; + sec = sec - dLEAPMONTH_3; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dLEAPMONTH_5){ + pDate->Split.Month=5; + sec = sec - dLEAPMONTH_4; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=6; + sec = sec - dLEAPMONTH_5; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + }else + if(sec < dLEAPMONTH_9){ + if(sec < dLEAPMONTH_7){ + pDate->Split.Month=7; + sec = sec - dLEAPMONTH_6; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dLEAPMONTH_8){ + pDate->Split.Month=8; + sec = sec - dLEAPMONTH_7; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=9; + sec = sec - dLEAPMONTH_8; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + }else{ + if(sec < dLEAPMONTH_10){ + pDate->Split.Month=10; + sec = sec - dLEAPMONTH_9; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dLEAPMONTH_11){ + pDate->Split.Month=11; + sec = sec - dLEAPMONTH_10; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=12; + sec = sec - dLEAPMONTH_11; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + } +} + +void TDateTime::s__DecodeYearMonth(unsigned int aSec, TDate *pDate) +{ + unsigned int sec = aSec; + + if(sec < dMONTH_3){ + if(sec < dMONTH_1){ + pDate->Split.Month=1; + sec = sec - 0; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dMONTH_2){ + pDate->Split.Month=2; + sec = sec - dMONTH_1; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=3; + sec = sec - dMONTH_2; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + }else + if(sec < dMONTH_6){ + if(sec < dMONTH_4){ + pDate->Split.Month=4; + sec = sec - dMONTH_3; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dMONTH_5){ + pDate->Split.Month=5; + sec = sec - dMONTH_4; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=6; + sec = sec - dMONTH_5; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + }else + if(sec < dMONTH_9){ + if(sec < dMONTH_7){ + pDate->Split.Month=7; + sec = sec - dMONTH_6; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dMONTH_8){ + pDate->Split.Month=8; + sec = sec - dMONTH_7; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=9; + sec = sec - dMONTH_8; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + }else{ + if(sec < dMONTH_10){ + pDate->Split.Month=10; + sec = sec - dMONTH_9; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else + if(sec < dMONTH_11){ + pDate->Split.Month=11; + sec = sec - dMONTH_10; + pDate->Split.Day = static_cast(sec / 86400) +1; + }else{ + pDate->Split.Month=12; + sec = sec - dMONTH_11; + pDate->Split.Day = static_cast(sec / 86400) +1; + } + } +} + +void TDateTime::s__EncodeLeapYearMonth(TDate aDate, unsigned int *pSec) +{ + unsigned int aDay; + if(aDate.Split.Month < 4){ + if(aDate.Split.Month == 2){ + *pSec = *pSec + dLEAPMONTH_1; + }else + if(aDate.Split.Month == 3){ + *pSec = *pSec + dLEAPMONTH_2; + } + }else + if(aDate.Split.Month < 7){ + if(aDate.Split.Month == 4){ + *pSec = *pSec + dLEAPMONTH_3; + }else + if(aDate.Split.Month == 5){ + *pSec = *pSec + dLEAPMONTH_4; + }else{ + *pSec = *pSec + dLEAPMONTH_5; + } + }else + if(aDate.Split.Month < 10){ + if(aDate.Split.Month == 7){ + *pSec = *pSec + dLEAPMONTH_6; + }else + if(aDate.Split.Month == 8){ + *pSec = *pSec + dLEAPMONTH_7; + }else{ + *pSec = *pSec + dLEAPMONTH_8; + } + }else{ + if(aDate.Split.Month == 10){ + *pSec = *pSec + dLEAPMONTH_9; + }else + if(aDate.Split.Month == 11 ){ + *pSec = *pSec + dLEAPMONTH_10; + }else{ + *pSec = *pSec + dLEAPMONTH_11; + } + } + + if(aDate.Split.Day > 0)aDay = aDate.Split.Day -1; + else aDay = 0; + *pSec = *pSec + ( ( static_cast(aDay) ) * 86400 ); +} + +void TDateTime::s__EncodeYearMonth(TDate aDate, unsigned int *pSec) +{ + unsigned int aDay; + if(aDate.Split.Month < 4){ + if(aDate.Split.Month == 2){ + *pSec = *pSec + dMONTH_1; + }else + if(aDate.Split.Month == 3){ + *pSec = *pSec + dMONTH_2; + } + }else + if(aDate.Split.Month < 7){ + if(aDate.Split.Month == 4){ + *pSec = *pSec + dMONTH_3; + }else + if(aDate.Split.Month == 5){ + *pSec = *pSec + dMONTH_4; + }else{ + *pSec = *pSec + dMONTH_5; + } + }else + if(aDate.Split.Month < 10){ + if(aDate.Split.Month == 7){ + *pSec = *pSec + dMONTH_6; + }else + if(aDate.Split.Month == 8){ + *pSec = *pSec + dMONTH_7; + }else{ + *pSec = *pSec + dMONTH_8; + } + }else{ + if(aDate.Split.Month == 10){ + *pSec = *pSec + dMONTH_9; + }else + if(aDate.Split.Month == 11 ){ + *pSec = *pSec + dMONTH_10; + }else{ + *pSec = *pSec + dMONTH_11; + } + } + + if(aDate.Split.Day > 0)aDay = aDate.Split.Day -1; + else aDay = 0; + *pSec = *pSec + ( ( static_cast(aDay) ) * 86400 ); +} + +void TDateTime::s__DecodeTime(unsigned int sec, TTime *pTime) +{ + unsigned int seconed = sec % 86400; + pTime->Split.Hour = static_cast(seconed / 3600); + seconed = seconed % 3600; + pTime->Split.Minute = static_cast(seconed / 60); + pTime->Split.Second = seconed % 60; + + pTime->Split.Rev = 0; +} + +void TDateTime::s__EncodeTime(TTime aTime, unsigned int *pSec) +{ + unsigned int sec; + sec = ( static_cast(aTime.Split.Hour ) )* 3600; + sec = sec + ( (static_cast(aTime.Split.Minute )) * 60); + sec = sec + aTime.Split.Second; + + *pSec = *pSec + sec; +} + +void TDateTime::sDecodeDateTime(unsigned int aSec, TDate *pDate, TTime *pTime) +{ + unsigned int Year,sec; + + sec = aSec / 126230400; + Year = sec * 4 + dDATETIME_BASESTART_YEAR; + sec = aSec % 126230400; + + if(sec < 31622400){ + //LeapYear + Year += 0; + sec = sec - 0; + s__DecodeLeapYearMonth(sec, pDate); + s__DecodeTime(sec,pTime); + }else + if(sec < 63158400){ + //Not LeapYear + Year += 1; + sec = sec - 31622400; + s__DecodeYearMonth(sec, pDate); + s__DecodeTime(sec,pTime); + }else + if(sec < 94694400){ + //Not LeapYear + Year += 2; + sec = sec - 63158400; + s__DecodeYearMonth(sec, pDate); + s__DecodeTime(sec,pTime); + }else{ + //Not LeapYear + Year += 3; + sec = sec - 94694400; + s__DecodeYearMonth(sec, pDate); + s__DecodeTime(sec,pTime); + } + + pDate->Split.Year = static_cast(Year); +} + + +void TDateTime::sEncodeDateTime(TDate aDate, TTime aTime, unsigned int *pSec) +{ + //4 Years (365*4+1)*24*60*60 = 1461 * 86400 = 126144000 seconed + //2000, leap year 366 * 24*60*60 = 366 * 86400 = 31622400 seconed 31622400 + //2001, year 365 * 24*60*60 = 365 * 86400 = 31536000 seconed 63158400 + //2002, year 365 * 24*60*60 = 365 * 86400 = 31536000 seconed 94694400 + //2003, year 365 * 24*60*60 = 365 * 86400 = 31536000 seconed 126144000 + + unsigned int sec, nmod, idiv; + + idiv = (aDate.Split.Year - dDATETIME_BASESTART_YEAR) / 4; + nmod = (aDate.Split.Year - dDATETIME_BASESTART_YEAR) % 4; + + if(nmod == 0){ + //LeapYear + sec = 0; + s__EncodeLeapYearMonth(aDate, &sec); + s__EncodeTime(aTime, &sec); + }else + if(nmod == 1){ + //Not LeapYear + sec = 31622400; + s__EncodeYearMonth(aDate, &sec); + s__EncodeTime(aTime, &sec); + }else + if(nmod == 2){ + //Not LeapYear + sec = 63158400; + s__EncodeYearMonth(aDate, &sec); + s__EncodeTime(aTime, &sec); + }else{ + //Not LeapYear + sec = 94694400; + s__EncodeYearMonth(aDate, &sec); + s__EncodeTime(aTime, &sec); + } + + sec = sec + (idiv * 126230400); + *pSec = sec; +} + +TDate TDateTime::GetDate(void) +{ + return Date; +} + +TTime TDateTime::GetTime(void) +{ + return Time; +} + +unsigned int TDateTime::GetDateTime(void) +{ + return DateTimeInSecond; +} + +void TDateTime::SetDateTimeSplit(TDate aDate, TTime aTime) +{ + Date.FullValue = aDate.FullValue; + Time.FullValue = aTime.FullValue; + Time.Split.Rev = 0; + sEncodeDateTime(Date, Time, &DateTimeInSecond); +} + +void TDateTime::SetDateTimeViaSecond(unsigned int aSec) +{ + DateTimeInSecond = aSec; + sDecodeDateTime(DateTimeInSecond, &Date, &Time); +} + + +int TDateTime::GetWeek(void) +{ + int day = 0; + + int curyear; + int Mnt; + int cyear = 0; + int cday = 0; + int curmonthday = 0; + + curyear = 20*100+ ((Date.Split.Year /16 * 10) + (Date.Split.Year & 0x0F)); + + if(curyear < 2000 || curyear > 2099 )return 0; + + cyear = curyear - 1970; + cday = cyear/4*(365*3+366); + + if(cyear%4 >= 3 ) + { + cday += (cyear%4-1)*365 + 366; + } + else + { + cday += (cyear%4)*365; + } + + Mnt = ((Date.Split.Month /16 * 10) + (Date.Split.Month & 0x0F)); + switch(Mnt) + { + case 2: curmonthday = 31; break; + case 3: curmonthday = 59; break; + case 4: curmonthday = 90; break; + case 5: curmonthday = 120; break; + case 6: curmonthday = 151; break; + case 7: curmonthday = 181; break; + case 8: curmonthday = 212; break; + case 9: curmonthday = 243; break; + case 10: curmonthday = 273; break; + case 11: curmonthday = 304; break; + case 12: curmonthday = 334; break; + default: curmonthday = 0; break; + } + + if((curyear%4 == 0) && (Mnt >= 3)) + { + curmonthday+= 1; + } + + cday += curmonthday; + cday += ((Date.Split.Day /16 * 10) + (Date.Split.Day & 0x0F)) -1; + + day = (cday + 4) % 7; + if(!day)day = 7; + return day; +} + +void TDateTime::sDateTimeIncSec(unsigned char *DtBytes, unsigned int IncSec) +{ + TDate aDate; + TTime aTime; + unsigned char Hib; + unsigned char Lowb; + unsigned int Sec; + + Hib = DtBytes[0] /16 *10; + Lowb = DtBytes[0] %16; + Hib = Lowb + Hib; + aDate.Split.Year = Hib; + aDate.Split.Year += dDATETIME_BASESTART_YEAR; + Hib = DtBytes[1] /16 * 10; + Lowb = DtBytes[1] %16; + Hib = Lowb + Hib; + aDate.Split.Month = Hib; + Hib = DtBytes[2] /16 * 10; + Lowb = DtBytes[2] %16; + Hib = Lowb + Hib; + aDate.Split.Day = Hib; + Hib = DtBytes[3] /16 * 10; + Lowb = DtBytes[3] %16; + Hib = Lowb + Hib; + aTime.Split.Hour = Hib; + Hib = DtBytes[4] /16 * 10; + Lowb = DtBytes[4] %16; + Hib = Lowb + Hib; + aTime.Split.Minute = Hib; + Hib = DtBytes[5] /16 * 10; + Lowb = DtBytes[5] %16; + Hib = Lowb + Hib; + aTime.Split.Second = Hib; + + sEncodeDateTime(aDate, aTime, &Sec); + Sec+=IncSec; + sDecodeDateTime(Sec, &aDate, &aTime); + + aDate.Split.Year -= dDATETIME_BASESTART_YEAR; + Hib = aDate.Split.Year/10 *16; + Lowb = aDate.Split.Year % 10 + Hib; + DtBytes[0] = Lowb; + Hib = aDate.Split.Month/10 *16; + Lowb = aDate.Split.Month % 10 + Hib; + DtBytes[1] = Lowb; + Hib = aDate.Split.Day/10 *16; + Lowb = aDate.Split.Day % 10 + Hib; + DtBytes[2] = Lowb; + Hib = aTime.Split.Hour/10 *16; + Lowb = aTime.Split.Hour % 10 + Hib; + DtBytes[3] = Lowb; + Hib = aTime.Split.Minute/10 *16; + Lowb = aTime.Split.Minute % 10 + Hib; + DtBytes[4] = Lowb; + Hib = aTime.Split.Second/10 *16; + Lowb = aTime.Split.Second % 10 + Hib; + DtBytes[5] = Lowb; +} + + + + + + + + + + + diff --git a/MyCode/src/TDateTime.h b/MyCode/src/TDateTime.h new file mode 100644 index 0000000..bff67f9 --- /dev/null +++ b/MyCode/src/TDateTime.h @@ -0,0 +1,97 @@ +#ifndef TDATETIME_H_ +#define TDATETIME_H_ + +#define dDATETIME_BASESTART_YEAR 2000 + +typedef union{ + unsigned int FullValue; + struct { + unsigned char Day; + unsigned char Month; + unsigned short Year; + }Split; +}TDate; + +typedef union{ + unsigned int FullValue; + struct { + unsigned char Second ; + unsigned char Minute ; + unsigned char Hour; + unsigned char Rev; + }Split; +}TTime; + +typedef struct { + unsigned char Second ; + unsigned char Minute ; + unsigned char Hour; + unsigned char Day; + unsigned char Month; + unsigned char Year; + unsigned char Dump0; + unsigned char Dump1; +}TDateTimeBytes; + +class TDateTime{ + public: + static constexpr unsigned char MonthDaysNotLeapYear[12] = {31, 28, 31, 30, 31, 30,31, 31, 30, 31, 30, 31}; + static constexpr unsigned char MonthDaysLeapYear[12] = {31, 29, 31, 30, 31, 30,31, 31, 30, 31, 30, 31}; + public: + unsigned int DateTimeInSecond; + TDate Date; + TTime Time; + + private: + static void s__DecodeLeapYearMonth(unsigned int sec, TDate *Date); + static void s__DecodeYearMonth(unsigned int sec, TDate *Date); + static void s__DecodeTime(unsigned int sec, TTime *pTime); + + static void s__EncodeLeapYearMonth(TDate aDate, unsigned int *pSec); + static void s__EncodeYearMonth(TDate aDate, unsigned int *pSec); + static void s__EncodeTime(TTime aTime, unsigned int *pSec); + + public: + TDateTime(void){ + DateTimeInSecond=0; + } + + TDate GetDate(void); + TTime GetTime(void); + unsigned int GetDateTime(void); + + static void sDecodeDateTime(unsigned int aDateTime, TDate *pDate, TTime *pTime); + static void sEncodeDateTime(TDate aDate, TTime aTime, unsigned int *pSec); + + void SetDateTimeSplit(TDate aDate, TTime aTime); + void SetDateTimeViaSecond(unsigned int aDateTime); + int GetWeek(void); + + static void sDateTimeIncSec(unsigned char *DtBytes, unsigned int IncSec); +}; + + + + + + + + +#endif + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/TimerTask.cpp b/MyCode/src/TimerTask.cpp new file mode 100644 index 0000000..f267942 --- /dev/null +++ b/MyCode/src/TimerTask.cpp @@ -0,0 +1,64 @@ +#include "TimerTask.h" + +class TTimerTask TimerTask; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MyCode/src/TimerTask.h b/MyCode/src/TimerTask.h new file mode 100644 index 0000000..2bdbf91 --- /dev/null +++ b/MyCode/src/TimerTask.h @@ -0,0 +1,105 @@ +#ifndef TIMERTASK_H_ +#define TIMERTASK_H_ + +#include "gType.h" + +//time tick task Center +class TTimerTask{ + private: + struct{ + unsigned int OneMs; + }RdyFlags; + unsigned int tick_MsForSec; + struct { + unsigned int Count; + void (*FunC[4])(void); + }Task_1S; + + private: + + public: + TTimerTask(void){ + Init(); + }; + void Init(void){ + Task_1S.Count = 0; + Task_1S.FunC[0] = nullptr; + Task_1S.FunC[1] = nullptr; + Task_1S.FunC[2] = nullptr; + Task_1S.FunC[3] = nullptr; + + tick_MsForSec = 0; + } + void Dm_1mS(void){ + tick_MsForSec++; + RdyFlags.OneMs = 1; + + if(tick_MsForSec > 999){ + tick_MsForSec = 0; + } + + if( ( tick_MsForSec == 200) && (Task_1S.FunC[0] != nullptr) ) Task_1S.FunC[0](); + if( ( tick_MsForSec == 400) && (Task_1S.FunC[1] != nullptr) ) Task_1S.FunC[1](); + if( ( tick_MsForSec == 600) && (Task_1S.FunC[2] != nullptr) ) Task_1S.FunC[2](); + if( ( tick_MsForSec == 800) && (Task_1S.FunC[3] != nullptr) ) Task_1S.FunC[3](); + } + + int RegisteOneSecTash(void (*aFunc)(void)){ + unsigned int i; + + i=0; + if(Task_1S.FunC[0] != nullptr) i++; + if(Task_1S.FunC[1] != nullptr) i++; + if(Task_1S.FunC[2] != nullptr) i++; + if(Task_1S.FunC[3] != nullptr) i++; + Task_1S.Count = i; + + if(Task_1S.Count < 4){ + if(Task_1S.FunC[0] != nullptr) {Task_1S.FunC[0] = aFunc; Task_1S.Count++; return 0;} + if(Task_1S.FunC[1] != nullptr) {Task_1S.FunC[1] = aFunc; Task_1S.Count++; return 0;} + if(Task_1S.FunC[2] != nullptr) {Task_1S.FunC[2] = aFunc; Task_1S.Count++; return 0;} + if(Task_1S.FunC[3] != nullptr) {Task_1S.FunC[3] = aFunc; Task_1S.Count++; return 0;} + return 1; + } + return 2; + } + + int UnRegisteOneSecTash(void (*aFunc)(void)){ + unsigned int i; + if(Task_1S.FunC[0] == aFunc) Task_1S.FunC[0] = nullptr; + if(Task_1S.FunC[1] == aFunc) Task_1S.FunC[1] = nullptr; + if(Task_1S.FunC[2] == aFunc) Task_1S.FunC[2] = nullptr; + if(Task_1S.FunC[3] == aFunc) Task_1S.FunC[3] = nullptr; + + i=0; + if(Task_1S.FunC[0] != nullptr) i++; + if(Task_1S.FunC[1] != nullptr) i++; + if(Task_1S.FunC[2] != nullptr) i++; + if(Task_1S.FunC[3] != nullptr) i++; + + Task_1S.Count = i; + return 0; + } +}; + + + + + + + + + + + + + + + + + +#endif + + + + diff --git a/MyCode/src/UartPrinter.cpp b/MyCode/src/UartPrinter.cpp new file mode 100644 index 0000000..e69de29 diff --git a/MyCode/src/UartPrinter.h b/MyCode/src/UartPrinter.h new file mode 100644 index 0000000..e69de29 diff --git a/MyCode/src/exRecord.cpp b/MyCode/src/exRecord.cpp new file mode 100644 index 0000000..a362ec2 --- /dev/null +++ b/MyCode/src/exRecord.cpp @@ -0,0 +1,1453 @@ +#include "exRecord.h" +#include "Runtime.h" +#include "MainCtl.h" + +extern "C"{ + #include "uart_memory_drv.h" + #include "internal_flash.h" +} + +unsigned short ExrecordStateCode; + +void TexRecord::Init() +{ + unsigned int i = 0; + + RxGetFlag = 0; + TxSetFlag = 0; + + InRecordIndex = 0; + OutRecordIndex = 0; + + OnlineTick = 0; + ReadyFlag = 0; + + GetVerFlag = 0; + GetModleFlag = 0; + + ExRecordBufTemp.Data.CtlAddr = MainCtl.fData.Split.MyNum; + ExRecordBufTemp.Data.CtlType = factory_prm.ctl_type & 0xFF; + for(i=0;i<8;i++){ + ExRecordBufTemp.Data.Pid[i] = factory_prm.pid[i]; + } + for(i=0;i<4;i++){ + ExRecordBufTemp.Data.Pid[i+8] = 0; + } +} + +void TexRecord::iBufInsert() +{ + ; +} + +void TexRecord::iBufProcess() +{ + if(RxGetFlag){ + RxGetFlag = 0; + if(RxMsg.DS.Cmd == TxMsg.DS.Cmd){ + + OnlineTick = 0; + ErrState.Body.OffLine = 0; + ReadyFlag = 1; + + if(exWriteRecord != TxMsg.DS.Cmd){ + TxMsg.DS.Cmd = exNoCmd; + OnTransmite.AckOk = 1; + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + OnTransmite.TimeOutTick = 0; + } + + switch(RxMsg.DS.Cmd){ + case exHeartBeat : + //ErrState &=~exErrCom; + break; + + case exGetModle: + HwInf.ExtMemUartPushData(cmQueryBoardModel, &RxMsg.DS.Data[0]); + break; + + case exGetVer: + HwInf.ExtMemUartPushData(cmQueryVer, &RxMsg.DS.Data[0]); + break; + + case exSetCtlMsg: + break; + + case exGetCtlMsg: + break; + + case exGetErrState: + if(1 == RxMsg.DS.Data[0]){ + ErrState.Body.ReadWriteFail = 66; + }else + if(0 == RxMsg.DS.Data[0]){ + ErrState.Body.ReadWriteFail = 0; + } + + if(ErrState.D32){ + if(ErrReport.D32 == 0){ + CtlCenter.ieAddDevFault(dDevFaultExStroge,0); + ErrReport.D32 = 0x6601; + } + }else{ + if(ErrReport.D32 != 0){ + CtlCenter.ieAddDevFaultCancel(dDevFaultExStroge,0); + ErrReport.D32 = 0; + } + } + + break; + + case exGetTotalRecordNum: + break; + + case exWriteRecord: + if(1 == RxMsg.DS.Data[0]){ + OnTransmite.OnGoing = 1; + OnTransmite.AckOk = 0; + + if(OnTransmite.RetryTimes > 2){ + OnTransmite.AckOk = 1; + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + OnTransmite.TimeOutTick = 0; + + ErrState.Body.ReadWriteFail = 66; + if(ErrReport.D32 == 0){ + CtlCenter.ieAddDevFault(dDevFaultExStroge,0); + ErrReport.D32 = 0x6601; + } + } + }else{ + TxMsg.DS.Cmd = exNoCmd; + OnTransmite.AckOk = 1; + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + OnTransmite.TimeOutTick = 0; + } + break; + + case exReadRecordOrder: + break; + + case exClearRecord: + break; + + default : break; + } + } + } + /* + if(RxGetFlag){ + RxGetFlag = 0; + if(RxMsg.DS.Cmd == dExRecordCmdIdf){ + + OnTransmite.AckOk = 1; + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + OnTransmite.TimeOutTick = 0; + + if(RxMsg.DS.Data[0] == dExRecordReport){ + OnlineTick = 0; + ErrState.Body.OffLine = 0; + + if(RxMsg.DS.Data[1] == 0x66){ + ErrState.Body.ReadWriteFail = 66; + }else{ + ErrState.Body.ReadWriteFail = 0; + } + + if(ErrState.D32){ + if(ErrReport.D32 == 0){ + CtlCenter.ieAddDevFault(dDevFaultExStroge,0); + ErrReport.D32 = 0x6601; + } + }else{ + if(ErrReport.D32 != 0){ + CtlCenter.ieAddDevFaultCancel(dDevFaultExStroge,0); + ErrReport.D32 = 0; + } + } + } + } + } + */ +} + +void TexRecord::oBufInsert() +{ + ; +} + +void TexRecord::oBufInsert(TMemComBufBody aNsBuf) +{ + ; +} + +void TexRecord::oBufProcess()//10ms +{ + unsigned int retry_time = 0; + + if(OnTransmite.OnGoing){ + OnTransmite.TimeOutTick++; + + if(exWriteRecord == TxMsg.DS.Cmd){ + retry_time = 49;//500ms retry + }else{ + retry_time = 1;//1ms retry + } + + if(OnTransmite.TimeOutTick > retry_time){ + OnTransmite.TimeOutTick = 0; + + if(OnTransmite.RetryTimes < 3){ + OnTransmite.RetryFLAG = 1; + }else{ + OnTransmite.RetryTimes = 0; + OnTransmite.OnGoing = 0; + //ErrState |= exErrCom; + } + } + } + + if(!memory_is_busy()){ + if(TxSetFlag){ + TxSetFlag = 0; + + set_memory_tx_data(TxMsg.DS.Cmd, TxMsg.DS.Data, TxMsg.DS.Len); + OnTransmite.TimeOutTick = 0; + OnTransmite.AckOk = 0; + OnTransmite.OnGoing = 1; + }else + if(OnTransmite.RetryFLAG){ + OnTransmite.RetryFLAG = 0; + + OnTransmite.RetryTimes++; + set_memory_tx_data(TxMsg.DS.Cmd, TxMsg.DS.Data, TxMsg.DS.Len); + OnTransmite.TimeOutTick = 0; + OnTransmite.AckOk = 0; + OnTransmite.OnGoing = 1; + } + } + /* + TxMsg.DS.Cmd = exWriteRecord; + TxMsg.DS.Len = 18; + TxMsg.DS.Data[0] = ExRecordBuf[OutRecordIndex].Data.Memtype; + TxMsg.DS.Data[1] = (ExRecordBuf[OutRecordIndex].Data.CtlNum & 0xFF); + TxMsg.DS.Data[2] = ((ExRecordBuf[OutRecordIndex].Data.CtlNum>>8) & 0xFF); + TxMsg.DS.Data[3] = ExRecordBuf[OutRecordIndex].Data.UnitNum; + TxMsg.DS.Data[4] = ExRecordBuf[OutRecordIndex].Data.DeviceNum; + TxMsg.DS.Data[5] = ExRecordBuf[OutRecordIndex].Data.ChannelNum; + TxMsg.DS.Data[6] = (ExRecordBuf[OutRecordIndex].Data.DeviceCode & 0xFF); + TxMsg.DS.Data[7] = ((ExRecordBuf[OutRecordIndex].Data.DeviceCode>>8) & 0xFF); + TxMsg.DS.Data[8] = (ExRecordBuf[OutRecordIndex].Data.EventCode & 0xFF); + TxMsg.DS.Data[9] = ((ExRecordBuf[OutRecordIndex].Data.EventCode>>8) & 0xFF); + TxMsg.DS.Data[10] = (ExRecordBuf[OutRecordIndex].Data.StateCode.D16 & 0xFF); + TxMsg.DS.Data[11] = ((ExRecordBuf[OutRecordIndex].Data.StateCode.D16>>8) & 0xFF); + TxMsg.DS.Data[12] = ExRecordBuf[OutRecordIndex].Data.Year; + TxMsg.DS.Data[13] = ExRecordBuf[OutRecordIndex].Data.Mon; + TxMsg.DS.Data[14] = ExRecordBuf[OutRecordIndex].Data.Day; + TxMsg.DS.Data[15] = ExRecordBuf[OutRecordIndex].Data.Hour; + TxMsg.DS.Data[16] = ExRecordBuf[OutRecordIndex].Data.Min; + TxMsg.DS.Data[17] = ExRecordBuf[OutRecordIndex].Data.Sec; + + if(!memory_is_busy()){ + + set_memory_tx_data(TxMsg.DS.Cmd, TxMsg.DS.Data, TxMsg.DS.Len); + } + */ +} + +void TexRecord::iRecordBufInsert(unsigned char * pdata) +{ + unsigned int i = 0; + + InRecordIndex++; + if(InRecordIndex >= EXRECORDBUFDEEP)InRecordIndex = 0; + + for(i=0;i<32;i++){ + ExRecordBuf[InRecordIndex].D8[i] = (*pdata); + pdata++; + } +} +/* +void TexRecord::iRecordSetMsgType(unsigned char MsgType) +{ + ExRecordBufTemp.Data.MsgType = MsgType; +} + +void TexRecord::iRecordSetCtlNum(unsigned short CtlNum) +{ + ExRecordBufTemp.Data.CtlNum = CtlNum; +} + +void TexRecord::iRecordSetUnitNum(unsigned char UnitNum) +{ + ExRecordBufTemp.Data.UnitNum = UnitNum; +} + +void TexRecord::iRecordSetEventCode(unsigned short EventCode) +{ + ExRecordBufTemp.Data.EventCode = EventCode; +} +*/ +void TexRecord::getExRecordTime(TRecordCommon aRC) +{ + ExRecordBufTemp.Data.Year = (aRC.Splite.Year/16*10) + (aRC.Splite.Year & 0x0F); + ExRecordBufTemp.Data.Mon = (aRC.Splite.Month/16*10) + (aRC.Splite.Month & 0x0F); + ExRecordBufTemp.Data.Day = (aRC.Splite.Day/16*10) + (aRC.Splite.Day & 0x0F); + ExRecordBufTemp.Data.Hour = (aRC.Splite.Hour/16*10) + (aRC.Splite.Hour & 0x0F); + ExRecordBufTemp.Data.Min = (aRC.Splite.Minute/16*10) + (aRC.Splite.Minute & 0x0F); + ExRecordBufTemp.Data.Sec = (aRC.Splite.Second/16*10) + (aRC.Splite.Second & 0x0F); +} + +void TexRecord::getExRecordStateCode(unsigned short StateCode) +{ + ExRecordBufTemp.Data.StateCode.D16 = StateCode; +} + +void TexRecord::setExRecordStateCode(unsigned short StateCode) +{ + ExrecordStateCode = StateCode; + +} + +void TexRecord::SetStateCodeAll() +{ + unsigned int aC; + aC = 0; + + //AllowAuto, AllowManual, + if(AllowAuto) aC |= 1; + if(PowerSuplyState) aC |= 2; + if(PowerSuplyComm | PowerBkState | BatState) aC |= 4; + if(CtlCenter.ieMsgFire.Count >0) aC |= 8; + if(CtlCenter.ieMsgLinkage.StartCount >0) aC |= 0x0000'0010; + if(CtlCenter.ieMsgLinkage.FbCount >0) aC |= 0x0000'0020; + if(CtlCenter.ieMsgSv.Count >0) aC |= 0x0000'0040; + if(CtlCenter.ieMsgFault.Count >0) aC |= 0x0000'0080; + if(CtlCenter.ieMsgMask.Count >0) aC |= 0x0000'0100; + + setExRecordStateCode(static_cast(aC)); +} + +void TexRecord::SetStateCodeAutoManual() +{ + if(AllowAuto)ExrecordStateCode |= 0x0001; + else ExrecordStateCode &= ~0x0001; +} + +void TexRecord::SetStateCodePsOnActive() +{ + if(PowerSuplyState)ExrecordStateCode |= 0x0002; + else ExrecordStateCode &= ~0x0002; +} + +void TexRecord::SetStateCodePsError() +{ + if(PowerSuplyComm | PowerBkState | BatState)ExrecordStateCode |= 0x0004; + else ExrecordStateCode &= ~0x0004; +} + +void TexRecord::SetStateCodeFire() +{ + if(CtlCenter.ieMsgFire.Count >0)ExrecordStateCode |= 0x0008; + else ExrecordStateCode &= ~0x0008; +} + +void TexRecord::SetStateCodeStart() +{ + if(CtlCenter.ieMsgLinkage.StartCount >0)ExrecordStateCode |= 0x0010; + else ExrecordStateCode &= ~0x0010; +} + +void TexRecord::SetStateCodeFeedBack() +{ + if(CtlCenter.ieMsgLinkage.FbCount >0)ExrecordStateCode |= 0x0020; + else ExrecordStateCode &= ~0x0020; +} + +void TexRecord::SetStateCodeSv() +{ + if(CtlCenter.ieMsgSv.Count >0)ExrecordStateCode |= 0x0040; + else ExrecordStateCode &= ~0x0040; +} + +void TexRecord::SetStateCodeFault() +{ + if(CtlCenter.ieMsgFault.Count >0)ExrecordStateCode |= 0x0080; + else ExrecordStateCode &= ~0x0080; +} + +void TexRecord::SetStateCodeMask() +{ + if(CtlCenter.ieMsgMask.Count >0)ExrecordStateCode |= 0x0100; + else ExrecordStateCode &= ~0x0100; +} + +void TexRecord::getExRecordDeviceCode(unsigned char dType) +{ + if(GBDeviceCodePrm[dType]){ + ExRecordBufTemp.Data.DeviceCode = dType; + }else{ + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + } +} + +void TexRecord::getExRecordEpFaultEvent(unsigned char aType, unsigned char State) +{ + if(1 == State){ + switch(aType){ + case 0: + ExRecordBufTemp.Data.EventCode = evFault; + break; + + case 1: + case 2: + case 3: + ExRecordBufTemp.Data.EventCode = evFaultComponent; + break; + + case 4: + case 5: + ExRecordBufTemp.Data.EventCode = evFaultCircuit; + break; + + case 6: + ExRecordBufTemp.Data.EventCode = evFaultMainPower; + break; + + case 7: + case 8: + ExRecordBufTemp.Data.EventCode = evFaultSparePower; + break; + + default: + ExRecordBufTemp.Data.EventCode = evUndefine; + break; + } + }else{ + switch(aType){ + case 0: + ExRecordBufTemp.Data.EventCode = evFaultRecover; + break; + + case 1: + case 2: + case 3: + ExRecordBufTemp.Data.EventCode = evFaultComponentRecover; + break; + + case 4: + case 5: + ExRecordBufTemp.Data.EventCode = evFaultCircuitRecover; + break; + + case 6: + ExRecordBufTemp.Data.EventCode = evFaultMainPowerRecover; + break; + + case 7: + case 8: + ExRecordBufTemp.Data.EventCode = evFaultSparePowerRecover; + break; + + default: + ExRecordBufTemp.Data.EventCode = evUndefine; + break; + } + } +} + +void TexRecord::getExRecordFaultBrdDeviceCode(unsigned char aType) +{ +switch(aType){ + case 0: + case 7: + case 11: + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + break; + + case 1: + case 10: + ExRecordBufTemp.Data.DeviceCode = ftCtlCircuit; + break; + + case 2: + ExRecordBufTemp.Data.DeviceCode = ftBusCtlPanel; + break; + + case 3: + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + break; + + case 4: + ExRecordBufTemp.Data.DeviceCode = ftCanNetworkComm; + break; + + case 5: + ExRecordBufTemp.Data.DeviceCode = ftMainPower; + break; + + case 6: + ExRecordBufTemp.Data.DeviceCode = ftStandbyPower; + break; + + case 8: + ExRecordBufTemp.Data.DeviceCode = ftBatChargeCircuit; + break; + + case 9: + ExRecordBufTemp.Data.DeviceCode = ftGraphShow; + break; + + default: + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + break; + } +} + +void TexRecord::getExRecordFaultBrdEventCode(unsigned char aType, unsigned char State) +{ + if(1 == State){ + switch(aType){ + case 0: + case 2: + case 3: + ExRecordBufTemp.Data.EventCode = evFault; + break; + + case 1: + ExRecordBufTemp.Data.EventCode = evFaultLoopTank; + break; + + case 4: + ExRecordBufTemp.Data.EventCode = evFaultCommunications; + break; + + case 5: + ExRecordBufTemp.Data.EventCode = evFaultMainPower; + break; + + case 6: + ExRecordBufTemp.Data.EventCode = evFaultSparePower; + break; + + case 7: + ExRecordBufTemp.Data.EventCode = evFaultCircuit; + break; + + case 8: + ExRecordBufTemp.Data.EventCode = evFaultCharge; + break; + + case 9: + case 10: + ExRecordBufTemp.Data.EventCode = evFaultCommunications; + break; + + default: + ExRecordBufTemp.Data.EventCode = evFault; + break; + } + }else{ + switch(aType){ + case 0: + case 2: + case 3: + ExRecordBufTemp.Data.EventCode = evFaultRecover; + break; + + case 1: + ExRecordBufTemp.Data.EventCode = evFaultLoopTankRecover; + break; + + case 4: + ExRecordBufTemp.Data.EventCode = evFaultCommunicationsRecover; + break; + + case 5: + ExRecordBufTemp.Data.EventCode = evFaultMainPowerRecover; + break; + + case 6: + ExRecordBufTemp.Data.EventCode = evFaultSparePowerRecover; + break; + + case 7: + ExRecordBufTemp.Data.EventCode = evFaultCircuitRecover; + break; + + case 8: + ExRecordBufTemp.Data.EventCode = evFaultChargeRecover; + break; + + case 9: + case 10: + ExRecordBufTemp.Data.EventCode = evFaultCommunicationsRecover; + break; + + default: + ExRecordBufTemp.Data.EventCode = evFaultRecover; + break; + } + } +} + +void TexRecord::getExRecordFaultDevDeviceCode(unsigned char aType) +{ + switch(aType){ + case 0: + case 1: + case 5: + case 14: + case 17: + case 18: + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + break; + + case 2: + ExRecordBufTemp.Data.DeviceCode = ftCtlCircuit; + break; + + case 3: + ExRecordBufTemp.Data.DeviceCode = ftBusCtlPanel; + break; + + case 4: + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + break; + + case 6: + ExRecordBufTemp.Data.DeviceCode = ftDataMemCard; + break; + + case 7: + case 8: + case 19: + case 21: + case 22: + case 23: + ExRecordBufTemp.Data.DeviceCode = ftMainPower; + break; + + case 9: + case 10: + case 20: + case 24: + case 25: + case 26: + case 27: + ExRecordBufTemp.Data.DeviceCode = ftStandbyPower; + break; + + case 11: + case 12: + case 15: + case 16: + ExRecordBufTemp.Data.DeviceCode = ftCanNetworkComm; + break; + + case 13: + ExRecordBufTemp.Data.DeviceCode = ftGraphShow; + break; + + default: + ExRecordBufTemp.Data.DeviceCode = ftUndefineFecDevType; + break; + } +} + +void TexRecord::getExRecordFaultDevEventCode(unsigned char aType, unsigned char State) +{ + if(1 == State){ + switch(aType){ + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 14: + ExRecordBufTemp.Data.EventCode = evFault; + break; + + case 7: + case 19: + ExRecordBufTemp.Data.EventCode = evFaultMainPower; + break; + + case 8: + case 11: + case 12: + case 13: + case 15: + case 16: + case 21: + ExRecordBufTemp.Data.EventCode = evFaultCommunications; + break; + + case 9: + case 10: + case 20: + case 24: + case 25: + case 26: + case 27: + ExRecordBufTemp.Data.EventCode = evFaultSparePower; + break; + + case 22: + case 23: + ExRecordBufTemp.Data.EventCode = evFaultCircuit; + break; + + default: + ExRecordBufTemp.Data.EventCode = evUndefine; + break; + } + }else{ + switch(aType){ + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 14: + ExRecordBufTemp.Data.EventCode = evFaultRecover; + break; + + case 7: + case 19: + ExRecordBufTemp.Data.EventCode = evFaultMainPowerRecover; + break; + + case 8: + case 11: + case 12: + case 13: + case 15: + case 16: + case 21: + ExRecordBufTemp.Data.EventCode = evFaultCommunicationsRecover; + break; + + case 9: + case 10: + case 20: + case 24: + case 25: + case 26: + case 27: + ExRecordBufTemp.Data.EventCode = evFaultSparePowerRecover; + break; + + case 22: + case 23: + ExRecordBufTemp.Data.EventCode = evFaultCircuitRecover; + break; + + default: + ExRecordBufTemp.Data.EventCode = evUndefine; + break; + } + } +} + +void TexRecord::iExRecordFaultInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + + ExRecordBufTemp.Data.MsgType = 3; + ExRecordBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + + if((aRC.Splite.Data1 & 0xF0) == 0xC0){ + if((aRC.Splite.P1 >= dADDR_HANDPAD_START) && (aRC.Splite.P1 <= dADDR_HANDPAD_END)){ + ExRecordBufTemp.Data.UnitNum = aRC.Splite.P1; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + + ExRecordBufTemp.Data.DeviceCode = ftBusCtlPanel; + if(aData1)ExRecordBufTemp.Data.EventCode = evFaultCommunications; + else ExRecordBufTemp.Data.EventCode = evFaultCommunicationsRecover; + }else + if((aRC.Splite.P1 >= dADDR_DIRECTPAD_START) && (aRC.Splite.P1 <= dADDR_DIRECTPAD_END)){ + ExRecordBufTemp.Data.UnitNum = aRC.Splite.P1; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + if(aData1)ExRecordBufTemp.Data.EventCode = evFaultCommunications; + else ExRecordBufTemp.Data.EventCode = evFaultCommunicationsRecover; + } + }else + if((aRC.Splite.Data1 & 0xF0) == 0xD0){ + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + + getExRecordFaultDevDeviceCode(aData0); + getExRecordFaultDevEventCode(aData0, aData1); + }else + if((aRC.Splite.Data1 & 0xF0) == 0xE0){ + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + + ExRecordBufTemp.Data.DeviceCode = ftCtlCircuit; + if(aData1)ExRecordBufTemp.Data.EventCode = evFault; + else ExRecordBufTemp.Data.EventCode = evFaultRecover; + }else + if((aRC.Splite.Data1 & 0xF0) == 0xF0){ + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + + getExRecordFaultBrdDeviceCode(aData0); + getExRecordFaultBrdEventCode(aData0, aData1); + }else{ + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + + if((aP0 > 0)&&(aP0 < 40)){ + getExRecordDeviceCode(dType); + }else + if((aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_START)){ + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + } + + getExRecordEpFaultEvent(aData0, aData1); + } + + /* + ExRecordBufTemp.Data.UnitNum = + ExRecordBufTemp.Data.DeviceNum = + ExRecordBufTemp.Data.ChannelNum = + ExRecordBufTemp.Data.DeviceCode = + ExRecordBufTemp.Data.EventCode = + + ExRecordBufTemp.Data.StateCode.D16 = + */ + getExRecordTime(aRC); + getExRecordStateCode(ExrecordStateCode); + iRecordBufInsert(ExRecordBufTemp.D8); +} + +void TexRecord::iExRecordFireInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + unsigned char IsFirst; + + ExRecordBufTemp.Data.MsgType = 2; + ExRecordBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + IsFirst = aRC.Splite.Data1; + + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + + if((aP0)&&(aP0 <= 40)){ + getExRecordDeviceCode(dType); + }else + if((aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END)){ + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + }else{ + ExRecordBufTemp.Data.DeviceCode = ftUndefineFecDevType; + } + + if(1 == IsFirst){ + ExRecordBufTemp.Data.EventCode = evFirstFireAlarm; + }else{ + ExRecordBufTemp.Data.EventCode = evFireAlarm; + } + + getExRecordTime(aRC); + getExRecordStateCode(ExrecordStateCode); + iRecordBufInsert(ExRecordBufTemp.D8); + + if(1 == IsFirst){ + ExRecordBufTemp.Data.MsgType = 1; + iRecordBufInsert(ExRecordBufTemp.D8); + } +} + +void TexRecord::iExRecordOperateInsert(TRecordCommon aRC) +{ + static unsigned int setHandAuto = 0x00; + + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char mType; + unsigned char aData0; + unsigned char aData1; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + mType = aRC.Splite.mType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1; + + ExRecordBufTemp.Data.MsgType = 4; + ExRecordBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + if(mType == etOperate){ + switch(aData0){ + case otPowerOff: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evSystemPowerOff; + break; + + case otPowerOn: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evSystemPowerOn; + break; + + case otReset: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evReset; + break; + + case otMute: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evMuteBell; + break; + + case otMask: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evMask; + break; + + case otUnMask: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evMaskRelieve; + break; + + case otRegiste: + return; + break; + + case otUnRegiste: + return; + break; + + case otSetCanNetwork: + return; + break; + + case otCfgBoard: + return; + break; + + case otCfgCrt: + return; + break; + + case otCfgPriter: + return; + break; + + case otCfgDevice: + return; + break; + + case otCfgDateTime: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evAdjustClock; + break; + + case otCfgPermissionAllow: + return; + break; + + case otAllowSet: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + + if(setHandAuto != (aData1 & 0x01)){ + setHandAuto &=~0x01; + setHandAuto |=(aData1 & 0x01); + ExRecordBufTemp.Data.EventCode = evAutomatic; + }else + if(setHandAuto != (aData1 & 0x02)){ + setHandAuto &=~0x02; + setHandAuto |=(aData1 & 0x02); + ExRecordBufTemp.Data.EventCode = evManual; + } + break; + + case otAlramSetOnOff: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftAlramVaCircuit; + if(aData1){ + ExRecordBufTemp.Data.EventCode = evLaunch; + }else{ + ExRecordBufTemp.Data.EventCode = evShutoff; + } + break; + + case otBusPadOn: + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftBusCtlPanel; + ExRecordBufTemp.Data.EventCode = evLaunch; + break; + + case otBusPadOff: + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftBusCtlPanel; + ExRecordBufTemp.Data.EventCode = evShutoff; + break; + + case otDirectPadManualAllowOn: + return; + //--------------------------------------------------------------------------------- + //FillText4DirectPadManualAllowOn(); + break; + + case otDirectPadManualAllowOff: + return; + //--------------------------------------------------------------------------------- + //FillText4DirectPadManualAllowOff(); + break; + + case otDirectPadNodeOn: + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + ExRecordBufTemp.Data.EventCode = evLaunch; + break; + + case otDirectPadNodeOff: + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + ExRecordBufTemp.Data.EventCode = evShutoff; + break; + + case otUserCheck: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evKeyPressFunctionCheck; + break; + + case otLinkageGo: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evLaunchInrerLink; + break; + + case otSetNwTime: + case otReqNwTime: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evAdjustClock; + break; + + case otSelfCheck: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evSelfCheck; + break; + + case otSetManualAllowState: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evManual; + break; + + case otSetAutoAllowState: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evAutomatic; + break; + + case otRemoteSetManualAllowState: + return; + break; + + case otRemoteSetAutoAllowState: + return; + break; + + case otReportManualAllowState: + return; + break; + + case otReportAutoAllowState: + return; + break; + + case otFireConfirm: + case otFireRemoteConfirm: + case otFaultConfirm: + case otFaultRemoteConfirm: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + ExRecordBufTemp.Data.EventCode = evFaultOrFireAlarmExactly; + break; + + case otSetSmokeSensViaCircuit: + return; + break; + + case otSetSmokeSensViaAddr: + return; + break; + + case otCleanUp: + return; + break; + + case otLinkageExpsSaveRemove: + return; + break; + + case otBusPadModify: + return; + break; + + case otDirectPadModify: + return; + break; + + case otDescpModify: + return; + break; + + case otPassWdModify: + return; + break; + + case otRegisterByManual: + return; + break; + + case otAddRemoveNwCtl: + return; + break; + + case otRegCanNetwork: + return; + break; + + case otClearNetworkCfg: + return; + break; + + case otBroadcastVa: + return; + break; + + case otSetAllowState: + ExRecordBufTemp.Data.UnitNum = 0; + ExRecordBufTemp.Data.DeviceNum = 0; + ExRecordBufTemp.Data.ChannelNum = 0; + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + if(aData1 == 3)ExRecordBufTemp.Data.EventCode = evManual; + else if(aData1 == 1)ExRecordBufTemp.Data.EventCode = evAutomatic; + else if(aData1 == 2)ExRecordBufTemp.Data.EventCode = evManual; + else if(aData1 == 2)ExRecordBufTemp.Data.EventCode = evManual; + break; + } + } + + getExRecordTime(aRC); + getExRecordStateCode(ExrecordStateCode); + iRecordBufInsert(ExRecordBufTemp.D8); +} + +void TexRecord::iExRecordLinkageInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + unsigned char data; + + ExRecordBufTemp.Data.MsgType = 4; + ExRecordBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + data = aRC.Splite.iByte0; + + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + + if( (aP0 >0) && (aP0 <=40) ){ + getExRecordDeviceCode(dType); + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + }else{ + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + } + + if(data == 0x01){ + ExRecordBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x02){ + ExRecordBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x03){ + ExRecordBufTemp.Data.EventCode = evFeedBack; + }else + if(data == 0x04){ + ExRecordBufTemp.Data.EventCode = evFeedBack; + }else + if(data == 0x05){ + ExRecordBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x06){ + ExRecordBufTemp.Data.EventCode = evLaunchInrerLink; + }else + if(data == 0x07){ + return; + }else + if(data == 0xB1){ + ExRecordBufTemp.Data.EventCode = evShutoff; + }else + if(data == 0xB3){ + ExRecordBufTemp.Data.EventCode = evFeedBackRevoke; + }else + if(data == 0xB5){ + ExRecordBufTemp.Data.EventCode = evShutoff; + }else + if(data == 0xB6){ + ExRecordBufTemp.Data.EventCode = evShutoff; + }else + if(data == 0xB7){ + return; + } + + getExRecordTime(aRC); + getExRecordStateCode(ExrecordStateCode); + iRecordBufInsert(ExRecordBufTemp.D8); +} + +void TexRecord::iExRecordSvInsert(TRecordCommon aRC) +{ + unsigned char aP0; + unsigned char aP1; + unsigned char dType; + unsigned char aData0; + unsigned char aData1; + + ExRecordBufTemp.Data.MsgType = 4; + ExRecordBufTemp.Data.CtlNum = aRC.Splite.PCtlNum; + + aP0 = aRC.Splite.P0; + aP1 = aRC.Splite.P1; + dType = aRC.Splite.dType; + aData0 = aRC.Splite.Data0; + aData1 = aRC.Splite.Data1 & 0x01; + + ExRecordBufTemp.Data.UnitNum = aP0; + ExRecordBufTemp.Data.DeviceNum = aP1; + ExRecordBufTemp.Data.ChannelNum = 0; + + if( (aP0 >0) && (aP0 <=40) ){ + getExRecordDeviceCode(dType); + }else + if( (aP0 >=dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + ExRecordBufTemp.Data.DeviceCode = ftDirCtlPanel; + }else{ + ExRecordBufTemp.Data.DeviceCode = ftMainCtl; + } + + ExRecordBufTemp.Data.EventCode = evSuperVisory; + + getExRecordTime(aRC); + getExRecordStateCode(ExrecordStateCode); + iRecordBufInsert(ExRecordBufTemp.D8); +} + +void TexRecord::oCmdInsert()//10ms +{ + static unsigned int send_tick = 0; + + if(!OnTransmite.OnGoing){ + send_tick++; + if(send_tick > (1000 - 1)){//10s + send_tick = 0; + } + + if(GetVerFlag){ + GetVerFlag = 0; + + TxMsg.DS.Cmd = exGetVer; + TxMsg.DS.Len = 0; + + TxSetFlag = 1; + }else + if(GetModleFlag){ + GetModleFlag = 0; + + TxMsg.DS.Cmd = exGetModle; + TxMsg.DS.Len = 0; + + TxSetFlag = 1; + }else + if((ReadyFlag)&&(InRecordIndex != OutRecordIndex)){ + OutRecordIndex++; + if(OutRecordIndex >= EXRECORDBUFDEEP)OutRecordIndex = 0; + + TxMsg.DS.Cmd = exWriteRecord; + TxMsg.DS.Len = 32; + TxMsg.DS.Data[0] = ExRecordBuf[OutRecordIndex].Data.MsgType; + TxMsg.DS.Data[1] = ExRecordBuf[OutRecordIndex].Data.CtlAddr; + TxMsg.DS.Data[2] = (ExRecordBuf[OutRecordIndex].Data.CtlType & 0xFF); + TxMsg.DS.Data[3] = ((ExRecordBuf[OutRecordIndex].Data.CtlType>>8) & 0xFF); + TxMsg.DS.Data[4] = ExRecordBuf[OutRecordIndex].Data.Pid[0]; + TxMsg.DS.Data[5] = ExRecordBuf[OutRecordIndex].Data.Pid[1]; + TxMsg.DS.Data[6] = ExRecordBuf[OutRecordIndex].Data.Pid[2]; + TxMsg.DS.Data[7] = ExRecordBuf[OutRecordIndex].Data.Pid[3]; + TxMsg.DS.Data[8] = ExRecordBuf[OutRecordIndex].Data.Pid[4]; + TxMsg.DS.Data[9] = ExRecordBuf[OutRecordIndex].Data.Pid[5]; + TxMsg.DS.Data[10] = ExRecordBuf[OutRecordIndex].Data.Pid[6]; + TxMsg.DS.Data[11] = ExRecordBuf[OutRecordIndex].Data.Pid[7]; + TxMsg.DS.Data[12] = ExRecordBuf[OutRecordIndex].Data.Pid[8]; + TxMsg.DS.Data[13] = ExRecordBuf[OutRecordIndex].Data.Pid[9]; + TxMsg.DS.Data[14] = ExRecordBuf[OutRecordIndex].Data.Pid[10]; + TxMsg.DS.Data[15] = ExRecordBuf[OutRecordIndex].Data.Pid[11]; + TxMsg.DS.Data[16] = ExRecordBuf[OutRecordIndex].Data.CtlNum; + TxMsg.DS.Data[17] = ExRecordBuf[OutRecordIndex].Data.UnitNum; + TxMsg.DS.Data[18] = ExRecordBuf[OutRecordIndex].Data.DeviceNum; + TxMsg.DS.Data[19] = ExRecordBuf[OutRecordIndex].Data.ChannelNum; + TxMsg.DS.Data[20] = (ExRecordBuf[OutRecordIndex].Data.DeviceCode & 0xFF); + TxMsg.DS.Data[21] = ((ExRecordBuf[OutRecordIndex].Data.DeviceCode>>8) & 0xFF); + TxMsg.DS.Data[22] = (ExRecordBuf[OutRecordIndex].Data.EventCode & 0xFF); + TxMsg.DS.Data[23] = ((ExRecordBuf[OutRecordIndex].Data.EventCode>>8) & 0xFF); + TxMsg.DS.Data[24] = (ExRecordBuf[OutRecordIndex].Data.StateCode.D16 & 0xFF); + TxMsg.DS.Data[25] = ((ExRecordBuf[OutRecordIndex].Data.StateCode.D16>>8) & 0xFF); + TxMsg.DS.Data[26] = ExRecordBuf[OutRecordIndex].Data.Year; + TxMsg.DS.Data[27] = ExRecordBuf[OutRecordIndex].Data.Mon; + TxMsg.DS.Data[28] = ExRecordBuf[OutRecordIndex].Data.Day; + TxMsg.DS.Data[29] = ExRecordBuf[OutRecordIndex].Data.Hour; + TxMsg.DS.Data[30] = ExRecordBuf[OutRecordIndex].Data.Min; + TxMsg.DS.Data[31] = ExRecordBuf[OutRecordIndex].Data.Sec; + + TxSetFlag = 1; + }else + /* + if(10 == send_tick){ + TxMsg.DS.Cmd = exHeartBeat; + TxMsg.DS.Len = 0; + + TxSetFlag = 1; + }else + */ + if(200 == send_tick){ + TxMsg.DS.Cmd = exGetErrState; + TxMsg.DS.Len = 0; + + TxSetFlag = 1; + } + } +} + +void TexRecord::Task10Ms() +{ + oCmdInsert(); + + oBufProcess(); +} + +void TexRecord::Task1000Ms() +{ + if(OnlineTick < 30){ + OnlineTick++; + }else{ + ErrState.Body.OffLine = 1; + ReadyFlag = 0; + } + + if(ErrState.D32){ + if(ErrReport.D32 == 0){ + CtlCenter.ieAddDevFault(dDevFaultExStroge,0); + ErrReport.D32 = 0x6601; + } + }else{ + if(ErrReport.D32 != 0){ + CtlCenter.ieAddDevFaultCancel(dDevFaultExStroge,0); + ErrReport.D32 = 0; + } + } +} + diff --git a/MyCode/src/exRecord.h b/MyCode/src/exRecord.h new file mode 100644 index 0000000..274717c --- /dev/null +++ b/MyCode/src/exRecord.h @@ -0,0 +1,192 @@ +#ifndef EXRECORD_H_ +#define EXRECORD_H_ + +#include "gType.h" +#include "TDateTime.h" +#include "ProtoFecBus.h" +#include "record.h" + +#define EXRECORDBUFDEEP 1024 +//#define dExRecordCmdIdf 0xB7 +//#define dExRecordReport 0xA6 + +typedef enum +{ + exNoCmd = (unsigned char)0x00,//没有 + + exHeartBeat = (unsigned char)0x20,//心跳回复 + + exGetModle = (unsigned char)0x40,//读取型号 + exGetVer = (unsigned char)0x50,//读取版本 + exSetCtlMsg = (unsigned char)0x51,//写入连接控制器信息 + exGetCtlMsg = (unsigned char)0x52,//读取连接控制器信息 + exGetErrState = (unsigned char)0x53,//查询存储器故障状态 + + exGetTotalRecordNum = (unsigned char)0x60,//读取总信息数量 + exWriteRecord = (unsigned char)0x61,//写入信息 + exReadRecordOrder = (unsigned char)0x62,//读取第几条信息 + exClearRecord = (unsigned char)0x63,//清空信息 +}exCmdTypeDef; + +typedef enum +{ + exErrCom = (unsigned char)0x01,//通讯故障 离线 + exErrSave = (unsigned char)0x02,//存储器故障 + exErrComSave = (unsigned char)0x04,//记录通讯故障 +}exErrTypeDef; + +typedef union{ + unsigned int D32[10]; + unsigned char D8[40]; + struct{ + unsigned char Cmd; + unsigned char Len; + //unsigned short Order; + + unsigned char Data[38]; + }DS; +}TMemComBufBody; + +typedef union{ + unsigned int D32[8]; + unsigned char D8[32]; + struct{ + unsigned char MsgType ;//信息类型 + unsigned char CtlAddr; + unsigned short CtlType; + + unsigned char Pid[12]; + + unsigned char CtlNum ;//控制器编号（1字节） + unsigned char UnitNum ;//单元编号（1字节） + unsigned char DeviceNum ; //设备编号（1字节） + unsigned char ChannelNum ; //通道编号（1字节） + + unsigned short DeviceCode ; //设备类型代码（2字节） + unsigned short EventCode ; //事件代码（2字节） + + TFecStateCode StateCode ; //状态代码（2字节） + unsigned char Year ;//年（1字节） + unsigned char Mon;//月（1字节） + + unsigned char Day;//日（1字节） + unsigned char Hour;//时（1字节） + unsigned char Min;//分（1字节） + unsigned char Sec;//秒（1字节） + }Data; +}TMemBufBody; + +class TexRecord{ + public: + unsigned int RxGetFlag; + TMemComBufBody RxMsg; + + unsigned int TxSetFlag; + TMemComBufBody TxMsg; + + unsigned int GetVerFlag; + unsigned int GetModleFlag; + + unsigned int InRecordIndex; + unsigned int OutRecordIndex; + TMemBufBody ExRecordBufTemp; + TMemBufBody ExRecordBuf[EXRECORDBUFDEEP]; + + struct{ + unsigned char State; + unsigned char AckOk; + unsigned char OnGoing; + unsigned char Order; + unsigned char RetryTimes; + unsigned char RetryFLAG; + unsigned short TimeOutTick; + }OnTransmite; + + union{ + unsigned int D32; + struct{ + unsigned char OffLine; + unsigned char ReadWriteFail; + unsigned char Rsv0; + unsigned char Rsv1; + }Body; + }ErrState, ErrReport; + + unsigned int OnlineTick; + unsigned int ReadyFlag; + + public: + TexRecord(){}; + void Init(); + + void getExRecordTime(TRecordCommon aRC); + void getExRecordStateCode(unsigned short StateCode); + void setExRecordStateCode(unsigned short StateCode); + + + void SetStateCodeAll(); + void SetStateCodeAutoManual(); + void SetStateCodePsOnActive(); + void SetStateCodePsError(); + void SetStateCodeFire(); + void SetStateCodeStart(); + void SetStateCodeFeedBack(); + void SetStateCodeSv(); + void SetStateCodeFault(); + void SetStateCodeMask(); + + void getExRecordDeviceCode(unsigned char dType); + + void getExRecordEpFaultEvent(unsigned char aType, unsigned char State); + + void getExRecordFaultBrdDeviceCode(unsigned char aType); + void getExRecordFaultBrdEventCode(unsigned char aType, unsigned char State); + void getExRecordFaultDevDeviceCode(unsigned char aType); + void getExRecordFaultDevEventCode(unsigned char aType, unsigned char State); + + void oBufInsert(); + void oBufInsert(TMemComBufBody aNsBuf); + void iBufInsert(); + void iBufProcess(); + void oBufProcess(); + + void iRecordBufInsert(unsigned char * pdata); + + void iExRecordFireInsert(TRecordCommon aRC); + void iExRecordFaultInsert(TRecordCommon aRC); + + void iExRecordLinkageInsert(TRecordCommon aRC); + void iExRecordOperateInsert(TRecordCommon aRC); + void iExRecordSvInsert(TRecordCommon aRC); + + void oCmdInsert(); + + void Task10Ms(); + void Task1000Ms(); +}; + + + + + + + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/gType.h b/MyCode/src/gType.h new file mode 100644 index 0000000..a57454a --- /dev/null +++ b/MyCode/src/gType.h @@ -0,0 +1,629 @@ +#ifndef GTYPE_H_ +#define GTYPE_H_ + +#define dBoardFaultTypeMax 48 + +#define dEpStateBitFire 0x01 +#define dEpStateBitStart 0x02 +#define dEpStateBitFeedBack 0x04 +#define dEpStateBitFbMiss 0x08 +#define dEpStateBitMask 0x10 +#define dEpStateBitFault 0x20 +#define dEpStateBitSv 0x40 +#define dEpStateBitDelayStart 0x80 + +#define dgTYPE_POWER_SUPPLY 1 +#define dgTYPE_BATTERY 2 + +#define dgTYPE_COMM_GRAPH 3 +#define dgTYPE_COMM_CAN 4 +#define dgTYPE_COMM_MULTI 5 + +#define dgTYPE_LCD_BOARD 6 +#define dgTYPE_KEY_BOARD_1 7 +#define dgTYPE_KEY_BOARD_2 8 + +#define dgTYPE_MOTHER_BOARD 9 +#define dgTYPE_HAND_CTL 10 +#define dgTYPE_DIRECT_CTL 11 +#define dgTYPE_PORT 12 + +#define dgTYPE_ROOT_UNDEFINE 0 +#define dgTYPE_ROOT_PORT 1 +#define dgTYPE_ROOT_HAND_CTL 2 +#define dgTYPE_ROOT_DIRECT_CTL 3 + + + +#define dgTYPE_COMM_CHANNEL 13 +#define dgTYPE_HAND_CTL_CHANNEL 14 +#define dgTYPE_DIRECT_CTL_CHANNEL 15 + + + + + +//#define dgTYPE_QUAKE_DETECTOR_I + +#define dgTYPE_EXTCURRENT_SENSOR_CHANNEL 31 + +#define dgTYPE_MAX 32 + +#define dgTYPE_CTL 255 + + +#define dAssign_iType_Undefine 0 +#define dAssign_iType_ExtSmoke 1 +#define dAssign_iType_ExtTempe 2 +#define dAssign_iType_ExtHandReport 3 +#define dAssign_iType_PowerLost 4 +#define dAssign_iType_PressureLow 5 +#define dAssign_iType_FlowRateLow 6 +#define dAssign_iType_HydrantActive 7 +#define dAssign_iType_NullMax 8 + +#define dAssign_oType_Undefine 0 +#define dAssign_oType_Watering 1 +#define dAssign_oType_WaterPumpStart 2 +#define dAssign_oType_FireDoorAction 3 +#define dAssign_oType_FireDoorOpen 4 +#define dAssign_oType_FireDoorClose 5 +#define dAssign_oType_SoundOn 6 +#define dAssign_oType_VisibleOn 7 +#define dAssign_oType_SoundVisibleOn 8 +#define dAssign_oType_FireElevatorOn 9 +#define dAssign_oType_SmokeExhaustOn 10 +#define dAssign_oType_FireRollerShutterOn 11 +#define dAssign_oType_RainOn 12 +#define dAssign_oType_NullMax 13 + + +//Color Define + // standard colors +#define clNearBlack 0xFF101010 +#define clNearWhite 0xFFF0F0F0 + +#define clBlack 0xFF000000 +#define clMaroon 0xFF800000 +#define clGreen 0xFF00FF00 +#define clOlive 0xFF808000 +#define clNavy 0xFF000080 +#define clPurple 0xFF800080 +#define clTeal 0xFF008080 +#define clGray 0xFF808080 +#define clSilver 0xFFC0C0C0 +#define clRed 0xFFFF0000 +#define clLime 0xFF00FF00 +#define clYellow 0xFFFFFF00 +#define clBlue 0xFF0000FF +#define clFuchsia 0xFFFF00FF +#define clAqua 0xFF00FFFF +#define clLtGray 0xFFC0C0C0 // clSilver alias +#define clWhite 0xFFFFFFFF + +#define clMoneyGreen 0xFFC0DCC0 +#define clSkyBlue 0xFFA6CAF0 +#define clCream 0xFFFFFBF0 + + +#define clMedOrange 0xFFA56600 +#define clMedYellow 0xFFAAAA00 +#define clMedGreen 0xFF008000 +#define clMedBlue 0xFF0000AA +#define clMedGray 0xFF707070 +#define clMedAqua 0xFF008080 + +#define clDeepGray 0xFF606060 +#define clDeepRed 0xFF770000 +#define clDeepOrange 0xFFA56600 +#define clDeepYellow 0xFF777700 +#define clDeepGreen 0xFF007700 +#define clDeepBlue 0xFF000077 + +#define clDarkkGray 0xFF505050 // clGray alias +#define clDarkBlue 0xFF000055 +#define clDarkYellow 0xFF555500 + +#define clOrange 0xFFFF9E00 +#define clRedOrange 0xFFFF5F00 +#define clFrmFace 0xFFDCDCDC + + +#define clNearNearWhite 0xFFE0E0E0 +#define clNearMoneyGreen 0xFFD0ECD0 +#define clNearTeal 0xFF006060 + +#define clWhiteBlue 0xFFF0F0FF +#define clWhiteGray 0xFFA7A7A7 +#define clWhiteRed 0xFFFF8080 + +#define cldRed 0xFFC80C02 +#define cldMaroon 0xFF800020 +#define cldOrange 0xFFFF8040 +#define cldYellow 0xFFA4A400 + +#define clShallowRed 0xFFFFDFDF +#define clShallowGreen 0xFFDFFFDF +#define clShallowBlue 0xFFDFDFFF + + + +//________________________________________________ +#define VK_NONE 0 +#define VK_LBUTTON 1 //$01 Linke Maustaste +#define VK_RBUTTON 2 //$02 Rechte Maustaste +#define VK_CANCEL 3 //$03 Für die Verarbeitung von Control-Break +#define VK_MBUTTON 4 //$04 Mittlere Maustaste (Dreitastenmaus) +//-- +#define VK_BACK 8 //$08 Taste: BACKSPACE +#define VK_TAB 9 //$09 Taste: TAB +#define VK_EN_CN 10 +//-- +#define VK_CLEAR 12 //$0C Taste: L?sch / Entf +#define VK_RETURN 13 //$0D Taste: RETURN +//-- +#define VK_SHIFT 16 //$10 Taste: SHIFT +#define VK_CONTROL 17 //$11 Taste: STRG +#define VK_MENU 18 //$12 Taste: ALT +#define VK_PAUSE 19 //$13 Taste: PAUSE +#define VK_CAPITAL 20 //$14 Taste: CAPS LOCK +#define VK_KANA 21 //$15 Reserviert für Kanji-Systeme +#define VK_HANGUL 21 //$15 Reserviert für Kanji-Systeme +//-- +#define VK_JUNJA 23 //$17 Reserviert für Kanji-Systeme +#define VK_FINAL 24 //$18 Reserviert für Kanji-Systeme +#define VK_KANJI 25 //$19 Reserviert für Kanji-Systeme +//-- +#define VK_ESCAPE 27 //$1B Taste: ESC +#define VK_CONVERT 28 //$1C Reserviert für Kanji-Systeme +#define VK_NONCONVERT 29 //$1D Reserviert für Kanji-Systeme +#define VK_ACCEPT 30 //$1E Reserviert für Kanji-Systeme +#define VK_MODECHANGE 31 //$1F Reserviert für Kanji-Systeme +#define VK_SPACE 32 //$20 Taste: LEERTASTE +#define VK_PRIOR 33 //$21 Taste: PAGE UP +#define VK_NEXT 34 //$22 Taste: PAGE DOWN +#define VK_END 35 //$23 Taste: ENDE +#define VK_HOME 36 //$24 Taste: POS1 / Home +#define VK_LEFT 37 //$25 Cursortaste: links +#define VK_UP 38 //$26 Cursortaste: oben +#define VK_RIGHT 39 //$27 Cursortaste: rechts +#define VK_DOWN 40 //$28 Cursortaste: unten +#define VK_SELECT 41 //$29 Taste: SELECT +#define VK_PRINT 42 //$2A Taste: Druck +#define VK_EXECUTE 43 //$2B Taste: Ausführen (EXECUTE) +#define VK_SNAPSHOT 44 //$2C Taste: PRINT SCREEN +#define VK_INSERT 45 //$2D Taste: EINFG +#define VK_DELETE 46 //$2E Taste: ENTF +#define VK_HELP 47 //$2F Taste: Hilfetaste +#define VK_0 48 //$30 Taste: 0 +#define VK_1 49 //$31 Taste: 1 +#define VK_2 50 //$32 Taste: 2 +#define VK_3 51 //$33 Taste: 3 +#define VK_4 52 //$34 Taste: 4 +#define VK_5 53 //$35 Taste: 5 +#define VK_6 54 //$36 Taste: 6 +#define VK_7 55 //$37 Taste: 7 +#define VK_8 56 //$38 Taste: 8 +#define VK_9 57 //$39 Taste: 9 +//-- +#define VK_A 65 //$41 Taste: A +#define VK_B 66 //$42 Taste: B +#define VK_C 67 //$43 Taste: C +#define VK_D 68 //$44 Taste: D +#define VK_E 69 //$45 Taste: E +#define VK_F 70 //$46 Taste: F +#define VK_G 71 //$47 Taste: G +#define VK_H 72 //$48 Taste: H +#define VK_I 73 //$49 Taste: I +#define VK_J 74 //$4A Taste: J +#define VK_K 75 //$4B Taste: K +#define VK_L 76 //$4C Taste: L +#define VK_M 77 //$4D Taste: M +#define VK_N 78 //$4E Taste: N +#define VK_O 79 //$4F Taste: O +#define VK_P 80 //$50 Taste: P +#define VK_Q 81 //$51 Taste: Q +#define VK_R 82 //$52 Taste: R +#define VK_S 83 //$53 Taste: S +#define VK_T 84 //$54 Taste: T +#define VK_U 85 //$55 Taste: U +#define VK_V 86 //$56 Taste: V +#define VK_W 87 //$57 Taste: W +#define VK_X 88 //$58 Taste: X +#define VK_Y 89 //$59 Taste: Y +#define VK_Z 90 //$5A Taste: Z +#define VK_LWIN 91 //$5B Taste: Linke Windowstaste +#define VK_RWIN 92 //$5C Taste: Rechte Windowstaste +#define VK_APPS 93 //$5D Taste: Application-Taste +// -- +#define VK_SLEEP 95 //$5F Sleep +//-- +#define VK_NUMPAD0 96 //$60 Numerisches Tastenfeld, Taste: 0 +#define VK_NUMPAD1 97 //$61 Numerisches Tastenfeld, Taste: 1 +#define VK_NUMPAD2 98 //$62 Numerisches Tastenfeld, Taste: 2 +#define VK_NUMPAD3 99 //$63 Numerisches Tastenfeld, Taste: 3 +#define VK_NUMPAD4 100 //$64 Numerisches Tastenfeld, Taste: 4 +#define VK_NUMPAD5 101 //$65 Numerisches Tastenfeld, Taste: 5 +#define VK_NUMPAD6 102 //$66 Numerisches Tastenfeld, Taste: 6 +#define VK_NUMPAD7 103 //$67 Numerisches Tastenfeld, Taste: 7 +#define VK_NUMPAD8 104 //$68 Numerisches Tastenfeld, Taste: 8 +#define VK_NUMPAD9 105 //$69 Numerisches Tastenfeld, Taste: 9 +#define VK_MULTIPLY 106 //$6A Taste: Multiplikationstaste +#define VK_ADD 107 //$6B Taste: Numerisches Tastenfeld, Taste + +#define VK_SEPARATOR 108 //$6C Taste: Trenntaste +#define VK_SUBTRACT 109 //$6D Numerisches Tastenfeld, Taste: - +#define VK_DECIMAL 110 //$6E Numerisches Tastenfeld, Taste: * +#define VK_DIVIDE 111 //$6F Numerisches Tastenfeld, Taste: / +#define VK_F1 112 //$70 Taste: F1 +#define VK_F2 113 //$71 Taste: F2 +#define VK_F3 114 //$72 Taste: F3 +#define VK_F4 115 //$73 Taste: F4 +#define VK_F5 116 //$74 Taste: F5 +#define VK_F6 117 //$75 Taste: F6 +#define VK_F7 118 //$76 Taste: F7 +#define VK_F8 119 //$77 Taste: F8 +#define VK_F9 120 //$78 Taste: F9 +#define VK_F10 121 //$79 Taste: F10 +#define VK_F11 122 //$7A Taste: F11 +#define VK_F12 123 //$7B Taste: F12 +#define VK_F13 124 //$7C Taste: F13 +#define VK_F14 125 //$7D Taste: F14 +#define VK_F15 126 //$7E Taste: F15 +#define VK_F16 127 //$7F Taste: F16 +#define VK_F17 128 //$80 Taste: F17 +#define VK_F18 129 //$81 Taste: F18 +#define VK_F19 130 //$82 Taste: F19 +#define VK_F20 131 //$83 Taste: F20 +#define VK_F21 132 //$84 Taste: F21 +#define VK_F22 133 //$85 Taste: F22 +#define VK_F23 134 //$86 Taste: F23 +#define VK_F24 135 //$87 Taste: F24 +//-- +#define VK_NUMLOCK 144 //$90 Taste: NUM LOCK +#define VK_SCROLL 145 //$91 Taste: SCROLL LOCK / Rollen +#define VK_OEM_FJ_JISHO 146 //$92 Reserviert für Kanji-Systeme +#define VK_OEM_FJ_MASSHOU 147 //$93 Reserviert für Kanji-Systeme +#define VK_OEM_FJ_TOUROKU 148 //$94 Reserviert für Kanji-Systeme +#define VK_OEM_FJ_LOYA 149 //$95 Reserviert für Kanji-Systeme +#define VK_OEM_FJ_ROYA 150 //$96 Reserviert für Kanji-Systeme +//-- +#define VK_LSHIFT 160 //$A0 Taste: Linke Grossschreibtaste +#define VK_RSHIFT 161 //$A1 Taste: Rechte Grossschreibtaste +#define VK_LCONTROL 162 //$A2 Taste: Linke Steuertaste +#define VK_RCONTROL 163 //$A3 Taste: Rechte Steuertaste +#define VK_LMENU 164 //$A4 Taste: Linke Menü-Taste +#define VK_RMENU 165 //$A5 Taste: Rechte Menü-Taste +#define VK_BROWSER_BACK 166 //$A6 Taste: Browser zurück +#define VK_BROWSER_FORWARD 167 //$A7 Taste: Browser vorw?rts (forward) +#define VK_BROWSER_REFRESH 168 //$A8 Taste: Browser Refresh +#define VK_BROWSER_STOP 169 //$A9 Taste: Browser Stop +#define VK_BROWSER_SEARCH 170 //$AA Taste: Browser Search +#define VK_BROWSER_FAVORITES 171 //$AB Taste: Browser Favoriten +#define VK_BROWSER_HOME 172 //$AC Taste: Browser Home +//-- +#define VK_MEDIA_NEXT_TRACK 176 //$B0 Taste: n?chster Track +#define VK_MEDIA_PREV_TRACK 177 //$B1 Taste: vorhergehender Track +#define VK_MEDIA_STOP 178 //$B2 Taste: Stop +#define VK_MEDIA_PLAY_PAUSE 179 //$B3 Taste: Play / Pause +#define VK_LAUNCH_MAIL 180 //$B4 Taste: Mail +#define VK_LAUNCH_MEDIA_SELECT 181 //$B5 Taste: Media +#define VK_LAUNCH_APP1 182 //$B6 App1 +#define VK_LAUNCH_APP2 183 //$B7 Taste: ?? +//-- +#define VK_OEM_1 186 //$BA Taste: ü +#define VK_OEM_PLUS 187 //$BB Taste: + +#define VK_OEM_COMMA 188 //$BC Taste: , +#define VK_OEM_MINUS 189 //$BD Taste: - +#define VK_OEM_PERIOD 190 //$BE Taste: . +#define VK_OEM_2 191 //$BF Taste: # +#define VK_OEM_3 192 //$C0 Taste: ? +//-- +#define VK_OEM_4 219 //$DB Taste: ? +#define VK_OEM_5 220 //$DC Taste: ^ +#define VK_OEM_6 221 //$DD Taste: ′ +#define VK_OEM_7 222 //$DE Taste: ? +#define VK_OEM_8 223 //$DF Taste: ?? +//-- +#define VK_OEM_AX 225 //$E1 Taste: ?? +#define VK_OEM_102 226 //$E2 Taste: < +#define VK_ICO_HELP 227 //$E3 Taste: IcoHlp +#define VK_ICO_00 228 //$E4 Taste: ?? +#define VK_PROCESSKEY 229 //$E5 Taste: Process +#define VK_ICO_CLEAR 230 //$E6 Taste: IcoClr +#define VK_PACKET 231 //$E7 Taste: Packet +//-- +#define VK_OEM_RESET 233 //$E9 Taste: Reset +#define VK_OEM_JUMP 234 //$EA Taste: Jump +#define VK_OEM_Pa1 235 //$EB Taste: OemPa1 +#define VK_OEM_PA2 236 //$EC Taste: OemPa2 +#define VK_OEM_PA3 237 //$ED Taste: OemPa3 +#define VK_OEM_WSCTRL 238 //$EE Taste: WsCtrl +#define VK_OEM_CUSEL 239 //$EF Taste: Cu Sel +#define VK_OEM_ATTN 240 //$F0 Taste: Oem Attn +#define VK_OEM_FINISH 241 //$F1 Taste: Finish +#define VK_OEM_COPY 242 //$F2 Taste: Copy +#define VK_OEM_AUTO 243 //$F3 Taste: Auto +#define VK_OEM_ENLW 244 //$F4 Taste: Enlw +#define VK_OEM_BACKTAB 245 //$F5 Taste: Back Tab +#define VK_ATTN 246 //$F6 Taste: Attn +#define VK_CRSEL 247 //$F7 Taste: Cr Sel +#define VK_EXSEL 248 //$F8 Taste: Ex Sel +#define VK_EREOF 249 //$F9 Taste: Er Eof +#define VK_PLAY 250 //$FA Taste: Play +#define VK_ZOOM 251 //$FB Taste: Zoom +#define VK_NONAME 252 //$FC Taste: NoName +#define VK_PA1 253 //$FD Taste: Pa1 +#define VK_OEM_CLEAR 254 //$FE Taste: OEM-Clear +//____________________________________________________ + +typedef unsigned int u32; +typedef unsigned short u16; +typedef unsigned char u8; +typedef char c8; + +typedef int s32; +typedef short s16; + +typedef enum{ + EN = 0, + CN = 1 +}TInputMethod; + + + +typedef union{ + unsigned int D32; + struct{ + unsigned int Bit0 :1; + unsigned int Bit1 :1; + unsigned int Bit2 :1; + unsigned int Bit3 :1; + unsigned int Bit4 :1; + unsigned int Bit5 :1; + unsigned int Bit6 :1; + unsigned int Bit7 :1; + + unsigned int Bit8 :1; + unsigned int Bit9 :1; + unsigned int Bit10 :1; + unsigned int Bit11 :1; + unsigned int Bit12 :1; + unsigned int Bit13 :1; + unsigned int Bit14 :1; + unsigned int Bit15 :1; + + unsigned int Bit16 :1; + unsigned int Bit17 :1; + unsigned int Bit18 :1; + unsigned int Bit19 :1; + unsigned int Bit20 :1; + unsigned int Bit21 :1; + unsigned int Bit22 :1; + unsigned int Bit23 :1; + + unsigned int Bit24 :1; + unsigned int Bit25 :1; + unsigned int Bit26 :1; + unsigned int Bit27 :1; + unsigned int Bit28 :1; + unsigned int Bit29 :1; + unsigned int Bit30 :1; + unsigned int Bit31 :1; + }BitF; +}Tu32BitFiled; + +typedef union{ + unsigned short D16; + struct{ + unsigned short Bit0 :1; + unsigned short Bit1 :1; + unsigned short Bit2 :1; + unsigned short Bit3 :1; + unsigned short Bit4 :1; + unsigned short Bit5 :1; + unsigned short Bit6 :1; + unsigned short Bit7 :1; + + unsigned short Bit8 :1; + unsigned short Bit9 :1; + unsigned short Bit10 :1; + unsigned short Bit11 :1; + unsigned short Bit12 :1; + unsigned short Bit13 :1; + unsigned short Bit14 :1; + unsigned short Bit15 :1; + }BitF; +}Tu16BitFiled; + +typedef union{ + unsigned char D8; + struct{ + unsigned short Bit0 :1; + unsigned short Bit1 :1; + unsigned short Bit2 :1; + unsigned short Bit3 :1; + unsigned short Bit4 :1; + unsigned short Bit5 :1; + unsigned short Bit6 :1; + unsigned short Bit7 :1; + }BitF; +}Tu8BitFiled; + +typedef struct{ + unsigned char Second ; + unsigned char Minute ; + unsigned char Hour ; + unsigned char Day; + unsigned char Month; + unsigned char Year; +}TsDateTime; + +typedef union{ + unsigned short D16; + unsigned char D8[2]; +}TDMix16; + +typedef union{ + unsigned int D32; + unsigned short D16[2]; + unsigned char D8[4]; +}TDMix; + +typedef union{ + unsigned long long D64; + unsigned int D32[2]; +}TDMix64; + +typedef union{ + unsigned int Full; + struct{ + unsigned char RoomLowB; + unsigned char RoomHiB; + unsigned char Floor; + unsigned char Building; + }Spl; +}TUserCode; + +typedef union{ + volatile unsigned int Full; + struct + { + volatile unsigned int BcdText_0: 4; /* [1-0] */ + volatile unsigned int BcdText_1: 4; /* [1-0] */ + volatile unsigned int BcdText_2: 4; /* [1-0] */ + volatile unsigned int BcdText_3: 4; /* [1-0] */ + volatile unsigned int BcdText_4: 4; /* [1-0] */ + volatile unsigned int BcdText_5: 4; /* [1-0] */ + volatile unsigned int BcdText_6: 4; /* [1-0] */ + volatile unsigned int BcdText_7: 4; /* [1-0] */ + }Spl; +}TUserCodeStr; + +typedef union{ + unsigned int D32; + unsigned char D8[4]; + struct{ + unsigned int Cmd :8; + unsigned int dAddr :7; + unsigned int sAddr :7; + unsigned int dLvl :3; + unsigned int sLvl :2; + unsigned int Pri :2; + unsigned int Dump :3; + }BitF; +}TCanHeaderID; + +typedef enum{ + CnInputModeEn = 0, + CnInputModeSymbol = 1, + CnInputModeCn = 2, + CnInputModeNum = 3 +}TTextInputMode; + +class TFCBusTx { + public: + unsigned char data[128][32]; + unsigned char Dlen[128]; + unsigned char available[128]; + unsigned int IndexRead; + public: + TFCBusTx(void){ + unsigned int i; + IndexRead = 0; + for(i=0;i<128;i++){ + available[i] = 0; + Dlen[i] = 0; + } + } + int WriteOneMsg(unsigned char *pData, unsigned int aLen){ + unsigned int i,j; + if(aLen > 32){ aLen = 0; return 1;} + i = IndexRead;; + for(; i<128; i++){ + if(available[i] == 0){ + for(j=0;j<32;j++)data[i][j] = *pData++; + available[i] = 1; + Dlen[i] = aLen; + return 0; + } + } + for(i=0; i 32)len = 32; + for(j=0;j 32)len = 32; + for(j=0;j(4096)) + +#define EraseBlock64K_TryRusumeTime 20 + +#define dPRIMARY_KEY_WARNING_NUM (0x6FFF'FFFF'FFFF'FFFF) + +const unsigned char NwDescpUsingChip[68] = { +1, + 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, + 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, + 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, + 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, +1,1,1, +}; + +const unsigned int NwDescpUsingFlashAddr[68] = { +0x900000, + 0x2F0000,0x350000,0x3B0000,0x410000, 0x470000,0x4D0000,0x530000,0x590000, 0x5F0000,0x650000,0x6B0000,0x710000, 0x770000,0x7D0000,0x830000,0x890000, + 0x2F0000,0x350000,0x3B0000,0x410000, 0x470000,0x4D0000,0x530000,0x590000, 0x5F0000,0x650000,0x6B0000,0x710000, 0x770000,0x7D0000,0x830000,0x890000, + 0x2F0000,0x350000,0x3B0000,0x410000, 0x470000,0x4D0000,0x530000,0x590000, 0x5F0000,0x650000,0x6B0000,0x710000, 0x770000,0x7D0000,0x830000,0x890000, + 0x2F0000,0x350000,0x3B0000,0x410000, 0x470000,0x4D0000,0x530000,0x590000, 0x5F0000,0x650000,0x6B0000,0x710000, 0x770000,0x7D0000,0x830000,0x890000, + +0x900000, 0x900000, 0x900000 +}; + +void TRecord::Init() +{ + unsigned int i, ar,x; + iMsgRx.D32[0] = 0; + iMsgRx.D32[1] = 0; + iMsgRx.D32[2] = 0; + iMsgRx.D32[3] = 0; + + ar = dAddrSdWrite2FlashBufBase; + for(i=0; i<(dWrite2FlashMaxCount); i++){ + for(x=0; x<6; x++)*(volatile unsigned int*)(ar + (i*24 + x*4)) = 0x00000000; + } + ar = dAddrSdWrite2FlashBufLinkage; + for(i=0; i<(dWrite2FlashMaxCount); i++){ + for(x=0; x<6; x++)*(volatile unsigned int*)(ar + (i*24 + x*4)) = 0x00000000; + } + ar = dAddrSdWrite2FlashBufSv; + for(i=0; i<(dWrite2FlashMaxCount); i++){ + for(x=0; x<6; x++)*(volatile unsigned int*)(ar + (i*24 + x*4)) = 0x00000000; + } + ar = dAddrSdWrite2FlashBufFault; + for(i=0; i<(dWrite2FlashMaxCount); i++){ + for(x=0; x<6; x++)*(volatile unsigned int*)(ar + (i*24 + x*4)) = 0x00000000; + } + ar = dAddrSdWrite2FlashBufOperate; + for(i=0; i<(dWrite2FlashMaxCount); i++){ + for(x=0; x<6; x++)*(volatile unsigned int*)(ar + (i*24 + x*4)) = 0x00000000; + } +} + +void TRecord::DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick>>>> +void TRecord::FireAdd(TRecordCommon aRC) +{ + unsigned int SdramAddr; + Buf4Fire.WriteIndex++; + if(Buf4Fire.WriteIndex >= dWrite2FlashMaxCount){ + Buf4Fire.WriteIndex = 0; + } + SdramAddr = dAddrSdWrite2FlashBufFire + (Buf4Fire.WriteIndex * 24 ); + *(volatile unsigned int*)(SdramAddr + 0) = aRC.D32[0]; + *(volatile unsigned int*)(SdramAddr + 4) = aRC.D32[1]; + *(volatile unsigned int*)(SdramAddr + 8) = aRC.D32[2]; + *(volatile unsigned int*)(SdramAddr + 12) = aRC.D32[3]; + *(volatile unsigned int*)(SdramAddr + 16) = aRC.D32[4]; + *(volatile unsigned int*)(SdramAddr + 20) = aRC.D32[5]; + + DoPrint.FillFireText(aRC); + ExRecord.iExRecordFireInsert(aRC); + FecBusCRT.iFecBusCRTFireInsert(aRC); + + //Conv2Utf8Text(aRC); +} + +void TRecord::LinkageAdd(TRecordCommon aRC) +{ + unsigned int SdramAddr; + Buf4Linkage.WriteIndex++; + if(Buf4Linkage.WriteIndex >= dWrite2FlashMaxCount){ + Buf4Linkage.WriteIndex = 0; + } + SdramAddr = dAddrSdWrite2FlashBufLinkage + (Buf4Linkage.WriteIndex * 24 ); + *(volatile unsigned int*)(SdramAddr + 0) = aRC.D32[0]; + *(volatile unsigned int*)(SdramAddr + 4) = aRC.D32[1]; + *(volatile unsigned int*)(SdramAddr + 8) = aRC.D32[2]; + *(volatile unsigned int*)(SdramAddr + 12) = aRC.D32[3]; + *(volatile unsigned int*)(SdramAddr + 16) = aRC.D32[4]; + *(volatile unsigned int*)(SdramAddr + 20) = aRC.D32[5]; + + DoPrint.FillLinkageText(aRC); + ExRecord.iExRecordLinkageInsert(aRC); + FecBusCRT.iFecBusCRTLinkageInsert(aRC); +} + +void TRecord::SvAdd(TRecordCommon aRC) +{ + unsigned int SdramAddr; + Buf4Sv.WriteIndex++; + if(Buf4Sv.WriteIndex >= dWrite2FlashMaxCount){ + Buf4Sv.WriteIndex = 0; + } + SdramAddr = dAddrSdWrite2FlashBufSv + (Buf4Sv.WriteIndex * 24 ); + *(volatile unsigned int*)(SdramAddr + 0) = aRC.D32[0]; + *(volatile unsigned int*)(SdramAddr + 4) = aRC.D32[1]; + *(volatile unsigned int*)(SdramAddr + 8) = aRC.D32[2]; + *(volatile unsigned int*)(SdramAddr + 12) = aRC.D32[3]; + *(volatile unsigned int*)(SdramAddr + 16) = aRC.D32[4]; + *(volatile unsigned int*)(SdramAddr + 20) = aRC.D32[5]; + + DoPrint.FillSvText(aRC); + ExRecord.iExRecordSvInsert(aRC); + FecBusCRT.iFecBusCRTSvInsert(aRC); +} + +void TRecord::FaultAdd(TRecordCommon aRC) +{ + unsigned int SdramAddr; + Buf4Fault.WriteIndex++; + if(Buf4Fault.WriteIndex >= dWrite2FlashMaxCount){ + Buf4Fault.WriteIndex = 0; + } + SdramAddr = dAddrSdWrite2FlashBufFault + (Buf4Fault.WriteIndex * 24 ); + *(volatile unsigned int*)(SdramAddr + 0) = aRC.D32[0]; + *(volatile unsigned int*)(SdramAddr + 4) = aRC.D32[1]; + *(volatile unsigned int*)(SdramAddr + 8) = aRC.D32[2]; + *(volatile unsigned int*)(SdramAddr + 12) = aRC.D32[3]; + *(volatile unsigned int*)(SdramAddr + 16) = aRC.D32[4]; + *(volatile unsigned int*)(SdramAddr + 20) = aRC.D32[5]; + + DoPrint.FillFaultText(aRC); + ExRecord.iExRecordFaultInsert(aRC); + FecBusCRT.iFecBusCRTFaultInsert(aRC); +} + +void TRecord::OperateAdd(TRecordCommon aRC) +{ + unsigned int addr; + Buf4Operate.WriteIndex++; + if(Buf4Operate.WriteIndex >= dWrite2FlashMaxCount){ + Buf4Operate.WriteIndex = 0; + } + addr = dAddrSdWrite2FlashBufOperate + (Buf4Operate.WriteIndex * 24); + *(volatile unsigned int*)(addr + 0) = aRC.D32[0]; + *(volatile unsigned int*)(addr + 4) = aRC.D32[1]; + *(volatile unsigned int*)(addr + 8) = aRC.D32[2]; + *(volatile unsigned int*)(addr + 12) = aRC.D32[3]; + *(volatile unsigned int*)(addr + 16) = aRC.D32[4]; + *(volatile unsigned int*)(addr + 20) = aRC.D32[5]; + + DoPrint.FillOperateText(aRC); + ExRecord.iExRecordOperateInsert(aRC); + FecBusCRT.iFecBusCRTOperateInsert(aRC); +} + +void TRecord::OperateAddFromNw(TRecordCommon aRC) +{ + unsigned int addr; + Buf4Operate.WriteIndex++; + if(Buf4Operate.WriteIndex >= dWrite2FlashMaxCount){ + Buf4Operate.WriteIndex = 0; + } + addr = dAddrSdWrite2FlashBufOperate + (Buf4Operate.WriteIndex * 24); + *(volatile unsigned int*)(addr + 0) = aRC.D32[0]; + *(volatile unsigned int*)(addr + 4) = aRC.D32[1]; + *(volatile unsigned int*)(addr + 8) = aRC.D32[2]; + *(volatile unsigned int*)(addr + 12) = aRC.D32[3]; + *(volatile unsigned int*)(addr + 16) = aRC.D32[4]; + *(volatile unsigned int*)(addr + 20) = aRC.D32[5]; + + DoPrint.FillOperateText(aRC); + ExRecord.iExRecordOperateInsert(aRC); + FecBusCRT.iFecBusCRTOperateInsert(aRC); +} + +void TRecord::TryFireWriteToFlash() +{ +/* unsigned int SdramAddr; + unsigned int NewFound =0; + unsigned int aWI = 0; + unsigned int aPage; + unsigned int aSector; + unsigned int aState; + unsigned int FlashAddr; + unsigned int ToWriteBytesCount; + unsigned int aIndex; + + aState = nor_get_busy_state(0); + if(aState){ + //Check Not Done, then + WriteTickChipF1 = 5; + return; + } + + aState = CheckFireNextSector(); + if(aState){ + aIndex = BufFire.Writing_64KBlockIndex +1; + if(aIndex > (dFrashUsingBlockCount-1)){ + aIndex = 0; + } + //Erase Next Sector Here, and Set Chip0 State to Erasing 64K Sector + } + + if(BufFire.WritePageChanged){ + aState = CheckChipF1Idle(); + if(aState){ + //Not Idle return + return; + } + aPage = BufFire.NowPage + 1; + if(aPage > 15){ + aPage = 0; + aSector = BufFire.NowSector + 1; + if(aSector > (dfFireSectorCount - 1)){ + aSector = 0; + } + + //Read and Check Next Sector if Must Be Erase + FlashAddr= (aSector * 4096) + dfFire; + aState = CheckChipF1_SectorEmpty(FlashAddr); + + if(aState){ + //Not Need To Erase + BufFire.NowPage = aPage; + BufFire.NowSector = aSector; + }else{ + //Erase Here + //Do Erase + BufFire.NowPage = aPage; + BufFire.NowSector = aSector; + BufFire.Erasing = 1; + WriteTickChipF1 = 50; + } + }else{ + BufFire.NowPage = aPage; + } + BufFire.WritePageChanged = 0; + return; + } + + if(BufFire.IndexWriteFlash != BufFire.IndexAddOn){ + FlushToWriteBuf(); + } + aWI = BufFire.IndexWriteFlash; + if(aWI != BufFire.IndexAddOn){ + aIndex = BufFire.Writing_ItemIndex; + for(; aIndex <16; aIndex++){ + + + + + + aWI++; + if(aWI > dfOperateItemsCount)aWI = 0; + + SdramAddr = aWI * 16 + daSdramFire; + ToWriteBuf[aIndex][0] = *(unsigned int*)(SdramAddr + 0x00); + ToWriteBuf[aIndex][1] = *(unsigned int*)(SdramAddr + 0x04); + ToWriteBuf[aIndex][2] = *(unsigned int*)(SdramAddr + 0x08); + ToWriteBuf[aIndex][3] = *(unsigned int*)(SdramAddr + 0x0C); + NewFound++; + aIndex++; + if(aIndex > 15){ + BufFire.WritePageChanged =1; + aIndex = 0; + break; + } + } + // + + } + + if(NewFound){ + //get flash addr and to write Length + ToWriteBytesCount = NewFound * 16; + BufFire.FlashPageAddr = (BufFire.NowSector * 4096) + (BufFire.NowPage * 256) + (BufFire.IndexInPage * 16) + dfFire; + //Write Flash Here + if(1){ + //write succes + BufFire.IndexWriteFlash = aWI; + BufFire.IndexInPage = aIndex; + WriteTickChipE1 = 5; + } + }*/ +} + +void TRecord::LoadOperateEventDateTimeFromCharPointer(unsigned char *aDt) +{ + eOperateEvent.Splite.Year = *aDt++; + eOperateEvent.Splite.Month = *aDt++; + eOperateEvent.Splite.Day = *aDt++; + eOperateEvent.Splite.Hour = *aDt++; + eOperateEvent.Splite.Minute = *aDt++; + eOperateEvent.Splite.Second = *aDt++; +} + +//______________________________________________________________________________>>>>> +void TRecord::OperateAdd_PowerOff(unsigned char aCn, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otPowerOff; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_PowerUp(unsigned char aCn, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otPowerOn; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_Reset(unsigned char aCn, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otReset; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_Mute(unsigned char aCn, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otMute; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_Mask(TDMix aFullPath, unsigned char aDType, unsigned char *aDt, unsigned int aUserCode, unsigned short aAreaNum) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otMask; + eOperateEvent.Splite.dType = aDType; + + eOperateEvent.Splite.UserCode = aUserCode; + eOperateEvent.Splite.AreaNum = aAreaNum; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_UnMask(TDMix aFullPath, unsigned char aDType, unsigned char *aDt, unsigned int aUserCode, unsigned short aAreaNum) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otUnMask; + eOperateEvent.Splite.dType = aDType; + + eOperateEvent.Splite.UserCode = aUserCode; + eOperateEvent.Splite.AreaNum = aAreaNum; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_Registe(TDMix aFullPath, unsigned char aDType, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otRegiste; + eOperateEvent.Splite.dType = aDType; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_UnRegiste(TDMix aFullPath, unsigned char aDType, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otUnRegiste; + eOperateEvent.Splite.dType = aDType; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_SetCanNetwork(unsigned char aCn, unsigned char sAddr, unsigned char IsMaster, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = sAddr; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetCanNetwork; + eOperateEvent.Splite.Data1 = IsMaster; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_CfgBoard(TDMix aFullPath, unsigned char aDType, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgBoard; + eOperateEvent.Splite.dType = aDType; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_CfgCrt(unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgCrt; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_CfgPriter(unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgPriter; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_CfgPritEventType(unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgPriter; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_CfgDevice(TDMix aFullPath, unsigned char aDType, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgDevice; + eOperateEvent.Splite.dType = aDType; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_CfgDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.Splite.PCtlNum = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgDateTime; + + eOperateEvent.Splite.P0 = aY; + eOperateEvent.Splite.P1 = aM; + eOperateEvent.Splite.P2 = aD; + eOperateEvent.Splite.Data1 = aH; + eOperateEvent.Splite.iByte0 = aMin; + eOperateEvent.Splite.iByte1 = aSec; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_CfgPermissionAllow(unsigned char aPa, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgPermissionAllow; + eOperateEvent.Splite.Data1 = aPa; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AllowState(unsigned char aCn, unsigned char aAllowAuto, unsigned char aAllowManual, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otAllowSet; + eOperateEvent.Splite.Data1 = 0; + if(aAllowAuto)eOperateEvent.Splite.Data1 |= 0x01; + if(aAllowManual)eOperateEvent.Splite.Data1 |= 0x02; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AlramSoundOn(unsigned char aCn, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otAlramSetOnOff; + eOperateEvent.Splite.Data1 = 1; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AlramSoundOff(unsigned char aCn, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otAlramSetOnOff; + eOperateEvent.Splite.Data1 = 0; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_BusPadOn(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otBusPadOn; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_BusPadOff(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otBusPadOff; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadManualAllowOn(unsigned char aCn, unsigned char aP0, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadManualAllowOn; + eOperateEvent.Splite.Data1 = 0; + + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadManualAllowOff(unsigned char aCn, unsigned char aP0, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadManualAllowOff; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadNodeOn(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadNodeOn; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadNodeOff(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadNodeOff; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_UserCheck(unsigned char aCn, unsigned char OnOff, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otUserCheck; + + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = OnOff; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_LinkageGo(unsigned char aCn, unsigned char *aDt) +{ + LoadOperateEventDateTimeFromCharPointer(aDt); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otLinkageGo; + eOperateEvent.Splite.Data1 = 3; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} +//____________________________<> + +void TRecord::OperateAdd_PowerOff(unsigned char aCn) +{ + unsigned char Data[6]; + unsigned char cVal, cValOnes; + DelayMs(10); + eeprom_read_byte(0,dEepAddrCtlShutDownTime,Data,6); + eOperateEvent.Splite.Year = Data[5]; + eOperateEvent.Splite.Month = Data[4]; + eOperateEvent.Splite.Day = Data[3]; + eOperateEvent.Splite.Hour = Data[2]; + eOperateEvent.Splite.Minute = Data[1]; + eOperateEvent.Splite.Second = Data[0]; + + cVal = eOperateEvent.Splite.Year / 16 * 10; + cValOnes = eOperateEvent.Splite.Year % 16; + if(cValOnes >9)return; + cVal += cValOnes; + if( cVal > 99 )return; + + cVal = eOperateEvent.Splite.Month / 16 * 10; + cValOnes = eOperateEvent.Splite.Month % 16; + if(cValOnes >9)return; + cVal += cValOnes; + if( (cVal==0) || (cVal>12) )return; + + cVal = eOperateEvent.Splite.Day / 16 * 10; + cValOnes = eOperateEvent.Splite.Day % 16; + if(cValOnes > 9)return; + cVal += cValOnes; + if( (cVal==0) || (cVal>31) )return; + + cVal = eOperateEvent.Splite.Hour / 16 * 10; + cValOnes = eOperateEvent.Splite.Hour % 16; + if(cValOnes > 9)return; + cVal += cValOnes; + if(cVal>23)return; + + cVal = eOperateEvent.Splite.Minute / 16 * 10; + cValOnes = eOperateEvent.Splite.Minute % 16; + if(cValOnes >9)return; + cVal += cValOnes; + if(cVal>59)return; + + + cVal = eOperateEvent.Splite.Second / 16 * 10; + cValOnes = eOperateEvent.Splite.Second % 16; + if(cValOnes > 9)return; + cVal += cValOnes; + if(cVal>59)return; + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otPowerOff; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::LoadOperateEventDateTimeFromCurrent() +{ + eOperateEvent.Splite.Year = DateTime.Date.Split.Year; + eOperateEvent.Splite.Month = DateTime.Date.Split.Month; + eOperateEvent.Splite.Day = DateTime.Date.Split.Day; + eOperateEvent.Splite.Hour = DateTime.Time.Split.Hour; + eOperateEvent.Splite.Minute = DateTime.Time.Split.Minute; + eOperateEvent.Splite.Second = DateTime.Time.Split.Second; +} + +void TRecord::OperateAdd_PowerUp(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otPowerOn; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_Reset(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otReset; + eOperateEvent.Splite.Data1 = 0; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_Mute(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otMute; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2) + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_Mask(TDMix aFullPath, unsigned char aDT, unsigned int aUc) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otMask; + eOperateEvent.Splite.dType = aDT; + + eOperateEvent.Splite.UserCode = aUc; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_UnMask(TDMix aFullPath, unsigned char aDType, unsigned int aUc) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otUnMask; + eOperateEvent.Splite.dType = aDType; + + eOperateEvent.Splite.UserCode = aUc; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_Registe(unsigned char Sta) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otRegiste; + eOperateEvent.Splite.Data1 = Sta; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_UnRegiste(TDMix aFullPath, unsigned char aDType) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otUnRegiste; + eOperateEvent.Splite.dType = aDType; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_SetCanNetwork(unsigned char NwType, unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetCanNetwork; + eOperateEvent.Splite.Data1 = NwType; + + OperateAdd(eOperateEvent); + //if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgBoard(TDMix aFullPath, unsigned char aDType) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgBoard; + eOperateEvent.Splite.dType = aDType; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgCrt() +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgCrt; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgPriter(unsigned char aOnOff, unsigned int aEvevtInc) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgPriter; + eOperateEvent.Splite.Data1 = aOnOff; + eOperateEvent.Splite.P0 = aEvevtInc & 0x000000FF; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgPritEventType() +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgPriter; + eOperateEvent.Splite.Data1 = 1; + eOperateEvent.Splite.P0 = 0; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgDevice(TDMix aFullPath, unsigned char aDType) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aFullPath.D32; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgDevice; + eOperateEvent.Splite.dType = aDType; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgCircuitSmokeSensGrade(unsigned int aFullPath, unsigned char Grade) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aFullPath; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetSmokeSensViaCircuit; + eOperateEvent.Splite.Data1 = Grade; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgAddrSmokeSensGrade(unsigned int aFullPath, unsigned char Grade) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aFullPath; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetSmokeSensViaAddr; + eOperateEvent.Splite.Data1 = Grade; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + + +void TRecord::OperateAdd_CfgDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgDateTime; + + eOperateEvent.Splite.P0 = aY; + eOperateEvent.Splite.P1 = aM; + eOperateEvent.Splite.P2 = aD; + eOperateEvent.Splite.Data1 = aH; + eOperateEvent.Splite.iByte0 = aMin; + eOperateEvent.Splite.iByte1 = aSec; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_GetDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgDateTime; + + eOperateEvent.Splite.P0 = aY; + eOperateEvent.Splite.P1 = aM; + eOperateEvent.Splite.P2 = aD; + eOperateEvent.Splite.Data1 = aH; + eOperateEvent.Splite.iByte0 = aMin; + eOperateEvent.Splite.iByte1 = aSec; + + OperateAdd(eOperateEvent); + //ProtoC2C.PublishOperate(eOperateEvent); +} + + +void TRecord::OperateAdd_SetNwDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetNwTime; + + eOperateEvent.Splite.P0 = aY; + eOperateEvent.Splite.P1 = aM; + eOperateEvent.Splite.P2 = aD; + eOperateEvent.Splite.Data1 = aH; + eOperateEvent.Splite.iByte0 = aMin; + eOperateEvent.Splite.iByte1 = aSec; + + OperateAdd(eOperateEvent); + + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_ReqNwDateTime() +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otReqNwTime; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_CfgPermissionAllow(unsigned char aPa) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCfgPermissionAllow; + eOperateEvent.Splite.Data1 = aPa; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_ManualStart(unsigned int aPath, unsigned char aType, unsigned char aSubType) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aPath; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = aType; + eOperateEvent.Splite.Data1 = aSubType; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_ManualStartCancel(unsigned int aPath, unsigned char aType, unsigned char aSubType) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aPath; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = aType; + eOperateEvent.Splite.Data1 = aSubType; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_ManualFb(unsigned int aPath, unsigned char aType, unsigned char aSubType) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = aPath; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = aType; + eOperateEvent.Splite.Data1 = aSubType; + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_ManualAllowSet(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetManualAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 1){ + eOperateEvent.Splite.Data0 = otRemoteSetManualAllowState; + ProtoC2C.PublishOperate(eOperateEvent); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + eOperateEvent.Splite.Data0 = otReportManualAllowState; + ProtoC2C.PublishOperate(eOperateEvent); + } +} + +void TRecord::OperateAdd_AutoAllowSet(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetAutoAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 1){ + eOperateEvent.Splite.Data0 = otRemoteSetAutoAllowState; + ProtoC2C.PublishOperate(eOperateEvent); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + eOperateEvent.Splite.Data0 = otReportAutoAllowState; + ProtoC2C.PublishOperate(eOperateEvent); + } +} + +void TRecord::OperateAdd_ManualAllowRemoteSet(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otRemoteSetManualAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AllowSet(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSetAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 1){ + eOperateEvent.Splite.Data0 = otRemoteSetAllowState; + ProtoC2C.PublishOperate(eOperateEvent); + }else + if(MainCtl.fData.Split.NetworkMode == 2){ + eOperateEvent.Splite.Data0 = otReportAllowState; + ProtoC2C.PublishOperate(eOperateEvent); + } +} + +void TRecord::OperateAdd_AutoAllowRemoteSet(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otRemoteSetAutoAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AllowRemoteSet(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otRemoteSetAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_ManualAllowReport(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otReportManualAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AutoAllowReport(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otReportAutoAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AllowReport(unsigned char aCn, unsigned char aAllow) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otReportAllowState; + eOperateEvent.Splite.Data1 = aAllow; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_AlramSoundOn(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otAlramSetOnOff; + eOperateEvent.Splite.Data1 = 1; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + //ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_AlramSoundOff(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otAlramSetOnOff; + eOperateEvent.Splite.Data1 = 0; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + //ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_BusPadOn(unsigned char aCn, unsigned char aP0, unsigned char aP1) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otBusPadOn; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_BusPadOff(unsigned char aCn, unsigned char aP0, unsigned char aP1) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otBusPadOff; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadManualAllowOn(unsigned char aCn, unsigned char aP0) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadManualAllowOn; + eOperateEvent.Splite.Data1 = 0; + + + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadManualAllowOff(unsigned char aCn, unsigned char aP0) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadManualAllowOff; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadNodeOn(unsigned char aCn, unsigned char aP0, unsigned char aP1) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadNodeOn; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadNodeOff(unsigned char aCn, unsigned char aP0, unsigned char aP1) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 0; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadNodeOff; + eOperateEvent.Splite.Data1 = 0; + OperateAdd(eOperateEvent); + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_UserCheck(unsigned char aCn, unsigned char OnOff) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otUserCheck; + + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = OnOff; + + if(OnOff)OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_SelfCheck(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otSelfCheck; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_MasterLinkageGo(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otLinkageGo; + eOperateEvent.Splite.Data1 = 1; + + eOperateEvent.Splite.PCtlNum = aCn; + OperateAdd(eOperateEvent); + + eOperateEvent.Splite.Data1 = 3; + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_SlaveLinkageGo(unsigned char aCn) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otLinkageGo; + eOperateEvent.Splite.Data1 = 1; + + eOperateEvent.Splite.PCtlNum = aCn; + + OperateAdd(eOperateEvent); + + eOperateEvent.Splite.Data1 = 0; + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_FireConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc, unsigned char IsSim) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.P2 = 0; //prm + eOperateEvent.Splite.dType = aType; + + eOperateEvent.Splite.mType = etOperate; + if(IsSim == TControlCenter::LinkInputTypeFireSimulate){ + eOperateEvent.Splite.Data0 = otFireSimConfirm; + }else{ + eOperateEvent.Splite.Data0 = otFireConfirm; + } + + eOperateEvent.Splite.UserCode = aUc; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_FaultConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char dType, unsigned char fType, unsigned char Data1, unsigned int aUc) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = aCn; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.P2 = fType; + eOperateEvent.Splite.dType = dType; + eOperateEvent.Splite.Data1 = Data1; //Fault Type + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otFaultConfirm; + + eOperateEvent.Splite.UserCode = aUc; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperatePublic_FireRemoteConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned char IsSim) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.P2 = 0; + eOperateEvent.Splite.dType = aType; //prm + eOperateEvent.Splite.Data1 = aCn; + + eOperateEvent.Splite.mType = etOperate; + if(IsSim == TControlCenter::LinkInputTypeFireSimulate){ + eOperateEvent.Splite.Data0 = otFireSimRemoteConfirm; + }else{ + eOperateEvent.Splite.Data0 = otFireRemoteConfirm; + } + + ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperatePublic_FaultRemoteConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char dType, unsigned char fType, unsigned char Data1) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.P2 = fType; + eOperateEvent.Splite.dType = dType; //prm + eOperateEvent.Splite.Data1 = Data1; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otFaultRemoteConfirm; + + eOperateEvent.Splite.iByte0 = aCn; + + ProtoC2C.PublishOperate(eOperateEvent); +} + + +void TRecord::OperateAdd_CleanUp(unsigned char cType) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.Data1 = cType; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otCleanUp; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_LinkageExpsModify(unsigned char IsAdd, unsigned int eInx) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.Data1 = IsAdd; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otLinkageExpsSaveRemove; + + eOperateEvent.Splite.P0 = eInx / 256; + eOperateEvent.Splite.P1 = eInx % 256; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_BusPadModifyModify(unsigned char aP0, unsigned int aP1) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otBusPadModify; + + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_DirectPadModify(unsigned char aP0) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDirectPadModify; + + eOperateEvent.Splite.P0 = aP0; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_DescpModify(unsigned char aP0, unsigned char aP1) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otDescpModify; + + + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_PassWdModify(unsigned char aLvl) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otPassWdModify; + + eOperateEvent.Splite.Data1 = aLvl; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_RegisterByManual(unsigned char aP0, unsigned char sAddr, unsigned char eAddr, unsigned char aType, unsigned char IsAdd) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otRegisterByManual; + eOperateEvent.Splite.Data1 = IsAdd; + + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = sAddr; + eOperateEvent.Splite.P2 = eAddr; + eOperateEvent.Splite.dType = aType; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + +void TRecord::OperateAdd_AddRemoveNwCtl(unsigned char Act, unsigned char aCtlNum) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otAddRemoveNwCtl; + + eOperateEvent.Splite.Data1 = Act; + eOperateEvent.Splite.P0 = aCtlNum; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_RegCanNetwork(unsigned char NwType, unsigned char aCtlNum, unsigned char SlaveCount) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otRegCanNetwork; + + eOperateEvent.Splite.Data1 = NwType; + eOperateEvent.Splite.P0 = aCtlNum; + eOperateEvent.Splite.P1 = SlaveCount; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_StartStop(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned char IsSatrt) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otStartStop; + + eOperateEvent.Splite.Data1 = IsSatrt; + eOperateEvent.Splite.P0 = aP0; + eOperateEvent.Splite.P1 = aP1; + eOperateEvent.Splite.P2 = aCn; + eOperateEvent.Splite.dType = aType; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_ClearNetworkCfg() +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otClearNetworkCfg; + + eOperateEvent.Splite.Data1 = MainCtl.fData.Split.NetworkMode; + + OperateAdd(eOperateEvent); +} + +void TRecord::OperateAdd_BroadcastVa(unsigned char aPadNum, unsigned char aAddr, unsigned char aMode) +{ + LoadOperateEventDateTimeFromCurrent(); + + eOperateEvent.D32[2] = 1; + eOperateEvent.Splite.PCtlNum = MainCtl.fData.Split.MyNum; + eOperateEvent.Splite.P0 = aPadNum; + eOperateEvent.Splite.P1 = aAddr; + + eOperateEvent.Splite.mType = etOperate; + eOperateEvent.Splite.Data0 = otBroadcastVa; + + eOperateEvent.Splite.Data1 = aMode; + + OperateAdd(eOperateEvent); + if(MainCtl.fData.Split.NetworkMode == 2)ProtoC2C.PublishOperate(eOperateEvent); +} + + + +void TRecord::OperateAdd_ScreenKeyLock(unsigned char aScreenSave, unsigned char EnterSaveTime, unsigned char aLock, char *aCr) +{ + +} +//______________________________________________________________________________<<<<< + +//______________________________________________________________________________>>>>> + + +//______________________________________________________________________________>>>>> + +void TRecord::Task10Ms() +{ + Chip0Prc(); + Chip1Prc(); +} + +void TRecord::Task5000Ms() +{ + +} + +void FireFlushRuntimeDataArray() +{ + +} +//__________________________________________________________________________________________________ +void TRecord::GetFireEntry(int aInx) +{ + volatile unsigned int aAddr ,i; + unsigned int aCn, aP0, aP1; + aAddr = dAddrSdWrite2FlashBufFire + (aInx * 24); + EntryRead.fData.Body.D32[0] = *(volatile unsigned int *)(aAddr + 0); + EntryRead.fData.Body.D32[1] = *(volatile unsigned int *)(aAddr + 4); + EntryRead.fData.Body.D32[2] = *(volatile unsigned int *)(aAddr + 8); + EntryRead.fData.Body.D32[3] = *(volatile unsigned int *)(aAddr +12); + EntryRead.fData.UserCode = *(volatile unsigned int *)(aAddr +16); + if(EntryRead.fData.Body.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else + if( (EntryRead.fData.Body.Splite.PCtlNum) && (EntryRead.fData.Body.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = EntryRead.fData.Body.Splite.PCtlNum -1; + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } +} + +void TRecord::PrcFireWrite() +{ + int i, aReadInx ,OK, m; + unsigned int aAddr, aState, GotNew; + unsigned int aEntry, aPage, aBlock, aBlock2; + int BlockCount; + int EntryCount; + + + //Read Chip0 State Here + + if(RtChip0.Sta == csIdle){ + aState = nor_get_busy_state(dFlashFireChip); + if(aState != 0)return; + + GotNew = 0; + FlushToWriteBuf(); + aReadInx = Buf4Fire.ReadIndex; + aEntry = Buf4Fire.EntryX; + aPage = Buf4Fire.PageX; + aBlock = Buf4Fire.BlockX; + while(aReadInx != Buf4Fire.WriteIndex){ + aReadInx++; + if(aReadInx >= dWrite2FlashMaxCount){ + aReadInx = 0; + } + GetFireEntry(aReadInx); + if(EntryRead.fData.Body.D32[2] != 0){ + if(aEntry < dFlashEntryCountPerPage){ + ToWriteBuf[aEntry].D32[ 0] = EntryRead.D32[ 0]; + ToWriteBuf[aEntry].D32[ 1] = EntryRead.D32[ 1]; + ToWriteBuf[aEntry].D32[ 2] = EntryRead.D32[ 2]; + ToWriteBuf[aEntry].D32[ 3] = EntryRead.D32[ 3]; + ToWriteBuf[aEntry].D32[ 4] = EntryRead.D32[ 4]; + ToWriteBuf[aEntry].D32[ 5] = EntryRead.D32[ 5]; + ToWriteBuf[aEntry].D32[ 6] = EntryRead.D32[ 6]; + ToWriteBuf[aEntry].D32[ 7] = EntryRead.D32[ 7]; + ToWriteBuf[aEntry].D32[ 8] = EntryRead.D32[ 8]; + ToWriteBuf[aEntry].D32[ 9] = EntryRead.D32[ 9]; + ToWriteBuf[aEntry].D32[10] = EntryRead.D32[10]; + ToWriteBuf[aEntry].D32[11] = EntryRead.D32[11]; + ToWriteBuf[aEntry].D32[12] = EntryRead.D32[12]; + ToWriteBuf[aEntry].D32[13] = EntryRead.D32[13]; + ToWriteBuf[aEntry].D32[14] = EntryRead.D32[14]; + ToWriteBuf[aEntry].D32[15] = EntryRead.D32[15]; + GotNew ++; + aEntry ++; + } + if(aEntry >= dFlashEntryCountPerPage){ + aEntry =0; + aPage++; + if(aPage >= dFlashPageCountPerBlock){ + aPage = 0; + aBlock++; + if(aBlock >= dFrashFireUsingBlockCount)aBlock = 0; + Buf4Fire.NeedCheckBlockEmpty = 1; + Buf4Fire.BlockToBeErase = aBlock; + aBlock2 = Buf4Fire.BlockToBeErase +1; + if(aBlock2 >= dFrashFireUsingBlockCount)aBlock2 = 0; + Buf4Fire.BlockToBeErase2 = aBlock2; + Buf4Fire.NeedCheckBlockEmpty2 = 1; + } + break; + } + if( (0 == Buf4Fire.EntryX ) && (0 == Buf4Fire.PageX) ){ + //Check Writing Block if Empty + fAddr = dFlashFireBaseAddr + (dFlashBlockSize * Buf4Fire.BlockX); + nor_read_byte(dFlashFireChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Fire.NeedCheckBlockEmpty = 1; + Buf4Fire.BlockToBeErase = Buf4Fire.BlockX; + GotNew = 0; + } + //Check Next Block if Need Erase + aBlock2 = Buf4Fire.BlockX +1; + if(aBlock2 >= dFrashFireUsingBlockCount)aBlock2 = 0; + fAddr = dFlashFireBaseAddr + (dFlashBlockSize * aBlock2); + nor_read_byte(dFlashFireChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Fire.NeedCheckBlockEmpty2 = 1; + Buf4Fire.BlockToBeErase2 = aBlock2; + GotNew = 0; + } + + Buf4Fire.wBlockWriteToEep = Buf4Fire.BlockX; + Buf4Fire.NeedMarkWriteBlcokToEep = 1; + } + }else{ + continue; + } + } + if(GotNew){ + //write Here and Check Ok + aAddr = dFlashFireBaseAddr + (dFlashBlockSize * Buf4Fire.BlockX) + (dFlashPageSize * Buf4Fire.PageX) + (dFlashEntrySize * Buf4Fire.EntryX); + OK = 0; + for(i=Buf4Fire.EntryX; i= GotNew){ + break; + } + } + nor_write_byte_via_page(dFlashFireChip, aAddr, ToWriteBuf[Buf4Fire.EntryX].D8, GotNew * dFlashEntrySize); + + OK = 0; + aAddr = dSdramFireHistoryContentBaseAddr + (Buf4Fire.BlockX * SizeOf64K) + (Buf4Fire.PageX * SizeOfPage) + (Buf4Fire.EntryX * dFlashEntrySize); + for(i=Buf4Fire.EntryX; i= GotNew){ + break; + } + aAddr += dFlashEntrySize; + } + + //read Back To ToWriteBuf + if(1){ + OK = 1; + }else{ + OK = 0; + } + + //OK + if(OK){ + Buf4Fire.ReadIndex = aReadInx; + Buf4Fire.BlockX = aBlock; + Buf4Fire.PageX = aPage; + Buf4Fire.EntryX = aEntry; + + BlockCount = ((Buf4Fire.BlockX + dFrashFireUsingBlockCount) - Buf4Fire.sBlock ) % dFrashFireUsingBlockCount +1; + if(BlockCount > (dFrashFireUsingBlockCount -2)){ + Buf4Fire.sBlock = Buf4Fire.BlockX - (dFrashFireUsingBlockCount -3); + if(Buf4Fire.sBlock <0)Buf4Fire.sBlock += dFrashFireUsingBlockCount; + + BlockCount = dFrashFireUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Fire.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Fire.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Fire.Count = dSdramHistoryEntryCount; + }else{ + Buf4Fire.Count = EntryCount; + } + Buf4Fire.SdramAddrCurrent = dSdramFireHistoryContentBaseAddr + (Buf4Fire.BlockX * SizeOf64K) + (Buf4Fire.PageX * dFlashPageSize) + (Buf4Fire.EntryX * dFlashEntrySize); + Buf4Fire.SdramAddrStart = Buf4Fire.SdramAddrCurrent - (Buf4Fire.Count * 64); + if(Buf4Fire.SdramAddrStart < dSdramFireHistoryContentBaseAddr){ + Buf4Fire.SdramAddrStart = Buf4Fire.SdramAddrStart + dSdramHistoryBytesLength; + } + } + } + } +} +//_____________________________________________________________________________________________________ +void TRecord::GetLinkageEntry(int aInx) +{ + volatile unsigned int aAddr ,i; + unsigned int aCn, aP0, aP1; + aAddr = dAddrSdWrite2FlashBufLinkage + (aInx * 24); + EntryRead.fData.Body.D32[0] = *(volatile unsigned int *)(aAddr + 0); + EntryRead.fData.Body.D32[1] = *(volatile unsigned int *)(aAddr + 4); + EntryRead.fData.Body.D32[2] = *(volatile unsigned int *)(aAddr + 8); + EntryRead.fData.Body.D32[3] = *(volatile unsigned int *)(aAddr +12); + EntryRead.fData.UserCode = *(volatile unsigned int *)(aAddr +16); + if(EntryRead.fData.Body.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else + if( (EntryRead.fData.Body.Splite.PCtlNum) && (EntryRead.fData.Body.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = EntryRead.fData.Body.Splite.PCtlNum -1; + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } +} + +void TRecord::PrcLinkageWrite() +{ + int i, aReadInx ,OK, m; + unsigned int aAddr, aState, GotNew; + unsigned int aEntry, aPage, aBlock, aBlock2; + int BlockCount; + int EntryCount; + + + //Read Chip0 State Here + + if(RtChip0.Sta == csIdle){ + aState = nor_get_busy_state(0); + if(aState != 0)return; + + GotNew = 0; + FlushToWriteBuf(); + aReadInx = Buf4Linkage.ReadIndex; + aEntry = Buf4Linkage.EntryX; + aPage = Buf4Linkage.PageX; + aBlock = Buf4Linkage.BlockX; + while(aReadInx != Buf4Linkage.WriteIndex){ + aReadInx++; + if(aReadInx >= dWrite2FlashMaxCount){ + aReadInx = 0; + } + GetLinkageEntry(aReadInx); + if(EntryRead.fData.Body.D32[2] != 0){ + if(aEntry < dFlashEntryCountPerPage){ + ToWriteBuf[aEntry].D32[ 0] = EntryRead.D32[ 0]; + ToWriteBuf[aEntry].D32[ 1] = EntryRead.D32[ 1]; + ToWriteBuf[aEntry].D32[ 2] = EntryRead.D32[ 2]; + ToWriteBuf[aEntry].D32[ 3] = EntryRead.D32[ 3]; + ToWriteBuf[aEntry].D32[ 4] = EntryRead.D32[ 4]; + ToWriteBuf[aEntry].D32[ 5] = EntryRead.D32[ 5]; + ToWriteBuf[aEntry].D32[ 6] = EntryRead.D32[ 6]; + ToWriteBuf[aEntry].D32[ 7] = EntryRead.D32[ 7]; + ToWriteBuf[aEntry].D32[ 8] = EntryRead.D32[ 8]; + ToWriteBuf[aEntry].D32[ 9] = EntryRead.D32[ 9]; + ToWriteBuf[aEntry].D32[10] = EntryRead.D32[10]; + ToWriteBuf[aEntry].D32[11] = EntryRead.D32[11]; + ToWriteBuf[aEntry].D32[12] = EntryRead.D32[12]; + ToWriteBuf[aEntry].D32[13] = EntryRead.D32[13]; + ToWriteBuf[aEntry].D32[14] = EntryRead.D32[14]; + ToWriteBuf[aEntry].D32[15] = EntryRead.D32[15]; + GotNew ++; + aEntry ++; + } + if(aEntry >= dFlashEntryCountPerPage){ + aEntry =0; + aPage++; + if(aPage >= dFlashPageCountPerBlock){ + aPage = 0; + aBlock++; + if(aBlock >= dFrashLinkageUsingBlockCount)aBlock = 0; + Buf4Linkage.NeedCheckBlockEmpty = 1; + Buf4Linkage.BlockToBeErase = aBlock; + aBlock2 = Buf4Linkage.BlockToBeErase +1; + if(aBlock2 >= dFrashLinkageUsingBlockCount)aBlock2 = 0; + Buf4Linkage.BlockToBeErase2 = aBlock2; + Buf4Linkage.NeedCheckBlockEmpty2 = 1; + } + break; + } + if( (0 == Buf4Linkage.EntryX ) && (0 == Buf4Linkage.PageX) ){ + //Check Writing Block if Empty + fAddr = dFlashLinkageBaseAddr + (dFlashBlockSize * Buf4Linkage.BlockX); + nor_read_byte(0, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Linkage.NeedCheckBlockEmpty = 1; + Buf4Linkage.BlockToBeErase = Buf4Linkage.BlockX; + GotNew = 0; + } + //Check Next Block if Need Erase + aBlock2 = Buf4Linkage.BlockX +1; + if(aBlock2 >= dFrashLinkageUsingBlockCount)aBlock2 = 0; + fAddr = dFlashLinkageBaseAddr + (dFlashBlockSize * aBlock2); + nor_read_byte(0, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Linkage.NeedCheckBlockEmpty2 = 1; + Buf4Linkage.BlockToBeErase2 = aBlock2; + GotNew = 0; + } + + Buf4Linkage.wBlockWriteToEep = Buf4Linkage.BlockX; + Buf4Linkage.NeedMarkWriteBlcokToEep = 1; + } + }else{ + continue; + } + } + if(GotNew){ + //write Here and Check Ok + aAddr = dFlashLinkageBaseAddr + (dFlashBlockSize * Buf4Linkage.BlockX) + (dFlashPageSize * Buf4Linkage.PageX) + (dFlashEntrySize * Buf4Linkage.EntryX); + OK = 0; + for(i=Buf4Linkage.EntryX; i= GotNew){ + break; + } + } + nor_write_byte_via_page(0, aAddr, ToWriteBuf[Buf4Linkage.EntryX].D8, GotNew * dFlashEntrySize); + + OK = 0; + aAddr = dSdramLinkageHistoryContentBaseAddr + (Buf4Linkage.BlockX * SizeOf64K) + (Buf4Linkage.PageX * SizeOfPage) + (Buf4Linkage.EntryX * dFlashEntrySize); + for(i=Buf4Linkage.EntryX; i= GotNew){ + break; + } + aAddr += dFlashEntrySize; + } + + //read Back To ToWriteBuf + if(1){ + OK = 1; + }else{ + OK = 0; + } + + //OK + if(OK){ + Buf4Linkage.ReadIndex = aReadInx; + Buf4Linkage.BlockX = aBlock; + Buf4Linkage.PageX = aPage; + Buf4Linkage.EntryX = aEntry; + + BlockCount = ((Buf4Linkage.BlockX + dFrashLinkageUsingBlockCount) - Buf4Linkage.sBlock ) % dFrashLinkageUsingBlockCount +1; + if(BlockCount > (dFrashLinkageUsingBlockCount -2)){ + Buf4Linkage.sBlock = Buf4Linkage.BlockX - (dFrashLinkageUsingBlockCount -3); + if(Buf4Linkage.sBlock <0)Buf4Linkage.sBlock += dFrashLinkageUsingBlockCount; + + BlockCount = dFrashLinkageUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Linkage.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Linkage.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Linkage.Count = dSdramHistoryEntryCount; + }else{ + Buf4Linkage.Count = EntryCount; + } + Buf4Linkage.SdramAddrCurrent = dSdramLinkageHistoryContentBaseAddr + (Buf4Linkage.BlockX * SizeOf64K) + (Buf4Linkage.PageX * dFlashPageSize) + (Buf4Linkage.EntryX * dFlashEntrySize); + Buf4Linkage.SdramAddrStart = Buf4Linkage.SdramAddrCurrent - (Buf4Linkage.Count * 64); + if(Buf4Linkage.SdramAddrStart < dSdramLinkageHistoryContentBaseAddr){ + Buf4Linkage.SdramAddrStart = Buf4Linkage.SdramAddrStart + dSdramHistoryBytesLength; + } + } + } + } +} +//_____________________________________________________________________________________________________________________________________________________________________________ +void TRecord::Chip0Prc() +{ + unsigned int aAddr, aState; + if(RtChip0.Sta == csIdle){ + if(RtChip0.FireOrSv){ + //Process Fire Here + RtChip0.FireOrSv = 0; + if(Buf4Fire.NeedCheckBlockEmpty){ + aState = nor_get_busy_state(0); + if(aState == 0){ + aAddr = dFlashFireBaseAddr + (dFlashBlockSize * Buf4Fire.BlockToBeErase); + nor_erase_sector_64k(dFlashFireChip,aAddr); + RtChip0.Sta = csErassing; + Buf4Fire.NeedCheckBlockEmpty = 0; + } + }else + if(Buf4Fire.NeedCheckBlockEmpty2){ + aState = nor_get_busy_state(0); + if(aState == 0){ + aAddr = dFlashFireBaseAddr + (dFlashBlockSize * Buf4Fire.BlockToBeErase2); + nor_erase_sector_64k(dFlashFireChip,aAddr); + RtChip0.Sta = csErassing; + Buf4Fire.NeedCheckBlockEmpty2 = 0; + } + }else{ + if(Buf4Fire.ReadIndex != Buf4Fire.WriteIndex){ + PrcFireWrite(); + } + } + if(Buf4Fire.NeedMarkWriteBlcokToEep){ + Wait10Ms(); + eeprom_write_byte_via_page(0, dEepAddrFireWritingBlock, &Buf4Fire.wBlockWriteToEep, 1); + Wait10Ms(); + Buf4Fire.NeedMarkWriteBlcokToEep = 0; + } + }else{ + //Process Start Here + RtChip0.FireOrSv = 1; + if(Buf4Linkage.NeedCheckBlockEmpty){ + aState = nor_get_busy_state(0); + if(aState == 0){ + aAddr = dFlashLinkageBaseAddr + (dFlashBlockSize * Buf4Linkage.BlockToBeErase); + nor_erase_sector_64k(dFlashLinkageChip,aAddr); + RtChip0.Sta = csErassing; + Buf4Linkage.NeedCheckBlockEmpty = 0; + } + }else + if(Buf4Linkage.NeedCheckBlockEmpty2){ + aState = nor_get_busy_state(0); + if(aState == 0){ + aAddr = dFlashLinkageBaseAddr + (dFlashBlockSize * Buf4Linkage.BlockToBeErase2); + nor_erase_sector_64k(dFlashLinkageChip,aAddr); + RtChip0.Sta = csErassing; + Buf4Linkage.NeedCheckBlockEmpty2 = 0; + } + }else{ + if(Buf4Linkage.ReadIndex != Buf4Linkage.WriteIndex){ + PrcLinkageWrite(); + } + } + if(Buf4Linkage.NeedMarkWriteBlcokToEep){ + Wait10Ms(); + eeprom_write_byte_via_page(0, dEepAddrLinkageWritingBlock, &Buf4Linkage.wBlockWriteToEep, 1); + Wait10Ms(); + Buf4Linkage.NeedMarkWriteBlcokToEep = 0; + } + } + }else + if(RtChip0.Sta == csCanTryResume){ + if(0 == nor_get_busy_state(0)){ + RtChip0.Sta = csIdle; + }else{ + RtChip0.Tick4_10Ms = EraseBlock64K_TryRusumeTime /2; + RtChip0.Sta = csBusy; + } + }else{ + RtChip0.Tick4_10Ms ++; + if(RtChip0.Tick4_10Ms > EraseBlock64K_TryRusumeTime){ + RtChip0.Sta = csCanTryResume; + } + } +} +//______________________________________________________________________________________________________________________________________________ + +void TRecord::GetSvEntry(int aInx) +{ + volatile unsigned int aAddr,i; + unsigned int aCn, aP0, aP1; + aAddr = dAddrSdWrite2FlashBufSv + (aInx * 24); + EntryRead.fData.Body.D32[0] = *(volatile unsigned int *)(aAddr + 0); + EntryRead.fData.Body.D32[1] = *(volatile unsigned int *)(aAddr + 4); + EntryRead.fData.Body.D32[2] = *(volatile unsigned int *)(aAddr + 8); + EntryRead.fData.Body.D32[3] = *(volatile unsigned int *)(aAddr +12); + EntryRead.fData.UserCode = *(volatile unsigned int *)(aAddr +16); + if(EntryRead.fData.Body.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else + if( (EntryRead.fData.Body.Splite.PCtlNum) && (EntryRead.fData.Body.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = EntryRead.fData.Body.Splite.PCtlNum -1; + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 <= dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } +} + +void TRecord::PrcSvWrite() +{ + int i, aReadInx ,OK, m; + unsigned int aAddr, aState, GotNew; + unsigned int aEntry, aPage, aBlock, aBlock2; + int BlockCount, EntryCount; + + + //Read Chip1 State Here + + if(RtChip1.Sta == csIdle){ + aState = nor_get_busy_state(dFlashSvChip); + if(aState != 0)return; + + GotNew = 0; + FlushToWriteBuf(); + aReadInx = Buf4Sv.ReadIndex; + aEntry = Buf4Sv.EntryX; + aPage = Buf4Sv.PageX; + aBlock = Buf4Sv.BlockX; + while(aReadInx != Buf4Sv.WriteIndex){ + aReadInx++; + if(aReadInx >= dWrite2FlashMaxCount){ + aReadInx = 0; + } + GetSvEntry(aReadInx); + if(EntryRead.fData.Body.D32[2] != 0){ + if(aEntry < dFlashEntryCountPerPage){ + ToWriteBuf[aEntry].D32[ 0] = EntryRead.D32[ 0]; + ToWriteBuf[aEntry].D32[ 1] = EntryRead.D32[ 1]; + ToWriteBuf[aEntry].D32[ 2] = EntryRead.D32[ 2]; + ToWriteBuf[aEntry].D32[ 3] = EntryRead.D32[ 3]; + ToWriteBuf[aEntry].D32[ 4] = EntryRead.D32[ 4]; + ToWriteBuf[aEntry].D32[ 5] = EntryRead.D32[ 5]; + ToWriteBuf[aEntry].D32[ 6] = EntryRead.D32[ 6]; + ToWriteBuf[aEntry].D32[ 7] = EntryRead.D32[ 7]; + ToWriteBuf[aEntry].D32[ 8] = EntryRead.D32[ 8]; + ToWriteBuf[aEntry].D32[ 9] = EntryRead.D32[ 9]; + ToWriteBuf[aEntry].D32[10] = EntryRead.D32[10]; + ToWriteBuf[aEntry].D32[11] = EntryRead.D32[11]; + ToWriteBuf[aEntry].D32[12] = EntryRead.D32[12]; + ToWriteBuf[aEntry].D32[13] = EntryRead.D32[13]; + ToWriteBuf[aEntry].D32[14] = EntryRead.D32[14]; + ToWriteBuf[aEntry].D32[15] = EntryRead.D32[15]; + GotNew ++; + aEntry ++; + } + if(aEntry >= dFlashEntryCountPerPage){ + aEntry =0; + aPage++; + if(aPage >= dFlashPageCountPerBlock){ + aPage = 0; + aBlock++; + if(aBlock >= dFrashSvUsingBlockCount)aBlock = 0; + Buf4Sv.NeedCheckBlockEmpty = 1; + Buf4Sv.BlockToBeErase = aBlock; + aBlock2 = Buf4Sv.BlockToBeErase +1; + if(aBlock2 >= dFrashSvUsingBlockCount)aBlock2 = 0; + Buf4Sv.BlockToBeErase2 = aBlock2; + Buf4Sv.NeedCheckBlockEmpty2 = 1; + } + break; + } + if( (0 == Buf4Sv.EntryX ) && (0 == Buf4Sv.PageX) ){ + //Check Writing Block if Empty + fAddr = dFlashSvBaseAddr + (dFlashBlockSize * Buf4Sv.BlockX); + nor_read_byte(dFlashSvChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Sv.NeedCheckBlockEmpty = 1; + Buf4Sv.BlockToBeErase = Buf4Sv.BlockX; + GotNew = 0; + } + //Check Next Block if Need Erase + aBlock2 = Buf4Sv.BlockX +1; + if(aBlock2 >= dFrashSvUsingBlockCount)aBlock2 = 0; + fAddr = dFlashSvBaseAddr + (dFlashBlockSize * aBlock2); + nor_read_byte(dFlashSvChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Sv.NeedCheckBlockEmpty2 = 1; + Buf4Sv.BlockToBeErase2 = aBlock2; + GotNew = 0; + } + + Buf4Sv.wBlockWriteToEep = Buf4Sv.BlockX; + Buf4Sv.NeedMarkWriteBlcokToEep = 1; + } + }else{ + continue; + } + } + if(GotNew){ + //write Here and Check Ok + aAddr = dFlashSvBaseAddr + (dFlashBlockSize * Buf4Sv.BlockX) + (dFlashPageSize * Buf4Sv.PageX) + (dFlashEntrySize * Buf4Sv.EntryX); + OK = 0; + for(i=Buf4Sv.EntryX; i= GotNew){ + break; + } + } + nor_write_byte_via_page(dFlashSvChip, aAddr, ToWriteBuf[Buf4Sv.EntryX].D8, GotNew * dFlashEntrySize); + + OK = 0; + aAddr = dSdramSvHistoryContentBaseAddr + (Buf4Sv.BlockX * SizeOf64K) + (Buf4Sv.PageX * SizeOfPage) + (Buf4Sv.EntryX * dFlashEntrySize); + for(i=Buf4Sv.EntryX; i= GotNew){ + break; + } + aAddr += dFlashEntrySize; + } + + //read Back To ToWriteBuf + if(1){ + OK = 1; + }else{ + OK = 0; + } + + //OK + if(OK){ + Buf4Sv.ReadIndex = aReadInx; + Buf4Sv.BlockX = aBlock; + Buf4Sv.PageX = aPage; + Buf4Sv.EntryX = aEntry; + + BlockCount = ((Buf4Sv.BlockX + dFrashSvUsingBlockCount) - Buf4Sv.sBlock ) % dFrashSvUsingBlockCount +1; + if(BlockCount > (dFrashSvUsingBlockCount -2)){ + Buf4Sv.sBlock = Buf4Sv.BlockX - (dFrashSvUsingBlockCount -3); + if(Buf4Sv.sBlock <0)Buf4Sv.sBlock += dFrashSvUsingBlockCount; + + BlockCount = dFrashSvUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Sv.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Sv.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Sv.Count = dSdramHistoryEntryCount; + }else{ + Buf4Sv.Count = EntryCount; + } + Buf4Sv.SdramAddrCurrent = dSdramSvHistoryContentBaseAddr + (Buf4Sv.BlockX * SizeOf64K) + (Buf4Sv.PageX * dFlashPageSize) + (Buf4Sv.EntryX * dFlashEntrySize); + Buf4Sv.SdramAddrStart = Buf4Sv.SdramAddrCurrent - (Buf4Sv.Count * 64); + if(Buf4Sv.SdramAddrStart < dSdramSvHistoryContentBaseAddr){ + Buf4Sv.SdramAddrStart = Buf4Sv.SdramAddrStart + dSdramHistoryBytesLength; + } + } + } + } +} + +void TRecord::GetFaultEntry(int aInx) +{ + volatile unsigned int aAddr,i; + unsigned int aCn, aP0, aP1; + aAddr = dAddrSdWrite2FlashBufFault + (aInx * 24); + EntryRead.fData.Body.D32[0] = *(volatile unsigned int *)(aAddr + 0); + EntryRead.fData.Body.D32[1] = *(volatile unsigned int *)(aAddr + 4); + EntryRead.fData.Body.D32[2] = *(volatile unsigned int *)(aAddr + 8); + EntryRead.fData.Body.D32[3] = *(volatile unsigned int *)(aAddr +12); + EntryRead.fData.UserCode = *(volatile unsigned int *)(aAddr +16); + if(EntryRead.fData.Body.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 < dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else + if( (EntryRead.fData.Body.Splite.PCtlNum) && (EntryRead.fData.Body.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = EntryRead.fData.Body.Splite.PCtlNum -1; + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 < dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } +} + +void TRecord::PrcFaultWrite() +{ + int i, aReadInx ,OK, m; + unsigned int aAddr, aState, GotNew; + unsigned int aEntry, aPage, aBlock, aBlock2; + int BlockCount, EntryCount; + + + //Read Chip1 State Here + + if(RtChip1.Sta == csIdle){ + aState = nor_get_busy_state(dFlashFaultChip); + if(aState != 0)return; + + GotNew = 0; + FlushToWriteBuf(); + aReadInx = Buf4Fault.ReadIndex; + aEntry = Buf4Fault.EntryX; + aPage = Buf4Fault.PageX; + aBlock = Buf4Fault.BlockX; + while(aReadInx != Buf4Fault.WriteIndex){ + aReadInx++; + if(aReadInx >= dWrite2FlashMaxCount){ + aReadInx = 0; + } + GetFaultEntry(aReadInx); + if(EntryRead.fData.Body.D32[2] != 0){ + if(aEntry < dFlashEntryCountPerPage){ + ToWriteBuf[aEntry].D32[ 0] = EntryRead.D32[ 0]; + ToWriteBuf[aEntry].D32[ 1] = EntryRead.D32[ 1]; + ToWriteBuf[aEntry].D32[ 2] = EntryRead.D32[ 2]; + ToWriteBuf[aEntry].D32[ 3] = EntryRead.D32[ 3]; + ToWriteBuf[aEntry].D32[ 4] = EntryRead.D32[ 4]; + ToWriteBuf[aEntry].D32[ 5] = EntryRead.D32[ 5]; + ToWriteBuf[aEntry].D32[ 6] = EntryRead.D32[ 6]; + ToWriteBuf[aEntry].D32[ 7] = EntryRead.D32[ 7]; + ToWriteBuf[aEntry].D32[ 8] = EntryRead.D32[ 8]; + ToWriteBuf[aEntry].D32[ 9] = EntryRead.D32[ 9]; + ToWriteBuf[aEntry].D32[10] = EntryRead.D32[10]; + ToWriteBuf[aEntry].D32[11] = EntryRead.D32[11]; + ToWriteBuf[aEntry].D32[12] = EntryRead.D32[12]; + ToWriteBuf[aEntry].D32[13] = EntryRead.D32[13]; + ToWriteBuf[aEntry].D32[14] = EntryRead.D32[14]; + ToWriteBuf[aEntry].D32[15] = EntryRead.D32[15]; + GotNew ++; + aEntry ++; + } + if(aEntry >= dFlashEntryCountPerPage){ + aEntry =0; + aPage++; + if(aPage >= dFlashPageCountPerBlock){ + aPage = 0; + aBlock++; + if(aBlock >= dFrashFaultUsingBlockCount)aBlock = 0; + Buf4Fault.NeedCheckBlockEmpty = 1; + Buf4Fault.BlockToBeErase = aBlock; + aBlock2 = Buf4Fault.BlockToBeErase +1; + if(aBlock2 >= dFrashFaultUsingBlockCount)aBlock2 = 0; + Buf4Fault.BlockToBeErase2 = aBlock2; + Buf4Fault.NeedCheckBlockEmpty2 = 1; + } + break; + } + if( (0 == Buf4Fault.EntryX ) && (0 == Buf4Fault.PageX) ){ + //Check Writing Block if Empty + fAddr = dFlashFaultBaseAddr + (dFlashBlockSize * Buf4Fault.BlockX); + nor_read_byte(dFlashFaultChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Fault.NeedCheckBlockEmpty = 1; + Buf4Fault.BlockToBeErase = Buf4Fault.BlockX; + GotNew = 0; + } + //Check Next Block if Need Erase + aBlock2 = Buf4Fault.BlockX +1; + if(aBlock2 >= dFrashFaultUsingBlockCount)aBlock2 = 0; + fAddr = dFlashFaultBaseAddr + (dFlashBlockSize * aBlock2); + nor_read_byte(dFlashFaultChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Fault.NeedCheckBlockEmpty2 = 1; + Buf4Fault.BlockToBeErase2 = aBlock2; + GotNew = 0; + } + + Buf4Fault.wBlockWriteToEep = Buf4Fault.BlockX; + Buf4Fault.NeedMarkWriteBlcokToEep = 1; + } + }else{ + continue; + } + } + if(GotNew){ + //write Here and Check Ok + aAddr = dFlashFaultBaseAddr + (dFlashBlockSize * Buf4Fault.BlockX) + (dFlashPageSize * Buf4Fault.PageX) + (dFlashEntrySize * Buf4Fault.EntryX); + OK = 0; + for(i=Buf4Fault.EntryX; i= GotNew){ + break; + } + } + nor_write_byte_via_page(dFlashFaultChip, aAddr, ToWriteBuf[Buf4Fault.EntryX].D8, GotNew * dFlashEntrySize); + + OK = 0; + aAddr = dSdramFaultHistoryContentBaseAddr + (Buf4Fault.BlockX * SizeOf64K) + (Buf4Fault.PageX * SizeOfPage) + (Buf4Fault.EntryX * dFlashEntrySize); + for(i=Buf4Fault.EntryX; i= GotNew){ + break; + } + aAddr += dFlashEntrySize; + } + + //read Back To ToWriteBuf + if(1){ + OK = 1; + }else{ + OK = 0; + } + + //OK + if(OK){ + Buf4Fault.ReadIndex = aReadInx; + Buf4Fault.BlockX = aBlock; + Buf4Fault.PageX = aPage; + Buf4Fault.EntryX = aEntry; + + BlockCount = ((Buf4Fault.BlockX + dFrashFaultUsingBlockCount) - Buf4Fault.sBlock ) % dFrashFaultUsingBlockCount +1; + if(BlockCount > (dFrashFaultUsingBlockCount -2)){ + Buf4Fault.sBlock = Buf4Fault.BlockX - (dFrashFaultUsingBlockCount -3); + if(Buf4Fault.sBlock <0)Buf4Fault.sBlock += dFrashFaultUsingBlockCount; + + BlockCount = dFrashFaultUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Fault.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Fault.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Fault.Count = dSdramHistoryEntryCount; + }else{ + Buf4Fault.Count = EntryCount; + } + Buf4Fault.SdramAddrCurrent = dSdramFaultHistoryContentBaseAddr + (Buf4Fault.BlockX * SizeOf64K) + (Buf4Fault.PageX * dFlashPageSize) + (Buf4Fault.EntryX * dFlashEntrySize); + Buf4Fault.SdramAddrStart = Buf4Fault.SdramAddrCurrent - (Buf4Fault.Count * 64); + if(Buf4Fault.SdramAddrStart < dSdramFaultHistoryContentBaseAddr){ + Buf4Fault.SdramAddrStart = Buf4Fault.SdramAddrStart + dSdramHistoryBytesLength; + } + } + } + } +} + +void TRecord::GetOperateEntry(int aInx) +{ + volatile unsigned int aAddr ,i, IsNeedFill; + unsigned int aCn, aP0, aP1; + unsigned char aOtType; + aAddr = dAddrSdWrite2FlashBufOperate + (aInx * 24); + EntryRead.fData.Body.D32[0] = *(volatile unsigned int *)(aAddr + 0); + EntryRead.fData.Body.D32[1] = *(volatile unsigned int *)(aAddr + 4); + EntryRead.fData.Body.D32[2] = *(volatile unsigned int *)(aAddr + 8); + EntryRead.fData.Body.D32[3] = *(volatile unsigned int *)(aAddr +12); + EntryRead.fData.UserCode = *(volatile unsigned int *)(aAddr +16); + aOtType = EntryRead.fData.Body.Splite.Data0; + IsNeedFill = 0; + if(aOtType == otMask)IsNeedFill =2; + else if(aOtType == otUnMask)IsNeedFill =2; + else if(aOtType == otCfgDevice)IsNeedFill =2; + else if(aOtType == otFireConfirm)IsNeedFill =2; + else if(aOtType == otFireRemoteConfirm)IsNeedFill =2; + else if(aOtType == otDescpModify)IsNeedFill =2; + else if(aOtType == otFaultConfirm){ + if( (EntryRead.fData.Body.Splite.Data1 & 0xF0) == 0)IsNeedFill =2; + } + else if(aOtType == otFaultRemoteConfirm){ + if( (EntryRead.fData.Body.Splite.Data1 & 0xF0) == 0)IsNeedFill =2; + } + + if(IsNeedFill == 0){ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + return; + } + + if(EntryRead.fData.Body.Splite.PCtlNum == MainCtl.fData.Split.MyNum){ + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 < dPORT_MAX_COUNT){ + aP0--; + aP1--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_Descp + (aP0 * 256 * 32) + (aP1 * 32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else + if( (EntryRead.fData.Body.Splite.PCtlNum) && (EntryRead.fData.Body.Splite.PCtlNum <= dNETWORK_MACHINE_COUNT) ){ + aCn = EntryRead.fData.Body.Splite.PCtlNum -1; + aP0 = EntryRead.fData.Body.Splite.P0; + aP1 = EntryRead.fData.Body.Splite.P1; + if(aP0 && aP1){ + if(aP0 < dPORT_MAX_COUNT){ + aP0--; + }else + if( (aP0 >= dADDR_DIRECTPAD_START) && (aP0 <= dADDR_DIRECTPAD_END) ){ + aP0 = aP0 - dADDR_DIRECTPAD_START; + aP1 = aP0 * dDIRECTCTL_KEY_MAX_COUNT + (aP1); + aP0 = 40; + } + aAddr = dAddrSdRam_DescpNw + (aCn*dONE_CTRL_DESCP_BYTES)+(aP0*8192) + (aP1*32); + for(i=7; i<15; i++){ + EntryRead.D32[i] = *(volatile unsigned int *)(aAddr + (i-7) *4); + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } + }else{ + for(i=7; i<15; i++){ + EntryRead.D32[i] = 0; + } + } +} + +void TRecord::PrcOperateWrite() +{ + int i, m, aReadInx ,OK; + unsigned int aAddr, aState, GotNew; + unsigned int aEntry, aPage, aBlock, aBlock2; + int BlockCount; + int EntryCount; + + //Read Chip1 State Here + if(RtChip1.Sta == csIdle){ + aState = nor_get_busy_state(dFlashOperateChip); + if(aState != 0)return; + + GotNew = 0; + FlushToWriteBuf(); + aReadInx = Buf4Operate.ReadIndex; + aEntry = Buf4Operate.EntryX; + aPage = Buf4Operate.PageX; + aBlock = Buf4Operate.BlockX; + while(aReadInx != Buf4Operate.WriteIndex){ + aReadInx++; + if(aReadInx >= dWrite2FlashMaxCount){ + aReadInx = 0; + } + GetOperateEntry(aReadInx); + if(EntryRead.fData.Body.D32[2] != 0){ + if(aEntry < dFlashEntryCountPerPage){ + ToWriteBuf[aEntry].D32[ 0] = EntryRead.D32[ 0]; + ToWriteBuf[aEntry].D32[ 1] = EntryRead.D32[ 1]; + ToWriteBuf[aEntry].D32[ 2] = EntryRead.D32[ 2]; + ToWriteBuf[aEntry].D32[ 3] = EntryRead.D32[ 3]; + ToWriteBuf[aEntry].D32[ 4] = EntryRead.D32[ 4]; + ToWriteBuf[aEntry].D32[ 5] = EntryRead.D32[ 5]; + ToWriteBuf[aEntry].D32[ 6] = EntryRead.D32[ 6]; + ToWriteBuf[aEntry].D32[ 7] = EntryRead.D32[ 7]; + ToWriteBuf[aEntry].D32[ 8] = EntryRead.D32[ 8]; + ToWriteBuf[aEntry].D32[ 9] = EntryRead.D32[ 9]; + ToWriteBuf[aEntry].D32[10] = EntryRead.D32[10]; + ToWriteBuf[aEntry].D32[11] = EntryRead.D32[11]; + ToWriteBuf[aEntry].D32[12] = EntryRead.D32[12]; + ToWriteBuf[aEntry].D32[13] = EntryRead.D32[13]; + ToWriteBuf[aEntry].D32[14] = EntryRead.D32[14]; + ToWriteBuf[aEntry].D32[15] = EntryRead.D32[15]; + GotNew ++; + aEntry ++; + } + if(aEntry >= dFlashEntryCountPerPage){ + aEntry =0; + aPage++; + if(aPage >= dFlashPageCountPerBlock){ + aPage = 0; + aBlock++; + if(aBlock >= dFrashOperateUsingBlockCount)aBlock = 0; + Buf4Operate.NeedCheckBlockEmpty = 1; + Buf4Operate.BlockToBeErase = aBlock; + aBlock2 = Buf4Operate.BlockToBeErase +1; + if(aBlock2 >= dFrashOperateUsingBlockCount)aBlock2 = 0; + Buf4Operate.BlockToBeErase2 = aBlock2; + Buf4Operate.NeedCheckBlockEmpty2 = 1; + } + break; + } + if( (0 == Buf4Operate.EntryX ) && (0 == Buf4Operate.PageX) ){ + //Check Writing Block if Empty + fAddr = dFlashOperateBaseAddr + (dFlashBlockSize * Buf4Operate.BlockX); + nor_read_byte(dFlashOperateChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Operate.NeedCheckBlockEmpty = 1; + Buf4Operate.BlockToBeErase = Buf4Operate.BlockX; + GotNew = 0; + } + //Check Next Block if Need Erase + aBlock2 = Buf4Operate.BlockX +1; + if(aBlock2 >= dFrashOperateUsingBlockCount)aBlock2 = 0; + fAddr = dFlashOperateBaseAddr + (dFlashBlockSize * aBlock2); + nor_read_byte(dFlashOperateChip, fAddr, FlashPageReadData.D8, 8); + if( (FlashPageReadData.D32[0] != 0xFFFFFFFF) || (FlashPageReadData.D32[1] != 0xFFFFFFFF) ){ + Buf4Operate.NeedCheckBlockEmpty2 = 1; + Buf4Operate.BlockToBeErase2 = aBlock2; + GotNew = 0; + } + + Buf4Operate.wBlockWriteToEep = Buf4Operate.BlockX; + Buf4Operate.NeedMarkWriteBlcokToEep = 1; + } + }else{ + continue; + } + } + if(GotNew){ + //write Here and Check Ok + aAddr = dFlashOperateBaseAddr + (dFlashBlockSize * Buf4Operate.BlockX) + (dFlashPageSize * Buf4Operate.PageX) + (dFlashEntrySize * Buf4Operate.EntryX); + OK = 0; + for(i=Buf4Operate.EntryX; i= GotNew){ + break; + } + } + nor_write_byte_via_page(dFlashOperateChip, aAddr, ToWriteBuf[Buf4Operate.EntryX].D8, GotNew * dFlashEntrySize); + + OK = 0; + aAddr = dSdramOperateHistoryContentBaseAddr + (Buf4Operate.BlockX * SizeOf64K) + (Buf4Operate.PageX * SizeOfPage) + (Buf4Operate.EntryX * dFlashEntrySize); + for(i=Buf4Operate.EntryX; i= GotNew){ + break; + } + aAddr += dFlashEntrySize; + } + + //read Back To ToWriteBuf + if(1){ + OK = 1; + }else{ + OK = 0; + } + + //OK + if(OK){ + Buf4Operate.ReadIndex = aReadInx; + Buf4Operate.BlockX = aBlock; + Buf4Operate.PageX = aPage; + Buf4Operate.EntryX = aEntry; + + BlockCount = ((Buf4Operate.BlockX + dFrashOperateUsingBlockCount) - Buf4Operate.sBlock ) % dFrashOperateUsingBlockCount +1; + if(BlockCount > (dFrashOperateUsingBlockCount -2)){ + Buf4Operate.sBlock = Buf4Operate.BlockX - (dFrashOperateUsingBlockCount -3); + if(Buf4Operate.sBlock <0)Buf4Operate.sBlock += dFrashOperateUsingBlockCount; + + BlockCount = dFrashOperateUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Operate.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Operate.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Operate.Count = dSdramHistoryEntryCount; + }else{ + Buf4Operate.Count = EntryCount; + } + Buf4Operate.SdramAddrCurrent = dSdramOperateHistoryContentBaseAddr + (Buf4Operate.BlockX * SizeOf64K) + (Buf4Operate.PageX * dFlashPageSize) + (Buf4Operate.EntryX * dFlashEntrySize); + Buf4Operate.SdramAddrStart = Buf4Operate.SdramAddrCurrent - (Buf4Operate.Count * 64); + if(Buf4Operate.SdramAddrStart < dSdramOperateHistoryContentBaseAddr){ + Buf4Operate.SdramAddrStart = Buf4Operate.SdramAddrStart + dSdramHistoryBytesLength; + } + } + } + } +} + +void TRecord::Chip1Prc() +{ + unsigned int aAddr, aState; + if(RtChip1.Sta == csIdle){ + RtChip1.SvFaultOpa++; + if(RtChip1.SvFaultOpa >2)RtChip1.SvFaultOpa = 0; + if(RtChip1.SvFaultOpa <0)RtChip1.SvFaultOpa = 0; + if(RtChip1.SvFaultOpa == 0){ + //Process Sv Here + if(Buf4Sv.NeedCheckBlockEmpty){ + aState = nor_get_busy_state(dFlashSvChip); + if(aState == 0){ + aAddr = dFlashSvBaseAddr + (dFlashBlockSize * Buf4Sv.BlockToBeErase); + nor_erase_sector_64k(dFlashSvChip,aAddr); + RtChip1.Sta = csErassing; + Buf4Sv.NeedCheckBlockEmpty = 0; + } + }else + if(Buf4Sv.NeedCheckBlockEmpty2){ + aState = nor_get_busy_state(dFlashSvChip); + if(aState == 0){ + aAddr = dFlashSvBaseAddr + (dFlashBlockSize * Buf4Sv.BlockToBeErase2); + nor_erase_sector_64k(dFlashSvChip,aAddr); + RtChip1.Sta = csErassing; + Buf4Sv.NeedCheckBlockEmpty2 = 0; + } + }else{ + if(Buf4Sv.ReadIndex != Buf4Sv.WriteIndex){ + PrcSvWrite(); + } + } + if(Buf4Sv.NeedMarkWriteBlcokToEep){ + Wait10Ms(); + eeprom_write_byte_via_page(0, dEepAddrSvWritingBlock, &Buf4Sv.wBlockWriteToEep, 1); + Wait10Ms(); + Buf4Sv.NeedMarkWriteBlcokToEep = 0; + } + }else + if(RtChip1.SvFaultOpa == 1){ + //Process Fault Here + if(Buf4Fault.NeedCheckBlockEmpty){ + aState = nor_get_busy_state(dFlashFaultChip); + if(aState == 0){ + aAddr = dFlashFaultBaseAddr + (dFlashBlockSize * Buf4Fault.BlockToBeErase); + nor_erase_sector_64k(dFlashFaultChip,aAddr); + RtChip1.Sta = csErassing; + Buf4Fault.NeedCheckBlockEmpty = 0; + } + }else + if(Buf4Fault.NeedCheckBlockEmpty2){ + aState = nor_get_busy_state(dFlashFaultChip); + if(aState == 0){ + aAddr = dFlashFaultBaseAddr + (dFlashBlockSize * Buf4Fault.BlockToBeErase2); + nor_erase_sector_64k(dFlashFaultChip,aAddr); + RtChip1.Sta = csErassing; + Buf4Fault.NeedCheckBlockEmpty2 = 0; + } + }else{ + if(Buf4Fault.ReadIndex != Buf4Fault.WriteIndex){ + PrcFaultWrite(); + } + } + if(Buf4Fault.NeedMarkWriteBlcokToEep){ + Wait10Ms(); + eeprom_write_byte_via_page(0, dEepAddrFaultWritingBlock, &Buf4Fault.wBlockWriteToEep, 1); + Wait10Ms(); + Buf4Fault.NeedMarkWriteBlcokToEep = 0; + } + }else + if(RtChip1.SvFaultOpa == 2){ + //Process Oprate Here + if(Buf4Operate.NeedCheckBlockEmpty){ + aState = nor_get_busy_state(dFlashOperateChip); + if(aState == 0){ + aAddr = dFlashOperateBaseAddr + (dFlashBlockSize * Buf4Operate.BlockToBeErase); + nor_erase_sector_64k(dFlashOperateChip,aAddr); + RtChip1.Sta = csErassing; + Buf4Operate.NeedCheckBlockEmpty = 0; + } + }else + if(Buf4Operate.NeedCheckBlockEmpty2){ + aState = nor_get_busy_state(dFlashOperateChip); + if(aState == 0){ + aAddr = dFlashOperateBaseAddr + (dFlashBlockSize * Buf4Operate.BlockToBeErase2); + nor_erase_sector_64k(dFlashOperateChip,aAddr); + RtChip1.Sta = csErassing; + Buf4Operate.NeedCheckBlockEmpty2 = 0; + } + }else{ + if(Buf4Operate.ReadIndex != Buf4Operate.WriteIndex){ + PrcOperateWrite(); + } + } + if(Buf4Operate.NeedMarkWriteBlcokToEep){ + Wait10Ms(); + eeprom_write_byte_via_page(0, dEepAddrOperateWritingBlock, &Buf4Operate.wBlockWriteToEep, 1); + Wait10Ms(); + Buf4Operate.NeedMarkWriteBlcokToEep = 0; + } + } + }else + if(RtChip1.Sta == csCanTryResume){ + if(0 == nor_get_busy_state(1)){ + RtChip1.Sta = csIdle; + }else{ + RtChip1.Tick4_10Ms = EraseBlock64K_TryRusumeTime /2; + RtChip1.Sta = csBusy; + } + }else{ + RtChip1.Tick4_10Ms ++; + if(RtChip1.Tick4_10Ms > EraseBlock64K_TryRusumeTime){ + RtChip1.Sta = csCanTryResume; + } + } +} + +/* +void TRecord::MsgReadInit(unsigned int aChip, TBufToFlash *aBuf, unsigned int aFlashBaseAddr, int aPstY) +{ + unsigned int BaseAddr, aAddr, sAddr, nAddr, IsBlockFound, IsPageFound, IsEntryFound; + int StartBlock, NextBlock; + int StartPage, NextPage; + int StartEntry, NextEntry; + unsigned char Data[4]; + int b, p, e; + + if(aChip > 1)return; + + StartBlock = 0; + for(b=0; bBlockDataAva[b] = 1; + }else{ + aBuf->BlockDataAva[b] = 0; + } + } + for(b=0; b= dFrashFireBlockCount){ + NextBlock = 0; + } + nAddr = dAddrSdRam_RuntimeBase + NextBlock * 4; + if( aBuf->BlockDataAva[b] && (*(volatile unsigned int *)nAddr == 0xFFFFFFFF ) ){ + IsBlockFound =1; + break; + } + } + + if(IsBlockFound){ + aBuf->BlockX = StartBlock; + IsPageFound = 0; + //Find Page + for(p=0; pPageX = StartPage; + }else{ + aBuf->PageX = dFlashPageCountPerBlock -1; + } + aBuf->PageX = StartPage; + IsEntryFound = 0; + //Check Entry + for(e=0; eEntryX = StartEntry; + }else{ + //this Page is Full + aBuf->EntryX = 0; + aBuf->PageX++; + if(aBuf->PageX >= dFlashPageCountPerBlock){ + aBuf->PageX = 0; + aBuf->BlockX++; + if(aBuf->BlockX >= dFrashFireBlockCount) + aBuf->BlockX =0; + } + } + }else{ + //Start Block Not Found + StartBlock = 0; + for(b=0; bBlockDataAva[b] == 1){ + StartBlock = 1; + } + } + aBuf->BlockX = 0; + aBuf->PageX = 0; + aBuf->EntryX = 0; + } + if( (IsBlockFound == 0) && (StartBlock) ){ + //Flash Error Show it + if(aBuf == &Buf4Fire) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fir:"); + else if(aBuf == &Buf4Linkage) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Lnk:"); + if(aBuf == &Buf4Sv) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Spv:"); + if(aBuf == &Buf4Fault) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fau:"); + if(aBuf == &Buf4Operate) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "OPA:"); + TextRender_string24(60, aPstY, clNearBlack, clNearWhite, "记录错误,请清除"); + }else{ + //Show + if(aBuf == &Buf4Fire) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fir:"); + else if(aBuf == &Buf4Linkage) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Lnk:"); + if(aBuf == &Buf4Sv) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Spv:"); + if(aBuf == &Buf4Fault) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fau:"); + if(aBuf == &Buf4Operate) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "OPA:"); + TextRender_string24(60, aPstY, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, aPstY, clNearBlack, clNearWhite, aBuf->BlockX); + TextRender_string24(130, aPstY, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, aPstY, clNearBlack, clNearWhite, aBuf->PageX); + TextRender_string24(200, aPstY, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, aPstY, clNearBlack, clNearWhite, aBuf->EntryX); + } +}*/ + +/* +void TRecord::MsgReadInit2(unsigned int aChip, TBufToFlash *aBuf, unsigned int aFlashBaseAddr, int aPstY) +{ + unsigned int BaseAddr, aAddr, sAddr, nAddr, IsBlockFound, IsPageFound, IsEntryFound; + int StartBlock, NextBlock; + int StartPage, NextPage; + int StartEntry, NextEntry; + int FoundStart, FoundEnd; + int b, p, e; + int Suce; + + if(aChip > 1)return; + + Suce =0; + + //Find Block_______________________________________________ + StartBlock = 0; + IsBlockFound = 0; + for(b=0; bBlockDataFirstAva[b] = 1; + }else{ + aBuf->BlockDataFirstAva[b] = 0; + } + + //Get Last + aAddr = aFlashBaseAddr + (dFlashBlockSize * b) + dFlashBlockSize - dFlashEntrySize; + nor_read_byte(aChip,aAddr,EntryRead.D8,8); + aAddr = dAddrSdRam_RuntimeBlockData + b*16; + *(volatile unsigned int *)(aAddr + 8) = EntryRead.fData.sIndex.spl.sIndex0; + *(volatile unsigned int *)(aAddr +12) = EntryRead.fData.sIndex.spl.sIndex1; + if(EntryRead.fData.sIndex.spl.sIndex0 != 0xFFFFFFFF){ + FoundEnd = 1; + aBuf->BlockDataEndAva[b] = 1; + }else{ + aBuf->BlockDataEndAva[b] = 0; + } + if( (FoundStart) && (FoundEnd == 0) ){ + IsBlockFound++; + StartBlock = b; + } + } + + if(IsBlockFound == 1){ + aBuf->BlockX = StartBlock; + IsPageFound = 0; + //Find Page______________________________________________ + for(p=0; pPageX = 0; + + } + }else{ + StartBlock = 0; + } + + for(b=0; bBlockDataAva[b] = 1; + }else{ + aBuf->BlockDataAva[b] = 0; + } + } + for(b=0; b= dFrashFireBlockCount){ + NextBlock = 0; + } + nAddr = dAddrSdRam_RuntimeBase + NextBlock * 4; + if( aBuf->BlockDataAva[b] && (*(volatile unsigned int *)nAddr == 0xFFFFFFFF ) ){ + IsBlockFound =1; + break; + } + } + + if(IsBlockFound){ + aBuf->BlockX = StartBlock; + IsPageFound = 0; + //Find Page + for(p=0; pPageX = StartPage; + }else{ + aBuf->PageX = dFlashPageCountPerBlock -1; + } + aBuf->PageX = StartPage; + IsEntryFound = 0; + //Check Entry + for(e=0; eEntryX = StartEntry; + }else{ + //this Page is Full + aBuf->EntryX = 0; + aBuf->PageX++; + if(aBuf->PageX >= dFlashPageCountPerBlock){ + aBuf->PageX = 0; + aBuf->BlockX++; + if(aBuf->BlockX >= dFrashFireBlockCount) + aBuf->BlockX =0; + } + } + }else{ + //Start Block Not Found + StartBlock = 0; + for(b=0; bBlockDataAva[b] == 1){ + StartBlock = 1; + } + } + aBuf->BlockX = 0; + aBuf->PageX = 0; + aBuf->EntryX = 0; + } + if( (IsBlockFound == 0) && (StartBlock) ){ + //Flash Error Show it + if(aBuf == &Buf4Fire) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fir:"); + else if(aBuf == &Buf4Linkage) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Lnk:"); + if(aBuf == &Buf4Sv) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Spv:"); + if(aBuf == &Buf4Fault) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fau:"); + if(aBuf == &Buf4Operate) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "OPA:"); + TextRender_string24(60, aPstY, clNearBlack, clNearWhite, "记录错误,请清除"); + }else{ + //Show + if(aBuf == &Buf4Fire) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fir:"); + else if(aBuf == &Buf4Linkage) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Lnk:"); + if(aBuf == &Buf4Sv) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Spv:"); + if(aBuf == &Buf4Fault) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fau:"); + if(aBuf == &Buf4Operate) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "OPA:"); + TextRender_string24(60, aPstY, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, aPstY, clNearBlack, clNearWhite, aBuf->BlockX); + TextRender_string24(130, aPstY, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, aPstY, clNearBlack, clNearWhite, aBuf->PageX); + TextRender_string24(200, aPstY, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, aPstY, clNearBlack, clNearWhite, aBuf->EntryX); + } +}*/ + + +/* +void TRecord::MsgReadInit3(unsigned int aChip, TBufToFlash *aBuf, unsigned int aFlashBaseAddr, int aPstY) +{ + unsigned int BaseAddr, aAddr, sAddr, nAddr, IsBlockFound, IsPageFound, IsEntryFound; + int StartBlock, NextBlock; + int StartPage, NextPage; + int StartEntry, NextEntry; + int FoundStart, FoundEnd; + int EmptyFound; + int b, p, e; + int Suce; + volatile unsigned int MaxBlockCount; + unsigned long long aInx; + + if(aChip > 1)return; + + if(aBuf == &Buf4Fire){ + MaxBlockCount = dFrashFireUsingBlockCount; + eeprom_read_byte(0, dEepAddrFireWritingBlock, &aBuf->WritingBlockReadFromEep, 1); + }else if(aBuf == &Buf4Linkage){ + MaxBlockCount = dFrashLinkageUsingBlockCount; + eeprom_read_byte(0, dEepAddrLinkageWritingBlock, &aBuf->WritingBlockReadFromEep, 1); + }else if(aBuf == &Buf4Sv){ + MaxBlockCount = dFrashSvUsingBlockCount; + eeprom_read_byte(0, dEepAddrSvWritingBlock, &aBuf->WritingBlockReadFromEep, 1); + }else if(aBuf == &Buf4Fault){ + MaxBlockCount = dFrashFaultUsingBlockCount; + eeprom_read_byte(0, dEepAddrFaultWritingBlock, &aBuf->WritingBlockReadFromEep, 1); + }else if(aBuf == &Buf4Operate){ + MaxBlockCount = dFrashOperateUsingBlockCount; + eeprom_read_byte(0, dEepAddrOpaWritingBlock, &aBuf->WritingBlockReadFromEep, 1); + }else{ + return; + } + + Suce =0; + + //Find Block_______________________________________________ + EmptyFound = 0; + StartBlock = 0; + IsBlockFound = 0; + IsPageFound = 0; + IsEntryFound = 0; + //aBuf->eBlock = 255; + aInx = 0; + for(b=0; b aInx ){ + aInx = EntryRead.fData.sIndex.fIndex; + IsBlockFound = 1; + StartBlock = b; + } + if(EmptyFound == 1){ + aBuf->sBlock = b; + EmptyFound = 2; + } + if(EmptyFound == 0){ + // aBuf->eBlock = b; + } + } + } + if(EmptyFound == 1){ + aBuf->sBlock = 0; + } + + if(IsBlockFound){ + aInx = 0; + for(p=0; p aInx ){ + aInx = EntryRead.fData.sIndex.fIndex; + IsPageFound = 1; + StartPage = p; + } + } + } + + if(IsPageFound){ + aInx = 0; + for(e=0; e<(dFlashEntryCountPerPage -1); e++){ + aAddr = aFlashBaseAddr + (dFlashBlockSize * StartBlock) + (dFlashPageSize * StartPage) + (dFlashEntrySize * e); + nor_read_byte(aChip,aAddr,EntryRead.D8,8); + aAddr = dAddrSdRam_RuntimeEntryData + e * 8; + *(volatile unsigned int *)(aAddr +0) = EntryRead.fData.sIndex.spl.sIndex0; + *(volatile unsigned int *)(aAddr +4) = EntryRead.fData.sIndex.spl.sIndex0; + if( (EntryRead.fData.sIndex.spl.sIndex0 == 0xFFFFFFFF) && (EntryRead.fData.sIndex.spl.sIndex1 == 0xFFFFFFFF) ){ + }else{ + if(EntryRead.fData.sIndex.fIndex > aInx ){ + aInx = EntryRead.fData.sIndex.fIndex; + IsEntryFound = 1; + StartEntry = e; + } + } + } + if(IsEntryFound){ + aBuf->fIndex.fIndex = aInx; + StartEntry++; + if(StartEntry >= (dFlashEntryCountPerPage) ){ + StartEntry = 0; + StartPage++; + if(StartPage >= dFlashPageCountPerBlock){ + StartPage = 0; + StartBlock++; + if(StartBlock >= MaxBlockCount ){ + StartBlock = 0; + } + } + } + aAddr = aFlashBaseAddr + (dFlashBlockSize * StartBlock) + (dFlashPageSize * StartPage) + (dFlashEntrySize * StartEntry); + nor_read_byte(aChip,aAddr,EntryRead.D8,8); + if( (EntryRead.fData.sIndex.spl.sIndex0 == 0xFFFFFFFF) && (EntryRead.fData.sIndex.spl.sIndex1 == 0xFFFFFFFF) ){ + aBuf->BlockX = StartBlock; + aBuf->PageX = StartPage; + aBuf->EntryX = StartEntry; + Suce = 1; + } + } + }else{ + + } + }else{ + aBuf->fIndex.fIndex = 1; + aBuf->BlockX = 0; + aBuf->PageX = 0; + aBuf->EntryX = 0; + Suce = 1; + } + + + if(Suce == 0){ + //Flash Error Show it + if(aBuf == &Buf4Fire) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fir:"); + else if(aBuf == &Buf4Linkage) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Lnk:"); + if(aBuf == &Buf4Sv) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Spv:"); + if(aBuf == &Buf4Fault) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fau:"); + if(aBuf == &Buf4Operate) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "OPA:"); + TextRender_string24(60, aPstY, clNearBlack, clNearWhite, "记录错误,请清除"); + + for(MaxBlockCount=0; MaxBlockCount<100000000; MaxBlockCount++); + }else{ + //Show + if(aBuf == &Buf4Fire) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fir:"); + else if(aBuf == &Buf4Linkage) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Lnk:"); + if(aBuf == &Buf4Sv) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Spv:"); + if(aBuf == &Buf4Fault) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "Fau:"); + if(aBuf == &Buf4Operate) + TextRender_string24(2, aPstY, clNearBlack, clNearWhite, "OPA:"); + TextRender_string24(60, aPstY, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, aPstY, clNearBlack, clNearWhite, aBuf->BlockX); + TextRender_string24(130, aPstY, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, aPstY, clNearBlack, clNearWhite, aBuf->PageX); + TextRender_string24(200, aPstY, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, aPstY, clNearBlack, clNearWhite, aBuf->EntryX); + } +}*/ + + + +void TRecord::LoadFireHistory() +{ + volatile unsigned int i, apg, sAddr, m, ReFindMaxInx, AvaCount, CanGoFindPageAndEntry, Found, BlockCount; + int FirstEmptyBlock =10000; + int FirstAvaBlock =10000; + int LastAvaBlock = 10000; + int EntryCount; + int x; + THisIndex rInx, tInx; + unsigned long long aInx; + + AvaCount = 0; + CanGoFindPageAndEntry = 0; + for(i=0; i rInx.fIndex){ + rInx.fIndex =tInx.fIndex; + } + } + } + } + /*if(apg == 0){ + if( (FlashPageReadData.D32[0] == 0xFFFFFFFF) && (FlashPageReadData.D32[1] == 0xFFFFFFFF) ){ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + }else{ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].spl.sIndex0 = FlashPageReadData.D32[0]; + TmpllIndex[i].spl.sIndex1 = FlashPageReadData.D32[1]; + } + }*/ + sys_error_led_task(); + } + if(rInx.fIndex > 0){ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].fIndex = rInx.fIndex; + }else{ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + } + } + + SysLoopTick = 0; + if(AvaCount == 0){ + Buf4Fire.BlockX = 0; + Buf4Fire.PageX = 0; + Buf4Fire.EntryX = 0; + Buf4Fire.sBlock = 0; + Buf4Fire.Count =0; + Buf4Fire.fIndex.fIndex = 2; + Buf4Fire.SdramAddrStart = dSdramFireHistoryContentBaseAddr + (Buf4Fire.sBlock * SizeOf64K); + }else + if(AvaCount >= dFrashFireUsingBlockCount){ + //Find Max + aInx = TmpllIndex[0].fIndex; + m =0; + for(i=0; i aInx){ + aInx = TmpllIndex[i].fIndex; + m = i; + } + } + Buf4Fire.fIndex.fIndex = aInx; + LastAvaBlock = m; + Buf4Fire.BlockX = LastAvaBlock; + m++; + if(m >= dFrashFireUsingBlockCount)m = 0; + FirstAvaBlock = m; + Buf4Fire.sBlock = FirstAvaBlock; + Buf4Fire.SdramAddrStart = dSdramFireHistoryContentBaseAddr + (FirstAvaBlock * SizeOf64K); + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + }else{ + if(TmpIsAva[0])FirstAvaBlock = 0; + for(i=0; i 256){ + if(TmpIsAva[i] == 0){ + FirstEmptyBlock = i; + } + }else{ + if(TmpIsAva[i]){ + if( (FirstAvaBlock == 0) || (FirstAvaBlock >256))FirstAvaBlock = i; + } + } + if(i<(dFrashFireUsingBlockCount-1)){ + if( (TmpIsAva[i]) && (TmpIsAva[i+1] ==0) ){ + LastAvaBlock = i; + } + } + } + if(LastAvaBlock > 256){ + LastAvaBlock = dFrashFireUsingBlockCount -1; + } + DelayMs(10); + eeprom_read_byte(0, dEepAddrFireWritingBlock, &Buf4Fire.WritingBlockReadFromEep, 1); + if(Buf4Fire.WritingBlockReadFromEep == LastAvaBlock){ + for(i=0; i= TmpllIndex[LastAvaBlock].fIndex)ReFindMaxInx =1; + } + } + } + Buf4Fire.sBlock = FirstAvaBlock; + Buf4Fire.BlockX = LastAvaBlock; + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + } + + //Find Out PageX And EntryX + SysLoopTick = 0; + if(CanGoFindPageAndEntry){ + Found = 0; + sAddr = dSdramFireHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + for(i=0; i<((dFlashBlockSize / dFlashEntrySize) -1); i++ ){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +4); + CmpllIndex2.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +0); + CmpllIndex2.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +4); + if( (CmpllIndex1.fIndex != 0xFFFFFFFFFFFFFFFF) && (CmpllIndex2.fIndex == 0xFFFFFFFFFFFFFFFF) ){ + Buf4Fire.PageX = (i+1) / dFlashEntryCountPerPage; + Buf4Fire.EntryX = (i+1) % dFlashEntryCountPerPage; + Buf4Fire.fIndex.fIndex = CmpllIndex1.fIndex; + Found = 1; + BlockCount = ((LastAvaBlock + dFrashFireUsingBlockCount) - FirstAvaBlock ) % dFrashFireUsingBlockCount; + Buf4Fire.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) + i -1; + if(Buf4Fire.Count <0)Buf4Fire.Count =0; + break; + } + } + if(Found == 0){ + Buf4Fire.BlockX++; + if(Buf4Fire.BlockX >= dFrashFireUsingBlockCount){ + Buf4Fire.BlockX = 0; + } + Buf4Fire.PageX = 0; + Buf4Fire.EntryX = 0; + i = (dFlashBlockSize / dFlashEntrySize) -1; + sAddr = dSdramFireHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +4); + Buf4Fire.fIndex.fIndex = CmpllIndex1.fIndex; + BlockCount = ((LastAvaBlock + dFrashFireUsingBlockCount) - FirstAvaBlock ) % dFrashFireUsingBlockCount +1; + Buf4Fire.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) -1; + if(Buf4Fire.Count <0)Buf4Fire.Count =0; + } + + BlockCount = ((Buf4Fire.BlockX + dFrashFireUsingBlockCount) - Buf4Fire.sBlock ) % dFrashFireUsingBlockCount +1; + if(BlockCount > (dFrashFireUsingBlockCount -2)){ + Buf4Fire.sBlock = Buf4Fire.BlockX - (dFrashFireUsingBlockCount -3); + if(Buf4Fire.sBlock <0)Buf4Fire.sBlock += dFrashFireUsingBlockCount; + + BlockCount = dFrashFireUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Fire.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Fire.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Fire.Count = dSdramHistoryEntryCount; + }else{ + Buf4Fire.Count = EntryCount; + } + Buf4Fire.SdramAddrCurrent = dSdramFireHistoryContentBaseAddr + (Buf4Fire.BlockX * SizeOf64K) + (Buf4Fire.PageX * dFlashPageSize) + (Buf4Fire.EntryX * dFlashEntrySize); + Buf4Fire.SdramAddrStart = Buf4Fire.SdramAddrCurrent - (Buf4Fire.Count * 64); + if(Buf4Fire.SdramAddrStart < dSdramFireHistoryContentBaseAddr){ + Buf4Fire.SdramAddrStart = Buf4Fire.SdramAddrStart + dSdramHistoryBytesLength; + } + } + + m=0; + Buf4Fire.fIndex.fIndex = 0; + EntryCount = Buf4Fire.Count -1; + do{ + if(EntryCount < 0)break; + sAddr = Buf4Fire.SdramAddrStart + (EntryCount * 64); + if(sAddr >= dSdramFireHistoryContentBaseAddr + dSdramHistoryBytesLength) + sAddr = sAddr - dSdramHistoryBytesLength; + for(i=0; i<16; i++){ + FlashPageReadData.D32[i] = *(volatile unsigned int *)(sAddr + i *4); + } + AvaCount = CheckHistoryCSum(FlashPageReadData.D8); + if(AvaCount){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr +4); + Buf4Fire.fIndex.fIndex = CmpllIndex1.fIndex; + break; + } + EntryCount--;; + m++; + }while(m<20); + + if(1){ + TextRender_string24(2, 80, clNearBlack, clNearWhite, "Fir:"); + TextRender_string24(60, 80, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, 80, clNearBlack, clNearWhite, Buf4Fire.BlockX); + TextRender_string24(130, 80, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, 80, clNearBlack, clNearWhite, Buf4Fire.PageX); + TextRender_string24(200, 80, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, 80, clNearBlack, clNearWhite, Buf4Fire.EntryX); + } +} + +void TRecord::LoadLinkageHistory() +{ + volatile unsigned int i, apg, sAddr, m, ReFindMaxInx, AvaCount, CanGoFindPageAndEntry, Found, BlockCount; + int FirstEmptyBlock =10000; + int FirstAvaBlock =10000; + int LastAvaBlock = 10000; + int EntryCount; + int x; + THisIndex rInx, tInx; + unsigned long long aInx; + + AvaCount = 0; + CanGoFindPageAndEntry = 0; + for(i=0; i rInx.fIndex){ + rInx.fIndex =tInx.fIndex; + } + } + } + } + /*if(apg == 0){ + if( (FlashPageReadData.D32[0] == 0xFFFFFFFF) && (FlashPageReadData.D32[1] == 0xFFFFFFFF) ){ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + }else{ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].spl.sIndex0 = FlashPageReadData.D32[0]; + TmpllIndex[i].spl.sIndex1 = FlashPageReadData.D32[1]; + } + }*/ + sys_error_led_task(); + } + if(rInx.fIndex > 0){ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].fIndex = rInx.fIndex; + }else{ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + } + } + + SysLoopTick = 0; + if(AvaCount == 0){ + Buf4Linkage.BlockX = 0; + Buf4Linkage.PageX = 0; + Buf4Linkage.EntryX = 0; + Buf4Linkage.sBlock = 0; + Buf4Linkage.Count =0; + Buf4Linkage.fIndex.fIndex = 2; + Buf4Linkage.SdramAddrStart = dSdramLinkageHistoryContentBaseAddr + (Buf4Linkage.sBlock * SizeOf64K); + }else + if(AvaCount >= dFrashLinkageUsingBlockCount){ + //Find Max + aInx = TmpllIndex[0].fIndex; + m =0; + for(i=0; i aInx){ + aInx = TmpllIndex[i].fIndex; + m = i; + } + } + Buf4Linkage.fIndex.fIndex = aInx; + LastAvaBlock = m; + Buf4Linkage.BlockX = LastAvaBlock; + m++; + if(m >= dFrashLinkageUsingBlockCount)m = 0; + FirstAvaBlock = m; + Buf4Linkage.sBlock = FirstAvaBlock; + Buf4Linkage.SdramAddrStart = dSdramLinkageHistoryContentBaseAddr + (FirstAvaBlock * SizeOf64K); + + CanGoFindPageAndEntry =1; + }else{ + if(TmpIsAva[0])FirstAvaBlock = 0; + for(i=0; i 256){ + if(TmpIsAva[i] == 0){ + FirstEmptyBlock = i; + } + }else{ + if(TmpIsAva[i]){ + if( (FirstAvaBlock == 0) || (FirstAvaBlock >256))FirstAvaBlock = i; + } + } + if(i<(dFrashLinkageUsingBlockCount-1)){ + if( (TmpIsAva[i]) && (TmpIsAva[i+1] ==0) ){ + LastAvaBlock = i; + } + } + } + if(LastAvaBlock > 256){ + LastAvaBlock = dFrashLinkageUsingBlockCount -1; + } + DelayMs(10); + eeprom_read_byte(0, dEepAddrLinkageWritingBlock, &Buf4Linkage.WritingBlockReadFromEep, 1); + if(Buf4Linkage.WritingBlockReadFromEep == LastAvaBlock){ + for(i=0; i= TmpllIndex[LastAvaBlock].fIndex)ReFindMaxInx =1; + } + } + } + Buf4Linkage.sBlock = FirstAvaBlock; + Buf4Linkage.BlockX = LastAvaBlock; + + CanGoFindPageAndEntry =1; + + sys_error_led_task(); + } + + //Find Out PageX And EntryX + + SysLoopTick = 0; + if(CanGoFindPageAndEntry){ + Found = 0; + sAddr = dSdramLinkageHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + for(i=0; i<((dFlashBlockSize / dFlashEntrySize) -1); i++ ){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +4); + CmpllIndex2.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +0); + CmpllIndex2.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +4); + if( (CmpllIndex1.fIndex != 0xFFFFFFFFFFFFFFFF) && (CmpllIndex2.fIndex == 0xFFFFFFFFFFFFFFFF) ){ + Buf4Linkage.PageX = (i+1) / dFlashEntryCountPerPage; + Buf4Linkage.EntryX = (i+1) % dFlashEntryCountPerPage; + Buf4Linkage.fIndex.fIndex = CmpllIndex1.fIndex; + Found = 1; + BlockCount = ((LastAvaBlock + dFrashLinkageUsingBlockCount) - FirstAvaBlock ) % dFrashLinkageUsingBlockCount; + Buf4Linkage.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) + i -1; + if(Buf4Linkage.Count <0)Buf4Linkage.Count =0; + break; + } + } + if(Found == 0){ + Buf4Linkage.BlockX++; + if(Buf4Linkage.BlockX >= dFrashLinkageUsingBlockCount){ + Buf4Linkage.BlockX = 0; + } + Buf4Linkage.PageX = 0; + Buf4Linkage.EntryX = 0; + i = (dFlashBlockSize / dFlashEntrySize) -1; + sAddr = dSdramLinkageHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +4); + Buf4Linkage.fIndex.fIndex = CmpllIndex1.fIndex; + BlockCount = ((LastAvaBlock + dFrashLinkageUsingBlockCount) - FirstAvaBlock ) % dFrashLinkageUsingBlockCount +1; + Buf4Linkage.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) -1; + if(Buf4Linkage.Count <0)Buf4Linkage.Count =0; + } + + BlockCount = ((Buf4Linkage.BlockX + dFrashLinkageUsingBlockCount) - Buf4Linkage.sBlock ) % dFrashLinkageUsingBlockCount +1; + if(BlockCount > (dFrashLinkageUsingBlockCount -2)){ + Buf4Linkage.sBlock = Buf4Linkage.BlockX - (dFrashLinkageUsingBlockCount -3); + if(Buf4Linkage.sBlock <0)Buf4Linkage.sBlock += dFrashLinkageUsingBlockCount; + + BlockCount = dFrashLinkageUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Linkage.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Linkage.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Linkage.Count = dSdramHistoryEntryCount; + }else{ + Buf4Linkage.Count = EntryCount; + } + Buf4Linkage.SdramAddrCurrent = dSdramLinkageHistoryContentBaseAddr + (Buf4Linkage.BlockX * SizeOf64K) + (Buf4Linkage.PageX * dFlashPageSize) + (Buf4Linkage.EntryX * dFlashEntrySize); + Buf4Linkage.SdramAddrStart = Buf4Linkage.SdramAddrCurrent - (Buf4Linkage.Count * 64); + if(Buf4Linkage.SdramAddrStart < dSdramLinkageHistoryContentBaseAddr){ + Buf4Linkage.SdramAddrStart = Buf4Linkage.SdramAddrStart + dSdramHistoryBytesLength; + } + } + + SysLoopTick = 0; + m=0; + Buf4Linkage.fIndex.fIndex = 0; + EntryCount = Buf4Linkage.Count -1; + do{ + if(EntryCount < 0)break; + sAddr = Buf4Linkage.SdramAddrStart + (EntryCount * 64); + if(sAddr >= dSdramLinkageHistoryContentBaseAddr + dSdramHistoryBytesLength) + sAddr = sAddr - dSdramHistoryBytesLength; + for(i=0; i<16; i++){ + FlashPageReadData.D32[i] = *(volatile unsigned int *)(sAddr + i *4); + } + AvaCount = CheckHistoryCSum(FlashPageReadData.D8); + if(AvaCount){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr +4); + Buf4Linkage.fIndex.fIndex = CmpllIndex1.fIndex; + break; + } + EntryCount--;; + m++; + }while(m<20); + + if(1){ + TextRender_string24(2, 110, clNearBlack, clNearWhite, "LNK:"); + TextRender_string24(60, 110, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, 110, clNearBlack, clNearWhite, Buf4Linkage.BlockX); + TextRender_string24(130, 110, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, 110, clNearBlack, clNearWhite, Buf4Linkage.PageX); + TextRender_string24(200, 110, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, 110, clNearBlack, clNearWhite, Buf4Linkage.EntryX); + } +} + +void TRecord::LoadSvHistory() +{ + volatile unsigned int i, apg, sAddr, m, ReFindMaxInx, AvaCount, CanGoFindPageAndEntry, Found, BlockCount; + int FirstEmptyBlock =10000; + int FirstAvaBlock =10000; + int LastAvaBlock = 10000; + int EntryCount; + int x; + THisIndex rInx, tInx; + unsigned long long aInx; + + AvaCount = 0; + CanGoFindPageAndEntry = 0; + for(i=0; i rInx.fIndex){ + rInx.fIndex =tInx.fIndex; + } + } + } + } + /*if(apg == 0){ + if( (FlashPageReadData.D32[0] == 0xFFFFFFFF) && (FlashPageReadData.D32[1] == 0xFFFFFFFF) ){ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + }else{ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].spl.sIndex0 = FlashPageReadData.D32[0]; + TmpllIndex[i].spl.sIndex1 = FlashPageReadData.D32[1]; + } + }*/ + sys_error_led_task(); + } + if(rInx.fIndex > 0){ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].fIndex = rInx.fIndex; + }else{ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + } + } + + SysLoopTick = 0; + if(AvaCount == 0){ + Buf4Sv.BlockX = 0; + Buf4Sv.PageX = 0; + Buf4Sv.EntryX = 0; + Buf4Sv.sBlock = 0; + Buf4Sv.Count =0; + Buf4Sv.fIndex.fIndex = 2; + Buf4Sv.SdramAddrStart = dSdramSvHistoryContentBaseAddr + (Buf4Sv.sBlock * SizeOf64K); + }else + if(AvaCount >= dFrashSvUsingBlockCount){ + //Find Max + aInx = TmpllIndex[0].fIndex; + m =0; + for(i=0; i aInx){ + aInx = TmpllIndex[i].fIndex; + m = i; + } + } + Buf4Sv.fIndex.fIndex = aInx; + LastAvaBlock = m; + Buf4Sv.BlockX = LastAvaBlock; + m++; + if(m >= dFrashSvUsingBlockCount)m = 0; + FirstAvaBlock = m; + Buf4Sv.sBlock = FirstAvaBlock; + Buf4Sv.SdramAddrStart = dSdramSvHistoryContentBaseAddr + (FirstAvaBlock * SizeOf64K); + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + }else{ + if(TmpIsAva[0])FirstAvaBlock = 0; + for(i=0; i 256){ + if(TmpIsAva[i] == 0){ + FirstEmptyBlock = i; + } + }else{ + if(TmpIsAva[i]){ + if( (FirstAvaBlock == 0) || (FirstAvaBlock >256))FirstAvaBlock = i; + } + } + if(i<(dFrashSvUsingBlockCount-1)){ + if( (TmpIsAva[i]) && (TmpIsAva[i+1] ==0) ){ + LastAvaBlock = i; + } + } + } + if(LastAvaBlock > 256){ + LastAvaBlock = dFrashSvUsingBlockCount -1; + } + DelayMs(10); + eeprom_read_byte(0, dEepAddrSvWritingBlock, &Buf4Sv.WritingBlockReadFromEep, 1); + if(Buf4Sv.WritingBlockReadFromEep == LastAvaBlock){ + for(i=0; i= TmpllIndex[LastAvaBlock].fIndex)ReFindMaxInx =1; + } + } + } + Buf4Sv.sBlock = FirstAvaBlock; + Buf4Sv.BlockX = LastAvaBlock; + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + } + + //Find Out PageX And EntryX + SysLoopTick = 0; + if(CanGoFindPageAndEntry){ + Found = 0; + sAddr = dSdramSvHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + for(i=0; i<((dFlashBlockSize / dFlashEntrySize) -1); i++ ){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +4); + CmpllIndex2.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +0); + CmpllIndex2.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +4); + if( (CmpllIndex1.fIndex != 0xFFFFFFFFFFFFFFFF) && (CmpllIndex2.fIndex == 0xFFFFFFFFFFFFFFFF) ){ + Buf4Sv.PageX = (i+1) / dFlashEntryCountPerPage; + Buf4Sv.EntryX = (i+1) % dFlashEntryCountPerPage; + Buf4Sv.fIndex.fIndex = CmpllIndex1.fIndex; + Found = 1; + BlockCount = ((LastAvaBlock + dFrashSvUsingBlockCount) - FirstAvaBlock ) % dFrashSvUsingBlockCount; + Buf4Sv.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) + i -1; + if(Buf4Sv.Count <0)Buf4Sv.Count =0; + break; + } + } + if(Found == 0){ + Buf4Sv.BlockX++; + if(Buf4Sv.BlockX >= dFrashSvUsingBlockCount){ + Buf4Sv.BlockX = 0; + } + Buf4Sv.PageX = 0; + Buf4Sv.EntryX = 0; + i = (dFlashBlockSize / dFlashEntrySize) -1; + sAddr = dSdramSvHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +4); + Buf4Sv.fIndex.fIndex = CmpllIndex1.fIndex; + BlockCount = ((LastAvaBlock + dFrashSvUsingBlockCount) - FirstAvaBlock ) % dFrashSvUsingBlockCount +1; + Buf4Sv.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) -1; + if(Buf4Sv.Count <0)Buf4Sv.Count =0; + } + + BlockCount = ((Buf4Sv.BlockX + dFrashSvUsingBlockCount) - Buf4Sv.sBlock ) % dFrashSvUsingBlockCount +1; + if(BlockCount > (dFrashSvUsingBlockCount -2)){ + Buf4Sv.sBlock = Buf4Sv.BlockX - (dFrashSvUsingBlockCount -3); + if(Buf4Sv.sBlock <0)Buf4Sv.sBlock += dFrashSvUsingBlockCount; + + BlockCount = dFrashSvUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Sv.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Sv.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Sv.Count = dSdramHistoryEntryCount; + }else{ + Buf4Sv.Count = EntryCount; + } + Buf4Sv.SdramAddrCurrent = dSdramSvHistoryContentBaseAddr + (Buf4Sv.BlockX * SizeOf64K) + (Buf4Sv.PageX * dFlashPageSize) + (Buf4Sv.EntryX * dFlashEntrySize); + Buf4Sv.SdramAddrStart = Buf4Sv.SdramAddrCurrent - (Buf4Sv.Count * 64); + if(Buf4Sv.SdramAddrStart < dSdramSvHistoryContentBaseAddr){ + Buf4Sv.SdramAddrStart = Buf4Sv.SdramAddrStart + dSdramHistoryBytesLength; + } + sys_error_led_task(); + } + + SysLoopTick = 0; + m=0; + Buf4Sv.fIndex.fIndex = 0; + EntryCount = Buf4Sv.Count -1; + do{ + if(EntryCount < 0)break; + sAddr = Buf4Sv.SdramAddrStart + (EntryCount * 64); + if(sAddr >= dSdramSvHistoryContentBaseAddr + dSdramHistoryBytesLength) + sAddr = sAddr - dSdramHistoryBytesLength; + for(i=0; i<16; i++){ + FlashPageReadData.D32[i] = *(volatile unsigned int *)(sAddr + i *4); + } + AvaCount = CheckHistoryCSum(FlashPageReadData.D8); + if(AvaCount){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr +4); + Buf4Sv.fIndex.fIndex = CmpllIndex1.fIndex; + break; + } + EntryCount--;; + m++; + }while(m<20); + + if(1){ + TextRender_string24(2, 140, clNearBlack, clNearWhite, "Spv:"); + TextRender_string24(60, 140, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, 140, clNearBlack, clNearWhite, Buf4Sv.BlockX); + TextRender_string24(130, 140, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, 140, clNearBlack, clNearWhite, Buf4Sv.PageX); + TextRender_string24(200, 140, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, 140, clNearBlack, clNearWhite, Buf4Sv.EntryX); + } +} + +void TRecord::LoadFaultHistory() +{ + volatile unsigned int i, apg, sAddr, m, ReFindMaxInx, AvaCount, CanGoFindPageAndEntry, Found, BlockCount; + int FirstEmptyBlock =10000; + int FirstAvaBlock =10000; + int LastAvaBlock = 10000; + int EntryCount; + int x; + THisIndex rInx, tInx; + unsigned long long aInx; + + AvaCount = 0; + CanGoFindPageAndEntry = 0; + for(i=0; i rInx.fIndex){ + rInx.fIndex =tInx.fIndex; + } + } + } + } + /*if(apg == 0){ + if( (FlashPageReadData.D32[0] == 0xFFFFFFFF) && (FlashPageReadData.D32[1] == 0xFFFFFFFF) ){ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + }else{ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].spl.sIndex0 = FlashPageReadData.D32[0]; + TmpllIndex[i].spl.sIndex1 = FlashPageReadData.D32[1]; + } + }*/ + sys_error_led_task(); + } + if(rInx.fIndex > 0){ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].fIndex = rInx.fIndex; + }else{ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + } + } + + SysLoopTick = 0; + if(AvaCount == 0){ + Buf4Fault.BlockX = 0; + Buf4Fault.PageX = 0; + Buf4Fault.EntryX = 0; + Buf4Fault.sBlock = 0; + Buf4Fault.Count =0; + Buf4Fault.fIndex.fIndex = 2; + Buf4Fault.SdramAddrStart = dSdramFaultHistoryContentBaseAddr + (Buf4Fault.sBlock * SizeOf64K); + }else + if(AvaCount >= dFrashFaultUsingBlockCount){ + //Find Max + aInx = TmpllIndex[0].fIndex; + m =0; + for(i=0; i aInx){ + aInx = TmpllIndex[i].fIndex; + m = i; + } + } + Buf4Fault.fIndex.fIndex = aInx; + LastAvaBlock = m; + Buf4Fault.BlockX = LastAvaBlock; + m++; + if(m >= dFrashFaultUsingBlockCount)m = 0; + FirstAvaBlock = m; + Buf4Fault.sBlock = FirstAvaBlock; + Buf4Fault.SdramAddrStart = dSdramFaultHistoryContentBaseAddr + (FirstAvaBlock * SizeOf64K); + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + }else{ + if(TmpIsAva[0])FirstAvaBlock = 0; + for(i=0; i 256){ + if(TmpIsAva[i] == 0){ + FirstEmptyBlock = i; + } + }else{ + if(TmpIsAva[i]){ + if( (FirstAvaBlock == 0) || (FirstAvaBlock >256))FirstAvaBlock = i; + } + } + if(i<(dFrashFaultUsingBlockCount-1)){ + if( (TmpIsAva[i]) && (TmpIsAva[i+1] ==0) ){ + LastAvaBlock = i; + } + } + } + if(LastAvaBlock > 256){ + LastAvaBlock = dFrashFaultUsingBlockCount -1; + } + DelayMs(10); + eeprom_read_byte(0, dEepAddrFaultWritingBlock, &Buf4Fault.WritingBlockReadFromEep, 1); + if(Buf4Fault.WritingBlockReadFromEep == LastAvaBlock){ + for(i=0; i= TmpllIndex[LastAvaBlock].fIndex)ReFindMaxInx =1; + } + } + } + Buf4Fault.sBlock = FirstAvaBlock; + Buf4Fault.BlockX = LastAvaBlock; + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + } + + //Find Out PageX And EntryX + + SysLoopTick = 0; + if(CanGoFindPageAndEntry){ + Found = 0; + sAddr = dSdramFaultHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + for(i=0; i<((dFlashBlockSize / dFlashEntrySize) -1); i++ ){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +4); + CmpllIndex2.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +0); + CmpllIndex2.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +4); + if( (CmpllIndex1.fIndex != 0xFFFFFFFFFFFFFFFF) && (CmpllIndex2.fIndex == 0xFFFFFFFFFFFFFFFF) ){ + Buf4Fault.PageX = (i+1) / dFlashEntryCountPerPage; + Buf4Fault.EntryX = (i+1) % dFlashEntryCountPerPage; + Buf4Fault.fIndex.fIndex = CmpllIndex1.fIndex; + Found = 1; + BlockCount = ((LastAvaBlock + dFrashFaultUsingBlockCount) - FirstAvaBlock ) % dFrashFaultUsingBlockCount; + Buf4Fault.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) + i -1; + if(Buf4Fault.Count <0)Buf4Fault.Count =0; + break; + } + } + if(Found == 0){ + Buf4Fault.BlockX++; + if(Buf4Fault.BlockX >= dFrashFaultUsingBlockCount){ + Buf4Fault.BlockX = 0; + } + Buf4Fault.PageX = 0; + Buf4Fault.EntryX = 0; + i = (dFlashBlockSize / dFlashEntrySize) -1; + sAddr = dSdramFaultHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +4); + Buf4Fault.fIndex.fIndex = CmpllIndex1.fIndex; + BlockCount = ((LastAvaBlock + dFrashFaultUsingBlockCount) - FirstAvaBlock ) % dFrashFaultUsingBlockCount +1; + Buf4Fault.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) -1; + if(Buf4Fault.Count <0)Buf4Fault.Count =0; + } + + BlockCount = ((Buf4Fault.BlockX + dFrashFaultUsingBlockCount) - Buf4Fault.sBlock ) % dFrashFaultUsingBlockCount +1; + if(BlockCount > (dFrashFaultUsingBlockCount -2)){ + Buf4Fault.sBlock = Buf4Fault.BlockX - (dFrashFaultUsingBlockCount -3); + if(Buf4Fault.sBlock <0)Buf4Fault.sBlock += dFrashFaultUsingBlockCount; + + BlockCount = dFrashFaultUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Fault.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Fault.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Fault.Count = dSdramHistoryEntryCount; + }else{ + Buf4Fault.Count = EntryCount; + } + Buf4Fault.SdramAddrCurrent = dSdramFaultHistoryContentBaseAddr + (Buf4Fault.BlockX * SizeOf64K) + (Buf4Fault.PageX * dFlashPageSize) + (Buf4Fault.EntryX * dFlashEntrySize); + Buf4Fault.SdramAddrStart = Buf4Fault.SdramAddrCurrent - (Buf4Fault.Count * 64); + if(Buf4Fault.SdramAddrStart < dSdramFaultHistoryContentBaseAddr){ + Buf4Fault.SdramAddrStart = Buf4Fault.SdramAddrStart + dSdramHistoryBytesLength; + } + sys_error_led_task(); + } + + SysLoopTick = 0; + m=0; + Buf4Fault.fIndex.fIndex = 0; + EntryCount = Buf4Fault.Count -1; + do{ + if(EntryCount < 0)break; + sAddr = Buf4Fault.SdramAddrStart + (EntryCount * 64); + if(sAddr >= dSdramFaultHistoryContentBaseAddr + dSdramHistoryBytesLength) + sAddr = sAddr - dSdramHistoryBytesLength; + for(i=0; i<16; i++){ + FlashPageReadData.D32[i] = *(volatile unsigned int *)(sAddr + i *4); + } + AvaCount = CheckHistoryCSum(FlashPageReadData.D8); + if(AvaCount){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr +4); + Buf4Fault.fIndex.fIndex = CmpllIndex1.fIndex; + break; + } + EntryCount--;; + m++; + }while(m<20); + + if(1){ + TextRender_string24(2, 170, clNearBlack, clNearWhite, "FAT:"); + TextRender_string24(60, 170, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, 170, clNearBlack, clNearWhite, Buf4Fault.BlockX); + TextRender_string24(130, 170, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, 170, clNearBlack, clNearWhite, Buf4Fault.PageX); + TextRender_string24(200, 170, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, 170, clNearBlack, clNearWhite, Buf4Fault.EntryX); + } +} + + +void TRecord::LoadOperateHistory() +{ + volatile unsigned int i, apg, sAddr, m, ReFindMaxInx, AvaCount, CanGoFindPageAndEntry, Found, BlockCount; + int FirstEmptyBlock =10000; + int FirstAvaBlock =10000; + int LastAvaBlock = 10000; + int EntryCount; + int x; + THisIndex rInx, tInx; + unsigned long long aInx; + + AvaCount = 0; + CanGoFindPageAndEntry = 0; + for(i=0; i rInx.fIndex){ + rInx.fIndex =tInx.fIndex; + } + } + } + } + /*if(apg == 0){ + if( (FlashPageReadData.D32[0] == 0xFFFFFFFF) && (FlashPageReadData.D32[1] == 0xFFFFFFFF) ){ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + }else{ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].spl.sIndex0 = FlashPageReadData.D32[0]; + TmpllIndex[i].spl.sIndex1 = FlashPageReadData.D32[1]; + } + }*/ + sys_error_led_task(); + } + if(rInx.fIndex > 0){ + TmpIsAva[i] =1; + AvaCount++; + TmpllIndex[i].fIndex = rInx.fIndex; + }else{ + TmpIsAva[i] =0; + TmpllIndex[i].fIndex = 0; + } + } + + SysLoopTick = 0; + if(AvaCount == 0){ + Buf4Operate.BlockX = 0; + Buf4Operate.PageX = 0; + Buf4Operate.EntryX = 0; + Buf4Operate.sBlock = 0; + Buf4Operate.Count =0; + Buf4Operate.fIndex.fIndex = 2; + Buf4Operate.SdramAddrStart = dSdramOperateHistoryContentBaseAddr + (Buf4Operate.sBlock * SizeOf64K); + }else + if(AvaCount >= dFrashOperateUsingBlockCount){ + //Find Max + aInx = TmpllIndex[0].fIndex; + m =0; + for(i=0; i aInx){ + aInx = TmpllIndex[i].fIndex; + m = i; + } + } + Buf4Operate.fIndex.fIndex = aInx; + LastAvaBlock = m; + Buf4Operate.BlockX = LastAvaBlock; + m++; + if(m >= dFrashOperateUsingBlockCount)m = 0; + FirstAvaBlock = m; + Buf4Operate.sBlock = FirstAvaBlock; + Buf4Operate.SdramAddrStart = dSdramOperateHistoryContentBaseAddr + (FirstAvaBlock * SizeOf64K); + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + }else{ + if(TmpIsAva[0])FirstAvaBlock = 0; + for(i=0; i 256){ + if(TmpIsAva[i] == 0){ + FirstEmptyBlock = i; + } + }else{ + if(TmpIsAva[i]){ + if( (FirstAvaBlock == 0) || (FirstAvaBlock >256))FirstAvaBlock = i; + } + } + if(i<(dFrashOperateUsingBlockCount-1)){ + if( (TmpIsAva[i]) && (TmpIsAva[i+1] ==0) ){ + LastAvaBlock = i; + } + } + } + if(LastAvaBlock > 256){ + LastAvaBlock = dFrashOperateUsingBlockCount -1; + } + DelayMs(10); + eeprom_read_byte(0, dEepAddrOperateWritingBlock, &Buf4Operate.WritingBlockReadFromEep, 1); + if(Buf4Operate.WritingBlockReadFromEep == LastAvaBlock){ + for(i=0; i= TmpllIndex[LastAvaBlock].fIndex)ReFindMaxInx =1; + } + } + } + Buf4Operate.sBlock = FirstAvaBlock; + Buf4Operate.BlockX = LastAvaBlock; + + CanGoFindPageAndEntry =1; + sys_error_led_task(); + } + + //Find Out PageX And EntryX + SysLoopTick = 0; + if(CanGoFindPageAndEntry){ + Found = 0; + sAddr = dSdramOperateHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + for(i=0; i<((dFlashBlockSize / dFlashEntrySize) -1); i++ ){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + i*dFlashEntrySize +4); + CmpllIndex2.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +0); + CmpllIndex2.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i+1)*dFlashEntrySize +4); + if( (CmpllIndex1.fIndex != 0xFFFFFFFFFFFFFFFF) && (CmpllIndex2.fIndex == 0xFFFFFFFFFFFFFFFF) ){ + Buf4Operate.PageX = (i+1) / dFlashEntryCountPerPage; + Buf4Operate.EntryX = (i+1) % dFlashEntryCountPerPage; + Buf4Operate.fIndex.fIndex = CmpllIndex1.fIndex; + Found = 1; + BlockCount = ((LastAvaBlock + dFrashOperateUsingBlockCount) - FirstAvaBlock ) % dFrashOperateUsingBlockCount; + Buf4Operate.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) + i -1; + if(Buf4Operate.Count <0)Buf4Operate.Count =0; + break; + } + } + if(Found == 0){ + Buf4Operate.BlockX++; + if(Buf4Operate.BlockX >= dFrashOperateUsingBlockCount){ + Buf4Operate.BlockX = 0; + } + Buf4Operate.PageX = 0; + Buf4Operate.EntryX = 0; + i = (dFlashBlockSize / dFlashEntrySize) -1; + sAddr = dSdramOperateHistoryContentBaseAddr + (LastAvaBlock * SizeOf64K); + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr + (i)*dFlashEntrySize +4); + Buf4Operate.fIndex.fIndex = CmpllIndex1.fIndex; + BlockCount = ((LastAvaBlock + dFrashOperateUsingBlockCount) - FirstAvaBlock ) % dFrashOperateUsingBlockCount +1; + Buf4Operate.Count = BlockCount * (dFlashBlockSize / dFlashEntrySize) -1; + if(Buf4Operate.Count <0)Buf4Operate.Count =0; + } + + BlockCount = ((Buf4Operate.BlockX + dFrashOperateUsingBlockCount) - Buf4Operate.sBlock ) % dFrashOperateUsingBlockCount +1; + if(BlockCount > (dFrashOperateUsingBlockCount -2)){ + Buf4Operate.sBlock = Buf4Operate.BlockX - (dFrashOperateUsingBlockCount -3); + if(Buf4Operate.sBlock <0)Buf4Operate.sBlock += dFrashOperateUsingBlockCount; + + BlockCount = dFrashOperateUsingBlockCount -2; + } + EntryCount = (BlockCount-1) * (dFlashBlockSize / dFlashEntrySize) + (Buf4Operate.PageX * (dFlashPageSize / dFlashEntrySize)) + Buf4Operate.EntryX ; + if(EntryCount > dSdramHistoryEntryCount){ + Buf4Operate.Count = dSdramHistoryEntryCount; + }else{ + Buf4Operate.Count = EntryCount; + } + Buf4Operate.SdramAddrCurrent = dSdramOperateHistoryContentBaseAddr + (Buf4Operate.BlockX * SizeOf64K) + (Buf4Operate.PageX * dFlashPageSize) + (Buf4Operate.EntryX * dFlashEntrySize); + Buf4Operate.SdramAddrStart = Buf4Operate.SdramAddrCurrent - (Buf4Operate.Count * 64); + if(Buf4Operate.SdramAddrStart < dSdramOperateHistoryContentBaseAddr){ + Buf4Operate.SdramAddrStart = Buf4Operate.SdramAddrStart + dSdramHistoryBytesLength; + } + sys_error_led_task(); + } + + SysLoopTick = 0; + m=0; + Buf4Operate.fIndex.fIndex = 0; + EntryCount = Buf4Operate.Count -1; + do{ + if(EntryCount < 0)break; + sAddr = Buf4Operate.SdramAddrStart + (EntryCount * 64); + if(sAddr >= dSdramOperateHistoryContentBaseAddr + dSdramHistoryBytesLength) + sAddr = sAddr - dSdramHistoryBytesLength; + for(i=0; i<16; i++){ + FlashPageReadData.D32[i] = *(volatile unsigned int *)(sAddr + i *4); + } + AvaCount = CheckHistoryCSum(FlashPageReadData.D8); + if(AvaCount){ + CmpllIndex1.spl.sIndex0 = *(volatile unsigned int *)(sAddr +0); + CmpllIndex1.spl.sIndex1 = *(volatile unsigned int *)(sAddr +4); + Buf4Operate.fIndex.fIndex = CmpllIndex1.fIndex; + break; + } + EntryCount--;; + m++; + }while(m<20); + + if(1){ + TextRender_string24(2, 200, clNearBlack, clNearWhite, "Opa:"); + TextRender_string24(60, 200, clNearBlack, clNearWhite, "BK"); + TextDigitRender3_24(90, 200, clNearBlack, clNearWhite, Buf4Operate.BlockX); + TextRender_string24(130, 200, clNearBlack, clNearWhite, "PG"); + TextDigitRender3_24(160, 200, clNearBlack, clNearWhite, Buf4Operate.PageX); + TextRender_string24(200, 200, clNearBlack, clNearWhite, "Ey"); + TextDigitRender3_24(230, 200, clNearBlack, clNearWhite, Buf4Operate.EntryX); + } +} + +void TRecord::AllMsgReadInit() +{ + LoadFireHistory(); + LoadLinkageHistory(); + LoadSvHistory(); + LoadFaultHistory(); + LoadOperateHistory(); + + sysIndex.fIndex = 1; + if(Buf4Fire.fIndex.fIndex > sysIndex.fIndex) sysIndex.fIndex = Buf4Fire.fIndex.fIndex; + if(Buf4Linkage.fIndex.fIndex > sysIndex.fIndex) sysIndex.fIndex = Buf4Linkage.fIndex.fIndex; + if(Buf4Sv.fIndex.fIndex > sysIndex.fIndex) sysIndex.fIndex = Buf4Sv.fIndex.fIndex; + if(Buf4Fault.fIndex.fIndex > sysIndex.fIndex) sysIndex.fIndex = Buf4Fault.fIndex.fIndex; + if(Buf4Operate.fIndex.fIndex > sysIndex.fIndex) sysIndex.fIndex = Buf4Operate.fIndex.fIndex; + + + TMyString::sFromUInt(sysIndex.D32.Inx1, FlashPageReadData.D8); + TextRender_string24(2, 240, clNearWhite, FlashPageReadData.D8); + TMyString::sFromUInt(sysIndex.D32.Inx0, FlashPageReadData.D8); + TextRender_string24(200, 240, clNearWhite, FlashPageReadData.D8); + + if(sysIndex.fIndex > dPRIMARY_KEY_WARNING_NUM){ + PrimaryKeyWarning = 1; + CtlCenter.ieAddBrdFault(40,TBoardFaultType::RecordPrimaryKeyWarning); + }else{ + PrimaryKeyWarning =0; + } + + DelayMs(1000); +} + +void TRecord::CheckPrimaryKeyWarning() +{ + if( (sysIndex.fIndex > dPRIMARY_KEY_WARNING_NUM) or (PrimaryKeyWarning) ){ + CtlCenter.ieAddBrdFault(40,TBoardFaultType::RecordPrimaryKeyWarning); + } +} + +void TRecord::ClearFireHistory() +{ + volatile unsigned int sta, aWait; + + int b; + + //Find Block_______________________________________________ + for(b=0; bdPORT_MAX_COUNT)return; + tP=aPort-1; + + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + //Read DisplayPad Cfg Table + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * tP) + (256 * 2); + nor_read_byte(dFlashRegisterDataChip,fAddr,FlashPageReadData.D8,256); + for(m=0; m<16; m++){ + for(int Gg=0; Gg<16; Gg++){ + Port[tP].DisplayPadSet[m].MemBytes[Gg] = FlashPageReadData.D8[m*16 +Gg]; + } + if(Port[tP].DisplayPadSet[m].MemBytes[0] ==0xFF){ + for(int Gg=0; Gg<16; Gg++){ + Port[tP].DisplayPadSet[m].MemBytes[Gg] = 0; + } + } + } + + //Read DisplayPad Crc + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * tP) + (256 * 3); + nor_read_byte(dFlashRegisterDataChip,fAddr,FlashPageReadData.D8,256); + Port[tP].CrcDisplayPad = FlashPageReadData.D32[0]; + SysLoopTick = 0; + Crc32Reset(); + for(m=0; m<16; m++){ + for(int x=0; x<4; x++)Crc32Feed(Port[tP].DisplayPadSet[m].MemD32[x]); + } + if(Crc32GetResult() == Port[tP].CrcDisplayPad){ + if(Port[tP].CrcFlag.CrcDisplayPad){ + Port[tP].CrcFlag.CrcDisplayPad =0; + CtlCenter.ieAddBrdFaultCancel(tP+1,TBoardFaultType::StoragePortDpSet); + } + }else{ + Port[tP].CrcFlag.CrcDisplayPad =1; + CtlCenter.ieAddBrdFault(tP+1,TBoardFaultType::StoragePortDpSet); + } +} + +void TRecord::ReadRegisterDataOnePort(unsigned char aPort) +{ + unsigned int i,m,x; + volatile unsigned int aFlashState; + volatile unsigned int tCrc; + TDMix tDm; + + if(aPort == 0)return; + if(aPort>dPORT_MAX_COUNT)return; + i=aPort-1; + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + SysLoopTick = 0; + //Read ExistTable + fAddr = dFlashRegisterDataAddr + (dFlashRegisterPortDataLen * i) + (256 * 0); + nor_read_byte(dFlashRegisterDataChip,fAddr,FlashPageReadData.D8,256); + for(m=0; m(Port[i].ExistTable[x])); + } + for(x=0; x(Port[i].dTypeTable[x])); + } + tCrc = Crc32GetResult(); + if(tCrc == Port[i].CrcDevType ){ + if(Port[i].CrcFlag.DevType){ + Port[i].CrcFlag.DevType =0; + CtlCenter.ieAddBrdFaultCancel(i+1, TBoardFaultType::StorageEpDType); + } + }else{ + Port[i].CrcFlag.DevType =1; + CtlCenter.ieAddBrdFault(i+1, TBoardFaultType::StorageEpDType); + } + + Port[i].fData.Port.dType = dgTYPE_PORT; + Port[i].fData.Port.Id = i+1; +} + +void TRecord::ReadRegisterData() +{ + unsigned int i,m,x; + volatile unsigned int aFlashState; + volatile unsigned int tCrc; + TDMix tDm; + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(0); + }while(aFlashState); + + //_____________________________________Port + for(i=0; i(FlashPageReadData.D8[m])); + tDm.D8[0]= FlashPageReadData.D8[dPORT_MAX_COUNT + 0]; + tDm.D8[1]= FlashPageReadData.D8[dPORT_MAX_COUNT + 1]; + tDm.D8[2]= FlashPageReadData.D8[dPORT_MAX_COUNT + 2]; + tDm.D8[3]= FlashPageReadData.D8[dPORT_MAX_COUNT + 3]; + MainCtl.CrcPortList = tDm.D32; + if(MainCtl.CrcPortList == Crc32GetResult()){ + if(MainCtl.CrcFlag.PortList){ + MainCtl.CrcFlag.PortList =0; + CtlCenter.ieAddBrdFaultCancel(41,TBoardFaultType::StoragePortList); + } + }else{ + MainCtl.CrcFlag.PortList =1; + CtlCenter.ieAddBrdFault (41,TBoardFaultType::StoragePortList); + } + MainCtl.fData.Split.PortCount = 0; + for(m=0; m= dDISPLAYPAD_MAX_COUNT)break; + } + } + } + sys_error_led_task(); + } + + //calc NeedFeedBackCount + for(i=0; i 99999999)Port[i].UcList[m*64+x].Full =0; + tAddr = dAddrSdRam_4UserCodeMatch + (i * 1024) + ((m*64+x) * 4); + tUserCodeStr.Spl.BcdText_7 = Port[i].UcList[m*64+x].Full / 10000000 % 10; + tUserCodeStr.Spl.BcdText_6 = Port[i].UcList[m*64+x].Full / 1000000 % 10; + tUserCodeStr.Spl.BcdText_5 = Port[i].UcList[m*64+x].Full / 100000 % 10; + tUserCodeStr.Spl.BcdText_4 = Port[i].UcList[m*64+x].Full / 10000 % 10; + tUserCodeStr.Spl.BcdText_3 = Port[i].UcList[m*64+x].Full / 1000 % 10; + tUserCodeStr.Spl.BcdText_2 = Port[i].UcList[m*64+x].Full / 100 % 10; + tUserCodeStr.Spl.BcdText_1 = Port[i].UcList[m*64+x].Full / 10 % 10; + tUserCodeStr.Spl.BcdText_0 = Port[i].UcList[m*64+x].Full / 1 % 10; + *(volatile unsigned int *)(tAddr) = tUserCodeStr.Full; + } + sys_error_led_task(); + if(m==3){ + Port[i].CrcAuxId = FlashPageReadData.D32[63]; + } + } + Crc32Reset(); + for(m=0; m(FlashPageReadData.D8[x])); + if(Crc32GetResult() == Port[i].CrcAssignedType){ + if(Port[i].CrcFlag.AssignedType){ + Port[i].CrcFlag.AssignedType =0; + CtlCenter.ieAddBrdFaultCancel(i+1, TBoardFaultType::StorageEpAssignedType); + } + }else{ + Port[i].CrcFlag.AssignedType =1; + CtlCenter.ieAddBrdFault(i+1, TBoardFaultType::StorageEpAssignedType); + } + for(x=0; x(Port[i].AssignType[x])); + Port[i].CrcRealAssignedType = Crc32GetResult(); + + sys_error_led_task(); + SysLoopTick = 0; + fAddr = dFlashAddrDevUserCode + (4096 * i) + (256 * 5); + nor_read_byte(dFlashAddrDevUserCodeChip,fAddr,FlashPageReadData.D8,256); + tCrc.D8[0] = FlashPageReadData.D8[252]; + tCrc.D8[1] = FlashPageReadData.D8[253]; + tCrc.D8[2] = FlashPageReadData.D8[254]; + tCrc.D8[3] = FlashPageReadData.D8[255]; + Port[i].CrcSignalType = tCrc.D32; + Crc32Reset(); + for(x=0; x(FlashPageReadData.D8[x])); + if(Crc32GetResult() == Port[i].CrcSignalType){ + if(Port[i].CrcFlag.SignalType){ + Port[i].CrcFlag.SignalType =0; + CtlCenter.ieAddBrdFaultCancel(i+1, TBoardFaultType::StorageEpSignalType); + } + }else{ + Port[i].CrcFlag.SignalType =1; + CtlCenter.ieAddBrdFault(i+1, TBoardFaultType::StorageEpSignalType); + } + for(x=0; x(Port[i].FuncSetByte[x])); + Port[i].CrcRealSignalType = Crc32GetResult(); + + sys_error_led_task(); + + Port[i].UserCodeMin = 0xFFFFFFFF; + Port[i].UserCodeMax = 0; + + for(x=0;x<256;x++){ + if(Port[i].UcList[x].Full < Port[i].UserCodeMin){ + Port[i].UserCodeMin = Port[i].UcList[x].Full; + } + if(Port[i].UcList[x].Full > Port[i].UserCodeMax){ + Port[i].UserCodeMax = Port[i].UcList[x].Full; + } + } + } +} + +void TRecord::ReadDirectPadUserSet(unsigned char aPath0) +{ + unsigned int i,m,x; + volatile unsigned int aFlashState; + TUserCodeStr tUserCodeStr; + TDMix tCrc1, tCrc2; + + if(aPath0 == 0)return; + if(aPath0>dDIRECTCTL_MAX_COUNT)return; + i=aPath0-1; + + SysLoopTick = 0; + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(dFlashAddrDevUserCodeChip); + }while(aFlashState); + fAddr = dFlashAddrDirectPadUserCode + (4096 * i) + (256 * 0); + nor_read_byte(dFlashAddrDevUserCodeChip,fAddr,FlashPageReadData.D8,256); + tCrc1.D8[0] = FlashPageReadData.D8[32+8 +0]; + tCrc1.D8[1] = FlashPageReadData.D8[32+8 +1]; + tCrc1.D8[2] = FlashPageReadData.D8[32+8 +2]; + tCrc1.D8[3] = FlashPageReadData.D8[32+8 +3]; + tCrc2.D8[0] = FlashPageReadData.D8[32+8 +4]; + tCrc2.D8[1] = FlashPageReadData.D8[32+8 +5]; + tCrc2.D8[2] = FlashPageReadData.D8[32+8 +6]; + tCrc2.D8[3] = FlashPageReadData.D8[32+8 +7]; + DirectCtlBoard[i].CrcAuxId = tCrc1.D32; + DirectCtlBoard[i].CrcAssignedType = tCrc2.D32; + Crc32Reset(); + for(x=0; x<8; x++){ + DirectCtlBoard[i].UcList[x].Full = FlashPageReadData.D32[x]; + Crc32Feed(FlashPageReadData.D32[x]); + if(DirectCtlBoard[i].UcList[x].Full >99999999)DirectCtlBoard[i].UcList[x].Full =0; + tUserCodeStr.Spl.BcdText_7 = DirectCtlBoard[i].UcList[x].Full / 10000000 % 10; + tUserCodeStr.Spl.BcdText_6 = DirectCtlBoard[i].UcList[x].Full / 1000000 % 10; + tUserCodeStr.Spl.BcdText_5 = DirectCtlBoard[i].UcList[x].Full / 100000 % 10; + tUserCodeStr.Spl.BcdText_4 = DirectCtlBoard[i].UcList[x].Full / 10000 % 10; + tUserCodeStr.Spl.BcdText_3 = DirectCtlBoard[i].UcList[x].Full / 1000 % 10; + tUserCodeStr.Spl.BcdText_2 = DirectCtlBoard[i].UcList[x].Full / 100 % 10; + tUserCodeStr.Spl.BcdText_1 = DirectCtlBoard[i].UcList[x].Full / 10 % 10; + tUserCodeStr.Spl.BcdText_0 = DirectCtlBoard[i].UcList[x].Full / 1 % 10; + DirectCtlBoard[i].UcFastMatch[x].Full = tUserCodeStr.Full; + } + if(DirectCtlBoard[i].CrcAuxId == Crc32GetResult()){ + if(DirectCtlBoard[i].CrcFlag.AuxId){ + DirectCtlBoard[i].CrcFlag.AuxId = 0; + CtlCenter.ieAddBrdFaultCancel(i+dADDR_DIRECTPAD_START, TBoardFaultType::StorageEpAuxId); + } + }else{ + DirectCtlBoard[i].CrcFlag.AuxId =1; + CtlCenter.ieAddBrdFault(i+dADDR_DIRECTPAD_START, TBoardFaultType::StorageEpAuxId); + } + + DirectCtlBoard[i].IsIncludePump = 0; + Crc32Reset(); + for(x=0; xdHANDCTL_MAX_COUNT)return; + + do{ + DelayMs(2); + aFlashState = nor_get_busy_state(dFlashBusPadLnkChipX); + }while(aFlashState); + Error = 0; + i=aPad-1; + SysLoopTick = 0; + + for(z=0; z> (Gz *4)) & 0x0000000F) == 10){ + HandCtlBoard[i].UcListNotAnd[z* 64 + x].Full |= 0x0000000F << (Gz * 4); + }else + if( ((HandCtlBoard[i].UcList[z* 64 + x].Full >> (Gz *4)) & 0x0000000F) > 10 ){ + HandCtlBoard[i].UcList[z* 64 + x].Full = 0; + Error =1; + break; + } + } + } + } + fAddr = dFlashAddrBusPadLnk + (i * 4096) + (2 * 256); + nor_read_page(dFlashBusPadLnkChipX, fAddr, FlashPageReadData.D8); + for(x=0; x(HandCtlBoard[i].AssignType[x])); + } + fAddr = dFlashAddrBusPadLnk + (i * 4096) + (3 * 256); + nor_read_page(dFlashBusPadLnkChipX, fAddr, FlashPageReadData.D8); + for(x=0; x(HandCtlBoard[i].IsMatchAreaAssign[x])); + } + fAddr = dFlashAddrBusPadLnk + (i * 4096) + (4 * 256); + nor_read_page(dFlashBusPadLnkChipX, fAddr, FlashPageReadData.D8); + for(x=0; x(HandCtlBoard[i].Area[x])); + if(HandCtlBoard[i].Area[x] > dAreaCountMax){ + HandCtlBoard[i].Area[x] =0; + Error =1; + } + } + + fAddr = dFlashAddrBusPadLnk + (i * 4096) + (5 * 256); + nor_read_page(dFlashBusPadLnkChipX, fAddr, FlashPageReadData.D8); + HandCtlBoard[i].PadIsProhibit = FlashPageReadData.D8[0]; + HandCtlBoard[i].KeyCount = FlashPageReadData.D8[1]; + HandCtlBoard[i].Crc = FlashPageReadData.D32[1]; + + if( (HandCtlBoard[i].KeyCount != 48) && (HandCtlBoard[i].KeyCount != 64) && (HandCtlBoard[i].KeyCount != 128) ){ + HandCtlBoard[i].KeyCount = 0; + Error =1; + } + + Crc32Feed(static_cast(HandCtlBoard[i].PadIsProhibit)); + Crc32Feed(static_cast(HandCtlBoard[i].KeyCount)); + + if( (HandCtlBoard[i].Crc==Crc32GetResult()) and (Error==0)){ + if(HandCtlBoard[i].CrcFlag){ + HandCtlBoard[i].CrcFlag = 0; + CtlCenter.ieAddBrdFaultCancel(i+1,TBoardFaultType::StorageBusPadCfg); + } + }else{ + HandCtlBoard[i].CrcFlag = 1; + CtlCenter.ieAddBrdFault(i+1,TBoardFaultType::StorageBusPadCfg); + } + + SysLoopTick = 0; + HandCtlBoard[i].PadHasConfig = 0; + HandCtlBoard[i].PadFbRequst = 0; + for(z=0; zdDIRECTCTL_MAX_COUNT)return; + + i=aPath0-1; + + DelayMs(2); + + SysLoopTick = 0; + for(x=0; x(DirectCtlBoard[i].IsRegisted[x])); + Crc32Feed(static_cast(DirectCtlBoard[i].IsCheckError[x])); + Crc32Feed(static_cast(FlashPageReadData.D8[x*8 +7])); + } + DirectCtlBoard[i].CrcConfig = FlashPageReadData.D32[16]; + if(DirectCtlBoard[i].CrcConfig== Crc32GetResult()){ + if(DirectCtlBoard[i].CrcFlag.Config){ + DirectCtlBoard[i].CrcFlag.Config =0; + CtlCenter.ieAddBrdFaultCancel(i+dADDR_DIRECTPAD_START, TBoardFaultType::StorageDirectPadCfg); + } + }else{ + DirectCtlBoard[i].CrcFlag.Config =1; + CtlCenter.ieAddBrdFault(i+dADDR_DIRECTPAD_START, TBoardFaultType::StorageDirectPadCfg); + } + + DirectCtlBoard[i].SendPadCfg2Pad(i); + + sys_error_led_task(); +} + +void TRecord::LoadDirectPadCfg() +{ + int i; + for(i=1; i<=dDIRECTCTL_MAX_COUNT; i++){ + LoadDirectPadCfg(i); + } +} + +void TRecord::ReadMainSet() +{ + unsigned int aAddr; + int i; + //Read ExistTable + aAddr = dEepAddrMainSet; + DelayMs(10); + eeprom_read_byte(0, aAddr, FlashPageReadData.D8, 32); + + MainCtl.fData.Split.MyNum = FlashPageReadData.D8[0]; + MainCtl.fData.Split.NetworkMode = FlashPageReadData.D8[1]; + PriterSetting.OnOff = FlashPageReadData.D8[2]; + PriterSetting.PrintSelected = FlashPageReadData.D8[3]; + AllowAuto = FlashPageReadData.D8[4]; + AllowManual = FlashPageReadData.D8[5]; + + if( (AllowAuto == 0) && (AllowManual == 0) ){ + AllowAuto =1; + } + if(AllowAuto == 0)AllowManual =2;else AllowManual =0; + + ScreenAndKeyLock.SaveOn = FlashPageReadData.D8[6]; + ScreenAndKeyLock.SaveTime = FlashPageReadData.D8[7]; + ScreenAndKeyLock.IsKeyLock = FlashPageReadData.D8[8]; + ScreenAndKeyLock.UnLockText[0] = FlashPageReadData.D8[9]; + ScreenAndKeyLock.UnLockText[1] = FlashPageReadData.D8[10]; + ScreenAndKeyLock.UnLockText[2] = FlashPageReadData.D8[11]; + ScreenAndKeyLock.UnLockText[3] = FlashPageReadData.D8[12]; + if(ScreenAndKeyLock.SaveTime <1)ScreenAndKeyLock.SaveTime = 1; + if(ScreenAndKeyLock.SaveTime >20)ScreenAndKeyLock.SaveTime = 20; + //ScreenAndKeyLock.IsKeyLock = 0; + + i = FlashPageReadData.D8[17]; + i = i<<8; + i |= FlashPageReadData.D8[16]; + i = i<<8; + i |= FlashPageReadData.D8[15]; + i = i<<8; + i |= FlashPageReadData.D8[14]; + + //if(FlashPageReadData.D8[13] == 0xA5)GraphUsing = 1; + //else GraphUsing = 0; + //GraphDevBrd = i; + //GraphDevFrameIntervalMs = FlashPageReadData.D8[18]; + //GraphDevHalfDuplex = FlashPageReadData.D8[19]; + //GraphDevReplyDelayUs = FlashPageReadData.D8[20]; + //GraphDevReplyRetainTimeMs = FlashPageReadData.D8[21]; + PowerPrmValue.MainCount = 1; + PowerPrmValue.SubExist[0] = FlashPageReadData.D8[22]; + PowerPrmValue.SubExist[1] = FlashPageReadData.D8[23]; + if(PowerPrmValue.SubExist[0] != 1)PowerPrmValue.SubExist[0] =0; + if(PowerPrmValue.SubExist[1] != 1)PowerPrmValue.SubExist[1] =0; + + LanguageEnCn = FlashPageReadData.D8[24]; + if(LanguageEnCn != 1)LanguageEnCn =0; + LanguageEnCn = 0; + + tData[1] =0; tData[1] =0; + tData[2] =0; tData[3] =0; tData[4] =0; tData[5] =0; tData[6] =0; tData[7] =0; + if(AllowAuto)tData[1] |= 0x01; + if(AllowManual)tData[1] |= 0x02; + InnerCan.OBufInsert(1, 88, tData, 2); + + if( (MainCtl.fData.Split.MyNum == 0) || (MainCtl.fData.Split.MyNum > dNETWORK_MACHINE_COUNT) ){ + MainCtl.fData.Split.MyNum =1; + MainCtl.fData.Split.NetworkMode = 0; + }else{ + if(MainCtl.fData.Split.NetworkMode >2)MainCtl.fData.Split.NetworkMode =0; + } + if(PriterSetting.PrintSelected > 255)PriterSetting.PrintSelected = 255; +} + +void TRecord::ReadAllowSet() +{ + volatile unsigned int aWait; + unsigned int aAddr; + int i; + //Read ExistTable + aAddr = dEepAddrMainSet; + DelayMs(10); + eeprom_read_byte(0, aAddr, FlashPageReadData.D8, 6); + + AllowAuto = FlashPageReadData.D8[4]; + AllowManual = FlashPageReadData.D8[5]; + if(AllowAuto == 0)AllowManual =2;else AllowManual =0; +} + +void TRecord::ReadPrintSet() +{ + unsigned int aAddr; + volatile unsigned int aWait; + int i; + //Read ExistTable + aAddr = dEepAddrMainSet; + DelayMs(10); + eeprom_read_byte(0, aAddr, FlashPageReadData.D8, 4); + + PriterSetting.OnOff = FlashPageReadData.D8[2]; + PriterSetting.PrintSelected = FlashPageReadData.D8[3]; +} + +void TRecord::WriteMainSetMainCtl(unsigned char aIsMaster, unsigned char aCtlNum) +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char aData[2]; + int i; + //Read ExistTable + aData[0] = aCtlNum; + aData[1] = aIsMaster; + aAddr = dEepAddrMainSet + 0; + DelayMs(10); + eeprom_write_byte_via_page(0, aAddr, aData, 2); + DelayMs(10); +} + +void TRecord::WritePrinterState(unsigned char aSta) +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char aData[2]; + //Read ExistTable + aData[0] = aSta; + aData[1] = 0; + aAddr = dEepAddrMainSet + 2; + DelayMs(20); + eeprom_write_byte_via_page(0, aAddr, aData, 1); +} + +void TRecord::WritePrinterEvent(unsigned char aEvent) +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char aData[2]; + //Read ExistTable + aData[0] = aEvent; + aData[1] = 0; + aAddr = dEepAddrMainSet + 3; + DelayMs(20); + eeprom_write_byte_via_page(0, aAddr, aData, 1); +} + +void TRecord::WriteAllow(unsigned char aAllowAuto, unsigned char aAllowManual) +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char aData[2]; + //Read ExistTable + aData[0] = aAllowAuto; + aData[1] = aAllowManual; + aAddr = dEepAddrMainSet + 4; + DelayMs(20); + eeprom_write_byte_via_page(0, aAddr, aData, 2); +} + +void TRecord::WriteScreenKeyLock(unsigned char aScreenSave, unsigned char EnterSaveTime, unsigned char aLock, char *aCr) +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char aData[8]; + //Read ExistTable + aData[0] = aScreenSave; + aData[1] = EnterSaveTime; + aData[2] = aLock; + aData[3] = *aCr++; + aData[4] = *aCr++; + aData[5] = *aCr++; + aData[6] = *aCr++; + + aAddr = dEepAddrMainSet + 6; + DelayMs(20); + eeprom_write_byte_via_page(0, aAddr, aData, 7); + + DelayMs(20); + eeprom_read_byte(0, aAddr, aData, 7); + ScreenAndKeyLock.SaveOn = aData[0]; + ScreenAndKeyLock.SaveTime = aData[1]; + ScreenAndKeyLock.IsKeyLock = aData[2]; + ScreenAndKeyLock.UnLockText[0] = aData[3]; + ScreenAndKeyLock.UnLockText[1] = aData[4]; + ScreenAndKeyLock.UnLockText[2] = aData[5]; + ScreenAndKeyLock.UnLockText[3] = aData[6]; + if(ScreenAndKeyLock.SaveTime <1)ScreenAndKeyLock.SaveTime = 1; + if(ScreenAndKeyLock.SaveTime >20)ScreenAndKeyLock.SaveTime = 20; + //ScreenAndKeyLock.IsKeyLock = 0; + DelayMs(20); +} + +void TRecord::ReadScreenSave() +{ + unsigned int aAddr; + int i; + //Read ExistTable + aAddr = dEepAddrMainSet; + DelayMs(10); + eeprom_read_byte(0, aAddr, FlashPageReadData.D8, 32); + + ScreenAndKeyLock.SaveOn = FlashPageReadData.D8[6]; + ScreenAndKeyLock.SaveTime = FlashPageReadData.D8[7]; + ScreenAndKeyLock.IsKeyLock = FlashPageReadData.D8[8]; + ScreenAndKeyLock.UnLockText[0] = FlashPageReadData.D8[9]; + ScreenAndKeyLock.UnLockText[1] = FlashPageReadData.D8[10]; + ScreenAndKeyLock.UnLockText[2] = FlashPageReadData.D8[11]; + ScreenAndKeyLock.UnLockText[3] = FlashPageReadData.D8[12]; + if(ScreenAndKeyLock.SaveTime <1)ScreenAndKeyLock.SaveTime = 1; + if(ScreenAndKeyLock.SaveTime >20)ScreenAndKeyLock.SaveTime = 20; + //ScreenAndKeyLock.IsKeyLock = 0; +} + +void TRecord::WriteGraphSet(unsigned int aBrd, unsigned char aIntavalMs, unsigned char aIsHaft, unsigned char RpyDelayUs, unsigned char RpyTimeMs) +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char aData[8]; + //Read ExistTable + aData[0] = static_cast(aBrd & 0x000000FF); + aData[1] = static_cast((aBrd >> 8) & 0x000000FF); + aData[2] = static_cast((aBrd >> 16) & 0x000000FF); + aData[3] = static_cast((aBrd >> 24) & 0x000000FF); + aData[4] = aIntavalMs; + aData[5] = aIsHaft; + aData[6] = RpyDelayUs; + aData[7] = RpyTimeMs; + aAddr = dEepAddrMainSet + 13; + DelayMs(20); + eeprom_write_byte_via_page(0, aAddr, aData, 8); +} + +void TRecord::SaveNewTime2Eep() +{ + volatile unsigned int aWait; + unsigned int aAddr; + unsigned char aData[6]; + + aData[0] = DateTime.Time.Split.Second; + aData[1] = DateTime.Time.Split.Minute; + aData[2] = DateTime.Time.Split.Hour; + + aData[3] = DateTime.Date.Split.Day; + aData[4] = DateTime.Date.Split.Month; + aData[5] = DateTime.Date.Split.Year; + + aAddr = dEepAddrCtlShutDownTime; + DelayMs(10); + eeprom_write_byte_via_page(0, aAddr, aData, 6); +} + +void TRecord::SaveNwCfg(unsigned char aMasterNum, unsigned char aSlaveCount, unsigned char *aList) +{ + volatile unsigned int i; + unsigned int aAddr; + + FlashPageReadData.D8[ 0] = aMasterNum; + FlashPageReadData.D8[ 1] = aSlaveCount; + + for(i=0; (i dNETWORK_MACHINE_COUNT) + ProtoC2C.MasterNum = 0; + + if(ProtoC2C.SlaveCount > dNETWORK_MACHINE_COUNT ) + ProtoC2C.SlaveCount = 0; + + for(i=0; idNETWORK_MACHINE_COUNT)ProtoC2C.SlaveList[i] =0; + } +} + +void TRecord::SaveNwM2MCfg(unsigned char aCnt, unsigned char *aList) +{ + volatile unsigned int i; + unsigned int aAddr; + + for(i=0; i12) ) MaintainData.fDa.Month0 = 1; + if( (MaintainData.fDa.Day0 == 0) || (MaintainData.fDa.Day0 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month0-1]) ) MaintainData.fDa.Day0 = 1; + + if( (MaintainData.fDa.Month1 ==0) || (MaintainData.fDa.Month1 >12) ) MaintainData.fDa.Month1 = 1; + if( (MaintainData.fDa.Day1 == 0) || (MaintainData.fDa.Day1 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month1-1]) ) MaintainData.fDa.Day1 = 1; + + if( (MaintainData.fDa.Month2 ==0) || (MaintainData.fDa.Month2 >12) ) MaintainData.fDa.Month2 = 1; + if( (MaintainData.fDa.Day2 == 0) || (MaintainData.fDa.Day2 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month2-1]) ) MaintainData.fDa.Day2 = 1; + + + /* + if(MaintainData.fDa.IsCustomTime == 0){ + if(MaintainData.fDa.IsHalfYear){ + //2 Point + if( (MaintainData.fDa.Month0 ==0) || (MaintainData.fDa.Month0 >12) ) MaintainData.fDa.Month0 = 1; + if( (MaintainData.fDa.Day0 == 0) || (MaintainData.fDa.Day0 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month0-1]) ) MaintainData.fDa.Day0 = 1; + + if( (MaintainData.fDa.Month1 ==0) || (MaintainData.fDa.Month1 >12) ) MaintainData.fDa.Month1 = 1; + if( (MaintainData.fDa.Day1 == 0) || (MaintainData.fDa.Day1 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month1-1]) ) MaintainData.fDa.Day1 = 1; + }else{ + //1 Point + if( (MaintainData.fDa.Month0 ==0) || (MaintainData.fDa.Month0 >12) ) MaintainData.fDa.Month0 = 1; + if( (MaintainData.fDa.Day0 == 0) || (MaintainData.fDa.Day0 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month0-1]) ) MaintainData.fDa.Day0 = 1; + } + }else{ + //3 Point + + if( (MaintainData.fDa.Month0 ==0) || (MaintainData.fDa.Month0 >12) ) MaintainData.fDa.Month0 = 1; + if( (MaintainData.fDa.Day0 == 0) || (MaintainData.fDa.Day0 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month0-1]) ) MaintainData.fDa.Day0 = 1; + + if( (MaintainData.fDa.Month1 ==0) || (MaintainData.fDa.Month1 >12) ) MaintainData.fDa.Month1 = 1; + if( (MaintainData.fDa.Day1 == 0) || (MaintainData.fDa.Day1 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month1-1]) ) MaintainData.fDa.Day1 = 1; + + if( (MaintainData.fDa.Month2 ==0) || (MaintainData.fDa.Month2 >12) ) MaintainData.fDa.Month2 = 1; + if( (MaintainData.fDa.Day2 == 0) || (MaintainData.fDa.Day2 >TDateTime::MonthDaysNotLeapYear[MaintainData.fDa.Month2-1]) ) MaintainData.fDa.Day2 = 1; + }*/ +} + +void TRecord::Read4Area() +{ + unsigned int fAddr, sdAddr; + unsigned int x,i; + unsigned int wP1; + unsigned int PageCount; + volatile unsigned int GetSta; + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlash4AreaChip); + }while(GetSta); + + PageCount = dAreaCountMax / (256 / 64); + + for(x=0; x(Port[i].Area[x])); + if(Port[i].Area[x] > dAreaCountMax)Port[i].Area[x] =0; + } + }else + if(Gg == 1){ + for(x=0; x<128;x++){ + Port[i].Area[x + 128] = FlashPageReadData.D16[x]; + if(Port[i].Area[x + 128] > dAreaCountMax)Port[i].Area[x + 128] =0; + if(x<(dEP_MAX_COUNT_PER_PORT-128))Crc32Feed(static_cast(Port[i].Area[x+128])); + } + tCrc.D16[0]=FlashPageReadData.D16[126]; + tCrc.D16[1]=FlashPageReadData.D16[127]; + Port[i].CrcArea = tCrc.D32; + if(Port[i].CrcArea == Crc32GetResult()){ + if(Port[i].CrcFlag.Area){ + Port[i].CrcFlag.Area =0; + CtlCenter.ieAddBrdFaultCancel(i+1,TBoardFaultType::StorageEpArea); + } + }else{ + Port[i].CrcFlag.Area =1; + CtlCenter.ieAddBrdFault(i+1,TBoardFaultType::StorageEpArea); + } + } + } + } +} + +void TRecord::ReadDirectPadAreaNum() +{ + unsigned int fAddr; + volatile unsigned int x, GetSta; + unsigned char aP0, aP1, wP1; + TDMix tCrc; + + SysLoopTick = 0; + do{ + DelayMs(3); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + + for(int Gg=0; Gg<2; Gg++){ + SysLoopTick = 0; + do{ + DelayMs(5); + GetSta = nor_get_busy_state(dFlash4DevAreaNumChip); + }while(GetSta); + + fAddr = dFlash4DevAreaNum + (40 * 512) + (Gg * 256); + DelayMs(2); + nor_read_page(dFlash4AreaChip, fAddr, FlashPageReadData.D8); + + if(Gg ==0){ + for(int pNum=0; pNum<10; pNum++){ + Crc32Reset(); + for(x=0; x<8; x++){ + DirectCtlBoard[pNum].Area[x] = FlashPageReadData.D16[pNum * (dDIRECTCTL_KEY_MAX_COUNT+2) + x]; + Crc32Feed(static_cast(DirectCtlBoard[pNum].Area[x])); + if(DirectCtlBoard[pNum].Area[x] > dAreaCountMax)DirectCtlBoard[pNum].Area[x] = 0; + } + tCrc.D16[0] = FlashPageReadData.D16[pNum * (dDIRECTCTL_KEY_MAX_COUNT+2) + 8]; + tCrc.D16[1] = FlashPageReadData.D16[pNum * (dDIRECTCTL_KEY_MAX_COUNT+2) + 9]; + DirectCtlBoard[pNum].CrcArea = tCrc.D32; + if(DirectCtlBoard[pNum].CrcArea == Crc32GetResult()){ + if(DirectCtlBoard[pNum].CrcFlag.Area){ + DirectCtlBoard[pNum].CrcFlag.Area =0; + CtlCenter.ieAddBrdFaultCancel(pNum+dADDR_DIRECTPAD_START,TBoardFaultType::StorageEpArea); + } + }else{ + DirectCtlBoard[pNum].CrcFlag.Area =1; + CtlCenter.ieAddBrdFault(pNum+dADDR_DIRECTPAD_START,TBoardFaultType::StorageEpArea); + } + } + }else + if(Gg == 1){ + for(int pNum=10; pNum<20; pNum++){ + Crc32Reset(); + for(x=0; x<8; x++){ + DirectCtlBoard[pNum].Area[x] = FlashPageReadData.D16[(pNum-10) * (dDIRECTCTL_KEY_MAX_COUNT+2) + x]; + Crc32Feed(static_cast(DirectCtlBoard[pNum].Area[x])); + if(DirectCtlBoard[pNum].Area[x] > dAreaCountMax)DirectCtlBoard[pNum].Area[x] = 0; + } + tCrc.D16[0] = FlashPageReadData.D16[(pNum-10) * (dDIRECTCTL_KEY_MAX_COUNT+2) + 8]; + tCrc.D16[1] = FlashPageReadData.D16[(pNum-10) * (dDIRECTCTL_KEY_MAX_COUNT+2) + 9]; + DirectCtlBoard[pNum].CrcArea = tCrc.D32; + if(DirectCtlBoard[pNum].CrcArea == Crc32GetResult()){ + if(DirectCtlBoard[pNum].CrcFlag.Area){ + DirectCtlBoard[pNum].CrcFlag.Area =0; + CtlCenter.ieAddBrdFaultCancel(pNum+dADDR_DIRECTPAD_START,TBoardFaultType::StorageEpArea); + } + }else{ + DirectCtlBoard[pNum].CrcFlag.Area =1; + CtlCenter.ieAddBrdFault(pNum+dADDR_DIRECTPAD_START,TBoardFaultType::StorageEpArea); + } + } + } + } +} + +int TRecord::WriteLastMaintainTime() +{ + unsigned int aAddr, tVal; + //dEepAddrMaintainLast //Year Month Day + aAddr = dEepAddrMaintainLast; + LastMaintain.Cent = 0x20; + tVal = LastMaintain.FullDate; + DelayMs(20); + eeprom_write_byte_via_page(0, aAddr, &LastMaintain.D8[0], 16); + DelayMs(20); + + ReadLastMaintainTime(); + if(tVal != LastMaintain.FullDate)return -1; + return 0; +} + +void TRecord::ReadLastMaintainTime() +{ + unsigned int aAddr; + //dEepAddrMaintainLast //Day Month Year + aAddr = dEepAddrMaintainLast; + DelayMs(10); + eeprom_read_byte(0, aAddr, &LastMaintain.D8[0], 4); + + if( (LastMaintain.Day == 0) || (LastMaintain.Day >0x31) ) LastMaintain.Day = 1; + if( (LastMaintain.Month == 0) || (LastMaintain.Month >0x12) ) LastMaintain.Month = 1; + if( LastMaintain.Year >0x99 ) LastMaintain.Year = 0; + LastMaintain.Cent = 0x20; +} + +void TRecord::Task1000Ms() +{ + static unsigned int aTick; + if(aTick < 60){ + aTick++; + }else{ + aTick = 0; + SaveNewTime2Eep(); + } +} + \ No newline at end of file diff --git a/MyCode/src/record.h b/MyCode/src/record.h new file mode 100644 index 0000000..d46bc7a --- /dev/null +++ b/MyCode/src/record.h @@ -0,0 +1,892 @@ +#ifndef RECORD_H_ +#define RECORD_H_ + +#include "gType.h" +#include "TDateTime.h" + +#define PagePrg_Time 5 +#define Erase4K_Time 420 +#define Erase32K_Time 1620 +#define Erase64K_Time 2020 + +#define SizeOf64K 0x10000 +#define SizeOf32K 0x8000 +#define SizeOf4K 0x1000 +#define SizeOfPage 0x100 + +#define dRECORD_ITEMS_COUNT 256 + +#define dFrashFireUsingBlockCount (22) +#define dFrashLinkageUsingBlockCount (22) +#define dFrashSvUsingBlockCount (22) +#define dFrashFaultUsingBlockCount (22) +#define dFrashOperateUsingBlockCount (22) + +#define dFlashRegisterDataChip (0) +#define dFlashRegisterDataAddr (0x00CC'0000) +#define dFlashRegisterPortDataLen (0x1000) +#define dFlashRegisterPortCount (64) + +#define dFlashDisplayPadSetChip (0) +#define dFlashDisplayPadSet (0x00DA'0000) +#define dEepFloorDescpChip (0) +#define dFlashAddrFloorDescp (0x00DB'0000) +#define dEepDescpChip (0) +#define dFlashAddrDescpBase (0x00DC'0000) + +#define dFlashMaskChip 0x0 +#define dFlashAddrMask (0x00E7'0000) +#define dFlashAddrMask_II (0x00EB'0000) +#define dMaskCrcCntOffset ((65536*3) + (4096*15)) +#define dMaskNonDataIdf (0xB8F6'7C26) +#define dMaskBackupExistIdf (0xF765'DC69) + +#define dFlashNwUserCodeChipX (0) +#define dFlashNwUserCode (0x009C'0000) + +#define dFlash4AreaChip (0) +#define dFlash4Area (0x00BB'0000) + +#define dFlash4DevAreaNumChip (0) +#define dFlash4DevAreaNum (0x00D8'0000) + +//Flash Chip 1 +#define dFlashAddrDevUserCodeChip (1) +#define dFlashAddrDevUserCode (0x00D1'0000) +#define dFlashAddrDirectPadUserCode (0x00D3'8000) + +#define dFlashBusPadLnkChipX (1) +#define dFlashAddrBusPadLnk (0x00D6'0000) +#define dFlashDirectPadLnkChipX (1) +#define dFlashAddrDirectPadLnk (0x00D8'0000) + + + + +//EEP 0 512 K______________________________________> +#define dEepAddrFireWritingBlock (0x6000) +#define dEepAddrLinkageWritingBlock (0x6001) +#define dEepAddrSvWritingBlock (0x6002) +#define dEepAddrFaultWritingBlock (0x6003) +#define dEepAddrOperateWritingBlock (0x6004) + +#define dEepAddrMainSet (0) +#define dEepAddrProjectName (0x80) +#define dEepAddrCtlName (0xA0) +#define dEepAddrPassWordII (0x0100) +#define dEepAddrPassWordIII (0x0120) +#define dEepAddrCtlShutDownTime (384) + +#define dEepAddrDesignPrmXXXX (512) +#define dEepAddrNetworkCfg (768) + +//Page 7 +#define dEepAddrLicsence (896) //128*7= +//Page 8 +#define dEepAddrMainTain (1024) //128*8= + +//Page 9 Page 10 Page 11 Page 12..Page 19 +#define dEepAddrDesignPrm (1152) + +//Page 23 +#define dEepAddrBroadcastSetting (2944) +//Page 24 +#define dEepAddrFecBusSetting (3072) +//Page 25 +#define dEepAddrCtlMaskNum (3200) +//Page 26 +#define dEepAddrCrtCfg (3328) +//Page 27 +#define dEepAddrMaintainLast (3456) + +//Page 510 +#define dEepAddrAuthorizePrm (510*128)//pcs 0 + +#define dFlashLinkageExpChipX (1) +#define dFlashAddrLinkageExp (0x00DE'0000) +#define dFlashBlock64kCount4LinkageExp (32) + + +//_________________________________________________< +//Sdram +#define dSdramHistoryBytesLength (0x160000) +#define dSdramHistoryEntryCount (20000) +#define dSdramFireHistoryContentBaseAddr (0xC260'0000) +#define dSdramLinkageHistoryContentBaseAddr (0xC2A0'0000) +#define dSdramSvHistoryContentBaseAddr (0xC2E0'0000) +#define dSdramFaultHistoryContentBaseAddr (0xC320'0000) +#define dSdramOperateHistoryContentBaseAddr (0xC360'0000) + +typedef enum{ + otPowerOn =0, + otPowerOff =1, + otReset =2, + otMute, + otMask, + otUnMask, + otRegiste, + otUnRegiste, + otSetCanNetwork, + otCfgBoard, + otCfgCrt, + otCfgPriter, + otCfgDevice, + otCfgDateTime, + otCfgPermissionAllow, + otAllowSet, + otAlramSetOnOff, + + otBusPadOn, + otBusPadOff, + + otDirectPadManualAllowOn, + otDirectPadManualAllowOff, + otDirectPadNodeOn, + otDirectPadNodeOff, + + otUserCheck, + otLinkageGo, + otSetNwTime, + otReqNwTime, + + otSelfCheck, + + otSetManualAllowState, + otSetAutoAllowState, + otRemoteSetManualAllowState, + otRemoteSetAutoAllowState, + otReportManualAllowState, + otReportAutoAllowState, + + otFireConfirm, + otFaultConfirm, + otFireRemoteConfirm, + otFaultRemoteConfirm, + + otSetSmokeSensViaCircuit, + otSetSmokeSensViaAddr, + + otCleanUp, + otLinkageExpsSaveRemove, + otBusPadModify, + otDirectPadModify, + otDescpModify, + otPassWdModify, + otRegisterByManual, + otAddRemoveNwCtl, + + otRegCanNetwork, + otStartStop, + otClearNetworkCfg, + otBroadcastVa, + + otSetAllowState, + otRemoteSetAllowState, + otReportAllowState, + + otFireSimConfirm, + otFireSimRemoteConfirm + +}TOperateType; + +typedef enum{ + csIdle = 0, + csErassing = 1, + csCanTryResume =2, + csDoErase =3, + csBusy +}TChipState; + +/*typedef union{ + unsigned int D32[4]; + unsigned char D8[16]; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char HasRead; + unsigned char SourceProto; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char mType; + unsigned char dType; + unsigned char Data0; + unsigned char Data1; + }Splite; +}TRecordInnerMsg;*/ +typedef union{ + unsigned int D32[4]; + unsigned char D8[16]; +}TrcEepToWriteBuf; + +typedef union{ + unsigned int D32[4]; + unsigned short D16[8]; + unsigned char D8[16]; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char iByte0; + unsigned char iByte1; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char mType; + unsigned char dType; + unsigned char Data0; + unsigned char Data1; + }Splite; +}TRecordBody; + +typedef union{ + unsigned int D32[6]; + unsigned short D16[12]; + unsigned char D8[24]; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char iByte0; + unsigned char iByte1; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char mType; + unsigned char dType; + unsigned char Data0; + unsigned char Data1; + + unsigned int UserCode; + unsigned short AreaNum; + unsigned short DumpShort; + }Splite; +}TRecordCommon; + +typedef union{ + unsigned char D8; + struct{ + unsigned char Bit0 :1; + unsigned char Bit1 :1; + unsigned char Bit2 :1; + unsigned char Bit3 :1; + unsigned char Bit4 :1; + unsigned char Bit5 :1; + unsigned char Bit6 :1; + unsigned char Bit7 :1; + }BitF; + struct{ + unsigned char IsAutomatic :1; //0:Manual; 1:Automatic + unsigned char IsUsingStandByPower :1; //0:Using Main Power; 1:Using Standby Power + unsigned char IsPowerError :1; + unsigned char IsAlram :1; + unsigned char IsAction :1; + unsigned char IsFeedBack :1; + unsigned char IsSuperVisory :1; + unsigned char IsFault :1; + }BitFlag; +}TFecStateLowByte; + +typedef union{ + unsigned char D8; + struct{ + unsigned char Bit0 :1; + unsigned char Bit1 :1; + unsigned char Bit2 :1; + unsigned char Bit3 :1; + unsigned char Bit4 :1; + unsigned char Bit5 :1; + unsigned char Bit6 :1; + unsigned char Bit7 :1; + }BitF; + struct{ + unsigned char IsMask :1; + unsigned char IsGasSpay :1; + unsigned char IsEmergency :1; + unsigned char Rsv0 :1; + unsigned char Rsv1 :1; + unsigned char Rsv2 :1; + unsigned char Rsv3 :1; + unsigned char Rsv4 :1; + }BitFlag; +}TFecStateHiByte; + +typedef union{ + unsigned char D8[18]; + struct{ + unsigned char Dump; + unsigned char MainCtlNumLowByte; + unsigned char MainCtlNumHiByte; + unsigned char UnitNum; + unsigned char DeviceNum; + unsigned char ChannelNum; + unsigned char dTypeLowByte; + unsigned char dTypeHiByte; + unsigned char EventCodeLowByte; + unsigned char EventCodeHiByte; + TFecStateLowByte StateCodeLowByte; + TFecStateHiByte StateCodeHiByte; + unsigned char Year; // -2000 + unsigned char Month; // 1..12 + unsigned char Day; // 1..31 + unsigned char Hour; + unsigned char Minute; + unsigned char Second; + }Data; + struct{ + unsigned char code; + unsigned char Dump[17]; + }MyMsgCode; +}TRecordFecMsg; + +typedef union{ + //17 Bytes GB4717--202X 表B.2 数据信息格式 + unsigned char d8[20]; + struct{ + unsigned char CtlNumLoByte; + unsigned char CtlNumHiByte; + unsigned char UnitNum; + unsigned char DeviceNum; + unsigned char ChannelNum; + unsigned char DeviceTypeLoByte; + unsigned char DeviceTypeHiByte; + unsigned char EventCodeLoByte; + unsigned char EventCodeHiByte; + unsigned char StateCodeLoByte; + unsigned char StateCodeHiByte; + unsigned char Year; + unsigned char Month; + unsigned char Day; + unsigned char Hour; + unsigned char Minute; + unsigned char Second; + unsigned char Rsv0; + unsigned char Rsv1; + unsigned char Rsv2; + }spl; +}TRecodeOneMsg; + +typedef union{ + //using 27 byte + unsigned char D8[28]; + struct{ + unsigned char StartCode; //0x40 + unsigned char rNumLoByte; + unsigned char rNumMiByte; + unsigned char rNumHiByte; + unsigned char CtlAddr; + unsigned char CtlTypeLoByte; + unsigned char CtlTypeHiByte; + unsigned char CtlPn[20]; + }spl; +}TRecordMappingHeader; + +typedef union{ + unsigned char D8[4]; + struct{ + unsigned char CrcLoByte; + unsigned char CrcHiByte; + unsigned char EndCode; //0x40 + unsigned char Rsv0; + }spl; +}TRecordMappingEnding; + + +typedef union{ + unsigned char D8[16]; + struct{ + unsigned char StartCode; //0x40 + unsigned char CommanderIdf[8];//数据导出装置识别码，识别数据导出装置的权限。 + unsigned char Ver; //2 + unsigned char Addr; //数据导出专用工具地址，固定 0x7E + unsigned char ExporterType; //数据导出专用工具代码，固定 0x7F + unsigned char CmdLen; //1 表 B.4 + unsigned char Cmd; //表 B.4 ; 1=Read; 2=Repeat; 3=Read The First Fire Msg; 4=Read Fire Msg; + unsigned char CrcLoByte; + unsigned char CrcHiByte; + unsigned char EndCode; //0x40 + }spl; +}TExportData; + +typedef struct{ + union{ + unsigned long long fIndex; + struct{ + unsigned int Inx0; + unsigned int Inx1; + }D32; + }fIndex; + int WriteIndex; + int ReadIndex; + int EntryX; + int PageX; + int BlockX; + int sBlock; + int NeedCheckBlockEmpty; + int NeedCheckBlockEmpty2; + unsigned int BlockToBeErase; + unsigned int BlockToBeErase2; + + int NeedMarkWriteBlcokToEep; + unsigned char WritingBlockReadFromEep; + unsigned char wBlockWriteToEep; + + unsigned int SdramAddrStart; + unsigned int SdramAddrCurrent; + int Count; +}TBufToFlash; + +typedef union{ + unsigned char D8[64]; + unsigned int D32[16]; + struct{ + union { + unsigned long long fIndex; + struct{ + unsigned int sIndex0; + unsigned int sIndex1; + }spl; + }sIndex; //D32 0..1 + unsigned int UserCode; //D32 2 + TRecordBody Body; //D32 3..6 + unsigned char Descp[32];//D32 7..14 + unsigned int Crc; + }fData; +}TRecordEntry; + +typedef union{ + unsigned int D32[6]; + unsigned char D8[24]; + struct{ + unsigned char Second; + unsigned char Minute; + unsigned char Hour; + unsigned char Day; + + unsigned char Month; + unsigned char Year; + unsigned char iByte0; + unsigned char State; + + unsigned char PCtlNum; + unsigned char P0; + unsigned char P1; + unsigned char P2; + + unsigned char IsMask; + unsigned char dType; + unsigned char Dump3; + unsigned char Dump4; + + unsigned int UserCode; + unsigned short AreaNum; + unsigned short DumpShort; + }Body; +}TRecordMaskMsg; + +typedef union{ + unsigned long long fIndex; + struct{ + unsigned int sIndex0; + unsigned int sIndex1; + }spl; +}THisIndex; + +extern const unsigned char NwDescpUsingChip[68]; +extern const unsigned int NwDescpUsingFlashAddr[68]; + +class TRecord{ + public: + TRecordCommon FastBuf; + TRecordCommon iMsgRx; + TRecordCommon eOperateEvent; + public: + unsigned int PrimaryKeyWarning; + unsigned int fAddr; + union{ + unsigned char D8[64]; + unsigned int D32[16]; + }ToWriteBuf[4]; + + union{ + unsigned long long fIndex; + struct{ + unsigned int Inx0; + unsigned int Inx1; + }D32; + }sysIndex; + + unsigned char TmpIsAva[128]; + THisIndex TmpllIndex[128]; + union{ + unsigned long long fIndex; + struct{ + unsigned int sIndex0; + unsigned int sIndex1; + }spl; + }CmpllIndex1, CmpllIndex2; + + TBufToFlash Buf4Fire; + TBufToFlash Buf4Linkage; + TBufToFlash Buf4Sv; + TBufToFlash Buf4Fault; + TBufToFlash Buf4Operate; + + struct{ + TChipState Sta; + int FireOrSv; + int NeedCheckSvEmpty; + int SecX; + unsigned int Tick4_10Ms; + }RtChip0; + + struct{ + TChipState Sta; + int SvFaultOpa; + int NeedCheckSvEmpty; + int SecX; + unsigned int Tick4_10Ms; + }RtChip1; + //unsigned int Eep0WriteTick; + //unsigned int Eep1WriteTick; + + TRecordEntry EntryRead; + TRecordEntry EntryWrite; + + union{ + unsigned char D8[256]; + unsigned short D16[128]; + unsigned int D32[64]; + }FlashPageReadData; + unsigned char tData[8]; + + unsigned int aCsum; + TDMix Actu; + public: + TRecord(){}; + void Init(); + + int InnerMsgGetIfReadOk(unsigned int aIndex); + unsigned int InnerMsgGetDate(unsigned int aIndex); + unsigned char InnerMsgGetYear(unsigned int aIndex); + unsigned char InnerMsgGetMonth(unsigned int aIndex); + unsigned char InnerMsgGetDay(unsigned int aIndex); + unsigned int InnerMsgGetTime(unsigned int aIndex); + unsigned char InnerMsgGetHour(unsigned int aIndex); + unsigned char InnerMsgGetMinute(unsigned int aIndex); + unsigned char InnerMsgGetSecond(unsigned int aIndex); + unsigned char InnerMsgGet_mType(unsigned int aIndex); + unsigned char InnerMsgGet_dType(unsigned int aIndex); + unsigned char InnerMsgGet_CtlNum(unsigned int aIndex); + unsigned char InnerMsgGet_P0(unsigned int aIndex); + unsigned char InnerMsgGet_P1(unsigned int aIndex); + unsigned char InnerMsgGet_P2(unsigned int aIndex); + unsigned char InnerMsgGet_ValueHi(unsigned int aIndex); + unsigned char InnerMsgGet_ValueLow(unsigned int aIndex); + + void InnerMsgSetIfReadOk (unsigned int aIndex, unsigned char isReadOk); + void InnerMsgSetDate (unsigned int aIndex, unsigned int aDate); + void InnerMsgSetYear (unsigned int aIndex, unsigned char aYear); + void InnerMsgSetMonth (unsigned int aIndex, unsigned char aMonth); + void InnerMsgSetDay (unsigned int aIndex, unsigned char aDay); + void InnerMsgSetTime (unsigned int aIndex, unsigned int aTime); + void InnerMsgSetHour (unsigned int aIndex, unsigned char aHour); + void InnerMsgSetMinute (unsigned int aIndex, unsigned char aMinute); + void InnerMsgSetSecond (unsigned int aIndex, unsigned char aSecond); + void InnerMsgSet_mType (unsigned int aIndex, unsigned char aMtype); + void InnerMsgSet_dType (unsigned int aIndex, unsigned char aDtype); + void InnerMsgSet_CtlNum (unsigned int aIndex, unsigned char aCtlNum); + void InnerMsgSet_P0 (unsigned int aIndex, unsigned char aP0); + void InnerMsgSet_P1 (unsigned int aIndex, unsigned char aP1); + void InnerMsgSet_P2 (unsigned int aIndex, unsigned char aP2); + void InnerMsgSet_Data0 (unsigned int aIndex, unsigned char aVh); + void InnerMsgSet_Data1 (unsigned int aIndex, unsigned char aVl); + void InnerMsgSet_iByte0 (unsigned int aIndex, unsigned char aB); + void InnerMsgSet_iByte1 (unsigned int aIndex, unsigned char aB); + + void FlushToWriteBuf(); + + //_____________________________________>>>>> + unsigned int CheckChipF0Idle(void); + unsigned int CheckChipF1Idle(void); + unsigned int CheckChipF0_SectorEmpty(unsigned int aAddr); + unsigned int CheckChipF1_SectorEmpty(unsigned int aAddr); + + void LoadOperateEventDateTimeFromCharPointer(unsigned char *aDt); + void LoadOperateEventDateTimeFromCurrent(); + + //Add Function + //_____________________________________>>>>> Fire Add + void FireAdd(TRecordCommon aRC); + void TryFireWriteToFlash(); + + //Linkage ADD + void LinkageAdd(TRecordCommon aRC); + + //Sv Add + void SvAdd(TRecordCommon aRC); + + //_____________________________________>>>>> Fault Add + void FaultAdd(TRecordCommon aRC); + + //_____________________________________>>>>> + void OperateAdd(TRecordCommon aRC); + void OperateAddFromNw(TRecordCommon aRC); + void OperateFindNextSector(); + void OperateWriteToEepRom(); + void OperateTryEraseSector(); + //_______________________________________________________________> + void OperateAdd_PowerOff(unsigned char aCn); + void OperateAdd_PowerUp(unsigned char aCn); + void OperateAdd_Reset(unsigned char aCn); + void OperateAdd_Mute(unsigned char aCn); + void OperateAdd_Mask(TDMix aFullPath, unsigned char aDType, unsigned int aUc); + void OperateAdd_UnMask(TDMix aFullPath, unsigned char aDType, unsigned int aUc); + void OperateAdd_Registe(unsigned char Sta); + void OperateAdd_UnRegiste(TDMix aFullPath, unsigned char aDType); + void OperateAdd_SetCanNetwork(unsigned char NwType, unsigned char aCn); + void OperateAdd_CfgBoard(TDMix aFullPath, unsigned char aDType); + void OperateAdd_CfgCrt(); + void OperateAdd_CfgPriter(unsigned char aOnOff, unsigned int aEvevtInc); + void OperateAdd_CfgPritEventType(); + void OperateAdd_CfgDevice(TDMix aFullPath, unsigned char aDType); + void OperateAdd_CfgDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec); + void OperateAdd_SetNwDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec); + void OperateAdd_ReqNwDateTime(); + void OperateAdd_CfgPermissionAllow(unsigned char aPa); + + void OperateAdd_AllowState(unsigned char aCn, unsigned char aAllowAuto, unsigned char aAllowManual); + void OperateAdd_ScreenKeyLock(unsigned char aScreenSave, unsigned char EnterSaveTime, unsigned char aLock, char *aCr); + + void OperateAdd_ManualStart (unsigned int aPath, unsigned char aType, unsigned char aSubType); + void OperateAdd_ManualStartCancel (unsigned int aPath, unsigned char aType, unsigned char aSubType); + void OperateAdd_ManualFb (unsigned int aPath, unsigned char aType, unsigned char aSubType); + + void OperateAdd_AlramSoundOn(unsigned char aCn); + void OperateAdd_AlramSoundOff(unsigned char aCn); + + void OperateAdd_BusPadOn(unsigned char aCn, unsigned char aP0, unsigned char aP1); + void OperateAdd_BusPadOff(unsigned char aCn, unsigned char aP0, unsigned char aP1); + + void OperateAdd_DirectPadManualAllowOn(unsigned char aCn, unsigned char aP0); + void OperateAdd_DirectPadManualAllowOff(unsigned char aCn, unsigned char aP0); + void OperateAdd_DirectPadNodeOn(unsigned char aCn, unsigned char aP0, unsigned char aP1); + void OperateAdd_DirectPadNodeOff(unsigned char aCn, unsigned char aP0, unsigned char aP1); + void OperateAdd_UserCheck(unsigned char aCn, unsigned char OnOff); + void OperateAdd_SelfCheck(unsigned char aCn); + void OperateAdd_MasterLinkageGo(unsigned char aCn); + void OperateAdd_SlaveLinkageGo(unsigned char aCn); + + void OperateAdd_PowerOff(unsigned char aCn, unsigned char *aDt); + void OperateAdd_PowerUp(unsigned char aCn, unsigned char *aDt); + void OperateAdd_Reset(unsigned char aCn, unsigned char *aDt); + void OperateAdd_Mute(unsigned char aCn, unsigned char *aDt); + void OperateAdd_Mask(TDMix aFullPath, unsigned char aDType, unsigned char *aDt, unsigned int aUserCode, unsigned short aAreaNum); + void OperateAdd_UnMask(TDMix aFullPath, unsigned char aDType, unsigned char *aDt, unsigned int aUserCode, unsigned short aAreaNum); + void OperateAdd_Registe(TDMix aFullPath, unsigned char aDType, unsigned char *aDt); + void OperateAdd_UnRegiste(TDMix aFullPath, unsigned char aDType, unsigned char *aDt); + void OperateAdd_SetCanNetwork(unsigned char aCn, unsigned char sAddr, unsigned char mAddr, unsigned char *aDt); + void OperateAdd_CfgBoard(TDMix aFullPath, unsigned char aDType, unsigned char *aDt); + void OperateAdd_CfgCrt(unsigned char *aDt); + void OperateAdd_CfgPriter(unsigned char *aDt); + void OperateAdd_CfgPritEventType(unsigned char *aDt); + void OperateAdd_CfgDevice(TDMix aFullPath, unsigned char aDType, unsigned char *aDt); + void OperateAdd_CfgCircuitSmokeSensGrade(unsigned int aFullPath, unsigned char Grade); + void OperateAdd_CfgAddrSmokeSensGrade(unsigned int aFullPath, unsigned char Grade); + void OperateAdd_CfgDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec, unsigned char *aDt); + void OperateAdd_CfgPermissionAllow(unsigned char aPa, unsigned char *aDt); + + void OperateAdd_AllowState(unsigned char aCn, unsigned char aAllowAuto, unsigned char aAllowManual, unsigned char *aDt); + void OperateAdd_ScreenKeyLock(unsigned char aScreenSave, unsigned char EnterSaveTime, unsigned char aLock, char *aCr, unsigned char *aDt); + + void OperateAdd_AlramSoundOn(unsigned char aCn, unsigned char *aDt); + void OperateAdd_AlramSoundOff(unsigned char aCn, unsigned char *aDt); + + void OperateAdd_BusPadOn(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt); + void OperateAdd_BusPadOff(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt); + + void OperateAdd_DirectPadManualAllowOn(unsigned char aCn, unsigned char aP0, unsigned char *aDt); + void OperateAdd_DirectPadManualAllowOff(unsigned char aCn, unsigned char aP0, unsigned char *aDt); + void OperateAdd_DirectPadNodeOn(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt); + void OperateAdd_DirectPadNodeOff(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt); + void OperateAdd_UserCheck(unsigned char aCn, unsigned char OnOff, unsigned char *aDt); + void OperateAdd_SelfCheck(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char *aDt); + void OperateAdd_LinkageGo(unsigned char aCn, unsigned char *aDt); + + void OperateAdd_GetDateTime(u8 aY, u8 aM, u8 aD, u8 aH, u8 aMin, u8 aSec); + + void OperateAdd_ManualAllowSet(unsigned char aCn, unsigned char aAllow); + void OperateAdd_AutoAllowSet(unsigned char aCn, unsigned char aAllow); + void OperateAdd_AllowSet(unsigned char aCn, unsigned char aAllow); + void OperateAdd_ManualAllowRemoteSet(unsigned char aCn, unsigned char aAllow); + void OperateAdd_AutoAllowRemoteSet(unsigned char aCn, unsigned char aAllow); + void OperateAdd_AllowRemoteSet(unsigned char aCn, unsigned char aAllow); + void OperateAdd_ManualAllowReport(unsigned char aCn, unsigned char aAllow); + void OperateAdd_AutoAllowReport(unsigned char aCn, unsigned char aAllow); + void OperateAdd_AllowReport(unsigned char aCn, unsigned char aAllow); + + void OperateAdd_FireConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned int aUc, unsigned char IsSim); + void OperateAdd_FaultConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char dType, unsigned char fType, unsigned char Data1, unsigned int aUc); + + void OperatePublic_FireRemoteConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned char IsSim); + void OperatePublic_FaultRemoteConfirm(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char dType, unsigned char fType, unsigned char Data1); + //----2024 07 10 --> + void OperateAdd_CleanUp(unsigned char cType); + void OperateAdd_LinkageExpsModify(unsigned char IsAdd, unsigned int eInx); + void OperateAdd_BusPadModifyModify(unsigned char aP0, unsigned int aP1); + void OperateAdd_DirectPadModify(unsigned char aP0); + void OperateAdd_DescpModify(unsigned char aP0, unsigned char aP1); + void OperateAdd_PassWdModify(unsigned char aLvl); + void OperateAdd_RegisterByManual(unsigned char aP0, unsigned char sAddr, unsigned char eAddr, unsigned char aType, unsigned char IsAdd); + void OperateAdd_AddRemoveNwCtl(unsigned char Act, unsigned char aCtlNum); + void OperateAdd_RegCanNetwork(unsigned char NwType, unsigned char aCtlNum, unsigned char SlaveCount); + void OperateAdd_StartStop(unsigned char aCn, unsigned char aP0, unsigned char aP1, unsigned char aType, unsigned char IsSatrt); + void OperateAdd_ClearNetworkCfg(); + void OperateAdd_BroadcastVa(unsigned char aPadNum, unsigned char aAddr, unsigned char aMode); + + + //_____________________________________<<<<< + void DelayMs(unsigned int aMs); + void Task10Ms(); + void Task1000Ms(); + void Task5000Ms(); + + void Wait10Ms(); + + void GetFireEntry(int aInx); + void PrcFireWrite(); + void GetLinkageEntry(int aInx); + void PrcLinkageWrite(); + void WaitChipIdle(unsigned int ChipX); + + void GetSvEntry(int aInx); + void PrcSvWrite(); + void GetFaultEntry(int aInx); + void PrcFaultWrite(); + void GetOperateEntry(int aInx); + void PrcOperateWrite(); + + void MsgReadInit(unsigned int aChip, TBufToFlash *aBuf, unsigned int aFlashBaseAddr, int aPstY); + void MsgReadInit2(unsigned int aChip, TBufToFlash *aBuf, unsigned int aFlashBaseAddr, int aPstY); + void MsgReadInit3(unsigned int aChip, TBufToFlash *aBuf, unsigned int aFlashBaseAddr, int aPstY); + + void Chip0Prc(); + void Chip1Prc(); + + void AllMsgReadInit(); + + void ClearFireHistory(); + void ClearLinkageHistory(); + void ClearSvHistory(); + void ClearFaultHistory(); + void ClearOperateHistory(); + + void LoadFireHistory(); + void LoadLinkageHistory(); + void LoadSvHistory(); + void LoadFaultHistory(); + void LoadOperateHistory(); + + int CheckHistoryCSum(unsigned char *p); + void WriteRegisterData(); + void ReadRegisterDataOnePort(unsigned char aPort); + void ReadRegisterData(); + void ReadProjAndCtlDescp(); + void ReadDescp(); + void ReadDescpNw(); + void FloorDescp(); + + void LoadBusPadLnk(unsigned char aPad); + void LoadBusPadLnk(); + void LoadDirectPadCfg(unsigned char aPath0); + void LoadDirectPadCfg(); + void ReadPortDisplayPadSet(unsigned char aPort); + void ReadDisplayPadSet(); + void ReadDesignPrm(); + void ReadMainSet(); + void ReadAllowSet(); + void ReadPrintSet(); + void ReadScreenSave(); + void ReadLanguage(); + + void WriteMaintain(unsigned char *p); + void ReadMaintain(); + + void SaveNewTime2Eep(); + void WriteMainSetMainCtl(unsigned char aIsMaster, unsigned char aCtlNum); + void WritePrinterState(unsigned char aSta); + void WritePrinterEvent(unsigned char aEvent); + void WriteAllow(unsigned char aAllowAuto, unsigned char aAllowManual); + void WriteScreenKeyLock(unsigned char aScreenSave, unsigned char EnterSaveTime, unsigned char aLock, char *aCr); + void WriteGraphSet(unsigned int aBrd, unsigned char aIntavalMs, unsigned char aIsHaft, unsigned char RpyDelayUs, unsigned char RpyTimeMs); + void WriteLanguage(unsigned char aNew); + + void WritePowerSuplyCount(unsigned char aSubExist0, unsigned char aSubExist1); + void ReadPowerSuplyCount(); + + void SaveNwCfg(unsigned char aMasterNum, unsigned char aSlaveCount, unsigned char *aList); + void ReadNwCfg(); + void SaveNwM2MCfg(unsigned char aCnt, unsigned char *aList); + void ReadNwM2MCfg(); + + void ReadDevUserSet(); + void ReadDirectPadUserSet(unsigned char aPath0); + void ReadDirectPadUserSet(); + + void Read4Area(); + void ReadDevAreaNum(); + void ReadDirectPadAreaNum(); + + int WriteLastMaintainTime(); + void ReadLastMaintainTime(); + + void CheckPrimaryKeyWarning(); +}; + + + + + + + + + + + + + + + + + + + + + + + +#endif + + diff --git a/MyCode/src/server.cpp b/MyCode/src/server.cpp new file mode 100644 index 0000000..fffc3a2 --- /dev/null +++ b/MyCode/src/server.cpp @@ -0,0 +1,1825 @@ +#include "gType.h" +#include "gvalue.h" +#include "RuntimeData.h" +#include "Runtime.h" +#include "Gui.h" +#include "CnCpp.h" +#include "ControlCenter.h" +#include "extern_C_include.h" +#include "server.h" + +extern "C"{ + #include "uart_key_drv.h" + #include "uart_linkage_drv.h" + #include "uart_printer_drv.h" + #include "fdcan_task.h" + #include "task.h" +} + +//const char ConstTestStr[64] = L"ABCDBDE"; + +void ProcessInnerCanRxMsg(); +void fNetworkService(void); +void ProcessUserAlramKey(void); +void CheckDelayStart(); +void SelfCheckReturn(); +void DebugAdd250Fault(); +void uart_key_task(); +void StartupPasswdGuiCheck(); +void RecallCrcFaultMsg(); + +char TestStr[64]; + +int ShrOrg; + +unsigned char IsMenuOperate = 0; +static TRecordCommon sIm; + +static TCanHeaderID tIde; +static unsigned char tData[8]; + +const static unsigned char cMonthDaysCount[12] = {31, 28, 31, 30, 31, 30, + 31, 31, 30, 31, 30, 31}; +static int DtStartupCrt = 0; +static unsigned char DtCrt[6]; + +struct { + unsigned char dType; + unsigned char ID; + unsigned char PortNum; + unsigned char dump; +}DeviceItem; + +enum{ + IsMenuLevel0 = 0, + ISMenuLevel1, + IsDeviceCheck, + +}MenuActionList; + +enum{ + rtIdle = 0, + rtUserOprate, + rt +}rtState; + +typedef union{ + unsigned int D32; + struct{ + unsigned char PCtl; + unsigned char P0; + unsigned char P1; + unsigned char P2; + }Body; +}TDMix_Path; + +void DelayMs(unsigned int aMs) +{ + volatile unsigned int mTick; + volatile unsigned int Tick; + for(Tick=0; Tick1){ + HotKeyAlramCallBack(); + }else{ + PmsIntervene.Show4Alram(); + } + }else + if(aKey == HOTKEY_LINKAGE_START){ + if(Register.IsOnGo)return; + if(AllowManual){ + LinkageManualGo = 1; + CtlCenter.CheckHydrantKpActionForce(); + if(MainCtl.fData.Split.NetworkMode == 1){ + Record.OperateAdd_MasterLinkageGo(MainCtl.fData.Split.MyNum); + }else{ + Record.OperateAdd_SlaveLinkageGo(MainCtl.fData.Split.MyNum); + } + } + }else + if(aKey == HOTKEY_INF_CONF){ + //This Run In EventShow + }else + if(aKey == HOTKEY_SELF_CHECK){ + if(SystemPermission >1){ + HotKeySelfCheckCallBack(); + }else{ + PmsIntervene.Show4SelfCheck(); + } + }else + if(aKey == HOTKEY_MUTE){ + if(AlarmSoundWhat < 4){ + AlarmSoundWhat = 0x07; + Record.OperateAdd_Mute(MainCtl.fData.Split.MyNum); + IsMute = 0xA5; + IsMuteFire = 0xA5; + IsMuteLnk = 0xA5; + IsMuteSv = 0xA5; + IsMuteFault = 0xA5; + + FecStd.TriggerCmd02SysMute(); + FecBusCRT.setFecBusCRTMsg02(0); + } + }else + if(aKey == HOTKEY_RESET){ + //ProtoC2C.PublishEventReset(); + if(Register.IsOnGo)return; + if(SystemPermission >1){ + HotKeyResetCallBack(); + }else{ + PmsIntervene.Show4Reset(); + } + }else + if(aKey == HOTKEY_CHECK){ + if(Register.IsOnGo)return; + if(EventShow.IsGoReset == 0){ + MainMenu.Hide(); + CheckNormal.Init(0, 36, 800, 406, 0, 0, clMedGray); + //EventShow.MakeFastCheck(); + EventShow.KeyJab(); + EventShow.Hide(); + PageIdle.Hide(); + Record.ReadDesignPrm(); + CheckNormal.Show(); + CheckNormal.pDesignPrmSet = &DesignPrmSet; + CheckNormal.LoadAndDrawData(); + GuiState = guiCheckNormal; + } + }else + if(aKey == VK_OEM_JUMP){ + if( AllowAuto == 0 ){ + AllowAuto = 1; + AllowManual = 0; + }else{ + AllowAuto = 0; + AllowManual = 2; + } + Allow.ExtChange(AllowAuto); + ProcessUserSetAutoState(); + ExRecord.SetStateCodeAutoManual(); + FecBusCRT.SetStateCodeAutoManual(); + Record.OperateAdd_AllowSet(MainCtl.fData.Split.MyNum, AllowAuto + AllowManual); + }else + if( (aKey == HOTKEY_AUTO_ALLOW) || (aKey == HOTKEY_MANUAL_ALLOW) ){ + if(aKey == HOTKEY_AUTO_ALLOW){ + if(AllowAuto){ + if(AllowManual){ + AllowAuto = 0; + }else{ + return; + } + }else{ + AllowAuto = 1; + } + ProcessUserSetAutoState(); + ExRecord.SetStateCodeAutoManual(); + FecBusCRT.SetStateCodeAutoManual(); + Record.OperateAdd_AutoAllowSet(MainCtl.fData.Split.MyNum, AllowAuto); + } + if(aKey == HOTKEY_MANUAL_ALLOW){ + if(AllowManual){ + if(AllowAuto){ + AllowManual = 0; + }else{ + return; + } + }else{ + AllowManual = 1; + } + ProcessUserSetManualState(); + ExRecord.SetStateCodeAutoManual(); + FecBusCRT.SetStateCodeAutoManual(); + Record.OperateAdd_ManualAllowSet(MainCtl.fData.Split.MyNum, AllowManual); + } + } +} + +void CheckNormalReturn() +{ + CheckNormal.Hide(); + EventShow.MakeFastCheck(); + if( (EventShow.MsgList[0].Count != 0) || + (EventShow.MsgList[1].Count != 0) || + (EventShow.MsgList[2].Count != 0) || + (EventShow.MsgList[3].Count != 0) || + (EventShow.MsgList[4].Count != 0) ){ + GuiState = guiShowEvent; + EventShow.MakeShow(); + }else{ + GuiState = guiIdle; + PageIdle.Show(); + } +} + +void SelfCheckReturn() +{ + EventShow.FirstFireHadDraw = 0; + EventShow.MakeFastCheck(); + if( (EventShow.MsgList[0].Count != 0) || + (EventShow.MsgList[1].Count != 0) || + (EventShow.MsgList[2].Count != 0) || + (EventShow.MsgList[3].Count != 0) || + (EventShow.MsgList[4].Count != 0) ){ + GuiState = guiShowEvent; + EventShow.MakeShow(); + }else{ + GuiState = guiIdle; + PageIdle.Show(); + } +} + +void Service_CheckDevFault() +{ + int i; + if(IsShowingMsgReset)return; + if(KeyPadData.HasUpdate){ + KeyPadData.HasUpdate = 0; + i = 0; + if(PowerSuplyStateOld != PowerSuplyState){ + if(PowerSuplyState){ + CtlCenter.ieAddDevFault(dDevFaultPowerSuply, 0); + }else{ + CtlCenter.ieAddDevFaultCancel(dDevFaultPowerSuply, 0); + } + PowerSuplyStateOld = PowerSuplyState; + ExRecord.SetStateCodePsOnActive(); + FecBusCRT.SetStateCodePsOnActive(); + } + + if(PowerSuplyCommOld != PowerSuplyComm){ + if(PowerSuplyComm){ + CtlCenter.ieAddDevFault(dDevFaultPowerSuplyComm,0); + }else{ + CtlCenter.ieAddDevFaultCancel(dDevFaultPowerSuplyComm,0); + } + PowerSuplyCommOld = PowerSuplyComm; + i = 1; + } + + if(PowerBkStateOld != PowerBkState){ + if(PowerBkState){ + CtlCenter.ieAddDevFault(dDevFaultPowerBk,0); + }else{ + CtlCenter.ieAddDevFaultCancel(dDevFaultPowerBk,0); + } + PowerBkStateOld = PowerBkState; + i = 1; + } + + if(BatStateOld != BatState){ + if(BatState){ + CtlCenter.ieAddDevFault(dDevFaultBat,0); + }else{ + CtlCenter.ieAddDevFaultCancel(dDevFaultBat,0); + } + BatStateOld = BatState; + i = 1; + } + + if(PowerSuplyOutputOld != PowerSuplyOutput){ + if(PowerSuplyOutput){ + CtlCenter.ieAddDevFault(22,0); + }else{ + CtlCenter.ieAddDevFaultCancel(22,0); + } + PowerSuplyOutputOld = PowerSuplyOutput; + i = 1; + } + + if(Bat1UnderVoltageOld != Bat1UnderVoltage){ + if(Bat1UnderVoltage){ + CtlCenter.ieAddDevFault(24,0); + }else{ + CtlCenter.ieAddDevFaultCancel(24,0); + } + Bat1UnderVoltageOld = Bat1UnderVoltage; + i = 1; + } + + if(Bat2UnderVoltageOld != Bat2UnderVoltage){ + if(Bat2UnderVoltage){ + CtlCenter.ieAddDevFault(25,0); + }else{ + CtlCenter.ieAddDevFaultCancel(25,0); + } + Bat2UnderVoltageOld = Bat2UnderVoltage; + i = 1; + } + + if(i){ + ExRecord.SetStateCodePsError(); + FecBusCRT.SetStateCodePsError(); + } + } +} + +void StartupPasswdGuiCheck() +{ + if(DialogStartup.CheckToShow()){ + DialogStartup.Show(); + DialogStartup.ShowSeries(MainCtl.Sn); + while(DialogStartup.CheckSkip() == 0){ + SysLoopTick = 0; + uart_key_task(); + if(KeyRdy == 0)continue; + KeyRdy =0; + (void)DialogStartup.KeyIn( KeyValue); + } + } +} + +void Service_Gui(void) +{ + TGuiMsgReturn aMsg; + unsigned int RequstReturn; + static TGuiState aGuiState = guiIdle; + static TGuiState GuiStateOld = guiIdle; + static TGuiState GuiStateBak = guiIdle; + unsigned int aAva =0; + + ShrOrg = -25; + ShrOrg >>= 1; + + if(KeyRdy == 0)return; + TipPopup.ClearTickOnKeyPress(); + + GeneralDev.LcdBlackLightSetOn(); + + if(GuiState == guiStateRemote){ + KeyRdy = 0; + return; + } + + KeyRdy =0; + SystemPermissionTick = 0; + if(EventShow.IsGoReset){ + KeyRdy =0; + return; + } + if( (LiteSelfCheck.IsShowing) ){ + KeyRdy =0; + return; + } + if(PmsIntervene.IsShow){ + aMsg = PmsIntervene.KeyIn(KeyValue); + if(aMsg == guiMsgReturn){ + //reDraw + } + + KeyValue = VK_NONE; + + if(aAva ==1){ + EventShow.KeyJab(); + } + SystemPermissionTick = 0; + return; + } + + //if(KeyValue == '1')Test_AddMask1(); + //if(KeyValue == '2')Test_AddUnMask1(); + //if(KeyValue == '4')Test_AddMask2(); + //if(KeyValue == '5')Test_AddUnMask2(); + + if(GuiState != GuiStateOld){ + GuiStateOld = GuiState; + } + + GuiCheckHotKey(KeyValue); + + if(TipPopup.IsShow){ + GuiState = guiTipPopup; + }else + if(EventShow.IsShowing){ + GuiState = guiShowEvent; + } + + if( (GuiState == guiIdle) || (GuiState == guiTipPopup) ){ + if(KeyValue == VK_MENU){ + GuiStateBak = GuiState; + GuiState = guiMenu; + PageIdle.Hide(); + EventShow.Hide(); + TipPopup.Hide(); + MainMenu.aPanel = &CtlPanelLite; + MainMenu.Show(); + aAva = 1; + }else + if(KeyValue == VK_F2){ + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + PageIdle.Hide(); + MainMenu.Hide(); + TipPopup.Hide(); + } + }else + if(KeyValue == VK_RETURN){ + if(GuiState == guiTipPopup){ + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + PageIdle.Hide(); + MainMenu.Hide(); + TipPopup.Hide(); + }else{ + MainMenu.Hide(); + TipPopup.Hide(); + PageIdle.Show(); + GuiState = guiIdle; + } + } + } + }else + if(GuiState == guiShowEvent){ + if(KeyValue == VK_MENU){ + GuiStateBak = GuiState; + GuiState = guiMenu; + PageIdle.Hide(); + EventShow.Hide(); + MainMenu.aPanel = &CtlPanelLite; + MainMenu.Show(); + aAva = 1; + }else{ + aMsg = EventShow.KeyIn(KeyValue); + /* Not return to Idle + if(aMsg == guiMsgReturn){ + EventShow.MakeFastCheck(); + EventShow.Hide(); + GuiState = guiIdle; + PageIdle.Show(); + }*/ + } + }else + if(GuiState == guiMenu){ + aMsg = MainMenu.KeyIn(KeyValue); + if(aMsg == guiMsgReturn){ + MainMenu.Hide(); + EventShow.MakeFastCheck(); + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + GuiState = guiShowEvent; + PageIdle.Hide(); + EventShow.MakeShow(); + }else{ + GuiState = guiIdle; + EventShow.Hide(); + PageIdle.Show(); + } + } + + aAva = 1; + }else + if(GuiState == guiCheckNormal){ + aMsg = CheckNormal.KeyIn(KeyValue); + if(aMsg == guiMsgReturn){ + CheckNormal.Hide(); + EventShow.MakeFastCheck(); + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + GuiState = guiShowEvent; + EventShow.MakeShow(); + }else{ + GuiState = guiIdle; + EventShow.Hide(); + PageIdle.Show(); + } + } + } + + KeyValue = VK_NONE; + + if(aAva ==1){ + EventShow.KeyJab(); + } +} + +void PreventPermissionDown() +{ + SystemPermissionTick = 0; +} + +void Service_Time_1mS(void) +{ + //On tick + CtlCenter.Task1Ms(); + C2cCompletedTick += get_excan_linkage_tx_complete(); +} +/* +void ManageStartCountDown() +{ + //Not On tick + int nSInx, Cnt; + int i,x; + unsigned char aP0, aP1; + + if(EventShow.StartCountDownList.Count > 0){ + for(i=0; i -1){ + EventShow.StartCountDownList.Path[nSInx] = EventShow.StartCountDownList.Path[i]; + EventShow.StartCountDownList.TimeSec[nSInx] = EventShow.StartCountDownList.TimeSec[i]; + EventShow.StartCountDownList.Path[i] = 0; + nSInx++; + } + Cnt++; + } + } + EventShow.StartCountDownList.Count = Cnt; + } +} +*/ +void Service_Time_10mS(void) +{ + //Not On Tick + Record.Task10Ms(); + InterLink.DoLnk(); + InterLink.Task10Ms(); + CtlCenter.Task10Ms(); + InnerCan.OBufCheckSend(); + ProtoC2C.Task10Ms(); + //fNetworkReg.Task10Ms(); + DoPrint.Task10Ms(); + ExRecord.Task10Ms(); + FecBusCRT.Task10Ms(); + FecStd.Task10ms(); + Config.Task10Ms(); + MqttData.Task10Ms(); +} + + +void DateTimeCrt() +{ + +} + +void Service_Time_100mS(void) +{ + //Not On Tick + static unsigned int tick100ms; + static unsigned int tick500ms; + static unsigned int tick1000ms; + static unsigned int tick4Hour =0; + + int d; + + SysLoopTick = 0; + TaskTimeUpData(); + + tick100ms++; + if(tick100ms){ + tick100ms = 0; + + if(CtlCenter.ieGot){ + CtlCenter.ieGot = 0; + EventShow.NoNewEventTick500mS = 0; + } + + FecStd.Task100ms(); + } + + tick500ms++; + if(tick500ms > 4){ + tick500ms = 0; + if(CheckNormal.Task500Ms() == -1)CheckNormalReturn(); + } + + tick1000ms++; + if(tick1000ms == 2){ + if(IsShowingMsgReset == 0){ + MotherBoard.CheckOnlineTask(); + ExRecord.Task1000Ms(); + StateBar_Pwr_SelfCheck(); + + KeyPad.CheckKeyPadOffline(); + DisplayPadDescpDownload.Task1000Ms(); + } + }else + if(tick1000ms == 4){ + ProtoC2C.CheckInBufCount(); + PmsIntervene.Task1000Ms(); + CtlCenter.CheckBatUpdate(); + if(GolbalDelayTick)GolbalDelayTick--; + CheckDelayStart(); + }else + if(tick1000ms == 6){ + for(d=0; d9){ + tick1000ms = 0; + tick4Hour++; + if(tick4Hour > 3599){ + tick4Hour = 0; + TimeSecHasRun++; + } + + //Not On Tick Run + ProtoC2C.Task1000Ms(); + + d = EventShow.Task1000Ms(); + if(EventShow.IsGoReset == 0){ + if(EventShow.IsShowing){ + GuiState = guiShowEvent; + CheckNormal.Hide(); + PageIdle.Hide(); + MainMenu.Hide(); + } + if(1 == d){ + if(EventShow.IsShowing){ + CheckNormal.Hide(); + PageIdle.Hide(); + MainMenu.Hide(); + } + }else + if(0 == d){ + if(EventShow.IsShowing){ + MainMenu.Hide(); + EventShow.Hide(); + PageIdle.Show(); + GuiState = guiIdle; + } + }else + if(-1 == d){ + MainMenu.Hide(); + EventShow.Hide(); + PageIdle.Show(); + GuiState = guiIdle; + } + } + + CtlCenter.Task1000Ms(); + //ManageStartCountDown(); + + if( (Register.IsOnGo) && (Register.IsOnNetwork == 2) ){ + GeneralDev.LcdBlackLightSetOn(); + Register.SlaveModeTask1000Ms(); + }else + if(MainMenu.OnAction){ + (void)Register.Task1000Ms(); + OnlineCtrl.Task1000Ms(); + //SimRun.Task1000Ms(); + FwUpgrade.Task1000Ms(); + CanNetworkRegister.Task1000Ms(); + DevMask.Task1000Ms(); + RegisterManual.Task1000Ms(); + //CircuitCfg.Task1000Ms(); + DevProperty.Task1000Ms(); + DevStartStop.Task1000Ms(); + DirectPadCfg.Task1000Ms(); + DuplicateCheck.Task1000Ms(); + HwInf.Task1000Ms(); + + ClearRegistedInf.Task1000Ms(); + ClearLinkageCfg.Task1000Ms(); + ClearDescp.Task1000Ms(); + DevOutputCfg.Task1000Ms(); + DevSensitiveCfg.Task1000Ms(); + DevVaCfg.Task1000Ms(); + } + RunModeCfg.Task1000Ms(); + + PageIdle.TaskBySecCall(); + + SystemPermissionTick++; + if(SystemPermissionTick > 89){ + SystemPermissionTick = 90; + SystemPermission = 1; + if(MainMenu.Active){ + MainMenu.Hide(); + EventShow.MakeFastCheck(); + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + PageIdle.Hide(); + GuiState = guiShowEvent; + }else{ + GuiState = guiIdle; + PageIdle.Show(); + } + }else + if(PageIdle.IsShowing){ + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + PageIdle.Hide(); + GuiState = guiShowEvent; + } + } + } + FecBusCRT.Upload2CrtTask(); + + } + + if(Sys_1s_Rdy){ + Sys_1s_Rdy = 0; + MaintainHourTick++; + FecBusCRT.Task1000Ms(); + + DevAuthorize.Task1000Ms(); + + uInportExport.Task1000Ms(); + + MqttData.Task1000Ms(); + + if(MaintainHourTick > 3599){ + MaintainHourRdy =1; + Check4MaintainToShow(); + if(LastMaintainTip != IsMaintainTip){ + if(IsSelfChecking == 0){ + StateBarReflashMaintain(); + } + LastMaintainTip = IsMaintainTip; + } + MaintainHourRdy =0; + } + } + + if(ProtoC2C.RemoteReq.Reg.IsRequsting){ + ProtoC2C.RemoteReq.Reg.IsRequsting = 0; + if(ProtoC2C.RemoteReq.Reg.RegPath <= dPORT_MAX_COUNT){ + PmsIntervene.IsShow = 0; + MainMenu.Hide(); + EventShow.Hide(); + PageIdle.Hide(); + GuiState = guiStateRemote; + SlaveDoRemoteReg(); + } + } +} + +void SlaveRemoteRegDoneResetCallBack() +{ + MainMenu.Hide(); + EventShow.MakeFastCheck(); + EventShow.MakeShow(); + if( EventShow.IsShowing ){ + GuiState = guiShowEvent; + PageIdle.Hide(); + EventShow.MakeShow(); + }else{ + GuiState = guiIdle; + EventShow.Hide(); + PageIdle.Show(); + } +} + +void Service_InterLink(void) +{ + +} + +void Service(void) +{ + //CtlCenter.TaskFreeRun(); + ProcessInnerCanRxMsg(); + ProtoC2C.iBufProcess(); + + Service_InterLink(); + EventShow.ShowTask(); + + FecStd.OperationTask(); + Config.OperationTask(); + + MqttData.OperationTask(); +} + +void Debug_data_init(void) +{ + unsigned int i,m; + MainCtl.fData.Split.PortCount = 3; + MainCtl.fData.Split.ExistTablePort[0] = 0xA5; + MainCtl.fData.Split.ExistTablePort[1] = 0xA5; + MainCtl.fData.Split.ExistTablePort[2] = 0xA5; + + Port[0].fData.Port.ResistedCount = 32; + Port[0].fData.Port.OnlineCount = 32; + Port[0].fData.Port.dType = dgTYPE_PORT; + Port[0].fData.Port.Id = 1; + + Port[1].fData.Port.ResistedCount = 32; + Port[1].fData.Port.OnlineCount = 32; + Port[1].fData.Port.dType = dgTYPE_PORT; + Port[1].fData.Port.Id = 2; + + Port[2].fData.Port.ResistedCount = 32; + Port[2].fData.Port.OnlineCount = 32; + Port[2].fData.Port.dType = dgTYPE_PORT; + Port[2].fData.Port.Id = 3; + + for(i=0; i<32; i++){ + Port[0].ExistTable[i] = 0xA5; + m = i%3; + if(m == 0){ + //EpDev[0][i].fData.Split.dType = dgTYPE_SMOKE_DETECTOR; + Port[0].dTypeTable[i] = dgTYPE_SMOKE_DETECTOR; + }else + if(m == 1){ + //EpDev[0][i].fData.Split.dType = dgTYPE_TEMPE_DETECTOR; + Port[0].dTypeTable[i] = dgTYPE_TEMPE_DETECTOR; + }else + if(m == 2){ + //EpDev[0][i].fData.Split.dType = dgTYPE_DISPLAY_PAD; + Port[0].dTypeTable[i] = dgTYPE_DISPLAY_PAD; + } + //EpDev[0][i].fData.Split.Id = i+1; + //EpDev[0][i].fData.Split.Flag = dEpStateBitMask; + + Port[0].StateTable[i] |= dEpStateBitMask; + } + + for(i=0; i<32; i++){ + Port[1].ExistTable[i] = 0xA5; + m = i%3; + if(m == 0){ + //EpDev[1][i].fData.Split.dType = dgTYPE_SMOKE_DETECTOR; + Port[1].dTypeTable[i] = dgTYPE_SMOKE_DETECTOR; + }else + if(m == 1){ + //EpDev[1][i].fData.Split.dType = dgTYPE_TEMPE_DETECTOR; + Port[1].dTypeTable[i] = dgTYPE_TEMPE_DETECTOR; + }else + if(m == 2){ + //EpDev[1][i].fData.Split.dType = dgTYPE_DISPLAY_PAD; + Port[1].dTypeTable[i] = dgTYPE_DISPLAY_PAD; + } + //EpDev[1][i].fData.Split.Id = i+1; + //EpDev[1][i].fData.Split.Flag = dEpStateBitMask; + + Port[1].StateTable[i] |= dEpStateBitMask; + } + + + for(i=0; i<9; i++){ + Port[2].ExistTable[i] = 0xA5; + Port[2].dTypeTable[i] = dgTYPE_SMOKE_DETECTOR; + //EpDev[2][i].fData.Split.dType = dgTYPE_SMOKE_DETECTOR; + //EpDev[2][i].fData.Split.Id = i+1; + } + for(i=11; i<12; i++){ + Port[2].ExistTable[i] = 0xA5; + Port[2].dTypeTable[i] = dgTYPE_SMOKE_DETECTOR; + //EpDev[2][i].fData.Split.dType = dgTYPE_SMOKE_DETECTOR; + //EpDev[2][i].fData.Split.Id = i+1; + } + for(i=16; i<19; i++){ + Port[2].ExistTable[i] = 0xA5; + Port[2].dTypeTable[i] = dgTYPE_TEMPE_DETECTOR; + //EpDev[2][i].fData.Split.dType = dgTYPE_TEMPE_DETECTOR; + //EpDev[2][i].fData.Split.Id = i+1; + } + for(i=24; i<32; i++){ + Port[2].ExistTable[i] = 0xA5; + Port[2].dTypeTable[i] = dgTYPE_DISPLAY_PAD; + //EpDev[2][i].fData.Split.dType = dgTYPE_DISPLAY_PAD; + //EpDev[2][i].fData.Split.Id = i+1; + } + + MainCtl.fData.Split.NetworkMode = 1; + MainCtl.fData.Split.MyNum = 2; + + MainCtl.fData.Split.HandCtlCount = 4; + MainCtl.fData.Split.ExistTableHandCtl[0] = 0xA5; + MainCtl.fData.Split.ExistTableHandCtl[1] = 0xA5; + MainCtl.fData.Split.ExistTableHandCtl[2] = 0xA5; + MainCtl.fData.Split.ExistTableHandCtl[3] = 0xA5; + + HandCtlBoard[0].fData.HandCtl.ResistedCount = 128; + HandCtlBoard[1].fData.HandCtl.ResistedCount = 128; + HandCtlBoard[2].fData.HandCtl.ResistedCount = 128; + HandCtlBoard[3].fData.HandCtl.ResistedCount = 128; + + HandCtlBoard[0].fData.HandCtl.dType = dgTYPE_HAND_CTL; + HandCtlBoard[1].fData.HandCtl.dType = dgTYPE_HAND_CTL; + HandCtlBoard[2].fData.HandCtl.dType = dgTYPE_HAND_CTL; + HandCtlBoard[3].fData.HandCtl.dType = dgTYPE_HAND_CTL; + + HandCtlBoard[0].fData.HandCtl.Id = 41; + HandCtlBoard[1].fData.HandCtl.Id = 42; + HandCtlBoard[2].fData.HandCtl.Id = 43; + HandCtlBoard[3].fData.HandCtl.Id = 44; + + MainCtl.fData.Split.DirectCtlCount = 6; + MainCtl.fData.Split.ExistTableDirectCtl[0] = 0xA5; + MainCtl.fData.Split.ExistTableDirectCtl[1] = 0xA5; + MainCtl.fData.Split.ExistTableDirectCtl[2] = 0xA5; + MainCtl.fData.Split.ExistTableDirectCtl[3] = 0xA5; + MainCtl.fData.Split.ExistTableDirectCtl[4] = 0xA5; + MainCtl.fData.Split.ExistTableDirectCtl[5] = 0xA5; + + DirectCtlBoard[0].fData.DirectCtl.ResistedCount = 64; + DirectCtlBoard[1].fData.DirectCtl.ResistedCount = 64; + DirectCtlBoard[2].fData.DirectCtl.ResistedCount = 64; + DirectCtlBoard[3].fData.DirectCtl.ResistedCount = 64; + DirectCtlBoard[4].fData.DirectCtl.ResistedCount = 64; + DirectCtlBoard[5].fData.DirectCtl.ResistedCount = 64; + DirectCtlBoard[6].fData.DirectCtl.ResistedCount = 64; + DirectCtlBoard[7].fData.DirectCtl.ResistedCount = 64; + + DirectCtlBoard[0].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + DirectCtlBoard[1].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + DirectCtlBoard[2].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + DirectCtlBoard[3].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + DirectCtlBoard[4].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + DirectCtlBoard[5].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + DirectCtlBoard[6].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + DirectCtlBoard[7].fData.DirectCtl.dType = dgTYPE_DIRECT_CTL; + + DirectCtlBoard[0].fData.DirectCtl.Id = 49; + DirectCtlBoard[1].fData.DirectCtl.Id = 50; + DirectCtlBoard[2].fData.DirectCtl.Id = 51; + DirectCtlBoard[3].fData.DirectCtl.Id = 52; + DirectCtlBoard[4].fData.DirectCtl.Id = 53; + DirectCtlBoard[5].fData.DirectCtl.Id = 54; + DirectCtlBoard[6].fData.DirectCtl.Id = 55; + DirectCtlBoard[7].fData.DirectCtl.Id = 56; +} + +void CleanUpEvent(void) +{ + +} + +void ProcessInnerCanRxMsg() +{ + int i; + if(InnerCanRxBuf.WriteIndex > (dInnerCanRxBufMaxCount -1))InnerCanRxBuf.WriteIndex = 0; + if(InnerCanRxBuf.ReadIndex != InnerCanRxBuf.WriteIndex){ + InnerCanRxBuf.ReadIndex++; + if(InnerCanRxBuf.ReadIndex >= dInnerCanRxBufMaxCount)InnerCanRxBuf.ReadIndex = 0; + InnerCan.aRxMsg.Ide.BitF.Cmd = InnerCanRxBuf.Body[InnerCanRxBuf.ReadIndex].Ide.BitF.Cmd; + InnerCan.aRxMsg.Ide.BitF.sAddr = InnerCanRxBuf.Body[InnerCanRxBuf.ReadIndex].Ide.BitF.sAddr; + InnerCan.aRxMsg.Ide.BitF.dAddr = InnerCanRxBuf.Body[InnerCanRxBuf.ReadIndex].Ide.BitF.dAddr; + InnerCanRxBuf.Body[InnerCanRxBuf.ReadIndex].Ide.D32 = 0; + InnerCan.aRxMsg.Dlc = InnerCanRxBuf.Body[InnerCanRxBuf.ReadIndex].Len; + if(InnerCanRxBuf.Body[InnerCanRxBuf.ReadIndex].Len <9){ + for(i=0; i 601){ + Port[i].DelayTick[x] = 601; + }else + if(Port[i].DelayTick[x] >1){ + if(Port[i].DelayTick[x] == 2){ + if(Port[i].DelayToDoEventType[x] == 0){ + Port[i].InterLinkGoStartDev(MainCtl.fData.Split.MyNum, i+1, x+1, Port[i].dTypeTable[x]); + Port[i].DelayTick[x] =0; + }else{ + //Add Sim + Port[i].AddRemoveMsgDelayStartSimulate(1, i+1, x+1, Port[i].dTypeTable[x]); + Port[i].DelayTick[x] =0; + } + }else{ + Port[i].DelayTick[x]--; + } + } + } + } + for(i=0; i601){ + DirectCtlBoard[i].DelayTick[x] = 601; + }else + if(DirectCtlBoard[i].DelayTick[x] > 1){ + if(DirectCtlBoard[i].DelayTick[x] == 2){ + if(DirectCtlBoard[i].DelayToDoEventType[x] == 0){ + DirectCtlBoard[i].InterLinkGoStartNode(MainCtl.fData.Split.MyNum, i +dADDR_DIRECTPAD_START, x+1); + DirectCtlBoard[i].DelayTick[x] =0; + }else{ + //Add Sim + DirectCtlBoard[i].AddRemoveMsgDelayStartSimulate(1, i +dADDR_DIRECTPAD_START, x +1); + DirectCtlBoard[i].DelayTick[x] =0; + } + }else{ + DirectCtlBoard[i].DelayTick[x]--; + } + } + } + } +} + +void KeepInUiJustEnter() +{ + TipPopup.ClearTickOnEventOcc(); +} + +void KeepInUiOperating() +{ + SystemPermissionTick =0; + EventShow.KeyJab(); +} + +void SysDoRecover() +{ + if(LanguageEnCn==0){ + TextRender_string24(40, 160, clNearWhite, ContentColor, "1.清除注册配置 "); + TClearRegistedInf::sIList = &ItemList; + TClearRegistedInf:: sDoClear(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "2.清除联动配置 "); + TClearLinkageCfg::sIList = &ItemList; + TClearLinkageCfg:: sDoClear(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "3.清除注释及描述 "); + TClearDescp:: sDoClear(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "4.清除打印机设置 "); + TPrinterSet:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "5.清除密码 "); + TPasswdChange:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "6.锁屏设定 "); + TScreenSaveCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "7.清除语言设定 "); + TLanguageCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "8.清除工程设定 "); + TProjectSet:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "9.清除维保设定 "); + TMaintain:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "10.清除运行模式 "); + TRunModeCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "11.清除设计数量 "); + DesignPrmSet.Init(); DesignPrmSet.RecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "12.清除终端设备设定 "); + TDevProperty::sIList = &ItemList; + TDevProperty:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "13.清除终端设备屏蔽 "); + TDevMask::sIList = &ItemList; + TDevMask:: sRecoverSetDefault(); + (void)DevMask.ReadMaskFromFlash(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "14.清除总线盘设定 "); + TBusPadLnk::sIList = &ItemList; + TBusPadLnk:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "15.清除多线盘设定 "); + TDirectPadCfg::sIList = &ItemList; + TDirectPadCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "16.清除广播设定 "); + TBroadcastCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "17.清除FecBus设定 "); + TLnkFecBusCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "18.清除区域设置 "); + TAreaCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "19.清除网络设定 "); + TCanNetworkRegister:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "20.清除网络屏蔽 "); + TCanNetworkMask:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "21.清除CRT设定 "); + TGraphDevCfg:: sRecoverSetDefault(); + LoopCheck1S(); + + TextRender_string24(40, 160, clNearWhite, ContentColor, "22.清除已上传的区域机注释信息"); + TfNetworkReg::sRecoverSetDefaultNetworkDescp(); + LoopCheck1S(); + + TextRender_string24(40, 160, clNearWhite, ContentColor, "23.清除传输设定,蓝牙,Wifi等 "); + + + }else{ + TextRender_string24(40, 160, clNearWhite, ContentColor, "1.Clearing Registed Data "); + TClearRegistedInf::sIList = &ItemList; + TClearRegistedInf:: sDoClear(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "2.Clearing Linkage Expression "); + TClearLinkageCfg::sIList = &ItemList; + TClearLinkageCfg:: sDoClear(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "3.Clearing Description "); + TClearDescp:: sDoClear(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "4.Clearing Printer Config "); + TPrinterSet:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "5.Clearing Password "); + TPasswdChange:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "6.Clearing Screen Config "); + TScreenSaveCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "7.Clearing Language Config "); + TLanguageCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "8.Clearing Project Info "); + TProjectSet:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "9.Clearing Maintenance Config "); + TMaintain:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "10.Clearing Run Mode "); + TRunModeCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "11.Clearing Designed Numbers "); + DesignPrmSet.Init(); DesignPrmSet.RecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "12.Clearing EP-Device Setting "); + TDevProperty::sIList = &ItemList; + TDevProperty:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "13.Clearing Device Blocking "); + TDevMask::sIList = &ItemList; + TDevMask:: sRecoverSetDefault(); + (void)DevMask.ReadMaskFromFlash(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "14.Clearing Bus Pad Board Config "); + TBusPadLnk::sIList = &ItemList; + TBusPadLnk:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "15.Clearing Direct Pad Board Config"); + TDirectPadCfg::sIList = &ItemList; + TDirectPadCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "16.Clearing Broadcast Setting "); + TBroadcastCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "17.Clearing FecBus Setting "); + TLnkFecBusCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "18.Clearing Zone Config "); + TAreaCfg:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "19.Clearing Network Config "); + TCanNetworkRegister:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "20.Clearing Network Blocking "); + TCanNetworkMask:: sRecoverSetDefault(); + LoopCheck1S(); + TextRender_string24(40, 160, clNearWhite, ContentColor, "21.Clearing CRT Setting "); + TGraphDevCfg:: sRecoverSetDefault(); + LoopCheck1S(); + + TextRender_string24(40, 160, clNearWhite, ContentColor, "22.Clearing Regional Description "); + TfNetworkReg::sRecoverSetDefaultNetworkDescp(); + LoopCheck1S(); + + TextRender_string24(40, 160, clNearWhite, ContentColor, "23.Clearing Transmiting Setting "); + + } + + //Has Not imp 2025 0331 + TBlueTooth:: sRecoverSetDefault(); + LoopCheck1S(); + TWifiConn:: sRecoverSetDefault(); + LoopCheck1S(); + TTransmiteDev:: sRecoverSetDefault(); + LoopCheck1S(); + + InnerCan.SendCmdMaskRemoveAll(); + + if(LanguageEnCn==0){ + TextRender_string24(40, 160, clNearWhite, ContentColor, "即将重新启动 "); + }else{ + TextRender_string24(40, 160, clNearWhite, ContentColor, "Restart Now "); + } + while(1){ + LL_IWDG_ReloadCounter(IWDG1); + DelayMs(20); + if(InnerCan.CheckOutBufFastFinish())break; + } + UserRequestReset = 0x12345678; + volatile unsigned int Stt; + while(1){ + Stt++; + } +} + +void DebugAdd250Fault() +{ + TRecordCommon aIm; + + aIm.Splite.Year = DateTime.Date.Split.Year; + aIm.Splite.Month = DateTime.Date.Split.Month; + aIm.Splite.Day = DateTime.Date.Split.Day; + aIm.Splite.Hour = DateTime.Time.Split.Hour; + aIm.Splite.Minute = DateTime.Time.Split.Minute; + aIm.Splite.Second = DateTime.Time.Split.Second; + aIm.Splite.mType = CmdActiveDefaultSet[cmOtherErr][7]; + aIm.Splite.PCtlNum = MainCtl.fData.Split.MyNum ; //(0,aRxMsg.Data.D8[1]); + + for(int i=0; i<250; i++){ + aIm.Splite.P0 = 1; //Board Index + aIm.Splite.P1 = i+1; + aIm.Splite.P2 = 0; //Fault Type + aIm.Splite.Data0 = 1; //Fault Type + aIm.Splite.Data1 = 1;//Is Set=1 Recover=0 + + + aIm.Splite.dType = 68; + aIm.Splite.mType = 0; + + CtlCenter.iePushOneMsgFault(aIm); + } +} + +void RecallCrcFaultMsg() +{ + int i; + SysLoopTick = 0; + for(i=0;i